{"count": 2370, "total": 2370, "jobs": [{"title": "Lead Security firmware engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-29T06:10:00+00:00", "url": "https://global-external-amd.icims.com/jobs/94423/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. LEAD SECURITY FIRMWARE ENGINEER THE ROLE: AMD S3 security firmware team is a part of S3 Software team and works with the world’s leading companies for their customized products. As a Security firmware engineer, you will be responsible for designing, developing and validating embedded firmware that comply with security requirements. You will be working with global pre-silicon and post-silicon teams across Software development, SoC design/verification, emulation and validation teams. THE PERSON: We are seeking a lead engineer to join our team that will thrive in a fast-paced work environment, using effective communication, problem-solving and prioritization skills. Individuals that are well organized, show great attention to detail, employ critical thinking and can drive sophisticated issues to closure are well-suited for our team. KEY RESPONSIBILITIES: Design and implement embedded firmware encompassing secure boot, trusted operating systems, trusted applications, enabling a wide range of security features Develop new firmware features and enhancements within pre & post silicon environments Triage, analyze, debug and fix sophisticated issues and drive the resolution to closure. Develops and execute test plans to evaluate functionality, security, and efficiency of firmware utilizing emulation and evaluation boards for pre-silicon and post silicon testing. Plan, track and deliver all firmware deliverables. Work closely with needed key stakeholders for efficient feature implementation and issue resolution and be responsible for the commitments. Scope and perform quick feasibility study of new asks and technologies. Able to mentor and guide the team members. PREFERRED EXPERIENCE: Minimum 8+ years’ experience in hands on firmware development on ARM or similar architectures. Strong with C and assembly language programming Experience with bootloader development, secure boot, IP initialization and low-level firmware development. Experience with bare metal and RTOS based firmware development. Proficient in debugging embedded firmware using debug tools. Solid understanding of security concepts such as Root of Trust, symmetric and asymmetric cryptography, etc., Hands on with one or more peripherals/controllers like UART, I2C, SPI, QSPI etc. Must have working knowledge on Git/Gerrit Experience in semiconductor domain preferred. Exposure to FTPM, Content Protection, HDCP, PlayReady is a plus. Experience in driver development is a plus Strong leadership and communication skills Quick learning and self-motivated. Good written and verbal communication skills in English ACADEMIC CREDENTIALS: Bachelor’s or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent LOCATION: Bangalore, IN #LI-PK2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "GPU Logic Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-29", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/GPU-Logic-Design-Engineer_JR0288631", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nAs a DFT Design Engineer, you will play a crucial role in developing and delivering high-quality design-for-test (DFT) solutions for cutting-edge semiconductor products. You will focus on logic design, RTL coding, and simulation, while collaborating on architecture and microarchitecture definitions. Your contributions directly impact product quality and manufacturability by optimizing test coverage, debug efficiency, and production ramp-up, ensuring Intel's leadership in advanced SoC designs.\n\nBusiness group\nThe Data Center Group (DCG) drives innovation in data center technologies to empower businesses and industries globally. As part of this high-impact organization, you will contribute to the development of world-class systems and solutions that support Intel's vision to transform data into actionable insights, enabling scalable, efficient, and secure computing.\n\nKey Responsibilities\n- Develop logic design, RTL coding, and DFT timing closure support for test content generation, including SCAN, MBIST, and BSCAN.\n- Collaborate on the definition of architecture and microarchitecture features for blocks and subsystems under DFT design.\n- Create and optimize HVM content for rapid bring-up and production ramp on automatic test equipment (ATE).\n- Apply strategies, tools, and methods to integrate DFT into RTL and structural code while meeting power, performance, area, and timing goals.\n- Review verification plans and drive verification of DFT designs to ensure alignment with architecture and microarchitecture specifications.\n- Resolve RTL test failures and implement corrective measures to ensure design accuracy and feature correctness.\n- Integrate DFT blocks into functional IP and SoC, supporting SoC customers to ensure seamless integration and high-quality design outcomes.\n- Collaborate with post-silicon and manufacturing teams to support debug and verification on silicon, documenting learnings for continuous improvement.\n- Drive high test coverage and develop structural and specific IP tests to achieve quality and defect-per-million (DPM) objectives.\n\nQualifications:\nMinimum Qualifications\n- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 0-1 years of hands-on experience through internships, academic projects, coursework, or training.\n- OR a Master's degree in Electrical Engineering, Computer Engineering, or related field with no prior professional experience.\n- Proficiency in RTL coding and simulation tools (e.g., SystemVerilog, VCS).\n- Foundational understanding of DFT methodologies such as SCAN, MBIST, and BSCAN.\n\nPreferred Qualifications\n- Strong problem-solving skills and a collaborative mindset.\n- Familiarity with SoC architecture and microarchitecture features.\n- Knowledge of test equipment tools and strategies for production ramp-up.\n- Passion for innovation and commitment to delivering high-quality solutions.\n\nJoin us in shaping the future of semiconductor technology. Your contributions will drive the scalability and reliability of Intel's products, while fostering personal growth and career development in an inspiring environment.\n          \n\nJob Type:\nCollege Grad\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.Legal Disclaimer:\nIt has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews.   We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.\n\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Integration Design Engineer", "company": "Lattice", "location": "Manila, Philippines", "date_posted": "2026-10-29", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Manila-Philippines/Integration-Design-Engineer_R-103499", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nJob Summary: \n \nThe position is for Integration Design Engineer at Lattice Semiconductor (PH) Corp. The design engineer will be part of the Silicon Integration Team and will mainly be responsible for the integration of different IPs to build the chip utilizing both custom and digital design flows.\n\nAccountabilities: \nDesign engineer will generally be responsible for the integration of different IPs to build the fullchip. This extends to the delivery of all the corresponding models, views and collaterals to different functional teams and the completion of all the required checks and simulations for sign-off.\nCollaborate with Architecture, SW, IP Design, and Physical Design Teams to generate fullchip logical floorplan. Generate fullchip behavioral model by integrating the various IP models in alignment to the logical floorplan and the requirements of SW and Verification teams. Responsibility extends to the delivery of fullchip synthesized netlist and fullchip schematics.\nDesign and implement (custom and digital) density-specific IPs (such as clock networks) and sectors (group of IPs) suitable for fullchip integration. Perform all flows and checks such as elaboration/compilation, synthesis, equivalence, DFT, timing closure (spice simulation and/or STA), power and performance analysis.\nWork closely with other functional teams to debug and resolve issues\nPerform fullchip tapeout-gating audits such as Electromigration and IR drop (EMIR) Analysis, Netlist Electrical Rule Checks (NetERC), Power Distribution Network (PDN) Extraction, Simultaneously Switching Outputs (SSO) simulations, and ESD checks.\n \nRequired Skills:\nBS or MS in Electronics/Computer/Electrical Engineering\nAt least 5 years of proven in-depth experience in Custom and Digital Design Implementation. Expertise in Verilog and System Verilog is a must.\nExperience in FPGA/CPLD design and integration is a plus.\nSolid understanding of the following:Custom Design FlowSemiconductor principles and transistor-level analysis\nIndustry standard tools for schematic and layout Entry (Cadence Virtuoso)\nCharacterization, performance, and power simulations (spice is preferred)\n\nDigital Design FlowRTL coding and verification\nLint Check, Elaboration/Compilation, Synthesis, Equivalence Check, SDC, and STA using industry standard tools (Xcelium, Genus, Innovus, Tempus)\nKnowledge in DFT flow and ATPG generation is an advantage.\nundefined\nExperience in IP and Fullchip functional verification is a plus.\nundefined\nExperience in coding/scripting (Perl, TCL, Shell, Skill, Phyton)\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nPhilippinesLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Firmware Engineer II", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-10-29", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Firmware-Engineer-II_R55520", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Description\nDesign Engineer II\n\nThis is an opportunity to join a dynamic and growing team of experienced engineers developing physical layer IP’s for industry-standard high-speed serial-link protocols. The successful candidate will ideally be a highly motivated self-starter who can work independently to complete assigned tasks and collaborate with other members to achieve project milestones. It is expected that the candidate will contribute during all phases of firmware development for high speed SERDES - from architecture development to implementation, verification, testing and customer deployment. \n\nResponsibilities\nWork closely with PHY digital and mixed signal architects to figure out the details of FW functions and sequences. Contribute during firmware architecture development and implementation of the defined firmware features.\nHelp to build system level prototype control software to develop/validate adaptation, equalization, and control algorithms for high speed SERDES.\nImplement assigned FW features and work closely with verification[simulation] and validation team to ensure the functionality and robustness of the implemented features.\nSupport FuSa compliant firmware development. Work closely with verification and validation team to develop and execute test plans for FuSa compliant firmware.\nSupport of Validation team during electrical and system characterization during post-silicon testing. Identify any FW and HW related functionality and performance issues and implement any necessary FW improvements to address these issues.\nSupport Product Engineering, System Validation and Design team to debug IP issues during customer deployment of the IP and provide hot fixes.\nCreate and maintain comprehensive documentation related to firmware design, development, bug fixes and compliance testing.\n\nDesired Skills\nB.Tech with 4yrs  or M.Tech with 2 yrs in Electrical/Electronics Engineering\nSolid programming knowledge in C/C++ and Python\nStrong problem-solving and communication skills\nUnderstanding of wireline communication principles and digital signal processing techniques is a plus\nKnowledge in mixed signal circuit design is a plus\nExperience with silicon validation process and debug is a plus\nExperience with digital verification environment and tools is a plus\nUnderstanding of FuSa compliance is a plus\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Firm ware Engineer II", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-10-29", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Firm-ware-Engineer-II_R55519", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Description\nDesign Engineer II\n\nThis is an opportunity to join a dynamic and growing team of experienced engineers developing physical layer IP’s for industry-standard high-speed serial-link protocols. The successful candidate will ideally be a highly motivated self-starter who can work independently to complete assigned tasks and collaborate with other members to achieve project milestones. It is expected that the candidate will contribute during all phases of firmware development for high speed SERDES - from architecture development to implementation, verification, testing and customer deployment. \n\nResponsibilities\nWork closely with PHY digital and mixed signal architects to figure out the details of FW functions and sequences. Contribute during firmware architecture development and implementation of the defined firmware features.\nHelp to build system level prototype control software to develop/validate adaptation, equalization, and control algorithms for high speed SERDES.\nImplement assigned FW features and work closely with verification[simulation] and validation team to ensure the functionality and robustness of the implemented features.\nSupport FuSa compliant firmware development. Work closely with verification and validation team to develop and execute test plans for FuSa compliant firmware.\nSupport of Validation team during electrical and system characterization during post-silicon testing. Identify any FW and HW related functionality and performance issues and implement any necessary FW improvements to address these issues.\nSupport Product Engineering, System Validation and Design team to debug IP issues during customer deployment of the IP and provide hot fixes.\nCreate and maintain comprehensive documentation related to firmware design, development, bug fixes and compliance testing.\n\nDesired Skills\nB.Tech with 4yrs  or M.Tech with 2 yrs in Electrical/Electronics Engineering\nSolid programming knowledge in C/C++ and Python\nStrong problem-solving and communication skills\nUnderstanding of wireline communication principles and digital signal processing techniques is a plus\nKnowledge in mixed signal circuit design is a plus\nExperience with silicon validation process and debug is a plus\nExperience with digital verification environment and tools is a plus\nUnderstanding of FuSa compliance is a plus\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Design Engineer II", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-10-29", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Firmware-Engineer_R53370", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nDesign Engineer II\n\nThis is an opportunity to join a dynamic and growing team of experienced engineers developing physical layer IP’s for industry-standard high-speed serial-link protocols. The successful candidate will ideally be a highly motivated self-starter who can work independently to complete assigned tasks and collaborate with other members to achieve project milestones. It is expected that the candidate will contribute during all phases of firmware development for high speed SERDES - from architecture development to implementation, verification, testing and customer deployment. \n\nResponsibilities\nWork closely with PHY digital and mixed signal architects to figure out the details of FW functions and sequences. Contribute during firmware architecture development and implementation of the defined firmware features.\nHelp to build system level prototype control software to develop/validate adaptation, equalization, and control algorithms for high speed SERDES.\nImplement assigned FW features and work closely with verification[simulation] and validation team to ensure the functionality and robustness of the implemented features.\nSupport FuSa compliant firmware development. Work closely with verification and validation team to develop and execute test plans for FuSa compliant firmware.\nSupport of Validation team during electrical and system characterization during post-silicon testing. Identify any FW and HW related functionality and performance issues and implement any necessary FW improvements to address these issues.\nSupport Product Engineering, System Validation and Design team to debug IP issues during customer deployment of the IP and provide hot fixes.\nCreate and maintain comprehensive documentation related to firmware design, development, bug fixes and compliance testing.\n\nDesired Skills\nB.Tech with 6yrs  or M.Tech with 4 yrs in Electrical/Electronics Engineering\nSolid programming knowledge in C/C++ and Python\nStrong problem-solving and communication skills\nUnderstanding of wireline communication principles and digital signal processing techniques is a plus\nKnowledge in mixed signal circuit design is a plus\nExperience with silicon validation process and debug is a plus\nExperience with digital verification environment and tools is a plus\nUnderstanding of FuSa compliance is a plus\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Staff CAD Engineer (Power Signal Integrity)", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-10-29", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Staff-CAD-Engineer--Power-Signal-Integrity-_2605101", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nYou will be part of Marvell's Central CAD and Design Services (CCDS) organization — the engine that powers every business unit at Marvell. Our team develops and maintains world-class design flows and infrastructure that enable Marvell's semiconductor products across Data Center, Networking, Automotive, and Storage markets.\n\nAbout PSI CAD team:  CCDS CAD PSI team is responsible for driving Power Signal Integrity signoff methodology across Marvell's worldwide business units. The team develops and maintains PSI flows within M1DP, supports design teams through tapeout, and collaborates with EDA vendors to continuously improve tool capabilities and methodology. The team operates with a \"One Marvell\" mindset\nWhat You Can Expect\nWork on block-level and full-chip static IR/EM analysis flow and methodology\n\nWork on dynamic IR analysis methodology (vectorless and vector-based using VCD/FSDB) at block and full-chip levels, with and without package models\n\nInvolved and tuning flows for Out-of-Context (OOC) and In-Context block-level IR analysis\n\nWork on Left Shifted IR Analysis like Early Rail Analysis (ERA) to detect power grid weaknesses at floorplan stage\n\nInterface with EDA vendors to evaluate new tool features, report bugs, and drive tool improvements.\n\nDevelop automation scripts (Tcl, Python) to streamline IR/EM flow execution, debug, and reporting.\n\nSupport tapeout activities by ensuring IR/EM signoff closure across blocks and full-chip designs.\n\nContribute to knowledge sharing, documentation, and training of IR?EM CAD flows across global teams.\n\nWhat We're Looking For\nB.E./B.Tech or M.E./M.Tech in Electrical Engineering, Electronics Engineering, Computer Science, or a related field.\n5+ years of hands-on experience with Cadence Voltus for IR drop and EM analysis in production ASIC/SoC flows\nProven track record of running block-level and full-chip PSI signoff on advanced technology nodes (7nm, 5nm, or 3nm)\nSolid understanding of static/dynamic power and IR Analysis flow & Methodology (including hierarchical)\nGood understanding of DC & AC-EM analysis and its impact\nUnderstanding of package aware IR simulation and chip power model generation flows\nUnderstanding of thermal flows is a plus\nUnderstanding of multi-die IR/EM analysis is a plus\n\nThis role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.\nAdditional Compensation and Benefit Elements\nWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\n\nInterview Integrity \nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\n\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\n\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n\n#LI-CP1", "jd_status": "stored"}, {"title": "Staff Engineer product Engineering", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-10-28T11:19:05+00:00", "url": "https://jobs.infineon.com/careers/job/563808972287162", "is_hardware": true, "platform": "eightfold", "jd_text": "Are you passionate about RF and Analog Mixed-Signal technologies and eager to solve complex manufacturing challenges? Join our Product Engineering team to drive product characterization, yield enhancement, failure analysis, and manufacturing optimization for next-generation IoT products. This role offers the opportunity to work across product development, qualification, and high-volume manufacturing while leading initiatives that directly impact product quality, cost, and customer satisfaction.\n\nYour role\nKey responsibilities in your new role\n\nInvestigate and resolve production failures using advanced laboratory tools and bench equipment to improve yield and product quality.\n\nDrive manufacturing cost-reduction initiatives through test time optimization, yield improvement, fab site qualification, and manufacturing transfer projects.\nPerform comprehensive customer return and failure analysis, delivering detailed reports and corrective action recommendations.\nSupport new sales opportunities by bringing up and qualifying product derivatives from existing product portfolios.\nDevelop and implement test program enhancements to improve product performance, quality, and manufacturing efficiency.\nExecute product characterization plans and analyze silicon performance data to ensure compliance with product specifications.\nDrive reliability qualification activities and perform ATE-to-bench correlation for product validation.\nLead root-cause investigations using statistical analysis and data-driven methodologies.\nCollaborate with cross-functional teams including Design, Test, Quality, Reliability, and Manufacturing Engineering to achieve business objectives.\nInfluence stakeholders and provide technical leadership to resolve complex product and manufacturing challenges.\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor's or Master's degree in Electronics Engineering or a related field.\n\n5-8 years of experience in Product Engineering, Test Engineering, Semiconductor Manufacturing, or a related discipline.\nStrong understanding of RF and Analog Mixed-Signal architectures, circuit operation, and performance characterization.\nHands-on experience in semiconductor device characterization, reliability qualification, ATE-to-bench correlation, and electrical failure analysis.\nProven expertise in data analysis, root-cause investigation, statistical methods, and yield improvement techniques.\nStrong problem-solving skills with a demonstrated ability to deliver impactful technical solutions and manufacturing improvements.\nExperience working with laboratory and characterization equipment in semiconductor environments.\nSelf-driven individual with the ability to independently manage priorities and drive initiatives to completion.\nExcellent analytical, troubleshooting, communication, and stakeholder management skills.\nAbility to thrive in a fast-paced manufacturing environment while effectively collaborating across global and cross-functional teams.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\n\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nKeerthini M H", "jd_status": "stored"}, {"title": "Staff Engineer product Engineering", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-10-28T11:15:45+00:00", "url": "https://jobs.infineon.com/careers/job/563808972287163", "is_hardware": true, "platform": "eightfold", "jd_text": "Are you passionate about RF and Analog Mixed-Signal technologies and eager to solve complex manufacturing challenges? Join our Product Engineering team to drive product characterization, yield enhancement, failure analysis, and manufacturing optimization for next-generation IoT products. This role offers the opportunity to work across product development, qualification, and high-volume manufacturing while leading initiatives that directly impact product quality, cost, and customer satisfaction.\n\nYour role\nKey responsibilities in your new role\n\nInvestigate and resolve production failures using advanced laboratory tools and bench equipment to improve yield and product quality.\n\nDrive manufacturing cost-reduction initiatives through test time optimization, yield improvement, fab site qualification, and manufacturing transfer projects.\nPerform comprehensive customer return and failure analysis, delivering detailed reports and corrective action recommendations.\nSupport new sales opportunities by bringing up and qualifying product derivatives from existing product portfolios.\nDevelop and implement test program enhancements to improve product performance, quality, and manufacturing efficiency.\nExecute product characterization plans and analyze silicon performance data to ensure compliance with product specifications.\nDrive reliability qualification activities and perform ATE-to-bench correlation for product validation.\nLead root-cause investigations using statistical analysis and data-driven methodologies.\nCollaborate with cross-functional teams including Design, Test, Quality, Reliability, and Manufacturing Engineering to achieve business objectives.\nInfluence stakeholders and provide technical leadership to resolve complex product and manufacturing challenges.\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor's or Master's degree in Electronics Engineering or a related field.\n\n5-8 years of experience in Product Engineering, Test Engineering, Semiconductor Manufacturing, or a related discipline.\nStrong understanding of RF and Analog Mixed-Signal architectures, circuit operation, and performance characterization.\nHands-on experience in semiconductor device characterization, reliability qualification, ATE-to-bench correlation, and electrical failure analysis.\nProven expertise in data analysis, root-cause investigation, statistical methods, and yield improvement techniques.\nStrong problem-solving skills with a demonstrated ability to deliver impactful technical solutions and manufacturing improvements.\nExperience working with laboratory and characterization equipment in semiconductor environments.\nSelf-driven individual with the ability to independently manage priorities and drive initiatives to completion.\nExcellent analytical, troubleshooting, communication, and stakeholder management skills.\nAbility to thrive in a fast-paced manufacturing environment while effectively collaborating across global and cross-functional teams.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\n\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nKeerthini M H", "jd_status": "stored"}, {"title": "Manager - Test Engineering", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-10-28T11:05:21+00:00", "url": "https://jobs.infineon.com/careers/job/563808972287703", "is_hardware": true, "platform": "eightfold", "jd_text": "Passionate about ATE Test Development, RF Validation, and Product Engineering? Join our team to drive end-to-end test solutions for cutting-edge IoT products, including Bluetooth and Wi-Fi devices. Work closely with design, DFT, applications, and manufacturing teams to deliver high-quality semiconductor products while leading innovation in test engineering and manufacturing excellence.\n\nYour role\nKey responsibilities in your new role\n\nDevelop and optimize ATE test solutions for Digital, Analog, and RF products.\n\nCreate new test programs and enhance existing manufacturing test solutions to improve quality, yield, and efficiency.\nTroubleshoot and resolve customer application issues, manage RMAs, and drive timely closure of customer concerns.\nProvide technical expertise in Bluetooth and Wi-Fi product testing and validation for IoT solutions.\nDrive device and package qualification activities, including FAB/backend transfers and new product introductions.\nExecute Design of Experiments (DOE) and Statistical Process Control (SPC) methodologies to improve product performance and manufacturing robustness.\nCollaborate with cross-functional teams including Design, DFT, Applications, Product Engineering, and Test Engineering across global development sites.\nSupport silicon bring-up, characterization, failure analysis, and yield improvement initiatives.\nMentor junior engineers and provide technical leadership in test development and manufacturing optimization projects.\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor's or Master's degree in Electronics, Electrical Engineering, Computer Science, or related disciplines.\n\n8+ years of experience in ATE test solution development within the semiconductor industry.\nHands-on experience with Teradyne UltraFlex/UltraFlex Plus and/or Advantest V93K test platforms.\nStrong expertise in Digital, Analog, and RF product test development.\nProficiency in programming languages such as C, C++, Java, VB, and automation scripting using Python, Perl, or MATLAB.\nWorking knowledge of Teradyne IGXL (v9/v10+) and Advantest SmarTest 8.\nExperience with lab equipment including oscilloscopes, logic analyzers, signal generators, power supplies, and source-measure units.\nStrong understanding of DFT, circuit testing, process integration, DOE, and SPC methodologies.\nExcellent project management, problem-solving, communication, and stakeholder management skills.\nProven ability to lead technical initiatives, drive manufacturing improvements, and work effectively in a dynamic cross-functional environment.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\n\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nKeerthini M H", "jd_status": "stored"}, {"title": "Staff Engineer Design", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-10-28T09:27:23+00:00", "url": "https://jobs.infineon.com/careers/job/563808972052757", "is_hardware": true, "platform": "eightfold", "jd_text": "Develop and implement innovative digital design flows, focusing on the synthesis, LEC and CLP runs and\n     physical design aspects.\n\nTranslate high-level design requirements into detailed\n     flow specifications, utilizing\n     state-of-the-art EDA tools and flows to ensure efficient timing closure,\n     and physical sign-off  \n\nWork independently across various phases of the RTL2GDS\n     flow, with a focus on synthesis,\n     equivalence checking, and physical implementation, to ensure highly\n     automated, safe, stable, easy-to-use, customizable and effective digital\n     design flows \n\nParticipate in an expert network to drive innovation,\n     methodology, and flow topics in SoC synthesis, UPF, physical design and\n     top-level timing closure,\n     contributing to the development of next-generation SoC designs \n\nYour role\nKey responsibilities in your new role\n\nDevelop and implement innovative digital design flows, focusing on the synthesis, LEC and CLP runs and\n     physical design aspects.\n\nTranslate high-level design requirements into detailed\n     flow specifications, utilizing\n     state-of-the-art EDA tools and flows to ensure efficient timing closure,\n     and physical sign-off  \n\nWork independently across various phases of the RTL2GDS\n     flow, with a focus on synthesis,\n     equivalence checking, and physical implementation, to ensure highly\n     automated, safe, stable, easy-to-use, customizable and effective digital\n     design flows \n\nParticipate in an expert network to drive innovation,\n     methodology, and flow topics in SoC synthesis, UPF, physical design and\n     top-level timing closure,\n     contributing to the development of next-generation SoC designs \n\nYour profile\nQualifications and skills to help you succeed \n\nA degree in Electrical Engineering,\n     Microelectronics, or a similar field \n\nAt least 5-8 years of working experience in Synthesis\n     and Physical Design handling\n     highly complex SoCs, with sound experience in Synthesis, LEC and\n     UPF/CLP Timing Closure.\n\nVery good knowledge in Synopsys and Cadence Toolset in the RTL2GDS domain \n\nProven track record in\n     developing digital design methodologies \n\nKnow-how in technical leadership in physical design projects  \n\nSound programming skills and knowledge\n     in scripting languages like Tcl or Python \n\nBasic experience in RTL coding\n\nUnderstanding of Functional Safety and Agile\n     Development Methods like Kanban Scrum XP. Test Driven\n     Development knowledge would be an advantage\n\nExcellent written and spoken English \n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nVidhi Thakkar", "jd_status": "stored"}, {"title": "Principal Engineer, SoC Architect", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-28T09:13:36.094000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000158237480-principal-engineer-soc-architect", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "About Renesas India (India for India – IFI)\nRenesas continues to significantly expand its presence in India, with headcount approaching 1,000 and strong engagement across government, academia, and the broader semiconductor ecosystem. As India emerges as a strategic semiconductor market and a global talent hub, Renesas’ India for India (IFI) initiative is focused on creating differentiated products that address local market needs, while remaining globally competitive.\nThis role represents a rare opportunity to shape future silicon platforms from India—directly influencing product architecture, execution methodologies, and portfolio direction for a fast‑growing, strategically important market. The individual will play a pivotal role in defining end‑to‑end SoC solutions that serve India’s unique applications across automotive, industrial, infrastructure, and emerging domains.\nKey Responsibilities\nProduct & Portfolio Architecture\nWork closely with Business, Product Management, Sales, and Customers to define product portfolio strategy and translate market needs into clear SoC/MCU requirements.\nArchitect scalable SoC/MCU platforms, including detailed technical specifications and cost–benefit trade‑offs across architecture options, process nodes, IP reuse, and integration strategies.\nDefine–Own–Deliver SoC implementations that meet product KPIs, quality, cost, and schedule targets.\nEnsure end‑to‑end specification compliance across verification, validation, characterization, and production test, with rigorous review of outcomes prior to release.\nDrive paradigm shifts in SoC/MCU execution—covering team structures, tools, design methodologies, and processes—to enable high‑quality, first‑pass silicon.\nLead IP selection strategies, including make/buy decisions, third‑party IP evaluation, and long‑term platform reuse.\nCollaborate deeply with RTL design, Design Verification, Firmware/Software, Pre‑ and Post‑Silicon Validation, Test, and Program Management teams.\nEnable delivery of first‑pass functional silicon on aggressive and aspirational schedules through architectural rigor and execution discipline.\nEngage with external stakeholders, including IP vendors, EDA partners, foundries, and OSATs.\nRepresent Renesas at technical conferences, standards bodies, and ecosystem forums, contributing to thought leadership and technology direction.\nContribute to training program definition and rollout, mentor senior engineers, and drive systematic lessons‑learned and best‑practice sharing across teams and programs.\n\nQualifications & Experience\nStrong can‑do attitude, adaptability, and openness to diverse people, cultures, and working environments.\nEducational background in Electrical Engineering, Electronics Engineering, Computer Engineering, or Computer Science.\nHands‑on experience across key portions of the SoC development lifecycle, including:Front‑end architecture and RTL design\nVerification\nRTL‑to‑GDSII flow\nEmbedded software and system‑level integration\n\nBroad technical exposure across multiple domains such as Automotive, Multimedia, Networking, Compute, Computer Vision, and Software‑defined systems.\nProven ability to influence and coordinate across highly experienced, globally distributed cross‑functional teams.\nExcellent communication, problem‑solving, and technical leadership skills with a strong focus on quality and execution.\nM.Tech / B.Tech in Electrical Engineering or Computer Science with 12+ years of experience in SoC/MCU architecture and RTL design, including leadership across the full NPI lifecycle.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Principal Validation Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-28T06:32:25.227000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000158212489-principal-validation-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Renesas is looking for a Principal SoC Validation Engineer, to redefine how SoCs are built and validated—driving first‑time‑right silicon, eliminating customer escapes, and setting a new industry benchmark for validation excellence \n \n\nKey Responsibilities \nDefine and own the end‑to‑end silicon validation strategy for automotive and Embedded SoCs, from pre‑silicon enablement through post‑silicon production release. \nEnsure first‑time‑right silicon, robust validation coverage, and zero customer escapes across all assigned programs. \nLead global validation teams responsible for silicon bring‑up, characterization, and system‑level validation across multiple concurrent programs. \nEstablish and drive a System Use Case Validation Program, harvesting real customer/OEM and system scenarios and converting them into automated, traceable validation suites. \nInfluence SoC architecture, design, and program decisions through early validation insights, risk identification, and data‑backed recommendations. \nDrive shift‑left validation as a measurable engineering program, increasing reuse across simulation, emulation/FPGA, and silicon to reduce late surprises. \nOwn escape‑prevention strategy, including robustness testing, fault scenarios, coverage models, and disciplined validation signoff criteria. \nBuild and scale high‑performing validation organizations, developing strong technical leadership (Staff/Principal pipeline) and execution ownership. \nLead automation, standardization, and infrastructure modernization across validation labs, board farms, and CI systems. \nEstablish validation methodologies, quality benchmarks, metrics, and dashboards aligned with Renesas standards and automotive expectations. \nIdentify technical, execution, and program risks early; drive data‑driven mitigation and executive decision‑making. \nProvide clear executive‑level reporting on validation status, risks, readiness, and outcomes. \nAct as a trusted partner to Design, DV, Test, Firmware, Software, Product Engineering, Quality, and BU leadership. \nAdoption of industry best practices as a measurable program \n\nRequired Skills & Experience \nB.E./B. Tech or M.E./M. Tech in Electronics, Electrical, or Computer Engineering, or equivalent industry experience. \n15+ years of experience in semiconductor validation, characterization, or silicon engineering, with demonstrated ownership of silicon quality outcomes. \n3+ years in senior technical leadership roles \nStrong domain expertise in SoC validation, system‑level use‑case testing, and robustness validation. \nProven experience delivering complex SoC programs from first silicon through production release. \nDeep understanding of silicon validation flows, lab environments, and post‑silicon debug ecosystems. \nDemonstrated success building and scaling automation‑first validation frameworks using Python, C++, or similar technologies. \nStrong experience driving cross‑functional execution in a matrixed, global environment. \nExcellent executive communication, stakeholder management, and decision‑making skills. \nExperience with AI frameworks for SoC Validation efficiency and quality gain— eg validation specific AI agents, Cody AI for content development etc. \nPreferred \nExperience with ISO 26262 / ASIL‑B development and validation environments. \nExposure to emulation/FPGA‑based shift‑left validation and pre↔post silicon continuity models. \nStrong foundation in mixed‑signal and digital silicon validation, including pattern‑based and system‑level methodologies. \nTrack record of institutionalizing industry best practices across multiple programs and organizations. \nExperience leading culture change toward proactive risk ownership, evidence‑based closure, and challenge‑ready execution. \nAutomotive OEM or Tier‑1 customer engagement experience.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Staff / Principal Engineer, AMS Verification", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-28T06:19:10.093000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000158210549-senior-staff-principal-engineer-ams-verification", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking an AMS Verification Engineer to lead verification of the digital content embedded within power, analog, and mixed-signal IC products. This is a senior individual-contributor role requiring ownership of verification architecture, methodology, execution, and sign-off at block and full-chip level. \nThe successful candidate will build scalable verification environments from specifications, develop verification plans and coverage strategies, and verify control, protection, diagnostics, communication, trimming, test, and safety-related digital functions that interact closely with analog circuitry. \nYou will be expected to work autonomously, resolve ambiguous specification issues, establish verification flows from scratch where required, mentor engineers, and provide clear evidence that the design meets functional and product requirements before tape-out. \nResponsibilities  \nVerification Strategy & Ownership \nOwn block-level and full-chip digital verification strategy for power, analog, and mixed-signal IC products. \nDevelop verification plans from product and design specifications, including feature extraction, test intent, coverage goals, assumptions, and sign-off criteria. \nDecompose complex functions into reusable verification components and scalable environments. \nIdentify specification gaps and drive closure with architecture, analog design, digital design, applications, and test teams. \nEnvironment Development & Execution \nDesign and develop SystemVerilog/UVM-based testbenches, agents, scoreboards, reference models, assertions, sequences, and coverage models. \nSet up verification flows from scratch where needed and own regression execution, triage, debug, and closure. \nApply simulation, assertion-based verification, formal verification, and FPGA or emulation techniques where they provide practical value. \nVerify digital behavior across reset, clock, power-state, fault, trim, communication, test-mode, and analog-interaction scenarios. \nMixed-Signal, DFT & Post-layout Support \nCollaborate with analog and digital teams to define appropriate models and verify analog-digital interactions at the required abstraction level. \nSupport DFT verification, scan and ATPG-related checks, production-test vector development, and test-mode verification. \nSupport gate-level simulation, timing-aware verification, and post-layout verification where required. \nContribute to silicon bring-up, device evaluation, root-cause analysis, and documented workarounds for device errata. \nTechnical Leadership & Methodology \nDrive reusable verification methodology, automation, metrics, documentation, and review standards across projects. \nMentor and train verification engineers through reviews, debug support, and technical guidance. \nProvide concise status, coverage, risk, and sign-off assessments to project and technical leadership. \nInfluence architecture and design choices by identifying verification complexity, observability gaps, and product risks early. \n\nBachelor or Masters degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline. \n10+ years of experience in AMS verification, including substantial hands-on experience with SystemVerilog and UVM. \nProven ownership of block-level and full-chip verification environments and sign-off for complex semiconductor products. \nStrong knowledge of functional verification, assertion-based verification, formal verification, regression frameworks, coverage closure, and debug methodologies. \nExperience verifying digital logic embedded in PMICs, power-management, automotive, audio, or other mixed-signal integrated circuits. \nGood understanding of RTL, microarchitecture, clocks, resets, low-power states, register interfaces, and common serial interfaces such as SPI, I2C, or UART. \nWorking knowledge of synthesis, STA, DFT, scan insertion, ATPG, and gate-level verification to collaborate effectively across the development flow. \nExperience with scripting or automation using Python, TCL, Perl, shell, or similar languages. \nProven ability to mentor engineers, establish verification methodology, and lead technical reviews without requiring formal people-management authority. \nSelf-driven, results-oriented, and able to deliver under tight schedules in a multisite and multicultural environment. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "AI Performance Modeling Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-28T06:06:00+00:00", "url": "https://global-external-amd.icims.com/jobs/84934/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The Role We're building GPUs to run the most demanding AI in the world — Transformers, LLMs, and large vision models — and we need an experienced hands-on engineer who can tell us how fast those workloads will run before the silicon exists. This is an AI performance projection/modeling role: your job is to model AI workloads on our GPU architecture, predict their performance with confidence, and use those projections to shape the hardware we build. You'll work across the full modeling spectrum — analytical models for fast architectural what-ifs, and architectural and cycle-accurate simulators for precision — choosing the right level of fidelity for the question at hand. Because these workloads live on the GPU, you'll need real GPU architecture depth to do it. If you think in rooflines, arithmetic intensity, tensor/pipeline/data parallelism, and KV-cache bandwidth budgets — and you want your models to change the microarchitecture, not just describe it — this is the role. What You'll Do Project AI workload performance (your core mission) Build and use models — analytical, architectural, and cycle-accurate — to project the performance of generative AI and LLM workloads (attention, GEMMs, collectives, training and inference, vision models etc) on our GPU architecture. Choose the right fidelity for the question: analytical bounds and rooflines for rapid trade-off exploration, architectural and cycle-accurate simulation for precise answers. Find where performance will be won or lost — compute-engine occupancy, L1/L2 hierarchy, memory bandwidth, SoC fabric — and quantify the impact of each. Characterize workloads & shape the hardware Characterize AI workloads end to end — trace and profile execution, extract structural footprints, and translate them into microarchitectural bottlenecks and performance bounding boxes. Run architecture experiments to evaluate GPU configurations, scaling limits, and trade-offs against real AI workloads, backing every recommendation with sensitivity analysis and data. Extend and maintain the cycle-accurate / cycle-approximate simulators for the GPU subsystems AI workloads depend on — compute engines, cache hierarchies, memory subsystems, interconnects. Prove it on silicon (post-silicon) Run AI workloads on early silicon, capture telemetry, and correlate results back to your pre-silicon models to sharpen fidelity. Root-cause AI performance mismatches on physical silicon using low-level performance counters, register dumps, and Linux tracing. Collaborate across the stack Partner with compiler, runtime, and framework teams to turn model insights into optimizations, and to ground your projections in how workloads actually execute. Act as the bridge between architecture/RTL and software, translating AI workload requirements into concrete architectural constraints. What You'll Bring AI workload expertise: Deep, hands-on understanding of LLM and Transformer performance — scaling techniques, parallel training/inference strategies (tensor, pipeline, data parallelism), kernel execution graphs — and how they map to hardware. Performance modeling breadth: Hands-on experience with analytical performance models and execution-driven / architectural / cycle-accurate simulators, and sound judgment about which to reach for. Track record of turning models into decisions. GPU architecture depth: Strong command of GPU execution pipelines, SIMD/SIMT models, cache hierarchy, memory technologies, and high-bandwidth interconnects (PCIe, custom fabrics). Engineering craft: Expert modern C++ and production-grade Python. Execution: Excellent structured problem-solving; able to turn noisy simulation data into crisp, actionable findings for engineering stakeholders. Nice to have: Experience with NPU / AI-accelerator architecture, or modeling AI workloads on dedicated inference/training accelerators. #LI-AA1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Specialist IP Core - GSD", "company": "Ericsson", "location": "Noida,Uttar Pradesh,India", "date_posted": "2026-10-28T04:56:51+00:00", "url": "https://jobs.ericsson.com/careers/job/563121777438468", "is_hardware": true, "platform": "eightfold", "jd_text": "Join our Team\n\nAbout this opportunity:\nThe Network Engineer performs design, optimization and audit of a network to meet the customer requirements. The role is focused on executing design, audit and optimization services, where the network engineer is responsible for part of the solution and part of the service process. The Network Engineer is responsible to upkeep time, performance and quality according to Ericsson requirements and Customer contract.\n.What you will do:\nAccountable for day-to-day delivery of the assigned project towards the MA.\nCustomer facing role\nAnalyzing & troubleshooting different network related issues\nInteract with internal and external stakeholders for delivery execution\nExcellent communication skills\nTroubleshoots network problems and implements corrective action\nResponsible for IP Networks Design, Deployment/configuration, troubleshooting, root cause analysis and workaround / solution definition activities for the assigned project.\nAnalysis of KPIs, ensure all project KPI(s) are met as per agreed targets/SLA’s.\nOptimization of MPBN and ISP networks.\nSupport for field tests as required for new features and/or HW.\nThe skills you bring:\n7-9 years industry experience with excellent exposure on Design, Planning, Deployment & Troubleshooting in IP networks / MPBN Backbone on Telecom / ISP based networks.\nExtensive hands-on experience on IP routing protocols / technologies L2/L3 IP/MPLS VPNs, VPLS & EVPN, IGPs (All) on Cisco & Juniper routers.\nExcellent understanding & experience on Routing Protocols like OSPF, BGP, IS- IS, MPLS, Traffic Engineering, QoS (Quality of Service) in IP networks.\nGood hands-on experience in Configuration of IP Networks (Routing/Switching) – Cisco, Juniper, Ericsson Network / Security Devices.\nGood hands-on experience in Troubleshooting of IP Networks – Network related issues.\nShould have hands-on experience with Cisco, Ericsson & Juniper IP products.\nPrepares High-level design / Low-level design (HLD/LLD) independently.\nIP Professional Certifications (CCNP / Cisco Encore) on Cisco/ Juniper (JNCIP) is required.\nGood understanding of Segment routing.\nStrong Technical and Communications skills with excellent conceptual knowledge.\nExcellent verbal and written communication skills.\nOpen to work for a Global operator with rotational night shifts.\nSubject matter expertise on operator network and understanding.\nSuccessful track record and strong background in large-scale network operational organizations.\nExcellent customer handling skills.\nAbility to learn the working of new nodes which are added in the network.\nExperience on automation & scripting would be a plus.\nAbility to guide and support other engineers\nProfessional IP Certification. (CCNP, JNCIP)\n\nWhy join Ericsson?At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.\n \nWhat happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.\n \nPrimary country and city: India (IN) || Noida\nReq ID: 792925", "jd_status": "stored"}, {"title": "Staff Engineer – SoC Validation Framework & Infrastructure", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-28T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720995822", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nQualcomm's System Validation & Emulation (SVE) organization is looking for an experienced Staff Engineer to develop scalable software frameworks, tools, and infrastructure for pre-silicon and post-silicon SoC validation. The role involves embedded/system software development, silicon bring-up, validation automation, and complex hardware-software debugging across multicore SoC platforms.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nExperience: 8–11 years mandatory\n\nKey Skills:\nStrong programming expertise in C/C++, Assembly, Python & Shell\nEmbedded/System Software and validation framework/infrastructure development\nStrong understanding of ARMv8/ARMv9, multicore and heterogeneous SoC architectures\nExperience with Linux/RTOS, boot flows, interrupts, MMU and low-level software\nKnowledge of cache coherency, memory ordering, synchronization and memory subsystems\nHands-on experience with pre-silicon/emulation, FPGA and post-silicon validation/debug\nDebugging using JTAG/Trace32 and similar silicon debug tools\nExperience with GCC/Clang/LLVM, build systems, Makefiles and linker scripts\nExposure to CI/CD, validation automation and regression infrastructure\n\nPreferred: Experience with silicon/board bring-up, hardware-software integration, reusable validation frameworks, and SoC infrastructure development.\n\nMandatory Experience: Candidates must have 8–11 years of relevant industry experience in Embedded Software, System Software, SoC Validation, Silicon Enablement, Platform Software, or Validation Framework/Infrastructure Development.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU Staff/Senior Staff Engineer – ARM GIC & CPU Post-Silicon Validation", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-28T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721010087", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nRole Overview\nWe are looking for an experienced CPU/SoC Validation Engineer with strong knowledge of ARM Generic Interrupt Controller (GIC) architecture and hands-on experience in post-silicon validation, system-level debugging. The engineer will own validation of interrupt-controller functionality across CPU, firmware, power-management, and OS interactions.\n\nKey Responsibilities\nDevelop and execute post-silicon validation plans for ARM GICv3/GICv4 and CPU interrupt subsystems.\nValidate GIC components including: Distributor (GICD)Redistributor (GICR)CPU interface and system registersInterrupt Translation Service (ITS)SGI, PPI, SPI and LPI interrupt flows\nValidate interrupt routing, prioritization, masking, preemption, affinity, acknowledgement and EOI behavior.\nDevelop stress scenarios covering: Concurrent interrupt generationHigh interrupt ratesMulti-core interrupt routingSGI broadcast and targeted SGIsInterrupt migration and CPU hotplugInterrupt handling during CPU idle and low-power transitions\nValidate GIC behavior across CPU power collapse, suspend/resume, reset and DVFS transitions.\nDebug complex issues involving lost interrupts, unexpected routing, interrupt latency, stuck interrupts and incorrect GIC state.\nAnalyze key GIC registers such as GICD, GICR, ICC system registers, ICH virtualization registers and ITS state.\nValidate interactions between the GIC and OS/kernel, firmware, hypervisor and power-management software.\nWork closely with CPU architecture, firmware, kernel, power-management, design and verification teams to root-cause silicon issues.\nUse hardware/software debugging techniques including register dumps, trace, kernel logs, crash dumps and waveform/trace correlation.\nDevelop automation and stress workloads for interrupt validation and regression testing.\nTrack validation coverage, defects, risks and closure status through engineering tracking systems.\nRequired Technical Skills\nStrong understanding of ARMv8/ARMv9 architecture.\nStrong understanding of ARM GICv3/GICv4 architecture.\nGood knowledge of: SGI / PPI / SPI / LPIInterrupt affinity and routingPriority masking and preemptionGroup 0 / Group 1 interruptsSecure and Non-secure interrupt handlingGIC Distributor and RedistributorCPU interface registersITS and MSI-based interruptsVirtual interrupts / vGIC concepts\nUnderstanding of CPU power states, clock/power collapse, reset sequences and low-power entry/exit.\nProgramming/scripting experience with C/C++, Python and shell scripting.\nExperience with JTAG/debuggers and SoC debug methodologies is desirable.\nPreferred Experience\n7  to 16 years of experience in CPU/SoC post-silicon validation or silicon bring-up experience.\nValidation of ARM-based multicore SoCs.\nKnowledge of virtualization, hypervisors and virtual interrupt handling.\nExperience debugging interactions among GIC, CPU low-power states, DVFS and firmware.\nAbility to convert architectural requirements into validation scenarios, stress tests and measurable coverage.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SOC Design Verification Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-28T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721244335", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field.\n\nAs verification engineer candidate will be responsible to own SoC NSP/DSP/Audio DV during project work for various product segments. \n \nResponsibilities : \n\n✏️ Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. \n✏️Work alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue. \n✏️Collaborate with architects, designers, and pre and post silicon verification teams. \n  \nSkillsets/Requirements : \n✏️B.E/B.Tech/M.E/M.Tech in Electronics with 8+ year experience in verification domain. \n✏️Good understanding of Soc level verification testbench and flows. \n✏️Working knowledge and design understanding of Debug architecture of a SoC which includes Crash flow, JTAG, Trace, triggers, monitors, Scandump etc. \n✏️Exposure to Power aware simulations and Gate Level simulations \n✏️Good understanding of processor based Soc level verification which includes Verilog, System Verilog and UVM based environment. \n✏️Good understanding of AHB/AXI & ATB-AMBA protocol. \n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "EM Passives and RF Module Design Engineer, Senior", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-28T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721694797", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nJob Overview:  \nQualcomm is the industry leader in 3G, 4G and 5G communication technology and designs the most advanced radio technology in the commercial wireless marketplace, from LTE to Bluetooth.  \n \nQCT's RF EM (Electromagnetic) Team is actively seeking engineers with demonstrated experience in the design, EM simulation, and circuit modeling of RF passive components for use in our RFIC designs. Exposure to RF package, module, and PCB design and modeling is a plus.  \n \nKnowledge of Module and PCB level Power Distribution Network (PDN) and RF transmission line layout and analysis is an asset.  \n \nWorking experience with programming languages like Python, Matlab, SKILL is also a desired skill.  \n \nWorking experience and knowledge of Power Amplifier (PA) and Low Noise Amplifier (LNA) matching along with basic understanding of patch antenna design parameters and matching is also desired.  \n \n \n   Responsibilities:  \nDesign and develop RF passive components for use in the next generation of highly integrated RF integrated circuits in deep sub-micron 28nm and 14ff CMOS and SOI technologies.  \nWork with the RF circuit design team to optimize component sizes and performance for use in RF circuit blocks.  \nDeliver components that include compact models, and DRC clean physical designs.  \nExecute isolation analysis and optimization to reduce on-chip and chip to package coupling.  \nOptimization of multichip carriers for RF systems, focusing on loss and isolation.  \nParticipate in RF package, module, and PCB level of design and modeling to optimize overall system level performance   \n \nAll Qualcomm employees are expected to actively support diversity on their teams, and in the Company. \n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field.\n\nSkills and Experience:  \nExperience in the design and simulation of RF passive components such as inductors, transformers, MOM capacitors and passive filters.  \nExperience in design and modeling of RF modules for RF and mmWave frequency.  \nDemonstrated abilities with EM simulation techniques and tool including MoM EM solvers (EMX, PeakView,  Helic) and HFSS.  \nExperience with circuit design and layout using Cadence tools and Agilent ADS.  \nCompact RLCK Model extraction of multiport passive components.  \nAbility to use EM tools to predict circuit level electric and magnetic coupling.  \nUnderstanding of Chip fabrication process and design understanding  \nElectromagnetic theory, microwave theory and design  \nAntenna design and understanding of radiation and propagation wave  \nGood understanding of SI and PI at chip, package, and PCB level  \nBasic RF system understanding  \nUnderstanding of noise propagation mechanism in chip, package, and PCB  \nTools: Ansys Suit (HFSS, Q3D, SiWave, Layout), Lorentz, Helic, EMX, Cadence virtuoso, Allegro or similar for Package/Module layout, Expedition (or similar) for PCB layout and schematic \nPassionate self-starter and team player with experience in project leadership and multi-tasking. \n \nKeywords:  \nOn-chip passive, Inductor, Transformer, RF module, mmWave Module design, MOM Cap, Antenna, Signal and Power Integrity, PDN, Substrate coupling, RF Module, RF Package modeling, HFSS, Ansys, ADS, VRF \nEducational Requirements:  \nRequired: Bachelor’s degree in science, Engineering, or related field. Preferred: Master's and PhD \n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Design Verification (NPU) - Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-28T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720292831", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    5+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "ASIC RTL Design Engineer (Sr. Engr / Sr. Lead Engr)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-28T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720514602", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Description\n\nThis role offers a position in system power management IP cores and subsystem design, targeted for variety of industry leading Snapdragon SoCs for mobile, compute, IoT and Automotive markets.\n\nKey Responsibilities\nMicro-architecture and RTL design for IP Cores / subsystems.\nWork in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence.\nEnable SW teams to use HW blocks.\nQualify designs using static tool checks including Lint, CDC, CLP etc.\nSynthesis, LEC and Netlist CLP\nReport status and communicate progress against expectations.\n\n Preferred Qualifications\n3 to 8 years of strong experience in RTL design for ASICs\nExpertise in RTL coding in Verilog/SV of complex designs with multiple clock domains and multiple power domains\nFamiliar with UPF and power domain crossing\nExperience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP\nFamiliarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI\nExperience in low power design methodology and clock domain crossing designs\nExperience in Spyglass Lint/CDC checks and waiver creation\nExperience in formal verification with Cadence LEC\nUnderstanding of full RTL to GDS flow to interact with DFT and PD teams\nExpertise in Perl/TCL/Python language\nExperienced in database management flows with Clearcase/Clearquest.\nExpertise in post-Si debug is a plus\nExcellent oral and written communications skills to ensure effective interaction with Engineering Management and team  members.\nTeam player, self-motivated, should be able to work with minimal supervision.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RTL Design (NPU) - Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-28T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720292827", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    5+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NOC DV Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-28T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720400024", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nLooking for an experience Verification Architect/ Engineer, who will be responsible for verification of next generation Infrastructure IPs (DDRSS, Memory Controllers etc.) which goes into System-on-chip (SoC) for smartphones, tablets and other product categories. In this position you will be expected to plan and implement IP/Cluster/Formal verification flows for the Infra IPs. Also expected to coordinate with different Design and SOC teams throughout the IP development cycle.  \n\nJob responsibilities include \nOwnership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage) \nDevelop test plan and test cases to cover design feature set, follow up with stakeholders on code coverage, functional coverage closure at different levels of test bench \nWork closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure \nDebug of regression signatures and identifying bug fixes \nResponsible for Quality sign off and required documentation \nDeveloping/Deploying scripts/tools for validation (Certitude, VC Formal, VPlan) \nDebug and root cause post silicon issues in collaboration with Design, SW and test teams \nWork with SoC level performance modeling team on latency, bandwidth analysis next-generation experiences and drives digital transformation to help create a smarter, connected future for all.\n\nRequired skillset include \nStrong debugging, Analytical and problem-solving skills \nExpertise on UVM based verification  \nKnowledgeable about ARM bus protocols, Virtual Memory concepts, SoC system architecture \nExperience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved \nCommunication and collaboration skills to work with a large world-wide design organization \n\nDesired skillset includes \nExperience in designs optimized for low power - Dynamic clock gating, Logic/ Memory power collapse  \nExperience in verifying designs meeting Automotive Safety Integrity Levels (ASIL) \nProficiency in Scripting languages (Python or Perl) for Automation initiatives, C/C++/SystemC for performance models \nPost-si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage \nQualification : \nBachelor/Master’s Degree in Electronics & Communication / Micro Electronics \n8 Years of Experience in IP verification or related\nExperience with UVM and ARM Bus protocols. \n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU Physical Design Engineer (Lead/Staff/Sr. Staff)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-28T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720942626", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nMasters/Bachelors Degree in Electrical/Electronics science engineering with at least 5 years of experience in physical design.\nExperience in Physical Design and timing signoff for high speed cores.\nShould have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology.\nExperience in leading block level or chip level Physical Design, STA and PDN activities.\nWork independently in the areas of RTL to GDSII implementation.\nAbility to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc.\nKnowledge of low power flow (power gating, multi-Vt flow, power supply management etc.)\nCircuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.)\nTcl/Perl scripting Willing to handle technical deliveries with a small team of engineers.\nStrong problem-solving skills.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SoC Physical Design Engineer (Lead/Staff)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-28T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721391877", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nQualcomm Overview:\nQualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.\n\nGeneral Summary:\nExperience: 3-6 Years\nLocation: Bangalore\nJob Responsibilities\nOwn end-to-end physical design implementation from Netlist to GDSII for complex SoC/IP blocks.\nDrive Floorplanning, Power Planning (PDN), Placement, CTS, Routing, STA, and Timing Closure.\nPerform physical verification including DRC, LVS, and signoff checks.\nCollaborate with RTL, STA, DFT, Verification, and CAD teams to achieve design and tapeout goals.\nDebug and resolve timing, congestion, IR drop, and physical design challenges.\nSupport successful chip tapeouts on advanced technology nodes.\nRequired Skills\n3-6 years of hands-on experience in SoC/ASIC Physical Design.\nStrong expertise in Floorplanning, PDN, Placement, CTS, Routing, and Timing Closure.\nExperience with industry-standard EDA tools such as Innovus, ICC2/Fusion Compiler, PrimeTime, and Calibre.\nGood understanding of physical verification, power integrity, and signoff methodologies.\nExperience working on advanced nodes (16nm and below preferred).\nStrong debugging, problem-solving, and communication skills.\nPreferred\nExperience in high-performance CPU, GPU, AI, Mobile, Networking, or Multimedia SoCs.\nCandidates from leading semiconductor product companies are strongly preferred.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail myhr.support@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Engineer - ASIC DV", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-10-28T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/44409869", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nBe part of ASIC Design Verification team responsible for verification of IP/Block or Subsystem.\nRoles & Responsibilities:\n•   To be part of a highly skilled ASIC Team working on latest technologies\n•   Responsible for overall IP/Block and Subsystem verification from Test plan creation, System Verilog/UVM testbench development to Sign-off\n•   Ability to lead and mentor a team of verification engineers\n•   Ensure first pass product through verification coverage and sign-off criteria\n•   Pair with similar domain specialists across other geographical locations on core technical initiatives\nMinimum Qualifications:\n•   M.S./M.Tech, BS/BE (Electronics) with 7+ Years of experience\n•   Should have expertise in IP/Block/Subsystem level verification\n•   Experience with AMBA protocols like AXI/AHB\n•   PCIe/NVMe/DDR protocol knowledge and work experience on DDR/PCIe/NVMe controllers or similar IPs \n•   Proven track record of building Verification Plan, UVM Environment and Test Benches\n•   Experience with RTL debugging, Scoreboard, Assertions, Functional coverage coding and Code Coverage analysis\n•   Sound knowledge of Verilog and System Verilog languages\n•   This position requires good written and verbal communication skills as well a strong commitment and ability to work in cross functional and global teams\nPreferred Qualifications:    \n•    NVMe protocol knowledge and experience with working on NVMe controllers\n•    Good exposure and familiarity with security related aspects (boot, ROM, FW protection, keys generation, etc.) \n•    Experience with using AI tools (Claude etc)\n•    Experience with Technically leading an IP/Block to completion\nDomain:\n•    IP/Block/Subsystem Verification (RTL Front end verification)\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Senior Technical Staff Engineer - Architect (SoC)", "company": "Microchip", "location": "United Kingdom - Cambridge", "date_posted": "2026-10-28", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/United-Kingdom---Cambridge/Senior-Technical-Staff-Engineer---Architect--SoC-_R2548-26-1", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nThe Wireless Solutions Group is seeking an experienced Architect to define the portfolio for 32-bit microcontroller-based Bluetooth, UWB, and Wi-Fi products. In this role, you will lead the architecture of next-generation wireless SoC solutions that balance high performance with low power consumption.\n\nYou will provide technical leadership and work closely with marketing, applications, engineering teams, and external customers to gather requirements and develop peripheral and SoC architecture specifications. Success in this role requires strong cross functional collaboration, excellent communication skills, and the ability to thrive in a fast-paced, dynamic environment.\n\nKey Responsibilities\n\nDefine the architecture of complex Bluetooth, UWB, and Wi-Fi SoC solutions, including core selection, memory subsystems, power management, security, and test features.\n\nOwn peripheral architecture, including programming models, interfaces, feature sets, and detailed operational behaviour.\n\nConduct feasibility studies and architectural trade-off analyses to define products that meet target market cost and feature requirements.\n\nDrive product innovation through creative thinking and differentiated solutions that strengthen market competitiveness.\n\nPresent product vision, features, specifications, and cost considerations to leadership teams and customers to gain alignment and support.\n\nDefine architectures and features that support functional safety (ISO 26262) and cybersecurity (ISO 21434, including TARA analysis).\n\nContribute to SoC development from concept through tape-out by partnering with cross-functional teams across marketing, design, applications, verification, emulation, and product/test.\n\nCollaborate with firmware teams to ensure strong software support for wireless products. • Work with IP vendors and internal stakeholders to align technical requirements and project roadmaps.\n\nApply AI-driven and automation techniques to improve design quality, methodology, and efficiency, enabling faster cycle times and first-silicon success.\n\nFoster teamwork, collaboration across geographies, and an inclusive workplace culture.\n\nRequirements/Qualifications:\n\n15+ years of industry experience in wireless technology design and/or architecture roles.\n\nBachelor’s degree in Computer Science, Engineering, or a related field.\n\nProven expertise in microarchitecture, microcontroller development, and wireless product implementation.\n\nStrong knowledge of BLE, UWB, and Wi-Fi communication principles and standards.\n\nDeep familiarity with ARM and RISC core architectures.\n\nSolid understanding of low-power design and power/analog subsystems.\n\nComprehensive understanding of the microcontroller development lifecycle, including marketing requirements, pre-silicon and post-silicon validation, and production testing.\n\nProven track record of working with geographically distributed teams.\n\nFamiliarity with functional safety (FuSa) and cybersecurity standards for embedded products.\n\nPreferred Skills and Experience: Master’s degree in computer engineering, electrical engineering, or a related field.\n\nExperience with industry-leading SoC EDA tools and flows.\n\nKnowledge of security features and related design principles.\n\nBackground in validation methodologies, including debugging on FPGA and silicon IC boards.\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "SoC Chip Lead", "company": "Lattice", "location": "San Jose, CA", "date_posted": "2026-10-28", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/San-Jose-CA/SoC-Chip-Lead_R-103351", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\n\nJob Description:\nWe are looking for a senior SoC Chip Lead to join our San Jose office.\n\nKey Responsibilities\n\n·    Lead development of MCMs with FPGA and ASSPs utilizing 2.5D/3D advanced packaging technologies and chiplet-based architectures across multiple program generations\n·    Own chip tapeout and chip signoff with full accountability for chip quality\n·    Drive cross-functional technical leadership across multiple sites; translate product requirements into clear priorities, tradeoffs, and execution paths\n·    Partner with architects, RTL engineers, and software teams to evaluate architecture tradeoffs and drive hardware design decisions across the SoC\n·    Lead cycle-approximate performance modeling to enable architectural exploration ahead of RTL availability and accelerate early software development\n·    Quantify system-level tradeoffs across compute, memory bandwidth, and on-chip interconnect to shape reference architectures and inform long-term silicon strategy\n·    Own system-level debug spanning floor-planning, power distribution, clocking, timing closure, and SI/PI\n·    Engage with leading IP vendors to define and execute the IP roadmap; conduct competitive benchmarking\n·    Present project status and technology roadmaps to executive leadership, with a focus on new growth markets and opportunities\n·    Apply agentic AI methodologies to scale and accelerate design execution\n\nRequired Qualifications\n\n·    BS/MS/PhD in Electrical or Computer Engineering with 20+ years of FPGA/SoC design experience\n·    Established track record leading programs from concept to tape-out and production release\n·    Expertise in SystemVerilog, synthesis, and static timing analysis\n·    Deep expertise across SoC domains including High-speed interfaces, System Interconnects, Processor subsystems, and 2.5D/3D packaging and chiplet-based architectures\n·    Own system-level functional and performance modeling across SoC subsystems, ensuring RTL correlation and supporting emulation-based pre-silicon validation\n·    Define and own DFx methodology including scan, BIST, and manufacturing test from IP to chip level\n·    Experience debugging complex use cases through verification, emulation, and system validation\n·    Demonstrated ability to lead and grow geographically distributed, cross-functional engineering teams\n·    Strong written and oral communication skills with a history of executive-level presentations\n\nPay & Benefits\n\nConsistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. \n\nFor candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.  The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.\n\nBase Pay Range\n250,000.00\nIn addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! \n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in the United States.\n\nLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.\n \nAs an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.", "jd_status": "stored"}, {"title": "Senior Technology Engineer", "company": "Lattice", "location": "San Jose, CA", "date_posted": "2026-10-28", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/San-Jose-CA/Senior-Analog-IC-Design-Engineer_R-102920-1", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\n\nJob Description:\nWe are looking for a Senior Technology Engineer.  This person will be responsible for the interface between Lattice engineering and external foundries to enable successful process adoption and on-time tape-out. Ensure PDK readiness, and ensure alignment between internal EDA, design teams, and foundry requirements.\n\nKey responsibilities:\nServe as the primary technical interface to foundries, driving technical alignment, issue resolution, and escalations\nPartner with EDA teams on procurement, validation, and rollout of PDKs, models, and technology collateral\nEnsure design and signoff flows align with foundry requirements (DRC/LVS, EM/IR, ESD, SI/PI, reliability, etc.)\nOwn device test structure definition and support silicon characterization to validate process assumptions\nEstablish and scale processes for managing technology collateral, documentation, and design methodology consistency across programs\n\nQualifications:\n\nBS/MS/PhD in Electrical Engineering or related field\n10+ years in semiconductor technology and foundry interfacing roles\nDeep understanding of advanced process nodes and device physics\nProven ability to work with external partners (foundry, EDA, and IP vendors)\nStrong cross-functional collaboration and communication skills\n\nPreferred\nDirect experience with TSMC and Samsung foundry ecosystems\nStrong understanding of CAD/EDA flows (PDK, reliability, ESD, EM/IR, SI/PI, etc.)\nExperience supporting tape-out and silicon validation across multiple nodes\n\nPay & Benefits\n\nConsistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. \n\nFor candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.  The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.\n\nBase Pay Range\n211,000.00\nIn addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! \n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in the United States.\n\nLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.\n \nAs an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.", "jd_status": "stored"}, {"title": "DFT Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-10-28", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/DFT-Engineer_R027594", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nAs a member of our team, you will be responsible for various aspects of DFT, including MBIST and scan insertion, ATPG, ATE pattern development, and yield analysis.\nKey Responsibilities:\nWork closely with the ATE engineer on yield improvement and analysis.\nDevelop ATE patterns, manage the hand-off process, and perform silicon debugging.\nParticipate in block and chip-level DFT implementation, developing and executing all related tasks.\nWork on DFT lint checking, MBIST architecture, logic insertion, and scan insertion using industry-standard tools.\nPerform ATPG and pattern simulation for both MBIST and scan.\nCollaborate with the design, verification, and implementation teams during the DFT design phase, and with the ATE and product development teams during silicon bring-up.\nEngage with various cross-functional team members, with opportunities to enhance our DFT design methodology.\nRequired Qualifications:\nBachelors in Engineering and 8+ years of related experience or Masters degree and 6+ years of related experience\nRequired experience in silicon bring-up and yield improvement.\nSolid understanding of DFT techniques.\nProven experience in RTL lint checking, scan compression, scan insertion, and the ATPG process.\nExperience in MBIST architecture and insertion.\nExperience in analyzing and debugging simulation failures.\nSolid understanding of digital logic fundamentals.\nStrong knowledge of the Mentor Tessent/Synopsys DFT and simulation tool suite.\nProficiency with Perl or other scripting languages.\nStrong communication and interpersonal skills.\nPlus: Experience in STA constraint development in DFT modes\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Physical Design Lead", "company": "NXP", "location": "Bangalore", "date_posted": "2026-10-28", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Physical-Design-Lead_R-10067207", "is_hardware": true, "platform": "workday", "jd_text": "As a Physical Design Lead Engineer, you will serve as a key technical leader responsible for the end-to-end physical implementation of complex SoCs and IPs on advanced technology nodes. You will own large and challenging design partitions or drive critical top-level physical design activities, including floorplanning, place-and-route, timing closure, and signoff.\nYou will play a pivotal role in achieving ambitious power, performance, area (PPA), quality, and schedule goals while providing technical leadership, mentoring engineers, and driving methodology improvements across multiple projects.\nKey Responsibilities\nLead and execute all aspects of physical design from RTL to GDSII, including synthesis, floorplanning, power planning, place and route, clock tree synthesis (CTS), timing closure, physical verification, and tapeout.\nOwn the complete physical implementation of complex SoC partitions, subsystems, or top-level designs and drive closure to production-quality signoff.\nPerform and drive advanced static timing analysis (STA), multi-corner multi-mode (MCMM) optimization, timing ECO implementation, and signoff closure.\nDrive closure across power, performance, area, signal integrity (SI), electromigration (EM), IR-drop, reliability, and manufacturability targets.\nDevelop and optimize physical design methodologies, automation frameworks, flows, and scripts to improve design quality, efficiency, and turnaround time.\nAnalyze critical timing paths, congestion, routing, and power bottlenecks, and develop innovative solutions to achieve aggressive PPA goals.\nCollaborate closely with architecture, RTL design, verification, DFT, package, and technology teams to resolve implementation challenges and optimize overall product quality.\nDrive physical signoff activities including DRC, LVS, antenna checks, density closure, metal fill verification, and tapeout readiness reviews.\nContribute to architecture and design reviews by providing implementation-driven feedback to improve PPA and physical feasibility.\nEvaluate and deploy new EDA tools, methodologies, and advanced implementation techniques.\nImplement advanced low-power design methodologies including clock gating, power gating, multi-voltage design, retention, isolation, and UPF/CPF-based flows.\nMentor and guide engineers, providing technical leadership and fostering engineering excellence across teams.\nGenerate comprehensive implementation reports, signoff documentation, and design reviews throughout the development cycle.\n\nRequired Qualifications\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.\n15+ years of ASIC/SoC physical design experience with a proven record of successful tapeouts on advanced process technologies.\nExtensive hands-on experience in synthesis, floorplanning, place and route, timing analysis, physical verification, and signoff closure.\nProven ability to independently drive block-level, subsystem-level, and top-level implementation of complex multi-million gate SoCs, including multi-processor architectures.\nStrong expertise in one or more of the following domains: Physical Design & Implementation Synthesis & Timing Analysis\nDeep understanding of MCMM timing closure methodologies, timing constraint development, ECO implementation, and signoff flows.\nHands-on experience with industry-standard EDA tools, including: Cadence Innovus and Tempus Synopsys Fusion Compiler, ICC2, and PrimeTime Ansys RedHawk or equivalent EM/IR analysis tools\nStrong knowledge of physical signoff methodologies including DRC, LVS, antenna checks, density validation, and metal fill closure.\nExperience with signal integrity analysis, crosstalk mitigation, electromigration (EM), and IR-drop closure.\nStrong understanding of manufacturability requirements and Design for Manufacturability (DFM) principles.\nProficiency in Tcl scripting and working knowledge of Python and/or Perl for automation, reporting, and flow development.\nDemonstrated ability to drive multiple implementation experiments and optimize designs against challenging PPA targets.\nExperience with advanced process nodes including 16nm FinFET and below; experience in 7nm, 5nm, or more advanced technologies is a plus.\nHands-on experience with low-power design techniques including clock gating, power gating, multi-voltage implementation, retention, isolation, and UPF/CPF methodologies.\nDemonstrated technical leadership, mentorship, and ability to drive cross-functional initiatives.\nExcellent problem-solving, analytical, debugging, communication, and stakeholder management skills.\nAbility to thrive in a fast-paced, collaborative, and globally distributed engineering environment.\n\nPreferred Qualifications\nExperience leading physical implementation and signoff for large-scale SoCs across multiple engineering sites.\nExperience developing organization-wide design methodologies, automation frameworks, and best practices.\nStrong understanding of advanced-node challenges including congestion management, variation-aware timing closure, power integrity, and reliability signoff.\nExperience evaluating and deploying next-generation EDA technologies and AI-assisted design optimization techniques.\n\nMore information about NXP in India...\n\n#LI-9415", "jd_status": "stored"}, {"title": "Application Engineering, Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-28", "url": "https://careers.synopsys.com/job/bengaluru/application-engineering-staff-engineer/44408/102541516464", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:\n \nAt Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.\n \n Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules.\nYou Are:\nYou are a highly skilled and passionate engineer with a talent for tackling complex problems and a strong desire to advance cutting-edge technology. With over 3 to 5 years of experience in Physical Implementation RTL-GDS, you bring deep expertise in autonomously diagnosing and resolving synthesis and place-and-route (PnR) challenges. Proficient in scripting languages like Tcl, Unix, and Perl, you possess an in-depth knowledge of Synopsys implementation tools and methodologies, especially Fusion Compiler.\n \n Your strong communication abilities enable you to engage effectively with both customers and internal teams, ensuring precise and attentive fulfilment of their needs. Driven, self-starting, and highly collaborative, you excel in environments where you can advocate for customers and represent the product. Your experience in multiple chip tape-outs—preferably at 7nm or lower nodes across foundries—gives you a unique perspective in delivering robust solutions for advanced silicon designs.\n \n You are motivated by the opportunity to drive innovation, translate technical insights into actionable requirements for R&D, and contribute to Synopsys’ solution capabilities. You thrive in diverse, inclusive environments and value the importance of knowledge sharing, mentoring, and continuous learning. Your commitment to customer success, technical excellence, and collaborative problem-solving makes you an essential part of any high-performance engineering team.\n \nWhat You’ll Be Doing:\n \nDrive global customer adoption of Synopsys Implementation products by providing expert technical guidance and support throughout the RTL-to-GDS flow.\nDiagnose and resolve synthesis and place-and-route challenges, leveraging in-depth knowledge of customer designs and Synopsys tools.\nEngage in technical campaigns—such as benchmarks, deployments, and new solution enablement—to fuel Synopsys solution adoption and improve usability.\nAct as a customer advocate, collaborating with R&D to influence product roadmap and future technologies based on real-world feedback.\nAuthor technical articles for the Knowledge Base, providing self-help guidance for common customer challenges.\nRoll out new product methodologies to customers through training sessions and technical support engagements.\n \nThe Impact You Will Have:\n \nDeliver comprehensive support and effective technical solutions that elevate customer satisfaction and project success.\nDrive innovation by tackling advanced design challenges and collaborating with R&D to enhance product performance.\nPromote Synopsys implementation tools, expanding market presence and accelerating solution adoption.\nEnsure seamless EDA transitions for customers, optimizing outcomes in power, cost, and performance.\nInfluence the development of next-generation processes and models for silicon chip manufacturing.\nEmpower engineering teams through technical mentorship and knowledge sharing.\n \nWhat You’ll Need:\n \nExpertise in implementation methodologies, with deep hands-on experience in Synopsys Fusion Compiler.\nThorough understanding of RTL-to-GDS flows and methodologies, including synthesis, place & route, and timing analysis.\nProficiency in scripting languages such as Tcl, Unix shell, Perl, and Python.\nExperience in low-power flows, design planning, and static timing analysis (STA).\nExcellent verbal and written communication skills; prior customer-facing experience is a plus.\nB-Tech or equivalent with minimum 5 years of experience, or M-Tech or equivalent with minimum 3 years of experience.\nDomain knowledge in multiple chip tape-outs, preferably at 7nm or lower nodes across foundries.\n \nWho You Are:\n \nCustomer-focused problem solver with a proactive and collaborative mindset.\nStrong communicator adept at translating complex technical concepts for diverse audiences.\nInnovative and resourceful, thriving in fast-paced, high-impact environments.\nSelf-starter who excels at independent and team-based work.\nCommitted to diversity, inclusion, and continuous learning.\n \n \nThe Team You’ll Be A Part Of:\n \nYou’ll join a dynamic and diverse Application Engineering team at Synopsys Bangalore, dedicated to driving customer success and innovation in AI-enabled design automation. The team partners closely with global customers, R&D, and product management to deliver state-of-the-art solutions for the most advanced silicon on the planet. We are passionate about pushing the boundaries of what's possible in chip design and software security, and we are looking for like-minded individuals to join us on this exciting journey.\n \nRewards and Benefits:\n \nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Principal Engineer, Agentic AI (CAD/EDA)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-28", "url": "https://careers.synopsys.com/job/bengaluru/principal-engineer-agentic-ai-cad-eda/44408/102541516352", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nYou have spent the better part of a decade building CAD infrastructure that has to hold up under real silicon development pressure, not just proof-of-concept demos or similar domains. You know that the difference between a flow that gets adopted and one that gets worked around is usually in the details no one else thought about. Lately, you have been watching the explosion of agentic AI and LLM orchestration, and instead of seeing hype, you see exactly how autonomous agents could transform the way IP gets designed, verified, and managed across its lifecycle.\nYou are someone who can sit with IP designers who need faster turnaround on design and verification and walk out with a multi-agent workflow spec that actually solves their problem. You do not wait for the AI platform team to tell you what is possible. You prototype, you integrate, you prove the concept, and then you scale it. You have strong opinions about what makes infrastructure scalable, and you are not afraid to push back when a proposed solution will not survive the challenges of a scalable production use.\nAt Synopsys, you will work at the center of Silicon Lifecycle Management (SLM) IP development in the AI Center of Excellence team, architecting AI Infrastructure, building Agents from scratch, leveraging when possible and customizing to the team needs. The problems are hard, the scale is real, and what you build will reshape how thousands of engineers work.\n\nWhat You'll Be Doing\nArchitect and define the next generation of AI-powered CAD infrastructure for Silicon IP development, building and integrating autonomous agents into core design and verification workflows\nBuild Agentic frameworks and Agents to improve Engineering productivity of the organization\nDeploy and operationalize Synopsys' global Agentic AI platform directly into the SLM IP development loop, building orchestration layers that connect LLMs, agents, and EDA toolchains across design, verification, synthesis, PnR, and timing\nDesign multi-agent workflows that automate IP design tasks, verification loops, and lifecycle analytics, turning manual bottlenecks into autonomous, scalable processes\nPartner with IP design teams, CAD engineers, and global AI platform teams to align architecture with real engineering needs and deployment constraints\nBuild and maintain the infrastructure layer that connects silicon design phases with AI-driven automation, ensuring performance, reliability, and scalability across the full IP lifecycle\nPrototype, test, and validate new AI-CAD integrations in live development environments, iterating based on feedback from design teams and measurable workflow improvements\nDrive technical strategy and roadmap for AI-augmented CAD systems within SLM, translating emerging AI capabilities into concrete engineering solutions\nProvide technical leadership and mentorship to the team, fostering best practices\n\nThe Impact You Will Have\nEnable IP design and verification teams to move faster by automating repetitive, high-friction tasks through intelligent agent-driven workflows\nReduce time-to-market for SLM IP by building scalable CAD infrastructure that adapts to design complexity without linear increases in manual effort\nSet the technical foundation for how Synopsys integrates agentic AI into silicon development, influencing architecture decisions across the broader EDA organization\nImprove design quality and lifecycle visibility by embedding AI-driven analytics and telemetry into the core IP development flow\nAccelerate adoption of Synopsys' Agentic AI platform by proving its value in one of the most demanding, high-stakes engineering environments in the company\nShape the future of CAD infrastructure at Synopsys, defining patterns and practices that will scale across multiple IP families and product lines\nDirectly influence how thousands of engineers experience their daily workflows, making complex silicon development more efficient, predictable, and autonomous\n\nWhat You'll Need\nBachelor's, Master's, or Ph.D. in Computer Science, VLSI, Electrical Engineering, or a related field\n12+ years of hands-on experience developing and deploying advanced CAD flows and infrastructure in silicon design environments\nProven experience implementing Agentic AI frameworks such as LangGraph, AutoGen, CrewAI, or equivalent platforms, LLM orchestrations, or autonomous software agent systems in production settings\nMastery of Python and C++ for building production-grade infrastructure, plus strong proficiency in EDA scripting languages like Tcl, Perl, and Shell\nTrack record of building agents and orchestration layers that interact with design, verification, synthesis, PnR, and timing flows\nTechnical understanding of silicon design phases, particularly IP development, verification, and lifecycle management workflows, is a plus\nExperience with Silicon Lifecycle Management concepts such as in-chip sensing, telemetry, and analytics is a strong plus\n\nWho You Are\nYou can walk into a room full of IP designers talking about verification bottlenecks and walk out with a clear architecture for an agent-driven solution that actually fits their workflow\nYou prototype fast and iterate based on real feedback, not theoretical requirements, and you know the difference between a demo that impresses and a system that ships\nYou have a point of view on what makes CAD infrastructure scalable and maintainable, and you are comfortable defending that view with technical depth and real-world examples\nYou are comfortable operating in ambiguity, especially when integrating cutting-edge AI technologies into established silicon development environments where stability and correctness are non-negotiable\nYou think in systems, understanding how changes in one part of the CAD flow ripple through design, verification, and downstream lifecycle analytics\nYou do not need perfect documentation or fully baked requirements to get started, you ask the right questions, align stakeholders, and find a path forward\n\nThe Team You'll Be Part Of\nYou will be part of the Silicon Lifecycle Management IP Development team in Bangalore, working at the intersection of advanced IP design and AI-driven automation. This team is responsible for building the infrastructure and workflows that power SLM IP development across Synopsys, and you will be the principal engineer defining how agentic AI gets integrated into that foundation. You will collaborate closely with IP designers, CAD engineers, and Synopsys' global Agentic AI platform teams, bridging technical domains and driving alignment across a distributed, highly technical organization. This is a Principal Individual Contributor role with significant technical leadership responsibilities across multiple globally distributed engineering teams. This role may evolve into leading a small team of AI infrastructure engineers as adoption scales.\n\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\n\n#TPG", "jd_status": "stored"}, {"title": "Senior Hardware Development Engineer", "company": "Nokia", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-10-28", "url": "https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/40135", "is_hardware": true, "platform": "oracle", "jd_text": "As a member of the Nokia GX product R&D team, the ECAD Layout Lead is responsible for delivering layouts for advanced optical L1 cards & pluggable.\nThis role involves close collaboration with architects across Mechanical, Thermal, Signal Integrity, and Electrical domains to assess layout feasibility. The responsibilities extend to full implementation, including coordination with Manufacturing for DFx considerations. Beyond hands-on layout work, the role also includes mentoring and guiding the broader ECAD team.\n\nNILightpath\n\nResponsibilities\nThis role involves close collaboration with architects across Mechanical, Thermal, Signal Integrity, and Electrical domains to assess layout feasibility. The responsibilities extend to full implementation, including coordination with Manufacturing for DFx considerations. Beyond hands-on layout work, the role also includes mentoring and guiding the broader ECAD team.\n\nQualifications\nMust-Have-Skills\nMinimum 7 years’ experience in ECAD layout\nHas led complex layout end to end \nKnowhow of Mentor Graphics and Cadence tool chain\nUnderstand PCB Stack-up, various materials and constrains \nVery good understanding of DFx\nWorked on complex boards, telecom boards are preferred \nHad through understanding of process, checklists.\nHas contributed to process improvement. \nFlexible in working across time-zones\nGood in communication \nWorking knowledge of MS office tools \nNice-to-have-skills \n\nUnderstand PCB Stack-up, various materials and constrains \nVery good understanding of DFx\n\nAbout the company\nAdvancing connectivity to secure a brighter world.\n\nNokia is a global leader in connectivity for the AI era. With expertise across fixed, mobile and transport networks, powered by the innovation of Nokia Bell Labs, we’re advancing connectivity to secure a brighter world. \n\nLearn more about life at Nokia.\n\nOur recruitment process\n\nWe act inclusively and respect the uniqueness of people. Our employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.\n\nIf you’re interested in this role but don’t meet every listed requirement, we still encourage you to apply. Unique backgrounds, perspectives, and experiences enrich our teams, and you may be just the right candidate for this or another opportunity.\n\nThe length of the recruitment process may vary depending on the specific role's requirements. We strive to ensure a smooth and inclusive experience for all candidates. Discover more about the recruitment process at Nokia.\n\nAbout the organization\nSome of our benefits in India:\n\nFlexible and hybrid working arrangements to support work–life balance\n\nHealth and well-being support – medical insurance for you and your family, health check-ups, life and accident insurance, well-being programs, and employee resource groups \n\nA minimum of 90 days of Maternity and Paternity Leave based on eligibility\n\nPersonal Support Service 24/7 – a confidential support channel open to all Nokia employees and their families in challenging situations\n\nCareer growth & mobility – technical career paths, job rotations, international assignments, and relocation support\n\nContinuous learning – technical certifications, mentoring programs, coaching, and digital learning platforms\n\nOpportunities to innovate and contribute through Nokia’s research and development environment\n\nRecognition programs that celebrate outstanding contributions\n\nWorkplace support – ergonomic working support and mobile device programs based on eligibility", "jd_status": "stored"}, {"title": "Staff Optical Engineer", "company": "Nokia", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-10-28", "url": "https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/39916", "is_hardware": true, "platform": "oracle", "jd_text": "We are seeking a talented Optical HW Engineer to join our dynamic team, contributing to the design and development of cutting-edge optical coherent transceiver plug/transponder line card, plus integration and oDVT (optical design verification test). \nYou will own optical design and integration at system and product level: optical architecture, how the product is verified, manufacturing handoff, and technical authority on optical design and DVT. You will turn product requirements into optical architecture, design rules, and oDVT coverage; lead closure of performance gaps across optics / DSP / firmware / card; and be accountable for optical quality at release.\n\n NILightpath\n\nResponsibilities\nOwn optical design architecture for coherent transceivers and transponder line cards: optical path, component/module strategy, schematic/design rules for optics, and approval of design updates.\nLead design reviews of schematic, layout, mechanical fiber, thermal, and SI as they affect optical performance; approve optical design for the product.\nDecide tradeoffs among PIC, analog ASIC, DSP, pluggable vs embedded, and line-card optics; negotiate with architecture, ASIC, and PIC teams.\nSet oDVT scope, pass/fail criteria, and coverage vs product requirements, impairments, environment, and MSA/reference (OIF, OpenZR+, OpenROADM, ITU-T as applicable).\nIntegrate optical modules into coherent transceivers and transponder line cards, ensuring optical performance.\nCompare results to spec and MSA/reference; drive closure with DSP, PIC, analog, FW, and hardware.\nTranslate oDVT findings into design changes (BOM, schematic, firmware defaults, mechanical fiber routing).\nApply DFx (test, manufacture, reliability, compliance) in the optical design; not added after oDVT, and not only a lab prototype.\nDefine calibration architecture and the manufacturing optical test strategy (yield, test time, DVT-to-production correlation).\nApprove test plans, procedures, and release reports; sign optical design and oDVT for the product.\nOwn the optical validation automation strategy (Python/framework, data quality); not only individual script fixes.\nCreate and approve technical documentation (architecture, design rules, test plans, procedures, reports).\nLead cross-functional (XF) work on optical performance; represent optical design, integration, and oDVT for the product.\n\nQualifications\nMust-have-skills\nBachelor's or Master's in Optical Engineering, Electronics, Electrical Engineering, or a related field (Ph.D. a plus).\nMust have worked on optical line cards/systems.\nMust have at least 8+ years of proven experience in optical design, integration, and testing of coherent transceivers/transponders, including ownership of optical transceiver design and optical DVT through product release.\nDeep coherent transmission: QAM, FEC/DSP basics, DWDM impairments (OSNR, CD, PMD, SPM/XPM/FWM, crosstalk) and spec tradeoffs.\nFamiliarity with optical characterization equipment and measurement techniques.\nAbility to define and approve design/test plans, troubleshoot complex optical systems, and communicate results clearly.\nHands-on expertise with optical characterization equipment and measurement techniques.\nStrong problem-solving skills and the ability to troubleshoot complex optical systems.\nExcellent communication skills.\nNice-to-have-skills  \n\nHands-on expertise with optical characterization equipment and measurement techniques.\nStrong problem-solving skills and the ability to troubleshoot complex optical systems.\n\nAbout the company\nAdvancing connectivity to secure a brighter world.\n\nNokia is a global leader in connectivity for the AI era. With expertise across fixed, mobile and transport networks, powered by the innovation of Nokia Bell Labs, we’re advancing connectivity to secure a brighter world. \n\nLearn more about life at Nokia.\n\nOur recruitment process\n\nWe act inclusively and respect the uniqueness of people. Our employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.\n\nIf you’re interested in this role but don’t meet every listed requirement, we still encourage you to apply. Unique backgrounds, perspectives, and experiences enrich our teams, and you may be just the right candidate for this or another opportunity.\n\nThe length of the recruitment process may vary depending on the specific role's requirements. We strive to ensure a smooth and inclusive experience for all candidates. Discover more about the recruitment process at Nokia.\n\nAbout the organization\nSome of our benefits in India:\n\nFlexible and hybrid working arrangements to support work–life balance\n\nHealth and well-being support – medical insurance for you and your family, health check-ups, life and accident insurance, well-being programs, and employee resource groups \n\nA minimum of 90 days of Maternity and Paternity Leave based on eligibility\n\nPersonal Support Service 24/7 – a confidential support channel open to all Nokia employees and their families in challenging situations\n\nCareer growth & mobility – technical career paths, job rotations, international assignments, and relocation support\n\nContinuous learning – technical certifications, mentoring programs, coaching, and digital learning platforms\n\nOpportunities to innovate and contribute through Nokia’s research and development environment\n\nRecognition programs that celebrate outstanding contributions\n\nWorkplace support – ergonomic working support and mobile device programs based on eligibility", "jd_status": "stored"}, {"title": "Layout Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-10-28", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018741", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n Texas Instruments is seeking a Layout Engineer. In this role, you will develop and prepare multi-dimensional layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering. Work may be completed through use of CAD or other computerized equipment. You may also check dimensions, write specifications, and verify completed drawings, artwork or digitized plots. Additional job functions may involve checking design layouts and detailed drawings, referring to offline layout leveling charts for details on duties. A bachelor's degree in engineering is typically required, and in the U.S. this job is restricted to specific job grades.\n\nCandidates are expected to have following skills -\n\nGood floor planning skills.\n\nBlock layout closure which meets performance / Area/ quality requirements.\n\nGood ESD knowledge & PAD ring completion with ESD & IO placements\n\nGood EM /IR knowledge + exposed to  Volus-Fi / Totem flow.\n\nGood process knowledge & Packaging knowledge.\n\nGood at automation.\n\nExpert in Virtuso XL, Assura/PVS tools.\n\nQualifications\nMinimum requirements:\n\nMinimum education (ie bachelor's degree in electrical engineering)\n\nMinimum of 3 years of experience\n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Senior Layout Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-10-28", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2507059", "is_hardware": true, "platform": "oracle", "jd_text": "Job Summary\n\nWe are seeking a motivated Analog Layout Engineer with strong hands-on experience in custom analog and mixed-signal layout development. The candidate should have a solid understanding of analog layout fundamentals, matching techniques, process understanding, and verification closure. Experience in higher-node technologies and DNW-based layouts is preferred.\n\nKey Responsibilities\n\nDevelop high-quality custom analog and mixed-signal layouts from schematics.\n\nImplement device matching, common-centroid structures, shielding, guard rings, symmetry, and parasitic-aware layout techniques.\n\nPerform layout verification and achieve clean DRC, LVS, and ERC sign-off.\n\nDebug DRC/LVS issues independently and drive closure efficiently.\n\nUnderstand and interpret process cross-sections, layer interactions, and device structures.\n\nWork closely with circuit designers to ensure proper implementation of design intent.\n\nParticipate in layout reviews and incorporate feedback for quality improvements.\n\nSupport extraction and post-layout verification activities.\n\n#LI-RG1\n\nQualifications\nRequired Skills\n\nB.E (Electronics, E&TC or relevant field)\n\n2-3 years of hands-on analog/custom layout experience.\n\nStrong understanding of: \n\nDevice matching techniques\n\nCommon centroid layouts\n\nInterdigitization\n\nGuard rings and shielding\n\nLatch-up prevention concepts\n\nAnalog routing methodologies\n\nGood understanding of semiconductor process technology and device cross-sections.\n\nExperience with Deep N-Well (DNW) processes is preferred.\n\nStrong debugging skills in DRC/LVS verification.\n\nGood, logical reasoning and analytical problem-solving skills.\n\nFamiliarity with Cadence Virtuoso and industry-standard verification flows.\n\nGood communication and teamwork skills.\n\n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Experienced Engineer- ASIC Verification", "company": "Ericsson", "location": "Bangalore,Karnataka,India", "date_posted": "2026-10-27T16:52:33+00:00", "url": "https://jobs.ericsson.com/careers/job/563121777515889", "is_hardware": true, "platform": "eightfold", "jd_text": "Join our Team\n\nAbout this opportunity:\nWe are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport – to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we don't just follow industry trends—we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, you'll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies.\nAs part of our global R&D organization, you'll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork.\nCreative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. You'll have the opportunity to explore advanced verification technologies alongside skilled experts.\n \nWhat you will do:\nTake part in the verification of designs, whether at the block or subsystem level.\nParticipate in defining and implementing UVM-based test environments.\nSupport the creation of Verification Strategies and contribute to the development and execution of Verification Plans.\nDevelop, run, and debug test cases to ensure design quality.\nContribute to the improvement and optimization of verification methodologies.\nGenerate documentation throughout the verification lifecycle.\nCollaborate closely with other verifiers, designers, and architects.\nBuild competence in the technical domain.\nEngage in cross-team collaboration to ensure successful project delivery.\n\nThe skills you bring:\nBachelor’s degree in electrical or computer engineering.\n5+ years industry experience in ASIC IP verification using System Verilog and UVM.\nExperience in / with:\n    1.Developing creating directed/randomized test cases.\n    2.Implementing scoreboards, checkers, bus functional models within UVM environments.\n    3.AMBA-based designs such as AXI and CHI.\n    4.System Verilog Assertions.\n\nPreferred Skills:\nUnderstanding of radio access systems and their components.\nExperience in low-power design verification.\nWorking knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira).\nExperience in formal verification\nExperience in verification in one or more of the following hardware domains:\n   1. ARM-based real-time embedded microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces.\n   2.Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.)\n\"All academic credentials must be from recognized and accredited institutions and are further subject to verification.”\n\nWhat happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.We encourage you to consider applying to jobs where you might not meet all the criteria. We recognize that we all have transferrable skills, and we can support you with the skills that you need to develop.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.\n \nPrimary country and city: India (IN) ||\nJob details: Developer\nJob Stage: Job Stage 5", "jd_status": "stored"}, {"title": "Senior Engineer - ASIC Verification", "company": "Ericsson", "location": "Bangalore,Karnataka,India", "date_posted": "2026-10-27T16:28:28+00:00", "url": "https://jobs.ericsson.com/careers/job/563121777515613", "is_hardware": true, "platform": "eightfold", "jd_text": "Join our Team\n\nAbout this opportunity:\n \nWe are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport – to enable communication service providers to surpass the expectations of their end-customers.  At our state-of-the-art design centers, we don't just follow industry trends—we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, you'll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. \n \nAs part of our global R&D organization, you'll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. \n \nCreative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. You'll have the opportunity to explore advanced verification technologies alongside skilled experts. \nGlobal Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. \nWork-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. \nProfessional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere.\nAn international work environment with opportunities for professional growth and development. \nA collaborative and inclusive culture that values diversity and innovation.\n\nYou will do:\n\nTake part in the verification of designs, whether at the block or subsystem level. \nParticipate in defining and implementing UVM-based test environments. \nSupport the creation of Verification Strategies and contribute to the development and execution of Verification Plans. \nDevelop, run, and debug test cases to ensure design quality. \nContribute to the improvement and optimization of verification methodologies. \nGenerate documentation throughout the verification lifecycle. \nCollaborate closely with other verifiers, designers, and architects. \nBuild competence in the technical domain. \nEngage in cross-team collaboration to ensure successful project delivery\n\nYou will bring:\n\nBachelor’s degree in electrical or computer engineering. \n10+ years industry experience in ASIC IP verification using SystemVerilog and UVM.  \nStrong experience in / with: developing verification test plans and creating directed/randomized test cases. \nin implementing scoreboards, checkers, bus functional models within UVM environments. \nAMBA-based designs such as AXI and CHI. \nSystemVerilog Assertions. \n\n \nAdditional Requirements: \nExperience with Cadence or Synopsys verification suites. \nTeam-oriented, prioritizing team success within the team, across teams, and across sites over individual results.   Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. \nHigh attention to detail and commitment to quality. \nStrong focus on meeting project deadlines and deliverables. \nProficient in English, with strong communication skills. \n \nPreferred Skills: \nUnderstanding of radio access systems and their components. \nExperience in low-power design verification. \nWorking knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). \nFormal Verification experience \nExperience in verification in one or more of the following hardware domains: ARM-based real-time embedded microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. \nImplementation of hardware-based digital signal processing systems (filters, adaptation, etc.)\n\n*\n\n“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”\n\nWhy join Ericsson?At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.\n \nWhat happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.\n \nPrimary country and city: India (IN) || Bangalore\nReq ID: 793557", "jd_status": "stored"}, {"title": "Principal DFT Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-27T11:10:39.949000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000158016390-principal-dft-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are looking for an experienced DFT Lead to own end-to-end Design-for-Test activities for complex Automotive MCU/SoC products. The role will drive DFT architecture, implementation, verification, and production-test readiness while working closely with SoC Design, Verification, PTE, Product and Test Engineering teams.\nKey Responsibilities\nOwn the DFT architecture and strategy for automotive MCU/SoC products from specification through silicon production readiness.\nDefine and implement DFT solutions including scan architecture, compression, memory BIST, logic BIST, boundary scan/JTAG and test access architecture, as applicable.\nDrive DFT implementation and associated RTL/design updates, working closely with SoC, IP and RTL design teams.\nOwn DFT verification and simulation, including test-mode validation, scan/MBIST connectivity, ATPG-related simulations and gate-level verification.\nDrive ATPG and pattern generation, validation and release of production-ready test patterns to Product and Test Engineering teams.\nAct as the primary technical interface with PTE/Product/Test teams for DFT, test-pattern and silicon-test requirements.\nWork with design teams to define and align DFT requirements, test modes, clocks, resets, power domains, constraints and chip-level integration requirements.\nReview DFT coverage, pattern count, test time and testability metrics, and drive closure of coverage gaps.\nSupport silicon bring-up, pattern debug, test failures and yield-related DFT investigations.\nOwn DFT deliverables, reviews, sign-off criteria and milestone tracking across the product development lifecycle.\nIdentify DFT-related technical and schedule risks early and drive cross-functional closure.\n\nRequired Skills & Experience\n15+  year experience in DFT architecture and implementation for complex MCU/SoC devices.\nHands-on expertise in scan insertion, scan compression, ATPG, MBIST and JTAG/boundary scan.\nStrong understanding of RTL and gate-level design, clocks, resets, power domains and SoC integration.\nExperience with DFT simulation, pattern verification and gate-level simulation/debug.\nExperience in ATPG pattern generation, fault coverage analysis and production pattern delivery.\nGood understanding of the interface between design DFT and ATE/production testing.\nExperience working with Product Engineering and Test Engineering teams during silicon bring-up and production ramp.\nFamiliarity with industry-standard DFT tool flows from Siemens EDA, Synopsys and/or Cadence.\nStrong problem-solving and debugging skills with the ability to drive issues across multiple engineering organizations.\nAbility to independently lead DFT activities and communicate effectively with architecture, design, verification, physical design and product/test teams.\nPreferred Experience\nExperience with automotive MCU or automotive SoC development.\nExposure to ISO 26262 / functional safety requirements and their impact on test architecture.\nExperience with advanced DFT methodologies such as hierarchical test, embedded compression, logic BIST, repair/redundancy schemes or safety-oriented test features.\nUnderstanding of production test cost, test time, coverage, diagnostic requirements and yield considerations.\nWhat We Are Looking For\nWe are looking for someone who can take technical ownership of DFT, not just execute an established flow. The ideal candidate can make architecture decisions, work hands-on through implementation and verification, anticipate downstream production-test requirements, and effectively connect the design organization with Product and Test Engineering.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Staff /Senior Staff Engineer/Principal – Analog Design Engineer ", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-27T10:56:13.908000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000158013580-staff-senior-staff-engineer-principal-analog-design-engineer-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Looking for an experienced Analog Design engineer to join the 2.6B$ Power Business Unit where in the candidate will get to work on a wide range of exciting products such as Hotswap Contollers, eFuse, IPD’s, PMICs, DC-DC converters and Drivers powering the next generation of automotive power needs.\nEssential Functions:\nExperienced in all aspects of Analog circuit design from block level to full chip with a demonstrated history in driving design innovation and best practices.\nShould have the ability to work independently with little supervision to design complex circuits and take complete ownership to drive all aspects within the committed schedule.\nMust be proficient in transistor level design and system implementation of typical building blocks like charge pumps, comparators, amplifiers, bandgaps, linear regulators, switching regulators etc.\nExperience in leading a team with a proven history of mentoring and promoting new college graduates\nDirect experience in building (concept to market release) power products in any of the desired functions is a big plus.\n\nMinimum Requirements:\nBachelor’s or Master’s degree in Electrical and Computer engineering\n8-15 years in Analog Circuit Design, Simulation,Verification, Hotswap Controller along with IPD’s, PMICs, DC-DC converters\nAdditional Preferred Qualifications\nSolid understanding of IC processing (preferably BCD nodes), packaging and production test along with familiarity with advanced IC CAD tools\nSchematic generation, simulation and verification using modern CAD tools\nFamiliarity with complete simulation suite including block level, top-level, worst-case corner identification and Monte Carlo analysis along with parasitic extraction and simulation.\nSolid understanding of layout care-abouts and identifying limitations of design to testability, debug, characterization and production/yield targets\nMust be a natural team player and strive towards fostering a highly creative and productive working environment\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Validation Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-27T08:59:40.866000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000157990089-validation-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "The Post-Silicon Validation team within the Performance Computing Power Division is building a world-class organization of highly skilled engineers across multiple global sites. Our mission is to push the boundaries of silicon validation for industry-leading integrated circuits enabling high-power, high-efficiency power management systems. \nWe are committed to delivering the highest level of validation quality by continuously improving test coverage, measurement accuracy, repeatability, automation, and execution efficiency while reducing overall validation time. \nAs a Validation Engineer, you will be part of a multidisciplinary global development team and play a key role in ensuring that every new product fully meets its electrical, functional, and performance specifications before release to production. You will work closely with Design, Applications, Product Engineering, Quality, and System teams to identify, debug, and resolve silicon and system-level issues while supporting aggressive product development and New Product Introduction (NPI) schedules. \nFor our office in Bangalore, we are looking for a passionate engineer who thrive on innovation, enjoy solving complex technical challenges, and is committed to delivering high-quality results in a fast-paced environment. \nPrincipal Responsibilities \nValidate analog, digital, mixed-signal, and power management ICs against electrical, functional, and performance specifications. \n\nPrepare advanced laboratory test setups for complex silicon evaluation. \n\nContribute to the design of custom evaluation boards and supporting hardware for silicon characterization. \n\nDevelop measurement scripts using Python. \n\nPerform data acquisition, statistical analysis, result correlation, preparation of detailed technical reports and silicon evaluation summaries. \n\nEvaluate silicon performance at device, board, and system level, identifying, documenting, and tracking silicon and application issues. \n\nCollaborate closely with Design, Applications, Firmware, Product Engineering, and Quality teams to investigate and resolve silicon and system-level bugs. \n\nContribute innovative ideas that enhance validation quality, automation, productivity, and time-to-market. \n\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related discipline with about 2 years of work-related experience. \nGood level of expertise in lab automation, ability to propose improvements to existing measurements techniques. \n\nProficiency with Python programming with particular use for lab automation hardware environments  \n\nBasic knowledge of power management applications in consumer electronic   \n\nBoard level analog and digital circuit design expertise for PCB schematic creation  \n\nStrong analytical and debugging skills with a systematic approach to problem solving. \n\nSelf-motivated, proactive, and able to manage priorities while delivering high-quality results under demanding project schedules. \n\nGoals-oriented and able to deliver on-time results under tight schedules  \n\nExcellent communication skills and ability to collaborate effectively within international cross-functional teams. \n\nImportant \nConcise and precise communication, internal and with customers   \n\nCross cultural awareness and sensitivity within multisite and multicultural environments  \n\nFlexible to undertake occasional international travel  \n\nExcellent command of verbal and written English  \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Verification Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-27T08:39:00+00:00", "url": "https://global-external-amd.icims.com/jobs/93735/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. SENIOR SILICON DESIGN ENGINEER THE ROLE: We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Develop/Maintain tests for functional verification and performance verification at the core level Build testbench components to support the next generation IP Maintain or improve current test libraries to support IP level testing Create hardware emulation build to verify the IP functional performance Maintain and improve current hardware emulation environment to speed up the runtime performance and improve the debug facility Provide technical support to other teams PREFERRED EXPERIENCE: Good at C/C++ Familiarity with SystemVerilog and modern verification libraries like UVM Experience/Background on Computing/Graphics is a benefit Experience with OpenGL/OpenCL/D3D programming is a benefit ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "RTL Design Engineer - PCIE, Ethernet, USB and DDR", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-27T08:20:00+00:00", "url": "https://global-external-amd.icims.com/jobs/93410/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. THE ROLE: We are looking for an adaptive, self-motivatived design engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Design Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Develop/Maintain design and integration for various in-house/vendor IPs, subsystems and SoC. Preferred knowledge on PCIE, DDR, USB, Ethernet. Ensure quality of the IP/Subsystem/SoC through various static QCs viz LINT, CDC, RDC, CLP/VCLP. Develop/Own various constraints like SDC, UPF, etc, Interact with various stakeholders to ensure timing closure and verification robustness of your design. PREFERRED EXPERIENCE: Familiarity with RTL coding and various indistry standard protocols like PCie, AMBA etc. Familiarity with various QC tools/flows and IPXACT. Strong fundamentals of VLSI, FIFO, arbitration techniques etc. ACADEMIC CREDENTIALS: Bachelors or Masters degree in Electronics/VLSI/computer engineering/Electrical Engineering with 5+Yrs of exp #LI-AB1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "RTL Design Engineer - PCIE, Ethernet, USB and DDR", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-27T08:18:00+00:00", "url": "https://global-external-amd.icims.com/jobs/93411/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. THE ROLE: We are looking for an adaptive, self-motivatived design engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Design Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Develop/Maintain design and integration for various in-house/vendor IPs, subsystems and SoC. Preferred experience in PCIE, Ethernet, USB and DDR Ensure quality of the IP/Subsystem/SoC through various static QCs viz LINT, CDC, RDC, CLP/VCLP. Develop/Own various constraints like SDC, UPF, etc, Interact with various stakeholders to ensure timing closure and verification robustness of your design. PREFERRED EXPERIENCE: Familiarity with RTL coding and various indistry standard protocols like PCie, AMBA etc. Familiarity with various QC tools/flows and IPXACT. Strong fundamentals of VLSI, FIFO, arbitration techniques etc. ACADEMIC CREDENTIALS: Bachelors or Masters degree in Electronics/VLSI/computer engineering/Electrical Engineering with 5+Yrs of exp #LI-AB1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Staff/Principal Robotics Validation Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-27T06:46:00+00:00", "url": "https://global-external-amd.icims.com/jobs/94351/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. Staff/Principal Robotics Validation Engineer Join AMD’s PAVS team as a Robotics Developer experience Usecases Validation Engineer where you will Validate and Execute diverse Robotics platforms, variants and customer usecases for advanced robotics systems across software, hardware, and integrated platforms. Your work will ensure safety, reliability, and performance through rigorous testing in simulation, Gazebo, Isaac sim, SIL/HIL environments, and real-world deployments. Key Responsibilities Validation Strategy & Usecases : Define Usecases and execute validation plans for robotics software stacks (perception, planning, control) and hardware subsystems. Validate AI frameworks and runtimes (PyTorch, TensorFlow, ONNX Runtime) Execute and optimize workloads on ROCm/HIP, CUDA, OpenCL, and heterogeneous accelerators Automation & Frameworks: Develop automated test suites for ROS2 nodes, navigation stack (Nav2), and fleet APIs using Python/C++, pytest, gtest/gmock. Simulation & Scenario Testing: Build simulation environments (Gazebo/Ignition, Isaac Sim) for warehouse layouts; author scenarios for obstacle avoidance, dynamic traffic, and multi-robot coordination. SIL/HIL Validation: Set up Software-in-the-Loop and Hardware-in-the-Loop rigs for AMR controllers, LiDAR emulators, and safety sensors; automate provisioning and logging. Sensor QA: Validate LiDAR, depth cameras, IMU, wheel encoders, and odometry accuracy under varying conditions. Navigation & Fleet QA: Test SLAM, localization robustness, path planning, and fleet orchestration (traffic management, task allocation, VDA5050 compliance). Safety & Compliance: Execute safety protocols for AMRs (emergency stop, zone monitoring, speed limits) aligned with ISO 3691-4, ISO 13849, ANSI/RIA R15.06. Performance & Reliability: Measure latency, throughput, and stability under high-load scenarios; validate battery management and docking behaviors. CI/CD Integration: Embed automated tests into pipelines for continuous validation; monitor KPIs like defect escape rate and scenario coverage. Leadership: Act as a strong individual contributor and mentor for robotics validation teams; collaborate with cross-functional stakeholders to ensure customer experience is prioritized. Required Qualifications 12+ years in QA/Validation, with 9+ years in robotics or AMR systems. Strong Python for automation and C++ for ROS2 integration. Hands-on experience with ROS2, Nav2 stack, colcon, and simulation tools (Gazebo/Ignition, Isaac Sim). Expertise in LiDAR, depth cameras, IMU, odometry, and sensor calibration. Familiarity with fleet management systems, traffic control, and VDA5050 protocol. CI/CD experience with GitHub Actions/GitLab CI/Jenkins; Docker-based test environments. Knowledge of functional safety standards for mobile robots (ISO 3691-4, ISO 13849). Preferred Skills Multi-robot coordination, dynamic obstacle handling, and SLAM algorithms. Robotics AMR safety PLCs, zone scanners, and emergency stop circuits. Warehouse automation workflows, WMS integration, and OPC-UA. Performance benchmarking, reliability testing, and telemetry dashboards. Success Metrics Automated coverage of navigation and fleet scenarios. Reduction in field defect escape rate. Stability and reliability under multi-robot deployments. Compliance with safety standards and successful audits. 🎓 Academic Credentials: Bachelor’s or Master’s degree in Robotics, Electronics, Mechatronics, Computer Science, or a related field. #LI-NR1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Staff Engineer Design ", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-10-27T06:01:22+00:00", "url": "https://jobs.infineon.com/careers/job/563808972279623", "is_hardware": true, "platform": "eightfold", "jd_text": "Join our world-class silicon design team and play a key role in developing next-generation semiconductor products. We are looking for an experienced RTL Design Engineer who can drive the complete design cycle from specification to micro-architecture, RTL implementation, and quality sign-off while optimizing for Power, Performance, and Area (PPA). This is an opportunity to work closely with architecture, verification, and implementation teams on cutting-edge SoC/IP development.\n\nYour role\nKey responsibilities in your new role\n\nOwn the RTL design cycle from specification analysis to micro-architecture definition and RTL implementation.\n\nDevelop detailed micro-architecture documents from high-level product specifications.\nTranslate architecture and design requirements into high-quality RTL using Verilog/SystemVerilog.\nCollaborate with architecture teams to review and refine design and micro-architecture proposals.\nDeliver RTL that is functionally correct and optimized for Power, Performance, and Area (PPA).\nDrive RTL quality sign-off activities including Lint, CDC, Synthesis, and CLP checks.\nImplement and review low-power design methodologies using UPF and related power-intent constructs.\nWork closely with verification, physical design, and integration teams to resolve design issues.\nDebug and root-cause functional, synthesis, timing, and low-power challenges.\nEnsure compliance with coding standards and design best practices throughout the development cycle.\nSupport design reviews and provide technical mentorship to junior engineers when required.\n\nYour profile\nQualifications and skills to help you succeed \n\nExperience: 8+ years of RTL Design experience in the semiconductor industry.\n\nEducation: B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, VLSI, or related disciplines.\nStrong experience in converting specifications into micro-architecture and RTL implementation.\nExpert-level proficiency in Verilog and System Verilog.\nHands-on experience with Lint, CDC, Synthesis, and CLP sign-off methodologies.\nStrong understanding of low-power design techniques and UPF constructs.\nGood knowledge of AMBA protocols, including AHB and AXI.\nExperience designing complex digital blocks with a focus on PPA optimization.\nStrong debugging and problem-solving skills across the RTL development lifecycle.\nExcellent collaboration and communication skills with cross-functional engineering teams.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\n\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nKeerthini M H", "jd_status": "stored"}, {"title": "Physical Design  Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-27T05:36:00+00:00", "url": "https://global-external-amd.icims.com/jobs/90056/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. PHYSICAL DESIGN ENGINEER #The Role: We are looking for a motivated and detail-oriented **Physical Design Library Engineer** to join our VLSI backend team. This role sits at the intersection of **library management using CAD supported tools, and AI-driven automation** — playing a critical enabling function for Front End & Back End team. You will own the end-to-end library delivery pipeline — from lib generation to tile owner unblocking — and will actively leverage and develop **AI-powered tools and dashboards** to improve team efficiency and visibility. # Key Responsibilities: Having 4+Years of experience in Physical Design #Library Flow Ownership - Own and execute the **LibBuilder flow** for standard cell and memory library generation - Drive **MemView generation** for memory compiler outputs across multiple PVT corners and process nodes - Maintain library quality and consistency across **NDM, Liberty (.lib), LEF, and timing model** deliverables - Track and manage **PVT corner coverage** — ensure all required corners (SS, FF, TT, low voltage, high temperature) are generated and validated # Cross-Team Coordination - Serve as the primary point of contact for **library-related issues** raised by tile and block owners - Proactively follow up with **internal teams** (design, DFT, timing) and **external teams** (foundry, IP vendors, memory compiler vendors) to resolve library blockers - Unblock tile owners on **NDM / PVT mismatch issues** — diagnose root cause, coordinate fix, and validate resolution - Coordinate with **CAD team** to ensure the latest compiler versions, EDA tool updates, and flow scripts are adopted in a timely manner # Debug and Issue Resolution - Perform **basic to intermediate debug** of library generation failures — identify issues in lib characterization, corner mapping, or MemView configuration - Triage and escalate complex issues to the right teams with clear problem statements and reproduction steps - Maintain a **library issue tracker** — log, prioritize, and close issues with documented root cause and fix #AI Tools and Dashboard Development - Comfortable working with **AI-assisted tools** (Genie, Claude Code, Copilot) for day-to-day productivity — querying, scripting, and automation - Develop, enhance, and maintain **AI-generated dashboards** for library health, flow status, and PVT coverage visibility - Proactively identify opportunities to **automate repetitive library tasks** using AI and scripting ## Knowledge of Physical Design Concepts -Timing concepts -Different file formats, lef/def/oasis Education: Bachelor’s or master’s degree in related discipline preferred #LI-SR5 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "RTL Design (SOC) Engineer-Principal/Manager", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-27T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720863657", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nJob Description\n\nYou will be part of the CSG team focused on Data Center innovation through next-gen architectures for Dragonfly which is Qualcomm's rack-scale Agentic AI platform, reshaping compute efficiency and scalability for the AI era .​\nEducation: Bachelor’s or master’s degree in Electrical or Electronics and Communication or Computer Science Engineering.\n\nExperience: 8+ years of proven experience in SoC development, and full-chip design\n\nExpertise:\nGood understanding of the design convergence cycle, including architecture, micro-architecture, Verification, Synthesis and timing closure.\n\nExpertise in managing IP dependencies, as well as planning front-end design tasks.\n\nDesign and development of high-speed serial IO protocols\n\nImplementation of clock rate compensation FIFO, gearbox design for data width, bypass on controller, power gating, low power modes\n\nSkills:\nExcellent communication and interpersonal skills.\n\nMinimum Qualifications:\nBus Protocols & Peripherals: Strong knowledge of bus protocols such as AHB, AXI, and peripherals like PCIe, USB, Ethernet, etc.\n\nMemory Controllers & Microprocessors: Experience with memory controller designs and microprocessors is an advantage.\n\nTest Plans & Verification: Proficient in reviewing high-level test plans and coverage metrics.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU Design - Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-27T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721778032", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > CPU Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm CPU Engineer, you will lead innovative Central Processing Unit (CPU) design efforts that have a critical impact on industries across the world. Qualcomm Engineers collaborate with cross-functional teams to design, verify, and implement multi-core CPU operations for all Qualcomm Business Units.\n\nMinimum Qualifications:\n•    Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.\n                                                                    OR\nMaster's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.\n                                                                    OR\nPhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.\n•    6+ years of work experience with high-performance microprocessor design.\n•    6+ years of work experience with high level programming (e.g., C, C++), scripting language programming (e.g., Perl, Python, etc.).\n•    6+ years of work experience with simulators and/or waveform debugging tools (e.g., Verilog, VHDL, etc.).\n•    6+ years of work experience with industry standard tools for synthesis place and/or route and design verification.\n•    6+ years of work experience with simulation, emulation, formal verification, or silicon validation.\n•    6+ years of experience in creating functional models, checkers, test plans, and/or test generation.\n•    2+ years experience working in a large matrixed organization.\n•    1+ year of work experience in a role requiring interaction with senior leadership (e.g., Director level and above).\n\nPrincipal Duties and Responsibilities:\n•    Leverages advanced knowledge of computer architecture, micro-architecture, logic design, circuits, and/or physical design to develop and verify high performance and low power CPU designs.\n•    Anticipates, identifies, and solves complex problems to ensure design completeness, functionality, power, and performance. \n•    Collaborates with cross-functional teams to define requirements, specifications, and trade-offs (e.g., performance, power, cost, functionalities, etc.) in order to accomplish product goals.\n•    Evaluates the design process from conceptualization to productization (i.e., architecture definition, feasibility, pre-silicon design and verification, and post-silicon validation) that meet customer and industry standards.  \n•    Writes detailed technical documentation (e.g., feature descriptions, architectural descriptions, verification test plans, and implementation details, etc.) for complex CPU designs.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making is significant in nature and affects work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Has a moderate amount of influence over key organizational decisions.\n•    Tasks do not have defined steps; planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU Design - Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-27T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721778212", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > CPU Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm CPU Engineer, you will lead innovative Central Processing Unit (CPU) design efforts that have a critical impact on industries across the world. Qualcomm Engineers collaborate with cross-functional teams to design, verify, and implement multi-core CPU operations for all Qualcomm Business Units.\n\nMinimum Qualifications:\n•    Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.\n                                                                    OR\nMaster's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.\n                                                                    OR\nPhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.\n•    6+ years of work experience with high-performance microprocessor design.\n•    6+ years of work experience with high level programming (e.g., C, C++), scripting language programming (e.g., Perl, Python, etc.).\n•    6+ years of work experience with simulators and/or waveform debugging tools (e.g., Verilog, VHDL, etc.).\n•    6+ years of work experience with industry standard tools for synthesis place and/or route and design verification.\n•    6+ years of work experience with simulation, emulation, formal verification, or silicon validation.\n•    6+ years of experience in creating functional models, checkers, test plans, and/or test generation.\n•    2+ years experience working in a large matrixed organization.\n•    1+ year of work experience in a role requiring interaction with senior leadership (e.g., Director level and above).\n\nPrincipal Duties and Responsibilities:\n•    Leverages advanced knowledge of computer architecture, micro-architecture, logic design, circuits, and/or physical design to develop and verify high performance and low power CPU designs.\n•    Anticipates, identifies, and solves complex problems to ensure design completeness, functionality, power, and performance. \n•    Collaborates with cross-functional teams to define requirements, specifications, and trade-offs (e.g., performance, power, cost, functionalities, etc.) in order to accomplish product goals.\n•    Evaluates the design process from conceptualization to productization (i.e., architecture definition, feasibility, pre-silicon design and verification, and post-silicon validation) that meet customer and industry standards.  \n•    Writes detailed technical documentation (e.g., feature descriptions, architectural descriptions, verification test plans, and implementation details, etc.) for complex CPU designs.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making is significant in nature and affects work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Has a moderate amount of influence over key organizational decisions.\n•    Tasks do not have defined steps; planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Principal Engineer - Verification", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-10-27", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Principal-Engineer---Verification_R4329-26-7", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nMicrochip Technology Inc. is looking for a self motivated individual to fill the position of Principal Verification Engineer within our WSG product development team. The successful candidate will have the ability to architect and implement robust verification environments for both unit level and full chip verification. Managing complex verification projects and mentoring junior level engineers will be an integral part of this position.\n\nKey Responsibilities:\n\n1. Develop an effective suite of tests and test environments using a mix of class based SystemVerilog and C based directed tests to achieve predefined functional verification goals.\n2. Actively participate in a team environment, working with verification, architecture, applications, and design teams to develop comprehensive verification plans and address issues.\n3. Own and drive verification related activities, provide technical support, and proactively manage tasks to meet schedule goals.\n4. Help define and develop effective functional assertions and cover points.\n5. Verify structural and functional coverage of module and system level test suite.\n\nRequirements/Qualifications:\n\n1. BSEE minimum with at least 7 years experience in the verification of large, complex IP and ICs.\n2. Experience in project management and leadership of small teams.\n3. Understanding of Microcontroller architectures and products.\n4. Hands on experience with Questa or similar advanced simulation tools.\n5. Advanced skills in various programming languages such as Verilog, System Verilog, C, C++, PERL\n6. Working experience using an industry standard verification methodology (UVM/AVM/VMM).\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Principal Engineer-Design (SoC Integration and RTL/IP)", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-10-27", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Principal-Engineer-Design--SoC-Integration-and-RTL-IP-_R4513-26-2", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nJThe dsPIC microcontroller group is seeking an experienced SoC Integration, RTL/IP Design, and FPGA Engineer to lead SoC integration, RTL development, IP design, and FPGA prototyping activities. The candidate will work closely with architecture, verification, and physical design teams to deliver high-quality hardware solutions.\n\nKey Responsibilities\nSoC Integration\nPerform top-level and subsystem integration of processors, memories, peripherals, and custom IPs.\nIntegrate IPs using proprietary bus interfaces and AMBA AXI, AHB / APB protocols.\nHandle clock/reset integration, interrupt routing, address mapping, and pad / pin connectivity.\nResolve chip-level Lint / Synthesis / Timing issues perform CDC / RDC analysis and implement relevant fixesOwnership of post-silicon debug and ECO revisions of the chip\nRTL and IP Design\nDevelop synthesizable RTL using SystemVerilog.\nDesign reusable peripherals, controllers (for memories, ADCs, PWMs), wrappers, and power management modules.\nResolve Lint / Synthesis / Timing issues; resolve CDC / RDC errors\nPerform RTL reviews, synthesis support, timing optimization, and design debug.\nMaintenance, enhancements and management of older IP\nTechnical Leadership\nCollaborate with architecture, verification, DFT, physical design, firmware, and system teams.\nLead design reviews, mentor junior engineers, and drive technical improvements\nHelp with key decisions related to IP and product definition and implementation\n\nRequirements/Qualifications:\n\nRequired Skills\nBachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, Physics, or a related field with 10+ years of experience in ASIC/SoC design, RTL development, FPGA, or SoC integration.\nStrong knowledge of SystemVerilog and AMBA AXI/AHB/APB protocols.\nExperience with SoC integration, IP development, clock/reset architecture, and memory mapping.\nHands-on experience with Vivado or Quartus, synthesis, STA, and timing closure.\nFamiliarity with simulation tools such as QuestaSim, VCS, or Xcelium.\nKnowledge of CDC/RDC, RTL lint, and Python/Tcl scripting.\n \nPreferred Qualifications\nExperience with ARM/RISC-V-based SoCs, Ethernet, USB, SPI, I2C, and UART interfaces.\nKnowledge of low-power design, DFT integration, and Formal-based verification.\nExperience with FPGA synthesis, place and route, timing closure, constraint development and FPGA-based validation.\nBachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field.\n \nExpected Deliverables\nIntegrated SoC/subsystem RTL and reusable IP modules.\nFPGA implementation and validation results.\nDesign quality reports and integration documentation.\n \nRole Expectation: Independently drive SoC integration, IP design, and FPGA prototyping while providing technical leadership and ensuring robust, reusable hardware designs.\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Sr Staff Static Timing Analysis (STA) Lead", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-10-27", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Senior-Staff-Physical-Design-Architect--Flow---ML-Automation-_R-101081", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nAbout the Role:\n\nWe are seeking a highly experienced STA Engineer to serve as the primary technical authority and owner for all timing-related aspects of our next-generation, high-speed data center scale CPUs. In this role, you will define sign-off criteria, drive advanced timing methodologies, and spearhead innovation to accelerate timing closure for massive, high-performance compute architectures at cutting-edge process nodes (N3/N2).\n\nKey Responsibilities\nTechnical Leadership: Act as the primary point of contact and subject matter expert for all STA and timing-related items across the high-speed CPU design team.\nMethodology Innovation: Develop and deploy \"correct-by-construction\" methodologies to proactively drive timing convergence early in the design cycle.\nPlatform Development: Architect and maintain advanced tracking platforms to monitor and analyze timing convergence metrics across complex data center CPU blocks.\nConstraint Management: Lead SDC quality assurance. Collaborate closely with cross-functional partners to ensure pristine, high-quality SDCs through our internal flows\n\nRequired Qualifications\nTiming Signoff & Tools: Deep, authoritative understanding of the complete Timing Signoff process (defining criteria, margins, and closure). Expertise in Synopsys PrimeTime is a must.\nAdvanced Node Experience: Proven, hands-on experience taping out complex designs at the 3nm (N3) process node.\nPhysical Design Flow: Strong working knowledge of the physical design flow, specifically transitioning from Synthesis through Place and Route (P&R).\nSDC Proficiency: Extensive experience in developing, managing, and debugging complex SDCs for massive SoC or CPU designs.\nAdvanced Clocking: Strong understanding of Clock Tree Synthesis (CTS) architectures, including Mesh and Multi-Source CTS (MSCTS).\nEducation Qualification: A bachelor's or master's in E&E, ECE, CS, VLSI, or PhD is required with 10+ years of experience.\n\nPreferred Qualifications\nHigh-Performance Compute: Direct, proven experience driving timing closure specifically for high-speed, data center scale CPUs.\nNext-Gen Nodes: Exposure to or active experience with 2nm (N2) technology nodes is highly preferred.\nAdvanced EDA Tools: Hands-on experience with Synopsys FusionCompiler is highly preferred.\nAI/ML Integration: Knowledge of Machine Learning (ML)-based timing prediction techniques to reduce design iterations and accelerate sign-off cycles.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Senior Engineer - CPU Verification (RISCV Vector,ALU, FPU Verification)", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-10-27", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Senior-Engineer---CPU-Verification--RISCV-Vector-ALU--FPU-Verification-_R-101489", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nResponsibilities\nOwn verification planning and execution for Vector, ALU, floating-point blocks from testplanning to unit level verification and integration to core level.\n\nDrive verification strategy, test planning, Testbench development, tests writing, debug, coverage analysis, and closure for complex Vector, ALU, FPU execution-pipeline and datapath behaviours.\n\nDefine effective verification approaches for arithmetic, floating-point, operand dependency, bypass/forwarding, replay, flush/recovery, exception, and execution-to-commit interactions.\n\nDevelop robust verification environments, assertions, checkers, scoreboards, stimulus, and coverage models that expose corner cases and improve bug-finding efficiency.\n\nPartner closely with architecture, design, and verification teams to review specifications, identify risk early, and improve verification completeness.\n\nDrive efficient root-cause debug across specification, RTL, tests, and verification infrastructure.\n\nContribute reusable methodology, automation, and infrastructure that improve verification quality and productivity across future CPU core programs.\n\nMinimum Qualifications\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\n\n4+ years of relevant experience in ASIC, CPU/core, or SoC design verification.\n\nStrong hands-on experience with SystemVerilog, UVM -based verification and modern verification methodologies.\n\nSolid understanding of computer architecture and CPU microarchitecture.\n\nExperience verifying one or more of the following areas: ALU pipelines, floating-point execution, datapath verification, formal verification, issue/dispatch behavior, dependency handling, forwarding, replay, or exception handling.\n\nStrong knowledge of verification flow methodology, including test planning, stimulus generation, debug, coverage analysis, and coverage closure.\n\nGood scripting or programming skills in Python, C/C++, or similar languages used for DV infrastructure and automation.\n\nPreferred Qualifications\nExperience with high-performance out-of-order CPU core verification.\n\nExperience developing high-value assertions, checkers, and scoreboards for control-heavy or dependency-sensitive CPU behavior.\n\nExperience applying formal verification to execution logic, control interactions, or datapath correctness.\n\nExperience collaborating effectively across architecture, design, performance, and verification teams.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Senior Engineer - CPU Verification (ALU, FPU Formal and Datapath Verification)", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-10-27", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Senior-Engineer---CPU-Verification--ALU--FPU-Formal-and-Datapath-Verification-_R-101488", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nResponsibilities\nOwn verification planning and execution for ALU, floating-point blocks focussing on formal and datapath verification of these blocks.\n\nDrive verification strategy, test planning, debug, coverage analysis, and closure for complex Vector, ALU, FPU execution-pipeline and datapath behaviours.\n\nDefine effective verification approaches for arithmetic, floating-point, operand dependency, bypass/forwarding, replay, flush/recovery, exception, and execution-to-commit interactions.\n\nDevelop robust verification environments, assertions, checkers, scoreboards, stimulus, and coverage models that expose corner cases and improve bug-finding efficiency.\n\nPartner closely with architecture, design, and verification teams to review specifications, identify risk early, and improve verification completeness.\n\nDrive efficient root-cause debug across specification, RTL, tests, and verification infrastructure.\n\nContribute reusable methodology, automation, and infrastructure that improve verification quality and productivity across future CPU core programs.\n\nMinimum Qualifications\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\n\n4+ years of relevant experience in ASIC, CPU/core, or SoC design verification.\n\nStrong hands-on experience with SystemVerilog-based verification and modern verification methodologies.\n\nSolid understanding of computer architecture and CPU microarchitecture.\n\nExperience verifying one or more of the following areas: ALU pipelines, floating-point execution, datapath verification, formal verification, issue/dispatch behavior, dependency handling, forwarding, replay, or exception handling.\n\nStrong knowledge of verification flow methodology, including test planning, stimulus generation, debug, coverage analysis, and coverage closure.\n\nGood scripting or programming skills in Python, C/C++, or similar languages used for DV infrastructure and automation.\n\nPreferred Qualifications\nExperience with high-performance out-of-order CPU core verification.\n\nExperience developing high-value assertions, checkers, and scoreboards for control-heavy or dependency-sensitive CPU behavior.\n\nExperience applying formal verification to execution logic, control interactions, or datapath correctness.\n\nExperience collaborating effectively across architecture, design, performance, and verification teams.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "EDA Tools License Management", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-27", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/EDA-Tools-License-Management_JR0286863", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nManages EDA license operations, governance, compliance, and optimization to ensure reliable access to critical design tools across hardware engineering teams. Defines and executes license management processes for major EDA suppliers, including entitlement tracking, usage analysis, cost optimization, audit readiness, and contract compliance. Addresses complex compliance challenges such as reconciling supplier entitlements against actual tool usage, preventing over-deployment or unauthorized access, validating geographic and business-unit usage restrictions, managing license transfers during reorganizations or divestitures, ensuring usage-reporting accuracy, and preparing defensible documentation for supplier audits. Required to migrate the license environment to SLES15, ensuring testing of end users' scripts and automation workflows to improve license visibility, reduce manual effort, and enable data-driven decision-making. Partners with design, contract manager, procurement, finance, legal, IT, and EDA vendors to support tool enablement, license planning, renewal strategy, and business continuity. Builds deep understanding of EDA tool usage, licensing models, supplier agreements, and operational controls to ensure scalable, compliant, and cost-effective license management across technology programs.\n\nQualifications:\nMinimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.\n\nMinimum Qualifications:\n\n• 4-12 years of Experience managing EDA license operations, license servers, vendor daemons, or engineering tool infrastructure.\n• Working knowledge of EDA licensing models, entitlement tracking, usage analysis, renewals, and supplier compliance.\n• Experience supporting audits, entitlement reconciliation, usage validation, and compliance documentation.\n• Ability to analyze license data, identify optimization opportunities, and communicate risks or recommendations to stakeholders.\n• Experience partnering with design, procurement, contract management, finance, legal, IT, and suppliers.\n• Experience with FlexNet/FLEXlm, Linux/SLES license environments, vendor daemon upgrades, or license migrations.\n*Experience in Linux and Unix.\n\nPreferred Qualifications:\n\n• Experience with major EDA suppliers such as Synopsys, Cadence, Siemens EDA, Ansys, Keysight, or Arm.\n• Experience building dashboards, databases, scripts, or automation for license visibility, usage monitoring, compliance, or renewals.\n• Knowledge of complex licensing models, including token-based, named-user, geographic, business-unit, cloud, or royalty-based licensing.\n• Ability to translate license data into executive summaries, risk assessments, and supplier negotiation inputs.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Analog Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-27", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Analog-Design-Engineer_JR0286977", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nAs an Analog Circuit Design Engineer, you will play a critical role in designing, developing, and optimizing cutting-edge analog and mixed-signal circuits in advanced process nodes. Your expertise will contribute directly to Intel's mission of driving innovation and delivering high-performance, power-efficient, and scalable IP solutions. Joining our team, you'll engage in solving complex technical challenges, collaborate cross-functionally, and influence Intel's success in the semiconductor industry. This role offers you the opportunity to work on groundbreaking technologies that shape the future of computing and communication systems.\n\nKey Responsibilities\n- Design, develop, and optimize analog circuits, including analog behavior models, GPIO, PLLs, LDOs and ADCs for industry-leading IPs.\n- Perform floor planning, circuit design, and parameter extraction, ensuring robust functionality and adherence to microarchitecture specifications.\n- Simulate and verify designs to optimize circuit performance, power, area, timing, and yield goals.\n- Create and execute detailed test plans to verify circuit functionality and evaluate results based on performance metrics.\n- Collaborate with architecture and layout teams to design circuits that maximize robustness, electrical capabilities, and functionality.\n- Analyze, track, and resolve performance issues, ensuring designs meet power and electrical specifications.\n- Report design progress and contribute to cross-functional collaboration for timely delivery of high-quality solutions.\n- Work towards reducing leakage and optimizing power, performance, and area of circuits across multiple projects.\n\nQualifications:\nMinimum Qualifications\n- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; or equivalent experience per business needs.\n- 12+ years of experience in analog circuit design with a Bachelor's degree, or 12+ years with a Master's degree.\n- Proficiency in CMOS technologies, circuit simulation, circuit testing, and analog fundamentals.\n- Expertise in analog behavior modeling, analog power circuits, and analog electronics.\n- Technical knowledge of LDO, clocking circuits and analog to digital converters.\n\nPreferred Qualifications\n- Strong problem-solving abilities and attention to detail in optimizing performance, power, and area metrics.\n- Excellent communication and collaboration skills to work effectively in cross-functional teams.\n- Demonstrated ability to handle complex circuit design challenges in advanced process nodes.\n- Passion for innovation and commitment to delivering high-quality designs that align with Intel's core values and goals.\n\nTake this opportunity to be part of Intel's world-class engineering team. Apply today and help shape the future of technology.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Physical Design Automation Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-27", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Physical-Design-Automation-Engineer_JR0288534", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Design Technology Platform team at Intel Foundry India is chartered with process technology definition, advanced methodology development, and design prototyping on Intel's latest process nodes. We support Intel's internal and external design customers and offer a unique opportunity to be among the first engineers working on cutting-edge process technologies.\n\nWe are seeking an experienced Technical Lead - APR Design Automation to develop and optimize RTL-to-GDS (R2G) flows primarily using Cadence Innovus Implementation System, while supporting test chip and foundry IP needs. The ideal candidate will bring deep expertise in Cadence Innovus-based PnR flow development, with working knowledge of Synopsys Fusion Compiler being a strong added advantage. A key aspect of this role will be enabling, deploying, and supporting Cadence Innovus-based APR flows for Intel's internal product design teams as well as external foundry customers who are leveraging Intel's process technology - ensuring robust, scalable, and production-ready flow solutions that meet the design and performance requirements across a diverse customer base.\nThis is an individual contributor (IC) technical leadership role focused on physical design automation tools, flows, and methodologies on leading-edge process nodes.\n\n•\tLead the development, deployment, and continuous improvement of RTL-to-GDS flows using Cadence Innovus as the primary PnR platform\n•\tDefine and drive physical design tools, flows, and methodologies including:\no\tBlock-level implementation and integration\no\tFloorplanning, placement, CTS, and routing automation\no\tTiming closure methodologies\n•\tDevelop and maintain Tcl-based scripting and automation to enhance layout productivity within Innovus and related Cadence tools\n•\tEvaluate and benchmark Cadence Innovus vs. Synopsys Fusion Compiler flows; provide data-driven recommendations on tool and methodology selection\n•\tEnable and support industry-standard static timing analysis (STA) tools for test chips and Foundry IPs (FIPs), and ensure continued support and enhancement\n•\tCollaborate with central CAD, design teams, local CAD teams, and EDA vendors (Cadence, Synopsys) to define next-generation PnR methodologies\n•\tWork closely with internal and external design customers to understand requirements and deliver robust, scalable automation solutions\n•\tRespond to customer/client requests proactively, developing solutions leveraging formal expertise and engineering judgment\n•\tContribute to process node bring-up by validating and refining flows on Intel's latest technology nodes\n\nQualifications:\nEducational Requirements\nMaster's degree in M.Tech or MS in Microelectronics, Electronics Engineering, or an equivalent qualification from a reputed institute, with relevant industry experience in physical design and APR flow development\nTechnical Qualifications\nPhysical Design and APR Expertise\nProven hands-on experience in block-level design closure using Cadence Innovus Implementation System as the primary APR tool for end-to-end RTL-to-GDS flows\nStrong working knowledge of all key physical design stages including Floorplanning covering die size estimation, macro placement and pin assignment, Power Planning covering power grid design, IR drop awareness, ring and stripe strategies, Placement covering timing-driven and congestion-aware placement optimization, Clock Tree Synthesis covering clock tree design, skew and latency optimization, and Routing covering global and detailed routing and DRC-clean routing closure\nWell-versed with multiple optimization techniques available in Cadence Innovus for achieving design closure, including timing, area, power, and congestion optimizations\nAbility to guide and mentor the team in resolving complex implementation challenges and providing structured solutions\nTiming and Constraints\nStrong understanding of digital timing concepts including setup, hold, clock domain crossing CDC, and multi-mode multi-corner MMMC analysis\nAbility to analyze and validate design constraints SDC and understand their impact on timing closure\nExperience with industry-standard STA tools such as Cadence Tempus or equivalent for timing sign-off\nLayout Closure and Sign-off\nDemonstrated experience in achieving full layout closure for blocks, ensuring compliance with DRC Design Rule Check, LVS Layout vs. Schematic, Density requirements and Antenna violation fixes\nFamiliarity with physical verification tools and sign-off flows as per process technology specifications\nTop-Level Integration\nGood understanding of top-level integration challenges and ability to ensure block-level deliverables meet project-level requirements for both timing and layout closures\nExperience in managing block-to-top handoffs and resolving integration-level issues effectively\nDomain Knowledge\nStrong foundation in VLSI design, digital electronics, and semiconductor device fundamentals\nGood understanding of digital design timing closure principles and methodologies\nKnowledge of semiconductor fabrication and process technology will be a distinct added advantage\nFamiliarity with Intel process technology or advanced node design environments is a plus\nSoft Skills and Behavioral Competencies\nStrong analytical and problem-solving skills with a structured approach to debugging complex physical design issues\nProactive and transparent communication style with the ability to articulate technical challenges and solutions clearly to stakeholders\nCollaborative mindset with demonstrated ability to work effectively in a diverse, cross-functional, and geographically distributed team environment\nAbility to work across multiple domains including design, CAD, and EDA vendor teams\nLeadership and Experience\nLeadership experience in driving block-level closure and physical design sign-off for tape-out is strongly preferred\nDemonstrated track record of silicon success having contributed to or led designs that have been successfully taped out and validated in silicon is highly desirable\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Senior Field Applications Engineer", "company": "Lattice", "location": "Taipei, Taiwan", "date_posted": "2026-10-27", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Taipei-Taiwan/Staff-Field-Applications-Engineer_R-101110-1", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\n\nWe are seeking a technically strong and customer-oriented Field Application Engineer (FAE) to support Lattice FPGA solutions. In this role, you will engage directly with customers to enable successful design-in and deployment of Lattice FPGA products. You will act as a bridge between customers, sales, and R&D, providing both pre-sales technical guidance and post-sales design support.\nYou’ll work directly with customers to enable platform security, root of trust, and secure system design for next-generation servers and data centers.\n\nKey Responsibilities\nProvide technical support to customers throughout the design cycle with a focus on Lattice FPGA solutions.\nConduct product evaluations, proof-of-concept designs, and demos showcasing Lattice FPGAs.\nGuide customers through the Lattice design flow using Radiant, Diamond, Propel, or other Lattice toolchains.\nDeliver technical presentations, training, and workshops on Lattice solutions (e.g., LTPI, MPESTI, Security/Root-of-Trust solutions).\nWork with customers on embedded system integration, including FPGA, processors, and interfaces.\nTroubleshoot timing closure, simulation, and board-level integration issues.\nProvide feedback to product and R&D teams on customer requirements and emerging application trends.\n\nJob Requirements\n\nEducation & Background\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.\n5+ years of FPGA development, technical support, or FAE experience.\n\nTechnical Skills\nHands-on experience with FPGA design flow: RTL coding (Verilog/VHDL/SystemVerilog), synthesis, simulation, and debugging.\nStrong knowledge of Lattice toolchains (Radiant, Diamond, Propel, Lattice Programming Cable tools).\nUnderstanding of standard interfaces such as I²C, SPI, SGPIO, LTPI and eSPI.\nExperience with embedded systems and software integration is a Plus.\nLab skills with oscilloscopes, logic analyzers, and FPGA prototyping boards.\n\nSoft Skills\nExcellent problem-solving and debugging skills.\nStrong presentation and communication abilities to engage customers effectively.\nAbility to work cross-functionally and manage multiple customer projects.\nWillingness to travel for customer support, training, or technical meetings.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nTaiwanLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Lead Product Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-10-27", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Product-Engineer_R55323", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Description\nCadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.\n \nThe Cadence Advantage\nThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.\nCadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.\nThe unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success\nMultiple avenues of learning and development available for employees to explore as per their specific requirement and interests\nYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.\n \n \nRole Overview:\nWork closely with R&D and drive timing signoff and ECO for advanced SoCs using industry-standard tools such as Tempus/Certus. Contribute to advanced-node enablement and emerging AI-driven workflows.\n Key Responsibilities:\n- Perform static timing analysis across MMMC scenarios (block and full-chip)\n- Debug setup/hold violations, SI, and variation-related issues\n- Drive timing closure using PBA/GBA and advanced derating techniques\n- Implement physical-aware timing ECOs and optimize PPA\n- Perform STA vs SPICE correlation and improve signoff accuracy\n- Support foundry enablement and technology node bring-up (5nm, 3nm, 2nm)\n- Collaborate with cross-functional teams including P&R, CAD, and Foundry\n- Develop automation using Tcl/Python for timing workflows\n AI / Automation (Preferred):\n- Basic understanding of AI/LLM concepts\n- Exposure to CLI-based infrastructure and automation\n- Interest in intelligent workflow automation and agent-based solutions\n \nQualifications:\n- B. Tech / M. Tech / PhD in Electrical/Electronics Engineering\n- 4–6 years of experience in STA and timing closure\n- Strong hands-on experience with PrimeTime and Tempus\n- Solid understanding of MMMC, OCV/AOCV/SOCV, LVF\n \nPreferred Skills:\n- SPICE simulation and correlation experience\n- Strong debugging skills in large SoC environments\n- Python/Tcl scripting expertise\n- Experience with advanced nodes and foundry interactions\n \nWhy Cadence:\n- Work on industry-leading signoff tools\n- Collaborate with top semiconductor and foundries\n- Drive innovation in AI-enabled STA flows\n- Contribute to next-generation chip tapeouts and methodology building\nBehavioral skills required\n \nDemonstrate adaptability in a fast-paced environment, showing resilience in the face of challenges and maintaining a positive attitude.\nExhibit a strong commitment to continuous learning and professional development, staying abreast of industry trends and technologies.\nFoster a collaborative team environment by being approachable and supportive.\nDisplay a proactive approach to problem-solving, taking initiative, and anticipating potential issues before they arise.\n \nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Staff/Senior Staff Physical Verification CAD engineer", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-10-27", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Staff-Senior-Staff-Physical-Verification-CAD-engineer_2605103", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nWe are seeking a highly skilled and experienced Senior Staff Level Physical Verification CAD Engineer to join our dynamic team in Bangalore, India. The ideal candidate will have a deep understanding of the physical verification process in the context of semiconductor design and manufacturing. This role involves working closely with design and layout teams to ensure the integrity and performance of Marvell's advanced semiconductor products.\nWhat You Can Expect\n​Develop run sets for nanotechnology and support Calibre, ICV and provide user support for DRC and LVS debugging to streamline physical verification flow. Automate and support physical verification flow for internal design tools group. Support tape-out and design-related foundry interface activities, physical verification CAD flow, and CAD flows for SOC integration. Develop and maintain validation procedures for physical verification flow and prepare user guides and documents. Job duties include some usage of full custom layout tools to review results and create validation test cases.\n\nCAD and EDA Tool Development: Develop and maintain advanced CAD and EDA tools and methodologies for digital and analog IC design, verification, and physical implementation.\n\nTool Integration: Integrate various EDA tools into an efficient and cohesive design flow, ensuring seamless interoperability and maximizing design productivity.\n\nMethodology Development: Define and optimize design methodologies, flows, and best practices for efficient and reliable chip design, from  physical verification to SoC tapeout\n\nDesign Automation: Automate design tasks, including physical verification flow, design rule decks, automate layout migration, to improve design efficiency and reduce time-to-market.\n\nTool Evaluation and Selection: Evaluate and select third-party EDA tools, libraries, and IPs to meet project requirements, considering performance, scalability, and cost-effectiveness.\n\nCollaboration and Support: Collaborate with cross-functional teams, including, foundry engineers, design engineers, layout designers, and software developers, to provide technical guidance, support, and training on CAD and EDA tools and methodologies.\n\nTool Performance and Maintenance: Monitor and optimize tool performance, addressing any issues or bottlenecks, and ensuring tool reliability, stability, and usability across design projects.\n\nIndustry Awareness: Stay up-to-date with the latest advancements in CAD and EDA tools, methodologies, and industry trends, and provide recommendations on incorporating new technologies to enhance design capabilities.\n\nDocumentation and Training: Create and maintain comprehensive documentation, user guides, and training materials for CAD and EDA tools and methodologies, enabling efficient knowledge transfer and onboarding of new team members.\n\nWhat We're Looking For\nBachelor’s/Master's degree in Computer Science, Electrical Engineering or related fields with 5 to 12 years of related professional experience.\nA minimum of 5 years of experience in CAD and EDA tool development and support, preferably within the semiconductor industry.\nCAD and EDA Expertise: In-depth knowledge and hands-on experience with industry-standard EDA tools and methodologies for digital and analog IC design, verification, and physical implementation. Proficiency with tools such as Cadence, Synopsys, Mentor Graphics, and scripting languages like Tcl, Perl, Python. Synopsys ICV is required, and Mentor Calibre svrf / tvf is preferred.\nDesign Flow: Strong understanding of the complete IC design flow, from front-end design (RTL, synthesis, simulation) to back-end physical implementation (place and route, timing analysis, physical verification).\nProblem-solving Skills: Demonstrated ability to analyze complex design and tool-related issues, propose innovative solutions, and drive them to completion.\nTeam Collaboration: Excellent interpersonal and communication skills, with a collaborative mindset and the ability to work effectively with cross-functional teams.\nLeadership: Proven experience in leading projects or initiatives, providing technical guidance, and mentoring junior engineers.\nContinuous Learning: Strong motivation for staying abreast of the latest advancements in CAD and EDA tools and methodologies, and a passion for innovation and continuous improvement.\n\nThis role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.\nAdditional Compensation and Benefit Elements\nWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\n\nInterview Integrity \nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\n\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\n\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n\n#LI-CP1", "jd_status": "stored"}, {"title": "Principal Engineer, DFT", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-10-27", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Principal-Engineer--DFT_2602930", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nAs a Principal Engineer-DFT with Marvell, you’ll be a member of the Connectivity business group. Connectivity solutions from Marvell help customers address the growing demands of AI, cloud computing, edge computing, 5G networks, and next-generation data centers. Engineers within the Connectivity Business Unit work on cutting-edge silicon design, firmware, software, system validation, and platform development, collaborating across global teams to deliver products that connect billions of devices and accelerate digital transformation.\n\nJoining the Connectivity Business Unit offers the opportunity to work on complex technical challenges, influence next-generation connectivity technologies, and contribute to products deployed at global scale.\nWhat You Can Expect\nDefine and drive DFT architecture and implementation strategies for complex SoC/ASIC designs.\n\nDevelop and implement scan, compression, MBIST, and other DFT features to achieve test coverage and manufacturing quality goals.\n\nExecute and support scan insertion, DFT verification, and ATPG flows.\n\nCollaborate closely with RTL, verification, physical design, timing, and product engineering teams throughout the design lifecycle.\n\nCreate and maintain DFT-related timing constraints and signoff requirements.\n\nPerform DFT timing analysis and debug timing-related issues.\n\nDrive DFT methodology improvements and contribute to flow automation.\n\nProvide technical leadership and mentorship to junior engineers.\n\nWhat We're Looking For", "jd_status": "stored"}, {"title": "Staff Engineer - DFT", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-10-27", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Staff-Engineer---DFT_2605126", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nAs a part of the Connectivity BU DFT and Timing team the suitable candidate will work on all aspects of DFT/STA in products catering to the networking domain that spans copper and optical products: Timing Constraints development, Timing modes / technology library infrastructure set up, DFT architecture and Testability strategy, Timing and DFT Flow definition, Implementation, DFT / STA Verification and post-Si bring up.\nYou'll work closely with other DFT / STA team members for DFT features Implementation, Integration and Verification in SoC. You will also have close interaction with Logic Design/Physical design/STA/ATE teams as needed.\nWhat You Can Expect\nThe candidate Marvell is looking for will have:\nVery good knowledge on SCAN/ATPG/JTAG/MBIST\nGood knowledge about running tile level and chip level STA flows\nExperience with one or more chip tapeout that included full timing closure responsibility\nProven experience on gate level simulations with notiming and SDF based simulations for DTT modes\nProven experience on Test structures for DFT, IP Integration, ATPG Fault models, test point insertion, coverage improvement techniques\nProven experience in Scan insertion techniques at block level and Chip top level\nGood knowledge on Test mode timing constraints\nCross domain knowledge to resolve DFT issues with design, synthesis, Physical design, STA team\nProficiency in Industry standard Tools for Scan insertion, ATPG, MBIST and JTAG. (Preferably Synopsys/Mentor tools)\nGood Knowledge and understanding on JTAG for IEEE1149.1/6 standards\nExperience with Post-Si ramp up and debug on ATE\nGood hands on experience on Memory BIST generation, Insertion, verification on RTL/Netlist level\nGood knowledge on Perl/ Tcl scripting skills.\nVery good team player capabilities and excellent communication skills to work with a variety of teams across the global organization\nHigh sense of responsibility and ownership within the team for successful Tapeout and Post -Si ramp up of the project\n\nWhat We're Looking For\nBachelor's degree in Computer Science, Electrical Engineering or related fields and 6 years of related professional experience in DFT.\n\nThis role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.\nAdditional Compensation and Benefit Elements\nWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\n\nInterview Integrity \nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\n\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\n\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n\n#LI-RV1", "jd_status": "stored"}, {"title": "Design Engineer, Digital IP", "company": "NXP", "location": "Bangalore", "date_posted": "2026-10-27", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Design-Engineer--Digital-IP_R-10067376", "is_hardware": true, "platform": "workday", "jd_text": "Join a highly experienced R&D team dedicated to developing Intellectual Property (IP) for advanced microcontrollers and microprocessors. This team focuses on creating a networking switch and network controller IP core (NETC) that supports the latest TSN standards, forming the networking foundation for NXP's latest microcontrollers, processors, and switches. The IP developed by this team underpins a product portfolio generating billions of USD in annual revenue. The chips you help develop are likely found in the car you drive, the smart devices in your home, and the factories producing the goods you use.\n\nJob Description\n \nWe are seeking a highly motivated Design  Engineer with a relentless drive to excel and make a significant impact. Our team offers innovative thinking, engineering expertise, and sustained market leadership in embedded processing. By joining us, you will work with the advanced platforms that NXP delivers to major players in the automotive, industrial, edge, and telecommunication markets, featuring multiple processing cores and high-performance networking accelerators integrated on the same silicon chip.\n \nResponsibilities:\nVerify breakthrough Ethernet/networking IP to be integrated into next-generation SoCs for automotive, industrial, and edge computing markets.\nResponsible for the architecture, design, and implementation of hardware IP Design & System on Chip (SoC) products.\nPerform thorough trade-off analysis on performance and complexity.\nWork closely with IP architecture, design, and verification teams on planning and execution to ensure the IP is delivered on time and with the highest quality.\nProduce quality documentation for all phases of the project, including detailed IP functional and implementation specifications.\nDebug test failures to determine the root cause; work with architect and design engineers to resolve defects and correct issues\nProactively drive continuous improvement in design and verification methodology.\n \nJob Qualifications:\n2+ years of experience in IP & System on Chip (SoC) products.\nThorough knowledge and expertise in RTL coding, Digital logic design\nStrong understanding of IP & SoC development methodology and proficiency in verification tools.\nStrong Experience in EDA tools and scripting (Python, TCL, Perl, Makefile, Shell) used to build tools and flows for verification environments\nExperience with revision control systems like Git\nFamiliarity with hardware and software implementation trade-offs.\nFocus on quality results with proven problem-solving abilities.\nAlgorithm development experience.\nStrong interpersonal, communication, and documentation skills.\nDynamic team player.\nBachelor's degree in Computer Science, Engineering, or a related field.\n\nMore information about NXP in India...\n\n#LI-7013", "jd_status": "stored"}, {"title": "Senior DFT Designer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-10-27", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Senior-DFT-Designer_R-10067423", "is_hardware": true, "platform": "workday", "jd_text": "Job Summary\n \nSeeking an experienced Senior DFT Designer to contribute to the development of cutting-edge mixed-signal and digital integrated circuits. This role involves responsibility for designing, implementing, and verifying DFT architectures for complex SoCs working closely with RTL, physical design, verification, product and test teams to ensure robust testability and high-quality silicon.\n \n \nJob Responsibilities\n \nLead and execute the full DFT design flow, including specification definition, architectural design, RTL coding (Verilog/SystemVerilog), synthesis, static timing analysis (STA), verification.\nDevelop and integrate scan insertion, test compression, and ATPG patterns.\nImplement memory BIST strategies.\nCollaborate closely with digital, analog, mixed-signal, product, test and software teams.\nCollaborate with RTL and physical design teams for DFT insertion and timing closure.\nDevelop and implement innovative DFT architectures and design methodologies to meet challenging performance, power, area and quality targets.\nOptimize test coverage, pattern count and test time.\nPerform comprehensive DFT verification at RTL and gate level.\nWork with ATE teams for test program development and silicon bring-up.\nParticipate in post-silicon validation and debug activities, identifying and resolving issues to ensure product quality.\nMentor junior engineers, provide technical guidance, and contribute to continuous improvement of DFT design processes and methodologies.\nGenerate detailed design documentation, including specifications, test plans, and design reviews.\nStay abreast of industry trends, emerging technologies, and best practices in digital IC design.\n \nRequirements\n \nBachelor or master degree in microelectronics, ECE or related\nStrong expertise in DFT methodologies: Scan, MBIST, LBIST, JTAG.\nHands-on experience with industry standard ATPG tools.\nProficiency in UPF/CPF-based low-power DFT.\nKnowledge of fault models (stuck-at, transition, path delay).\nFamiliarity with physical design constraints for DFT.\nExperience in silicon debug and ATE bring-up\nKnowledge of Verilog, SystemVerilog, VHDL\nStrong commitment to schedule and quality, a good team player\n\nMore information about NXP in India...\n\n#LI-9415", "jd_status": "stored"}, {"title": "Build and Release Methodology Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-27", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Build-and-Release-Methodology-Engineer_JR2028814", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\nWe are looking for a Senior Engineer for our Build and Release Methodology Group catering to our pioneering SOCs. As the SOC development becomes more complex requiring packing of more and more IPs and the need for doing more SOCs increase, we need to have a scalable infrastructure to be able to complete SOC development in fastest as well as most efficient way possible. This requires an SOC Build and IP Release infrastructure that caters to and keeps up with these ever-increasing complexities. In this position, you will work first-hand on architecting and developing this methodology. If you have real passion for methodologies and automation solutions, you will fit in great!\n\nWhat you'll be doing:\nDefine and develop system-level methodologies and tools to build SOCs in an efficient and scalable manner.\nArchitect and implement core build flows so as to optimize build and make it simpler and efficient.\nImprove build, release, and integration tools and procedures.\nIdentify and develop Checks to enforce the best practices for the Build and Release guidelines.\nDevelop solutions to enable abstraction and compartmentalization for customer IPs.\nIdentify difficulties and inefficiencies in the SOC implementation process and propose ideas to solve them.\nSupport IP teams with Build and Release related issues.\n\nWhat we need to see:\nBS or MS in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent experience.\n2+ years of industry experience as Build and Release Engineer, Build Automation, IP integration and related areas.\nStrong coding skills in Perl, Python, Makefile, Shell script, or other industry-standard scripting languages.\nExcellent analytical and problem-solving skills.\nExcellent interpersonal skills to work with multi-functional teams and collaborate with team members across sites and cultures to build consensus.\nBackground in RTL (Verilog), Verification (UVM, System Verilog) and C/C++ is a plus - Not must.\nExperience in synthesis and physical design is a plus - Not must.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "ASIC Design Engineer, BOOT and Power Management", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-27", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/ASIC-Design-Engineer--BOOT-and-Power-Management_JR2028799-1", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.\n\nWe are now looking for RTL Design engineers for our BOOT and Power management Subsystem Design deployed in Automotive and Client chips. As one of the primary designers, you will be responsible for implementing system BOOT and overall power management architecture of next generation chips. One should possess strong digital design and verification fundamentals.\n\nWhat you'll be doing:\nAs a designer, be responsible for making architectural trade-offs based on feature/performance/power requirements, analyze system implications, come up with the micro-architecture, implement RTL, drive the verification, close timing, and support silicon validation. During the course of a project you would end up driving the following aspects of design for your unit:\nOwn micro-architecture and RTL development of design modules\n\nMicro-architect features to meet performance, power and area requirements\n\nWork with HW architects to define critical features\n\nWork with verification teams to verify the correctness of implemented features\n\nPartner with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable.\n\nWhat we need to see:\nBTech/MTech with 2+ years of experience in crafting complex Units and CPU/micro-controller based Sub-systems\n\nKnowledge of security standards, protocols and system security architectures of modern SOC's would be a significant plus\n\nExcellent influencing skills resulting in collaboration with cross-cultural, multi geography and matrixed teams\n\nGood debugging, analytical and problem solving skills\n\nGreat interpersonal skills and ability to work as an excellent teammate\n\nWe have some of the most brilliant and talented people in the world working for us. If you're creative and independent, with a genuine real passion for technology and improving the state of art, we want to hear from you! Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/\n\nNVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior Verification Engineer - HSIO Unit Level", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-27", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer---HSIO-Unit-Level_JR2028800", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people.\nToday, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.\nWe are seeking hardworking, determined, and imaginative individuals to join our automotive verification group. As the owner of HSIO IP's unit level verification, you will contribute to projects crafting the future of automotive chips and systems. You will gain direct experience of chip working with high-performance CPU and memory sub-systems, NOC-based interconnect fabric, high-speed I/Os, and various advanced technologies used in our Tegra chips.\n \nWhat you'll be doing:\nYou will develop UVM-based verification test benches and methodologies. These will verify complex rapid data transfer IO IPs and sub-systems such as USB, UFS, MPHY, Ethernet, and MACSEC.\nDuring the course of a project, you will drive the following aspects of verification for your unit:\nArchitect the testbenches and craft verification environment using SV and UVM methodology\n\nDefine test plans, tests and verification infrastructure for modules, clusters and systems\n\nBuild efficient and reusable bus functional models, monitors, checkers, and scoreboards\n\nImplement functional coverage and coordinate the verification closure process for the unit\n\nWork with architects, designers, FPGA, and post-silicon teams to ensure that your unit is robust\n\nWhat we need to see:\nBTech or MTech in ECE, EE, CSE, or an equivalent degree is required. Candidates should have 4+ years of demonstrated ability in verification closure of complex units, sub-systems, or SOC level verification.\n\nProven experience in High Speed IO verification (UFS/PCIE/XUSB), knowledge of 10G/1G Ethernet MAC and Switch\n\nExperience in the latest verification methodologies like SV and UVM\n\nGood debugging and analytical skills with exposure to industry-standard verification tools for simulation and debug\n\nGood interpersonal skills, ability to work as a diligent teammate, and excellent communication skills to collaborate with cross-cultural global teams and work in a matrix organization\n\nWays to stand out from the crowd:\nExposure on using AI (Claude and Curser) extensively for code development would be a big plus\n\nA mentality towards constant improvement and looking to build a multiplier effect through your work and automation\n\nExposure to Formal verification would be excellent\n\nWe have some of the most experienced and dedicated people in the world working at NVIDIA. If you're creative and independent, with a genuine passion for adopting the newest technology, we want to hear from you. Join us and be part of something outstanding!\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.\nWidely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Design Verification Engineer, Silicon and Systems Group", "company": "Amazon", "location": "Bengaluru, Karnataka, IND", "date_posted": "2026-10-27", "url": "https://www.amazon.jobs/en/jobs/10590244/design-verification-engineer-silicon-and-systems-group", "is_hardware": true, "platform": "amazon", "jd_text": "As a Design Verification (DV) Engineer, you will be part of an advanced architecture team that is exploring new hardware designs to improve our devices. In this role, you will be responsible for defining the verification methodology and implementing the corresponding test plan for advanced functional blocks. You will participate in the design verification and bring-up of such blocks by writing relevant assertions, debugging code, test benches, test harnesses, and otherwise interacting with the extended team.\n\nYou will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware Engineering, and Software Engineering, to architect and implement complex functional block that enable development of world-class hardware devices. In this role, you will:\n\n· Design world class hardware and software\n· Communicate and work with team members across multiple disciplines\n· Deliver detailed test plans for verification of complex digital design blocks by working with design engineers and architects\n· Create and enhance constrained-random verification environments using SystemVerilog and UVM\n· Identify and write all types of coverage measures for stimulus and corner-cases.\n· Debug tests with design engineers to deliver functionally correct design blocks.\n· Close coverage measures to identify verification holes and to show progress towards tape-out.\n· Participate in test plan and coverage reviews\n· Integrated 3rd party IPs/VIPs and transactors\n· Perform IP/SOC bringup in simulation, emulation and prototyping environments\n\nThe ideal candidate should have experience with RTL development environments, fluency in modern hardware description languages and verification methodologies. They should have experience verifying complex IP blocks from scratch that have successfully been integrated in SOCs or other such silicon that have been productized in consumer devices. We are looking for a self-driven individual who can work with architects, HW and SW developers and can quickly resolve blocking issues.\n\nBasic qualifications\n- Bachelor's degree in Electrical Engineering or a related field\n- Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills\n- Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing\n- Experience using multiple verification platforms: UVM test bench, FPGA, emulator, software environments, and system testing\n- Experience with test plan development, building the necessary test bench infrastructure, developing tests and verifying the design\n- Experience with industry standard tools and scripting languages (Python or Perl) for automation\n- Experience in English-language communication skills, both written and verbal\n- 7+ years or more of practical semiconductor design verification including System Verilog, UVM, assertions and coverage driven verification.\n- Experience defining verification methodologies\n- Experience with writing directed/constrained-random tests\n\nPreferred qualifications\n- Master's degree in Electrical or Communications Engineering or a related field\n- Experience in system-level debugging\n- Knowledge of SoC architecture\n- Experience with boot-up and bare metal flows for CPU cores\n- Strong programming skills in C and scripting skills in Python and/or Perl\n- Experience with high performance industry standard IO interfaces like AMBA AXI4, USB, MIPI etc.\n- Experience with PCIE Experience with formal verification\n- Experience with transaction level modeling Knowledge of FPGA and emulation platforms\n\nOur inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "jd_status": "stored"}, {"title": "Device Associate III, Hardware Compute Group", "company": "Amazon", "location": "Bengaluru, Karnataka, IND", "date_posted": "2026-10-27", "url": "https://www.amazon.jobs/en/jobs/10590245/device-associate-iii-hardware-compute-group", "is_hardware": true, "platform": "amazon", "jd_text": "A Device Associate’s primary responsibility is to execute test case instructions and report discrepancies, execution and analysis of automated regressions and track daily execution status using recommended tools and techniques. A DA is also responsible for successful and on time delivery of results\n\nKey job responsibilities\n* Execute test cases prepared for testing Software builds\n* Perform test case execution and report bugs accurately\n* Understand testing procedures and guidelines for new  builds / releases.\n* Perform regression and repetitive testing exercises to  qualify builds without compromising on quality\n* Use software tools like dashboards for data capture on a daily basis.\n* Be comfortable with capturing results, communicating  and escalating failures and providing individual status reports.\n* Raising all failures/doubts related to the execution of  test cases in the clarification portal and closing the same as per the  SLA’s.\n* Lab and test farm maintenance\n\nAbout the team\nThe Silicon System Group (SSG) is at the forefront of designing and developing cutting-edge System-on-Chip (SoC) solutions that power the next generation of consumer electronic devices. As part of this high-impact team, you will have the unique opportunity to work on the latest SoC architectures — from early silicon bring-up through production validation — shaping the performance, power efficiency, and reliability of products used by millions of customers worldwide.\n\nWork Environment\n\nOur work environment is fast-paced, dynamic, and intellectually stimulating. We thrive on solving complex challenges, pushing the boundaries of silicon quality, and delivering world-class products on aggressive timelines. If you enjoy working in a high-energy setting where no two days are the same, this is the team for you.\n\nThis is a rare opportunity to be part of a team that is building something new — where your ideas matter, your expertise is valued, and your impact is visible from day one.\n\nBasic qualifications\n- 1+ years of Quality Assurance/testing domain experience\n- Bachelor's degree in any field of study\n- Flexibility and Interest to do repetitive tasks is required\n- High level of energy and proactive nature. A sense of ownership and drive and a willingness to accept the challenge of daily deadlines is essential\n\nPreferred qualifications\n- Knowledge of Linux fundamentals\n- Quantitative fields such as science and engineering preferred but not mandatory\n- Understanding schematics, little bit hardware / board knowledge\n- Power measurement\n\nOur inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "jd_status": "stored"}, {"title": "Validation Engineer – Post Silicon Functional Validation, Compute Subsystem (CSS)", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-10-27", "url": "https://careers.arm.com/job/bengaluru/validation-engineer-post-silicon-functional-validation-compute-subsystem-css/33099/102516606672", "is_hardware": true, "platform": "talentbrew", "jd_text": "About the Team\n\nThe Compute Subsystem (CSS) team at Arm designs and delivers integrated, validated compute subsystems that serve as reference platforms for Arm-based SoCs. The team collaborates across CPU, interconnect, memory, and IO IP teams to build efficient, high-performance solutions targeting client, infrastructure, and automotive markets.\nThe Functional Validation Team ensures that Arm’s compute subsystems meet quality, performance, and functionality expectations through comprehensive pre-silicon and post-silicon validation across the product lifecycle.\n \nRole Overview\n\nAs a Validation Engineer, you will be responsible for developing, executing, and improving validation methodologies for Arm’s compute subsystems IPs both before and after silicon bring-up. You will work closely with design, verification, emulation and customer enablement teams to ensure robust validation coverage and early detection of complex system-level issues.\nor\nAs a Validation Engineer in the Compute Sub-System (CSS) team, you will be responsible for validating key subsystem IPs and platform functionality across the pre-silicon and post-silicon lifecycle. You will develop validation solutions, execute comprehensive test plans, debug complex hardware/software issues, and collaborate closely with Architecture, Design, DV, Firmware, and Software teams to ensure high-quality silicon delivery.\n \nKey Responsibilities\nDevelop and execute pre-silicon and post-silicon validation plans for Arm’s compute subsystems.\nBuild and enhance test environments, automation frameworks, and validation infrastructure using emulation and silicon platforms.\nPerform system-level functional validation, focusing on CPU clusters, coherent interconnects, memory controllers, and peripheral integration.\nDrive root-cause analysis of hardware, firmware, and software issues, collaborating with cross-functional teams.\nDevelop diagnostic, stress, and performance workloads to validate system functionality, power, and performance.\nSupport silicon bring-up and debug activities, including board-level testing and post-silicon lab validation.\nAnalyse coverage gaps and contribute to improving validation efficiency and quality metrics.\nContribute to automation and continuous integration for validation workflows.\n \nRequired Skills and Experience\n1–3 years of relevant industry experience in SoC, subsystem, or IP-level functional validation.\nStrong understanding of ARM based SoC architecture, AMBA protocols (AXI/ACE/CHI), cache coherency, and CPU subsystems.\nProficiency in C/C++ and scripting languages (Python) for test automation and analysis.\nExperience with hardware validation tools (logic analyzers, oscilloscopes, JTAG debuggers) and pre-silicon simulation/emulation environments.\nSolid understanding of pre-silicon verification techniques and post-silicon validation challenges.\nFamiliarity with C based IP drivers and firmware for system-level bring-up and validation.\nStrong analytical and debugging skills; ability to triage complex hardware/software interactions.\n#LI-KR2\n \nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Engineer - Physical design", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-10-27", "url": "https://careers.arm.com/job/bengaluru/engineer-physical-design/33099/102503863536", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview: \n\nWe are looking for a Physical Engineer specialized in building with 1–2 years of relevant experience to join our SoC implementation team. You will contribute to next-generation SoC projects, working across the synthesis-to-GDSII flow. \n\nThis role offers hands-on experience in physical implementation, timing analysis, debugging and power, performance and area (PPA) optimization. You will collaborate with design , verification, DFT and physical IP teams, using scripting and AI-assisted workflows to improve engineering efficiency. \n\nResponsibilities: \n\nComplete and support RTL synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and GDSII generation with mentorship from senior engineers. \n\nAnalyze and improve PPA through synthesis and physical implementation. \n\nConduct static timing analysis with Synopsys PrimeTime, troubleshoot setup and hold violations, and assist in achieving timing closure across operating modes and corners. \n\nReview timing constraints, tool reports and implementation results to identify issues, investigate root causes and propose fixes. \n\nAssist with physical verification and final approval processes, including DRC, LVS, signal integrity, and EM/IR analysis. \n\nDevelop Python and Tcl scripts to automate implementation tasks, analyze reports and track quality. \n\nUse approved AI tools and agents to assist with scripting, report analysis and debugging, while independently validating their outputs. \n\nDocument results, communicate technical findings and collaborate with teams to resolve implementation issues. \n\nNecessary Skills and Experience:  \n\nBachelor’s or Master’s degree in Electronics, Electrical Engineering, Microelectronics, VLSI or a related field. \n\n1–2 years of relevant experience in ASIC/SoC physical design or implementation. \n\nFamiliarity with the RTL-to-GDSII process, encompassing synthesis, floorplanning, placement, CTS, routing, and timing closure. \n\nUnderstanding of physical designfundamentals, including utilization, congestion, clock skew, latency, buffering and cell sizing. \n\nHands-on experience with PrimeTime and at least one synthesis or physical implementation tools such as Fusion Compiler, Genus or Innovus. \n\nKnowledge of static timing analysis, including setup/hold checks, clock definitions, timing exceptions and multi-mode, multi-corner analysis. \n\nAbility to read Verilog RTL and gate-level netlists and trace timing paths to investigate implementation issues. \n\nPractical programming skills in Python, familiarity with Tcl, and confidence working in a Linux environment. \n\nStrong analytical and debugging skills, clear communication and a willingness to learn and take ownership of assigned tasks. \n\n“Preferred” Skills and Experience:  \n\nExposure to advanced-node, hierarchical implementation or large SoC integration. \n\nFamiliarity with low-power concepts, UPF, multiple voltage domains, power gating and level shifters. \n\nExposure to on-chip variation, timing derates, crosstalk and signal integrity. \n\nBasic knowledge of power distribution networks, EM/IR analysis, IO placement, and bump-planning considerations. \n\nFamiliarity with DFT requirements and physical verification flows. \n\nExperience using AI coding assistants or agents for engineering automation, including effective task definition, output validation and responsible handling of proprietary build data. \n\n#LI-BB1\n\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Principal Emulation IP Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-27", "url": "https://careers.synopsys.com/job/bengaluru/principal-emulation-ip-engineer/44408/102513988288", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nYou have spent years in the trenches of ASIC verification, and somewhere along the way you realized that emulation is not just another tool in the flow, it is the thing that makes or breaks your ability to ship complex IP on time. You know PCIe or DDR inside and out, not just the spec but the weird corner cases, the errata that nobody talks about, and the places where emulation models fall short of what the design team actually needs.\nYou have worked on Zebu or similar platforms long enough to know what good emulation IP looks like and what happens when it is not quite right. You have closed that gap before, probably more than once, and you know how to do it without creating chaos for the teams depending on your work. Sitting with a design team in Bangalore, a verification lead in California, and an IP product manager in Europe does not faze you. You walk out with a plan that everyone believes in.\nYou do not wait for perfect alignment. Ask the right questions, push back when something does not make sense, and move. At Synopsys, you will work on IP that powers the next generation of silicon, and the emulation strategies you define will directly affect how fast we get there.\n\nWhat You'll Be Doing\nBridge the gap between Emulation IP capabilities and Design IP verification needs across both Controller and PHY domains for high-speed interfaces like PCIe and DDR\nDefine technical requirements for Emulation IP, working directly with IP development and verification teams to ensure correct implementation and deployment on Zebu platforms\nTrack and report key metrics on Emulation IP quality, performance, and coverage, driving continuous improvement across verification workflows\nStay ahead of evolving PCIe and DDR standards, interpret specification updates, ECNs, and errata, and translate those into actionable changes for both Emulation and Design IP teams\nReview and validate test plans for Emulation IP and Design IP, ensuring completeness, traceability, and alignment with product quality goals\nCollaborate cross-functionally with verification, design, product, and platform teams to optimize emulation methodologies and standardize best practices\nMentor engineers on emulation strategies, verification techniques, and IP development workflows\n\nThe Impact You Will Have\nAccelerate time to market for high-performance IP by defining emulation strategies that catch issues earlier and reduce silicon respins\nElevate product quality across Synopsys IP portfolios by ensuring Emulation IP meets the real needs of design and verification teams\nDrive adoption of best-in-class emulation and verification methodologies that become standard practice across the organization\nInfluence the next generation of emulation solutions and workflows, positioning Synopsys as a leader in pre-silicon validation\nImprove cross-functional collaboration and alignment between geographically distributed teams, reducing friction and rework\nStandardize verification workflows and metrics, making it easier for teams to track progress, identify gaps, and deliver with confidence\nShape how Synopsys develops and deploys Emulation IP for cutting-edge digital designs and system architectures\n\nWhat You'll Need\n8+ years of hands-on experience in emulation, pre-silicon verification, or IP product development\nExpert-level knowledge of PCIe or DDR interfaces, including protocol details, verification strategies, and real-world implementation challenges\nExtensive experience with Zebu or similar emulation platforms, specifically for IP verification and system-level validation\nProven track record leading IP product development initiatives with a strong focus on emulation and verification\nDemonstrated ability to work cross-functionally in matrixed, global teams and drive consensus across diverse stakeholders\nStrong communication skills with the ability to influence technical direction and inspire change across engineering teams\nComfort working in dynamic, ambiguous environments where requirements evolve and priorities shift\n\nWho You Are\nYou can walk into a room where the Emulation IP does not quite match what the design team needs and walk out with a concrete plan to close the gap without derailing either team's schedule\nYou do not need someone to tell you what the next version of the PCIe or DDR spec means for your work. You read it, figure out the implications, and start the conversation with your team\nYou are the person people come to when emulation results do not make sense, and you know how to debug across the boundary between emulation models, RTL, and test environments\nYou push back when a test plan looks complete on paper but is missing coverage for the cases that actually matter in production\nMentoring engineers who are newer to emulation or IP verification comes naturally to you, and you do it in a way that builds their confidence and capability\nYou stay organized across multiple workstreams, stakeholders, and time zones without losing track of what matters most\n\nThe Team You'll Be Part Of\nYou will join a dynamic, high-performing engineering team focused on IP development, emulation, and verification at the forefront of semiconductor innovation. Our team is collaborative, cross-functional, and globally distributed, working together to solve complex challenges and deliver industry-leading solutions. You will have the opportunity to collaborate with experts across multiple domains, drive impactful initiatives, and shape the future of digital design and verification at Synopsys.\n\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "ASIC Digital Design, Sr Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-27", "url": "https://careers.synopsys.com/job/bengaluru/asic-digital-design-sr-engineer/44408/102541516384", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nYou are an early-career engineer ready to make your mark in semiconductor design. You have spent your academic years drawn to digital design that requires proof, not just simulation. When you see a spec, you think about corner cases and what could break. You have written Verilog or SystemVerilog, debugged logic that did not behave as expected, and you are comfortable in a Unix terminal. Formal verification might be new to you, but the rigor makes sense. You learn by doing, ask questions when stuck, and you do not mind being the person who finds the bug everyone else missed.\n\nWhat You'll Be Doing\nLearn the latest formal verification methodology from experts and apply your learnings to live projects.\nWork with a team of seasoned FV engineers and execute validation as per defined plans.\nSupport quality improvements and contribute insights that help enhance verification tool capabilities.\nWrite and refine assertions in SystemVerilog Assertions (SVA) to capture design intent and uncover edge-case failures.\nScript verification flows using Python, Perl, or Tcl to automate repetitive tasks and improve team productivity in Unix/Linux environments.\n\nThe Impact You Will Have\nHelp catch critical design bugs before tapeout that would otherwise cost months and millions to fix in silicon.\nContribute to the quality and reliability of Synopsys IP and EDA tools that power semiconductor development across the industry.\nAccelerate verification closure on complex designs by applying formal methods that simulation alone cannot cover.\nStrengthen the formal verification methodology at Synopsys by bringing fresh perspectives and identifying gaps in existing flows.\n\nWhat You'll Need\n Master’s degree in Electronics, Electrical, Instrumentation, or a related engineering discipline. (2026 Fresh Masters Grad Expected).\n0 to 2 years of experience in digital design, verification, or related semiconductor work (internships, projects, and coursework count).\nStrong understanding of computer architecture and digital design fundamentals including state machines, pipelining, and timing.\nHands-on experience with hardware description languages, Verilog or SystemVerilog preferred.\nProficiency in at least one scripting language such as Python, Perl, or Tcl, and comfort working in Unix or Linux environments.\nSolid academic performance with relevant coursework or project work in VLSI, digital design, or verification.\nExperience with formal verification tools, assertion languages, or model checking is a strong plus.\n\nWho You Are\nYou can look at a block diagram or RTL code and start asking the right questions about what could go wrong, not just what is supposed to work.\nYou are comfortable learning new tools and methodologies on the job without needing everything explained upfront, you read documentation, try things, and ask targeted questions when you are stuck.\nYou communicate clearly when you find something, whether it is a bug, a gap in coverage, or a script that is not working the way it should.\nYou are detail-oriented enough to track down a single-bit logic error in a complex design without losing sight of what the block is supposed to do.\n\nThe Team You'll Be Part Of\nYou will join a focused team at Synopsys dedicated to advancing formal verification methodologies and delivering proven IP and EDA solutions. You will collaborate with experienced formal verification engineers and design experts who are committed to pushing the boundaries of what formal methods can achieve. The team values rigorous thinking, continuous learning, and clear communication, creating an environment where your growth is supported.\n\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior Digital Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-10-27", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25019192", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n In this position, you will be working on high-speed mixed-signal communication circuits using state-of-the art process technology, as well as be involved in the design of high performance digital circuits interfacing to leading edge analog circuitry as part of an overall system.\n\n Your responsibilities will include RTL coding, simulation, synthesis, timing closure, verification, evaluation, debugging of high-speed communication chips both at the circuit level and behavioral level.\n\n As a design engineer, you will prepare test methods and specifications, assist in preparation of application information, data sheets and demo boards. You will develop solutions to complex problems through assessment of various techniques and approaches. You will plan and organize work to ensure timely completion of many independent tasks with general instructions on routine tasks and with detailed instructions on new assignments.\n\n This position involves routine communication with a highly talented team of analog and digital design engineers to solve problems and present information as well as active participation in work groups, providing ideas and collaborative teamwork.\n\nQualifications\nMinimum requirements:\n\n5+ years of relevant experience\n\nA thorough understanding of digital logic design\n\nFamiliarity with the Verilog language and simulators\n\nA good understanding of analog functionality and exposure to analog IC design methods\n\nAbility to solve problems using a systematic approach\n\nPreferred qualifications:\n\nExperience with System Verilog\n\nDemonstrated strong analytical and problem solving skills\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nStrong time management skills that enable on-time project delivery\n\nDemonstrated ability to build strong, influential relationships\n\nAbility to work effectively in a fast-paced and rapidly changing environment\n\nAbility to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Test Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-10-27", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25019233", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n This is a unique opportunity to be part of a team that drives testing of highly integrated multi-rail power management devices going into markets with significant growth potential. The ideal candidate would have a background that includes probe and final test development of complex mixed signal circuits.\n\nResponsibilities include:\n\nWork with design and DFT team to understand design, DFT specifications\n\nGenerate test plan, create test and char program, design ATE hardware interface boards\n\nDebug characterizing silicon on ATE, correlate results with bench data\n\nAnalyze silicon results, supporting failure analysis tasks\n\nPerform statistical analysis of yield fallout, debug and fix yield issues; optimize test time\n\nWork with production team to release products to volume production\n\nTest strategy definition and implementation for digital, mixed signal products (MCUs, MPUs)\n\nATE (Automatic Test Equipment) test hardware and software\n\nSilicon qualification& characterization including qual hardware development\n\nComprehensive device debugging, design validation and failure analysis\n\nDrive for robust and cost effective test solutions while being accountable for product quality\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in Electrical Engineering\n\n3-8 years of relevant experience, preferably at SOC level for a microcontroller, microprocessor type of SOCs\n\nATE experience on Teradyne J750 or equivalent ATE (UFlex+, V93K), although J750HD experience is preferred and is a differentiator\n\nCharacterization test program and hardware development experience, Production test program and hardware development experience\n\nStrong technical knowledge of electronic devices and circuits, and digital, Scan, Memories, Analog test techniques\n\nData analysis skills using Spotfire, dataPower or equivalent tool based on STDF\n\nExperience with product engineering activities such as yield improvement and test time reduction\n\nStrong understanding of the IC product development process, from concept to volume production\n\nPreferred qualifications:\n\nScan, Memories and Mixed signal test techniques and experience with developing, integrating tests on ATE\n\nExperienced with test program and hardware offload to TI offshore manufacturing sites\n\nProficiency in programming/scripting in C++, Python, C#\n\nLabview, Teststand experience\n\nRevision control tools experience : Subversion, Git\n\nDemonstrated strong analytical and problem solving skills\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nStrong time management skills that enable on-time project delivery\n\nDemonstrated ability to build strong, influential relationships\n\nAbility to work effectively in a fast-paced and rapidly changing environment\n\nAbility to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Analog IC Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-10-27", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25019359", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\nJoin the APP-LP (Analog Power Products - Linear Power) team, where we push the boundaries of power management silicon. Our group manages an extensive and highly diverse product portfolio that spans precision voltage references, LDO's, sophisticated protection circuitry like eFuses and high-side switch controllers. Working within APP-LP means tackling unique engineering challenges across a wide spectrum of technologies, including high-speed switching and ultra-low-dropout (LDO) regulation. We build the fundamental building blocks that enable safe and seamless power delivery in any system architecture.\n\n \n\nThe High Side Switche and Controller product line is looking for analog design engineers who are experienced, highly driven and fast-learners to join their development team based in Bangalore, IN. We work on high voltage and high current ICs for Automotive and Industrial market. We develop cutting edge and highly differentiated products that push the boundaries of power density. This team has full product development responsibility from definition to productizing. \n\n \n\nWhat will you be doing in this role? (Responsibilities)\n\nAs a design engineer you will be expected to:\n\nCollaborate with design lead and system engineer in defining cutting edge products\n\nDevelop circuit architectures for the IP blocks starting from datasheet / system specifications. \n\nDerive block level specifications and circuit architectures. You will be responsible for circuit implementation which not only meet the specifications, but work reliably and robustly while meeting high yields in production. \n\nCollaborate with chip-lead and layout engineers in developing floorplan and layout strategies for optimal implementaiton.\n\nOwn block / module level verification of the blocks and participate/contribute in full chip level verification  planning and execution. \n\nDevelop design collaterals and deliver high quality design review documentation. \n\nSupport the bench validation, testand product engineering teams in planning of their activities as well as actively participate in silicon bring-up and debug..\n\nContinuously challenge the status-quo and push the frontiers of technologies in collaboration with subject matter experts, while also driving new and improved circuit architectures/topologies and design flows and methodologies \n\nWork along with partner organizations such as process technology teams, packaging teams, EDA etc. \n\nWhat can you expect to learn in this role? (Opportunity)\n\nWork on high growth, high impact domain of power-delivery systems. \n\nPush the limits of technology, be it process or packaging.  Get to work with leading experts in the domain of process technology and packaging solutions, while working with circuit experts in developing full product solutions.\n\nGet exposure to full product life-cycle by co-location and collaboration with teams working on product definition to cross functional development and customer support, enabling development of broad-spectrum skills. \n\nExample products developed by this team for reference\n\nTPS1HC100: https://www.ti.com/product/TPS1HC100-Q1 \n\nTPS2HCS08: https://www.ti.com/product/TPS2HC08-Q1 \n\nTPS1HTC100: https://www.ti.com/product/TPS1HTC100-Q1 \n\nTPS1211: https://www.ti.com/product/TPS1211-Q1\n\nQualifications\nMinimum Qualification\n\nBachelors degree in Electrical or Electronics Engineering or equivalent.\n\n2-5 years experience in analog circuit design preferably in high voltage and power domain.\n\nStrong fundamentals in electrical engineering and basic analog and digital building blocks.\n\nAbility to develop and read simple digital logic circuits.\n\nPreferred qualifications:\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to analyze complex problems and risks and develop structured execution plans\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to demonstrate ownership, take the initiative and drive for results\n\nAbility to take decisions for self work and seek help when needed.\n\nStrong time management skills that enable on-time project delivery\n\nAbility to mentor junior engineers and willingness to learn from experts\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Si GPU Functional Debug - Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-26T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720933788", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nQualcomm graphics is the best in the mobile GPU world with the best perf/watt, perf/area and in raw performance. The GPU team has well established RnD teams from Architecture and Design to Post Silicon Validation and Functional Debug in Bangalore. The team delivers on products from the Snapdragon 800 series to the low tier 200 series. You will be joining a successful engineering department whose deliveries can be found in billions of smartphones, wearables.\n\nBased out of Qualcomm’s Bangalore office, this role is for GPU Functional Debug of Final Silicon issues for Snapdragon MSMs. You will be part of GPU system bring -up team and focus on the root cause the real time functional issue observed/reported in Silicon. Pulling on your design knowledge and technical expertise, you solve technical issues in all projects to ensure smooth execution across projects. As part of your role, you will work with Architecture, Design, DV, emulation, SW driver to understand about GPU architecture, design , System level scenario and further use those knowledge for solving GPU functional issues.\n\nKey Responsibilities\nDrive Functional GPU issue reported by internal SW testing or external customers.\n\nParticipation on the reproduction of the issue in the lab in Windows/Android/Auto platforms and analyzing the symptoms.\n\nBuilding hypothesis based on symptoms of failures, devising experiments to check the hypothesis and arrive at the root cause of the issue\n\nCommunication to Design, DV, SW, HLM and other teams to advance the root cause, solving the Si issues.\n\nDevelop new processes and methodologies / tools to improve time to root cause.\n\nTaking initiative of enhancing the debug architecture of GPU core.\n\nPreferred Qualifications\n4 to 10 years of experience working in RTL Design (Micro-Architecture) or Systems experience in GPU or CPU or multimedia IP. Candidates are expected to have experience in:\nShould have a proven track record to work with multidomain, across site teams.\n\nGPU pipeline knowledge is preferred\n\nExperience in debugging low level hardware Design issues, and working closely with design, verification, and software simulator teams.\n\nHave good understanding of modern SoC architectures.\n\nBasics of Power, performance concepts and able to articulate the tradeoffs\n\nExposure to Debug tools like JTAG and kernel debuggers\n\nExposure to at least one of scripting language e.g. Perl, Python, or Java\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Lead Engineer, Senior-System Performance Engineer (NSP, AI/ML, CPU, DDR)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-26T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721737748", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Systems Engineering\nGeneral Summary:\nYou will be part of System Performance team that is responsible for profiling and optimizing the System Performance on Snapdragon Data center chipsets. This role will require a strong knowledge of AI/ML performance using NPU cores. The knowledge of CPU, DDR, NoCs will be an added advantage.\n \nSkills Required:\nA deep understanding of NPU, CPU and DDR architecture internals like\nNPU: Understanding of NPU micro-architecture, including its specialized processing elements for operations like matrix multiplications and convolutions.\nA strong grasp of deep learning fundamentals, including neural network architectures like Convolutional Neural Networks (CNNs), transformers, GenAI etc.\nUnderstanding the distinction between the compute-intensive training of a model (often done on GPUs) and running inference (making predictions) on NPUs.\nKnowledge of Model optimization and compression techniques (Quantization, Pruning, Distillation etc.)\nCPU caches (L1, L2, L3), instruction pipelines, branch prediction, memory hierarchy (including register, cache, and main memory) and multi-core/multi-threaded processing. You need to understand how memory access, instruction dependencies, and contention for shared resources can impact performance.\nDDR: Understanding of JEDEC specifications LPDDR4, LPDDR5, LPDDR6, including command and timing parameters (e.g., 𝑡𝐶𝐿, 𝑡𝑅𝐶𝐷, tRP), memory organization (rows, columns, banks), and basic view of training and initialization sequences, how a memory controller works and its specific features like command queue, port arbitration, and various control schemes.\nFamiliarity with frameworks like TensorFlow Lite, PyTorch Mobile, and ONNX Runtime for preparing models for deployment. Experience with NPU-specific compilers, such as those from Qualcomm (QNN), Arm (Vela), Intel (OpenVINO), to optimize and orchestrate AI workloads.\nEvaluating hardware and software to determine the best fit for specific AI tasks and measure performance metrics like TOPS/W (trillions of operations per second per watt).\nUsing tools like the Windows Performance Toolkit and Qualcomm's Snapdragon Profiler to analyze and optimize NPU and system-level performance\nA core understanding of how to use parallel processing architectures for efficient AI computations.\nExpertise in how operating systems manage processes, threads, memory, MMU, and interrupt handling. This knowledge is crucial to understanding software for the kernel scheduler and system-level bottlenecks.\nGood understanding of Benchmarks CPU (like GeekBench, SpecInt, CoreMark etc) and DDR (like lat_mem, stream, bw_mem etc.) and how they exercise the underlying CPU/GPU/DDR architecture.\nExperience with a variety of performance monitoring tools like Intel VTune, Linux perf, and Utilities like top, vmstat, iostat, and netstat to monitor system resources like CPU, memory, and I/O. Experience with software tools to monitor system hotspots, command bus utilization, and identify memory traffic patterns is critical. This includes validating that the traffic generated by software is as expected.\nGood understanding of memory allocation policies, prefetching, and caching to minimize latency and maximize bandwidth. Understanding how an application accesses memory is vital. Skills in profiling code to analyze memory access patterns and then optimizing the code for better data locality.\nAnalyzing large datasets from performance tests requires strong statistical skills. This can involve creating histograms of transaction latencies and deriving performance metrics to understand a system's behavior.\n \nResponsibilities include:\n•     Drive Performance analysis on silicon using various System and Cores (i.e. NPU, AI/ML, CPU, Memory) benchmarks like Dhrystone, GeekBench, SPECInt, CNN/GenAI ML networks etc.\n•     Use of Performance tools to analyze the load patterns across IPs and identify any performance bottlenecks in system.\n•     Analyzing Perf KPIs of SoC subsystems like NPU, CPU, Memory, and corelate performance with projection\n•     Evaluate and characterize performance at various junction temperatures and optimize running at high ambient temperatures.\n•     Analyze and optimize the System performance parameters of SoC infrastructure like NoC, LP5 DDR, etc.\n•     Collaborate with cross-functional global teams to plan and execute performance activities on chipsets as well as make recommendations for next generation chipsets.\n \nMinimum Qualifications:\n5+ years of industry experience in the following:\n•     Experience working on any ARM/x86 based platforms, mobile/automotive/Data center operating systems and/or performance profiling tools.\n•     Experience in application or driver development in Linux\\QNX and ability to create/customize make files with various compiler options is a plus.\n•     Must be quick learner and should be able to adapt to new technologies.\n•     Must have excellent communication skills.\n \n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience.\n                                                                    OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.\n                                                                    OR\nPhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience.\n\nPreferred Qualifications:\nAdditional skills in the following areas are preferred:\n•     Knowledge of Computer architecture, LP5 DDR, Bus/NOC profiling is a big plus.\n•     Fundamentals on any operating system like Linux/QNX/Hypervisor & experience working on any Data center applications.\n•     Experience in creating professional quality reports and slides using MS Office or any advanced visualization tools.\n•     Experience in PoC development and competitive analysis Knowledge on Voltage/Power/ Thermal domain is plus.\n \nEducation Requirements:\n•     Required: Bachelor's, Computer Engineering, and/or Electrical Engineering\n•             Preferred: Master's, Computer Engineering, and/or Electrical Engineering\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Principal Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-26T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721752807", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.\n•    12+ years of ASIC design, verification, validation, integration, or related work experience.  \n•    4+ years of experience with architecture and design tools.\n•    4+ years of experience with scripting tools and programming languages.\n•    4+ years of experience with design verification methods.\n•    2+ years of work experience in a role requiring interaction with senior leadership (e.g., Vice President level and above).\n\nPrincipal Duties and Responsibilities:\n•    Leverages expert ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.\n•    Creates highly advanced architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.\n•    Collaborates with high-level representatives across functional teams (e.g., software architecture, hardware architecture, product management, program management teams) to develop and execute an implementation strategy that meets system requirements and customer needs.\n•    Serves as an expert resource for all aspects of the process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.\n•    Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable highly advanced architecture and design of multiple complex blocks/SoC or IC Packages; provides technical expertise and support to team members.\n•    Writes detailed technical documentation for highly complex EDA/IP/ASIC projects; reviews technical documentation for experienced engineers.\n\nLevel of Responsibility:\n•    Provides supervision to direct reports.\n•    Decision-making is critical in nature and highly impacts program, product, or project success. \n•    Requires verbal and written communication skills to convey highly complex and/or detailed information. May require strong negotiation and influence with large groups or high-level constituents.\n•    Has a great degree of influence over key organizational decisions (e.g., is making or directly making key decisions that will have substantial impact over the organization).\n•    Tasks often require multiple steps which can be performed in various orders; extensive planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Design Verification  Infrastructure Engineer - VIPs and Testbench", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-10-26", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Senior-Design-Verification--Infrastructure-Engineer---VIPs-and-Testbench_R-101274", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nJoin SiFive’s Design Verification Infrastructure team to develop and maintain the Verification Platform VIPs, AIPs, and other testbench components used across SiFive. An ideal candidate will be a strong Design Verification engineer with a solid understanding of software engineering. You will be expected to collaborate with Design Verification engineers to develop reusable testbench components and integrate them within SiFive’s Chisel-based Verification Platform..\n\nResponsibilities:\nArchitect, develop, and maintain the Verification Platform to provide a common infrastructure that scales with the growth of SiFive for Design Verification and other verification and validation activities\n\nDevelop Verification Platform libraries for expressing verification intent in Scala with Chisel, including test harnesses, stimulus, scoreboards, and other generators\n\nDevelop Verification Platform VIPs, AIPs, and other testbench components using System Verilog, UVM, and other related technologies\n\nDevelop Verification Platform test plans and testbenches to verify and release testbench components with high quality\n\nEducate the Design Verification and other verification and validation teams on best practices and how to achieve them with the Verification Platform\n\nRequirements:\n\nDesign Verification experience with System Verilog and UVM\n\nExperience designing and verifying VIPs, AIPs, and other testbench components\n\nUnderstanding of modern software engineering practices\n\nTypically 3+ years with BS/MS/PhD in EE/CE/CS or related field.\n\nDesired:\nExperience with Chisel, Scala, and/or Python\n\nUnderstanding of EDA tools and flows for Design Verification\n\nFamiliarity with DevOps practices, build systems, and CI / CD\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Staff Design Verification Infrastructure Engineer - VIPs and Testbench", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-10-26", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Staff-Design-Verification-Infrastructure-Engineer---VIPs-and-Testbench_R-101270", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nJoin SiFive’s Design Verification Infrastructure team to develop and maintain the Verification Platform VIPs, AIPs, and other testbench components used across SiFive. An ideal candidate will be a strong Design Verification engineer with a solid understanding of software engineering. You will be expected to collaborate with Design Verification engineers to develop reusable testbench components and integrate them within SiFive’s Chisel-based Verification Platform..\n\nResponsibilities:\nArchitect, develop, and maintain the Verification Platform to provide a common infrastructure that scales with the growth of SiFive for Design Verification and other verification and validation activities\n\nDevelop Verification Platform libraries for expressing verification intent in Scala with Chisel, including test harnesses, stimulus, scoreboards, and other generators\n\nDevelop Verification Platform VIPs, AIPs, and other testbench components using System Verilog, UVM, and other related technologies\n\nDevelop Verification Platform test plans and testbenches to verify and release testbench components with high quality\n\nEducate the Design Verification and other verification and validation teams on best practices and how to achieve them with the Verification Platform\n\nRequirements:\nDesign Verification experience with System Verilog and UVM\n\nExperience designing and verifying VIPs, AIPs, and other testbench components\n\nUnderstanding of modern software engineering practices\n\nDesired:\nExperience with Chisel, Scala, and/or Python\n\nUnderstanding of EDA tools and flows for Design Verification\n\nFamiliarity with DevOps practices, build systems, and CI / CD\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Staff Design Verification Infrastructure Engineer - VIPs and Testbench", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-10-26", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Staff-Design-Verification-Infrastructure-Engineer---VIPs-and-Testbench_R-101272", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nJoin SiFive’s Design Verification Infrastructure team to develop and maintain the Verification Platform VIPs, AIPs, and other testbench components used across SiFive. An ideal candidate will be a strong Design Verification engineer with a solid understanding of software engineering. You will be expected to collaborate with Design Verification engineers to develop reusable testbench components and integrate them within SiFive’s Chisel-based Verification Platform..\n\nResponsibilities:\nArchitect, develop, and maintain the Verification Platform to provide a common infrastructure that scales with the growth of SiFive for Design Verification and other verification and validation activities\n\nDevelop Verification Platform libraries for expressing verification intent in Scala with Chisel, including test harnesses, stimulus, scoreboards, and other generators\n\nDevelop Verification Platform VIPs, AIPs, and other testbench components using System Verilog, UVM, and other related technologies\n\nDevelop Verification Platform test plans and testbenches to verify and release testbench components with high quality\n\nEducate the Design Verification and other verification and validation teams on best practices and how to achieve them with the Verification Platform\n\nRequirements:\n\nDesign Verification experience with System Verilog and UVM\n\nExperience designing and verifying VIPs, AIPs, and other testbench components\n\nUnderstanding of modern software engineering practices\n\nTypically 7+ years with BS/MS/PhD in EE/CE/CS or related field.\n\nDesired:\nExperience with Chisel, Scala, and/or Python\n\nUnderstanding of EDA tools and flows for Design Verification\n\nFamiliarity with DevOps practices, build systems, and CI / CD\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Senior CPU Formal Verification Engineer", "company": "SiFive", "location": "Hyderabad, India", "date_posted": "2026-10-26", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Hyderabad-India/Senior-CPU-Formal-Verification-Engineer_R-101476", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nRole Summary\n\nWe are seeking a Senior Design Formal Verification Engineer to own formal strategies for advanced out‑of‑order (OoO) CPU cores. You will work closely with micro‑architects and RTL designers to verify complex execution pipelines.\n\nResponsibilities:\n• Identify blocks suitable for applying Formal Verification\n• Create Formal Test-plan for blocks identifying properties to be implemented and sign-off metrics\n• Implementation and maintenance of Formal Verification environments in Chisel\n• Applying various FV techniques to reduce complexity and prove correctness of DUT\n• Debugging RTL to identify causes of failure scenarios\n• Guide and train team members on effective usage of Formal Verification tools\n• Develop/modify scripts to automate the verification process\n• Review formal setups and proofs with design and verification teams\n• Maintain and extend assertion libraries\n\nRequirements:\n5+ years of experience in Formal Verification of Digital Hardware Design\nA Bachelor's or Master's in Engineering\nExtensive experience with Formal Abstraction Techniques and sign-off process\nFamiliarity with industry-standard Formal Verification Tools, such as VC Formal, JasperGold\nKnowledge of Hardware Description and Verification Languages, such as VHDL, Verilog/ SystemVerilog\nKnowledge of Object-oriented Programming is a plus\nA keen interest in Processors and Digital systems\nStrong reasoning skills and excellent attention to detail\nGood inter-personal and teamwork skills!\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Senior Engineer - Physical Design", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-10-26", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Senior-Engineer---Physical-Design_R-101427", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nAbout the Role:\n\nAs a Senior Physical Design Engineer, you will be a core technical contributor responsible for the physical design implementation of our next-generation IPs. In this role, you will implement RTL2GDS ensuring the architecture and design achieve their peak physical potential.\n\nWe are looking for a \"full-stack\" physical design engineer who is deeply curious about the logic they are building. You should be the type of engineer who thrives at the convergence of microarchitecture and physical layout, enjoying the challenge of analyzing how an architectural datapath affects timing closure and how to push the boundaries of Power, Performance, and Area (PPA).\n\nKey Responsibilities:\nEnd-to-End Implementation: Own and execute the complete physical design flow (Synthesis, Floorplanning, P&R, Signoff) for major sub-systems and diverse IP blocks, ensuring they meet or exceed aggressive targets for PPA.\n\nArchitectural & RTL Co-Optimization: Partner with RTL and Architecture teams from early-stage design to signoff. Identify physical and structural bottlenecks early—such as routing congestion in complex crossbars, dynamic power hot-spots in execution units, and interconnect span limits—and collaborate on microarchitectural or structural solutions to overcome them.\n\nCross-Product PPA Execution: Apply advanced physical design techniques customized to the unique demands of different design classes. This includes implementing extreme leakage/dynamic power efficiency for edge IPs, rigorous reliability and redundancy structures for automotive standards, or maximizing bandwidth and throughput for high-speed fabrics.\n\nTechnical Ownership: Take ownership of complex implementation challenges, contribute to the improvement of flows, methodology, and automation, and assist in mentoring junior engineers while promoting best practices.\n\nRequirements - What you’ll bring\nExperience: 4+ years of hands-on physical design experience on advanced process nodes (7nm and below preferred).\n\nIP Implementation Expertise: Solid experience with the physical implementation of at least one major IP domain (such as CPUs, high-speed interconnects/fabrics, cache/memory hierarchies, or specialized accelerators) and a proven ability to adapt to new logic classes.\n\nCo-Design Mindset: Understanding of the interplay between physical implementation and microarchitecture, coupled with the curiosity to learn and adapt to different product architectures.\n\nTool Proficiency: Strong proficiency with industry-standard EDA tools—specifically Synopsys (Fusion Compiler, PrimeTime) and/or Cadence (Innovus, Tempus) implementation and sign-off suites.\n\nAdvanced Problem Solving: Ability to debug complex physical design challenges, including structural timing violations, routing congestion etc. with minimal supervision.\n\nEducation: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.\n\nWhy join us?\nIn this role, you will play a pivotal part in driving aggressive PPA optimizations across significant design sections, operating at the critical intersection of physical layout, RTL design, and hardware architecture. You will have the autonomy to make a substantial impact across our entire product portfolio—from highly efficient IoT cores and dense memory systems to demanding high-performance platforms. We offer a direct path for technical growth, allowing you to collaborate with world-class engineers in a supportive, fast-paced, and learning-rich environment.\n \n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "CPU RTL Design Manager", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-26", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/CPU-Front-end-Design-Manager_JR0287309", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nIntel's P-Core organization is seeking a highly experienced engineering manager to lead the Memory Execution Unit (MEU) Front-End development team responsible for delivering world-class CPU microarchitecture solutions for next-generation Server and Client products. The manager will own end-to-end execution of the MEU cluster across RTL Design, Design Verification, and Formal Verification, driving feature development from architecture definition through RTL implementation, pre-silicon validation, quality signoff, and silicon readiness. This role requires a strong technical leader who can build and grow a high-performing organization, drive execution excellence, influence cross-functional stakeholders, and deliver predictable first time-right silicon.\nKey Responsibilities\nTechnical Leadership\n•\tOwn end-to-end delivery of the MEU cluster across RTL, DV, and Formal Verification functions.\n•\tDrive microarchitecture reviews, implementation strategy, verification closure, and quality signoff.\n•\tEnsure delivery of features meeting Power, Performance, Area (PPA), Quality, Reliability, and Security objectives.\n•\tDefine execution strategy, milestones, risk mitigation plans, and resource allocation.\n•\tDrive adoption of advanced methodologies, automation, AI-assisted debug, formal technologies, and verification innovations.\nPeople Leadership\n•\tLead and grow an experienced team of RTL, DV, and Formal Verification engineers and technical leads.\n•\tBuild leadership bench strength and succession plans.\n•\tDrive talent development, mentoring, career growth, retention, and organization health.\n•\tFoster a culture of innovation, collaboration, accountability, and continuous improvement.\nCross-Functional Collaboration - Partner with Architecture, Design, Validation, Physical Design, DFT, Power, Security, and Product Engineering teams. Influence technical decisions across multiple organizations and geographies. Drive effective stakeholder management and executive communication.\nQuality and Execution Excellence - Deliver predictable execution against major CPU program milestones, bug prevention, early bug interception, coverage closure, and validation quality improvements. Ensure robust pre-silicon quality metrics and risk-based signoff methodology. Establish best practices for RTL, DV, and Formal Verification across the organization.\n\nQualifications:\nMinimum Qualifications\n•\tBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 15+ years of industry experience, or Master's degree with 12+ years of experience.\n•\t5+ years of engineering management experience leading senior technical teams.\n•\tStrong expertise in CPU microarchitecture, RTL design, verification methodologies, and formal verification.\n•\tProven experience delivering complex SoC/CPU products from definition through silicon.\n•\tDeep understanding of SystemVerilog, verification methodologies, assertions, coverage-driven verification, and formal tools.\n•\tDemonstrated success leading cross-functional programs and geographically distributed teams.\nPreferred Qualifications\n•\tExperience leading large Front-End CPU organizations spanning RTL, DV, and Formal Verification.\n•\tExpertise in Out-of-Order CPUs, Memory Subsystems, Cache Coherency, or Execution Units.\n•\tStrong understanding of performance, power, security, and quality tradeoffs.\n•\tExperience driving AI/ML-based validation methodologies and automation initiatives.\n•\tProven track record of building high-performing organizations and developing future leaders.\n•\tStrong executive communication and stakeholder management skills.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Silicon Packaging Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-26", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Silicon-Packaging-Design-Engineer_JR0288609", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nDefine packaging solutions for highly innovative integrated circuits, meeting adequate mechanical, thermal and electrical performance with the goal to achieve lowest package and system level cost.\nCo-design with chip designer, system engineering and PCB design teams during the development stage to optimize pad layout and pin map for most cost effective package and system.\nIndependently plan, design and develop quality custom lead frame/substrate/module with supporting electrical simulation to reduce cross-talk, IR drop, and noise issues of the device.\nTechnical lead for implementing packaging solutions at OSAT assembly site and/or internal assembly site. Ensure optimized package design which meets the assembly design rules of the selected assembly site. Work with the assembly partner to mitigate any potential risk and improve situation to meet yield target within the project milestone requirement.\nCo-work with NPI manager to prepare assembly site readiness for continuous uninterrupted flow from wafer fab-out to quality packaged sample meeting the required NPI schedule.\nMaintain complete set of product specific packaging related drawings, and reports.\n\nQualifications:\nBachelor / Master degree in Electrical Engineering / Mechanical Engineering / Material Science with more than 10 years experience in the field of IC Packaging Design and Layout.\nPackage design experience using Siemens Xpedition EDA tool set is a must.\nUnderstand performance and cost trade-offs for different layout and assembly rules.\nExtensive manufacturing process knowledge regarding wafer bumping, substrate and lead frame manufacturing and assembly of wire bond and flip chip packages is required.\nPractical knowledge of Signal integrity and Power integrity in PCB design will be an advantage.\nPossesses good analytical, communication and organization skills.\n          \n\nJob Type:\nIntel Contract Employee\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Silicon Packaging Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-26", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Silicon-Packaging-Design-Engineer_JR0288608", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nDefine packaging solutions for highly innovative integrated circuits, meeting adequate mechanical, thermal and electrical performance with the goal to achieve lowest package and system level cost.\nCo-design with chip designer, system engineering and PCB design teams during the development stage to optimize pad layout and pin map for most cost effective package and system.\nIndependently plan, design and develop quality custom lead frame/substrate/module with supporting electrical simulation to reduce cross-talk, IR drop, and noise issues of the device.\nTechnical lead for implementing packaging solutions at OSAT assembly site and/or internal assembly site. Ensure optimized package design which meets the assembly design rules of the selected assembly site. Work with the assembly partner to mitigate any potential risk and improve situation to meet yield target within the project milestone requirement.\nCo-work with NPI manager to prepare assembly site readiness for continuous uninterrupted flow from wafer fab-out to quality packaged sample meeting the required NPI schedule.\nMaintain complete set of product specific packaging related drawings, and reports.\n\nQualifications:\nBachelor / Master degree in Electrical Engineering / Mechanical Engineering / Material Science with more than 10 years experience in the field of IC Packaging Design and Layout.\nPackage design experience using Siemens Xpedition EDA tool set is a must.\nUnderstand performance and cost trade-offs for different layout and assembly rules.\nExtensive manufacturing process knowledge regarding wafer bumping, substrate and lead frame manufacturing and assembly of wire bond and flip chip packages is required.\nPractical knowledge of Signal integrity and Power integrity in PCB design will be an advantage.\nPossesses good analytical, communication and organization skills.\n          \n\nJob Type:\nIntel Contract Employee\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Silicon Design Verification Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-26", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Silicon-Design-Verification-Engineer_JR0288280", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nCome join Intel's Devices Development Group, responsible for creating leading Client SOCs. We envision the future of computing and design for the next generation of laptop and desktop computers. We are looking for a ready to research, design, develop, and test Intel designs as we reimagine how to build SOCs at Intel and in the semiconductor industry. Our bold purpose as a company is to 'create world-changing technology that enriches the lives of every person on earth' and this role is instrumental in furthering our mission to shape the future of technology.\n\nResponsibilities may include but not be limited to:\n\n- Validation of an IP or feature, either directly or at the system level\n- Creating plans and tests for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide\n- Learning the architecture and microarchitecture by debugging failures to the root cause\n- Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design\n- Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models\n- Engaging with IP providers and customers to define, develop and deliver necessary infrastructure and address issues found during execution\n- Developing tools and methods to streamline IP development and SOC integration to deliver highest quality in shortest time possible\n- Developing debugging tools and software\n- Validation of a Power Management IP or feature, either directly or at the system level\n\nQualifications:\nYou must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.\n\nMinimum Qualifications:\n\n- Must have either a BS + 4 years' experience or MS + 3 years' experience in Computer Science, Computer Engineering or Electrical Engineering\n- Minimum 3 years' experience with reading and interpreting technical specs and Register Transfer Level (RTL) code\n- Minimum 3 years' experience working on IP or SoC development, verification, or integration using Verilog/SystemVerilog/OVM/UVM\n- Minimum 3 years' experience with writing validation plans and software to implement those validation plans\n- Minimum 1 year experience with UNIX or Linux\n- Knowledge on Power Aware verification \n- Knowledge on clock gating and power gating \n\nPreferred Qualifications:\n\n- Minimum 1 year experience with computer architecture\n- Minimum 1 year experience with IA-32 assembly and/or Verilog programming experience\n- Minimum 2 years' experience with validation or testing experience, especially in a silicon design team\n-Minimum 3 years' experience working on Power Management IP, PM Firmware, or PM SoC development, verification, or integration using Verilog/SystemVerilog/OVM/UVM\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Senior Design Verification Engineer (IP)", "company": "Lattice", "location": "Penang, Malaysia", "date_posted": "2026-10-26", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Penang-Malaysia/Senior-Design-Verification-Engineer--IP-_R-103524", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nJob Summary: \n \nThere is energy here…energy you can feel crackling at any of our international locations.  It’s an energy generated by enthusiasm for our work, for our teams, for our results and for our customers.  Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing and support teams, who are developing programmable logic solutions that are changing the industry.  Our focus is on R&D, product innovation and customer service, and to that focus we bring total commitment and a keenly sharp competitive personality. \n\nEnergy feeds on energy.  If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.  \n \nLattice Semiconductor is seeking a senior Design Verification Engineer to join the RnD organization. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn and grow.\n\nResponsibilities & Skills:\nWe are seeking a Senior IP DV engineer with significant hands-on experience in pre-silicon Design verification, verification methodologies and UVM.\nDevelop and Review Comprehensive Test Plan based on design specification\nDevelop, and maintain scalable UVM-based constrained-random verification environments for complex IPs\nCreate test cases, sequences, scoreboards, checkers, and assertions based on testplan and drive verification execution from planning through coverage closure and sign-off.\nAnalyze failures and perform root-cause debugging of design and verification issues.\nCollaborate closely with design, architecture, system validation, and application teams to resolve functional and performance issues and customer escapes.\nContribute to verification methodology improvements, automation initiatives, and best practices across the team.\n \nRequirements:\nGood understanding of verification process from test plan through coverage closure and sign-off\nHands-on experience with SystemVerilog and UVM verification methodologies.\nExperience developing constrained-random verification environments for complex digital designs.\nStrong debugging, analytical, and problem-solving skills.\nExcellent communication and teamwork skills in a cross-functional and geographically distributed environment.\nStrong communication and Analytical skills\nGood understanding of HDL (Verilog, SystemVerilog)\nExperience with designing with FPGA is a plus\nProficiency in at least one scripting or programming language such as Python, Tcl, Perl, or C/C++.\nExperience in one or more of the following areas is highly desirable: High speed Interface Protocols (Ethernet, PCIe, CPRI or JESD204B/C, USB), Memory (DRAM, SRAM, Flash, DMA), Interconnect (AMBA AXI, AHB, APB), Peripherals (SPI, I2C or I3C)\n \nEducation and General:\nBS/MS/PhD in Electrical Engineering, Electronics Engineering, Computer Engineering\nMinimum 5+ years of hands-on Design Verification experience using SystemVerilog and UVM.\nIndependent, self-motivated, and capable of delivering results in a dynamic environment with evolving priorities.\n \nLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.\n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.\n \nLattice\nFeel the energy.\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nMalaysiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Staff EDA Engineer", "company": "Lattice", "location": "Pune, India", "date_posted": "2026-10-26", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Pune-India/Staff-EDA-Engineer_R-103374", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\n\nLattice is seeking a Senior CAD/EDA Engineer with deep expertise in Static Timing Analysis (STA), Place and Route (PNR), and hierarchical timing abstraction using Extracted Timing Models (ETM) and Quick Timing Models (QTM), to join our CAD/EDA Engineering group in Pune, India. Qualified candidates must hold a BS or MS degree in EE, ECE, or CoE with 8 to 12 years of industry experience on 5, 7, 16, or 28 nm process technology nodes. This individual will be a key driver in developing, deploying, and supporting the logic and digital design implementation and signoff methodologies and flows across the company's FPGA product lines\n\nThe candidate's general responsibilities include the following:\nStatic Timing Analysis and Signoff\nOwn and maintain the multi-corner multi-mode (MCMM) STA signoff methodology, including constraint development, timing closure criteria, and signoff sign-check automation.\nDevelop and support timing signoff flows using Synopsys PrimeTime, PrimeTime SI, and Cadence Tempus, covering setup, hold, recovery/removal, and transition/capacitance checks.\nDeploy advanced variation modeling methodologies including AOCV, POCV, and LVF, and define derating and margining strategies across process nodes.\nDrive crosstalk and signal integrity analysis, noise-aware timing, and correlation between implementation and signoff timing engines.\nDefine and automate SDC generation, validation, and equivalence checking across RTL, synthesis, PNR, and signoff stages.\nTiming Abstraction: ETM and QTM\nOwn the hierarchical timing model generation methodology, including ETM extraction for hardened blocks and IP, and QTM construction for blocks that are not yet implemented.\nDefine model validation and correlation procedures that quantify ETM/QTM accuracy against flat and full block timing, and establish acceptance criteria for model release.\nDevelop automation for context-aware and mode-aware model generation, interface logic model (ILM) alternatives, and model regeneration triggered by block-level ECOs.\nDrive top-level timing closure strategies that rely on abstracted models to reduce runtime and memory footprint on large hierarchical designs.\nEstablish guidance for design teams on when to apply ETM, QTM, ILM, or flat analysis, and document the accuracy and runtime trade-offs of each.\nPhysical Implementation and Place and Route\nDevelop and support physical design place and route and tape-out flows for advanced FinFET nodes (28nm, 16nm, 7 nm and below) using Cadence Innovus and/or Synopsys IC Compiler II and Fusion Compiler.\nDrive floorplanning, power planning, placement, clock tree synthesis, and routing methodology, including low-skew and clock mesh structures.\nOwn post-CTS and post-route tool ECO flows, timing and DRV closure automation, and physical-aware ECO implementation.\nSupport early IR drop and power analysis, EM/IR signoff hooks, and congestion and routability analysis within the implementation flow.\nSupport IP block and full-chip integration for designs on 5, 7, 16, and 28 nm process nodes.\nMethodology, Automation, and Support\nCreate, release, and maintain design scripts and utilities that automate EDA tool flows across physical design, timing signoff, and QA.\nDefine and implement comprehensive design QA procedures and regression test suites for the backend PNR and STA flows.\nTrack and resolve tool and technology file issues through hands-on, objective-driven engagement with foundry and EDA vendor support teams.\nDrive cross-functional initiatives and design methodology alignment across geographically distributed design and CAD/EDA teams.\nDocument and deliver training on developed methodology and EDA flows to the broader engineering organization.\nMonitor EDA industry trends and new tool capabilities by attending conferences and research forums and evaluate their applicability to Lattice flows.\nMentor junior CAD engineers and serve as an escalation point for complex timing and physical design issues.\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Electrical Engineer", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2026-10-26", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/Electrical-Engineer_R2632144-1", "is_hardware": true, "platform": "workday", "jd_text": "Who We Are\n\nApplied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI and accelerating the commercialization of next-generation semiconductor chips. Join us and push the boundaries of materials science and engineering in a company at the foundation of the electronics industry. The work we do together advances the world’s technology.\n\nWhat We Offer\n\nLocation:\nBangalore,IND\nYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. \n\nAt Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. \n \n \nAs an Electrical Engineer, you are responsible for designing, modifying, and troubleshooting electrical or electronic engineering assemblies, layouts, schematics, and drawings to advance the equipment that supports our technology. Using your technical experience and critical thinking skills, you will perform engineering analysis, generate test reports, develop innovative solutions, and create documentation for product releases. You will also coordinate the procurement and assembly of components, identify sources of critical parts, and resolve technical issues to ensure peak performance. \n \nRole Responsibilities: \nDesign or modify electrical or electronic engineering assemblies, layouts, schematics, drawings or specifications of moderate scope under general supervision \n\nPerform basic engineering analysis under general supervision \n\nPerform and generate basic engineering test reports; generate related alpha/gamma documentation for product releases \n\nCoordinate the procurement and assembly of electrical or electronic components and equipment, and identify sources of critical parts and subsystems to resolve technical issues \n\nTroubleshoot a variety of moderately complex electrical problems \n\nImplement concepts for product issues and electrical solutions of moderate difficulty \n\nAssist in the development of electrical product specifications \n\nClearly communicate complex information in straightforward situations\n\nMinimum Qualifications:\nBachelor’s degree\n\n2-4 years of related experience\n\nPreferred Qualifications:\nA solid understanding of the industry’s key business drivers  \n\nGood communication/interpersonal skills to explain complex information to others   \n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nAssignee / Regular\nTravel:\nYes, 50% of the Time\nRelocation Eligible:\nNo\n\nApplied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "Electrical Engineer", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2026-10-26", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/Electrical-Engineer_R2632145", "is_hardware": true, "platform": "workday", "jd_text": "Who We Are\n\nApplied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI and accelerating the commercialization of next-generation semiconductor chips. Join us and push the boundaries of materials science and engineering in a company at the foundation of the electronics industry. The work we do together advances the world’s technology. \n\nWhat We Offer\n\nLocation:\nBangalore,IND\nYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. \n\nAt Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. \n\nRole Responsibilities: \nDesign or modify electrical or electronic engineering assemblies, layouts, schematics, drawings or specifications of moderate scope under general supervision \n\nPerform basic engineering analysis under general supervision \n\nPerform and generate basic engineering test reports; generate related alpha/gamma documentation for product releases \n\nCoordinate the procurement and assembly of electrical or electronic components and equipment, and identify sources of critical parts and subsystems to resolve technical issues \n\nTroubleshoot a variety of moderately complex electrical problems \n\nImplement concepts for product issues and electrical solutions of moderate difficulty \n\nAssist in the development of electrical product specifications \n\nClearly communicate complex information in straightforward situations\n\nMinimum Qualifications:\nBachelor’s degree\n\n2-4 years of related experience\n\nPreferred Qualifications:\nA solid understanding of the industry’s key business drivers  \n\nGood communication/interpersonal skills to explain complex information to others  \n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nAssignee / Regular\nTravel:\nYes, 50% of the Time\nRelocation Eligible:\nNo\n\nApplied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "ASIC Methodology, Flow and Integration Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-26", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/ASIC-Methodology--Flow-and-Integration-Engineer_JR2028673", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We are now looking for ASIC Flow and Integration Engineer to drive design methodology, automation, and integration for our High Speed IO team.\n\nWhat you'll be doing:\nAs one of the primary methodology engineer, you’ll work across all NVIDIA-delivered projects, owning the integration process and collaborating with global teams to define and implement best-in-class methodologies. You’ll operate beyond RTL coding—building infrastructure and systems that are modular, reusable, and easily deployable across diverse silicon platforms. During the course of a project you would end up driving the following aspects of:\nOwn the full-chip and block-level integration process across multiple NVIDIA SoC and GPU projects.\nStitch together RTL units and ensure seamless connectivity, and hierarchy management.\nDefine and evolve internal design methodologies to improve scalability, quality, and turnaround time.\nBuild automation pipelines using Python/Perl to streamline integration, debug, and delivery.\nDevelop modular and reusable systems that can be easily delivered and adapted across different SoC and GPU architectures.\nCollaborate extensively with RTL, verification, physical design, and architecture teams to ensure flow compatibility and design readiness.\nDrive full-chip debug efforts, connectivity, and functional issues across multiple hierarchies and technology nodes.\nContribute to continuous improvement of internal standards and mentor engineers on flow usage and integration practices.\n\nWhat we need to see:\nBS or B.Tech or MS or M.tech in EE, ECE, CS, or equivalent degree with 1+ year or more experience in design integration and methodologies for ASIC design.\nComprehensive understanding of IP development flows, build flows is a must\nExcellent influencing skills resulting in collaboration with cross-cultural, multi geography and matrixed teams\nGood debugging, analytical and problem solving skills\nGreat interpersonal skills and ability to work as an excellent teammate\nWorking exposure with AI tools like Claude and Cursor would be a plus\n\nWe have some of the most brilliant and talented people in the world working for us. If you're creative and independent, with a genuine real passion for technology and improving the state of art, we want to hear from you! Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior Manager - SoC Verification", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-26", "url": "https://careers.synopsys.com/job/bengaluru/senior-manager-soc-verification/44408/102470445616", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Title:SoC Verification - Senior Manager\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent over a decade in SoC verification, and somewhere along the way you realized that the hardest part of the job is not just catching bugs, it is building a team that catches them before they become expensive problems. You know what good verification looks like because you have written testbenches, debugged waveforms at 2 a.m., and closed coverage gaps on complex subsystems yourself. Now you lead teams through that same work, and you are good at it.\nYou understand customer engagements are not internal projects. Scope creeps, requirements shift, and timelines compress. You have learned to read between the lines when a customer says 'we need verification support' and figure out what they actually need, then translate that into a plan your team can execute without drama.\nManaging seven engineers across multiple projects means you spend your day context-switching between technical reviews, customer calls, and mentoring conversations. You do not micromanage, but you also do not disappear. You know when to step in and when to let someone work through a problem. At Synopsys, you will lead verification work that directly enables customers building chips for AI, automotive, aerospace, and high-performance computing. The work is real, the customers are demanding, and your team will depend on you to keep it all moving.\nWhat You'll Be Doing\nLead and manage a team of 7-8 SoC and subsystem verification engineers working on customer engagements across automotive, aerospace, defense, and high-performance computing domains\nWork directly with Synopsys customers to scope verification activities, define deliverables, and translate their technical challenges into actionable verification plans\nAssess project complexity and resource needs, then propose staffing and timeline plans that actually hold up under execution pressure\nMentor engineers daily on verification methodology, debug strategies, coverage closure, and customer communication, growing their technical depth for future assignments\nReview testbench code, verification plans, coverage reports, and waveform analysis to provide feedback that improves quality before deliverables go to the customer\nReport project status to senior management, flag risks early, and work through execution issues with peers and stakeholders across SSG, sales, and business unit application engineering teams\nDrive adoption of Synopsys verification tools including VCS, Verdi, and Synopsys VIP within customer projects, and collaborate with internal teams to refine methodology and improve efficiency\nThe Impact You Will Have\nYour team will deliver verification solutions that enable customers to tape out complex SoCs on schedule, directly affecting product launches in AI, automotive, and aerospace markets\nThe engineers you mentor will grow into technical leads and customer-facing verification experts, strengthening Synopsys capability to take on larger, more complex engagements\nYour project scoping and resource planning will determine whether customer engagements stay on track or slip, affecting both customer satisfaction and SSG revenue\nThe verification methodology improvements you drive will be reused across future projects, compounding efficiency gains across the entire Systems Solutions Group\nYour ability to translate customer needs into clear verification scope will shape how Synopsys tools and IP get deployed in real-world SoC projects\nThe quality standards you enforce will define what customers expect from Synopsys verification services, setting the bar for future engagements\nYour collaboration with sales and AE teams will help position SSG for new customer opportunities and expand the types of verification work Synopsys can take on\nWhat You'll Need\nBachelor's or Master's in Electronics Engineering or related field with 12+ years of hands-on experience in SoC verification\nDeep technical expertise across pre-silicon verification including UVM testbench development, coverage analysis, verification planning, and complex debug using waveform tools\nStrong working knowledge of industry-standard protocols such as PCIe, Ethernet, USB, DDR, and familiarity with processor, interconnect, or debug architectures\nProven hands-on experience with VCS, Verdi or similar waveform analyzers, and integration of third-party VIP including Synopsys VIP\nDemonstrated ability to lead verification teams through complex SoC, subsystem, or IP verification projects from planning through delivery\nExperience managing verification scope, timelines, and resources for customer-facing projects or service engagements is a strong plus\nSolid understanding of ASIC design flows, RTL design concepts, and how verification fits into the broader chip development lifecycle\nWho You Are\nYou can walk into a customer meeting, listen to a vague request for 'verification support,' and walk out with a concrete scope, timeline, and resource plan that your team can actually execute\nYou review a coverage report or testbench and immediately spot what is missing, not just technically but strategically, and you explain it in a way that helps the engineer see it too\nYou manage multiple projects without losing track of details, and your team knows you will catch issues before they escalate to the customer or senior management\nYou push back when a customer asks for something unrealistic or when internal stakeholders propose a plan that will not work, and you do it in a way that keeps the relationship intact\nYou communicate clearly with engineers, customers, and executives, adjusting your level of detail depending on who is in the room without oversimplifying or overcomplicating\nYou treat mentoring as part of the job, not an extra task, and engineers on your team get better at verification because you invest time in their growth\nThe Team You'll Be Part Of\nYou will join the System Solutions Group (SSG), a team that delivers end-to-end SoC design and verification services to Synopsys customers. SSG works on everything from subsystem blocks to full turnkey SoCs, serving customers that range from startups to industry leaders across high-performance computing, automotive, aerospace, and defense. Your verification team will collaborate closely with architects, RTL designers, and post-silicon teams, and you will work alongside peers in other SSG functions, sales, and Synopsys business unit application engineering teams to deliver customer engagements and refine internal methodology.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Architect - ASIC Digital IP Verification (Ethernet)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-26", "url": "https://careers.synopsys.com/job/bengaluru/architect-asic-digital-ip-verification-ethernet/44408/102470445600", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nAn experienced and highly skilled ASIC Digital Verification Engineer with a passion for ensuring the highest quality in digital design. You have a deep understanding of verification methodologies and are proficient in using advanced verification tools and techniques. Your expertise allows you to work independently, taking on complex challenges and delivering innovative solutions. You are detail-oriented, with a strong analytical mindset, and can communicate effectively with various stakeholders. Your ability to mentor and lead junior engineers is a testament to your extensive experience in the field. You thrive in a collaborative environment and are committed to continuous learning and improvement.\nWhat You’ll Be Doing:\nDesigning, implementing and optimizing verification environments to ensure the correctness of Interface IP protocols.\nCreating, executing and tracking against detailed test plans to verify complex ASIC designs.\nDeveloping and maintaining verification IP and testbenches using System Verilog and UVM.\nCollaborating with design and architecture teams identifying fix bugs.\nPerforming functional coverage analysis and driving coverage closure.\nMentoring and guiding junior verification engineers in best practices and methodologies.\nThe Impact You Will Have:\nEnsuring the delivery of high-quality, reliable ASIC designs that meet customer specifications.\nEnhancing the robustness and efficiency of our verification processes and methodologies.\nContributing to the successful launch of Interface IP products, impacting various industries.\nDriving innovation and excellence within the verification team.\nImproving the overall performance and functionality of Synopsys' IP offerings.\nFostering a culture of continuous improvement and technical excellence.\nWhat You’ll Need:\nExtensive experience with 12+ years in ASIC digital verification, specifically with Interface IP protocols, such as PCIe, CXL, DDR, Ethernet, AMBA (CHI, AXI, AHB, APB).\nProficiency in System Verilog, SVA and UVM methodologies.\nStrong understanding of digital design and verification concepts.\nFamiliarity with wider digital ASIC and IP development flow, including RTL design through synthesis.\nExperience with simulation tools such as VCS, Model Sim, or similar.\nStrong analytical and problem-solving skills, with the ability to tackle complex and unique design challenges.\nExcellent communication skills, with the ability to effectively collaborate with cross-functional teams and stakeholders.\nWho You Are:\nDetail-oriented with a strong analytical mindset.\nExcellent communicator, able to convey complex technical concepts clearly.\nCollaborative team player who thrives in a dynamic environment.\nProactive and self-motivated, with a commitment to continuous learning.\nMentor and leader, capable of guiding and developing junior engineers.\nThe Team You’ll Be A Part Of:\nYou will be part of a highly skilled and motivated verification team focused on delivering cutting-edge Interface IP solutions. The team is dedicated to maintaining the highest standards of quality and performance, working collaboratively to tackle complex verification challenges. You will have the opportunity to work alongside industry experts and contribute to the development of next-generation technologies.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "ASIC Digital Design , Sr Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-26", "url": "https://careers.synopsys.com/job/bengaluru/asic-digital-design-sr-staff-engineer/44408/102455703440", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years building RTL that ships in silicon, not just passes simulation. When you read a protocol specification, you see the corner cases that will break three months into verification, and you architect around them before anyone else notices. You are comfortable taking a huge page Ethernet spec and walking out with a micro-architecture that balances latency, power, and area without needing someone to hold your hand. You write Verilog that other engineers can actually read and maintain. Debugging asynchronous FIFO issues and CDC violations has taught you what good design discipline looks like, and you hold yourself to it even when schedules get tight. Multi-site collaboration does not slow you down. You can review someone's RTL in a different timezone, leave clear feedback, and move the design forward without waiting for a meeting. At Synopsys, you will work on IP cores that power everything from AI accelerators to automotive systems, and the designs you own will matter.\nWhat You'll Be Doing\nDesign and code RTL for high-speed Ethernet IP cores ranging from 100G to 1.6T, focusing on low latency and timing closure in complex datapath and control logic\nTranslate protocol specifications and functional requirements into micro-architecture and detailed design documents for DesignWare IP in Ethernet, AMBA AXI, CHI, PCIe, USB, MIPI, or memory controller domains\nBuild and refine directed Verilog testbenches to improve functional and code coverage, analyzing metrics and defining targeted test cases that catch real bugs\nPerform technical reviews of functional specs, micro-architecture documents, and RTL code from peers across global design teams\nDrive timing analysis and closure for high-speed designs using synthesis, STA, lint, CDC, and formal verification flows\nApply low power design methodologies and automotive safety requirements to IP development\nCollaborate with verification, integration, and product teams across Bangalore, the US, and other global sites to deliver production-quality IP on schedule\nThe Impact You Will Have\nYour RTL will ship in customer SoCs powering data center infrastructure, automotive platforms, and AI systems used by millions of people\nThe micro-architecture decisions you make today will determine whether a customer's chip meets their performance and power targets six months from now\nYour coverage improvements and directed tests will catch silicon bugs before tapeout, saving customers months of respins and lost revenue\nThe design quality and documentation you deliver will set the standard for how the rest of the IP team approaches complex protocol implementations\nYour timing closure work on multi-gigabit interfaces will enable Synopsys to stay ahead in the race toward higher-speed Ethernet and interconnect IP\nThe technical reviews you provide will level up junior engineers and prevent architectural mistakes from becoming costly late-stage fixes\nYour ability to work across sites will keep globally distributed projects on track and reduce friction in cross-functional handoffs\nWhat You'll Need\nBachelor's in Electrical Engineering with 8+ years of hands-on ASIC or IP design experience, or Master's with 6+ years\nDeep RTL design experience on IP cores or SoC subsystems that have taped out or shipped to customers\nStrong working knowledge of at least one protocol from this list: AMBA (AHB, AXI, CHI), SD, eMMC, DDR, PCIe, USB, MIPI. High-speed Ethernet (100G and above) experience is a strong plus\nProven ability to create micro-architecture and detailed design documents from functional specs for small to medium complexity blocks, especially control-path designs like async FIFOs, DMA engines, or SRAM/DPRAM interfaces\nHands-on experience with Verilog or SystemVerilog, simulation tools, synthesis flows, static timing analysis, lint, CDC, and formal verification tools\nSolid understanding of high-speed, low-latency design techniques and timing closure challenges. Experience with datapath designs or arithmetic algorithms like FEC is a plus\nFamiliarity with Perforce or similar version control systems, and scripting in Perl or shell for automation\nWho You Are\nYou can take a vague feature request and turn it into a clean, implementable design without needing three rounds of clarification meetings\nWhen you review RTL, you catch the subtle issues that would have caused problems in integration, and you explain them clearly enough that the engineer learns something\nYou know how to prioritize when you are juggling timing closure, coverage improvements, and a design review scheduled for tomorrow, and nothing falls through the cracks\nYou communicate technical tradeoffs in writing and in review meetings with enough clarity that engineers in other timezones can act on your feedback without a follow-up call\nYou push back when a spec is ambiguous or a schedule does not account for real design complexity, and you do it in a way that moves the conversation forward\nYou treat documentation as part of the design, not an afterthought, because you know the next person reading your micro-arch doc might be you in six months\nThe Team You'll Be Part Of\nYou will join the IPG Group at the Bangalore Design Center as a technical individual contributor working on DesignWare IP cores. This is a multi-site team spread across global locations, focused on delivering high-speed protocol IP in areas like Ethernet, AMBA, PCIe, USB, MIPI, and memory controllers. The work is technically challenging, the designs are complex, and the team expects you to own your deliverables with minimal supervision while collaborating across timezones to hit shared milestones.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "R&D Engineering, Sr Manager", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-26", "url": "https://careers.synopsys.com/job/bengaluru/r-and-d-engineering-sr-manager/44408/102484804608", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in the trenches of ASIC verification, and somewhere along the way you realized that emulation is not just another tool in the flow, it is the thing that makes or breaks your ability to ship complex IP on time. You know PCIe or DDR inside and out, not just the spec but the weird corner cases, the errata that nobody talks about, and the places where emulation models fall short of what the design team actually needs.\nYou have worked on Zebu or similar platforms long enough to know what good emulation IP looks like and what happens when it is not quite right. You have closed that gap before, probably more than once, and you know how to do it without creating chaos for the teams depending on your work. You are comfortable sitting with a design team in Bangalore, a verification lead in California, and an IP product manager in Europe, and walking out with a plan that everyone believes in.\nYou do not wait for perfect alignment. You ask the right questions, you push back when something does not make sense, and you move. At Synopsys, you will work on IP that powers the next generation of silicon, and the emulation strategies you define will directly affect how fast we get there.\nWhat You'll Be Doing\nBridge the gap between Emulation IP capabilities and Design IP verification needs across both Controller and PHY domains for high speed interfaces like PCIe and DDR\nDefine technical requirements for Emulation IP, working directly with IP development and verification teams to ensure correct implementation and deployment on Zebu platforms\nTrack and report key metrics on Emulation IP quality, performance, and coverage, driving continuous improvement across verification workflows\nStay ahead of evolving PCIe and DDR standards, interpret specification updates, ECNs, and errata, and translate those into actionable changes for both Emulation and Design IP teams\nReview and validate test plans for Emulation IP and Design IP, ensuring completeness, traceability, and alignment with product quality goals\nCollaborate cross-functionally with verification, design, product, and platform teams to optimize emulation methodologies and standardize best practices\nMentor engineers on emulation strategies, verification techniques, and IP development workflows\nThe Impact You Will Have\nAccelerate time to market for high performance IP by defining emulation strategies that catch issues earlier and reduce silicon respins\nElevate product quality across Synopsys IP portfolios by ensuring Emulation IP meets the real needs of design and verification teams\nDrive adoption of best in class emulation and verification methodologies that become standard practice across the organization\nInfluence the next generation of emulation solutions and workflows, positioning Synopsys as a leader in pre-silicon validation\nImprove cross-functional collaboration and alignment between geographically distributed teams, reducing friction and rework\nStandardize verification workflows and metrics, making it easier for teams to track progress, identify gaps, and deliver with confidence\nShape how Synopsys develops and deploys Emulation IP for cutting edge digital designs and system architectures\nWhat You'll Need\n15+ years of hands-on experience in emulation, pre-silicon verification, or IP product development\nExpert-level knowledge of PCIe or DDR interfaces, including protocol details, verification strategies, and real-world implementation challenges\nExtensive experience with Zebu or similar emulation platforms, specifically for IP verification and system-level validation\nProven track record leading IP product development initiatives with a strong focus on emulation and verification\nDemonstrated ability to work cross-functionally in matrixed, global teams and drive consensus across diverse stakeholders\nStrong communication skills with the ability to influence technical direction and inspire change across engineering teams\nComfort working in dynamic, ambiguous environments where requirements evolve and priorities shift\nWho You Are\nYou can walk into a room where the Emulation IP does not quite match what the design team needs and walk out with a concrete plan to close the gap without derailing either team's schedule\nYou do not need someone to tell you what the next version of the PCIe or DDR spec means for your work, you read it, figure out the implications, and start the conversation with your team\nYou are the person people come to when emulation results do not make sense, and you know how to debug across the boundary between emulation models, RTL, and test environments\nYou push back when a test plan looks complete on paper but is missing coverage for the cases that actually matter in production\nYou are comfortable mentoring engineers who are newer to emulation or IP verification, and you do it in a way that builds their confidence and capability\nYou stay organized across multiple workstreams, stakeholders, and time zones without losing track of what matters most\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior Staff Emulation Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-26", "url": "https://careers.synopsys.com/job/bengaluru/senior-staff-emulation-engineer/44408/102484804080", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in the trenches of ASIC verification, and somewhere along the way you realized that emulation is not just another tool in the flow, it is the thing that makes or breaks your ability to ship complex IP on time. You know PCIe or DDR inside and out, not just the spec but the weird corner cases, the errata that nobody talks about, and the places where emulation models fall short of what the design team actually needs.\nYou have worked on Zebu or similar platforms long enough to know what good emulation IP looks like and what happens when it is not quite right. You have closed that gap before, probably more than once, and you know how to do it without creating chaos for the teams depending on your work. You are comfortable sitting with a design team in Bangalore, a verification lead in California, and an IP product manager in Europe, and walking out with a plan that everyone believes in.\nYou do not wait for perfect alignment. You ask the right questions, you push back when something does not make sense, and you move. At Synopsys, you will work on IP that powers the next generation of silicon, and the emulation strategies you define will directly affect how fast we get there.\nWhat You'll Be Doing\nBridge the gap between Emulation IP capabilities and Design IP verification needs across both Controller and PHY domains for high speed interfaces like PCIe and DDR\nDefine technical requirements for Emulation IP, working directly with IP development and verification teams to ensure correct implementation and deployment on Zebu platforms\nTrack and report key metrics on Emulation IP quality, performance, and coverage, driving continuous improvement across verification workflows\nStay ahead of evolving PCIe and DDR standards, interpret specification updates, ECNs, and errata, and translate those into actionable changes for both Emulation and Design IP teams\nReview and validate test plans for Emulation IP and Design IP, ensuring completeness, traceability, and alignment with product quality goals\nCollaborate cross-functionally with verification, design, product, and platform teams to optimize emulation methodologies and standardize best practices\nMentor engineers on emulation strategies, verification techniques, and IP development workflows\nThe Impact You Will Have\nAccelerate time to market for high performance IP by defining emulation strategies that catch issues earlier and reduce silicon respins\nElevate product quality across Synopsys IP portfolios by ensuring Emulation IP meets the real needs of design and verification teams\nDrive adoption of best in class emulation and verification methodologies that become standard practice across the organization\nInfluence the next generation of emulation solutions and workflows, positioning Synopsys as a leader in pre-silicon validation\nImprove cross-functional collaboration and alignment between geographically distributed teams, reducing friction and rework\nStandardize verification workflows and metrics, making it easier for teams to track progress, identify gaps, and deliver with confidence\nShape how Synopsys develops and deploys Emulation IP for cutting edge digital designs and system architectures\nWhat You'll Need\n8+ years of hands-on experience in emulation, pre-silicon verification, or IP product development\nExpert-level knowledge of PCIe or DDR interfaces, including protocol details, verification strategies, and real-world implementation challenges\nExtensive experience with Zebu or similar emulation platforms, specifically for IP verification and system-level validation\nProven track record leading IP product development initiatives with a strong focus on emulation and verification\nDemonstrated ability to work cross-functionally in matrixed, global teams and drive consensus across diverse stakeholders\nStrong communication skills with the ability to influence technical direction and inspire change across engineering teams\nComfort working in dynamic, ambiguous environments where requirements evolve and priorities shift\nWho You Are\nYou can walk into a room where the Emulation IP does not quite match what the design team needs and walk out with a concrete plan to close the gap without derailing either team's schedule\nYou do not need someone to tell you what the next version of the PCIe or DDR spec means for your work, you read it, figure out the implications, and start the conversation with your team\nYou are the person people come to when emulation results do not make sense, and you know how to debug across the boundary between emulation models, RTL, and test environments\nYou push back when a test plan looks complete on paper but is missing coverage for the cases that actually matter in production\nYou are comfortable mentoring engineers who are newer to emulation or IP verification, and you do it in a way that builds their confidence and capability\nYou stay organized across multiple workstreams, stakeholders, and time zones without losing track of what matters most\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior Staff Emulation Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-26", "url": "https://careers.synopsys.com/job/bengaluru/senior-staff-emulation-engineer/44408/102484804000", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in the trenches of ASIC verification, and somewhere along the way you realized that emulation is not just another tool in the flow, it is the thing that makes or breaks your ability to ship complex IP on time. You know PCIe or DDR inside and out, not just the spec but the weird corner cases, the errata that nobody talks about, and the places where emulation models fall short of what the design team actually needs.\nYou have worked on Zebu or similar platforms long enough to know what good emulation IP looks like and what happens when it is not quite right. You have closed that gap before, probably more than once, and you know how to do it without creating chaos for the teams depending on your work. You are comfortable sitting with a design team in Bangalore, a verification lead in California, and an IP product manager in Europe, and walking out with a plan that everyone believes in.\nYou do not wait for perfect alignment. You ask the right questions, you push back when something does not make sense, and you move. At Synopsys, you will work on IP that powers the next generation of silicon, and the emulation strategies you define will directly affect how fast we get there.\nWhat You'll Be Doing\nBridge the gap between Emulation IP capabilities and Design IP verification needs across both Controller and PHY domains for high speed interfaces like PCIe and DDR\nDefine technical requirements for Emulation IP, working directly with IP development and verification teams to ensure correct implementation and deployment on Zebu platforms\nTrack and report key metrics on Emulation IP quality, performance, and coverage, driving continuous improvement across verification workflows\nStay ahead of evolving PCIe and DDR standards, interpret specification updates, ECNs, and errata, and translate those into actionable changes for both Emulation and Design IP teams\nReview and validate test plans for Emulation IP and Design IP, ensuring completeness, traceability, and alignment with product quality goals\nCollaborate cross-functionally with verification, design, product, and platform teams to optimize emulation methodologies and standardize best practices\nMentor engineers on emulation strategies, verification techniques, and IP development workflows\nThe Impact You Will Have\nAccelerate time to market for high performance IP by defining emulation strategies that catch issues earlier and reduce silicon respins\nElevate product quality across Synopsys IP portfolios by ensuring Emulation IP meets the real needs of design and verification teams\nDrive adoption of best in class emulation and verification methodologies that become standard practice across the organization\nInfluence the next generation of emulation solutions and workflows, positioning Synopsys as a leader in pre-silicon validation\nImprove cross-functional collaboration and alignment between geographically distributed teams, reducing friction and rework\nStandardize verification workflows and metrics, making it easier for teams to track progress, identify gaps, and deliver with confidence\nShape how Synopsys develops and deploys Emulation IP for cutting edge digital designs and system architectures\nWhat You'll Need\n8+ years of hands-on experience in emulation, pre-silicon verification, or IP product development\nExpert-level knowledge of PCIe or DDR interfaces, including protocol details, verification strategies, and real-world implementation challenges\nExtensive experience with Zebu or similar emulation platforms, specifically for IP verification and system-level validation\nProven track record leading IP product development initiatives with a strong focus on emulation and verification\nDemonstrated ability to work cross-functionally in matrixed, global teams and drive consensus across diverse stakeholders\nStrong communication skills with the ability to influence technical direction and inspire change across engineering teams\nComfort working in dynamic, ambiguous environments where requirements evolve and priorities shift\nWho You Are\nYou can walk into a room where the Emulation IP does not quite match what the design team needs and walk out with a concrete plan to close the gap without derailing either team's schedule\nYou do not need someone to tell you what the next version of the PCIe or DDR spec means for your work, you read it, figure out the implications, and start the conversation with your team\nYou are the person people come to when emulation results do not make sense, and you know how to debug across the boundary between emulation models, RTL, and test environments\nYou push back when a test plan looks complete on paper but is missing coverage for the cases that actually matter in production\nYou are comfortable mentoring engineers who are newer to emulation or IP verification, and you do it in a way that builds their confidence and capability\nYou stay organized across multiple workstreams, stakeholders, and time zones without losing track of what matters most\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior Software Engineer - Jira Workflows and Automation", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-10-26", "url": "https://careers.arm.com/job/bengaluru/senior-software-engineer-jira-workflows-and-automation/33099/100168579712", "is_hardware": true, "platform": "talentbrew", "jd_text": "Role Overview\nAs a Senior Software Engineer, you will work closely with the Technical Lead to develop and support engineering workflow solutions built on the Atlassian platform. You will chip in to JIRA workflow automation, dashboard development, data analytics, and engineering process improvements that enable efficient execution across semiconductor development teams.\nThis role provides an opportunity to gain experience working with multi-functional engineering organizations while building software solutions that improve engineering productivity and execution visibility.\nResponsibilities:\nJIRA Configuration & Automation\nSupport the implementation of JIRA workflows, issue types, screens, automation rules, and project configurations. Assist in maintaining engineering processes, defect tracking, and workflow standardization under the guidance of the Technical Lead.\nSoftware Development\nDevelop scripts, utilities, and automation using Python and SQL to extract, validate, and process engineering data from Atlassian databases and REST APIs. Chip in to custom integrations with engineering tools and reporting systems.\nDashboard & UI Development\nDevelop and maintain web-based dashboards and user interfaces that visualize project health, engineering metrics, defect trends, and execution status. Work with modern web technologies to enhance usability and user experience.\nData Analytics\nAssist in building reporting pipelines, generating engineering metrics, validating data quality, and creating dashboards that provide actionable insights for engineering and program teams.\nCollaboration\nWork with Design, Verification, Implementation, Validation, Power, Performance, Software, and Program Management teams to understand workflow requirements, support issue resolution, and continuously improve engineering processes.\nRequired Skills and Experience :\n5+ Year of relevant experience.\nBachelor’s degree or equivalent experience in Computer Science, Electronics, Information Technology, or a related field.\nGood programming skills in Python and SQL.\nBasic understanding of databases, REST APIs, and software development practices.\nFamiliarity with web technologies such as HTML, CSS, JavaScript, React, or similar frameworks.\nExposure to JIRA and Confluence is desirable.\nStrong analytical, problem-solving, and communication skills.\nWillingness to learn enterprise workflow automation and engineering process development.\n“Nice To Have” Skills and Experience :\nKnowledge of Agile development methodologies.\nBasic understanding of the semiconductor or SoC development lifecycle.\nExposure to PostgreSQL, Git, Flask/FastAPI, or similar technologies.\nInterest in data visualization, dashboards, and engineering analytics.\nIn Return:\nJoining Arm means becoming part of a collaborative engineering community where you’ll be supported throughout your career. We invest in learning, mentoring, and professional development so you can continue building your technical expertise while working on technology that powers billions of devices worldwide.\nYou’ll have opportunities to:\nLearn from extraordinary engineers across hardware and software.\nWork on latest SoC and low-power technologies.\nBuild software, automation, and data solutions used across Arm engineering.\nGain experience across the complete silicon development lifecycle.\nGrow your career through technical mentoring, training, and multi-functional collaboration.\n#LI-KR2\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "SoC PnP Architect", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-10-26", "url": "https://careers.arm.com/job/bengaluru/soc-pnp-architect/33099/102455064496", "is_hardware": true, "platform": "talentbrew", "jd_text": "4+ years of experience in SoC PnP Architecture within the semiconductor industry, with a strong track record of driving system-level performance, power, and efficiency investigations across complex silicon platforms.\n \nStrong expertise in SoC performance architecture and pre-silicon performance analysis, including:\nHands-on experience with simulation and hardware emulation platforms such as Palladium, Veloce, ZeBu, or equivalent\nPerformance analysis using cycle-accurate, transaction-level, and emulation-based environments\nWaveform-based debug and signal-level performance analysis\nLatency, bandwidth, throughput, QoS, and utilization characterization\nTransaction-level tracing and protocol debug across CHI, AXI, PCIe, CXL, or equivalent system protocols\nIdentification of system-level bottlenecks across compute, interconnect, memory, and IO subsystems\nArchitectural tradeoff analysis across performance, power, area, latency, bandwidth, and implementation complexity\nStrong experience with SOC Performance and Power modeling methodologies, including:\nDevelopment and use of SystemC/TLM, analytical, trace-driven architecture models\nBuilding and calibrating models for performance, power, latency, bandwidth, utilization, and efficiency analysis\nModel-to-silicon correlation, including alignment of pre-silicon projections, emulation results, and post-silicon measurements\nEarly-stage architecture exploration to evaluate performance, power, area, thermal, TDP, and efficiency tradeoffs\nUsing models to guide SoC architecture decisions, IP configuration, memory/interconnect sizing, QoS strategy, and platform-level optimization\nAbility to translate modeling insights into clear architectural recommendations and measurable product improvements\nExtensive experience in post-silicon performance and power characterization, including:\nSilicon bring-up support from a performance and PnP perspective\nPerformance counter, PMU, telemetry, and trace-driven investigations\nCorrelation of pre-silicon projections, architectural models, and silicon measurements\nRoot-cause analysis of performance gaps, power inefficiencies, and workload-level bottlenecks\nSystem-level performance tuning under real silicon constraints\nAnalysis of workload behavior under power, thermal, voltage, frequency, and TDP limits\nStrong understanding of SoC system infrastructure and platform-level PnP behavior, including:\nCoherent interconnect fabrics and cache-coherency protocols\nDDR memory subsystems, memory controller behavior, scheduling, QoS, and bandwidth efficiency\nIO subsystems including PCIe, CXL\nPower management architecture, DVFS, clocking, voltage domains, power states, and throttling mechanisms\nProven experience working in both Linux and bare-metal environments, including:\nPerformance profiling and debug in Linux-based systems\nKernel-level performance analysis and tracing using perf, ftrace, PMU-based analysis, or equivalent tools\nLow-level bring-up, debug, and performance characterization in bare-metal environments\nUnderstanding of boot flows, firmware interactions, BIOS/UEFI or bootloader configuration, and system initialization impacts on performance and power\nAbility to debug issues across hardware, firmware, OS, driver, and workload layers\nStrong background in computer architecture and microarchitecture, including:\nCPU/GPU/NPU/DSP or accelerator performance behavior\nPipelines, cache hierarchy, prefetching, coherency, memory systems, and interconnect behavior\nSystem-level performance interactions across compute, memory, IO, and power-management blocks\nWorkload characterization and mapping of application behavior to architectural bottlenecks\nProficiency in C/C++ and Python for developing:\nPerformance and power analysis tools\nAutomation frameworks\nProfiling and telemetry infrastructure\nData analysis and visualization dashboards\nCorrelation flows across model, emulation, and silicon data\nExcellent communication and cross-functional collaboration skills, with the ability to:\nClearly present complex performance and power findings to architecture, design, verification, firmware, software, and leadership teams\nDrive data-based architectural recommendations\nInfluence SoC architecture, platform configuration, and product-level PnP decisions\nLead investigations across multiple teams and convert debug findings into architectural improvements, tuning proposals, or product guidance\n#LI-SC2\n \nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "CPU RTL Design- Sr Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-25T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720995971", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > CPU Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    8+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates complex features and functionality into hardware designs in line with proposals or roadmaps for complex products.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the novel manufacturing of solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for complex Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making is significant in nature and affects work beyond immediate work group.\n•    Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. \n•    Has a moderate amount of influence over key organizational decisions.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Principal Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-10-25", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Design-Engineer_R56509", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Description\nJob role: Analog Circuit Design\nExp: 8+ years Equivalent or Relevant\n\nEducation: BE/ B Tech/ ME/ M Tech / MS or Equivalent or Relavent\n \n· In-depth understanding of high-speed Serdes/Memory interface circuits like I/O’s,PLL’s, Clocking, Datapath’s.\n· Hands on experience on PCIe Gen3/4/5/6, GDDRx/DDRx/LPDDRx memory interface circuits.\n· Strong Analog Design and I/O Design fundamentals. Knowledge of ESD/Reliability/SI/PI.\n· Must have excellent written and verbal communication skills as well as good problem-solving skills.\n· Prior experience of working on cutting edge technology nodes like 16nm/10nm/12nm/7nm is added advantage.\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Senior Layout Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-10-25", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2507060", "is_hardware": true, "platform": "oracle", "jd_text": "Job Summary\n\nWe are seeking a motivated Analog Layout Engineer with strong hands-on experience in custom analog and mixed-signal layout development. The candidate should have a solid understanding of analog layout fundamentals, matching techniques, process understanding, and verification closure. Experience in higher-node technologies and DNW-based layouts is preferred.\n\nKey Responsibilities\n\nDevelop high-quality custom analog and mixed-signal layouts from schematics.\n\nImplement device matching, common-centroid structures, shielding, guard rings, symmetry, and parasitic-aware layout techniques.\n\nPerform layout verification and achieve clean DRC, LVS, and ERC sign-off.\n\nDebug DRC/LVS issues independently and drive closure efficiently.\n\nUnderstand and interpret process cross-sections, layer interactions, and device structures.\n\nWork closely with circuit designers to ensure proper implementation of design intent.\n\nParticipate in layout reviews and incorporate feedback for quality improvements.\n\nSupport extraction and post-layout verification activities.\n\n#LI-RG1\n\nQualifications\nRequired Skills\n\n2-3 years of hands-on analog/custom layout experience.\n\nStrong understanding of: \n\nDevice matching techniques\n\nCommon centroid layouts\n\nInterdigitization\n\nGuard rings and shielding\n\nLatch-up prevention concepts\n\nAnalog routing methodologies\n\nGood understanding of semiconductor process technology and device cross-sections.\n\nExperience with Deep N-Well (DNW) processes is preferred.\n\nStrong debugging skills in DRC/LVS verification.\n\nGood, logical reasoning and analytical problem-solving skills.\n\nFamiliarity with Cadence Virtuoso and industry-standard verification flows.\n\nGood communication and teamwork skills.\n\nPreferred Qualifications\n\nB.E (Electronics, E&TC or relevant field)\n\n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Staff Layout Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-10-25", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2507061", "is_hardware": true, "platform": "oracle", "jd_text": "Job Summary\n\nWe are looking for an experienced Analog Layout Engineer capable of independently owning analog and mixed-signal layout blocks from floorplanning through sign-off. The ideal candidate should demonstrate strong technical expertise in analog layout implementation, automation, scripting, and team collaboration while providing layout guidance to junior engineers.\n\nKey Responsibilities\n\nOwn complete analog/mixed-signal layout blocks from specification review through tape out readiness.\n\nPerform architecture-driven floorplanning and layout execution from scratch.\n\nDrive layout quality through robust DRC, LVS, ERC, and extraction closure.\n\nOptimize layouts for matching, performance, area, reliability, and manufacturability.\n\nDevelop and enhance layout automation solutions using scripting and custom utilities.\n\nCreate reusable methodologies to improve layout productivity and quality.\n\nLead design reviews and collaborate with circuit designers across multiple projects.\n\nMentor junior layout engineers and support technical growth within the team.\n\nContribute to layout best practices, process understanding, and automation strategy.\n\n#LI-RG1\n\nQualifications\nRequired Skills\n\n5-6 years of hands-on analog/custom layout experience.\n\nStrong expertise in: \n\nAnalog floorplanning from scratch\n\nComplex mixed-signal and analog IP layouts\n\nDevice matching and symmetry techniques\n\nDeep N-Well and isolation methodologies\n\nDRC/LVS/ERC debugging and closure\n\nParasitic-aware layout design\n\nStrong understanding of process cross-sections and fabrication-related layout considerations.\n\nWorking knowledge of automation and scripting (SKILL, Python, Tcl, Perl, or similar).\n\nAbility to identify opportunities for layout-flow automation and productivity enhancement.\n\nStrong logical reasoning and problem-solving skills.\n\nExcellent verbal and written communication skills.\n\nProven ability to work independently and collaborate across global teams.\n\nPreferred Qualifications\n\nB.E (Electronics, E&TC or relevant field)\n\n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "DDR STA/Timing Engineer, Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-24T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721599870", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nResponsibilities:\nSTA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.\nTiming analysis, validation and debug across multiple PVT conditions using PT/Tempus.\nRun Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.\nEvaluate multiple timing methodologies/tools on different designs and technology nodes.\nWork on automation scripts within STA/PD tools for methodology development.\nGood Technical writing and Communication skills, should be willing to work in cross-collaborative environment\nExperience in design automation using TCL/Perl/Python.\nFamiliar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus\nFamiliar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo.\nEducation : B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI.\nPreferred Qualification/Skills\n5+ years of experience in STA/Timing\nStrong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling\nHands-on experience with STA tools - Prime-time, Tempus\nHave experience in driving timing convergence at Chip-level and Hard-Macro level\nIn-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,\nKnowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)\nKnowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation.\nProficient is scripting languages – TCL, Perl, Awk\nBasic knowledge of device physics\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Package Layout Engineer - Hardware", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-24", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Package-Layout-Engineer---Hardware_JR2028579-1", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nNVIDIA's GPUs and SOCs are the world leaders in power, performance and efficiency. We are continually innovating to deliver new and creative, unusual solutions to extraordinary problems in a wide range of sectors. To this purpose, we are now seeking a hard-working Senior Package Layout Engineer who is committed to making a difference in the world through their contributions! This position will collaborate with Technical Package Lead and different design teams in the design and development of sophisticated, detailed layout of IC substrates for NVIDIA products. In addition, work with design teams to plan schedules, resolve costs, manufacturing, and electrical design issues.\n\nWhat you'll be doing:\nAs part of a Layout team, you will collaborate to implement high speed/density ASIC packages.\nPerform substrate breakout patterns for ASIC packages.\nOptimize package pinout incorporating system level trade-offs of pins assignment.\nHelp perform package routing, placement, stack-up, reference plane and power distribution using Cadence APD or SiP tool suite.\nPropose layout design trade-offs to the Technical Package Lead for resolution and implementation.\nConduct design feasibility studies to evaluate the Package design goals for size, cost, and system performance.\nDevelop symbols and CAD library databases using Cadence APD design tools\nDevelop methodologies to improve layout productivity\n\nWhat we need to see:\nHold a B.S. Electrical Engineering or equivalent experience\n5+ years experience in PCB Layout of graphics cards, motherboards, line cards or other related technology. Experience with HDI designs is a plus\nProven experience in substrate layout of wire bond and flip chip packages, preferred\nSignificant background with Cadence APD or SiP and/or PCB layout tools (including Constraint Manager)\nSolid understanding of high-speed design signal integrity practices\nExperience with Virtuoso and Calibre is a plus\nExperience using Valor is helpful\n \nNVIDIA is widely considered to be one of the technology world’s most desirable employers! We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative and autonomous, we want to hear from you.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior SoC Architect, Control Plane and Management Interconnect", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-24", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-SoC-Architect--Control-Plane-and-Management-Interconnect_JR2027524", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nAre you ready to develop the future of AI and computing? NVIDIA, a pioneer in computer graphics and accelerated computing, is hiring a Senior SoC Architect, Control Plane/Management Interconnect, to join our ambitious and world-class engineering team. This role offers an outstanding chance to lead innovation and influence the technology of the future! Be part of a team that thrives on innovation and excellence, and work in an environment that encourages diverse perspectives and collaboration. Your expertise will help build the future of AI and computing.\n\nWhat you'll be doing:\nLead the cohesive development of the Control Plane Architecture specifications, ensuring flawless integration across all SoCs.\nAnticipate new SoC requirements affecting Control Plane/Management Network Architecture and propose innovative solutions to broaden scope and address new use cases.\nExplore and effectively adopt latency reduction, wire reduction, and power reduction strategies to boost Interconnect Performance.\nValidate your ideas using Functional (untimed) and Performance(approximately timed) System-C models\nEffectively use AI to fully automate RTL and C-model generation flows.\n\nWhat we need to see:\nMinimum 12+ years experience as a Senior SoC Architect or an equivalent engineering role.\nBachelor's or Master's degree, or equivalent experience, in Electrical Engineering, Computer Engineering, or a related field.\nProficiency in ARM(AXI, CHI, APB), PCIE, UCIE protocols and other interconnect protocols.\nOutstanding ability to develop and implement architecture plans for control planes and management interconnects\nSkilled in SOC frameworks, reducing latencies, and optimizing energy consumption.\nExcellent collaboration skills, with the ability to work effectively in a diverse and encouraging environment.\nExperience in leading cross-functional teams and driving complex projects to completion.\n\nWays to stand out from the crowd:\nDemonstrated expertise in advanced AI methods implemented in SoC architecture.\nStrong track record of leading ambitious projects and delivering world-class results.\nA strong publication record in relevant areas of SoC architecture and especially Interconnects.\nProven capability to succeed and flourish in a dynamic, forward-thinking environment.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Mixed-Signal Design Engineer – RTL and Co-Simulation", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-24", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Mixed-Signal-Design-Engineer---RTL-and-Co-Simulation_JR2027731", "is_hardware": true, "platform": "workday", "jd_text": "We are seeking a Mixed-Signal Engineer to work on analog–digital co-simulation and digital RTL design for a power controller. The digital RTL implements the full control loop, including protections, fault handling, and calibration. This is a unique role with complete system-level exposure and the opportunity to influence both analog and digital design. The engineer should be flexible as priorities shift between co-simulation, RTL development, and debugging.\n \nNVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n \nWhat you'll be doing:\nBuild and run co-simulations that connect digital RTL with analog circuits or SPICE and Verilog-A models.\nEnhance and maintain the RTL for the power controller’s full digital control loop.\nVerify startup, steady-state, transient, calibration, and fault behavior at the system level in either a purely digital or a co-simulation environment.\nDebug issues across the analog–digital boundary with analog and digital designers.\nDevelop RTL behavioral models for mixed-signal blocks.\nDesign and implement control, protection, fault-handling, and calibration features.\n \nWhat we need to see:\nB.S. or MS degree in Electrical Engineering (or equivalent experience)\n1-3 years of work on analog–digital co-simulation and digital RTL design for a power controller.\nExperience designing and debugging synthesizable Verilog or SystemVerilog RTL.\nFlexibility to work across co-simulation and RTL design as project priorities change.\nA strong inclination to learn how the analog circuitry behaves. Analog expertise is not required; the team will provide support to help you ramp up.\nStrong teamwork and outstanding interpersonal skills.\n \nWays to stand out from the crowd:\nExperience with digital control logic in power management or a related system.\nStrong knowledge of, or experience working with, mixed-signal and custom-designed IP solutions.\nUnderstanding of firmware and embedded controllers.\nPrior exposure to analog design and mixed-signal simulation.\n \nTogether, let’s push the boundaries of innovation and make a lasting impact on the world. Make the choice, join our diverse team today!\n \n#LI-Hybrid", "jd_status": "stored"}, {"title": "System Verification Engineer II", "company": "Ericsson", "location": "Bangalore,Karnataka,India", "date_posted": "2026-10-23T06:49:31+00:00", "url": "https://jobs.ericsson.com/careers/job/563121777110705", "is_hardware": true, "platform": "eightfold", "jd_text": "Join our Team\n\nAbout this opportunity:\nAt Ericsson, we are the world leader in 5G innovation and deployment, powering a connected future where technology improves the way we live and work. With unmatched expertise and market penetration in 5G New Radio (NR), we are shaping the future of communication and pioneering advancements that will lead us into the era of 6G.  \nThe Opportunity:  \nReliability earns trust. As part of our RAN System Verification team, you will verify, troubleshoot and deliver Ericsson’s 5G New Radio (NR) solutions on high-performance General Purpose Processors (GPP), with sharp focus on performance, scalability and quality. You will work in advanced lab environments to validate system behaviour under realistic and extreme traffic conditions, influencing release readiness and overall product quality. \n \nWhat you will do:\nDrive end-to-end system-level verification of 5G RAN technologies to secure release readiness. \nPerform capacity and performance verification of RAN systems under high-load traffic scenarios comprising Max supported UEs per cell/DU, throughput (DL/UL), control plane capacity and mobility under load. \nAnalyse system behaviour and performance using logs, traces, KPIs including throughput, latency, PRB utilisation, resource load and QoS/QoE indicators. \nTroubleshooting Link curve verification, Channel quality and perform root cause analysis across multiple protocol layers (PHY, MAC, RLC, PDCP, IP) for complex system issues. \nPerform requirement analysis for feature integration and verification to ensure alignment with customer expectations. \nContribute to continuous improvements of products, test coverage, verification frameworks, automation and CI/CD pipelines. \nCollaborate closely with RAN development, integration/CI and product management teams. \nContinuously develop competence in relevant technical domains and modern verification practices. Explore and apply AI-assisted verification methods\n\nThe skills you bring\n\nBachelor’s or Master’s degree in Computer Engineering, Computer Science, Electrical Engineering or equivalent. \n2 to 8 years of hands‑on experience in system‑level verification, configuring, deploying, and troubleshooting LTE/5G NR baseband and radio equipment. \nStrong understanding of wireless communication systems (LTE/5G NR), RAN architecture/protocol stack and 5G NR air-interface technologies \nDemonstrated experience analyzing and troubleshooting performance issues at PHY/MAC layer under varying channel conditions. \nDeep knowledge of system level KPIs (throughput, latency, resource load, QoS/QoE) and the ability to identify performance bottlenecks. \nExperience working in Linux environments and overall IP networking. \nProgramming/Automation/scripting skills (for example Python, Bash, Java). Understanding of CI/CD concepts. \nExposure to configuration management and automation tools (for example Git, Gerrit, Jenkins).\n \nNice to have: \nExposure to Cloud-Native RAN, O-RAN Architecture. \nExperience with UE simulators, channel emulators, fading technologies, Link curve analysis and lab test tools. \nExperience with commercial UE chipset platform testing (Qualcomm, MediaTek etc). \nKnowledge of Cloud Native principles, Machine Learning and AI. \nSoftware development skills, particularly in Java and Python. \n \nWhy join us: \nWork with global experts in a high-performing, innovative, and global engineering environment. \nWork on cutting-edge 5G technology and be at the forefront of 6G innovation. \nContribute directly to the quality of live networks and customer experience worldwide. \nBuild deep expertise in system-level performance, capacity and reliability engineering. \nFlexible work environment, career growth and a diverse, inclusive environment.\n“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”\n\nWhy join Ericsson?At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.\n \nWhat happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.\n \nPrimary country and city: India (IN) ||\nReq ID: 789648", "jd_status": "stored"}, {"title": "PD Power Lead", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-23T05:16:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92546/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. MTS Silicon Design Engineer – PTPX Power Engineer Role Summary Responsible for power analysis, power optimization, and signoff of complex SoC/IP designs using PrimeTime PX (PTPX) and related power methodologies. The engineer will drive dynamic and leakage power convergence, identify power bottlenecks, develop power reduction strategies, and collaborate across PD, RTL, Architecture, Timing, DFT, and Power teams to achieve product power targets. Key Responsibilities Perform block, tile, and full-chip power analysis using PrimeTime PX (PTPX). Analyze dynamic, leakage, clock, memory, and switching power components to identify optimization opportunities. Drive power convergence across project milestones and signoff stages. Correlate power across RTL, synthesis, implementation, and silicon projections. Debug high-power hotspots and recommend architecture, RTL, clocking, and physical design optimizations. Execute power regression flows and generate power dashboards, reports, and trend analysis. Collaborate with PD, timing, clocking, and RTL teams to implement power-reduction solutions. Develop automation, scripts, and methodologies to improve power analysis efficiency and accuracy. Support power signoff reviews and customer-facing power deliverables. Required Qualifications Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, VLSI, Computer Engineering, or related field. 7 to 10 years of experience in ASIC Physical Design, STA, or Power Analysis. Strong understanding of digital design, CMOS power fundamentals, and low-power design techniques. Hands-on experience with PrimeTime PX (PTPX) or equivalent power analysis tools. Good understanding of activity propagation, SAIF/VCD-based power analysis, and switching activity estimation. Familiarity with synthesis, STA, clocking, and physical design flows. Proficiency in Tcl, Python, Perl, or Shell scripting. Strong analytical, debugging, and problem-solving skills. Preferred Experience Experience in SoC power signoff for CPU, GPU, AI/ML, networking, or datacenter products. Strong understanding of clock power optimization, power gating, multi-Vt strategies, DVFS, and low-power methodologies. Experience correlating RTL power, implementation power, and silicon power measurements. Exposure to advanced process nodes (5nm, 4nm, 3nm, or below). Experience with PrimeTime, Fusion Compiler, RedHawk, Joules, PowerArtist, or similar EDA tools. Knowledge of UPF/CPF, IR/EM considerations, and thermal-aware power analysis. Ability to independently drive power closure for critical blocks and mentor junior engineers. Experience developing power automation flows, dashboards, and AI-assisted power optimization methodologies. #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "PD Timing lead", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-23T05:12:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92547/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. MTS Silicon Design Engineer – Constraints & Full-Chip Timing (FCT) Role Summary Responsible for developing, validating, and maintaining timing constraints and driving full-chip timing convergence for complex SoCs. The engineer will own SDC methodology, timing signoff quality, cross-domain timing closure, and collaborate with RTL, Architecture, Tile PnR, Clocking, DFT, and Full-Chip teams to achieve timing signoff targets across all project milestones. Key Responsibilities Develop, validate, and maintain block, subsystem, and SoC-level timing constraints (SDC). Perform comprehensive timing analysis and closure for full-chip and partition-level designs. Analyze setup, hold, SI, OCV, AOCV, POCV, CDC-related, and mode-specific timing violations. Drive timing convergence across multiple corners, modes, and milestone releases. Debug timing issues originating from RTL, constraints, clock architecture, physical implementation, and ECO changes. Own timing signoff readiness and ensure timing quality across all project deliverables. Collaborate with Tile PnR, Clocking, DFT, Integration, and RTL teams to resolve critical timing bottlenecks. Develop timing automation, QoR dashboards, and methodology improvements to improve closure efficiency. Support customer timing reviews, signoff audits, and tapeout readiness activities. Mentor junior engineers and provide technical guidance on timing methodologies and best practices. Required Qualifications Bachelor's or Master's degree in Electrical Engineering, Electronics, VLSI, Computer Engineering, or related field. 7 to 10 years of experience in STA, Timing Closure, Constraints Development, or Physical Design. Strong understanding of STA concepts including setup, hold, recovery, removal, SI, OCV, AOCV, and POCV. Hands-on experience developing and validating SDC constraints. Proficiency with Synopsys PrimeTime and timing signoff methodologies. Strong understanding of clocking architectures, timing exceptions, and CDC interactions. Experience debugging timing violations and driving closure across multiple corners and modes. Proficiency in Tcl, Python, Perl, or Shell scripting. Strong analytical, problem-solving, and communication skills. Preferred Experience Experience driving full-chip timing closure for large CPU, GPU, AI/ML, networking, or datacenter SoCs. Expertise in constraint quality checks, timing signoff reviews, and correlation methodologies. Knowledge of clock-domain crossings, asynchronous interfaces, and timing exception verification. Experience with PrimeTime, PrimeTime-SI, Tempus, Fusion Compiler, or equivalent EDA tools. Familiarity with low-power timing methodologies, UPF flows, and advanced-node signoff requirements. Experience supporting tapeouts at 5nm, 4nm, 3nm, or newer process technologies. Proven track record of independently driving timing convergence for critical project milestones. Experience developing automation, AI-assisted timing analysis flows, and productivity-enhancing methodologies. Success Profile for an MTS FCT Engineer Independently owns timing closure for major SoC partitions or full-chip domains. Recognized as a constraints and STA expert within the project team. Drives timing convergence with minimal supervision. Identifies and resolves complex timing issues across RTL, Clocking, DFT, and Physical Design. Contributes to methodology improvements that improve timing closure efficiency, quality, and scalability. #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "LEAD PLATFORM EMULATION ENGINEER", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-23T05:03:00+00:00", "url": "https://global-external-amd.icims.com/jobs/93442/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. LEAD PLATFORM EMULATION ENGINEER: THE ROLE: The focus of this role is to plan, build, execute the verification, validation/emulation and debug of new and existing features for AMD’s SOCs, resulting in no bugs in the final SOC design and the firmware/BIOS. This senior role will stretch you as you lead emulation team in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design teams, marketing, and business unit executives. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification/debugging in general. You are a team player who has experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Drive Emulation Methodologies, SOC Design Model and Test Architecture for full chip SOC and hybrid models Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed Pre-Silicon Emulation tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test or infra issues Responsible for writing directed tests to verify features in a co-simulated and emulated/FPGA hardware environment Responsible for writing monitors and checkers to support end-to-end firmware/hardware validation Responsible for running emulator workloads to test new features and debug technical issues using logs, waveform dumps and RTL debug Use AI for hardware debug, improve execution and emulation capacity efficiency and automation PREFERRED EXPERIENCE: Must have exposure to SOC architecture (preferred X86) Experience with BIOS/OS bring up on full X86 SOC emulation platform Proficient in IP level ASIC verification, experience working with CPU, GPU, and Memory subsystem Proficient in debugging firmware and RTL code using simulation tools  Good understanding of PCIe/USB/Ethernet standards; safety concepts/IPs Must have hands-on experience on Zebu/Palladium/Veloce platform to bring-up SOC SOC design model build experience Experienced with Verilog, System Verilog, C, and C++   Experience in writing and debugging testbenches Scripting language experience: Perl, Ruby, Makefile, shell preferred Experience on debugging SOC IO interfaces with Transactor solutions in Emulation platform Think differently and out of the box to stress the DUT in Emulation platform and verify it in efficient way Should be open to learning verification methodologies and working closely with design, verification, validation, architecture and firmware teams Excellent communication, management, and presentation skills Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies ACADEMIC CREDENTIALS: Bachelor’s or Master’s degree in Computer/Electronics/Electrical Engineering with 18+ years of experience #L1-RG2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "CPU Verification Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-23T04:17:00+00:00", "url": "https://global-external-amd.icims.com/jobs/93559/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. THE ROLE: The Core design and verification team is responsible for development of ‘High performance and Ultralow power x86 microprocessor core’. The role provides a unique opportunity to work at the micro-architectural level of the next-gen Core, with exposure to designs that defines the next wave of client (laptops/ultra-books/think-clients) and custom designs. The multi-billion gate complexity and high-frequency (GHz) design development gives the learning experience of the latest and greatest design and verification methodologies, using cutting edge advanced technology nodes. THE PERSON: Candidates should have solid track record of working on complex designs with hands on experience on architecting and developing test-bench, test-bench components, test-planning and execution of testplan, coverage development and closure. Candidate should have working experience with global teams spread across different geography and time-zones. KEY RESPONSIBLITIES: Verification of Power management features of complex CPU Designs Architecting and development of testbench, test-bench components for complex system management/contol features including clock, reset and power management functionality of CPU cores Development of detailed test plans and driving the execution of test plan, including functional coverage. Understanding the existing test bench setup and look for opportunities to improve the existing test bench. Adhering to coding guideline practices, develop and implement code review process. Collaborate with global design verification teams and drive effectively the execution of the verification plans. Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion. PREFERRED EXPERIENCE: ASIC design verification experience 2 to 5 years. Strong understanding the design and verification life cycle. Hands on verification experience with C/C++/SystemVerilog testbench development. Hands on experience with coverage planning, coding and coverage closure. Experience with x86, ARM or any other industry standard microprocessor architecture and ACPI standards. Experience in clocking, reset, power-up sequences and power management verification. Understanding of low power design verification techniques is a plus. exposure to GLS, power aware verification and post-si verification is a plus ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "CPU Verification Engineer - Core Enablement", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-23T04:08:00+00:00", "url": "https://global-external-amd.icims.com/jobs/93669/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. MTS SILICON DESIGN ENGINEER    THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.     THE PERSON:  You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.   KEY RESPONSIBILITIES:  Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues  Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements   PREFERRED EXPERIENCE:  Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools  Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++   Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment.   Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience.   Scripting language experience: Perl, Ruby, Makefile, shell preferred.   Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions.     ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Staff Engineer, AMS Verification", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-23T03:07:25.267000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000157338659-staff-engineer-ams-verification", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking an AMS Verification Engineer to lead verification of the digital content embedded within power, analog, and mixed-signal IC products. This is a senior individual-contributor role requiring ownership of verification architecture, methodology, execution, and sign-off at block and full-chip level. \nThe successful candidate will build scalable verification environments from specifications, develop verification plans and coverage strategies, and verify control, protection, diagnostics, communication, trimming, test, and safety-related digital functions that interact closely with analog circuitry. \nYou will be expected to work autonomously, resolve ambiguous specification issues, establish verification flows from scratch where required, mentor engineers, and provide clear evidence that the design meets functional and product requirements before tape-out. \nResponsibilities  \nVerification Strategy & Ownership \nOwn block-level and full-chip digital verification strategy for power, analog, and mixed-signal IC products. \nDevelop verification plans from product and design specifications, including feature extraction, test intent, coverage goals, assumptions, and sign-off criteria. \nDecompose complex functions into reusable verification components and scalable environments. \nIdentify specification gaps and drive closure with architecture, analog design, digital design, applications, and test teams. \nEnvironment Development & Execution \nDesign and develop SystemVerilog/UVM-based testbenches, agents, scoreboards, reference models, assertions, sequences, and coverage models. \nSet up verification flows from scratch where needed and own regression execution, triage, debug, and closure. \nApply simulation, assertion-based verification, formal verification, and FPGA or emulation techniques where they provide practical value. \nVerify digital behavior across reset, clock, power-state, fault, trim, communication, test-mode, and analog-interaction scenarios. \nMixed-Signal, DFT & Post-layout Support \nCollaborate with analog and digital teams to define appropriate models and verify analog-digital interactions at the required abstraction level. \nSupport DFT verification, scan and ATPG-related checks, production-test vector development, and test-mode verification. \nSupport gate-level simulation, timing-aware verification, and post-layout verification where required. \nContribute to silicon bring-up, device evaluation, root-cause analysis, and documented workarounds for device errata. \nTechnical Leadership & Methodology \nDrive reusable verification methodology, automation, metrics, documentation, and review standards across projects. \nMentor and train verification engineers through reviews, debug support, and technical guidance. \nProvide concise status, coverage, risk, and sign-off assessments to project and technical leadership. \nInfluence architecture and design choices by identifying verification complexity, observability gaps, and product risks early. \n\nBachelor or Masters degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline. \n10+ years of experience in AMS verification, including substantial hands-on experience with SystemVerilog and UVM. \nProven ownership of block-level and full-chip verification environments and sign-off for complex semiconductor products. \nStrong knowledge of functional verification, assertion-based verification, formal verification, regression frameworks, coverage closure, and debug methodologies. \nExperience verifying digital logic embedded in PMICs, power-management, automotive, audio, or other mixed-signal integrated circuits. \nGood understanding of RTL, microarchitecture, clocks, resets, low-power states, register interfaces, and common serial interfaces such as SPI, I2C, or UART. \nWorking knowledge of synthesis, STA, DFT, scan insertion, ATPG, and gate-level verification to collaborate effectively across the development flow. \nExperience with scripting or automation using Python, TCL, Perl, shell, or similar languages. \nProven ability to mentor engineers, establish verification methodology, and lead technical reviews without requiring formal people-management authority. \nSelf-driven, results-oriented, and able to deliver under tight schedules in a multisite and multicultural environment. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "SOC Design Verification Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-23T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721139054", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n\nUnderstand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.\n\nResponsible to implement and analyze system Verilog assertion and coverage(code, toggle, functional) .\n\nWork alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue.\n\nCollaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nAdhere to quality standards and good test and verification practices.\n\nB.E/B. Tech/M.E/M. Tech in electronics with 8+ year experience in verification domain.\n\nPrior work experience on IP level or Soc level.\n\nPrior work on UFS (Universal Flash Storage),Ethernet and PCIe Protocol is desirable.\n\nGood understanding of processor based Soc level verification  which includes native ,Verilog ,system Verilog and UVM mix environment.\n\nHand on experience with verification tools such as VCS, waveform analyzer and  third party VIP integration (such as Synopsys VIPs).\n\nHands on experience in UVM. C/C++ ,System Verilog verification language.\n\nGood understanding of AXI-AMBA  protocol variants.\n\nCan work with scripting language (shell, Makefile, Perl )\n\nStrong understanding of design concepts and ASIC flow.\n\nGood problem solving , analytical and debugging skill is must.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Mixed Signal IP Verification Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-23", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Mixed-Signal-IP-Verification-Engineer_JR0288284", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nCome join Intel's Devices Development Group, responsible for creating leading Client SOCs. We envision the future of computing and design for the next generation of laptop and desktop computers. We are looking for a Mixed Signal IP Verification Engineer, ready to research, design, develop, and test Intel designs as we reimagine how to build SOCs at Intel and in the semiconductor industry. Our bold purpose as a company is to 'create world-changing technology that enriches the lives of every person on earth' and this role is instrumental in furthering our mission to shape the future of technology.\n\nResponsibilities may include but not be limited to:\n\n•\tPerform functional verification of Mixed Signal Power Delivery IPs (like Voltage Regulator, ADC, DAC) to ensure design meets specification.\n•\tProactively and independently develop test plan, add stimuli, add checkers/assertions to ensure adequate coverage and verify compliance with IP microarchitecture specifications.\n•\tCollaborate with RTL developers, Analog Design Engineers to improve verification of architectural and microarchitectural features.\n•\tReplicate, root cause, and debug issues in the pre-silicon verification environment.\n•\tDocument test plans and participate in technical reviews with design teams.\n•\tLead or be willing to lead Mixed Signal Validation(MSV) activities by running AMS simulations, collaborate cross-functionally with design teams to identify, root-cause and resolve schematic bugs.\n•\tMaintain and refine existing functional verification infrastructure and methodology for multiple IP generations.\n•\tActively participate in defining the architecture and microarchitecture of the IP being developed.\n\nQualifications:\nYou must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.\n\nMinimum Qualifications:\n\n•\tMust have either a Bachelor's degree with 5+ years of experience or Master's degree with 3+ years of experience in Electrical Engineering or Computer Engineering\n•\tMinimum 3 years of experience in Design Verification and Validation methodologies with UVM, System Verilog and industry standard EDA tools\n•\tMinimum 3 years of hands-on experience working on Mixed Signal IPs and driving AMS activities\n•\tMinimum 3 years of experience with reading and interpreting technical specs and Register Transfer Level (RTL) code and Behavioral Model (BMOD) code\n•\tMinimum 3 years of experience with writing validation plans and implement those validation plans\n\nPreferred Qualifications:\n\n•\tExperience with Design Verification of both Digital and Mixed Signal IPs\n•\tStrong ability to communicate technical analysis and conclusions clearly to stakeholders\n•\tExcellent self-organizing and time management skills\n•\tProficient in using AI tools to boost automation and efficiency\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "GPU Design Verification Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-23", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/GPU-Design-Verification-Engineer_JR0288330", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact:\nWe are looking for a GPU Design Verification Engineer to ensure the functional accuracy of cutting-edge graphics logic components, including 3D graphics, media, and display. In this role, you will develop and execute verification plans, build scalable test benches, and perform system simulations to uncover bugs and ensure design compliance. Your work will be integral in delivering high-quality designs that power Intel's advanced graphics solutions.\n\nBusiness Group:\nJoin Intel's Data Center Group (DCG), a team that drives innovation in computing and accelerates solutions for data-centric workloads. This group is focused on advancing technologies that support Intel's leadership in the data center domain, from performance optimization to scalability. As part of this team, you will contribute to Intel's mission to transform data into actionable insights and enable breakthrough innovations.\n\nKey Responsibilities :\n- Perform functional verification of graphics logic components to ensure they meet specifications.\n- Define and develop scalable and reusable verification plans, test benches, and verification environments.\n- Execute system simulation models to verify design functionality, analyze power and timing, and identify bugs.\n- Root cause and debug issues in the presilicon environment and implement corrective measures.\n- Collaborate with GPU architects, RTL developers, and physical design teams to improve verification processes and meet design goals.\n- Document test plans and drive technical reviews with design and architecture teams.\n- Maintain and enhance verification infrastructure and methodologies.\n\nQualifications:\nMinimum Qualifications :\n\n- Bachelor's degree in Electronics or Computer Engineering, or any related STEM degree, OR Master's degree in a relevant field OR PhD in a relevant field with no prior professional experience with 4+ years of hands on experience in IP Verification.\n- Proficiency in Verilog, System Verilog, and UVM for pre-silicon verification.\n- Hands-on experience with test bench development, coverage/assertion writing, and closure.\n- Exposure to GPU or CPU architecture and debugging experience with industry-standard frontend design flows and tools.\n- Programming expertise in scripting languages such as Python, Perl, or Shell scripting.\n\nPreferred Qualifications\n- Familiarity with Graphics architecture and GPU verification processes.\n- Expertise in RTL verification and validation, testbench development, and functional modeling.\n- Experience with coverage-driven verification methodologies.\n- Strong analytical and debugging skills, with the ability to work independently and mentor junior engineers.\n\nWe invite you to be part of a team that shapes the future of graphics innovation. Take this opportunity to grow, learn, and make a meaningful impact on the next generation of technology solutions.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "GPU Logic Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-23", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/GPU-Logic-Design-Engineer_JR0288331", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact :\nAs a GPU Logic Design Engineer, you will play a pivotal role in developing and optimizing the RTL design for cutting-edge graphics IPs, including compute, display, and media components. On a day-to-day basis, you will create logic designs, write RTL code, and conduct simulations to ensure high-quality integration of GPU blocks within full chip designs. By contributing to architecture definition and microarchitecture features, your work will directly impact Intel's ability to deliver state-of-the-art performance in graphics hardware. The candidate will also be responsible for Verifying the designs on their own or with other team members, including, test plan, TB changes, test content, debug, coverage etc.\n\nBusiness Group:\nThe role is part of Intel's Data Center Group (DCG), which focuses on advancing high-performance computing solutions that power data centers around the world. This group develops innovative GPU hardware designs that enable Intel's leadership in graphics and compute technologies, supporting scalable solutions for data-intensive workloads. DCG drives the creation of solutions that amplify Intel's broader mission of powering a data-driven future.\n\nKey Responsibilities:\n- Develop logic design, RTL coding, and simulation for GPU IPs, including graphics and media components.\n- Collaborate on defining architecture and microarchitecture features of the designed blocks.\n- Optimize logic for power, performance, area, and timing to meet design goals.\n- Review and implement verification plans to ensure correctness across validation hierarchies.\n- Resolve and implement corrective measures for RTL tests to guarantee feature integrity.\n- Support SoC customers for seamless GPU block integration in chip designs.\n\nQualifications:\nMinimum Qualifications :\n\n- Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field.\n- 6+ years of hands-on experience in IP RTL design, with demonstrated skills in microarchitecture and system verification using Verilog/SystemVerilog.\n- Proficiency in logic design optimization, timing analysis, and validation workflows.\n- Experience in scripting languages such as Python or Perl for automation purposes.\n- Knowledge of computer architecture and basic digital electronics principles.\n\nPreferred Qualifications:\n- Master's degree in a relevant field with 6+ years of industry experience or PhD with no prior professional experience.\n- Familiarity with UVM concepts and developing testbenches, monitors, and scoreboards.\n- Strong problem-solving skills and debugging capabilities for complex design challenges.\n- Effective collaboration and communication skills to work in cross-functional teams.\n\nTake the next step in advancing the future of GPU hardware innovation-apply now to be part of Intel's groundbreaking team where your contributions will shape the evolution of graphics technology.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Silicon Design Verification Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-23", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Silicon-Design-Verification-Engineer_JR0288285", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nCome join Intel's Devices Development Group, responsible for creating leading Client SOCs. We envision the future of computing and design for the next generation of laptop and desktop computers. We are looking for a ready to research, design, develop, and test Intel designs as we reimagine how to build SOCs at Intel and in the semiconductor industry. Our bold purpose as a company is to 'create world-changing technology that enriches the lives of every person on earth' and this role is instrumental in furthering our mission to shape the future of technology.\n\nResponsibilities may include but not be limited to:\n\n- Validation of DFx features such as Scan, SBFT,TAP, Arrays, Fuse, MBIST etc..using simulation, emulation\n- Creating plans and tests for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide\n- Learning the architecture and microarchitecture by debugging failures to the root cause\n- Developing and utilizing various DFT and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design\n- Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models\n- Engaging with IP providers and customers to define, develop and deliver necessary infrastructure and address issues found during execution\n- Developing tools and methods to streamline IP development and SOC integration to deliver highest quality in shortest time possible\n- Developing debugging tools and software\n\nQualifications:\nMinimum Qualifications:\n\n- Must have either a BS + 5 years' experience or MS + 3 years' experience in Computer Science, Computer Engineering or Electrical Engineering\n- Minimum 3 years' experience with reading and interpreting technical specs and Register Transfer Level (RTL) code\n- Minimum 3 years' experience working on IP or SoC development, verification, or integration using Verilog/SystemVerilog/OVM/UVM\n- Minimum 3 years' experience with writing validation plans and software to implement those validation plans\n- Minimum 1 year experience with UNIX or Linux\n\nPreferred Qualifications:\n\n- Minimum 1 year experience with computer architecture\n- Minimum 1 year experience with IA-32 assembly and/or Verilog programming experience\n- Minimum 2 years' experience with validation or testing experience, especially in a silicon design team\n - 3yrs+ experience with industry standards such as Scan, JTAG, BScan\n- Experience in Coherency\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Analog Circuit Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-23", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Analog-Circuit-Design-Engineer_JR0288527", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact:\n\nAs an Analog Circuit Design Engineer, you will lead the design and development of high-speed analog circuits for advanced process nodes. Your day-to-day responsibilities will include creating and optimizing circuits for analog and mixed-signal IPs, ensuring robust functionality, high performance, and power efficiency. Through your technical expertise, you will play a critical role in delivering innovative solutions that drive Intel's ability to meet global technology demands and maintain industry leadership.\n\nBusiness group:\n\nYou will join the Central Engineering Group (CEG), a world-class engineering organization dedicated to developing cutting-edge technologies. The team focuses on delivering state-of-the-art solutions that enable Intel's success in innovation and product excellence, contributing to the company's broader mission of technological leadership.\n\nKey Responsibilities:\n\n- Design, develop, and optimize analog circuits for advanced process nodes, focusing on high-speed SerDes, memory interfaces, and clocking systems.\n- Extract key chip parameters and simulate analog behavior models to validate designs against block specifications.\n- Create and execute thorough test plans to ensure functionality, reliability, and performance of circuits.\n- Collaborate with architecture and layout teams to optimize circuits for power, area, timing, and electrical robustness.\n- Perform post-silicon debug and validation to analyze and resolve circuit-related issues for high-volume manufacturing readiness.\n- Continuously refine design methodologies to improve innovation, efficiency, and delivery timelines.\n- Utilize industry-standard EDA tools such as Cadence Virtuoso, SPICE simulators, and post-layout extraction tools for design and validation tasks.\n\nQualifications:\nMinimum Qualifications:\n\n- Bachelor's degree in Electrical Engineering or a related field with 6+ years of experience, Master's degree with 4+ years, or PhD with 2+ years in analog circuit design.\n- Proficiency in designing high-speed analog/mixed-signal circuits, including SerDes, PLLs, regulators, and clocking systems.\n- Expertise in CMOS design fundamentals, circuit simulation tools, and modeling techniques.\n- Experience with EDA tools such as Cadence Virtuoso, Spectre, PrimeSim, DRC, LVS, and post-layout extraction tools.\n- Familiarity with optimizing circuits for power, area, timing, and yield goals.\n\nPreferred Qualifications:\n\n- Experience in post-silicon validation, reliability testing, and debugging.\n- Knowledge of scripting languages such as Python, TCL, or Perl for design automation tasks.\n- Familiarity with modeling and simulation of high-speed interface interconnects and channels.\n- Strong problem-solving and analytical skills, with a demonstrated ability to lead initiatives and mentor junior engineers.\n\nWe are excited to invite talented engineers to join our mission of driving innovation and transforming technology. Make an impact by contributing to Intel's cutting-edge solutions-apply now.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Principal Engineer – CAD Design Engineering & EDA Infrastructure", "company": "Lattice", "location": "San Jose, CA", "date_posted": "2026-10-23", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/San-Jose-CA/Dir--CAD-Eng---R-D_R-101040", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\n\nJob Description:\nPrincipal Engineer – CAD Design Engineering & EDA Infrastructure\n\nWe are seeking an experienced and highly technical Principal Engineer to lead the strategy, architecture, development, and operational excellence of our CAD and EDA Infrastructure. This role is responsible for enabling world-class semiconductor and hardware design teams through scalable design environments, automation, tool optimization, cloud adoption, and engineering productivity initiatives.\nThe ideal candidate combines deep expertise in semiconductor design flows, EDA tools, infrastructure engineering, and large-scale automation with strong leadership and cross-functional collaboration skills.\n\nKey Responsibilities\n\nCAD & EDA Infrastructure Leadership\nDefine and execute the vision, roadmap, and strategy for CAD and EDA infrastructure supporting ASIC, SoC, IP, and verification teams.\n\nLead the design, deployment, and maintenance of highly scalable and secure engineering environments.\n\nDrive infrastructure modernization initiatives including cloud-enabled design workflows, hybrid compute environments, and next-generation engineering platforms.\n\nPartner with design, verification, implementation, and architecture teams to understand evolving tool and infrastructure requirements.\n\nEDA Tools & Design Flow Development\nOptimize RTL-to-GDSII design flows across synthesis, place-and-route, STA, DFT, verification, emulation, and signoff.\n\nEvaluate, deploy, and support industry-standard EDA tools from Synopsys, Cadence, Siemens/Mentor, and other vendors.\n\nStandardize methodologies and best practices across global engineering teams.\n\nImprove tool reliability, performance, and user productivity through automation and workflow optimization.\n\nAutomation & Engineering Productivity\nDrive automation using Python, Tcl, Perl, Shell scripting, and modern software engineering practices.\n\nBuild self-service platforms and dashboards for monitoring tool usage, licenses, compute resources, and design flow metrics.\n\nReduce design cycle times through process optimization and infrastructure innovation.\n\nImplement CI/CD and DevOps practices for CAD environments and engineering workflows.\n\nInfrastructure & Compute Management\nArchitect and manage large-scale Linux-based compute farms and distributed job scheduling systems.\n\nOptimize storage, networking, HPC clusters, and cloud resources to support demanding EDA workloads.\n\nManage EDA license infrastructure, capacity planning, and utilization optimization.\n\nEnsure high availability, reliability, security, and compliance of engineering environments.\n\nTechnical Leadership\nServe as a subject matter expert and trusted advisor to design leadership and engineering teams.\n\nMentor engineers and contribute to the growth of CAD and infrastructure talent.\n\nInfluence technology decisions and provide guidance on future engineering platform investments.\n\nLead root-cause analysis and resolution of complex technical issues impacting engineering productivity.\n\nRequired Qualifications\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline.\n\n12+ years of experience in semiconductor design methodologies, CAD engineering, or EDA infrastructure.\n\nDeep understanding of ASIC/SoC design and verification flows.\n\nStrong expertise with Linux/Unix environments and distributed computing systems.\n\nHands-on experience with leading EDA platforms from Synopsys, Cadence EDA.\n\nAdvanced programming and automation skills in Python, Tcl, Shell, or similar languages.\n\nExperience managing large-scale compute farms, license servers, storage systems, and enterprise infrastructure.\n\nStrong analytical, problem-solving, and stakeholder management skills.\n\nPay & Benefits\n\nConsistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. \n\nFor candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.  The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.\n\nBase Pay Range\n250,000.00\nIn addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! \n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in the United States.\n\nLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.\n \nAs an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.", "jd_status": "stored"}, {"title": "Senior Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-10-23", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Senior-Engineer_R026378-6", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nCandidate would be required to work on various phases of SOC physical design activities. The job will include but not limited to  block level – floor-planning, partitioning, placement, clock tree synthesis, route, physical verification (LVS/DRC/ERC/Antenna etc).\nShould be able to meet congestion, timing and area metrics.  Candidate would be required to do equivalence checks, STA, Crosstalk delay analysis ,noise analysis, power optimization. Should be able to implement timing and functional ECOs.\n \nShould have excellent problem solving skill to help through congestion resolution and timing closure. Should have experience formal verification and timing analysis and ECO implementation.\nExperience with tools such as Innovus/Encounter, ICC, Caliber, LEC, Primetime etc is highly desirable.\n \nCandidate should be able to work independently and guide other team members. Should be experienced in working in a global team and dynamic environment.\nShould possess ability to learn and adapt to new tools and methodologies.\nExcellent communication skill is a must. \n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Cyber Detection Engineer", "company": "Analog Devices", "location": "India, Bangalore, Nova", "date_posted": "2026-10-23", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-Nova/Cyber-Detection-Engineer_R266699", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nDetection Engineer – Early Career\n\nRole Overview\nThe Detection Engineer supports the development, testing, tuning, and maintenance of cyber detection capabilities across the Security Operations Centre (SOC). Working closely with SOC analysts, threat intelligence, incident response, and engineering teams, this role helps improve visibility, detection accuracy, and response effectiveness. This is an early-career position designed for individuals looking to build expertise in detection engineering, SIEM content development, threat analytics, and automation.  The successful candidate will demonstrate curiosity, analytical reasoning, and the ability to independently investigate why a detection fired, how an attack could occur, and how future detections can be improved.\n\nKey Responsibilities\nSupport the development, testing, and maintenance of SIEM detection rules, analytics, alerts, and correlation logic.\nAssist with tuning existing detections to reduce false positives and improve detection quality.\nInvestigate missed detections and support root-cause analysis activities.\nWork with SOC analysts to understand alert triage outcomes and improve detection content.\nHelp onboard new log sources into monitoring platforms and validate data quality and coverage.\nSupport detection use-case development using threat intelligence, MITRE ATT&CK, incident findings, and known attack techniques.\nParticipate in threat hunting exercises and assist with developing new detection opportunities.\nAssist with maintaining detection engineering documentation, standards, playbooks, and testing records.\nSupport development of automation workflows within SIEM, SOAR, and response platforms.\nAssist the SOC in the triage, investigation, and response of security alerts, incidents, and escalations\nContribute to purple-team, tabletop, and validation exercises to measure effectiveness of detections.\nTrack detection performance metrics, including false positives, false negatives, detection coverage, and alert quality.\nSupport continuous improvement activities following incidents, audits, and lessons learned reviews.\nMaintain flexibility to support global cybersecurity operations, including participation in management meetings, vendor engagements, support calls, incident response activities, and after-hours escalations across multiple time zones as needed.\n\nRequired Qualifications\nBachelor’s degree in Cybersecurity, Computer Science, Information Technology, Engineering, or equivalent experience.\n1–3 years experience in cybersecurity, IT operations, SOC operations, system administration, or related technical field.\nUnderstanding of cybersecurity fundamentals including phishing, malware, identity attacks, network attacks, and incident response.\nKnowledge of AI-assisted detection engineering, large language models (LLMs), agentic workflows, and security automation platforms used to improve analyst productivity and detection outcomes.\nBasic knowledge of SIEM platforms and log analysis concepts.\nUnderstanding of networking fundamentals including TCP/IP, DNS, HTTP, authentication, and firewalls.\nStrong analytical and problem-solving skills.\nAbility to learn quickly and work effectively within a collaborative team environment.\nStrong written and verbal communication skills.\n\nPreferred Qualifications\nExperience with SIEM/SOAR platforms, Microsoft Defender, Azure, AWS, or similar platforms.\nExperience developing, integrating, or operationalizing AI-powered analysis, automation, and agent-based workflows within security operations, incident response, or detection engineering functions.\nKnowledge of MITRE ATT&CK framework.\nBasic scripting experience using Python, PowerShell, KQL, or SQL.\nSecurity+, SC-200, AZ-500, CySA+, or equivalent certifications.\nExperience participating in labs, CTFs, internships, threat hunting, or cyber research projects.\n\nSuccess Measures\nImprovement in detection quality and reduction in false positives.\nSuccessful onboarding and validation of data sources.\nDelivery of new and enhanced detection use cases.\nContribution to incident-driven detection improvements.\nAccurate documentation and testing of detection logic.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Level 3 SOC Analyst", "company": "Analog Devices", "location": "India, Bangalore, Nova", "date_posted": "2026-10-23", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-Nova/Level-3-SOC-Analyst_R266700", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nL3 SOC Analyst\n\nRole Overview\nThe L3 SOC Analyst is the senior technical escalation point within the Security Operations Centre (SOC). This role is responsible for leading complex cyber investigations, directing incident response activities, providing threat intelligence expertise, mentoring L1/L2 analysts, and driving continuous improvement of detection and response capabilities. The role combines advanced technical investigation, threat hunting, cyber threat intelligence, incident command, and operational leadership.\n\nKey Responsibilities\n·        Act as the primary technical escalation point for high-severity and complex cyber incidents.\n·        Lead investigations involving ransomware, business email compromise, insider threats, cloud compromise, identity attacks, and advanced persistent threats.\n·        Perform detailed scoping, root-cause analysis, containment, eradication, and recovery activities during active incidents.\n·        Provide incident command support and coordinate response activities across Cybersecurity, IT, Legal, HR, Privacy, and business stakeholders.\n·        Conduct proactive threat hunting using intelligence, behavioural analytics, SIEM, EDR, NDR, identity, and cloud telemetry.\n·        Collect, analyse, operationalise, and disseminate cyber threat intelligence from internal and external sources.\n·        Track threat actor tactics, techniques, and procedures (TTPs) and map activity to MITRE ATT&CK.\n·        Develop, tune, and improve detection use cases, correlation rules, analytics, and automated response workflows.\n·        Own and maintain SOC playbooks, incident response procedures, escalation criteria, and communication templates.\n·        Provide coaching, mentorship, and quality oversight for L1 and L2 analysts.\n·        Review alert triage quality, escalation decisions, documentation standards, and investigation outcomes.\n·        Produce executive-ready incident summaries, threat assessments, lessons learned, and risk-based recommendations.\n·        Drive continuous improvement activities including post-incident reviews, threat modelling, detection coverage reviews, and operational readiness exercises.\n·        Support compliance, audit, and regulatory activities including NIST CSF, CMMC, TISAX, and incident response evidence requirements.\n·        Maintain flexibility to support global cybersecurity operations, including participation in management meetings, vendor engagements, support calls, incident response activities, and after-hours escalations across multiple time zones as needed.\n\nRequired Qualifications\n·        5+ years of experience in SOC Operations, Incident Response, Threat Intelligence, Digital Forensics, Detection Engineering, or related cybersecurity disciplines.\n·        Advanced understanding of cyber attack methodologies, adversary behaviour, and incident response frameworks.\n·        Strong experience with SIEM, EDR, NDR, email security, identity security, and cloud security platforms.\n·        Experience leading complex investigations and coordinating response activities across multiple teams.\n·        Strong analytical, investigative, and decision-making skills.\n·        Excellent written and verbal communication skills with the ability to communicate with both technical and executive audiences.\n·        Ability to operate independently in high-pressure situations and make risk-based decisions.\n\nPreferred Qualifications\n·        GCIH, GCIA, GCTI, CISSP, GCFA, GREM, CEH or equivalent certifications.\n·        Experience with Microsoft Defender, WIZ, SIEM/SOAR platforms, and cloud-native security tools.\n·        Experience within a global enterprise SOC or regulated environment.\n·        Experience leveraging AI, generative AI, and agentic security capabilities to enhance threat detection, investigation, response, and SOC operational efficiency.\n·        Scripting and automation experience using Python, PowerShell, or similar languages.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "GPU Core Pipeline IP Verification Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-23", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/GPU-Core-Pipeline-IP-Verification-Engineer_JR2020914", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking a highly enthusiastic and motivated Verification Engineer to verify the design and implementation of the next generation of control subsystems for the world’s leading GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We are united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science.\nThe GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n \nWhat you’ll be doing:\nAs a key member of our ASIC Verification team, you will contribute to verifying graphics and compute features within an IP.\n\nYou will be responsible for IP-level verification of GPU ASICs, including the design, architecture, golden models, and micro-architecture, using advanced verification tools and methodologies.\n\nYou will work with the specifications, develop test plans, tests and verification infrastructure using UVM methodology and ensure functional and code coverage of all the RTL which you will verify.\n\nWork with HW architects and designers to make the right implementation choices.\n\nYou will be working with architects, designers, and other members of your verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech. with 2+ years of relevant experience\n\nFamiliarity with Verilog, C++ and OOPs concepts.\n\nExperience in verification and test planning at Unit level.\n\nExperience in developing and working in functional coverage based constrained random verification environments\n\nGood understanding of computer architecture concepts.\n\nStrong technical fundamentals with superior analytical skills and problem-solving skills\n\nKnowledge in SystemVerilog or similar HVL, experience in verification methodologies like UVM/VMM is highly desirable\n\nExposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nPrior experience in 3D graphics processing, processor verification.\n\nC/C++ programming language experience\n\nExperience in scripting and tool development using Perl and Python\n\nExcellent debugging skills\n\nGood interpersonal & communication skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Verification Engineer - PCIE", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-23", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Verification-Engineer---PCIE_JR2023400", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n\nAt NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nResponsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nExpected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.\n\nYou will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech. with 2+ years of relevant experience\n\nExperience in verification at Unit/Sub-system/SOC level using Verilog and SystemVerilog\n\nBackground with verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)\n\nExperience in developing and working in functional coverage based constrained random verification environments\n\nExperience in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nExcellent problem solving skills\n\nKnowledge of PCIE protocol - Gen3 and above\n\nProficiency in Testbench development using SystemVerilog\n\nPerl, Python or similar scripting and SW programming language experience\n\nGood debugging and analytical skills\n\nWith competitive salaries and a generous benefits package, Nvidia is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.\n\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "PCIe IP Verification Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-23", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/PCIe-IP-Verification-Engineer_JR2019919-1", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science.\n\nThe GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nBe responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nExpected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.\n\nYou will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech or equivalent experience\n\n2+ years of relevant experience\n\nExperience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog\n\nExpertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)\n\nExperience in developing and working in functional coverage based constrained random verification environments\n\nBackground in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nExcellent knowledge of PCIE protocol - Gen3 and above\n\nGood understanding of the system level architecture of PCIE/CXL-based designs\n\nPerl, Python or similar scripting and SW programming language experience\n\nGood debugging and analytical skills\n\nGood interpersonal skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "IP Verification Engineer - GPU Core Pipeline", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-23", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/IP-Verification-Engineer---GPU-Core-Pipeline_JR2019962", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking a highly enthusiastic and motivated Verification Engineer to verify the design and implementation of the next generation of control subsystems for the world’s leading GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We are united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science.\n\nThe GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nAs a key member of our ASIC Verification team, you will contribute to verifying graphics and compute features within an IP.\n\nYou will be responsible for IP-level verification of GPU ASICs, including the design, architecture, golden models, and micro-architecture, using advanced verification tools and methodologies.\n\nYou will work with the specifications, develop test plans, tests and verification infrastructure using UVM methodology and ensure functional and code coverage of all the RTL which you will verify.\n\nWork with HW architects and designers to make the right implementation choices.\n\nYou will be working with architects, designers, and other members of your verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech. with 2+ years of relevant experience\n\nFamiliarity with Verilog, C++ and OOPs concepts.\n\nExperience in verification and test planning at Unit level.\n\nExperience in developing and working in functional coverage based constrained random verification environments\n\nGood understanding of computer architecture concepts.\n\nStrong technical fundamentals with superior analytical skills and problem-solving skills\n\nKnowledge in SystemVerilog or similar HVL, experience in verification methodologies like UVM/VMM is highly desirable\n\nExposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nPrior experience in 3D graphics processing, processor verification.\n\nC/C++ programming language experience\n\nExperience in scripting and tool development using Perl and Python\n\nExcellent debugging skills\n\nGood interpersonal & communication skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.\n\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Verification Engineer - GPU Fullchip", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-23", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Verification-Engineer---GPU-Fullchip_JR2019166", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nThe GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nAs a key member of our ASIC Verification team, you will verify the design and implementation of the industry's leading GPUs.\n\nResponsible for verification of the ASIC design, architecture, golden models and micro-architecture of the GPUs and full-chip level using advanced verification tools and methodologies.\n\nBuild reusable bus functional models, traffic generators, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nYou are expected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.\n\nWorking with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech or equivalent experience with 2+ years of relevant experience\n\nProficiency in Verilog and C\n\nFamiliarity with OOPs concepts\n\nHands-on experience in verification at Unit/Sub-system/SOC level\n\nGood understanding of computer architecture concepts\n\nStrong technical fundamentals with superior analytical skills and problem-solving skills\n\nKnowledge of SystemVerilog or similar HVL is highly desirable\n\nExperience in verification methodologies like UVM/VMM is highly desirable\n\nExposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nPrior experience in 3D graphics processing or processor verification\n\nC/C++ programming language experience\n\nExperience in scripting and tool development using Perl and Python\n\nExcellent debugging skills\n\nGood interpersonal and communication skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Verification Engineer, Memory Subsystem", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-23", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Verification-Engineer--Memory-Subsystem_JR2019261", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.\n\nNVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nWhat you’ll be doing:\nResponsible for verifying the ASIC design, architecture and micro-architecture using advanced verification methodologies.\n\nExpected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.\n\nCome up with test plans, tests and verification infrastructure for complex IPs/sub-systems.\n\nResponsible for performance and deadlock verification of the GPU memory subsystem unit.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nPerform functional coverage driven verification closure.\n\nWorking with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech. with 2+ years of relevant experience\n\nExperience in verification of complex IPs/units and sub-systems\n\nVerification experience using random stimulus along with functional coverage and assertion-based verification methodologies\n\nExpertise in Verilog\n\nKnowledge in SystemVerilog or similar HVL\n\nFamiliarity with verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nExperience in memory subsystem or network interconnect IP verification\n\nGood debugging and analytical skills\n\nScripting knowledge (Python/Perl/shell)\n\nGood communication skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior Verification Engineer, Memory Subsystem", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-23", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer--Memory-Subsystem_JR2016842", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.\n\nNVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nWhat you’ll be doing:\nResponsible for verifying the ASIC design, architecture and micro-architecture using advanced verification methodologies.\n\nExpected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.\n\nCome up with test plans, tests and verification infrastructure for complex IPs/sub-systems.\n\nResponsible for performance and deadlock verification of the GPU memory subsystem unit.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nPerform functional coverage driven verification closure.\n\nWorking with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech. with 4+ years of relevant experience\n\nExperience in verification of complex IPs/units and sub-systems\n\nVerification experience using random stimulus along with functional coverage and assertion-based verification methodologies\n\nExpertise in Verilog\n\nKnowledge in SystemVerilog or similar HVL\n\nFamiliarity with verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nExperience in memory subsystem or network interconnect IP verification\n\nGood debugging and analytical skills\n\nScripting knowledge (Python/Perl/shell)\n\nGood communication skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior Verification Engineer, PCIE", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-23", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer--PCIE_JR1998099", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science.\n\nThe GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nBe responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nExpected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.\n\nYou will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech or equivalent experience\n\n5+ years of relevant experience\n\nExperience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog\n\nExpertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)\n\nExperience in developing and working in functional coverage based constrained random verification environments\n\nBackground in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nExcellent knowledge of PCIE protocol - Gen3 and above\n\nGood understanding of the system level architecture of PCIE/CXL-based designs\n\nPerl, Python or similar scripting and SW programming language experience\n\nGood debugging and analytical skills\n\nGood interpersonal skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior Verification Engineer, PCIE", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-23", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer--PCIE_JR1998093", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science.\n\nThe GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nBe responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nExpected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.\n\nYou will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech or equivalent experience\n\n5+ years of relevant experience\n\nExperience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog\n\nExpertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)\n\nExperience in developing and working in functional coverage based constrained random verification environments\n\nBackground in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nExcellent knowledge of PCIE protocol - Gen3 and above\n\nGood understanding of the system level architecture of PCIE/CXL-based designs\n\nPerl, Python or similar scripting and SW programming language experience\n\nGood debugging and analytical skills\n\nGood interpersonal skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n#LI-Hybrid", "jd_status": "stored"}, {"title": "GPU Core Pipeline IP Verification Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-23", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/GPU-Core-Pipeline-IP-Verification-Engineer_JR2024121", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking a highly enthusiastic and motivated Verification Engineer to verify the design and implementation of the next generation of control subsystems for the world’s leading GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We are united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science.\n\nThe GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nAs a key member of our ASIC Verification team, you will contribute to verifying graphics and compute features within an IP.\n\nYou will be responsible for IP-level verification of GPU ASICs, including the design, architecture, golden models, and micro-architecture, using advanced verification tools and methodologies.\n\nYou will work with the specifications and ensure functional and code coverage of all the RTL which you will verify.\n\nYou are expected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.\n\nWork with HW architects and designers to make the right implementation choices.\n\nYou will be working with architects, designers, and other members of your verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech. with 1+ years of relevant experience\n\nFamiliarity with Verilog, C++ and OOPs concepts.\n\nHands-on experience in verification at Unit/Sub-system/SOC level.\n\nBackground with design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).\n\nGood understanding of computer architecture concepts.\n\nStrong technical fundamentals with superior analytical skills and problem-solving skills\n\nKnowledge in SystemVerilog or similar HVL, experience in verification methodologies like UVM/VMM is highly desirable\n\nExposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nPrior experience in 3D graphics processing, processor verification.\n\nC/C++ programming language experience\n\nExperience in scripting and tool development using Perl and Python\n\nExcellent debugging skills\n\nGood interpersonal & communication skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior Verification Engineer, PCIE", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-23", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer--PCIE_JR2025156", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science.\n\nThe GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nBe responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nExpected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.\n\nYou will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech or equivalent experience\n\n4+ years of relevant experience\n\nExperience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog\n\nExpertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)\n\nExperience in developing and working in functional coverage based constrained random verification environments\n\nBackground in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nExcellent knowledge of PCIE protocol - Gen3 and above\n\nGood understanding of the system level architecture of PCIE/CXL-based designs\n\nPerl, Python or similar scripting and SW programming language experience\n\nGood debugging and analytical skills\n\nGood interpersonal skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior ASIC Design Engineer, GPU Core Pipeline IP", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-23", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-ASIC-Design-Engineer--GPU-Core-Pipeline-IP_JR2025698", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking a highly enthusiastic and motivated Design Engineer to design and implement the next generation of control subsystems for the world’s leading GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n\nAt NVIDIA, our employees are passionate about parallel and visual computing. We are united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you'll be doing:\nAs a key member of our ASIC Design team, you will contribute to the design and implementation of graphics and compute features within an IP.\n\nYou will be responsible for the micro-architecture and RTL design of GPU ASICs, working closely with architecture, verification and physical design teams to deliver high-quality designs.\n\nYou will develop RTL using Verilog/SystemVerilog, collaborate on design specifications, and ensure that designs meet performance, power, area, and timing goals.\n\nWork with HW architects and designers to make the right implementation choices.\n\nCollaborate with verification engineers to ensure comprehensive validation and coverage of all implemented functionality.\n\nYou will be working with architects, verification engineers, and other members of your design teams to accomplish your tasks.\n\nParticipate in silicon bring-up, post-silicon debug, and performance analysis as needed.\n\nWhat we need to see:\nB.Tech./ M.Tech. with 5+ years of relevant experience.\n\nFamiliarity with Verilog, C++ and OOPs concepts.\n\nExperience in RTL design and micro-architecture development at the unit or subsystem level.\n\nGood understanding of digital design fundamentals, including synchronous design, timing, and clock/reset methodologies.\n\nGood understanding of computer architecture concepts.\n\nStrong technical fundamentals with superior analytical and problem-solving skills.\n\nKnowledge of SystemVerilog and ASIC design methodologies is highly desirable.\n\nExposure to industry-standard design, simulation, and debug tools.\n\nWays to stand out from the crowd:\nPrior experience in 3D graphics processing or processor design.\n\nC/C++ programming language experience.\n\nExperience in scripting and tool development using Perl and Python.\n\nExcellent debugging skills.\n\nUnderstanding of ASIC implementation flows including synthesis, timing closure, DFT, and physical design considerations.\n\nGood interpersonal & communication skills and dream to work as a great teammate.\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior Verification Engineer, PCIE", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-23", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer--PCIE_JR2025140", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science.\n\nThe GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nBe responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nExpected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.\n\nYou will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech or equivalent experience\n\n5+ years of relevant experience\n\nExperience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog\n\nExpertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)\n\nExperience in developing and working in functional coverage based constrained random verification environments\n\nBackground in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nExcellent knowledge of PCIE protocol - Gen3 and above\n\nGood understanding of the system level architecture of PCIE/CXL-based designs\n\nPerl, Python or similar scripting and SW programming language experience\n\nGood debugging and analytical skills\n\nGood interpersonal skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Verification Engineer - PCIE", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-23", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Verification-Engineer---PCIE_JR2023403", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n\nAt NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nResponsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nExpected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.\n\nYou will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech. with 2+ years of relevant experience\n\nExperience in verification at Unit/Sub-system/SOC level using Verilog and SystemVerilog\n\nBackground with verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)\n\nExperience in developing and working in functional coverage based constrained random verification environments\n\nExperience in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nExcellent problem solving skills\n\nKnowledge of PCIE protocol - Gen3 and above\n\nProficiency in Testbench development using SystemVerilog\n\nPerl, Python or similar scripting and SW programming language experience\n\nGood debugging and analytical skills\n\nGood interpersonal skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, Nvidia is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Verification Engineer - PCIE", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-23", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Verification-Engineer---PCIE_JR2023394", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n\nAt NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nResponsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nExpected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.\n\nYou will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech. with 2+ years of relevant experience\n\nExperience in verification at Unit/Sub-system/SOC level using Verilog and SystemVerilog\n\nBackground with verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)\n\nExperience in developing and working in functional coverage based constrained random verification environments\n\nExperience in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nExcellent problem solving skills\n\nKnowledge of PCIE protocol - Gen3 and above\n\nProficiency in Testbench development using SystemVerilog\n\nPerl, Python or similar scripting and SW programming language experience\n\nGood debugging and analytical skills\n\nGood interpersonal skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, Nvidia is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior Verification Engineer, PCIE", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-23", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer--PCIE_JR2023405", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science.\n\nThe GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nBe responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nExpected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.\n\nYou will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech or equivalent experience\n\n5+ years of relevant experience\n\nExperience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog\n\nExpertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)\n\nExperience in developing and working in functional coverage based constrained random verification environments\n\nBackground in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nExcellent knowledge of PCIE protocol - Gen3 and above\n\nGood understanding of the system level architecture of PCIE/CXL-based designs\n\nPerl, Python or similar scripting and SW programming language experience\n\nGood debugging and analytical skills\n\nGood interpersonal skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Verification Engineer, PCIE", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-23", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Verification-Engineer--PCIE_JR2018537", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science.\n\nThe GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nBe responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nExpected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.\n\nYou will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech or equivalent experience\n\n2+ years of relevant experience\n\nExperience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog\n\nExpertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)\n\nExperience in developing and working in functional coverage based constrained random verification environments\n\nBackground in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nExcellent knowledge of PCIE protocol - Gen3 and above\n\nGood understanding of the system level architecture of PCIE/CXL-based designs\n\nPerl, Python or similar scripting and SW programming language experience\n\nGood debugging and analytical skills\n\nGood interpersonal skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Verification Engineer - PCIE", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-23", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Verification-Engineer---PCIE_JR2023399", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n\nAt NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nResponsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nExpected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.\n\nYou will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech. with 2+ years of relevant experience\n\nExperience in verification at Unit/Sub-system/SOC level using Verilog and SystemVerilog\n\nBackground with verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)\n\nExperience in developing and working in functional coverage based constrained random verification environments\n\nExperience in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nExcellent problem solving skills\n\nKnowledge of PCIE protocol - Gen3 and above\n\nProficiency in Testbench development using SystemVerilog\n\nPerl, Python or similar scripting and SW programming language experience\n\nGood debugging and analytical skills\n\nGood interpersonal skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, Nvidia is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "PCB Design Engineer, Electronic Systems", "company": "Tesla", "location": "Bengaluru, India ; India", "date_posted": "2026-10-23", "url": "https://hire-r1.mokahr.com/social-recruitment/tesla/100004142?#/job/31c9dff6-927c-4415-a011-5f09b5e77098", "is_hardware": true, "platform": "mokahr", "jd_text": "The Role:\nThe high speed layout team is responsible for layout of the physical hardware that delivers the autonomous driving\ncapability, high performance computing and infotainment experience to Tesla vehicles and Tesla Super Computer AI. The team designs the complex, high speed printed circuit boards that delivers on computation performance while meeting\nefficiency, cost and reliability. We are looking for a PCB Layout Design Engineer to implement effective design practices to bring high speed print circuit board from proof of concept to mass production.\n\nResponsibilities:\n·        High speed PCB layout: implement effective high speed design practices into complex multilayer HDI PCB.\n·        Communication: work effectively with cross functional teams to ensure design requirements are met and provide feedback and solution on the board level for the issues related to hardware, SI/PI, mechanical, thermal and manufacturing.\n·        Effectiveness: optimize PCB design to minimize DFM/DFT issues as indicated by vendors.\n·        Support: generate documentation for PCB fabrications and assembly.\n\nPreferred qualifications:\n·        5+ years of relevant circuit board design experience.\n·        Proficiency in HDI PCB design using fine pitch BGA with multilayer PCB boards.\n·        Proficiency in Cadence Allegro.\n·        Experience with high-speed interface layout design rules such as DRAM, CSI, PCIe, etc.\n·        Experience with power supply and switching regulators layout.\n·        Knowledge on PCB materials and develop board stackup per design requirement.\n·        Strong capability to drive project and finish qualified design on time.\n·        Experience with IPC standards and practices. CID an asset.\n·        Excellent communication skills with strong initiative and the ability to work in a highly collaborative, team environment.", "jd_status": "stored"}, {"title": "Design Verification Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-10-23", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018767", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n Join the APP-LP (Analog Power Products - Linear Power) team, where we push the boundaries of power management silicon. Our group manages an extensive and highly diverse product portfolio that spans precision voltage references, LDO's, sophisticated protection circuitry like eFuses and high-side switch controllers. Working within APP-LP means tackling unique engineering challenges across a wide spectrum of technologies, including high-speed switching and ultra-low-dropout (LDO) regulation. We build the fundamental building blocks that enable safe and seamless power delivery in any system architecture.\n\nIf you like to dig deeper, love finding root causes and not just report issues, are passionate about quality, do not want to get bounded by functional boundaries, then we did love to hear from you. \n\nWhat will you be doing in this role? (Responsibilities)\n\nYou will be responsible for driving silicon quality by preventing bugs from creeping into silicon, and making continuous improvements to address hitherto non-simulatable issues and driving efficiency improvements by adapting and developing methodologies for faster execution.\n\n1.      Verification Planning: Develop detailed, coverage-driven verification plans in close collaboration with System and Design teams. Able to identify the test plan segregation between Analog, digital and analog mixed signal test bench.\n\n2.      Mixed-Signal Modeling: Create behavioral modeling of analog blocks using SV RNM/ Verilog-AMS (wreal, electrical).\n\n3.      System-Level Testing: Identify and develop system-level tests in AMS to ensure bug-free silicon.\n\n4.      Electrical characterization: Identify the Electrical Characterizations scenarios to be verified on SoC top.\n\n5.      Testbench Development: Independently develop testbenches using efficient approaches, develop tests, checkers, and assertions, enhancing them with randomization and coverage.\n\n6.      Methodology Innovation: Drive and implement new, improved design verification methodologies and work with EDA teams to upgrade tools and flows.\n\n7.      Post-Silicon Support: Interact with Test/Validation teams during various post-silicon activities and assist in customer debug and analysis. Address methodology improvements in cases of simulation to silicon correlation gaps. \n\n8.      Cross-Functional Collaboration: Work closely with Systems engineers, Digital and Analog Designers  to understand the full-chip expectations and test and validation teams during silicon bring-up and debug. \n\nWhat You Can Expect?\n\nProfessional Growth & Impact\n\nEnd-to-End Ownership: Gain full product development experience, contributing to the entire lifecycle from initial concept to successful productization.\n\nSilicon-Level Engagement: Move beyond the virtual environment with hands-on opportunities in silicon debug and the critical task of silicon-to-simulation correlation.\n\nComplex Problem Solving: Tackle high-level challenges that span the analog/digital boundary, pushing the limits of what is simulatable and challenging traditional design notions.\n\nTechnical Excellence & Mastery\n\nMethodology Leadership: Exercise autonomy in defining and implementing the optimal verification methodology tailored to the specific demands of the product.\n\nDeep-Dive Debugging: Develop the ability to interpret complex analog schematics and RTL to independently root-cause simulation failures.\n\nSimulation Optimization: Master analog/digital simulator concepts, making informed, high-impact decisions regarding the trade-offs between simulation accuracy and execution speed.\n\nQuality Ownership: Take full accountability for silicon quality by architecting and deploying highly efficient, effective, and robust verification approaches.\n\nSystem-Level Thinking: Transition from a \"component-only\" mindset to a \"system-level\" approach. You will be expected to translate complex system use cases and design specifications into sophisticated test cases that maximize coverage with maximum efficiency\n\nQualifications\nCore Qualifications\n\n1.      Education: Bachelor’s or Master’s degree in Electrical or Electronics Engineering.\n\n2.      Mixed-Signal Fundamentals: Strong understanding of analog building blocks, digital design processes, and top-level integration.\n\n3.      Verification Expertise: Proven experience in developing mixed-signal testbenches in SV/UVM from scratch, including the ability to debug and optimize simulation performance and understand necessary trade-offs.\n\n4.      Debug Skills: Strong simulation debug capability with the ability to analyze waveforms and pinpoint issues in schematic simulations or models, including ability to read and interpret analog transistor level schematics and RTL codes. \n\n5.      Controller Knowledge: Familiarity with analog controllers to develop system-level testbenches and debug complex issues.\n\nSoft Skills\n\n1.      Drive: A self-driven individual with a thirst for continuous learning.\n\n2.      Communication: Excellent interpersonal and communication skills.\n\n3.      Teamwork: A collaborative attitude with the ability to function effectively both independently and within a team.\n\nPreferred Skills & Experience\n\n1.      Experience: 1–3 years of professional experience in mixed-signal design verification.\n\n2.      Tool Proficiency: Expertise in Cadence Mixed-Signal Design Environment tools (Virtuoso, ADE Assembler, Xcelium, VIVA, and Simvision).\n\n3.      Simulation Mastery: Expertise in Cadence Spectre simulation testbench development, regression flows, and debugging.\n\n4.      HDL Mastery: Advanced proficiency in SystemVerilog, UVM, and Verilog-AMS; experience writing checkers, assertions, and monitors for top-level simulations.\n\n5.      Automation: Proficiency in automation using Python, Perl, Tcl, or Shell scripting.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Career Accelerator Program - Test Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-10-23", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25019234", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n In your first year with TI, you will participate in the Career Accelerator Program (CAP), which provides professional and technical training and resources to accelerate your ramp into TI, and set you up for long-term career success. Within this program, we also offer function-specific technical training and on-the-job learning opportunities that will encourage you to solve problems through a variety of hands-on, meaningful experiences from your very first day on the job. The TMG Development program is a 12-month program for new college graduates in the TMG organization.\n\nAt Texas Instruments (TI) a Test Engineer is part of a team responsible for designing, developing, and implementing cost-effective methods of testing and troubleshooting systems and equipment. In this role, the Test Engineer prepares test and diagnostic programs, designs test fixtures and equipment, completes specifications and procedures for new products.\n\nResponsibilities include:\n\nWork with design team to understand design specifications\n\nGenerate test plan, creating test and char program, designing ATE hardware interface boards\n\nDebug characterizing silicon on ATE, correlate results with bench data\n\nAnalyze silicon results, supporting failure analysis tasks\n\nPerform statistical analysis of yield fallout, debugging and fixing yield issues; optimizing test time\n\nWork with production team to release products to volume production\n\nCreate test strategy definition and implementation for new products\n\nWork silicon qualification& characterization including qual hardware development\n\nComprehensive device debugging, design validation and failure analysis\n\nDrive for robust and cost effective test solutions while being accountable for product quality\n\nQualifications\nMinimum requirements:\n\nBachelors in Electrical Engineering\n\nPreferred qualifications:\n\nATE experience on Teradyne Eagle or equivalent analog ATE (iFlex, LTX, VLCT)\n\nCharacterization test program and hardware development knowledge\n\nProduction test program and hardware development knowledge\n\nTechnical knowledge of electronic devices and circuits, and Analog test techniques\n\nData analysis skills using Spotfire, dataPower or equivalent tool based on STDF\n\nExperienced with various lab equipment such as scopes, power supplies, sourcemeters, loads etc.\n\nExperience with product engineering activities such as yield improvement and test time reduction\n\nUnderstanding of the IC product development process, from concept to volume production\n\nProficiency in programming/scripting in C++, Python, C#\n\nDemonstrated strong analytical and problem solving skills\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nStrong time management skills that enable on-time project delivery\n\nDemonstrated ability to build strong, influential relationships\n\nAbility to work effectively in a fast-paced and rapidly changing environment\n\nAbility to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Career Accelerator Program - Test Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-10-23", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25019235", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n In your first year with TI, you will participate in the Career Accelerator Program (CAP), which provides professional and technical training and resources to accelerate your ramp into TI, and set you up for long-term career success. Within this program, we also offer function-specific technical training and on-the-job learning opportunities that will encourage you to solve problems through a variety of hands-on, meaningful experiences from your very first day on the job. The TMG Development program is a 12-month program for new college graduates in the TMG organization.\n\nAt Texas Instruments (TI) a Test Engineer is part of a team responsible for designing, developing, and implementing cost-effective methods of testing and troubleshooting systems and equipment. In this role, the Test Engineer prepares test and diagnostic programs, designs test fixtures and equipment, completes specifications and procedures for new products.\n\nResponsibilities include:\n\nWork with design team to understand design specifications\n\nGenerate test plan, creating test and char program, designing ATE hardware interface boards\n\nDebug characterizing silicon on ATE, correlate results with bench data\n\nAnalyze silicon results, supporting failure analysis tasks\n\nPerform statistical analysis of yield fallout, debugging and fixing yield issues; optimizing test time\n\nWork with production team to release products to volume production\n\nCreate test strategy definition and implementation for new products\n\nWork silicon qualification& characterization including qual hardware development\n\nComprehensive device debugging, design validation and failure analysis\n\nDrive for robust and cost effective test solutions while being accountable for product quality\n\nQualifications\nMinimum requirements:\n\nBachelors in Electrical Engineering\n\nPreferred qualifications:\n\nATE experience on Teradyne Eagle or equivalent analog ATE (iFlex, LTX, VLCT)\n\nCharacterization test program and hardware development knowledge\n\nProduction test program and hardware development knowledge\n\nTechnical knowledge of electronic devices and circuits, and Analog test techniques\n\nData analysis skills using Spotfire, dataPower or equivalent tool based on STDF\n\nExperienced with various lab equipment such as scopes, power supplies, sourcemeters, loads etc.\n\nExperience with product engineering activities such as yield improvement and test time reduction\n\nUnderstanding of the IC product development process, from concept to volume production\n\nProficiency in programming/scripting in C++, Python, C#\n\nDemonstrated strong analytical and problem solving skills\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nStrong time management skills that enable on-time project delivery\n\nDemonstrated ability to build strong, influential relationships\n\nAbility to work effectively in a fast-paced and rapidly changing environment\n\nAbility to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Physical Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-10-23", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25019240", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n As a Digital IC Design Engineer, you'll architect new TI products and make our customers' visions a reality. You'll define, design, model and verify digital circuits, which fully meet the performance, power, cost and schedule requirements. You'll define, design, model, implement and document the world first 64-bit DSP processor, MMU and heterogeneous multicore shared memory and cache systems including coherent TI DSP and ARM processors. You'll have the opportunity to work in exciting areas such as CPU simulator development, 64-bit vector processor ISA architecture, development and verification etc.\n\n As a Digital IC Design Engineer, some of your responsibilities may include:\n\nPartner with business teams and system engineering to develop mutually agreeable design specifications\n\nProvide high-level analysis on chip architecture trade-offs to ensure spec compliance and superior performance at a competitive cost\n\nParticipate in design reviews and creating the necessary design and product documentation\n\nSupervise IC layouts to ensure a high-performance standard\n\nCharacterize prototypes, developing test specifications and coordinating with test/product engineering to drive product releases\n\nDrive behavioral models\n\nPut your talent to work with us as a Digital Design Engineer !\n\nTexas Instruments will not sponsor job applicants for visas or work authorization for this position.\n\nQualifications\nMinimum requirements:\n\nBachelors degree in Electrical Engineering, Electronics Technology, Electrical Engineering Technology, Electrical and Computer Engineering or related field\n\nCumulative 3.0/4.0 GPA or higher\n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Principal Engineer - SOC Verification", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-10-23", "url": "https://careers.arm.com/job/bengaluru/principal-engineer-soc-verification/33099/102340648928", "is_hardware": true, "platform": "talentbrew", "jd_text": "About Solutions SoC Engineering\nJoin the Solutions SoC Engineering organization and help shape the future of silicon. We are building a world-class engineering organization focused on delivering innovative, high-performance, and energy-efficient SoC solutions that power next-generation computing across diverse markets.\n\nAs a rapidly growing global team, we bring together expertise across architecture, design, verification, emulation, FPGA, software, and post-silicon validation to deliver first-time-right silicon. Our engineers solve some of the industry's most challenging engineering problems using advanced verification methodologies, automation, and AI-driven tools while maintaining the highest standards of quality and execution.\n\nOur culture is built on technical excellence, ownership, collaboration, and continuous learning. We invest in our people, encourage innovation, and provide opportunities to influence engineering methodologies, contribute across the product lifecycle, and grow alongside an organization that is defining the future of SoC engineering.\nRole Overview\nAs a Design Verification Engineer, you will verify complex Arm-based IPs, subsystems, and SoCs powering next-generation computing platforms. You will develop scalable verification solutions, own end-to-end verification execution, and contribute to advanced SoC methodologies.\nKey Responsibilities\nDevelop and execute verification strategies for IP, subsystem, and SoC designs.\nVerify CPU, PCIe, DDR, Security, coherency, memory subsystem, and interconnect functionality.\nPerform power-aware verification and system scenario/performance validation.\nOwn verification deliverables from planning through verification closure while ensuring quality, schedule, and execution commitments are met.\nArchitect, develop, and maintain reusable verification environments, verification IPs, methodologies, and automation.\nDevelop verification plans, test methodologies, test cases, and coverage closure strategies.\nDrive functional, code, toggle, assertion, and coverage closure.\nDebug RTL, testbench, integration, and system-level issues.\nCollaborate with architecture, design, firmware, emulation, FPGA, validation, and post-silicon teams.\nLeverage automation, scripting, and AI-assisted workflows to improve verification productivity.\nContribute to methodology improvements, documentation, and engineering best practices.\nRequired Skills and Qualifications\nBachelor's or Master's degree in a relevant engineering discipline.\n13+ years of IP, subsystem, or SoC verification experience.\nStrong Verilog, SystemVerilog, UVM, and modern verification methodologies.\nExperience with Arm-based SoC architecture, coherency, interconnects, memory hierarchy, and UPF.\nExperience with C/C++, scripting, coverage closure, and strong RTL/testbench debug.\nExcellent analytical, communication, and collaboration skills.\nDesired Skills and Qualifications\nExperience with CHI, ACE, AMBA, PCIe, DDR, or Security IP.\nArm System Architecture knowledge.\nAssembly programming.\nFormal verification, emulation, FPGA, gate-level simulation, or post-silicon validation.\nAI-assisted verification and globally distributed engineering experience.\n#LI-KR2\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Staff Design Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-10-23", "url": "https://careers.arm.com/job/bengaluru/staff-design-engineer/33099/102318150416", "is_hardware": true, "platform": "talentbrew", "jd_text": "Responsibilities \n\nAs a creative design engineer with a strong understanding of subsystems and SoC Architectures, you will be part of a team responsible for developing advanced Subsystems & SoCs. \n\nYou will work the Architecture team to gather the requirements and develop Micro-architecture specifications for one or more SOC Infrastructure areas such as Clocking, Reset, Debug, Power management, Interconnect, Interrupts. \n\nYour key responsibilities will include writing micro-architecture specifications, developing the RTL, fixing bugs and running various design checks. \n\nYou will work with the verification team to review test plans and help debug design issues. \n\nYou will work with the Power and Performance analysis team to evaluate and improve Subsystem/SOC PPA. \n\nYou will also contribute to developing and enhancing the design methodologies used by the team. \n\nYou will guide and support other members of the team as needed to enable the successful completion of project activities. \n\nYou will balance other opportunities such as working with Project Management on activities, plans, and schedules \n\n  \n\nRequired Skills and Experience: \n\n  \n\nA bachelor’s or master’s degree in computer science or electrical/computer engineering. \n\n8+ years’ experience in design and developments of complex compute subsystems or SoCs, along with the following skills and expertise:  \n\nExpertise in creating Micro-architecture and Design specifications for the SoC Infrastructure areas such as Clocking, Reset, Debug, Power management, Interconnect, Interrupts. \n\nStrong knowledge of digital hardware design and Verilog HDL. \n\nA thorough understanding and experience of the current design techniques for complex SoC development. \n\nExperience leading and developing RTL for Subsystems or SoCs. \n\nConversant with Lint, CDC, RDC, UPF/CLP flows. \n\nGood communication (written, verbal, presentations) skills.  \n\nExperience with Perl, Python or other scripting language \n\n  \n\nDesired Skills and Experience: \n\nExperience with ARM-based designs and/or ARM System Architectures \n\nExperience developing subsystems for Interconnect, DDR/LPDDR, HBM, UCIe. \n\nExperience with System Verilog and verification methodologies – UVM/OVM \n\nExperience leading small teams or projects \n\nExperience or knowledge in the following areas \n\nSynthesis and timing analysis \n\nConstraint development and hand-off to Implementation \n\nPower management and Power optimization methodologies \n\nDFT and physical implementation \n\n10x Mindset at Arm\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Read more about how we bring the 10x mindset to life on the Arm blog.\n \n#LI-SC2\n\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Analog IC Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-10-23", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25019136", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\n This is a great opportunity to be part of an established team that's continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electronics, mobile computing and communications.\n\nIn this role, responsibilities may include:\n\nLead an Analog IC design team with product ownership and responsibility from definition to release to manufacturing\n\nDirect, guide and participate in activities of a research or technical design function responsible for designing, developing, modifying and evaluating electronic parts, components, integrated circuits for a variety of applications\n\nMake assignments for team members, providing design guidance as needed, developing schedules and monitoring progress throughout the project\n\nEvaluate intermediate and final results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout\n\nCollaborate with Design Verification teams during the pre-PG phase of a project to ensure completion of all technical tasks before PG\n\nWork with systems engineers, application engineers and marketing to prepare product briefs, datasheets, application notes and assisting in the definition of the product to meet customer needs as well as contributing to roadmap formulation and new concept creation\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nInterface and lead discussions with the customer and/or TI field sales/field applications teams to understand customer designs, problems and support as required\n\nActively participate in hiring, developing and evaluating personnel to ensure efficient operation of the organization and growth of the individuals into leader\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in Electrical Engineering\n\nXX years of relevant experience\n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Design Verification Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-10-23", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25019216", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\nAs a verification engineer in this group, the candidate will be responsible for:\n\nDeveloping detailed verification plans while working closely with the design and system team\n\nDeveloping test benches, tests and simulations at RTL and GLS\n\nRunning coverage regressions to meet the defined coverage goals\n\nTracking and communicating verification status, issues, and concerns\n\nQualifications\nMinimum Requirements:\n\nBachelor' degree in Electrical Ebgineering, Electrical & Computer Engineering, Computer Engineering or related field of study\n\nCumulative 3.0/4.0 GPA or higher\n\nPreferred Qualifications:\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nWorking well in a team environment is imperative in this role.\n\nDemonstrated ability to build strong, influential relationships\n\nGood listener and excellent verbal and written communication skills\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Sr Manager - DFT", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-22T12:58:00+00:00", "url": "https://global-external-amd.icims.com/jobs/93446/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. Senior Manager, DFT THE ROLE: As a Senior Manager – DFT Design within the S3 SoC DFT Team, the successful candidate will provide technical and people leadership for the DFT organization responsible for the architecture, design, integration, verification, and silicon enablement of advanced DFT solutions across complex SoCs. The candidate will lead a team of DFT engineers and work closely with DFT Architecture, RTL Design, Verification, Physical Design, STA, Test, and Post-Silicon teams to drive robust and scalable DFT solutions across multiple programs. This role requires a strong combination of deep DFT technical expertise, team leadership, execution ownership, and cross-functional collaboration. KEY RESPONSIBILITIES: Lead and manage a team of DFT engineers responsible for end-to-end DFT design, integration, verification, and implementation. Provide technical leadership for complex DFT architectures including Scan, ATPG, MBIST, Boundary Scan/JTAG and related test methodologies. Own DFT execution from architecture and requirements definition through RTL implementation, verification, physical implementation support, pattern generation, and silicon bring-up. Partner closely with DFT Architecture and IP/SoC Design teams to define requirements and drive successful DFT implementation across complex SoCs. Drive correct-by-construction DFT methodologies, design quality, verification completeness, and predictable execution. Work closely with RTL Design, Verification, Physical Design, STA, and Test Engineering teams to resolve complex design, timing, implementation, and testability challenges. Lead technical reviews and provide guidance on DFT architecture, methodologies, implementation, verification, and debug. Drive execution planning, resource prioritization, risk identification, and timely closure of technical dependencies and program deliverables. Develop and improve DFT methodologies, automation, flows, and infrastructure to improve engineering productivity and design quality. Provide hands-on technical guidance for complex ATPG, scan, MBIST, timing, simulation, and silicon-debug issues. Build and develop engineering talent through mentoring, technical guidance, and capability development. Collaborate effectively with geographically distributed engineering teams and stakeholders. PREFERRED EXPERIENCE: Extensive experience in ASIC/SoC DFT architecture, design, integration, verification, and implementation. Strong experience leading end-to-end DFT execution for complex, high-performance SoCs. Demonstrated experience leading and mentoring DFT engineers and driving technical execution across multiple projects/programs. Deep understanding of Scan insertion, ATPG, compression, MBIST, Boundary Scan/JTAG, test modes and test architecture. Strong experience with industry-standard DFT and implementation tools such as Siemens Tessent, Synopsys Design Compiler and SpyGlass or equivalent tools. Experience defining and developing scalable DFT flows and methodologies. Strong knowledge of RTL development and integration using Verilog/SystemVerilog. Experience integrating multiple IPs and DFT structures into large and complex SoCs. Good understanding of synthesis, simulation, CDC, lint, RTL quality checks, and design verification methodologies. Strong understanding of Static Timing Analysis, DFT timing constraints and timing closure. Experience in Scan/ATPG pattern generation, test-flow development, debug, coverage analysis, and characterization. Excellent hands-on debugging skills with the ability to drive complex technical issues to closure. Strong scripting and automation experience using Perl, Python and TCL. Understanding of low-power design concepts including clock gating and power gating. Experience with post-silicon bring-up and silicon DFT/debug is highly desirable. Strong communication, stakeholder-management, and organizational skills with the ability to work effectively across global engineering teams. Proven ability to balance technical depth, people leadership, program execution, and strategic priorities. ACADEMIC CREDENTIALS: B.E./B.Tech./M.E./M.Tech. in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline. Typically 15+ years of relevant semiconductor/SoC design experience, with significant experience in DFT and technical/team leadership. #LI-RR1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "AI Solution Engineer - Agentic AI", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-22T10:55:00+00:00", "url": "https://global-external-amd.icims.com/jobs/93585/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. AI Solutions Engineer – Debug Tools The Role: We are looking for a highly motivated AI Solutions Engineer to help transform how semiconductor debugging and tool readiness are delivered through AI-powered solutions. In this role, you will work directly with debug tools developers, architects, and SoC engineers to identify high-impact engineering problems and rapidly develop AI-driven solutions that improve productivity, accelerate bring-up activities, and shift-left debug readiness. The Person: You will serve as the bridge between engineering teams and AI technologies, turning complex debugging workflows into scalable AI-enabled experiences. The ideal candidate combines strong technical problem-solving skills, software development expertise, and a passion for applying modern AI technologies to real-world challenges. Key Responsibilities: Partner with debug tools leads, debug teams/key users to identify engineering bottlenecks and automation opportunities. Design, prototype, and deploy AI-powered solutions that improve debug efficiency, reduce manual effort, and accelerate root-cause analysis. Develop agentic workflows, copilots, MCP integrations, RAG systems, and AI assistants for semiconductor debugging use cases. Build proof-of-concepts and production-ready solutions using LLMs, AI agents, and automation frameworks. Translate semiconductor debug workflows into scalable software and AI solutions. Analyze logs, reports, register data, validation results, and other engineering artifacts to develop intelligent troubleshooting capabilities. Drive shift-left initiatives by enabling earlier defect detection, readiness validation, and automated diagnostics. Work closely with software, firmware, validation, and silicon teams to deploy solutions into daily engineering workflows. Measure business impact through productivity improvements, cycle-time reduction, and readiness acceleration. Evangelize AI best practices and help engineers adopt AI-first workflows. Required experience: • Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, Computer Science, or related field. 5-8 years of software engineering, automation, validation, or semiconductor engineering experience. Strong programming skills in Python. Experience developing enterprise applications, automation solutions, or engineering tools. Hands-on experience with Generative AI technologies including: LLMs (OpenAI, Azure OpenAI, Claude, Gemini, Llama, etc.) Agentic AI frameworks MCP (Model Context Protocol) Retrieval Augmented Generation (RAG) Vector databases and embeddings Prompt engineering and evaluation Experience building APIs, automation workflows, and integrations. Strong analytical and problem-solving skills. Excellent communication and stakeholder management abilities. Preferred Experience Experience in semiconductor debugging, silicon validation, bring-up, or DFT/debug environments. Familiarity with scan, JTAG, registers, validation logs, silicon debug, or post-silicon workflows. Experience with SoC architecture, debug tools, firmware validation, or hardware/software co-debug. Knowledge of GitHub Copilot, AI coding assistants, and developer productivity tools. Experience deploying AI solutions in production environments. Familiarity with data engineering, knowledge graphs, and search technologies. #LI-RG2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Principal Physical Design Engineer", "company": "Astera Labs", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-10-22T07:26:45-04:00", "url": "https://job-boards.greenhouse.io/asteralabs/jobs/4746472005", "is_hardware": true, "platform": "greenhouse", "jd_text": "Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\n\n \n\nPhysical Design \n\nAstera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.  \n\nBasic qualifications:\n\nStrong academic and technical background in electrical engineering. A Bachelor’s degree in EE / Computer is required, and a Master’s degree is preferred.\n\n≥10 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.\n\nProfessional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. \n\nEntrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!\n\nRequired experience:\n\nHands-on and thorough knowledge of synthesis, place and route, CTS, extraction timing analysis/STA, Physical Verification and other backend tools and methodologies for technologies 16nm or less, preferably 7nm or less.\n\nProven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level.\n\nFull chip or block level ownership from architecture to GDSII, driving multiple complex designs to production.\n\nExperience with Cadence and/or Synopsys physical design tools/flows.\n\nFamiliarity and working knowledge of System Verilog/Verilog.\n\nExperience with DFT tools and techniques.\n\nExperience in working with IP vendors for both RTL and hard-mac blocks.\n\nGood scripting skills in python or Perl\n\nPreferred :\n\nGood knowledge of design for test (DFT), stuck-at and transition scan test insertion.\n\nFamiliarity with DFT test coverage and debug.\n\nFamiliarity with ECO methodologies and tools.\n\n \nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.", "jd_status": "stored"}, {"title": "Staff/ Senior Staff Engineer, STA", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-22T05:54:51.636000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000157040169-staff-senior-staff-engineer-sta", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are looking for a highly motivated STA Engineer to join our VLSI design team. The ideal candidate will be responsible for driving timing closure and signoff readiness for block-level and full-chip designs across all operating modes and process corners. This role involves developing and validating timing constraints, performing comprehensive timing analysis, and collaborating closely with RTL Design, Synthesis, Clock Tree Synthesis (CTS), and Physical Design teams to identify, debug, and resolve timing violations. The successful candidate will play a key role in achieving timing convergence and delivering high-quality silicon through successful tapeout.\nThis position offers an opportunity to work on advanced semiconductor technologies and contribute to the development of high-performance, power-efficient SoCs.\nWhat You'll Do\nPerform block-level and full-chip Static Timing Analysis (STA) across all modes and corners in MMMC environments.\nAnalyze and debug setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations.\nDevelop, validate, and maintain timing constraints, including SDC creation, review, and signoff readiness.\nPartner closely with RTL Design, Synthesis, CTS, Physical Design, and Signoff teams to achieve timing closure goals.\nDrive timing closure through ECO implementation, timing optimization, and timing convergence activities.\nPerform pre-layout and post-layout timing analysis and support tapeout signoff requirements.\nAnalyze timing impact due to process, voltage, and temperature (PVT) variations and variation-aware methodologies.\nReview and validate timing exceptions including false paths, multicycle paths, case analysis, and clock definitions.\nIdentify root causes of timing violations and recommend effective optimization strategies.\nParticipate in cross-functional design reviews and provide guidance on timing-related issues.\nGenerate timing reports, closure metrics, and signoff summaries for project stakeholders.\nSupport design quality improvements by establishing and enhancing STA methodologies, automation, and best practices.\n\nRequired Qualifications\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, VLSI, Microelectronics, or a related field.\n7 to 13 years of hands-on experience in Static Timing Analysis (STA) and timing closure for block-level and/or full-chip semiconductor designs.\nStrong understanding of CMOS fundamentals, timing concepts, and end-to-end semiconductor design flow.\nSolid experience with setup/hold analysis, path-based analysis (PBA), and timing signoff methodologies.\nIn-depth knowledge of OCV, AOCV, POCV, timing derates, uncertainty modeling, and MMMC analysis.\nStrong understanding of clock tree concepts including clock latency, skew, jitter, uncertainty, and clock propagation.\nExperience developing and debugging timing constraints and timing exceptions.\nGood understanding of SDC syntax, false paths, multicycle paths, generated clocks, and case analysis.\nHands-on experience with timing closure techniques and ECO methodologies.\nProficiency with industry-standard STA tools such as Synopsys PrimeTime and/or Cadence Tempus.\nGood scripting and automation skills using Tcl, Perl, Python, or similar languages.\nStrong analytical, debugging, and problem-solving skills with the ability to independently resolve complex timing issues.\nExcellent communication and collaboration skills in cross-functional engineering environments.\nPreferred Qualifications\nExperience with low-power timing analysis and UPF/CPF-aware STA methodologies.\nFamiliarity with signal integrity (SI)-aware timing analysis, crosstalk analysis, and IR-drop-aware timing closure.\nUnderstanding of advanced technology nodes and variation-aware signoff methodologies.\nExposure to automation, flow development, and methodology enhancement.\nExperience collaborating with Physical Design, RTL, Verification, DFT, and Signoff teams.\nKnowledge of advanced timing signoff practices for high-performance and low-power SoCs.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Staff Engineer, Physical Design", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-22T05:44:51.032000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000157039359-senior-staff-engineer-physical-design", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.\nRenesas India is seeking an experienced Staff / Senior Staff Physical Design Engineer to lead subsystem- and block-level physical implementation and closure for complex hierarchical SoCs at advanced technology nodes. This role requires deep expertise in timing, congestion, power integrity, and clocking methodologies, along with strong cross-functional collaboration skills. While this role does not own SoC-level physical design, it plays a critical role in aligning subsystem implementation with overarching SoC strategies.\nKey Responsibilities\nLead block- and subsystem-level physical design closure, including timing closure, congestion mitigation, power integrity, and overall physical implementation quality\nCollaborate closely with SoC-level physical design teams to align on clocking strategies, floorplanning intent, and integration requirements, without direct ownership of SoC-level execution\nApply deep understanding of clocking methodologies to ensure subsystem-level clock domains integrate cleanly into the broader SoC clock architecture\nDevelop, refine, and scale subsystem closure methodologies, flows, and automation, improving predictability, quality, and execution efficiency\nMentor and guide physical design engineers within subsystem teams, promoting best practices, technical rigor, and methodology adoption\nWork cross-functionally with RTL design, STA, power, verification, and backend teams to ensure smooth handoffs and robust closure\nProactively identify, assess, and mitigate physical design risks, coordinating closely with SoC teams to manage impacts and drive solutions\n\n7+ years of experience in physical design, with a strong focus on subsystem-level closure for complex hierarchical SoCs\nStrong expertise in:Timing closure and constraint management\nCongestion analysis and resolution\nPower integrity and power-aware physical implementation\nBlock and subsystem-level physical design flows\n\nSolid understanding of SoC-level floorplanning and clocking methodologies, including:Clock domain partitioning\nClock tree architecture\nSkew management\nClock gating\n\n(Candidate is expected to collaborate effectively at the SoC level, not lead these activities.)\n\nHands-on experience with industry-standard tools such as:Synopsys ICC2, Fusion Compiler, PrimeTime\nCadence Innovus, Tempus, Certus\nSignoff and analysis platforms\n\nProficiency in scripting and automation using Tcl, Python, and/or Perl\nDeep knowledge of end-to-end SoC design flows, with strong collaboration experience across timing, power, clocking, verification, and backend teams\nStrong understanding of low-power design techniques and power-aware implementation methodologies\nEducation\nBTech or MTech in Electronics and Communication, Electrical Engineering, Computer Science, or a related field\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Bring up and Characterization Engineer", "company": "Graphcore", "location": "Bengaluru, India", "date_posted": "2026-10-22T01:27:26-04:00", "url": "https://job-boards.greenhouse.io/graphcore/jobs/8899580002", "is_hardware": true, "platform": "greenhouse", "jd_text": "Bring-Up and Characterization Engineer\n\nMultiple roles across different levels\n\nGraphcore is a globally recognized leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialized processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. \n\nAs part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing.  \n\nWe are looking for a Characterisation and Bring-Up engineer to work with Architecture, Silicon Engineering, Hardware Engineering, Operations (device manufacture) and Product teams to help create and execute the bring-up and characterisation of our cutting-edge silicon devices and system platforms. Graphcore design and develop leading edge silicon processors and high-power high-speed blade systems at the forefront of AI technology. As such you will need to develop a detailed understanding of our silicon and platform products. Your role will be to create and execute bring-up and characterisation plans of our silicon devices in systems to show that they will operate correctly over all conditions in the final product. You will concentrate on automated and manual testing of systems in the lab and datacentre. The results will be integrated with data from other teams to provide the complete characterisation solution for the product. For example, a large amount of device testing can be performed by the production test team using high-speed production test equipment. \n\nResponsibilities and Duties \n\nUnderstand the architecture and design of silicon devices and systems, and clearly document the requirements for characterisation\n\nCreation of product specific characterisation plans\n\nLiasing with engineering teams to understand what are tests are available for characterisation purposes and driving change where appropriate\n\nCreate and maintain an automated system for running characterisation testing, capturing the results to a central database and performing data analysis\n\nExecution of manual characterisation tests where automation is not appropriate\n\nReport regularly on progress and issues during the characterisation\n\nProduce characterisation reports containing platform test results and feeding them up into the overall product characterisation report\n\nEssential skills\n\nA proven track record of delivering technical output, perhaps as an individual contributor, manager, or project manager\n\nSolid experience and understanding of silicon digital device design characterization\n\nKnowledge of silicon process technology and how that impacts device performance at transistor and system level\n\nKnowledge of high-performance processor and system-on-chip systems\n\nExperience of high-speed digital interfaces, such as PCIe, Ethernet or DDR\n\nKnowledge of measurement automation and data analysis\n\nThe ability to code or script automation and data analysis using appropriate coding languages such as Python, JMP for example\n\nAn ability to work independently without daily oversight\n\nDesirable skills:\n\nKnowledge of PCBA and system level technologies\n\nBackground knowledge of ATE systems and capabilities. Whilst you will not be directly involved with such testing, some of the characterisation work will be performed on such systems\n\nBenefits:\n\nIn addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.", "jd_status": "stored"}, {"title": "Staff Signal Integrity Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-22T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721627021", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n\nTitle - Staff Signal Integrity Engineer\n\nThis role represents individual contributor within the CHS Signal Integrity organization responsible for end-to-end SI/PI architecture, analysis, and signoff for next-generation mobile, compute, Automotive and various other connectivity platforms.\n\nThe engineer acts as\nSystem SI/PI owner across full platform (SoC ↔ package ↔ board ↔ connectors ↔ external systems)\nTechnical owner for high-speed interfaces and system margins\nCross-functional leader driving SIPI driven design convergence across silicon, package, and platform teams\n\nCore Responsibilities\nOwn end-to-end SI/PI closure for programs (pre-silicon → post-silicon → production)\nDefine design targets and layout design guidelines for all high-speed interfaces\nInfluence architecture decisions early in product lifecycle\nEnsure SI/PI alignment with product KPIs (performance, yield, power, cost)\nDrive new IP co-design across IC/IO/PHY, package, and PCB\nEnsure compliance to standards (JEDEC, PCI-SIG, MIPI, IEEE)\nInfluence PDN architecture definition at system and package level, provide related optimum cost solutions\nEnsure cross functional alignments. Partner with SoC/PHY design teams, Package engineering, Board/system teams and OEM/ODM ecosystem\nLead design reviews and signoff decisions\nRepresent SI/PI in program reviews and leadership forums\nDefine company-wide SI/PI methodologies\nDrive correlation between pre-silicon models and silicon/lab data\nLead debug of eye collapse / jitter margin issues, crosstalk and power noise and silicon-package-board interactions\nDrive best practices adoption across programs\nEstablish golden methods for system SI/PI\nMentor senior engineers across SI/PI domains\n\nHigh-Speed Interface Expertise\nDrive SI/PI for interfaces such as:\nMemory: LPDDR4/5/6\nHigh-speed IO: PCIe Gen4/5/6/7, USB4, UFS, 10G–112G+ PHYs\nCamera/Display: MIPI CSI/DSI\nSystem PDN\n\nRequired Qualifications / Experience\n8+ years in Signal Integrity / Power Integrity / High-speed systems\nProven ownership of multiple tapeouts or high-volume products\n\nDomain Expertise\nDeep expertise in Transmission line theory, EM fundamentals, SI/PI interactions and jitter/noise coupling. Strong hands-on experience with: Tools: HFSS, ADS, Sigrity, CST, SIwave, HSPICE; Measurement: VNA, TDR, real-time scopes\n\nPreferred Differentiators\nExperience with: Packaging technologies like FCBGA, 2.5D/3D; Products like Data center, Compute and Servers\nTrack record of Patents, standards contributions, or published work internal / external conferences\nyou will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Lead Layout Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-22T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721650492", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Services Group, Engineering Services Group > Layout Engineer\nGeneral Summary:\nDevelops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues.\n\nMinimum Qualifications:\n•    Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 3+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.\n                                                                    OR\nAssociate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 5+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.\n                                                                    OR\nHigh School diploma or equivalent and 7+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.\n\n•    3+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap).\n\n*Completed advanced degrees in a relevant field may be substituted for up to two years (Master’s = one year, Doctorate = two years) of the general custom layout design work experience in a relevant domain (e.g., analog, mixed signal, RF, digital design).\n\nCandidate needs to have hands on experience on various Power Management (PMIC) Module layouts, physical verification using Calibre Verification suite.  Skill sets needs to include but not limited to the following:\nExtensive floor planning and signal planning skills in Cadence Virtuoso IC201 and above.\nLayout Design for various analog circuits like: Linear and Switching Regulators, ADCs, DACs, CHARGERS, Envelope Trackers, APTs, High Current POWERFETS, OTAs, Error Amplifiers, etc.\nStrong understanding of submicron, deep-submicron, High Voltage CMOS processes. SOI process knowledge is an advantage.\nVery strong analog layout fundamentals and basic electrical knowledge for layout development.\nStrong physical verification debugging capability using Calibre Verification Suite.\nCreate area and parasitic efficient layouts, with strong problem-solving skills.\nAbility to perform in a dynamic, team-oriented environment.\nWell-developed organizational skills and the ability to multi-task.\nScripting knowledge in SKILL/PERL/SHELL and hands on knowledge of AI based layout development flow is an advantage\nStrong communication skills for efficient delivery.\nTeam player skills to work with geographically spread team members.\nCreate technical documentation and presentations.\n Minimum Qualifications:\n Graduation in Electrical or Electronics is preferred with 5+ years of exp.\nDiploma with minimum 8 years of hands on layout development experience is also okay.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Engineer, ASIC Analog Design", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-10-22T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/43605082", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nKey Responsibilities\nBe part of a highly skilled and challenging high-speed PHY design team working on advanced technology nodes (12nm and below).\nOwn analog sub-blocks within the PHY and drive specification, design, simulation, reliability, and mixed-mode verification.\nLeverage AI-enabled tools to improve productivity and decision-making.\nDrive layout implementation through mask designers while ensuring compliance with process rules and DFM requirements.\nParticipate in design reviews with internal teams and customers, explaining design choices and robustness.\nCollaborate with cross-functional teams across multiple global locations.\nCreate IP EDA views including Behavioral models, Verilog-A, timing views, and abstracts.\nParticipate in silicon bring-up, characterization, and correlation of silicon results with models and simulations.\nMentor and guide junior engineers.\nCompetitive compensation and equal opportunity workplace.\nRequired Skills\nStrong analog/mixed-signal CMOS circuit design experience in deep sub-micron technologies (2nm to 28nm).\nExperience in High-Speed Memory Interfaces (DDR3/4/5, LPDDR5/6, GDDR5/6/7) or SerDes Interfaces (PCIe, MIPI, HDMI, USB, SATA, etc.).\nFull ownership experience of at least one critical PHY sub-block such as:PLL\nDLL\nCDR\nHigh-speed Receiver with Equalization\nTransmitter Front-End\nHigh-Speed Data Path\n\nDeep understanding of analog and mixed-signal design concepts with high-speed link experience.\nMandatory experience in SerDes and/or Parallel Interfaces.\nMandatory experience with TX/RX Equalization techniques (FFE, CTLE, DFE).\nExperience with CDR and clocking architectures.\nHands-on experience in FinFET technologies (10nm and below).\nAbility to develop block-level specifications based on link budgets.\nExperience in system-level modeling using Verilog-A and/or Python.\nExperience working with Packaging and Board teams.\nKnowledge of ESD design considerations.\nExperience in lab testing and collaborating with validation teams for data analysis.\nExperience designing high-speed I/O cells such as DDR, LVDS, HSTL, and CML.\nExperience with power delivery circuits including Bandgap, LDO, and Bias circuits.\nStrong understanding of AMS design, advanced CMOS, and FinFET technologies.\nKnowledge of mismatch analysis, Monte Carlo simulations, transistor-level noise analysis, and deep sub-micron device physics.\nExperience supervising complex analog layouts and defining IP floorplans.\nHands-on experience with industry-standard tools such as Cadence ADE, Spectre, AMS Verification, EM/IR flows, MATLAB, and Calibre.\nWorking knowledge of mixed-mode simulation, signal integrity, and ESD analysis.\nEducation & Experience\nM.S./M.Tech or B.S./B.E. in Electronics.\nExperience Required: 5+ Years.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Principal Engineer - SSD Hardware Design", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-10-22T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/41892191", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nSeeking a self-motivated, team-oriented board design & validation engineer to develop Micron’s next generation Solid State Drive (SSD) products.  This position requires experience in hardware design, signal integrity and power supply design and characterization. This would include modeling and simulation for high speed signaling implementations and power supply design including power distribution network (PDN) simulations.\n\nJob responsibilities:\nTechnical Expertise:\nCandidate should have in depth knowledge on PCIe interface Gen5 & Gen6, PCIe Base and CEM specs, LPDDR4/5, NAND memories, ONFI interface (preferred)\nStrong knowledge on DC-DC converters, Buck and Boost, PMIC, Power Loss Protection (PLP), LDO, Load Switch devices\nA thorough understanding of Signal Integrity (SI), Power Integrity (PI), and Electromagnetic Compatibility (EMC) requirements is very much important.\nHands on experience in performing measurements using low- and high-end Oscilloscopes, Power Analyzers, Logic Analyzers, PCIe analyzers\nDocument and communicate results with cross functional counterparts.\nSimulate and analyze design proposals, review results and provide recommendations on optimal design practices to other design engineers.\nExperience in Hardware design, worst-case analysis, simulations, capture schematic, de-rating and assumes complete ownership of the SSD hardware through the product lifecycle.\nHands on experience in hardware validation and characterization of DC-DC converters, LDOs, PMIC devices, I2C/I3C, SMBus, LPDDR5, PCIe interfaces with automation using Python & AI tools\nPCB back-end process: defining stack-up and via technologies, setting design constraints, signal integrity and power integrity analysis\nWorks proactively with cross functional team members during design, verification and validation\nAutomation of HW validation tests, hands on experience in Python coding for automation is preferred\nDesign and Development: Lead the design and development of Solid State Drives (SSDs) EDSFF (E3.S, E1.L, E3.L) and U.2 form factors, daughter cards, Evaluation and Test boards.\nQuality Assurance: Ensure all designs comply with industry standards (IPC) and regulatory requirements (UL, IEC).\nDocumentation: Maintain detailed design documentation, test reports, FMEA analysis reports and testing procedures.\nCollaboration: Work closely with other engineering teams, including simulation (SI/PI), mechanical engineers, FW validation engineers. Work closely with Micron teams located in others Geo’s with different time zones\nContinuous improvement: Participate in internal technical, DFM/DFA, Continuous Improvement, Industry standard and other meetings as necessary ​\nComfortable using AI tools\nQualifications:\nEducation: Candidate must have Bachelor’s/Master’s degree in Electronics Engineering, Electrical Engineering or related field.\nExperience: Candidate should have minimum of 10+ years of experience in hardware design, validation, debugging & root causing of hardware and system related issues.\nCommunication: Strong verbal and written communication skills to effectively collaborate with team members and stakeholders across different geographic centers.\n\nJob Location\nBengaluru, India\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Silicon & Data Automation Systems Software Engineer, Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-22T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719866630", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nJob Description\n\nWe are seeking a highly motivated and technically strong Staff Engineer, Silicon & Data Automation Systems to help build and expand a growing automation team supporting silicon and system yield engineering, spanning design, DFT, diagnostics, and yield engineering workflows. This role will focus on developing production-grade automation, data pipelines, database-backed applications, and engineering tools that improve the speed, quality, and scalability of complex semiconductor engineering workflows.\nThis position is part of a broader effort to increase automation capacity within the silicon engineering organization, beginning with new engineering roles in the Bangalore Design Center (BDC). The engineer will work closely with U.S.-based yield automation leadership and stakeholders, including regular overlap with U.S. Central Time morning hours.\nThis is a senior individual contributor role. The successful candidate will build new automation capabilities under architectural guidance, contribute to robust production systems, and use modern AI-assisted engineering practices to increase development velocity and quality. This role requires an AI-first engineering mindset, where LLM-based coding agents and AI-assisted automation tools are used as core productivity multipliers while maintaining strong human ownership of correctness, security, review, and production safety.\nThe ideal candidate is a strong Linux, data, database, and automation engineer who can work effectively in complex semiconductor engineering environments. Prior experience with semiconductor engineering domains such as silicon design, DFT, validation, diagnostics, or yield is strongly preferred but not required for candidates with strong automation and data engineering depth.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nAutomation Development & Production Engineering\nDesign, develop, test, and maintain automation tools that improve silicon and system yield engineering workflows, including data processing, diagnostics, reporting, and operation efficiency.\n\nBuild reliable Linux-based automation services, scripts, data loaders, and backend systems used by engineering teams.\n\nDevelop production-grade solutions with appropriate logging, monitoring, error handling, alerting, documentation, and operational supportability.\n\nContribute to systems that are maintainable, fault-tolerant, secure, and suitable for long-running production use.\n\nDebug and resolve automation issues across Linux servers, databases, file systems, scheduled jobs, data feeds, and dependent engineering systems.\n\nWork under architectural guidance to implement new automation capabilities while developing deeper ownership of specific tools, workflows, or data domains over time.\n\nData Systems & Database Automation\nBuild and maintain data pipelines that collect, transform, validate, and load engineering and manufacturing data across design, DFT, validation, diagnostics, and yield-related systems.\n\nWork with relational databases, SQL, schema design, query optimization, and database-backed automation workflows.\n\nIntegrate data from multiple sources, including engineering systems, manufacturing data feeds, logs, reports, and analysis outputs.\n\nDevelop tools that make complex data easier to access, validate, monitor, and act upon.\n\nEnsure data quality, traceability, and operational robustness in automation that supports engineering analysis and decision-making.\n\nAI-Assisted Engineering & Automation Acceleration\nUse LLM-based coding agents and AI-assisted automation tools responsibly as part of day-to-day engineering work.\n\nApply AI-assisted development practices to improve code quality, accelerate troubleshooting, generate tests, improve documentation, and increase engineering output.\n\nBuild or integrate AI-enabled engineering tools where appropriate, including automation agents, internal assistants, MCP servers, and workflow accelerators.\n\nMaintain strong human review and engineering judgment for AI-generated code, SQL, analysis, documentation, and operational recommendations.\n\nEnsure AI-assisted workflows follow appropriate standards for security, correctness, maintainability, and production safety.\n\nHelp establish practical patterns for using AI-first development methods in production engineering environments.\n\nTooling, Applications & Workflow Integration\nBuild backend tools, dashboards, web applications, APIs, command-line utilities, and scheduled automation to support engineering needs.\n\nUse appropriate technologies for the problem, including Python, shell scripting, SQL, Django or similar frameworks, REST APIs, log analytics tools, and enterprise data systems.\n\nIntegrate automation into existing engineering workflows without disrupting production operations.\n\nCollaborate with engineers and stakeholders to identify manual pain points and convert them into reliable automated solutions.\n\nCreate clear documentation, usage guidance, and operational notes so tools can be supported and extended over time.\n\nCross-Functional Collaboration\nWork closely with engineers across design, DFT, validation, diagnostics, and data domains to understand requirements and deliver practical solutions.\n\nCommunicate technical findings, implementation options, risks, and tradeoffs clearly to both software-oriented and semiconductor engineering audiences.\n\nParticipate in code reviews, design discussions, troubleshooting sessions, and production readiness reviews.\n\nCollaborate effectively across time zones, including regular overlap with U.S. Central Time morning hours.\n\nContribute to a growing team culture focused on engineering rigor, accountability, automation leverage, and continuous improvement.\n\nRequired Qualifications\nBachelor’s or Master’s degree in Computer Science, Electrical Engineering, Data Engineering, Software Engineering, or related field, or equivalent practical experience.\n\nStrong hands-on experience with Linux-based development and automation, including shell scripting, server-side troubleshooting, cron or scheduled jobs, file systems, permissions, and operational debugging.\n\nStrong programming skills in Python or a comparable language used for automation, data processing, backend systems, or engineering tools.\n\nStrong experience with SQL, relational databases, data modeling, query development, and database-backed applications.\n\nExperience building automation that processes, validates, transforms, or integrates large technical datasets.\n\nExperience developing production-quality software or automation with testing, logging, error handling, documentation, and maintainability.\n\nExperience using Git or similar version control systems in a collaborative environment.\n\nPractical experience using LLM-based coding agents or AI-assisted development tools to improve productivity.\n\nAbility to review AI-generated work critically and maintain ownership of correctness, security, reliability, and production readiness.\n\nStrong debugging and problem-solving skills across software, data, database, and Linux environments.\n\nExcellent written and verbal communication skills in English.\n\nAbility to work effectively with U.S.-based stakeholders with required time overlap.\n\nAdditional consideration:\nCandidates with strong software, data, or automation backgrounds from non-semiconductor domains will be considered if they demonstrate the ability to learn complex engineering workflows quickly.\n\nPreferred Qualifications\nExperience with semiconductor design, DFT, validation, diagnostics, yield, or product engineering environments.\n\nExperience working with engineering datasets such as test data, DFT outputs, manufacturing data, diagnostic data, or high-volume silicon or system telemetry.\n\nFamiliarity with semiconductor data formats such as STDF, KLARF, wafer maps, lot history, test results, binning, dispositions, or assembly data.\n\nExperience building automation for engineering teams in semiconductor, manufacturing, hardware, or similar domains.\n\nExperience with Oracle, PL/SQL, ODBC, database loaders, schema design, or production database integration.\n\nExperience with Django or similar backend frameworks.\n\nExperience with REST APIs, internal tools, dashboards, reporting systems, or workflow applications.\n\nExperience with log analytics, monitoring, Splunk, or observability tools.\n\nExperience with batch compute, distributed jobs, LSF or grid environments, or multi-server automation.\n\nExperience building or integrating AI-assisted tools, internal agents, MCP servers, or RAG workflows.\n\nFamiliarity with responsible AI-assisted development practices, including human-in-the-loop review and secure handling of generated outputs.\n\nExperience working across global teams and time zones.\n\nDesired Technical Profile\nThe ideal candidate operates across multiple layers of the engineering stack:\nLinux: Comfortable diagnosing runtime issues, managing scripts, and troubleshooting production systems.\n\nData: Able to handle complex, messy engineering data and build reliable transformations with traceability.\n\nDatabases: Strong SQL skills with practical understanding of schemas, performance, and data integrity.\n\nAutomation: Able to convert manual workflows into robust and scalable systems.\n\nProduction Mindset: Builds systems that are observable, maintainable, secure, and resilient.\n\nAI-First Engineering: Uses AI tools to increase output while maintaining full accountability.\n\nEngineering Communication: Works effectively with domain experts and delivers practical solutions.\n\nWhat Success Looks Like\nA successful engineer in this role will:\nDeliver reliable automation that reduces manual effort for silicon and systems yield engineering teams across design, DFT, diagnostics, and yield workflows.\n\nBuild data tools and pipelines that engineers trust and reuse.\n\nImprove development velocity and quality through responsible use of AI-assisted tools.\n\nContribute production-ready systems that scale across teams and time zones.\n\nLearn semiconductor workflows well enough to translate engineering needs into practical solutions.\n\nOperate as a strong senior individual contributor while growing into deeper ownership.\n\nHelp establish the foundation for a larger Bangalore-based automation capability.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RTL Design Verification  (NOC)- Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-22T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718664874", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    3+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n\nPrincipal Duties and Responsibilities:\n•    Applies Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Assists in the assessment of complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RTL Design(DDR)- Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-22T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720363603", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    8+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates complex features and functionality into hardware designs in line with proposals or roadmaps for complex products.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the novel manufacturing of solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for complex Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making is significant in nature and affects work beyond immediate work group.\n•    Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. \n•    Has a moderate amount of influence over key organizational decisions.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "DFT Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-22T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720715723", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nGood communication skills\nExperience in RTL/GLS verification at SOC.\nGood in Verilog/SV and familiarity with basic concepts of UVM and C-based test case bring up.\nExperience in Python/Perl or any other scripting tools.\nKnowledge in GLS/SDF debugs and problem solving.\nKnowledge in JTAG protocols and Boundary Scan architecture Verification.\nKnowledge in ARM based SOC architecture.\nKnowledge in Bus protocols (AHB, AXI, APB), Serial protocols (I2C, SPI, UART) and Peripherals(USB2/3, PCIE, UFS) PHYs.\nDebugging knowledge from Assertions/waveform dumps.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nEngineer, Senior(Exp : 2-5 years) :\nResponsible for RTL/GLS verification at SOC. Identifying issues in RTL/Netlist/Timing DBs and work with Design/PD teams.\nWorking in tools Verdi and VCS for Pre Silicon verification.\nVector generation and providing Post Silicon validation support to TE teams.\nDevelop C based testcases and integrate in SV UVM environment in SOC level.  \nUnderstand core level tests and create SOC level test plan and test cases.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "EDA Tools Hardware Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-22", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/EDA-Tools-Hardware-Engineer_JR0286973", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nDesigns, develops, and supports custom design infrastructure, EDA methodologies, and automation solutions for semiconductor testchip development across advanced technology nodes. Drives end-to-end enablement of testchip integration, custom layout design, E-Test structures, design libraries, and verification flows to accelerate process technology development and silicon readiness. Develops and maintains automation frameworks using SKILL, Python, and scripting languages for layout generation, library management, data migration, and design-flow optimization. Enables and validates CAD environments, version-control systems, and database infrastructures. Collaborates with design, process, technology development, reliability and validation teams to deliver scalable methodologies for full-chip integration, DRC/LVS verification, tape-in readiness, and silicon characterization.\n\nQualifications:\n•\tBachelor's / Master's degree in Electronics Engineering, Computer Science, or a related field.\n•\t3-10 years of experience in CAD software development, VLSI, or Design Enablement.\n•\tProficiency in SKILL, Python, and TCL/PERL programming.\n•\tKnowledge of VLSI concepts and EDA tools (Cadence/Synopsys).\n•\tKnowledge of Custom layout\n•\tKnowledge of Data Structures, Algorithms, and software optimization.\n•\tStrong problem-solving, teamwork, and communication skills.\n•\tFamiliarity with software development practices including version control, testing, and quality assurance\n\nPreferred Qualifications:\n•\tExposure to C/C++ or other object oriented programming languages.\n•\tKnowledge P-cell development and Testchip integration.\n•\tExposure to implementation of AI based applications in EDA tools.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "CPU Physical Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-22", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/CPU-Physical-Design-Engineer_JR0288389", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nPerforms physical design implementation of CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams. Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT. Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU. Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.\n\nQualifications:\nAs a CPU Physical Design Engineer, you will play a pivotal role in implementing high-performance, low-power CPU designs from RTL to GDSII. You will focus on detailed processes such as synthesis, placement, routing, timing analysis, and power optimization, enabling designs that meet stringent performance and efficiency targets. Your work will directly influence the success of Intel's next-generation CPUs and their manufacturing readiness, contributing to innovative advancements in computing technology.\n\nYou will join a dynamic team dedicated to designing Intel's latest high-performance CPUs using cutting-edge technologies. This group focuses on delivering innovative solutions that propel Intel's leadership in the semiconductor industry. Collaborating across multiple domains, the team drives groundbreaking designs that support Intel's mission of creating world-changing technologies to enrich the lives of every person on Earth.\n\nKey Responsibilities\n- Perform physical design implementation from RTL to GDSII, including synthesis, placement, routing, clock tree synthesis, and optimization.\n- Conduct static timing analysis, power distribution analysis, and reliability verification to ensure design convergence and high manufacturability.\n- Collaborate with logic, circuit, architecture, and automation teams to improve CPU microarchitectures and design methodologies.\n- Work closely with industry-leading EDA vendors to enhance tool capabilities for high-speed, low-power CPU development.\n- Optimize designs for power, frequency, and area, ensuring product-level parameter excellence.\n- Participate in developing and improving physical design methodologies and flow automation for future projects.\n\nQualifications\n- B. Tech or M. Tech degree in Electrical, Electronics with 3+ years of relevant experience.\n- Technical expertise in synthesis, placement, clock tree synthesis (CTS), and routing tools, particularly using Synopsys and Cadence platforms.\n- Proficiency in timing signoff, formal verification, and low-power design techniques.\n- Solid understanding of submicron process node technologies and layout verification methods such as LVS/DRC.\n- Skilled in power estimation, power optimization, and power delivery methodologies.\n\nPreferred Qualifications\n- Familiarity with scripting languages like Tcl, Perl, and Python for automating physical design workflows.\n- Experience with Verilog or VHDL for hardware description and design execution.\n- Strong communication skills, both verbal and written, for collaborative problem-solving.\n- Demonstrated ability to work effectively in dynamic environments across geographies.\n- Knowledge of innovative feature feasibility studies and SD flow methodologies.\n\nBe part of a world-class team driving innovation in CPU design. Apply today to contribute to Intel's mission of shaping the future of technology.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "SOC Design Engineer – RTL/Logic", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-22", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/SOC-Design-Engineer---RTL-Logic_JR0288402", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nCome join Intel's highly regarded Devices Development Group, responsible for creating Client SOCs. We envision the future of computing and design for the next generation of laptop and desktop computers.\n\nWe are looking for an SoC (System on Chip) Front-End Design Engineer, ready to research, design, develop, and test lead Intel designs as we reimagine how to build SOCs at Intel and in the semiconductor industry. Our bold purpose as a company is to create world-changing technology that enriches the lives of every person on earth, and this role is instrumental in furthering our mission to shape the future of technology.\n\nYour responsibilities may include, but not be limited to:\nDevelops the logic design, Register Transfer Level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design.\nParticipates in the definition of architecture and microarchitecture features of the block being designed.\nPerforms Quality checks in various logic design aspects ranging from RTL to timing/power convergence.\nApplies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.\nReviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.\nWorks with IP providers to integrate and validate IPs at the SoC level.\nDrives quality assurance compliance for smooth IP-SoC handoff.\n\nThe ideal candidate should exhibit behavioral traits that indicate:\nSelf-motivator with strong problem-solving skills.\nGood leadership capabilities.\nExcellent interpersonal skills, including written, verbal, and presentation communications.\nAttention to detail and organizational skills.\nAbility to work as part of a team and collaborate in a high-paced atmosphere.\n\nQualifications:\nQualifications:\nYou must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.\n\nMinimum Qualifications:\nBS degree in Electrical Engineering, Computer Engineering and 6+ years of experience or MS degree and 4+ years of relevant experience.\nRelevant experience includes a combination of any of the following:\nSilicon design, VLSI design, Microarchitecture definition, RTL development, Verification, Post-silicon testing.\nClient micro-architecture, including power management flows, and memory ordering and coherency.\n\nPreferred Qualifications:\nB.Tech: 7+ years of experience, up to 12 years\nM.Tech: 5+ years of experience, up to 10 years\nexperience in front-end design and/or integration.\nExperience with Python, Perl, or other scripting languages.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "GPU Logic Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-22", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/GPU-Logic-Design-Engineer_JR0288325", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact:\n\nAs a GPU Logic Design Engineer, you will be instrumental in developing the next generation of graphics IPs, contributing directly to the design and optimization of register transfer level (RTL) coding for cutting-edge GPU blocks. Your day-to-day work will involve creating high-performance logic designs, ensuring they meet power, performance, area, and timing goals. The work you do will be integral to delivering innovative solutions for Intel's graphics products, directly impacting millions of users worldwide.\n\nBusiness Group:\n\nThe Graphics IP team within Intel's Data Center Group (DCG) is dedicated to delivering world-class graphics and compute solutions for integrated, discrete, and data center AI products. Leveraging continuous innovation and engineering excellence, the team supports Intel's overall mission to drive technological advancements and deliver high-performance computing solutions. This role places you at the forefront of industry-leading graphics IP development efforts.\n\nKey Responsibilities:\n\nDevelop logic designs and create RTL code for graphics IPs, including compute, display, and media blocks.\nOptimize logic designs to meet power, performance, area, and timing goals, ensuring design integrity for physical implementation.\nParticipate in defining the architecture and microarchitecture features of GPU blocks.\nReview verification plans to ensure design features are accurately validated across hierarchies.\nDrive unit-level verification and resolve RTL test failures, implementing corrective measures to ensure design correctness.\nCollaborate with SoC teams to ensure high-quality integration of GPU blocks.\nUtilize industry-standard tools and methodologies for design and verification.\n\nQualifications:\nMinimum Qualifications:\n\nBachelor's degree or Masters in Computer Engineering, Computer Science, Electrical Engineering, or a related field.\n4+ years M.Tech and 5+ B.tech with hands on experience in RTL coding, logic design, and verification processes for GPU or similar domains.\nProficiency in Verilog/System Verilog and familiarity with hardware design flows and methodologies.\nExperience with synthesis, timing analysis, and structural design using tools such as Lint and CDC.\nKnowledge of computer architecture, microarchitecture, and static timing analysis.\nProficiency in programming/scripting languages such as Python, Perl, or Shell scripting for automation.\n\nPreferred Qualifications:\n\nMaster's degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field.\nStrong analytical skills and experience in low-power design and power optimization techniques.\nFamiliarity with ASIC design flow and industry-standard verification tools/methodologies.\nExposure to ML/AI and HPC workload knowledge.\nEffective team player with strong communication skills and a continuous learning mindset.\n\nJoin a team that thrives on innovation and excellence, where your contributions will shape the future of graphics technology. Apply today and take the next step in advancing your career with Intel.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Signal Integrity Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-22", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Signal-Integrity-Engineer_JR0287938", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nAre you ready to drive innovation in signal integrity solutions for high-speed platforms, boards, and packages? As a Signal Integrity Engineer, you will play a critical role in designing, simulating, and optimizing electrical interconnects, ensuring exceptional performance and reliability in next-generation technologies. Your expertise will shape electrical specifications and industry standards, guiding platform designs and enabling cutting-edge advancements.\n\nBusiness group\nThe Data Center Group (DCG) focuses on delivering innovative technologies that power the world's most advanced data centers. By enabling robust and efficient solutions, DCG supports Intel's mission to drive the digital transformation of industries, empowering businesses and individuals to achieve more. This role contributes to the group's efforts to push the boundaries of platform-level design and performance.\n\nKey Responsibilities\n- Develop and optimize signal integrity solutions for high-speed platforms, boards, and packages, ensuring robust performance across complex interconnects.\n- Perform detailed simulations of electrical structures, guiding physical implementation and design trade-offs to enhance product quality.\n- Design and characterize test structures, leveraging high-speed equipment to correlate simulations with real-world measurements.\n- Define signal integrity rules, document characterization reports, and provide guidelines for end customers as part of platform design documentation.\n- Collaborate with IP design teams and system-on-chip (SoC) integration teams to maximize platform-level solution space and meet targeted requirements.\n- Develop electrical specifications and contribute to the establishment of new industry standards for next-generation interfaces.\n\nQualifications:\nMinimum Qualifications\n- Bachelor's degree in Electrical Engineering, Physics, or a related field and 3+ years of hands-on experience in signal integrity design and analysis OR Master's degree in Electrical Engineering, Physics, or a related field with 2+ years of relevant experience OR PhD in a related field with no prior professional experience.\n- Proficiency in electromagnetic simulation tools (e.g., HFSS, CST, ADS) and expertise in analyzing signal integrity parameters such as jitter, crosstalk, and attenuation.\n- Experience with high-speed measurement equipment, including oscilloscopes, vector network analyzers, and time-domain reflectometers.\n- Familiarity with PCB/Package design tools (e.g., Cadence, Mentor Graphics) and layout optimization strategies.\n\nPreferred Qualifications\n- Strong analytical and problem-solving skills with a demonstrated ability to debug challenges in high-speed signal environments.\n- Excellent communication and collaboration skills, enabling effective teamwork across diverse technical domains.\n- Passion for advancing industry standards and driving innovation in signal integrity design.\n\nTake the first step in joining a team that's redefining what's possible in high-speed technologies. Your contributions will shape the future of data center innovation and make a lasting impact-apply today.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "GPU Logic Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-22", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/GPU-Logic-Design-Engineer_JR0288132", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nGPU Logic Design Engineer:\nDevelop logic design, generate/write Register Transfer Level (RTL) code, and perform simulation for Media IP components. This includes generating essential components such as libraries and functional units and delivering complete IP blocks for full chip design integration. Participate in the definition of architecture and microarchitecture features of the block being designed. Apply various strategies, tools, and methods to generate/write RTL and optimize the logic to meet power, performance, area, timing goals, and design integrity for physical implementation. Review the verification plan and the implementation to ensure design features are correctly verified across verification hierarchies. Drive unit level verification and implement corrective measures for failing RTL tests to ensure feature correctness. Supports SoC customers to ensure high-quality integration of Media IP block. Your contributions will directly impact Intel's ability to deliver innovative graphics technologies to our customers, helping shape the future of computing\n\nBusiness group: Intel's Media HW Engineering team\n\nKey Responsibilities\n•\tConduct feature feasibility studies, performance analysis, and microarchitecture design based on landing zone requirements\n•\tDesign a wide variety of digital logic functions with the emphasis on media encoder/decoder design\n•\tDevelop, implement, and validate Register Transfer Level (RTL) design\n•\tPerform power, performance, area, and timing optimization to meet design goals\n•\tDeveloping C or Perl behavioral models to support RTL functionality verification\n•\tUtilize AI models to enhance specification development, RTL code generation, and verification collateral creation\n\nQualifications:\nEducation and Experience\n•\tBachelor's degree in Computer Engineering, Electrical Engineering, or a related field with 5+ years of industry experience in RTL design and logic development with expertise in System Verilog.\nOR\n•\tMaster's degree in Computer Engineering, Electrical Engineering, or a related field with 3+ years of industry experience in RTL design and logic development with expertise in System Verilog.\n\nRequired skills and experience\n•\tComputer system architecture\n•\tDigital electronics and logic design\n•\tVerilog or System Verilog\n•\tLogic verification, synthesis, and timing analysis tools\n•\tC, Perl, and Python programming\n•\tAI-assisted ASIC Design and Verification tools.\n\nPreferred skills and experience\n•\tKnowledge of video codec standards such as H.264, HEVC, VP8/9, AV1, VVC, and other popular codecs\n•\tAdvanced knowledge of microarchitecture fundamentals and logic design verification methodologies.\n•\tStrong communication, collaboration, and problem-solving skills\n•\tSelf-motivated and self-directed, with the ability to work effectively both independently and as part of a team\n•\tProven ability to effectively debug microarchitecture and hardware simulations.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Manufacturing Engineer - Master Layout", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2026-10-22", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/Manufacturing-Engineer---Master-Layout_R2626879", "is_hardware": true, "platform": "workday", "jd_text": "Who We Are\n\nApplied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI and accelerating the commercialization of next-generation semiconductor chips. Join us and push the boundaries of materials science and engineering in a company at the foundation of the electronics industry. The work we do together advances the world’s technology.\n\nWhat We Offer\n\nLocation:\nBangalore,IND\nYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. \n\nAt Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. \n \n \nAs a Manufacturing Engineer, you are responsible for developing and maintaining methods, operating sequences, and processes in the fabrication of parts, components, subassemblies, and final assemblies. You'll work closely with other engineering functions to coordinate the release of product improvements and new products, and you'll use engineering principles to estimate and reduce manufacturing costs, improve product quality, determine time standards, and make recommendations for tooling and process requirements. Your expertise in lean principles, automation, and continuous improvement will be instrumental in driving operational excellence and achieving higher levels of productivity and cost-effectiveness. You'll develop and use test procedures, evaluate test results, and assess work methods, procedures, and policies to identify root cause issues and solutions that ensure operational success. \n \nRole Summary\nThe Manufacturing Engineering will provide technical and operational support to Design Engineering and Manufacturing Engineering teams across the semiconductor equipment product lifecycle. The role is responsible for improving product readiness, maintaining an accurate digital product definition, validating product structures and manufacturing requirements, and resolving design-to-manufacturing issues before product build.\n\nKey Responsibilities\nDesign and Manufacturing Engineering Support\nProvide day-to-day engineering support to Design and Manufacturing Engineering teams for new product introduction, product upgrades, prototype builds, pilot builds, production ramp, and sustaining activities.\nReview product designs for manufacturability, assembly, installation, accessibility, maintainability, and serviceability.\nIdentify and communicate design risks, assembly constraints, tolerance concerns, clearance issues, hardware incompatibilities, and manufacturing readiness gaps.\nSupport build issue resolution by coordinating containment, root-cause analysis, corrective actions, and design or process updates with relevant stakeholders.\nTrack engineering and manufacturing issues through closure and capture lessons learned for reuse in future designs.\n\nMaster Layout and Digital Product Model Management\nCreate, maintain, and validate Master Layouts at module and system levels for multiple product configurations.\nDevelop and maintain accurate 3D virtual product models aligned with the released physical product configuration.\nIncorporate approved design changes into product models and ensure configuration consistency across affected assemblies.\nCreate and manage parts, kits, subassemblies, and top-level assemblies in Siemens NX and Teamcenter Engineering.\nApply Master Layout, assembly, modelling, drafting, and Model-Based Definition standards.\nSupport product-option architecture, options and variants logic, effectivity, and product configuration in Teamcenter.\nReview electrical and mechanical schematics and translate routing requirements into NX assemblies.\nCreate and validate mechanical, cable, and harness assembly routing within the product model.\nCheck routing for length, bend radius, accessibility, connector interfaces, service loops, clamp locations, interference, and assembly feasibility.\nCoordinate with Design Engineering, Electrical Engineering, Manufacturing Engineering, and assembly teams to resolve routing-related issues.\nSupport E3S drawing reviews and ensure routing deliverables meet applicable engineering and manufacturing standards.\nCreate, revise, and release parts, assemblies, kits, drawings, and product structures through the approved Engineering Change Management process.\nEvaluate change impact across product models, BOMs, manufacturing documentation, options, variants, and affected configurations.\nSupport release-readiness reviews and verify that required engineering deliverables are complete, consistent, and available to downstream users.\n\nRequired Technical Skills\nProficiency in Siemens NX, including solid modelling, sheet-metal design, assemblies, drafting, routing, and Model-Based Definition.\nProficiency in Teamcenter Engineering and Teamcenter Visualization for product data, structure, configuration, workflow, and release management.\nStrong understanding of Master Layout methodology and management of complex module- and system-level assemblies.\nKnowledge of Design for Manufacturing, Design for Assembly, Design for Serviceability, tolerance analysis, fit and clearance validation, and assembly-sequence assessment.\nAbility to interpret mechanical drawings, electrical schematics, cable and harness drawings, specifications, and engineering standards.\nExperience with Engineering Change Management and product lifecycle release processes.\nAwareness of SAP, iOMS, ERP, MES, and digital-thread integration.\nStrong analytical, troubleshooting, root-cause analysis, and structured problem-solving skills.\n\nBehavioral and Collaboration Skills\nClear written and verbal communication with technical and non-technical stakeholders.\nAbility to work effectively with Design Engineering, Manufacturing Engineering, Electrical Engineering, NPME, Quality, Supply Chain, Operations, and Service teams.\nStrong ownership, attention to detail, prioritization, and follow-through.\nAbility to manage multiple priorities in a fast-paced product-development and manufacturing environment.\nContinuous-improvement mindset with a focus on issue prevention, product quality, cycle-time reduction, and manufacturing readiness.\n\nEducation and Experience\nBachelor’s degree in mechanical engineering, Manufacturing Engineering, Mechatronics, or a related engineering discipline.\nTypically 10–15 years of relevant experience supporting semiconductor equipment, complex electromechanical products, capital equipment, or high-technology manufacturing.\nDemonstrated experience supporting Design and Manufacturing Engineering teams through design release, build, issue resolution, and product change implementation.\nExperience in semiconductor equipment product development or manufacturing is preferred.\n \n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nAssignee / Regular\nTravel:\nYes, 10% of the Time\nRelocation Eligible:\nYes\n\nApplied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "SoC Verification Senior Lead Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-10-22", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/SoC-Verification-Senior-Lead-Engineer_R-10067187", "is_hardware": true, "platform": "workday", "jd_text": "Role Overview:\nWe are seeking an experienced Verification Engineer with 12+ years of experience for execution of SoC verification of complex SoCs. The ideal candidate will have deep knowledge of ARM-based microcontrollers, low-power design verification, and experience with multiple interfaces and security IPs. This is a hands-on role requiring strong technical skills and collaboration in a fast-paced environment.\n\nKey Responsibilities:\nDevelop and own SoC-level and/or IP-level verification suites with coverage goals.\nResponsible for executing verification plan according to the product specification and verification requirements defined by product architects.\nResponsible for developing, debugging and running UVM based verification environment for RTL/netlist simulation.\nDefine and develop test cases in an appropriate verification framework. Create stimulus and assertions, run simulation, debug test cases on the design models (RTL, power aware RTL, gate level, FPGA, Emulation platform), run regression, collect and analyze code/functional coverage\nDrive DV closure on diverse IPs and subsystems, ensuring maximum coverage and quality.\nGood understanding of formal verification techniques and methodologies.\nFamiliar with both SoC-level and IP-level verification environments.\nCollaborate with the team in developing and improving flows for maximum reuse and efficiency.\nMentor junior team members while actively collaborating with design teams for issue resolution and sign-off.\n\nRequired Qualifications:\nExperience: 12-15 years in SoC/IP verification with participation in successful tape-outs of SoCs.\nTechnical Skills: Strong expertise in ARM-based microcontrollers and SoC-level verification, including C based DV.\nProficiency in Verilog, SystemVerilog, UVM, and constrained-random verification.\nFamiliarity with EDA tools (Synopsys VCS, Cadence Xcelium).\nExperience with low-power verification (UPF) is a must.\nGate-level simulations and power-aware simulations is a must.\nGood working knowledge of assertions (SVA) and functional coverage.\nVerification of multiple interfaces: SPI, I²C, UART, CAN, eSPI is desirable.\nKnowledge of Flash memory and security IPs is nice to have.\nAny experience with common Analog IPs in microcontroller design (ADC, DAC, PLLs) is an added advantage.\n\nSoft Skills: Comfortable working in a fast-paced environment.\nStrong team player with excellent communication skills.\n\nEducation: Bachelors or Master’s in Microelectronics, Electronics, Electrical Engineering\n\nMore information about NXP in India...\n\n#LI-29f4", "jd_status": "stored"}, {"title": "SoC Verification Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-10-22", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/SoC-Verification-Engineer_R-10067209", "is_hardware": true, "platform": "workday", "jd_text": "NXP is seeking highly qualified candidates to join SOC Verification team.\nIn this role, you will be responsible for functional Verification of NXP SOCs and Sub-Systems using state of the art technology and methodologies, should be able to work independently and drive to closure of assigned tasks. You will be engaged with the design, Architecture, IP providers, FW/SW, DFT and backend teams to collaborate and execute to ensure First time right silicon.\n\nExpectations include:\nUnderstand the product requirements and Develop Verification plans to meet the Specification.\nDevelopment of Pre-Silicon Verification environment.\nRigorously executing Verification Plans to ensure Right First Time Success of our Products.\nDevelopment of Subsystem/SoC Verification and Coverage plans.\nDemonstrate excellent Self–motivation, communication, strong problem solving and teamwork skills.\nFlexible enough to work in a dynamic environment and multitask seamlessly.\nAbility to work well as part of a team both locally, and with remote or multi-site teams\n \nKey Skills\n4+ years of experience on SOC/Chip level/Cluster/Sub-System Verification\nExperience in Microcontroller and Microprocessor architecture, ARM Cores A/M/R series, Interconnect (NIC, FlexNoC), Cache Coherency.\nExperience in protocols like AHB/AMBA, AXI, ACE, OCP, Memory (Flash, SRAM, ROM) and memory controllers\nExperience in serial protocols like UART, SPI, I2C, CAN, Multimedia/Networking protocols like MIPI CSI2.\nGood knowledge of ARM debug subsystem and SWD, JTAG protocols.\nExperience with System Verilog/UVM for IP/Subsystem and SOC development environment.\nVerification using formal methods will be an added advantage.\nAssembly and C programming skills are mandatory\nScripting and Automation (BASH, Python) to continuously improve operational efficiency\n \nJob Qualifications\nBSEE / MSEE with 4+ years’ experience in Semiconductor industry. \n\nMore information about NXP in India...\n\n#LI-29f4", "jd_status": "stored"}, {"title": "SoC Verification Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-10-22", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/SoC-Verification-Engineer_R-10067210", "is_hardware": true, "platform": "workday", "jd_text": "NXP is seeking highly qualified candidates to join SOC Verification team.\nIn this role, you will be responsible for functional Verification of NXP SOCs and Sub-Systems using state of the art technology and methodologies, should be able to work independently and drive to closure of assigned tasks. You will be engaged with the design, Architecture, IP providers, FW/SW, DFT and backend teams to collaborate and execute to ensure First time right silicon.\nExpectations include:\nUnderstand the product requirements and Develop Verification plans to meet the Specification.\nDevelopment of Pre-Silicon Verification environment.\nRigorously executing Verification Plans to ensure Right First Time Success of our Products.\nDevelopment of Subsystem/SoC Verification and Coverage plans.\nDemonstrate excellent Self–motivation, communication, strong problem solving and teamwork skills.\nFlexible enough to work in a dynamic environment and multitask seamlessly.\nAbility to work well as part of a team both locally, and with remote or multi-site teams\n \nKey Skills\n4+ years of experience on SOC/Chip level/Cluster/Sub-System Verification\nExperience in Microcontroller and Microprocessor architecture, ARM Cores A/M/R series, Interconnect (NIC, FlexNoC), Cache Coherency.\nExperience in protocols like AHB/AMBA, AXI, ACE, OCP, Memory (Flash, SRAM, ROM) and memory controllers\nExperience in serial protocols like UART, SPI, I2C, CAN, Multimedia/Networking protocols like MIPI CSI2.\nGood knowledge of ARM debug subsystem and SWD, JTAG protocols.\nExperience with System Verilog/UVM for IP/Subsystem and SOC development environment.\nVerification using formal methods will be an added advantage.\nAssembly and C programming skills are mandatory\nScripting and Automation (BASH, Python) to continuously improve operational efficiency\n \nJob Qualifications\nBSEE / MSEE with 4+ years’ experience in Semiconductor industry. \n \n\nMore information about NXP in India...\n\n#LI-29f4", "jd_status": "stored"}, {"title": "NFC FW Architect", "company": "NXP", "location": "Bangalore", "date_posted": "2026-10-22", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/NFC-FW-Architect_R-10064282-1", "is_hardware": true, "platform": "workday", "jd_text": "NFC‑based platforms are at the heart of secure connected experiences across mobile, wearables, automotive, and IoT ecosystems. They span domains such as secure NFC transactions, digital wallets, infrastructure services, platform enablement, and low-level silicon integration. As a Firmware Architect in the NFC Firmware organization, you will contribute to defining and delivering robust firmware architectures that operate close to silicon and enable reliable product execution across multiple NFC use cases.\nThis role focuses on platform firmware architecture and execution for PCRM, low-level platform software, tapeout readiness, and post-silicon bring-up, while collaborating across hardware, systems, validation, and firmware development teams.\nWe are looking for a hands-on firmware technologist with strong embedded/firmware roots, good understanding of real-time systems and SoC platforms, and practical experience translating system and hardware requirements into clean, scalable firmware designs.\n\nYour Responsibilities:\nShe/He shall work as an NFC Firmware Architect and contribute to new product development, debugging, bring-up, and maintenance of NXP's embedded firmware for NFC products.\nDefine and support firmware architecture for RISC-V/ARM platform.\nDerive firmware requirements from system, hardware, PCRM, and customer specifications.\nDesign firmware sub-systems and low-level software components to meet functional, performance, memory, timing, and power requirements.\nReview design and code contributions, provide technical guidance, and help maintain quality of firmware deliverables.\nOwn one or more firmware modules or platform software sub-systems from design through integration and bring-up.\nDefine and write firmware design specifications, interface specifications, and low-level platform software documentation.\nSupport definition of validation and bring-up environments for pre-silicon, emulation, FPGA, and post-silicon phases.\nContribute to firmware test strategy at unit, integration, system, and silicon bring-up levels.\nSupport tapeout readiness activities by reviewing firmware dependencies, register/interface assumptions, boot flows, and hardware-software integration risks.\nClosely interact with hardware development teams, system architects, validation teams, and component technical experts to resolve low-level integration issues.\nCollaborate effectively with partner teams and ensure firmware architecture considers product, platform, and silicon constraints.\nDefine firmware design guidelines, development flows, debug approaches, and bring-up checklists for platform software.\n\nYour Profile:\nMandatory:8-12 years of embedded firmware development experience, preferably in SoC, mobile, secure embedded, or RTOS-based embedded systems.\nBachelor’s or Master’s Degree in Electronics & Communication, Power Electronics from reputed institute with strong academic records.\nEmbedded software design and development on 8/16/32-bit platforms, preferably RISC-V and ARM architectures.\nExcellent C programming skills, exposure to assembly with hands-on development experience.\nMust have experience in low-level firmware programming, including boot flows, boot loaders, interrupt handling, memory maps, clocks, power states, SPI/I2C/UART drivers, RF interfaces, and embedded RTOS concepts.\nHands-on knowledge of RTOS, its concepts and usage.\nGood knowledge of SoC hardware IP datasheets, register-level programming, hardware-software interfaces, and low-level driver development.\nHands-on exposure to PCRM topics, platform configuration, reset/clock/power management, and low-level initialization flows.\nExperience supporting tapeout and bring-up activities, including pre-silicon validation on RTL, FPGA/emulation usage, post-silicon debug, and issue triage with hardware teams.\nExposure to IDEs like LPCXpresso, Keil, Eclipse\nExperience in using Debuggers. (TRAC32/J-LINK/LPC-LINK)\nExposure to change management / configuration management, bug tracking tools.\nHands-on with AI based efficiency gaining tools.\n\nOptionalExposure to C++ / C#, Perl/Python is an added advantage\nGood understanding of NFC technology.\n\nPersonalityExcellent analytical, problem solving, debugging skills & influencing skills with go-to attitude\nSelf-motivated, proactive, good verbal and written communication.\nSufficiently mobile and flexible, work location based out of Bangalore\nExperienced in requirements derivation, low-level design, high-level design, and hands-on implementation in platform firmware domains.\nEmpathic communicator, able to see things from the other person's point of view and a good team player with cross functional, cross cultural & Global teams\n\nDesired Skill Set\nKnowledge of software development life cycle (SDLC) for embedded firmware development\nKnowledge of embedded platforms, low-level platform software, and close collaboration with hardware teams is preferred.\nUnderstanding of tapeout milestones, silicon bring-up planning, debug instrumentation, and hardware-software readiness criteria.\nKnow-how of smart card Contact less Proximity Standards such as ISO14443, ISO15693, ISO18092, ISO7816 etc.\nNear Field Communication Standards.\nWilling to travel to other countries on need basis\n\nMore information about NXP in India...\n\n#LI-29f4", "jd_status": "stored"}, {"title": "Staff STA Engineer", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-10-22", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Staff-STA-Engineer_R266776-1", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nJob Description\nJob Description\nStaff Synthesis & STA Engineer\n\nAbout the Role\n \nAs a Staff Synthesis & STA Engineer, you will own lead & own Synthesis & STA for complex high performance ICs with large digital & analog interfaces.\n \nYou'll influence implementation, guide methodology improvements, and lead small technical teams. This position requires deep expertise across multiple technical domains and strong cross-functional collaboration skills to drive innovation and excellence in digital design.\n\nKey Responsibilities\nDigital Synthesis of high performance Digital blocks\nTiming constraint development, analysis, validation and debug \nRTL to Netlist Logical equivalence check and debugging failures\nSTA flow setup, convergence, reviews, flow optimization\nTiming, Noise, DRC (transition, capacitance) signoff for multi-mode, multi-corner\nFlow automation using TCL/Perl/Python\nSupporting Floor-planning, Placement, CTS, Routing, Extraction, Physical Verification, EM/IR flows, Signoff checks\n\nMust Have Skills\nHands on experience in Digital Synthesis, DFT insertion, Check Design and Check Timing Analysis\nGood understanding of all aspects of liberty models including power\nAbility to develop complex timing constraints by working with designers is a must. Should have experience in IP/subsystem/full-chip timing constraints\nKnowledge of commands and constructs supported across synthesis, STA , LEC and PD tools\nAnalysis skills to root cause of timing violations issues and suggest solutions across various stages of design Implementation\nHands on experience with the STA and Signoff of complex high speed SoC designs in cutting edge process technologies (16nm and below).\nStrong expertise in Timing ECOs driven by tool and manual ECO techniques for timing closure\nSound understanding of Scan/DFT modes and timing\nMust have worked on Leakage and Dynamic power optimization of logic as part of Synthesis\nMust have worked on Synthesis/STA of 4+ successful tapeouts at lower geometries\nFamiliar with digital flow design aspects RTL to GDS\nProficiency in tcl/perl/python scripts and automation on timing analysis tools\nFlow enhancements to resolve timing and/or timing-DRC issues\nHands on experience in Floor-planning, Placement, CTS, Routing using physical design tools, Extraction, Physical Verification, EM/IR flows, Signoff checks is desirable\nGood communication skills in cross-collaborative environment\n\nPreferred Education and Experience\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering.\n6-12 years of relevant experience.\n\nWhy You'll Love Working Here\nAt Analog Devices, you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on professional growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world.\n\nYour expertise will shape the future of technology, and you’ll be supported by a culture that values continuous advancement and professional growth. Join us and help create the technologies that bridge the physical and digital worlds, making a tangible difference in how people live, work, and connect.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Principal Digital Design Engineer", "company": "Analog Devices", "location": "India, Bangalore, Nova", "date_posted": "2026-10-22", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-Nova/Principal-Digital-Design-Engineer_R267194", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nDescription:\nThe Digital IP team within Analog Devices Inc. is responsible for developing, curating, and providing reusable strategic IPs to Business Units to accelerate product development across the company. The team is looking for an experienced Digital Design Lead who will be responsible for providing technical leadership to the digital design team, while managing IP development and delivery.\nThe ideal candidate would be someone with strong technical background combined with management acumen and demonstrable ability to handle ambiguity while still finding creative ways to make things happen.\nA key focus area for this position includes interacting and engaging with internal customers to communicate, identify, improve, and maintain developed IP, as well as scout for 3rd party IPs and evaluate them on a regular basis for future requirements.\nJob Responsibilities:\nProvide technical leadership and expertise to a team of design engineers on all aspects of digital design & quality assurance (CDC, Low Power design, Synthesis & timing closure, Design for Test improvements, silicon debug etc)\nArchitect and Design key digital blocks such as accelerators/ data path IP in Verilog/ System Verilog with built-in configurability to allow Power/ Performance/ Area tradeoffs\nDemonstrate strong understanding of heterogenous processor cores & subsystems (A55/ M55/ M4/ U55/ RISC-V/ DSP core, and associated infrastructure such as caches, interconnect fabric, GIC, DMA, MMU, Coresight Debug & Trace, TZC, SMPU, SPU) and their integration requirements\nWork closely with all stakeholders, including product teams, project managers, senior managers & leadership team to align team schedules, milestones, commitments, deliverables\nConduct detail-oriented design reviews and drive adherence to quality metrics\nCreate and manage a streamlined workflow for the design team that enables them to work collaboratively and efficiently. This includes creating a project visibility system and setting up design review processes to establish a clear scheme of design delivery\nDrive efforts towards development of Design Management and IP Centric infrastructure and flows across different tools such as Methodics / Perforce / Github / IP catalog creation etc\nDevelop and maintain catalog of digital IPs to enable ease of information sharing to customers across different BUs\nLead the way to build deep expertise on complex interfaces, peripherals & protocols such as DDR, Ethernet, eMMC/ SD, MIPI, Display Port, HDMI, PCIe, high speed D2D\nPackage Digital IP for seamless integration into design flow at different stages – RTL/ constraints/ CDC waivers, timing wavers, DFT DRCs and waivers, software programming sequence etc.\nDrive evaluation of 3rd party IPs on Power/ Performance/ Area (PPA) and other key qualitative aspects such as design quality, Design For Testability, robustness of Design Verification (DV) practice, ease of integration and make recommendations\nEstablish evaluation flows for home-grown & 3rd party IPs for consistent benchmarking of evaluation\nManage & streamline efforts towards consolidation/ curation of digital IP blocks, such as standard peripherals, processor cores & collaterals, high speed protocol & interface IP\nStrive to remove complexity and ambiguity within the teams and their processes. Ability to distil and provide clear and actionable recommendations to the team\nPosition Requirements:\nMinimum B.E. /B. Tech degree in Electrical/Electronics/Computer science\n15+ years of relevant experience with a strong focus on definition/ architecture/ u-arch/ design and hands-on RTL coding experience using Verilog and System-Verilog\nStrong understanding of all aspects of ASIC/SoC product development incl Design Verification/ timing constraints/ closure, physical implementation, quality assurance flows with hands-on prior experience in a few of these aspects\nProven experience in managing/ handling large complex hardware projects in lead role\nStrong understanding of control path and data-path digital design concepts with an eye for realizing correct by construction solutions\nExperience with specifying Design Verification (DV) requirements such as test plans, coverage metrics, and evaluate DV quality so as to realize robust design quality\nStrong knowledge of Lint, CDC, formal equivalence, DFT concepts, power analysis, low power design\nExperience with developing timing constraints and ability to carry out logic synthesis and Static timing analysis\nAbility to technically mentor a large digital design team\nGood interpersonal, teamwork and communication skills to drive discussions logically & effectively with teams spread geographically\nStrong understanding of standard on-chip interfaces such as APB/AHB/AXI/ Stream protocols\nKnowledge of Processor/SoC architecture and/or DSP fundamentals\nServe as the focal point for communications. Compile regular status updates for all stakeholders and effectively escalate critical issues and risks as necessary\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Analog Design Senior Manager - SerDes", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-22", "url": "https://careers.synopsys.com/job/bengaluru/analog-design-senior-manager-serdes/44408/102293775152", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nYou have spent over a decade building high-speed SerDes circuits that actually ship in products, not just pass simulations. The difference between a VCO that locks cleanly across PVT and one that drifts at the edge of spec is something you see coming three design reviews earlier, and you are the kind of engineer who catches it before it becomes a silicon problem. You think in both transistor-level trade-offs and team-level execution. When a junior designer brings you a sampler topology, you can spot the bandwidth bottleneck in two minutes and sketch three alternatives that might work better, then help them choose the right one for this particular standard and this particular process node.\nManaging a team does not mean you stop designing. You still get into the schematics when a critical path needs attention, but you also know when to step back and let your team solve it. You care about building engineers, not just circuits. At Synopsys, you will lead a team developing multi-Gbps SerDes IP in advanced FinFET and GAA nodes, and the work you guide will power connectivity in systems that matter.\n\nWhat You'll Be Doing\nLead a team of analog designers developing multi-Gbps NRZ and PAM4 SerDes IP from standards analysis through silicon bring-up\nConduct technical design reviews for critical SerDes sub-circuits including equalizers, samplers, voltage and current-mode drivers, serializers, deserializers, VCOs, phase mixers, DLLs, PLLs, bandgap references, ADCs, and DACs\nTranslate SerDes standards and system requirements into block-level specifications and circuit architectures that your team can execute against\nReview simulation results, electrical characterization data, and post-silicon debug findings, then recommend design updates or corrective actions\nBuild project schedules and action plans that keep complex analog IP development on track across multiple process nodes\nDevelop and mentor your team through hiring, technical coaching, design reviews, and career growth conversations\nWork cross-functionally with digital designers, verification engineers, layout teams, and CAD to resolve mixed-signal integration and timing challenges\n\nThe Impact You Will Have\nDeliver high-speed SerDes IP that enables PCIe and Ethernet connectivity in customer products across a range of industries\nDefine circuit architectures and design strategies that set the technical direction for your team and influence IP roadmap decisions\nImprove design quality and reduce post-silicon risk by catching issues early through structured reviews and hands-on technical guidance\nBuild a stronger analog design team by hiring well, coaching effectively, and creating an environment where engineers grow their skills\nAccelerate time to market by maintaining clear schedules, removing blockers, and keeping cross-functional teams aligned\nInfluence process node readiness and design-for-reliability practices through your team's work in advanced FinFET and GAA technologies\nShape the technical standards and documentation that define how SerDes IP is designed, tested, and delivered at Synopsys\n\nWhat You'll Need\nBachelor's or Master's in Electronics Engineering or related field\n14+ years of hands-on analog design experience focused on high-speed SerDes applications\n1 to 2 years in a management or supervisory role leading analog design teams\nDeep transistor-level circuit design expertise with strong CMOS fundamentals and experience across a wide range of SerDes sub-circuits including receive equalizers, samplers, drivers, serializers, deserializers, VCOs, phase mixers, DLLs, PLLs, bandgap references, ADCs, and DACs\nProven ability to design IP for high-speed connectivity standards such as PCIe and Ethernet\nSolid understanding of mixed-signal design challenges including analog-digital interface timing, ESD circuit techniques and layout, custom digital design for high-speed logic paths, and layout effects like matching, reliability, and proximity\nExperience with design-for-reliability considerations including electromigration, IR drop, and aging effects\n\nWho You Are\nYou stay technically hands-on even in a management role. You can still open a schematic, debug a phase noise issue, or review a layout for matching and reliability concerns without losing a step.\nYou know how to assess complex analog work quickly. When a designer brings you a PLL architecture or a driver topology, you can identify the risk areas and suggest a better path forward in one conversation.\nYou build schedules that reflect reality, not wishful thinking. You understand what takes three weeks versus three days in analog design, and you plan accordingly.\nYou communicate clearly with people who do not live in your domain. You can explain a jitter budget to a digital architect or a post-silicon issue to a program manager without losing the technical thread.\nYou care about growing your team. You give feedback that helps people get better, you create space for engineers to take on stretch work, and you hire people who will raise the bar.\nYou push back when something does not make sense. If a spec is unrealistic or a timeline ignores a known process limitation, you say so and propose an alternative.\n\nThe Team You'll Be Part Of\nYou will join a team focused on high-speed SerDes IP and transistor-level analog and mixed-signal design. The work supports high-speed connectivity applications including PCIe and Ethernet. Your recruiter will share more about team size, reporting structure, and specific product roadmap responsibilities during the interview process.\n\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Test Engineer (HVP-DBB)", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-10-22", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018199", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n This is a unique opportunity to be part of a team that drives testing of highly integrated multi-rail power management devices going into markets with significant growth potential. The ideal candidate would have a background that includes probe and final test development of complex mixed signal circuits.\n\nResponsibilities include:\n\nWork with design team to understand design specifications\n\nGenerate test plan, create test and char program, design ATE hardware interface boards\n\nDebug characterizing silicon on ATE, correlate results with bench data\n\nAnalyze silicon results, supporting failure analysis tasks\n\nPerform statistical analysis of yield fallout, debug and fix yield issues; optimize test time\n\nWork with production team to release products to volume production\n\nTest strategy definition and implementation for new DCDC converter products\n\nATE (Automatic Test Equipment) test hardware and software\n\nSilicon qualification& characterization including qual hardware development\n\nComprehensive device debugging, design validation and failure analysis\n\nDrive for robust and cost effective test solutions while being accountable for product quality\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in Electrical Engineering\n\n3 years of relevant experience\n\nATE experience on Advantest 93k or Teradyne Eagle or equivalent analog ATE (iFlex, LTX, VLCT), although Advantest experience is preferred and is a differentiator\n\nCharacterization test program and hardware development experience, Production test program and hardware development experience\n\nStrong technical knowledge of electronic devices and circuits, and Analog test techniques. Some experience with power products like DC-DC converters and Gate Drivers is a plus\n\nData analysis skills using Spotfire, dataPower or equivalent tool based on STDF\n\nExperienced with various lab equipment such as scopes, power supplies, sourcemeters, loads etc.\n\nExperience with product engineering activities such as yield improvement and test time reduction\n\nStrong understanding of the IC product development process, from concept to volume production\n\nPreferred qualifications:\n\nMixed signal test techniques and experience with developing mixed-signal tests on TI roadmap testers\n\nExperienced with test program and hardware offload to TI offshore manufacturing sites\n\nProficiency in programming/scripting in C++, Python\n\nRevision control tools experience : Subversion, Git\n\nDemonstrated strong analytical and problem solving skills\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nStrong time management skills that enable on-time project delivery\n\nDemonstrated ability to build strong, influential relationships\n\nAbility to work effectively in a fast-paced and rapidly changing environment\n\nAbility to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Test Engineering Lead", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-10-22", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009922", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n The Test Engineering Lead manages the planning, development, and implementation of procedures for the testing and evaluation of standard and special devices. In this role, you are expected to lead TE activities for the program including managing interactions and alignments with the cross functional teams. Test Lead specifies tests to be performed, compiles data, and makes recommendations for changes required in testing equipment procedures, manufacturing processes, new testing requirements and/or design of testing equipment. You will also recommend the purchase of test equipment and select, develop and evaluate personnel to ensure the efficient operation of the function.\n\nResponsibilities include:\n\nDevelop and drive innovation in test to drive test cost to entitlement\n\nOptimize production test programs, including test time reduction activities, and yield Improvement\n\nDevelop and drive TI technology for Design for Test (DFT), design verification, failure analysis and qualification of products\n\nTranslate defect driven test suites to production test solutions that also validate spec performance\n\nCreate and implement highly optimized tester agnostic& design centric test methods\n\nAnalyze test data to thoroughly understand and resolve problems\n\nPresent analysis and conclusions to internal customer teams in a comprehensive and effective manner\n\nLead TE activities for the entire program including managing interactions and alignments with the cross functional teams\n\nLead, coach, and train a team of product/test engineers to a higher level of performance and ability\n\nQualifications\nMinimum requirements:\n\nBachelors in Electrical Engineering\n\n8-15 years of relevant experience\n\nProven history of technical accomplishment, leadership, planning, coordinating, executing on multiple projects simultaneously for all silicon verification, characterization, qualification, capacity and test cost reduction activities\n\nGreat breadth of test platform and test technologies\n\nAdvanced level of understanding and use of Advantest and Teradyne/Eagle ATE\n\nProbe Burn-In stress application & testing methods experience\n\nPreferred qualifications:\n\nArchitectural model level understanding and familiarity with digital designs in TI (Verilog and VHDL designs\n\nTrack record of innovation in the test methods resulting in elimination of Burn-In\n\nWillingness to learn new things even when it might not directly be related to the job role/responsibility\n\nExperience working with demanding customers with the highest standards in quality and reliability\n\nDemonstrated leadership skills with confidant and charismatic personality\n\nDemonstrated strong analytical, critical thinking and problem solving skills\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nStrong time management skills that enable on-time project delivery\n\nDemonstrated ability to build strong, influential relationships\n\nAbility to work effectively in a fast-paced and rapidly changing environment\n\nAbility to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Lead Physical Design Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-21T11:21:00+00:00", "url": "https://global-external-amd.icims.com/jobs/93022/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. Physical Design Engineer :EMIR / PDN Domain: ASIC / SoC Physical Design, EMIR THE ROLE: We are looking for an adaptive, self-motivated Senior Silicon Design Engineer with strong experience in Electromigration and IR Drop (EMIR) analysis to join our growing team. As a key contributor, you will be responsible for driving EMIR analysis, debug, and signoff closure for complex, high-performance SoC designs using industry-standard tools such as Ansys RedHawk-SC and Cadence Voltus. You will collaborate closely with Physical Design, Power, Package, and other cross-functional teams to identify power integrity risks, perform root-cause analysis, recommend design improvements, and drive issues to closure. You will also contribute to improving EMIR methodologies, automation, flow efficiency, and overall design quality to enable robust and reliable silicon. THE PERSON: You have a passion for silicon design, physical design, and solving complex EMIR challenges. You possess a strong understanding of power delivery networks and the interaction between floorplan, power grid, placement, routing, bumps, power distribution, and design activity. You are a team player with excellent communication and collaboration skills and are comfortable working with engineers across different teams, sites, and time zones. You have strong analytical and problem-solving skills, with the ability to independently debug complex EMIR issues, identify root causes, propose practical design solutions, and drive issues to closure. You are self-motivated, willing to learn, and continuously look for opportunities to improve methodologies, automation, debug efficiency, and overall design convergence. KEY RESPONSIBILITIES: Perform static and dynamic IR-drop and Electromigration analysis using industry-standard EMIR tools such as Ansys RedHawk-SC and Cadence Voltus for complex SoC designs. Develop, maintain, and validate EMIR flows and analysis setups across different stages of the physical design cycle. Perform power-grid validation and identify weak-grid regions, voltage-drop hotspots, current-density violations, and power connectivity issues. Validate EMIR database quality and input data integrity, and identify setup or data-related issues that could impact the accuracy and quality of EMIR analysis. Perform detailed root-cause analysis of EMIR violations and provide actionable recommendations to Physical Design and other related teams. Work closely with Physical Design teams to drive power-grid optimization, via enhancement, metal strengthening, floorplan updates, placement optimization, and ECO-based fixes. Analyze EMIR challenges associated with voltage islands, multiple power domains, power-domain boundaries, bump distribution, and power-grid connectivity. Identify critical issues early in the design cycle that may require floorplan, bump, or power-grid architecture changes. Analyze results across multiple design iterations to identify new violations, regressions, and unexpected changes, and drive them toward resolution. Work closely with design teams to determine whether identified EMIR issues can be addressed through ECO changes or require more significant power-grid/design modifications. Drive assigned blocks/subsystems toward EMIR signoff and design convergence, while meeting project quality and schedule requirements. Develop and improve automation for EMIR flow execution, data processing, analysis, debug, and reporting. Collaborate effectively with cross-functional teams and provide technical guidance and support on EMIR related issues. Contribute to continuous improvement of EMIR methodologies, checks, best practices, and design closure processes. PREFERRED EXPERIENCE: 7 +Years of hands-on experience in ASIC/SoC Physical Design with significant experience in EMIR analysis and signoff. Strong hands-on experience with Ansys RedHawk-SC and/or Cadence Voltus for Electromigration and IR-drop analysis. Experience with both tools is highly preferred. Strong understanding of Power Delivery Networks (PDN), static IR drop, dynamic IR drop, Electromigration, current density, and power-grid reliability. Experience with EMIR flow setup, database validation, debug, analysis, and signoff closure. Strong understanding of the impact of floorplan, placement, routing, power-grid design, vias, and bumps on EMIR. Experience in debugging EMIR violations and providing effective and practical design recommendations for issue resolution. Good understanding of multi-voltage designs, voltage islands, and power-domain interactions. Experience in power-grid robustness analysis and validation and identifying potential design weaknesses early in the implementation cycle. Familiarity with physical design inputs and data such as LEF/DEF, parasitics, power/activity data, technology files, power intent, and design databases. Good understanding of the overall ASIC Physical Design flow from floorplanning through implementation, ECO, and signoff. Experience with scripting languages such as Python, Tcl, Perl, and/or Shell for flow automation, data analysis, reporting, and productivity improvement. Experience working on advanced-node, high-performance, or large-scale SoC designs is preferred. Experience with hierarchical/block-to-top EMIR analysis methodologies is an added advantage. Exposure to chip/package power-integrity interactions, bump planning, and package-related power delivery considerations is preferred. Ability to independently analyze large amounts of EMIR data, identify trends and systematic issues, and drive corrective actions. ACADEMIC CREDENTIALS: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, VLSI, Microelectronics, or a related discipline. #LI-SR5 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Experienced Engineer - ASIC Verification", "company": "Ericsson", "location": "Bangalore,Karnataka,India", "date_posted": "2026-10-21T09:15:30+00:00", "url": "https://jobs.ericsson.com/careers/job/563121776415477", "is_hardware": true, "platform": "eightfold", "jd_text": "Join our Team\n\nAbout this opportunity\n \nWe are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport – to enable communication service providers to surpass the expectations of their end-customers.  At our state-of-the-art design centers, we don't just follow industry trends—we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, you'll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. \n\nAs part of our global R&D organization, you'll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. \n\nCreative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. You'll have the opportunity to explore advanced verification technologies alongside skilled experts.\nGlobal Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. \nWork-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. \nProfessional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere.\nAn international work environment with opportunities for professional growth and development. \nA collaborative and inclusive culture that values diversity and innovation.\n\nYou will do:\n\nTake part in the verification of designs, whether at the block or subsystem level.\nParticipate in defining and implementing UVM-based test environments.\nSupport the creation of Verification Strategies and contribute to the development and execution of Verification Plans.\nDevelop, run, and debug test cases to ensure design quality.\nContribute to the improvement and optimization of verification methodologies.\nGenerate documentation throughout the verification lifecycle.\nCollaborate closely with other verifiers, designers, and architects.\nBuild competence in the technical domain.\nEngage in cross-team collaboration to ensure successful project delivery.\n\nYou will bring:\n\nRequired Qualifications: \nBachelor’s degree in electrical or computer engineering.\n8+ years industry experience in ASIC IP verification using SystemVerilog and UVM.  \nExperience in / with:developing creating directed/randomized test cases.\nimplementing scoreboards, checkers, bus functional models within UVM environments.\nAMBA-based designs such as AXI and CHI.\nSystemVerilog Assertions.\n\nAdditional Requirements:\n\nExperience with Cadence or Synopsys verification suites.\nTeam-oriented, prioritizing team success within the team, across teams, and across sites over individual results.   Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment.\nHigh attention to detail and commitment to quality.\nStrong focus on meeting project deadlines and deliverables.\nProficient in English, with strong communication skills. \n \nPreferred Skills:\nUnderstanding of radio access systems and their components. \nExperience in low-power design verification. \nWorking knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). \nExperience in verification in one or more of the following hardware domains: \nARM-based real-time embedded microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. \nImplementation of hardware-based digital signal processing systems (filters, adaptation, etc.) \n\n*\n\n“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”\n\nWhy join Ericsson?At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.\n \nWhat happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.\n \nPrimary country and city: India (IN) || Bangalore\nReq ID: 786469", "jd_status": "stored"}, {"title": "Staff /Senior Staff Engineer/Principal – Analog Design  Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-21T07:23:37.009000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000156726174-staff-senior-staff-engineer-principal-analog-design-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Looking for an experienced Analog Design engineer to join the 2.6B$ Power Business Unit where in the candidate will get to work on a wide range of exciting products such as Hotswap Contollers, eFuse, IPD’s, PMICs, DC-DC converters and Drivers powering the next generation of automotive power needs.\nEssential Functions:\nExperienced in all aspects of Analog circuit design from block level to full chip with a demonstrated history in driving design innovation and best practices.\nShould have the ability to work independently with little supervision to design complex circuits and take complete ownership to drive all aspects within the committed schedule.\nMust be proficient in transistor level design and system implementation of typical building blocks like charge pumps, comparators, amplifiers, bandgaps, linear regulators, switching regulators etc.\nExperience in leading a team with a proven history of mentoring and promoting new college graduates\nDirect experience in building (concept to market release) power products in any of the desired functions is a big plus.\n\nMinimum Requirements:\nBachelor’s or Master’s degree in Electrical and Computer engineering\n8-15 years in Analog Circuit Design, Simulation,Verification, Hotswap Controller along with IPD’s, PMICs, DC-DC converters\nAdditional Preferred Qualifications\nSolid understanding of IC processing (preferably BCD nodes), packaging and production test along with familiarity with advanced IC CAD tools\nSchematic generation, simulation and verification using modern CAD tools\nFamiliarity with complete simulation suite including block level, top-level, worst-case corner identification and Monte Carlo analysis along with parasitic extraction and simulation.\nSolid understanding of layout care-abouts and identifying limitations of design to testability, debug, characterization and production/yield targets\nMust be a natural team player and strive towards fostering a highly creative and productive working environment\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Camera IP Verification - Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-21T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721650490", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\n\nCandidate will be responsible for IP Level Verification of Qualcomm Spectra Camera Sub Systems Modules for next gen Qualcomm product portfolio. This role will require the candidate to understand details of the camera signal processing modules, verify them at module & subsystem level for enhanced features. Engineer should independently be able to own the verification of IP level modules end to end with continuous enhancements and collaborate with IP Verification, Design and System leads.\nNecessary skills/experience:\n• 3+ years of experience in RTL design verification using SystemVerilog/UVM and industry-standard simulation tools (Mandatory)\n• Experience in power aware simulation is a big plus\n• Experience on camera verification is a big plus\n• Expertise in Coverage closure , RTL debug skills\n• Expertize in SV – UVM, Assertions based verification, DPI\n• Familiarity in Firmware/emulation (ex: Veloce) based verification , GLS\n• Familiarity with bus protocols like AHB, AXI, ARM based system architecture\n• Experience with Perl, Python, or similar scripting language\n• Excellent problem solving skills & Verification aptitude\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "IP Micro-architect (RTL) design Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-21T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719727202", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nRole Focus :Core Domains Architecture definition, microarchitecture development, custom protocol design, RTL implementation, performance optimization, and silicon delivery for complex Custom IPs.\n\nCore Domains: Infrastructure IP, NoC, PCIe, CXL, memory systems, cache coherency, UALink, ESUN, and AI scale-up interconnect fabrics.\n\nJob Summary : Hands-on technical leader capable of driving IP from concept through production silicon while mentoring engineers and influencing architecture decisions. We are seeking a highly motivated and experienced Senior IP Micro-architect to join our Custom IP Team focused on developing next-generation Infrastructure IPs, memory subsystem solutions, and scalable interconnect architectures for high-performance SoCs. The ideal candidate will possess deep expertise in architecture definition, microarchitecture development, protocol design, RTL implementation, and performance optimization for complex custom IPs. This role requires strong technical leadership, hands-on design expertise, and the ability to drive IP development from architectural concept through silicon realization.\n\nKey Responsibilities • Drive architecture and microarchitecture definition of complex custom Infrastructure IPs. • Develop detailed microarchitecture specifications including datapath design, control logic, packet formats, flow control, ordering rules, coherency mechanisms, and state machines. • Lead RTL development and collaborate closely with verification, physical design, firmware, and SoC integration teams. • Evaluate and optimize architecture trade-offs across performance, power, area, scalability, latency, and implementation complexity. • Design and develop high-performance interconnect, memory, and protocol-centric IP solutions. • Drive design reviews, microarchitecture reviews, and technical decision-making across multiple projects. • Support verification planning, debug, emulation, FPGA validation, and silicon bring-up activities. • Ensure RTL quality through lint, CDC/RDC, synthesis, and design signoff methodologies. • Mentor junior engineers and provide technical leadership within the IP development team. • Stay abreast of emerging technologies in AI infrastructure, scale-up fabrics, memory systems, and high-speed interconnects.\n\nRequired Qualifications • 8-15 years of experience in SoC/IP architecture, microarchitecture, and RTL design. • Proven experience defining and delivering complex custom IPs from concept through production silicon. • Strong experience in architecture and microarchitecture development of one or more of the following: Infrastructure IPs, NoC, interconnect fabrics, memory subsystem IPs, cache coherency solutions, or high-speed interface IPs. • Strong understanding of computer architecture, SoC architecture, digital design methodologies, performance modeling and analysis, synchronization and flow control mechanisms, and high-performance data movement architectures. • Hands-on RTL design experience using Verilog/SystemVerilog. • Experience with design signoff methodologies including lint, CDC/RDC, synthesis, and timing closure fundamentals. • Strong debugging, analytical, and problem-solving skills. • Excellent verbal and written communication skills. • Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nPreferred Skills • Experience building custom protocol-based IPs from ground-up architecture through silicon validation. • Familiarity with AI, Datacenter, Compute, Automotive, Mobile, or XR SoC architectures. • Experience with ASIC design and implementation flows. • Knowledge of scripting and automation using Python, Perl, or Tcl. • Experience with Git, ClearCase, or similar version control systems. • Exposure to post-silicon debug and bring-up.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Hardware Security Architect – Staff", "company": "Qualcomm", "location": "Chennai, Tamil Nādu, India", "date_posted": "2026-10-21T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721419465", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Systems Engineering\nGeneral Summary:\nIn this position you will join the team responsible for the security architecture of Qualcomm Snapdragon processors. The team works at a system level spanning across hardware, software and infrastructure while striving for industry-leading solutions. This team interacts with product management, customers (e.g., OEMs), partners, HW/SW engineering, and Services engineering teams to find the optimal Security solution. Snapdragon processors are utilized in a variety of devices, including mobile phones, laptops, automotive systems, and data centers, each with distinct security needs. These processors are engineered to address most of these requirements, encompassing a wide range of security technologies found in consumer electronics, such as Root of Trust, Integrated Secure Element, Virtualization, and Confidential Compute.\n\nMinimum Qualifications\n10+ years industry experience in SoC Security encompassing both architecture and design\n5+ years industry experience in Compute and/or Data Centre SoC Architecture\nDemonstrated expertise in Security Technologies (Root of Trust, TEE, Access Control, I/O Security)\nProficient in Confidential Compute Architecture (RME, TDX, SEV-SNP, TDISP)\nStrong understanding of Security Software Architecture for Compute and Data Centers, with a focus on Secure Boot.\nSkilled in HW/SW threat analysis\nStrong capabilities in creating and presenting architecture-level documentation.\n\nPreferred Qualifications\nProficient in isolation-related extensions, including TrustZone, Virtualization, and RME.\nExtensive knowledge of Server Platform security architecture covering lifecycle/debug management, provisioning, attestation/measurement.\nExpertise in Applied Cryptography and Protocols.\nKnowledgeable about Security Certification Processes and Requirements (such as OCP)\nExcellent communication and teamwork skills.\nLeadership and management experience at the project level\n\nKey Responsibilities\nEstablish system security requirements (both hardware and software) for Server SoC focusing on functionality, performance, and security levels.\nSpecify and review the architecture and implementation of System/SoC level security mechanisms.\nConduct platform security threat analysis.\nPerform competitive analysis of security systems and features\nExplore future and roadmap server security-related technologies.\nServe as the technical interface to product management and standards teams.\n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.\n                                                                    OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience.\n                                                                    OR\nPhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "BT - Design Verification Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-21T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720255082", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nJob Area: Hardware Engineering (Verification)\n\nQCT's Bangalore Wireless R&D Bluetooth HW team is looking for experienced Wireless HW design verification engineers to work on Qualcomm’s best in class chipsets for mobile phones, wearables and IOT. Candidate will be working with ASIC designs on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, emulation, GLS and Formal techniques. The role also requires deep understanding of the Bluetooth Hardware Architecture.  Candidate will require close interactions with Global Design, Systems, SoC, Validation and FW teams for design convergence and required to work with minimal supervision. Candidate must be able to take ownership of IP/Block/Sub-System verification. Incumbent will be analyzing HW design spec and develop a verification test plan/strategy for it, breaking down the work for new features, perform feasibility studies, estimate effort and mitigate risk. The role also required the candidate to mentor new joiners and less experienced colleagues.  The candidate will work with design team on RTL debug during Pre-silicon HW development phase.\n\nSkills/Experience:\n6-10 years of strong experience in design verification\n\nStrong knowledge of HDLs like Verilog, System Verilog\n\nProven experience of writing efficient constraint random tests\n\nProven experience of building or maintaining a medium to complex SV/UVM environments\n\nStrong debugging and analytical skills and independent problem solving ability\n\nProficient in debugging RTL/TB issues using Verdi or similar tools\n\nDemonstrate good judgment in selecting methods and techniques for obtaining solutions\n\nStrong communication skills, both written and verbal, with ability to evaluate and create testplans detailing complex features and relationships\n\nBachelor’s or Master’s Degree in Engineering in Electronics, VLSI, Communications or related field\n\nMinimum Qualifications:\nBachelor’s Degree in Engineering in Electronics, VLSI, Communications or related field\n\n6 years of VLSI industry experience in verification\n\nPreferred Qualifications:\nExposure to Bluetooth/BLE Technologies\n\nKnowledge on scripting languages such as Perl and(or) Python\n\nSkills:\nFunctional Verification, Functional/Code Coverage, SystemVerilog Assertions, Universal Verification Methodology (UVM), Verification IP (VIP) Integration, SoC Integration, Formal checks\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Engineer I - Digital Verification", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-10-21", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Senior-Engineer-I---Digital-Verification_R4408-26-1", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nCompany Overview\nAt Microchip, we are at the forefront of technology innovation, committed to delivering cutting-edge solutions to our customers. We specialize in designing and manufacturing high-performance integrated circuits, with a focus on precision analog-to-digital converters (ADCs), DACs, Voltage References (Vrefs),  Op-Amps, Comparators, Current Sense Amplifiers, and Inductive Sensors that serve a wide range of applications in industries such as telecommunications, medical devices, instrumentation, and aerospace. Join our dedicated team of professionals who are passionate about pushing the boundaries of technology and excellence.\n \nJob Description\n \nThe Mixed Signal & Linear Business Unit (MSLD) provides a broad spectrum of analog and mixed-signal products and solutions that enable customers to interact with real world signals through digital systems. MSLD team is actively looking for an Experience Digital Verification Engineer to Verify high performance data converters and other mixed signal products which use data converters. This is a hands-on technical contributor role that will allow the right candidate to develop their engineering skills and participate in varied, interesting and challenging development projects. The successful candidate works to achieve operational targets with major impact on the departmental results.\nDefine and develop verification architecture\nDefine and develop verification methodologies\nDefine and develop verification environments\nWrite verification specifications, verification plans, and documentation\nGenerate test bench and automatic regression plans\nBe responsible for verification architecture, simulations, verifications, and debugging of circuit and logic designs\nComplete block-level verification and chip level verification\nBring a self-motivated and enthusiastic approach that will achieve any new requirements and overcome all challenges\nAble to debug the RTL for design intent and Interface with cross-functional teams and collaboration in all verification related activities\nMentor Junior Engineers on need basis\nPresent verification plan and verification results to product team.\nDrive product verification activity to closure with metric driven verification methodology\nWork with validation team for post silicon debug\n\nRequirements/Qualifications:\n\nJob Requirements\nBachelor/Master degree in Electronics or Equivalent\n5+ years of experience in Digital Verification\nLanguages (Must) : Verilog and System Verilog\nMethodologies (Any one) : OVM, VMM., UVM (UVM Preferred)\nEDA Tools (One of them is must): Questasim, VCS, NCSim, NCVerilog\nGood understanding of digital design fundamentals\nProficient with Unix environment and common scripting languages\nExpertise in test plan development\nExpertise in Functional / Code Coverage activity\nExperience in IP level verification activities\nHands on project experience in coverage/assertion driven verification\nHands on project experience in constrained random stimulus and auto checking verification\nTestbench development in Verilog/SystemVerilog using verification methodology\nStrong in simulation and debugging skills\nKnowledge of revision control tools like CVS and GIT\nExperience in UVM methodology\nMust have strong written and verbal communication skills with an ability to work with teams spread across geographic locations\nSelf-motivated and capable of working independently or as part of a team. Should know when to ask for help\nMixed signal verification & real number modeling (Preferred)\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Senior Engineer II-Digital Design", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-10-21", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Senior-Engineer-II-Digital-Design_R4490-26", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nCompany Overview\nAt Microchip, we are at the forefront of technology innovation, committed to delivering cutting-edge solutions to our customers. We specialize in designing and manufacturing high-performance integrated circuits, with a focus on precision analog-to-digital converters (ADCs), DACs, Voltage References (Vrefs),  Op-Amps, Comparators, Current Sense Amplifiers, and Inductive Sensors that serve a wide range of applications in industries such as telecommunications, medical devices, instrumentation, and aerospace. Join our dedicated team of professionals who are passionate about pushing the boundaries of technology and excellence.\n \nJob Description\n \nThe Mixed Signal & Linear Business Unit (MSLD) provides a broad spectrum of analog and mixed-signal products and solutions that enable customers to interact with real world signals through digital systems. MSLD team is actively looking for an Experience Digital Engineer to design/architect high performance data converters and other mixed signal products which use data converters. This is a hands-on technical contributor role that will allow the right candidate to develop their engineering skills and participate in varied, interesting and challenging development projects. The successful candidate works to achieve operational targets with major impact on the departmental results.\n\nThrough understanding of digital design, RTL coding and simulation\nInvolved in architectural and micro architecture design\nExperienced in Lint, CDC, logic synthesis, formal verification and static timing analysis\nWorked with physical design team for layout implementation\nFamiliar with low power methodology and flow\nCapable of debugging EDA tool issues or design related issues\nKnowledge in DFT is must\nGood script language skill using Tcl, Perl and/or Awk\nProtocol knowledge and experience in serial peripherals SPI/I2C is plus\n\nRequirements/Qualifications:\n\nJob Requirements\nBachelor/Master degree in Electronics or Equivalent\n7+ years of experience in VLSI / RTL design.\nProficient with Unix environment and common scripting languages\nKnowledge of revision control tools like CVS and GIT\nMust have strong written and verbal communication skills with an ability to work with teams spread across geographic locations\nSelf-motivated and capable of working independently or as part of a team. Should know when to ask for help\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "GPU IP Integration Model Build Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-21", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/GPU-IP-Integration-Model-Build-Engineer_JR0286908", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nPerforms functional verification model integration of graphics logic components, including 3D graphics, media, to ensure design will meet specification requirements. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification. Closely work with different clusters owners and integrate their code into media IP.\n\nQualifications:\nMinimum Qualifications:\n\n• Master's degree in a relevant field (e.g., Electronics, Computer Science, Embedded Systems) with 3-7 years of hands-on experience in domain-specific areas such as pre- silicon simulation model builds, VLSI design, or testing.\n• Ability to design, develop, understand, and optimize test environments such as stress stimuli and trackers to validate and verify products, components, and systems.\n• Ability to architect and implement an IP test environment (checkers, monitors, test infrastructure, VC) to meet the requirements of IP/SoC including expertise in Verdi, VCS, and UVM/OVM\n• Knowledge of digital basic building blocks (including combinatorial/sequential design, finite state machines, registers, counters),\n• Ability to make commitments through clear, prioritized goals and high-quality decisions, assume responsibility for outcomes, and predictably execute and meet those commitments over time. Ability to overcome challenges, recover from setbacks, and adapt and adjust course as needed based on data to achieve desired results for the team, customers, and Intel. Consistently uses Intel's enterprise standards for goal setting, decision making, and meeting practices to move work forward rapidly and effectively.\n• Knowledge of tools and flows used to validate an IP and handoff to SoC.\n• Ability to identify and diagnose a problem, to propose, implement, and test solutions, and to drive effective and sustainable solutions across unique situations.\n• Knowledge of validation processes including HSD-ES, DCCB (APM), and Gatekeeper management.\n• Working knowledge of scripting languages, including Python, Perl, or Ruby.\n• Demonstrated problem-solving, debugging, and technical analysis skills.\n\nPreferred Qualifications:\n\n- Understanding of media industry trends and technologies.\n- Strong communication and teamwork skills to drive collaboration across technical teams.\n\nTake the next step in your career by joining Intel's team of experts dedicated to pushing the boundaries of technology. Your contributions will help shape the future of computing, and we look forward to exploring your unique perspective and skills.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "GPU IP Lead Emulation Model Build Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-21", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/GPU-IP-Lead-Emulation-Model-Build-Engineer_JR0286914", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nStandalone drives and builds functional Emulation model environment using graphics logic components, including 3D graphics, media for various media IP's, Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design builds. works with different EDA vendors to enhance emulation model builds.\n\nQualifications:\nMinimum Qualifications:\n\n• Master's degree in a relevant field (e.g., Electronics, Computer Science, Embedded Systems) with 8-15 years of hands-on experience in pre- silicon Emulation model builds using different vendor platforms.\n• Knowledge of emulation model builds and releases and/or ability to perform analysis on the emulation model performance and size. Ability to experiment with various techniques and solutions to reduce model size in situations where RTL constructs lead to unwanted size increase such memory structure implemented as registers\n• Knowledge of and ability to use emulators (e.g., ZeBu, Palladium, Veloce or FPGA) that create and run virtual machines to develop and implement test plans, create test scenarios, and validate IPs/SoCs on emulation platforms. Ability to use emulation software suites including Maestro, Metro-Maestro, and Supercollider.\n• Ability to understand what emulation is, differences between emulation and other pre-silicon platforms, procs and cons, various usages, and latest emulation industry trend. Ability to use emulation models for RTL verification, FW-HW co-verification, and performance validation.\n• Knowledge of emulation model builds and releases and/or ability to perform analysis on the emulation model performance and size. Ability to experiment with various techniques and solutions to reduce model size in situations where RTL constructs lead to unwanted size increase such memory structure implemented as registers.\n• Ability to design, develop, understand, and optimize test environments such as stress stimuli and trackers to validate and verify products, components, and systems.\n• Ability to architect and implement an IP test environment (checkers, monitors, test infrastructure, VC) to meet the requirements of IP/SoC including expertise in Verdi, VCS, and UVM/OVM\n• Knowledge of digital basic building blocks (including combinatorial/sequential design, finite state machines, registers, counters),\n• Ability to make commitments through clear, prioritized goals and high-quality decisions, assume responsibility for outcomes, and predictably execute and meet those commitments over time. Ability to overcome challenges, recover from setbacks, and adapt and adjust course as needed based on data to achieve desired results for the team, customers, and Intel. Consistently uses Intel's enterprise standards for goal setting, decision making, and meeting practices to move work forward rapidly and effectively.\n• Knowledge of tools and flows used to validate an IP and handoff to SoC.\n• Ability to identify and diagnose a problem, to propose, implement, and test solutions, and to drive effective and sustainable solutions across unique situations.\n• Knowledge of validation processes including HSD-ES, DCCB (APM), and Gatekeeper management.\n• Working knowledge of scripting languages, including Python, Perl, or Ruby.\n• Demonstrated problem-solving, debugging, and technical analysis skills.\n\nPreferred Qualifications:\n\n- Understanding of media industry trends and technologies.\n- Strong communication and teamwork skills to drive collaboration across technical teams.\n\nTake the next step in your career by joining Intel's team of experts dedicated to pushing the boundaries of technology. Your contributions will help shape the future of computing, and we look forward to exploring your unique perspective and skills.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Board Level Power Delivery Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-21", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Board-Level-Power-Delivery-Design-Engineer_JR0287263", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nIntel India Customer Engineering Team is in a mission to create successful Original Design Manufacturers (ODMs) from India across their customer base. We are seeking a Hardware Board Design Engineer specializing in Power Delivery design and debug experience to help Intel customers design and debug their hardware platforms based on Intel Core and Atom CPUs.\n\nQualifications:\n• Education: Bachelor's or Master's degree in Electronics/Electrical Engineering or related field\n• Experience: 7-12 years of industry experience (preferably 5-6 years designing and debugging hardware boards with Power Delivery focus using Intel Core/Atom CPUs)\n• Power Delivery Expertise: Deep understanding of system Power Delivery requirements and familiarity with Intel Core/Atom processor Power Delivery guidelines including IMVP specifications and PDN analysis\n• Circuit Design: Extensive experience with Buck, Boost, and Multi-phase Power Delivery Network design, including control loop understanding and very high current/low-voltage power delivery design\n• Design Tools: Proficiency in schematic capture using industry standard tools (Cadence OrCAD, Mentor Graphics xPedition, Altium Designer etc) and ability to review complex digital and analog circuits layout\n• PCB Design: Experience with multi-layer stack-up design (8-16 layers) and layout guidelines for Power Delivery of different processor rails including IMVP Rails\n• Power Integrity: Strong understanding of Power Delivery design, power budgeting and Power Integrity practices with hands-on experience in PI simulation tools (Cadence Sigrity and Siemens HyperLynx)\n• Manufacturing Knowledge: Good understanding of board manufacturing guidelines, DFM/DFT practices, and assembly processes\n• Debug Skills: Hands-on experience with board power-on and debugging, especially Intel processor-based platform debugging using lab tools (multimeter, oscilloscope, electronic load etc.)\n• Problem Solving: Ability to analyze debug results, ensure correct functionality, triage failures, and develop corrective actions\n• Customer Support: Capability to provide technical support to customer queries on Power Delivery design and assist with board debug and power-on support\n• Communication: Good listening and communication skills for effective customer interaction\nPreferred Qualifications\n• Customer Facing Experience: Previous experience in customer-facing roles with ability to translate complex technical concepts to diverse audiences.\n• Platform Knowledge: Familiarity with Intel platform architecture, chipsets, and ecosystem components\n• Regulatory Knowledge: Understanding of EMI/EMC requirements and compliance testing procedures\n• Industry Standards: Knowledge of industry standards (JEDEC, USB-3.2 Type C Power Delivery, etc.) related to power delivery and platform design\n• Training & Documentation: Experience creating technical documentation, application notes, and conducting training sessions for customers\n• Presentation Skills: Ability to present to technical and non-technical audiences at various organizational levels\n• Adaptability: Ability to work in a fast-paced environment with changing customer requirements and urgent support requests\n \nTravel Requirements\n• Domestic Travel: Regular travel to customer locations across India (up to 40-50% travel) to support design reviews, debug sessions, and training activities\n• Flexibility: Ability to accommodate urgent customer requests requiring immediate on-site support\n \nPrimary Location\nIndia, Bangalore\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "CPU Power Delivery Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-21", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/CPU-Power-Delivery-Engineer_JR0288288", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nAs a CPU Power Delivery Engineer, you will play a pivotal role in shaping the future of high-performance computing by driving the physical design implementation of cutting-edge CPU designs. You will ensure robust IR drop, electromigration, and power integrity performance across required operating modes and conditions. This role works across design, physical design, package, and technology teams to reduce risk and support successful silicon delivery.\n\nBusiness group\nYou will join Intel Corporation's CPU design and development team, which is dedicated to engineering world-class computing solutions. This group is at the heart of innovation, delivering high-performance designs that power industry-leading technologies and support Intel's broader mission to advance computing performance and capabilities globally.\n\nKey Responsibilities\n- Own CPU power delivery and power integrity analysis across implementation and signoff, including static and dynamic IR drop, electromigration, and overall power integrity closure.\n- Develop and drive power grid strategies, power planning, and optimization to meet CPU performance, power, and reliability targets.\n- Debug and resolve complex power delivery issues in partnership with physical design, package, clock, and RTL teams.\n- Review and guide floorplan, bump, strap, decap, and grid decisions to improve top-level CPU power robustness.\n- Track power integrity risks, drive mitigation plans, and support signoff readiness for successful tapeout.\n\nQualifications:\nMinimum Qualifications\n- Bachelor's degree in Electrical Engineering, Electronics Engineering, or related field with 3+ years of hands-on experience OR Master's degree in a relevant field with 2+ years of hands-on experience with strong exposure to CPU or high-performance IP timing closure.\n- Strong experience in CPU or high-performance IP power delivery, power integrity, or physical design.\n- Solid understanding of IR drop, electromigration, decap strategy, power grid design, and signoff methodology.\n- Hands-on experience with industry-standard tools such as RedHawk, PrimePower, Kelvin, and related power integrity or physical design tools.\n- Proficiency in Tcl and at least one scripting language such as Python or Perl.\n- Strong debugging, problem-solving, and cross-functional communication skills.\n\nPreferred Qualifications\n- Knowledge of scripting languages like Tcl, Perl, or Python for workflow automation in physical design.\n- Proven ability to work effectively in dynamic, cross-geographical, and interdisciplinary teams.\n- Enthusiasm for designing world-class CPUs that drive innovation and empower future technologies.\n\nWe're eager to welcome talented engineers who are passionate about technology and thrive in collaborative environments. If you're excited to contribute to groundbreaking designs and make an impact, we encourage you to apply today.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "CPU Senior Timing Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-21", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/CPU-Senior-Timing-Engineer_JR0288282", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nAs a CPU Senior Engineer, you will play a pivotal role in shaping the future of high-performance computing by driving the physical design implementation of cutting-edge CPU designs. You will ensure that the design meets frequency, power, and signoff targets across all required modes and corners. This role works across design, block timing, physical design, clocking, and integration teams to resolve critical timing issues, improve timing predictability, and support successful tapeout.\n\nBusiness group\nYou will join Intel Corporation's CPU design and development team, which is dedicated to engineering world-class computing solutions. This group is at the heart of innovation, delivering high-performance designs that power industry-leading technologies and support Intel's broader mission to advance computing performance and capabilities globally.\n\nKey Responsibilities\n- Drive top-level timing analysis and closure for CPU IP across implementation and signoff stages.\n- Develop, review, and maintain timing constraints, MMMC scenarios, path budgets, and timing exceptions for top-level integration.\n- Analyze and resolve setup, hold, clock gating, noise, and cross-block timing issues affecting CPU performance targets.\n- Partner with RTL, block owners, physical design, and clock teams to close critical paths and improve timing convergence.\n- Ensure correlation between block-level, top-level, and signoff timing environments, and track timing risks against project milestones.\n- Develop scripts and methodology improvements to automate timing analysis, reporting, and closure efficiency.\n\nQualifications:\nMinimum Qualifications\n- Bachelor's degree in Electrical Engineering, Electronics Engineering, or related field with 4+ years of hands-on experience OR Master's degree in a relevant field with 3+ years of hands-on experience with strong exposure to CPU or high-performance IP timing closure.\n- Strong knowledge of static timing analysis, MMMC flows, timing constraints, OCV/derates, crosstalk, and timing exceptions.\n- Hands-on experience with STA tools such as PrimeTime or Tempus, and familiarity with implementation tools such as ICC2 or Innovus.\n- Proficiency in Tcl and at least one scripting language such as Python, Perl, or shell.\n- Strong debugging, problem-solving, and cross-functional communication skills.\n\nPreferred Qualifications\n- Knowledge of scripting languages like Tcl, Perl, or Python for workflow automation in physical design.\n- Proven ability to work effectively in dynamic, cross-geographical, and interdisciplinary teams.\n- Enthusiasm for designing world-class CPUs that drive innovation and empower future technologies.\n\nWe're eager to welcome talented engineers who are passionate about technology and thrive in collaborative environments. If you're excited to contribute to groundbreaking designs and make an impact, we encourage you to apply today.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "BIOS Firmware Development Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-21", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/BIOS-Firmware-Development-Engineer_JR0288239", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nAs a Sr. Firmware/BIOS Engineer, you will drive the design and implementation of firmware/BIOS solutions for IP and subsystem components within System-on-Chip (SoC) products. This role requires a strong foundation in SoC and system-level architecture, firmware development in resource-constrained environments, and hardware/firmware co-engineering methodologies to ensure the highest quality product delivery.\nYou will pioneer innovative approaches to firmware development, including AI-assisted engineering workflows, to enhance efficiency and accuracy. Additionally, you will design scalable and flexible firmware architectures that support graceful evolution across multiple disciplines and future product generations.\n\nBusiness Group\nAs part of Intel's Client Computing and Physical AI Group (CCPG), you will be joining the Software and AI (AI) group, a team dedicated to creating innovative software solutions that maximize performance and efficiency across Intel technologies. This group plays a critical role in developing firmware for Intel's advanced silicon products, Edge and Physical AI systems, contributing to the company's mission to deliver world-class computing experiences.\n\nKey Responsibilities\n• As a Senior Firmware Engineer, you will Drive end-to-end BIOS/firmware design, implementation, integration, debug, and delivery for a chiplet-based platform involving new internal IP and third-party IP.\n• Work closely with hardware, architecture, platform, validation, security, and program teams to define requirements, resolve issues and drive the implementation.\n• Design and Implement scalable, modular, and maintainable firmware/BIOS solutions across IP, SoC, and platform layers, ensuring correctness, extensibility, and robust system behavior.\n• Design, implement, and debug embedded firmware/BIOS in constrained environments using C, C++, and Python across pre-silicon and post-silicon phases, including RTL simulation, emulation, silicon bring-up, and platform validation.\n• Drive enablement of new silicon capabilities, platform features, and third-party components within the BIOS/firmware stack.\n• Establish strong engineering discipline through design reviews, code reviews, debug methodologies, continuous integration, automation, and issue tracking.\n• Collaborate on HW/FW co-design and co-validation flows, including test infrastructure, automation frameworks, and debug tools.\n• Maintain source code using professional systems like GitHub, ensuring seamless software development integration.\nWork on various firmware interfaces, including PCIe, UART, I2C, SPI, USB, TCSS, SATA, UFS, eMMC, and others, for enhanced system functionality.\n• Drive continuous improvement in engineering productivity through modern development practices and effective use of AI-assisted engineering tools.\n\nWhat We're Looking For\n• Results-oriented ownership, autonomously solving complex system-level problems spanning technical and organizational boundaries.\n• Strong understanding of system software and firmware interactions.\n• Strong interpersonal and collaboration skills, with the ability to influence across functions, teams, and geographic sites.\n\nQualifications:\nMinimum Qualifications\n- Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field with 4+ years of industry experience, or a Master's degree in the same fields with 3+ years of experience, or a PhD with no prior professional experience.\n- Proficiency in C programming with hands-on experience in BIOS, Core-boot, or embedded firmware development.\n- Strong understanding of modern processor architecture, computer systems architecture, and low-level firmware that directly interfaces with hardware.\n- Experience with UEFI, ACPI, and modular software design within the Intel Architecture domain.\n- Familiarity with source code management systems such as GitHub for professional software development.\n- Hands-on experience with debugging and trace tools, including Intel x86 ITP and CCA debuggers.\n\nPreferred Qualifications\n- Strong knowledge in x86 Processors, and system software architecture.\n-Software and firmware development practices including patch submission, bug reporting, and code reviews.\n- Knowledge of platform buses and interfaces such as PCIe, UART, IC, SPI, TCSS, USB, SATA, UFS, eMMC, and other related technologies.\n- Demonstrate strong technical communication, organizational and collaboration skills with the ability to effectively work across diverse teams and environments.\n- A proactive, resourceful approach to problem-solving combined with strong analytical and interpersonal skills.\n\nBring your expertise and passion for firmware engineering to Intel and take your career to the next level. Join us in shaping the future of edge computing and delivering impactful solutions to the global technology landscape.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "SOC RTL Design Engineer", "company": "Lattice", "location": "Pune, India", "date_posted": "2026-10-21", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Pune-India/SOC-RTL-Design-Engineer_R-101168", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\n\nLattice Semiconductor is seeking a SoC RTL Design Engineer to join the HW design team focused on IP design and full chip integration.  This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn, innovate and grow.\nRole specifics:\n·       This is a full-time individual contributor position located in Pune, India.\n·       The role will focus on FPGA projects concentrated in Pune and similar time zones.\n·       The qualified candidate will be working in RTL design, best-in-class coding styles, algorithms, and both Verilog and System Verilog.\n·       The qualified candidate will be working in SoC integration and associated quality checks including lint, CDC, RDC, SDC etc.\n·       The role requires to work with architect and micro-architect team to understand define design specifications\n·       The successful candidate will be open and willing to both (a) teach best-known-methods to an existing FPGA team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and an open-minded student. \n\nAccountabilities:\n·       Serve as a key contributor to FPGA design efforts.\n·       Drive logic design of key FPGA blocks & full chip and bring best-in-class methodologies to accelerate design time and improve design quality.\n·       Ensuring design quality through assertions, checkers, and scripting.\n·       Develop strong relationships with worldwide teams.\n·       Mentor and develop strong partners and colleagues.\n·       Occasional travel as needed.\n\nRequired Skills:\n·       BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent.\n·       6+ years of experience in driving logic design across a multitude of silicon projects.\n·       Expertise in SoC integration, defining micro-architecture and experience of selecting 3rd party IP.\n·       Experience in working with ARM processor, AXI, AMBA bus, ENET, PCIE, safety and security protocols, debug architecture will be plus.\n·       Familiarity with FPGA designs, use-cases, and design considerations is a plus.\n·       Independent worker and leader with demonstrated problem-solving abilities.\n·       Proven ability to work with multiple groups across different sites and time zones.\n\nLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.\n\nLattice\nFeel the energy.\n\n#LI-DNP\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Advanced Package Architect Sr. Staff Engineer", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-10-21", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Advanced-Package-Architect-Sr-Staff-Engineer_2605053", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nAbout Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.\nYour Team, Your Impact\n\nWithin this ecosystem, Marvell’s central advanced packaging organization plays a critical role in delivering next generation connectivity and compute products. The organization brings deep expertise in architecture, package design, and electrical performance, including SI/PI to develop advanced IC packages that support high speed interfaces. This work directly shapes product performance, reliability, and time to market, making it a key contributor to Marvell’s overall technology leadership.\nWhat You Can Expect\nWhat You Can Expect\nMarvell’s Central Engineering team is seeking a talented High-speed IC package development engineer to contribute to the development of advanced microelectronic packages.\nThe engineer will be responsible for driving microelectronic package development from concept through tapeout, working with package architects and technical leads to select appropriate technologies and ensure manufacturability, performance, reliability, and cost compliance.\nKey responsibilities include developing C4 and BGA ball maps optimized for SI/PI and layout efficiency; planning and validating netlist mappings across dies, interposers, and substrates; and defining die placement, padstacks, net assignments, and package‑level connectivity.\nThe engineer will create and maintain Package Requirement Documents (PRDs) detailing die arrangements, stackups, and design constraints.\n\nWhat We're Looking For\nWhat We're Looking For", "jd_status": "stored"}, {"title": "Package Layout Design Staff/Senior Staff Engineer", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-10-21", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Package-Layout-Design-Staff-Senior-Staff-Engineer_2605056", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nThe Marvell Advanced Packaging team is responsible for package designs\nthat meet challenging electrical requirements. High speed signaling and challenging power delivery networks require complex and custom solutions to meet constantly advancing application needs. Many of the new designs require multi-chip and multiple component configurations with high-speed IP requirements. In addition, our team is advancing Marvell's expertise in 3D packaging, Co-packaged optics and cutting-edge substrate materials. We work with the world's leading manufacturers to solve our client's most challenging designs and integrations with industry-leading packaging techniques.\nWhat You Can Expect\nWhat You Can Expect\nMarvell’s Central Engineering team is seeking a talented High-speed IC package development engineer to contribute to the development of advanced microelectronic packages.\nThe engineer will be responsible for driving microelectronic package development from concept through tapeout, working with package architects and technical leads to select appropriate technologies and ensure manufacturability, performance, reliability, and cost compliance.\n\nWhat We're Looking For\nWhat We're Looking For", "jd_status": "stored"}, {"title": "R&D - Senior Firmware Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-10-21", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/R-D---Senior-Firmware-Engineer_R-10065800", "is_hardware": true, "platform": "workday", "jd_text": "Job Summary:\nWe are seeking an Embedded Firmware Engineer with 4-8 years of experience in real-time embedded software development to design, develop, and validate firmware for UWB/NB modem, ranging, and radar systems. The ideal candidate will have strong expertise in Embedded C, microcontroller/SoC architectures, device drivers, HAL development, hardware bring-up, and system-level debugging, along with experience in communication protocols such as SPI, I2C, and UART. Knowledge of UWB technologies, modem software, DSP concepts, wireless PHY/MAC protocols, and ranging/radar applications is preferred. The role requires close collaboration with architecture, DSP, RF, and validation teams to deliver high-performance wireless connectivity solutions.\n\nJob Qualification:\n4-8 years of experience in Firmware with Bachelors/Masters in EC/CS/EEE/IS.\nStrong Embedded C programming skills with experience in real-time embedded systems.\nGood understanding of microcontroller/SoC architectures, interrupts, DMA, timers, and memory management.\nExperience in embedded software development for UWB/NB modem, or signal-processing systems.\nKnowledge of software architecture, HAL/driver development, and hardware bring-up.\nFamiliarity with debugging tools such as JTAG, SWD, Trace32, logic analyzers, and oscilloscopes.\nUnderstanding of communication protocols and interfaces such as SPI, I2C, UART, IPC, and mailbox mechanisms.\nStrong problem-solving and system-level debugging skills.\nPreferred / Domain-Specific Skills\nKnowledge of Ultra-Wideband (UWB) and Narrowband (NB) communication systems.\nUnderstanding of Ranging, Radar, and wireless PHY/MAC concepts.\nKnowledge of IEEE 802.15.4z / 802.15.4ab and UWB ranging concepts\nExperience with modem software\nFamiliarity with DSP signal-processing concepts for UWB ranging and radar applications\nExposure to automotive, industrial, or IoT wireless products.\n\nJob Responsibilities\nDesign, develop, and maintain embedded software for modem - UWB/NB ranging, and radar subsystems.\nDevelop HAL, drivers, middleware, and system software for modem and RF control.\nIntegrate and validate BB, DSP, and RF components on silicon, FPGA, and simulation platforms.\nTroubleshoot complex system-level issues spanning software, DSP and modem domains.\nCollaborate with architecture, algorithm, DSP, RF, and validation teams to deliver scalable solutions.\n\nMore information about NXP in India...\n\n#LI-7013", "jd_status": "stored"}, {"title": "Staff Engineer, Systems Design/Architecture Engineering", "company": "Analog Devices", "location": "India, Bangalore, Nova", "date_posted": "2026-10-21", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-Nova/Staff-Engineer--Systems-Design-Architecture-Engineering_R267232", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nJob Responsibilities:\nLead the architecture, development, and integration of SystemC/TLM-2.0 virtual platforms for complex multi-core SoCs, including processors, interconnects, memory subsystems, peripherals, accelerators, and custom IPs.Own individual IP modeling and lifecycle maintenance, ensuring alignment with evolving specifications.\nDefine and own the virtual platform modeling strategy, methodology, coding standards, and reusable model libraries across programs.\nServe as technical lead for multiple IP models and full-system platforms, managing them from specification through release and lifecycle maintenance.\nDrive shift-left enablement by delivering virtual platforms early for firmware, driver, OS, and application bring-up ahead of RTL and silicon availability.\nArchitect models of complex system behavior, including memory-mapped transactions, interrupts, DMA, cache coherency, power management, security, and bus protocols\nDefine model validation and RTL correlation strategies, including co-simulation and hybrid emulation flows, regression infrastructure, and quality metrics.\nIntegrate virtual platforms with third-party and open-source ecosystems such as QEMU, Synopsys Virtualizer, Cadence, Siemens, and Arm Fast Models, as well as debuggers and CI/CD pipelines.\nWork with architecture, hardware, software, verification, and product teams to set VP requirements, milestones, and deliverables aligned with program schedules.\nLead post-silicon validation and debug support by reproducing field and silicon issues on virtual platforms, performing root-cause analysis, and feeding results back into models and specifications.\nMentor and technically guide P1–P3 engineers through design and code reviews and technical growth.\nRepresent the modeling team in cross-site technical forums, customer engagements, and industry standards discussions\n \n \n \nPosition Requirements:\nMinimum B.E./B.Tech or MS/M.Tech/Ph.D. in Electrical, Electronics, or Computer Science.\nB.E./B.Tech with 8–12 years, MS/M.Tech with 6–10 years, or Ph.D. with 4+ years of relevant industry experience.\nExpert-level knowledge of SystemC, TLM-2.0, C, and modern C++ (C++14/17), including model performance optimization.\nProven track record of architecting and delivering full-system SoC virtual platforms used in production software development.\nDeep experience with ARM and/or RISC-V processor architectures, including ISS/CPU model integration, boot flows, and software bring-up (bare-metal, RTOS, Linux).\nStrong understanding of SoC architecture, memory hierarchies, coherency protocols, interconnects, and hardware/software co-design.\nExperience with commercial or open-source VP tools and frameworks (e.g., Synopsys Virtualizer, Arm Fast Models, QEMU, GreenSocs/QBox).\nExperience with RTL co-simulation, hybrid emulation, or model-to-RTL correlation methods.\nProficient in Python and build systems (CMake) for automation, model generation, and validation.\nHands-on experience with software development practices and tools such as Agile, DevOps, Git, Jenkins/GitHub Actions, and code-quality tooling.\nDemonstrated technical leadership, including mentoring engineers, leading cross-functional initiatives, and influencing architecture decisions.\nExcellent debugging, analytical, and problem-solving skills across hardware/software boundaries.\nStrong verbal and written communication skills, including presenting technical strategy to stakeholders and management.\nAbility to work across a geographically dispersed team and deal with ambiguity in a fast-paced environment.Strong debugging, analytical, and cross-functional collaboration skills.\nStrong problem-solving skills and ability to work effectively in a fast-paced, collaborative environment\nStrong verbal and written communication skills\nSelf-motivated team player with the ability to collaborate with team members of varying skillsets\nAbility to work effectively as part of a geographically dispersed team\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Cybersecurity Analyst — Semiconductor IP", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-21", "url": "https://careers.synopsys.com/job/bengaluru/cybersecurity-analyst-semiconductor-ip/44408/102236641056", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nYou are someone who builds trust with product and engineering teams and helps them do security work as part of normal delivery. You listen first, write in clear language, and own your conclusions. You work well with people in different disciplines and locations without needing to be the loudest person in the room.\nYou are practical when information is incomplete. You explain complex topics in simple terms, stay calm when the design changes, and challenge unclear choices in a respectful way. You care about teamwork, follow-through, and leaving work that others can use.\nThis is a full-time role.\nWhat You’ll Be Doing:\nLead threat analysis for semiconductor IP and associated firmware: identify assets, access points, threat scenarios, and attack paths, and recommend controls in the IP versus requirements for the integrator.\nRun security analysis as part of the cybersecurity lifecycle, from planning through design, implementation, verification, and release.\nAdvise product teams on cybersecurity requirements, architecture, and verification so security work is built into the existing development flow.\nAuthor customer-facing security integration guidance that describes the threat landscape, implemented controls, and how customers should integrate the IP.\nReview RTL, architecture, and verification intent against secure-design principles; judge whether a claimed control is implemented and testable; capture integrator recommendations where needed.\nSupport in-field cybersecurity activities for the products you cover, including vulnerability assessment, incident analysis, and security advisories, working with product-team architects and corporate vulnerability response as required.\nFacilitate working sessions with cybersecurity architects and design and verification leads; keep analysis consistent across similar IP classes.\nDeliver analysis incrementally with product teams working in agile sprints: plan security work against the product backlog, adjust scope when the design changes, and keep evidence current at each milestone.\nUse Python to automate analysis, transform inventories and threat-model data, and produce repeatable reports other analysts can run and review.\nUse agentic workflows (AI agents, structured prompts, and human-in-the-loop review) to speed research, first drafts, consistency checks, and routine tasks without handing off ownership of findings.\nRun the job in Jira, Confluence, Git, and GitLab: track analysis and incident work, keep project documentation current, and version work products through merge requests and review.\nThe Impact You Will Have:\nGive product teams threat analysis they can trust and act on without re-deriving the work.\nLeave cybersecurity requirements and verification objectives that design and verification teams can execute.\nProduce integration guidance that customers can follow without a security specialist in the room.\nStrengthen the cybersecurity lifecycle for IP products so security work stays current as the design changes.\nImprove consistency of analysis across similar IP classes through shared working sessions and clear written conclusions.\nHelp the organization respond to in-field issues with clear assessment and practical advisories.\nRaise analysis throughput with Python and agentic workflows without lowering the quality of technical conclusions.\nWhat You’ll Need:\nBachelor’s degree in electrical engineering, computer engineering, computer science, or a related field, or equivalent practical experience. An advanced degree is welcome, not required.\nTypically, 4 or more years in product cybersecurity, embedded security, digital design, digital verification, or a closely related engineering role. Stronger evidence on the required capabilities can offset fewer years. Title (Analyst or Senior Analyst) will match demonstrated depth.\nPractical experience performing threat modeling or threat analysis and risk assessment on real products, not only training exercises.\nAbility to identify assets, attackers, attack surfaces, and attack paths, and to map each path to a mitigation (in-product control or integration requirement).\nComfort working without a single known end-system: analysis must cover representative integration scenarios and state assumptions clearly.\nExperience applying a cybersecurity lifecycle across planning, requirements, design, implementation, verification, and release.\nAbility to turn threat-analysis results into requirements, design guidance, verification objectives, and release evidence.\nHands-on understanding of embedded systems: SoC or MCU integration, firmware, hardware/software interfaces, memory-mapped registers, boot and debug, and on-chip interconnects.\nAbility to reason about hardware-rooted threats and firmware threats, and to read architecture, databooks, and interface specifications with the design team.\nHands-on proficiency as a digital designer or a digital verification engineer. Either path is sufficient.\nAbility to read and discuss RTL (Verilog, SystemVerilog, or VHDL), architecture, interfaces, and register maps with designers and verification leads.\nAbility to judge whether a claimed cybersecurity control is implemented in the design and whether it is verifiable.\nExperience delivering analysis or engineering work inside agile product teams, including re-scoping when product content changes.\nAbility to write and maintain Python for analysis and automation. This is not a software-engineering role. Scripts should be readable and usable by other analysts.\nPractical experience using AI agents and agentic workflows to speed research, drafting, and repetitive analysis, while keeping the human as owner of technical conclusions.\nHands-on use of Jira, Confluence, Git, and GitLab (or an equivalent Git forge) for tickets, documentation, and review.\nClear written and spoken English; able to lead technical sessions with geographically distributed teams.\nWorking knowledge of ISO/SAE 21434 or a comparable product-cybersecurity standard is helpful, as is analog or mixed-signal background, semiconductor IP product experience, vulnerability handling, or applied embedded cryptography.\nWho You Are:\nYou build trust with design teams and keep working relationships strong when the discussion is difficult.\nYou own the technical conclusion. You do not hand off judgment to a tool, a template, or the loudest voice in the room.\nYou write clearly so engineers and customers can use your work without you in the room.\nYou work well with incomplete information and out-of-context IP, and you state assumptions instead of hiding them.\nYou challenge unclear practices in a respectful way and recommend improvements teams can actually adopt.\nYou are collaborative and non-disruptive with product teams, including when you need them to change course.\nYou are structured and detail-oriented, and you keep evidence current as the design changes.\nYou are comfortable with agile change and re-scope analysis without waiting for a late gate.\nThe Team You’ll Be A Part Of:\nYou will join the cybersecurity team that supports Synopsys semiconductor IP products. As an analyst, you are assigned to IP product teams and work in their delivery cadence. You collaborate with digital, analog, mixed-signal, and firmware engineers, and with cybersecurity architects, to complete analysis, guidance, and evidence through the cybersecurity lifecycle. The team works across regions. Your written work products are used by product teams and by customers who integrate the IP.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Manager, Product Cybersecurity — Semiconductor IP", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-21", "url": "https://careers.synopsys.com/job/bengaluru/manager-product-cybersecurity-semiconductor-ip/44408/102236641104", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nYou are a leader who builds trust with product teams, engineers, and the analysts you manage. You listen first, write in clear language, and take ownership of results. You work well with people in different disciplines and locations, and you help others do their best work without needing to be the loudest person in the room.\nYou are practical when information is incomplete. You explain complex topics in simple terms, stay calm when the design changes, and challenge unclear choices in a respectful way. You care about teamwork, growing people, and leaving work that others can use.\nThis is a full-time role.\nWhat You’ll Be Doing:\nLead a team of cybersecurity analysts who support semiconductor IP products: set priorities, assign analysts to product teams, and balance workload across the portfolio.\nSet the direction for threat analysis of semiconductor IP and associated firmware, including assets, access points, threat scenarios, attack paths, and controls in the IP versus requirements for the integrator.\nGuide the team in running security analysis as part of the cybersecurity lifecycle, from planning through design, implementation, verification, and release.\nReview the team’s analysis, requirements, and integration guidance for quality, consistency, and clear assumptions before they reach product teams and customers.\nAdvise product leaders and architects on cybersecurity requirements, architecture, and verification so security work is built into the existing development flow.\nOversee customer-facing security integration guidance that describes the threat landscape, implemented controls, and how customers should integrate the IP.\nGuide the team’s support for in-field cybersecurity activities, including vulnerability assessment, incident analysis, and security advisories, working with cybersecurity architects and corporate vulnerability response.\nCoach and develop analysts: set clear goals, give regular feedback, and plan career growth.\nFacilitate working sessions with cybersecurity architects and design and verification leads; keep analysis consistent across similar IP classes.\nPlan the team’s work with product teams in agile sprints: align security work with the product backlog, adjust scope when the design changes, and keep evidence current at each milestone.\nPromote the use of Python and agentic workflows (AI agents, structured prompts, and human-in-the-loop review) so the team works faster while analysts keep ownership of their findings.\nRun team work in Jira, Confluence, Git, and GitLab: track work and capacity, keep documentation current, and report status to leadership.\nThe Impact You Will Have:\nGive product teams threat analysis they can trust and act on without re-deriving the work.\nBuild a team of analysts who grow in skill, own their conclusions, and deliver steady quality.\nImprove consistency of analysis, risk language, and guidance across similar IP classes.\nLeave cybersecurity requirements and verification objectives that design and verification teams can execute.\nStrengthen the cybersecurity lifecycle for IP products so security work stays current as the design changes.\nHelp customers integrate Synopsys IP with guidance they can follow without a security specialist in the room.\nHelp the organization respond to in-field issues with clear assessment and practical advisories.\nRaise team throughput with Python and agentic workflows without lowering the quality of technical conclusions.\nWhat You’ll Need:\nBachelor’s degree in electrical engineering, computer engineering, computer science, or a related field, or equivalent practical experience. An advanced degree is welcome, not required.\nTen or more years in product cybersecurity, embedded security, digital design, digital verification, or a closely related engineering role, including four or more years leading people or technical teams. Stronger evidence on the required capabilities can offset fewer years.\nExperience managing or leading analysts or engineers: setting priorities, giving feedback, coaching, hiring, and growing people.\nPractical experience performing or reviewing threat modeling, threat analysis, and risk assessment on real products, not only training exercises.\nAbility to judge whether threat-analysis work identifies assets, attackers, attack surfaces, and attack paths, and maps each path to a mitigation (in-product control or integration requirement).\nComfort working without a single known end-system: analysis must cover representative integration scenarios and state assumptions clearly.\nExperience applying a cybersecurity lifecycle across planning, requirements, design, implementation, verification, and release.\nAbility to turn threat-analysis results into requirements, design guidance, verification objectives, and release evidence.\nHands-on understanding of embedded systems: SoC or MCU integration, firmware, hardware/software interfaces, memory-mapped registers, boot and debug, and on-chip interconnects.\nBackground as a digital designer or a digital verification engineer, with the ability to read and discuss RTL (Verilog, SystemVerilog, or VHDL), architecture, interfaces, and register maps with designers and verification leads.\nAbility to judge whether a claimed cybersecurity control is implemented in the design and whether it is verifiable.\nExperience delivering work inside agile product teams, including re-scoping when product content changes.\nWorking ability to read and review Python used for analysis and automation, and to guide analysts on readable, reusable scripts.\nPractical experience using AI agents and agentic workflows to speed research, drafting, and repetitive analysis, while keeping the human as owner of technical conclusions.\nHands-on use of Jira, Confluence, Git, and GitLab (or an equivalent Git forge) for tickets, documentation, and review.\nClear written and spoken English; able to lead technical sessions and communicate with leaders across geographically distributed teams.\nFamiliarity with digital design and verification languages and methods, such as SystemVerilog, UVM (Universal Verification Methodology), and SystemC, and how verification teams use them to test security controls.\nWorking knowledge of ISO/SAE 21434 or a comparable product-cybersecurity standard is helpful, as is analog or mixed-signal background, semiconductor IP product experience, vulnerability handling, or applied embedded cryptography.\nWho You Are:\nYou build trust with product teams, design teams, and your own analysts, and you keep working relationships strong when the discussion is difficult.\nYou grow people. You give honest feedback, share credit, and help analysts take on more responsibility.\nYou own the outcome for your team. You do not hand off judgment to a tool, a template, or the loudest voice in the room.\nYou write and speak clearly so engineers, leaders, and customers can use your work without you in the room.\nYou work well with incomplete information and out-of-context IP, and you state assumptions instead of hiding them.\nYou challenge unclear practices in a respectful way and recommend improvements teams can actually adopt.\nYou are collaborative and non-disruptive with product teams, including when you need them to change course.\nYou are structured and detail-oriented, and you keep evidence current as the design changes.\nYou are comfortable with agile change and re-prioritize the team’s work without waiting for a late gate.\nThe Team You’ll Be A Part Of:\nYou will lead the cybersecurity analysts who support Synopsys semiconductor IP products. Your analysts are assigned to IP product teams and work in their delivery cadence. You and your team collaborate with digital, analog, mixed-signal, and firmware engineers, and with cybersecurity architects, to complete analysis, guidance, and evidence through the cybersecurity lifecycle. The team works across regions. Its work products are used by product teams and by customers who integrate the IP.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Digital Design Architect", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-10-21", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018758", "is_hardware": true, "platform": "oracle", "jd_text": "About TI\n\nTexas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world’s brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We’re committed to building a better future – from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. Put your talent to work with us – change the world, love your job! \n\n \n\nAbout the Job\n\nAre you looking for a career at one of the leading semiconductor companies in the world Texas Instruments (TI) is looking for a Digital Design Engineer to join the team of enthusiastic engineers who develops highly complex mixed signal devices for audio applications with industry leading performance.\n\nThese audio products are truly mixed-signal devices with highly integrated digital circuits such as a DSP core for digital filters and audio signal processing blocks, hardware processing blocks, analog controllers, various serial interfaces (Audio serial interfaces, I2C, SPI) and other digital blocks like clock-generation, registers map, Interrupts etc. \n\nThis is a great opportunity to be part of an established team that’s continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electronics, industrial and automotive markets.\n\n \n\nPosition                : Digital Design Engineer\n\nDomain                : Consumer Audio Amplifiers and Haptics\n\nLocation               : Bangalore\n\nBasic Qualifications: Bachelor's/Master's Degree in EE/ECE\n\nMinimum Requirements:\n\nBachelor’s degree in Electrical/Electronics Engineering.\n\n~8 years of Digital design experience.\n\n \n\nWhat can you expect to learn in this role/Opportunity?\n\nTo work with the best experts in the industry.\n\nTo develop capability to work effectively in a technically challenging fast-paced and rapidly changing environment.\n\nTo innovate on core technology in design methodologies & influence decisions that have wide business impact across many products & teams.\n\nTo work on cutting edge industry leading products.\n\nTo learn overall product development Process and directly influence the features, differentiation & quality of the product.\n\nTo learn and develop business insights, drive open discussions with business & technology leaders and drive decisions impacting product & technology execution.\n\nTo build strong, influential relationships with domain experts.\n\nTo develop good communication, interpersonal skills while interacting with worldwide cross functional experts.\n\nTo learn identifying risks across domains and adapt to support changing priorities.\n\nTo present analysis and conclusions to internal customers and business leaders in a comprehensive and effective manner.\n\nTo work closely with cross-domain experts other engineers and interns.\n\n \n\nBasic Requirement:\n\nStrong digital design fundamentals and basic electrical/electronic engineering concepts.\n\nExperience in building RTL micro architectures development.\n\nHands on experience in RTL coding.\n\nExperience with Verilog/VHDL/System Verilog language.\n\nShould be good knowledge on lint, CDC, RDC, constraint development, synthesis.\n\nGood understanding of digital timing analysis. \n\nExpert in using simulation tools (preferably Cadence).\n\nBasic scripting knowledge using shell/python/perl is preferred. \n\nKnowledge of audio signal chain, I2C, ASI/TDM, memory architecture and FPGA is preferred.\n\nExcellent debugging and problem-solving skill.\n\nGood communication, presentation skills and teamwork.\n\n \n\nPrimary Responsibilities:\n\nDesign and Development of digital logic circuits including signal chain, clocking circuits, fault & interrupt handler, memory management and FPGA.\n\nDetailed documentation preparation and knowledge sharing of design architecture and implementation with other domains along with conducting Arch and design Reviews\n\nWork with analog and firmware design domains on integration of system level specification. \n\nWork closely with other design and systems teams to review/close spec gaps and design bugs, as they arise. \n\nHandle Design QCs like lint, CDC, RDC\n\nDeveloping constraint development and synthesis. \n\nSupport physical design team and work closely on timing closure.\n\nSupport DV and silicon validation team with testplan support, design debugs, root cause analysis and workaround.\n\nReview verification coverage and sign off on waivers. \n\nInnovate & drive new and improved methodologies where needed, work with the EDA team to upgrade tools and flows. \n\nConducting design reviews and creating the necessary design and product documentation. \n\nInteracting with Test/Silicon Validation/Application Engineering team to ensure successful use of products and support customer applications debug/analysis.\n\nExcellent teamwork, adapting to situations and ability to guide, help other team members.\n\nCommunication of design status, issues, and concerns.\n\nQualifications\nPreferred Qualifications:\n\nDemonstrated strong analytical and problem-solving skills.\n\nEffective communication skills to interact with all stakeholders.\n\nAbility to work in teams and collaborate effectively with people in different functions.\n\nStrong time management skills that enable on-time project delivery.\n\nAbility to work effectively in a fast-paced and rapidly changing environment.\n\nAbility to take the initiative and drive for results.\n\nAbility to build strong, influential relationships with cross-functional teams.\n\n \n\nAdded Advantage:\n\nExperience/know-how in Physical design concepts.\n\nExperience in audio signal processing and understanding of audio systems/applications. \n\nExperience in silicon debug along with silicon validation team.\n\n \n\nPreferred Skills/ Experience \n\n~8 years of relevant experience\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "AVV Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-10-21", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018765", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \nAbout Team:\nASM Auto Group develops safety-compliant automotive MCUs for EV, HEV, traction inverters, onboard chargers, BMS, and body and chassis control. We are at a pivotal moment in automotive technology, and this role offers a chance to work on cutting-edge MCUs with real-world impact. If you want to solve complex technical challenges in fast-growing segments, we encourage you to apply.\n\nPosition Overview:\nWe are seeking engineers with 2-5 years of experience to independently own functional validation of MCU peripherals and subsystems, spanning pre-silicon (RTL simulation, QuickTurn/Palladium/ZeBu emulation, FPGA prototyping) and post-silicon (functional bring-up and validation on silicon).\nYou will work closely with Architecture, Design, and Firmware teams to ensure robust, competitive automotive devices.\n \nKey Responsibilities:\nOwn functional validation of Automotive peripherals and communication interfaces\nDevelop requirements-based test plans, directed tests, and negative/corner-case scenarios\nDevelop firmware test suites and automation in Python and C\nDebug hardware/software interactions across firmware, RTL waveforms, emulation, and silicon\nExecute first-silicon functional bring-up and peripheral functional tests\nMaintain regressions, track coverage, and close functional gaps\nExecute performance and benchmarking tests on assigned peripherals and subsystems\nReproduce customer-reported issues and perform root-cause analysis\nVerify fixes for customer-reported issues\nProduce test plans, validation reports, and defect root-cause analyses\nCoordinate with RTL designers and architecture teams on design issues\n\nQualifications\nMinimum requirements:\nBachelor's degree in Electrical Engineering, ECE, Computer Engineering, or related field\n2-5 years of engineering experience working with silicon design and/or validation\nExperience with digital/embedded design on emulation/FPGA platforms/RTL simulation\n \nPreferred Qualifications:\n \nWork experience with ARM architecture\nStrong embedded C (drivers, interrupts, DMA, register-level programming)\nPython for test automation and log/result analysis\nHands-on lab experience with JTAG/SWD debuggers and basic bench tools for functional debug\nAdvanced knowledge of digital logic\nAutomotive protocols: CAN FD and LIN; Ethernet MAC fundamentals\nWorking knowledge of ISO 26262 functional safety concepts\nGit and strong technical documentation skills\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Lead AVV Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-10-21", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018766", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \nAbout Team:\nASM Auto Group develops safety-compliant automotive MCUs for EV, HEV, traction inverters, onboard chargers, BMS, and body and chassis control. We are at a pivotal moment in automotive technology, and this role offers a chance to work on cutting-edge MCUs with real-world impact. If you want to solve complex technical challenges in fast-growing segments, we encourage you to apply.\n\nPosition Overview:\nWe are seeking an experienced AVV technical leader with 5+ years of pre-silicon and post-silicon functional validation experience to own subsystem-level validation strategy for automotive MCUs. You will define functional validation methodology, lead complex root-cause investigations, drive functional bring-up on silicon, and make evidence-based silicon readiness recommendations. You will work as a technical peer with Architecture, Design, RTL Verification, and Firmware teams.\n\nKey Responsibilities:\nOwn functional validation strategy and sign-off for complex subsystems (e.g., Ethernet MAC, functional safety, clock/reset/power, multicore interactions)\nDefine requirements-to-test traceability, functional coverage closure criteria, and sign-off readiness\nArchitect reusable validation frameworks spanning emulation platforms and silicon test environments\nLead first-silicon functional bring-up and silicon functional test execution\nLead complex root-cause analysis across firmware, RTL, emulation models, and silicon\nValidate cross-peripheral interactions with DMA, interrupts, clock switching, and low-power transitions\nLead fault-injection campaigns and functional safety validation evidence (ISO 26262)\nDefine pre-silicon to post-silicon correlation and test reuse strategy\nArchitect and maintain automation and CI/CD-integrated regression infrastructure\nDefine and own performance and benchmarking strategy, including throughput, latency, and timing-margin target.\nLead resolution of customer-reported issues through reproduction and root-cause analysis\nDefine fix or workaround recommendations for customers and drive them to closure\nLead validation reviews and provide sign-off recommendations\nMentor engineers and drive continuous improvement in methodology and tooling\n\nQualifications\nMinimum requirements:\nBachelor's degree in Electrical Engineering, ECE, Computer Engineering, or related field\n5+ years of engineering experience working with silicon design and/or validation\nExperience with digital/embedded design on emulation/FPGA platforms/RTL simulation\n \nPreferred Qualifications:\n \nWork experience with ARM architecture\nAdvanced embedded C and firmware architecture knowledge\nMCU/SoC architecture understanding (multicore, coherency, boot, power domains)\nExpert-level peripheral validation, including complex interactions and error recovery\nEmulation platform experience (QuickTurn, Palladium, ZeBu) and test infrastructure design\nRTL and waveform debugging for SoC-level issues\nDeep understanding of ISO 26262, AUTOSAR, and CAN FD / LIN / Ethernet\nFunctional safety subsystem validation and safety-case evidence\nComplex DMA and bus (arbitration, ordering, timeout) validation\nSystemVerilog and advanced RTL debugging\nTrack record of building and mentoring validation teams, or publishing technical work\nExcellent technical communication and documentation skills\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Analog IC Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-10-21", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018810", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\n This is a great opportunity to be part of an established team that's continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electronics, mobile computing and communications.\n\nIn this role, responsibilities may include:\n\nLead an Analog IC design team with product ownership and responsibility from definition to release to manufacturing\n\nDirect, guide and participate in activities of a research or technical design function responsible for designing, developing, modifying and evaluating electronic parts, components, integrated circuits for a variety of applications\n\nMake assignments for team members, providing design guidance as needed, developing schedules and monitoring progress throughout the project\n\nEvaluate intermediate and final results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout\n\nCollaborate with Design Verification teams during the pre-PG phase of a project to ensure completion of all technical tasks before PG\n\nWork with systems engineers, application engineers and marketing to prepare product briefs, datasheets, application notes and assisting in the definition of the product to meet customer needs as well as contributing to roadmap formulation and new concept creation\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nInterface and lead discussions with the customer and/or TI field sales/field applications teams to understand customer designs, problems and support as required\n\nActively participate in hiring, developing and evaluating personnel to ensure efficient operation of the organization and growth of the individuals into leader\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in Electrical Engineering\n\nXX years of relevant experience\n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "ASIC Digital Design, Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-21", "url": "https://careers.synopsys.com/job/bengaluru/asic-digital-design-engineer/44408/102251697408", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nYou are an early-career engineer ready to make your mark in semiconductor design. You have spent your academic years drawn to digital design that requires proof, not just simulation. When you see a spec, you think about corner cases and what could break. You have written Verilog or SystemVerilog, debugged logic that did not behave as expected, and you are comfortable in a Unix terminal. Formal verification might be new to you, but the rigor makes sense. You learn by doing, ask questions when stuck, and you do not mind being the person who finds the bug everyone else missed.\n\nWhat You'll Be Doing\nLearn the latest formal verification methodology from experts and apply your learnings to live projects.\nWork with a team of seasoned FV engineers and execute validation as per defined plans.\nSupport quality improvements and contribute insights that help enhance verification tool capabilities.\nWrite and refine assertions in SystemVerilog Assertions (SVA) to capture design intent and uncover edge-case failures.\nScript verification flows using Python, Perl, or Tcl to automate repetitive tasks and improve team productivity in Unix/Linux environments.\n\nThe Impact You Will Have\nHelp catch critical design bugs before tapeout that would otherwise cost months and millions to fix in silicon.\nContribute to the quality and reliability of Synopsys IP and EDA tools that power semiconductor development across the industry.\nAccelerate verification closure on complex designs by applying formal methods that simulation alone cannot cover.\nStrengthen the formal verification methodology at Synopsys by bringing fresh perspectives and identifying gaps in existing flows.\n\nWhat You'll Need\nBachelors or Master’s degree in Electronics, Electrical, Instrumentation, or a related engineering discipline\n0 to 2 years of experience in digital design, verification, or related semiconductor work (internships, projects, and coursework count).\nStrong understanding of computer architecture and digital design fundamentals including state machines, pipelining, and timing.\nHands-on experience with hardware description languages, Verilog or SystemVerilog preferred.\nProficiency in at least one scripting language such as Python, Perl, or Tcl, and comfort working in Unix or Linux environments.\nSolid academic performance with relevant coursework or project work in VLSI, digital design, or verification.\nExperience with formal verification tools, assertion languages, or model checking is a strong plus.\n\nWho You Are\nYou can look at a block diagram or RTL code and start asking the right questions about what could go wrong, not just what is supposed to work.\nYou are comfortable learning new tools and methodologies on the job without needing everything explained upfront, you read documentation, try things, and ask targeted questions when you are stuck.\nYou communicate clearly when you find something, whether it is a bug, a gap in coverage, or a script that is not working the way it should.\nYou are detail-oriented enough to track down a single-bit logic error in a complex design without losing sight of what the block is supposed to do.\n\nThe Team You'll Be Part Of\nYou will join a focused team at Synopsys dedicated to advancing formal verification methodologies and delivering proven IP and EDA solutions. You will collaborate with experienced formal verification engineers and design experts who are committed to pushing the boundaries of what formal methods can achieve. The team values rigorous thinking, continuous learning, and clear communication, creating an environment where your growth is supported.\n\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Digital Design Verification Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-10-21", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010580", "is_hardware": true, "platform": "oracle", "jd_text": "We are at a pivotal moment where technology is rapidly evolving, and we have some exciting opportunities within our MCU organization that place us right at the center of this transformation. \n\nOur current work is focused on developing solutions for high-growth markets such as AI-driven data centers and emerging domains like humanoid systems. These areas are shaping the future of computing, automation, and intelligent systems, and offer a unique chance to work on cutting-edge technologies with real-world impact.\n\n If you are passionate about solving complex technical challenges and want to contribute to innovations in these fast-growing segments, I encourage you to come forward and apply. This is an opportunity to be part of a journey that is not only technically rewarding but also strategically significant.\n\nLooking forward to seeing many of you take this step\n\nQualifications\nMinimum requirements:\n\n5 + years of extensive verification experience on high‑performance SoCs, preferably MCUs or wireless connectivity products.\n\nDeep expertise in SystemVerilog/UVM and major simulation platforms; proven track record of delivering high‑coverage verification solutions.\n\nStrong background in power‑aware verification, mixed‑signal (AMS) verification, and hardware emulation (FPGA, Palladium, etc.).\n\nDemonstrated ability to lead coverage‑driven verification campaigns and meet aggressive schedule targets.\n\nAdvanced scripting/automation skills (tcl, perl, python, Bash) and familiarity with CI/CD for verification flows.\n\nExcellent communication and stakeholder‑management skills; ability to build strong relationships across functional groups and global sites.\n\nProven experience mentoring engineers and driving methodology improvements.\n\nPreferred qualifications:\n\nExperience with System Verilog\n\nDemonstrated strong analytical and problem solving skills\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nStrong time management skills that enable on-time project delivery\n\nDemonstrated ability to build strong, influential relationships\n\nExperience with TI internal verification platforms or custom IP verification frameworks\n\nPublications or conference presentations on verification methodologies.\n\nHands‑on involvement with silicon bring‑up and debugging on silicon prototypes.\n\nKnowledge of industry standards (IEEE 1800‑UVM, IEEE 1500, IEEE 1149.1) and low‑power verification techniques.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Senior Design Verification Engineer", "company": "Lattice", "location": "Manila, Philippines", "date_posted": "2026-10-20", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Manila-Philippines/Senior-Design-Verification-Engineer_R-103530", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nJob Summary: \n \nLattice Semiconductor is seeking a Senior Design Verification Engineer to join the Silicon team.  This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn and grow.\n\nAccountabilities\nDevelop comprehensive verification plans, clear metrics and continuously measure progress against the plan throughout the project\nVerify design blocks, sub systems and full chip using assertion-based verification, formal verification, directed tests and randomized tests\nUnderstand the specifications, use cases and develop System Verilog and ‘C’ based testbenches in UVM environment\nDesign and develop testbench components such as Universal Verification Components, BFMs and verification tools\nDefine and design verification regression environment\nPerform Functional coverage, RTL code coverage, assertion coverage, and gate level simulations\nCollaborate with design engineers, IP developers and SW developers to deliver high quality SoC verification on aggressive time schedules\nDevelop best practices and world class methods for SoC verification\nundefined\n \nRequired Skills\n6-10 years Digital Design Verification Related Experience\nBachelor or Masters Degree in Computer Science, Computer Engineering, Electronics and Electrical Engineer\nSkill in debugging and analyzing complex digital design\nExperience in HDL and HVL Languages and Methodologies\nExperience in ASIC/FPGA/SoC verification or development cycle\nExperience in simulation tools like Cadence IES/XCELIUM, Synopsys VCS or Mentor's Questa\nHands-on experience in Python, Perl or Shell Scripting, TCL and Make.\nStrong communication, analytical and documentation skills and ability to interface with other groups/site\nStay up to date on industry trends and direction of verification technology development\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nPhilippinesLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Senior Staff Device Engineer", "company": "Lattice", "location": "Taipei, Taiwan", "date_posted": "2026-10-20", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Taipei-Taiwan/Senior-Staff-Device-Engineer_R-103353", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\n\nWe are seeking a Senior Staff Device Engineer with broad technical expertise spanning semiconductor technology, device physics, circuit analysis, CAD tools, and yield engineering. This role focuses on diagnosing product yield and failure issues from the circuit level down to the transistor and fab process level, driving root cause analysis and corrective actions, and optimizing process conditions for robust yield, reliability, and NPI success. The engineer will collaborate closely with Design, Layout, Product Engineering, and Foundries, and will advise Design and Layout teams on design changes that improve yield and reliability.\n\nResponsibilities\n\n1. Device Engineering & Circuit Analysis\nAnalyze circuit failures and yield anomalies, tracing and isolating failure behavior to the transistor level or specific fab process steps using CAD navigation and circuit/layout knowledge.\nStudy Process Design Rules, DRC, DFM guidelines, device construction, transistor characteristics, and SPICE model corner coverage to proactively identify structural or layout-dependent weak points.\nPerform transistor characterization by designing test keys (SLM, test chip design) for advanced transistor characterization and monitoring of reliability limits.\nModify Design Rule Checks (DRC) or collaborate with CAD teams to screen specific wafer lots for weak layout features susceptible to process drift.\nWork closely with Product Engineers to refine or modify test scripts when narrowing down failure root causes.\n\n2. Yield Engineering & Sustaining\nOwn sustaining activities including yield improvement, process window optimization, and SPC monitoring on production silicon.\nAnalyze WAT, inline, and final test data to identify process drift, yield loss mechanisms, and reliability risks; drive root cause and corrective action with foundry process owners.\nCorrelate complex electrical failure data (sort, bitmap, and customer returns) with WAT data to pinpoint process shifts.\nPerform product process corner and design window studies to optimize process targets.\nCollaborate with Design, Product Test, and Failure Analysis teams to debug and root cause systematic yield issues.\n\n3. Failure Analysis & Fault Isolation\nSupport fault isolation by translating complex electrical test failures (sort, bitmap, customer returns) into precise layout-level regions for localized de-layering, nanoprobing, SEM, and TEM analysis.\nPerform product failure diagnosis for yield debug and failure localization, including bitmap analysis.\nAnalyze structural PFA cross-sections, material anomalies, and physical defects alongside transistor characterization data to identify fab-side or layout-dependent root causes.\nCoordinate failure analysis efforts across internal teams and foundry FA resources.\n\n4. Quality & Customer Support\nSupport customer-facing quality escalations including 8D and CAR responses.\n\nRequirements\nM.S. or Ph.D. in Electrical Engineering, Microelectronics, Materials Science, or a related field, with 10+ years of relevant experience in a fabless semiconductor or foundry ecosystem.\nDevice Physics & Reliability: Strong knowledge and hands-on experience in transistor-level characterization, compact modeling, and semiconductor reliability mechanisms (e.g., HCI, NBTI, TDDB).\nCircuit & Layout CAD: Full proficiency in industry-standard CAD tools (e.g., Cadence Virtuoso, Synopsys) for schematic capture, layout verification (DRC/LVS), and physical design analysis.\nDesign for Manufacturing (DFM): Proven ability to identify physical weak points in product layouts and directly link them to specific fab manufacturing constraints.\nDemonstrated experience with WAT parametric analysis, yield engineering, SPC, failure diagnosis and analysis coordination, and process window optimization.\nUnderstanding of semiconductor product test flow and ability to engage effectively with manufacturing test and product engineering teams.\nFamiliarity with Lattice FPGA architecture or programmable logic products a plus.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nTaiwanLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Senior Staff, Emulation Engineer", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-10-20", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Senior-Staff--Emulation-Engineer_2604903", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nThe Connectivity Business Unit at Marvell is at the forefront of delivering high-performance silicon for the world's most demanding data infrastructure, spanning Optical DSPs, high-speed Ethernet PHYs, and AEC/AOC enablement devices. Within the BU, the Pre-Silicon Emulation team plays a critical role in program execution—bridging RTL design and real-world system behavior before a single chip is taped out. Our team owns emulation model development, test execution, and system-level debug across Marvell's emulation platforms (Palladium, Veloce, Zebu), enabling early firmware bring-up, hardware/software co-validation, and risk reduction on the path to silicon. We work closely with design, verification, firmware, software, and post-silicon teams to ensure emulation is a productive, schedule-driving resource—not a bottleneck. If you thrive on solving complex technical problems at the intersection of hardware and software, and want your work to directly impact the success of next-generation connectivity silicon, we'd love to hear from you.\nWhat You Can Expect\nExecute emulation model bring-up, test development, and debug for connectivity silicon programs, including ODSP, high-speed Ethernet PHYs, and AEC/AOC enablement devices, on platforms such as Palladium, Veloce, and Zebu.\nWork with design, validation, and firmware teams to understand emulation hardware and software requirements, and implement platform configurations, transactors, speed bridges, protocol adapters, and firmware/software stacks.\nEngage with EDA and emulation hardware vendors to resolve platform, tooling, and model issues and maintain a productive emulation environment.\nDevelop and maintain HW/SW enablement flows and scripts to support RTL validation and improve emulation model usability for firmware, driver, and system software development.\nCollaborate with pre-silicon validation, design, firmware, and post-silicon teams to identify and resolve emulation bottlenecks and improve validation coverage.\nBuild and maintain automation scripts and infrastructure to improve emulation environment productivity, reliability, and utilization within assigned programs.\n\nWhat We're Looking For\nMinimum Requirements\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 7+ years of relevant experience, or a Master's/PhD with 3+ years of experience.\nHands-on experience with one or more SoC emulation platforms (Palladium, Veloce, Zebu), including building and maintaining emulation models for SoC designs.\nBackground in test planning, simulation, and debug in Verilog/SystemVerilog environments.\nExperience with SoC development flows, emulation-based debug, and system-level validation.\nScripting and automation skills using Python, Perl, Tcl, and/or UNIX shell.\nAbility to collaborate effectively with cross-functional teams including design, validation, firmware, and vendor partners.\nGood to Have\nExperience with emulation of networking devices or mixed-signal designs, including systems containing PHY or Layer-2/Layer-3 functionality.\nExposure to connectivity-focused silicon, such as:\nOptical DSPs (ODSP)\nHigh-speed Ethernet PHYs\nAEC/AOC enablement devices\nFamiliarity with firmware or software bring-up using emulation platforms.\nExperience contributing to or improving emulation infrastructure within a project or product line.\n \n\nThis role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.\nAdditional Compensation and Benefit Elements\nWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\n\nInterview Integrity \nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\n\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\n\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n\n#LI-RV1", "jd_status": "stored"}, {"title": "Principal DFT design Engineer", "company": "onsemi", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-10-20", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506884", "is_hardware": true, "platform": "oracle", "jd_text": "Principal / Sr Principal DFT design Engineer \n\nExp : 10-14 Years\n\nWe are seeking a skilled Design for Test (DFT) Principal / Sr Principal / Architect/Lead/Manager to join our team. This role is pivotal in ensuring the testability and manufacturability of our ASIC/SoC products designed for the automotive, Industrial & Consumer applications. The ideal candidate will have extensive experience in DFT methodologies and will lead a team of engineers to develop robust test strategies that meet industry standards.\n\nResponsibilities\nDFT Strategy Development: Design and implement DFT methodologies for ASIC/SoC products, focusing on automotive/industrial/consumer applications to ensure high quality and reliability.\n\nArchitecture Design: Collaborate with hardware and software teams to integrate DFT features into the product architecture, ensuring compatibility with testing standards.\n\nTeam Leadership: Lead & manage a team of DFT engineers, providing mentorship and technical guidance to enhance their skills and capabilities.\n\nTest Planning: Develop comprehensive test plans, including ATPG, BIST, and scan insertion strategies, to optimize fault coverage and reduce test costs.\n\nCollaboration: Work closely with design, validation, test and manufacturing teams to align DFT strategies with overall product goals and requirements.\n\nQuality Assurance: Establish metrics and benchmarks for DFT processes, and ensure compliance with automotive industry standards (e.g., ISO 26262).\n\nTool Development: Evaluate and implement DFT tools and methodologies to improve test efficiency and effectiveness.\n\nContinuous Improvement: Stay updated with industry trends and technologies in DFT and automotive testing, driving innovation within the team.\n\nQualifications\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.\n\n10 - 15+ years of experience in DFT for ASIC/SoC design, with a strong background in automotive applications.\n\nProven experience leading DFT teams and managing complex projects.\n\nExperience in post silicon debug, yield improvement and On-field failure (EFAR) debug.\n\nIn-depth knowledge of DFT techniques such as scan design, boundary scan, BIST, and fault simulation.\n\nFamiliarity with automotive industry standards and regulations (e.g., ISO 26262).\n\nProficiency in using DFT tools and EDA software.\n\nStrong problem-solving skills and ability to work collaboratively in a fast-paced environment.\n\nExcellent communication skills, both verbal and written.\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Software Engineer - Jira Workflow & Automation Engineering", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-10-20", "url": "https://careers.arm.com/job/bengaluru/software-engineer-jira-workflow-and-automation-engineering/33099/102199045568", "is_hardware": true, "platform": "talentbrew", "jd_text": "Role Overview\nAs a Senior Software Engineer, you will work closely with the Technical Lead to develop and support engineering workflow solutions built on the Atlassian platform. You will chip in to JIRA workflow automation, dashboard development, data analytics, and engineering process improvements that enable efficient execution across semiconductor development teams.\nThis role provides an opportunity to gain experience working with multi-functional engineering organizations while building software solutions that improve engineering productivity and execution visibility.\nResponsibilities:\nJIRA Configuration & Automation\nSupport the implementation of JIRA workflows, issue types, screens, automation rules, and project configurations. Assist in maintaining engineering processes, defect tracking, and workflow standardization under the guidance of the Technical Lead.\nSoftware Development\nDevelop scripts, utilities, and automation using Python and SQL to extract, validate, and process engineering data from Atlassian databases and REST APIs. Chip in to custom integrations with engineering tools and reporting systems.\nDashboard & UI Development\nDevelop and maintain web-based dashboards and user interfaces that visualize project health, engineering metrics, defect trends, and execution status. Work with modern web technologies to enhance usability and user experience.\nData Analytics\nAssist in building reporting pipelines, generating engineering metrics, validating data quality, and creating dashboards that provide actionable insights for engineering and program teams.\nCollaboration\nWork with Design, Verification, Implementation, Validation, Power, Performance, Software, and Program Management teams to understand workflow requirements, support issue resolution, and continuously improve engineering processes.\nRequired Skills and Experience :\n2+ Year of relevant experience.\nBachelor’s degree or equivalent experience in Computer Science, Electronics, Information Technology, or a related field.\nGood programming skills in Python and SQL.\nBasic understanding of databases, REST APIs, and software development practices.\nFamiliarity with web technologies such as HTML, CSS, JavaScript, React, or similar frameworks.\nExposure to JIRA and Confluence is desirable.\nStrong analytical, problem-solving, and communication skills.\nWillingness to learn enterprise workflow automation and engineering process development.\n“Nice To Have” Skills and Experience :\nKnowledge of Agile development methodologies.\nBasic understanding of the semiconductor or SoC development lifecycle.\nExposure to PostgreSQL, Git, Flask/FastAPI, or similar technologies.\nInterest in data visualization, dashboards, and engineering analytics.\nIn Return:\nJoining Arm means becoming part of a collaborative engineering community where you’ll be supported throughout your career. We invest in learning, mentoring, and professional development so you can continue building your technical expertise while working on technology that powers billions of devices worldwide.\nYou’ll have opportunities to:\nLearn from extraordinary engineers across hardware and software.\nWork on latest SoC and low-power technologies.\nBuild software, automation, and data solutions used across Arm engineering.\nGain experience across the complete silicon development lifecycle.\nGrow your career through technical mentoring, training, and multi-functional collaboration.\n#LI-KR2\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Physical Design Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-10-20", "url": "https://careers.arm.com/job/bengaluru/physical-design-engineer/33099/102190154656", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview:\nAs a part of Arm's Solutions Engineering group we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance, and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is the development of comprehensive implementation and analysis methodologies.\nResponsibilities:\nTiming constraints development and validation for functional and test modes\nTiming analysis and closure responsibilities at block/subsystem level\nECO generation and tracking to closure by collaborating with PD, Design, Constraint team and other partners\nRequired Skills and Experience :\nBachelor’s or master’s degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields.\nExperience in performing timing closure at SoC level and block level\nHands-on experience with industry leading STA and ECO generation tools(PrimeTime, Tempus, Tweaker)\nIP integration and timing signoff\nStrong data analysis and presentation skills\nWell versed with TCL/PERL or Python\nWork experience of 2-4 years in STA closure and Signoff methodologies\nStrong Communication and Problem-Solving Skills\n \nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Lead DFT Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-19T05:44:00+00:00", "url": "https://global-external-amd.icims.com/jobs/94228/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. Lead DFT ENGINEER THE ROLE: As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning PREFERRED EXPERIENCE: Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.) Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR5 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "SoC Physical Design", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-19T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721336334", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nExperience:3+ Years\nLocation: Bangalore\n\nJob Responsibilities:\nLead end-to-end physical design implementation for large-scale SoCs and complex subsystems, driving projects from architecture definition to successful tapeout.\nOwn full-chip and subsystem physical design strategy including Floorplanning, Power Planning (PDN), Placement, CTS, Routing, Timing Closure, Signal Integrity, and Physical Verification.\nDrive PPA (Performance, Power, Area) optimization and signoff closure across advanced process nodes.\nDefine and enhance physical design methodologies, automation flows, and best practices to improve design efficiency and quality.\nLead cross-functional collaboration with Architecture, RTL, STA, DFT, Package, CAD, Technology, and Product Engineering teams to achieve aggressive silicon schedules.\nResolve complex design challenges involving timing convergence, congestion, IR/EM, noise, reliability, and manufacturability.\nProvide technical leadership during tapeout planning and execution, ensuring high-quality silicon delivery.\nMentor and guide junior engineers, driving technical excellence across the organization.\nInfluence future design methodologies and contribute to strategic technology roadmap decisions.\n\nRequired Skills\n3+ years of hands-on experience in ASIC/SoC Physical Design with proven success across multiple tapeouts.\nDeep expertise in Floorplanning, Power Delivery Networks, Placement, CTS, Routing, Timing Closure, Signal Integrity, IR/EM Analysis, and Physical Verification.\nStrong understanding of advanced signoff methodologies including STA, SI, Power Integrity, Reliability, DRC/LVS, ERC, PERC, and ESD verification.\nExtensive experience with industry-standard EDA tools such as Innovus, ICC2/Fusion Compiler, PrimeTime, Tempus, Calibre, RedHawk, Voltus, and related signoff tools.\nProven experience leading physical design execution on advanced technology nodes (5nm, 3nm, or equivalent).\nStrong expertise in low-power design methodologies, power-aware implementation, and multi-voltage designs.\nDemonstrated ability to drive technical decisions, solve complex design challenges, and influence cross-functional teams.\nExcellent leadership, communication, and stakeholder management skills.\n\nPreferred Qualifications:\nExperience in high-performance CPU, GPU, AI/ML, Mobile, Networking, Datacenter, or Multimedia SoCs.\nDemonstrated ownership of full-chip physical design and successful delivery of complex SoCs to production.\nExperience driving methodology development, flow automation, and design productivity improvements.\nPrior experience leading and mentoring teams of Physical Design engineers.\nCandidates from leading semiconductor product companies are strongly preferred.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "PDN Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-19T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720713231", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nSign-off Ownership:Own full-chip and block-level static/dynamic IR drop and signal/power electromigration sign-off. \nOwn die plus interposer analysis, die plus interposer plus pkg analysis.\nShould have expertise in handling vector based IR signoff and vector less signoff in different modes\nDrive root-cause debugging for voltage, EM violations and collaborate with physical design (PD) teams on floorplanning and power grid fixes.\nOwn power estimation and signoff on Primepower and Joules on different use cases\nShould have knowledge of CPM generation on different use cases\nUnderstand Mixed signal IP requirements and derive metrics for signoff\n \n\nFlow Development:Define and maintain robust EMIR methodologies using standard EDA tools like Ansys RedHawk-SC, or Cadence Voltus. \nWork on enhancing flow and methods for faster convergence and covering critical gaps with changing signoff trends.\n\nCross functional: Support chip-package-system (CPS) integration and work alongside silicon package and interposer teams. \nWork closely with PnR on fixes needed for EMIR violations and left shift strategy for correct by construction methods\nWork with DFT teams to understand impact of DFT strategy on EMIR, assess/fix impact on IR from DFT patterns, provide guidelines for toggling activity in DFT modes, provide power estimation to ATE and board testing teams.\nWork proactively with EDA vendors to get resolution on Tool issues, track critical issues impacting project, initiate and track topics of long term and future interests.\nWork with flow teams to integrate new methods and fixes in to the flow that are impacting ongoing projects. Initiate work flows for long term and future interests.\n\nQualifications & Requirements\nExperience: 5+ years of relevant semiconductor industry experience, with proven background in power integrity sign-off.\nTechnical Skills: Advanced expertise in RedHawk_SC, Voltus, PTPX alongside strong scripting proficiency (Python/TCL). Should have deep knowledge in EMIR domain. Should have good knowledge of adjacent domains like STA and inter-operation with those domains.\nEducation: Bachelor’s or Master’s degree in Electrical Engineering, VLSI, or a related electronics discipline. \n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Camera IP Verification - Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-19T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720163802", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nCandidate will be responsible for IP Level Verification of Qualcomm Spectra Camera Sub Systems Modules for next gen Qualcomm product portfolio. This role will require the candidate to understand details of the camera signal processing modules, verify them at module & subsystem level for enhanced features. Engineer should independently be able to own the verification of IP level modules end to end with continuous enhancements and collaborate with IP Verification, Design and System leads.\n\nNecessary skills/experience:\n• 3+ years of experience in RTL design verification using SystemVerilog/UVM and industry-standard simulation tools (Mandatory)\n• Experience in power aware simulation is a big plus\n• Experience on camera verification is a big plus\n• Expertise in Coverage closure , RTL debug skills\n• Expertize in SV – UVM, Assertions based verification, DPI\n• Familiarity in Firmware/emulation (ex: Veloce) based verification , GLS\n• Familiarity with bus protocols like AHB, AXI, ARM based system architecture\n• Experience with Perl, Python, or similar scripting language\n• Excellent problem solving skills & Verification aptitude\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "BT - Design Verification Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-19T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720255088", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nQCT's Bangalore Wireless R&D Bluetooth HW team is looking for experienced Wireless HW design verification engineers to work on Qualcomm’s best in class chipsets for mobile phones, wearables and IOT. Candidate will be working with ASIC designs on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, emulation, GLS and Formal techniques. The role also requires deep understanding of the Bluetooth Hardware Architecture. Candidate will require close interactions with Global Design, Systems, SoC, Validation and FW teams for design convergence and required to work with minimal supervision. Candidate must be able to take ownership of IP/Block/Sub-System verification. Incumbent will be analyzing HW design spec and develop a verification test plan/strategy for it, breaking down the work for new features, perform feasibility studies, estimate effort and mitigate risk. The role also required the candidate to mentor new joiners and less experienced colleagues. The candidate will work with design team on RTL debug during Pre-silicon HW development phase.\nSkills/Experience:\n3 years to 6 years of strong experience in design verification\nStrong knowledge of HDLs like Verilog, System Verilog\nProven experience of writing efficient constraint random tests\nProven experience of building or maintaining a medium to complex SV/UVM environments\nStrong debugging and analytical skills and independent problem solving ability\nProficient in debugging RTL/TB issues using Verdi or similar tools\nDemonstrate good judgment in selecting methods and techniques for obtaining solutions\nStrong communication skills, both written and verbal, with ability to evaluate and create test plans detailing complex features and relationships\nBachelor’s or Master’s Degree in Engineering in Electronics, VLSI, Communications or related field\nMinimum Qualifications:\nBachelor’s Degree in Engineering in Electronics, VLSI, Communications or related field\n6 months of VLSI industry experience in verification\nPreferred Qualifications:\nExposure to Bluetooth/BLE Technologies\nKnowledge on scripting languages such as Perl and(or) Python\nSkills:\nFunctional Verification, Functional/Code Coverage, SystemVerilog Assertions, Universal Verification Methodology (UVM), Verification IP (VIP) Integration, SoC Integration, Formal checks\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Platform Hardware design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-19", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Platform-Hardware-design-Engineer_JR0288292", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nPosition Overview:\nAs a Platform Hardware Design Engineer, you will contribute to the end-to-end development of advanced platform hardware, translating platform level requirements into circuit and component level specifications and ultimately into high quality board designs.\nYou will work across the hardware development lifecycle, including architecture and requirements definition, component selection, schematic design, PCB implementation, design reviews, board fabrication and assembly support, power-on, bring-up, debug, validation, and delivery.\nThis is a hands-on engineering role for candidates who enjoy solving complex hardware problems and working across disciplines to turn system requirements into reliable, manufacturable hardware.\n\nOur Business Group\nYou will be joining the Silicon and Platform Engineering Group (SPE), an organization at Intel committed to advancing Intel's mission of delivering world class silicon and platform solutions. The group focuses on developing integrated systems that align with customer needs and support Intel's broader goals of leadership in technology innovation. SPE collaborates across diverse domains to ensure Intel platforms meet performance, reliability, and scalability requirements.\nOur work sits at the intersection of silicon, board hardware, firmware, validation, signal and power integrity, mechanical and thermal engineering, PCB technology, manufacturing, and system integration.\nOur hardware engineers have a broader responsibility than executing an individual design. They help establish platform architecture, guide implementation, identify and qualify appropriate hardware solutions, provide technical leadership during board power-on and debug, and lead resolution of schematic, layout, SI/PI, and hardware issues.\n\nKey Responsibilities\nPlatform and Board Design\n\t• Translate platform level requirements into circuit level, component level, and PCB design requirements.\n\t• Design and develop complex platform boards incorporating high speed digital, analog and mixed-signal circuitry considering board/system-level design tradeoffs during development.\n\t• Own schematic development for assigned boards, subsystems, and functional blocks, including component definition and selection.\n\t• Develop electrical solutions associated with processors/SoCs, FPGAs, memory, high-speed interfaces, voltage regulators, clocks, resets, control interfaces, and platform-management functions.\n\nPCB Design and Implementation\n\t• Define PCB implementation requirements, including component placement, critical interfaces, routing rules, stack-up considerations, and other layout constraints.\n\t• Work closely with PCB layout engineers and guide board implementation from feasibility through design release/tape-out while meeting multidisciplinary platform requirements.\n\t• Review complex multilayer PCB designs for electrical performance, signal integrity, power integrity, manufacturability, and system requirements.\n\t• Apply high speed transmission-line and layout principles to critical interfaces.\n\nPower, Signal Integrity and Platform Considerations\n\t• Apply signal integrity and power integrity principles during board architecture, schematic design, component selection, and PCB implementation.\n\t• Design and review power delivery architectures, voltage regulation, sequencing, power budgeting, and platform power distribution.\n\t• Work with SI/PI specialists to analyze critical high speed interfaces and power delivery networks and incorporate analysis results into board design.\n\t• Understand platform level trade-offs involving electrical performance, power, thermal constraints, PCB implementation, component availability, and manufacturability.\n\nBoard Bring-up, Validation and Debug\n\t• Develop and execute board power-on, bring-up, validation, and characterization plans.\n\t• Collaborate with architects, hardware engineers, validation engineers, firmware engineers, technicians, and other specialists during platform power-on and debug.\n\t• Troubleshoot board and system level problems and perform systematic root cause analysis.\n\t• Use laboratory equipment such as oscilloscopes, digital multimeters, logic analyzers, and other measurement equipment for electrical characterization and debug. Analyze failures, determine root causes, implement corrective actions, and drive issues to technical closure.\n\nCross-functional Execution\n\t• Collaborate with silicon, firmware, validation, SI/PI, mechanical, thermal, PCB layout, manufacturing, supplier, and program teams.\n\t• Incorporate feedback from verification, validation, manufacturing, and other stakeholders into hardware development and design improvements.\n\t• Support PCB fabrication, assembly, design-for-manufacturability, design-for-test, and hardware readiness.\n\t• Create and maintain design specifications, schematics, review documentation, design checklists, bring-up plans, validation reports, and other technical collateral.\n\t• Own assigned hardware deliverables and proactively identify technical, component, manufacturing, and schedule risks.\n\nQualifications:\nMinimum Qualifications\n\t•  Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.\n\t• 6+ years relevant hands-on industry experience in platform hardware, boar -level product development, PCB design, or related hardware engineering.\n\t• Demonstrated hands-on experience with PCB design, schematic capture, component definition/selection, and interaction with PCB layout teams.\n\t• Strong fundamentals in digital and analog board design, electrical interfaces, mixed-signal design, and platform power-on.\n\t• Experience with high density, multilayer board design and high speed PCB implementation.\n\t• Understanding of high speed interfaces, transmission line fundamentals, signal integrity, and power integrity.\n\t• Knowledge of voltage regulation, power delivery, clocking, resets, and sequencing.\n\t• Experience with industry standard schematic capture and PCB design/review tools like Cadence environments including Allegro and Concept HDL alongside other industry-standard design environments.\n\t• Hands-on experience with board power-on, bring-up, electrical measurement, hardware debugging, and root-cause analysis.\n\t• Strong problem solving, communication, technical documentation, and cross functional collaboration skills.\n\nPreferred Qualifications\n\t• Experience designing complex compute, server, client, validation, FPGA based, or semiconductor development platforms.\n\t• Experience with high speed I/O and memory interfaces such as PCIe, DDR/LPDDR, USB, Ethernet, or comparable technologies.\n\t• Working knowledge of signal integrity, power integrity, transmission line theory, impedance control, crosstalk, PCB stack-up, and power distribution networks.\n\t• Experience with SI/PI, circuit, or power simulation tools.\n\t• Experience with board-level power delivery, basic Verilog coding, power budgeting, voltage regulation, sequencing, and power integrity.\n\t• Knowledge of PCB fabrication, board assembly, DFM/DFT, manufacturing flows, and component/BOM management.\n\t• Experience taking hardware through multiple stages of the lifecycle from design through PCB implementation, fabrication, assembly, bring-up, validation, and deployment.\n\t• Working experience in integrating the AI-based tools and agents in regular workflow\n\t• Familiarity with scripting or automation, such as Python, for hardware development, validation, or debug is an added advantage.\n\t• Experience working effectively with geographically distributed engineering teams, suppliers, and manufacturing partners.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Senior Platform Hardware Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-19", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Senior-Platform-Hardware-Design-Engineer_JR0288291", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nPosition Overview\nAs a Platform Hardware Design Engineer, you will provide technical leadership for the architecture, design, integration, bring-up, and validation of complex platform hardware. You will drive hardware development end-to-end, translating high level system requirements into detailed circuit and component specifications and leading designs from architecture and schematic development through PCB implementation, board power-on, debugging, validation, and delivery. You will be expected to make platform level technical decisions, resolve complex and ambiguous multidisciplinary problems, lead critical design reviews, drive cross-functional alignment, mentor engineers, and influence hardware development practices across projects.\n\nOur Business Group\nYou will be joining the Silicon and Platform Engineering Group (SPE), an organization at Intel committed to advancing Intel's mission of delivering world-class silicon and platform solutions. The group focuses on developing integrated systems that align with customer needs and support Intel's broader goals of leadership in technology innovation. SPE collaborates across diverse domains to ensure Intel platforms meet performance, reliability, and scalability requirements.\nOur work sits at the intersection of silicon, board hardware, firmware, validation, signal and power integrity, mechanical and thermal engineering, PCB technology, manufacturing, and system integration.\nOur senior hardware engineers have a broader responsibility than executing an individual design. They help establish platform architecture, guide implementation, identify and qualify appropriate hardware solutions, provide technical leadership during board power-on and debug, and lead resolution of schematic, layout, SI/PI, and hardware issues.\n\nKey Responsibilities\nPlatform Architecture and End-to-End Technical Ownership\n\t• Own complex platform-board designs from requirements and architecture through deployment.\n\t• Translate high level platform and silicon requirements into system architecture, circuit level requirements, component specifications, and PCB implementation requirements.\n\t• Define and drive critical platform architecture decisions encompassing high speed interfaces, memory, power delivery, clocking, resets, sequencing, control, management, and validation functionality.\n\t• Lead design trade-offs across electrical performance, SI/PI, thermal and mechanical constraints, board complexity, reliability, manufacturability, component availability, cost, schedule, and system compatibility.\n\t• Establish clear technical direction where platform requirements or implementation approaches are initially ambiguous.\nAdvanced Board Design and Technical Leadership\n\t• Lead development of complex high density, multilayer PCBs incorporating advanced digital, analog, mixed signal, and power circuitry.\n\t• Own or provide technical leadership for schematic design, component selection, interface definition, PCB implementation, and design verification.\n\t• Establish PCB stack-up, placement, routing, impedance, power distribution, and critical interface requirements in collaboration with layout and analysis teams.\n\t• Lead schematic, layout, and technical design reviews and ensure critical findings are driven to closure.\n\t• Guide engineers and layout teams in resolving challenging schematic, PCB, layout, and design-for-X issues.\n\t• Identify and qualify new hardware solutions and reusable design approaches where appropriate.\nHigh-Speed Design and SI/PI\n\t• Apply deep understanding of signal integrity, power integrity, transmission-line behavior, high-speed interfaces, and platform power delivery to architecture and implementation decisions.\n\t• Partner with SI/PI engineers to establish design constraints and evaluate critical interfaces and power delivery networks.\n\t• Review PCB implementations for stack-up, placement, routing, return path continuity, high speed performance, and advanced SI/PI considerations.\n\t• Use modeling, simulation, measurement, and hardware correlation to guide technical decisions as appropriate.\nPower Architecture and Power Delivery\n\t• Define and review platform power delivery architecture, voltage regulation, sequencing, power budgeting, and power distribution networks.\n\t• Evaluate board and system power delivery tradeoffs, considering electrical performance, transient behavior, PCB implementation, and platform requirements.\n\t• Work with power integrity specialists to assess PDN behavior and drive required design improvements.\n\t• Apply simulation and hardware measurement to correlate power delivery behavior and resolve platform issues.\nBoard Bring-up, System Integration and Debug\n\t• Define and lead power-on, bring up, validation, characterization, and debug strategy for complex platform hardware.\n\t• Lead resolution of difficult issues spanning board hardware, silicon, firmware, high-speed interfaces, power delivery, and system integration.\n\t• Use disciplined root cause analysis to diagnose failures and define corrective actions.\n\t• Provide hands-on technical leadership in the lab during critical power-on, bring up, and debug activities.\n\t• Apply appropriate measurement techniques and laboratory equipment for high speed, low speed, clock, power, and digital/analog circuitry.\n\t• Drive problems across engineering boundaries until technical closure.\nProgram and Cross-functional Leadership\n\t• Serve as a senior technical interface across silicon, firmware, validation, SI/PI, mechanical, thermal, PCB layout, manufacturing, suppliers, and program teams.\n\t• Lead technical discussions and design reviews and communicate risks, tradeoffs, recommendations, and design decisions clearly to stakeholders.\n\t• Identify technical and execution risks early and drive mitigation plans.\n\t• Own technical readiness for critical hardware milestones, including design release, fabrication, assembly, power-on, and validation.\n\t• Develop and improve reusable architectures, review methodologies, design checklists, development flows, and engineering practices.\n\t• Mentor engineers through architecture development, schematic and PCB reviews, bring-up, debug, and technical problem solving.\n\t• Influence technical decisions and engineering practices beyond an individual board or project.\n\nQualifications:\nMinimum Qualifications\n\t• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.\n\t• 6+ years significant hands-on industry experience in complex platform hardware, PCB development, or system hardware engineering.\n\t• Demonstrated experience leading complex board designs from architecture and requirements through schematic design, PCB implementation, bring-up, debug, and validation.\n\t• Deep understanding of digital and analog board design, electrical interfaces, mixed-signal fundamentals, and system architecture.\n\t• Strong knowledge of high speed interfaces, transmission line behavior, signal integrity, power integrity, memory, clocking, reset, sequencing, and power delivery.\n\t• Proven experience with PCB technologies and layout techniques, including stack-up, placement, routing, and advanced SI/PI considerations.\n\t• Advanced experience with schematic capture and PCB design/review environments.\n\t• Strong hands-on laboratory experience and demonstrated ability to diagnose complex board level problems, determine root cause, and drive corrective actions.\n\t• Demonstrated ability to analyze board/system level design tradeoffs and make sound technical decisions.\n\t• Ability to independently lead complex technical development activities and drive issues across multiple engineering functions.\n\t• Strong technical documentation, presentation, written communication, and cross-functional collaboration skills.\n\t• Demonstrated technical leadership and mentoring capability.\nPreferred Qualifications\n\t• Extensive experience designing complex compute, server, client, FPGA-based, semiconductor validation or other high performance platform hardware.\n\t• Experience with high speed I/O and memory technologies such as PCIe, DDR/LPDDR, Ethernet, USB, or comparable interfaces.\n\t• Deep understanding of PCB stack-up, placement, routing, high speed design, transmission lines, signal integrity, crosstalk, power integrity, and PDN design.\n\t• Experience applying SI/PI, power, circuit, or electromagnetic simulation to board architecture and design decisions.\n\t• Experience defining and validating sophisticated power delivery solutions, power management architectures and basic Verilog coding,\n\t• Strong understanding of PCB fabrication, assembly manufacturing flows, DFM/DFT, component selection, and design release processes.\n\t• Proven experience taking complex boards through the complete lifecycle from architecture through PCB implementation, fabrication, assembly, power-on, validation, and deployment.\n\t• Experience establishing or improving hardware design flows, methodologies, design reviews, and reusable engineering practices.\n\t• Experience with scripting or automation using Python or comparable tools for hardware development, analysis, validation, or debug.\n\t• Working experience in integrating the AI-based tools and agents in regular workflow\n\t• Experience providing technical leadership across multidisciplinary and geographically distributed engineering teams.\n\t• Demonstrated ability to mentor other engineers while remaining hands-on with architecture, board design, bring-up, and complex debug.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Design Verification Engineer", "company": "Lattice", "location": "Penang, Malaysia", "date_posted": "2026-10-19", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Penang-Malaysia/Design-Verification-Engineer_R-103525", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\n\nResponsibilities\nVerify various IP blocks and full-chip FPGA/ASIC designs.\nDefine test plans and develop SystemVerilog/UVM testbenches and test content.\nDebug failures and run regressions to deliver high-quality design validation.\nWork closely with architects, RTL designers, DFX engineers, and automation engineers to ensure robust verification coverage and quality signoff.\n\nQualifications\nBachelor's degree in Electronic Engineering or related field.\nMinimum 2 years of semiconductor or related industry experience.\nFamiliarity with protocols such as Ethernet, PCIe, JESD, CPRI, DDR, Video IP, and FPGA technologies.\nExperience in test planning, testbench development, stimulus generation, reference models, assertion-based verification, and functional coverage.\nExperience with SystemVerilog, UVM, constrained-random verification, and assertion-based methodologies is highly desirable.\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nMalaysiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Staff Design Verification Engineer", "company": "Lattice", "location": "Penang, Malaysia", "date_posted": "2026-10-19", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Penang-Malaysia/Staff-Design-Verification-Engineer_R-103528", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nResponsibilities\nLead verification planning, execution, and sign-off for complex FPGA/ASIC IPs, subsystems, and SoC-level designs.\nDefine verification methodologies, test strategies, coverage goals, and closure criteria for project deliverables.\nArchitect and develop advanced SystemVerilog/UVM verification environments, reusable verification components, scoreboards, assertions, and coverage models.\nDrive verification closure through functional coverage, code coverage, regression analysis, and risk assessments.\nLead debug of complex RTL, integration, low-power, timing, and gate-level simulation issues.\nCollaborate with architects, RTL designers, validation engineers, firmware teams, and program managers to ensure successful product execution.\nProvide technical leadership for verification methodologies, automation, infrastructure, and best practices across projects.\nMentor and guide verification engineers, perform design and verification reviews, and drive team technical excellence.\nSupport silicon bring-up, failure analysis, and root-cause investigations as required.\nDrive continuous improvements in verification productivity, quality, and reusability.\n\nRequired Qualifications\nBachelor's or Master's degree in Electrical/Electronic Engineering, Computer Engineering, or related field.\n8+ years of ASIC/FPGA functional verification experience.\nStrong expertise in SystemVerilog, UVM, and assertion-based verification.\nProven experience leading verification of complex IPs, subsystems, or SoCs from planning through sign-off.\nStrong debugging skills in RTL, gate-level, and system-level verification environments.\nExperience with constrained-random verification, coverage-driven verification, and regression management.\nProficiency in Python, Perl, Shell, or other scripting languages.\nExcellent communication and cross-functional collaboration skills.\n\nPreferred Qualifications\nExperience with PCIe, USB, MIPI CSI/DSI, Ethernet, SerDes, USB, or similar high-speed protocols.\nExperience with low-power verification (UPF/CPF).\nExperience with GLS, timing validation, and post-silicon debug.\nExperience driving verification methodology and infrastructure improvements across multiple projects.\nProven ability to mentor engineers and lead technical initiatives.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nMalaysiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Senior Design Verification Engineer", "company": "Lattice", "location": "Penang, Malaysia", "date_posted": "2026-10-19", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Penang-Malaysia/Senior-Design-Verification-Engineer_R-103527", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nResponsibilities\nLead verification of complex FPGA/ASIC IPs, subsystems, and SoC features from specification through tape-out.\nDevelop verification strategies, test plans, and verification closure criteria aligned with product requirements.\nArchitect and develop scalable SystemVerilog/UVM-based verification environments, checkers, assertions, scoreboards, and coverage models.\nDrive constrained-random and directed verification to achieve functional and code coverage goals.\nDebug design, testbench, simulation, and integration issues across RTL, GLS, low-power, and system-level verification environments.\nCollaborate closely with architects, design engineers, firmware engineers, and validation teams to ensure successful project execution.\nDrive verification sign-off activities, including coverage closure, regression analysis, and risk assessment.\nMentor junior verification engineers and contribute to verification methodology improvements and reusable infrastructure.\nSupport silicon bring-up and root-cause analysis when required.\n\nRequired Qualifications\nBachelor's or Master's degree in Electrical/Electronic Engineering, Computer Engineering, or a related field.\n5+ years of experience in ASIC/FPGA functional verification.\nStrong expertise in SystemVerilog and UVM.\nExperience developing verification environments including drivers, monitors, scoreboards, assertions, and coverage models.\nStrong debugging skills across RTL, gate-level, and system-level simulations.\nExperience with industry-standard simulators and verification tools.\nStrong scripting skills in Python, Perl, Shell, or equivalent.\n\nPreferred Qualifications\nExperience with PCIe, USB, MIPI CSI/DSI, Ethernet, SerDes, or other high-speed protocols.\nExperience with low-power verification methodologies (UPF/CPF).\nExperience with GLS, timing analysis, and post-silicon debug.\nKnowledge of FPGA architecture and programmable logic devices.\nPrior experience leading verification activities for a major IP or subsystem.\nExperience mentoring engineers and driving methodology improvements.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nMalaysiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Senior Design Verification Engineer", "company": "Lattice", "location": "Penang, Malaysia", "date_posted": "2026-10-19", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Penang-Malaysia/Senior-Design-Verification-Engineer_R-103526", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nResponsibilities\nLead verification of complex FPGA/ASIC IPs, subsystems, and SoC features from specification through tape-out.\nDevelop verification strategies, test plans, and verification closure criteria aligned with product requirements.\nArchitect and develop scalable SystemVerilog/UVM-based verification environments, checkers, assertions, scoreboards, and coverage models.\nDrive constrained-random and directed verification to achieve functional and code coverage goals.\nDebug design, testbench, simulation, and integration issues across RTL, GLS, low-power, and system-level verification environments.\nCollaborate closely with architects, design engineers, firmware engineers, and validation teams to ensure successful project execution.\nDrive verification sign-off activities, including coverage closure, regression analysis, and risk assessment.\nMentor junior verification engineers and contribute to verification methodology improvements and reusable infrastructure.\nSupport silicon bring-up and root-cause analysis when required.\n\nRequired Qualifications\nBachelor's or Master's degree in Electrical/Electronic Engineering, Computer Engineering, or a related field.\n5+ years of experience in ASIC/FPGA functional verification.\nStrong expertise in SystemVerilog and UVM.\nExperience developing verification environments including drivers, monitors, scoreboards, assertions, and coverage models.\nStrong debugging skills across RTL, gate-level, and system-level simulations.\nExperience with industry-standard simulators and verification tools.\nStrong scripting skills in Python, Perl, Shell, or equivalent.\n\nPreferred Qualifications\nExperience with PCIe, USB, MIPI CSI/DSI, Ethernet, SerDes, or other high-speed protocols.\nExperience with low-power verification methodologies (UPF/CPF).\nExperience with GLS, timing analysis, and post-silicon debug.\nKnowledge of FPGA architecture and programmable logic devices.\nPrior experience leading verification activities for a major IP or subsystem.\nExperience mentoring engineers and driving methodology improvements.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nMalaysiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Staff Design verification Engineer", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-10-19", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Staff-Design-verification-Engineer_R262921-1", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nStaff Digital Design Engineer\n\nAbout the Role\nAs a Staff Digital Design Engineer, you will lead complex digital design projects and provide technical leadership for system-level architecture. You'll influence product direction, guide methodology improvements, and lead small technical teams. This position requires deep expertise across multiple technical domains and strong cross-functional collaboration skills to drive innovation and excellence in digital design.\n\nKey Responsibilities\nDefine and develop system-level architectures for complex digital designs\nLead technical teams on complex digital design projects\nGuide methodology improvements and best practices across the organization\nInfluence product direction and technical roadmaps\nCollaborate across functions to drive innovative solutions\nEngage directly with customers on technical requirements and solutions\nMentor engineers and help develop technical talent\n\nMust Have Skills\nSystem Architecture: Expert ability to define and implement complex digital system architectures\nTechnical Leadership: Demonstrated capability to provide technical direction to engineering teams\nMulti-Domain Expertise: Deep knowledge across multiple technical domains relevant to digital design\nMethodology Expertise: Authority in digital design methodologies with ability to drive improvements\nCross-Functional Collaboration: Strong capability to work across organizational boundaries\nCustomer Engagement: Experience translating customer needs into technical requirements and solutions\n\nPreferred Education and Experience\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent experience\n8-12 years of relevant experience in digital design engineering\n\nWhy You'll Love Working Here\nAt Analog Devices, you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on professional growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world.\n\nYour expertise will shape the future of technology, and you’ll be supported by a culture that values continuous advancement and professional growth. Join us and help create the technologies that bridge the physical and digital worlds, making a tangible difference in how people live, work, and connect.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Staff Engineer, Design Verification Engineering", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-10-19", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Staff-Engineer--Design-Verification-Engineering_R265378", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nStaff Design Verification Engineer\n\nAbout the Role\nAs a Staff Design Verification Engineer at Analog Devices, you will provide technical leadership in developing verification strategies for our most complex analog and mixed-signal designs. You'll architect sophisticated verification environments, mentor junior engineers, and collaborate across organizational boundaries to ensure product quality and reliability.\nWorking with limited direction, you'll apply your deep technical expertise to solve critical verification challenges while representing ADI in interactions with key customers and industry partners. This senior position involves significant influence on verification methodology adoption and technical decisions that impact crucial organizational objectives.\n\nKey Responsibilities\nStrategic Leadership: Architect and lead verification strategy for complex digital and mixed-signal designs, acting as a key contributor in critical verification environments\nVerification Architecture: Design and implement sophisticated UVM-based verification environments that ensure comprehensive test coverage and design quality\nTechnical Mentorship: Guide and develop junior engineers, serving as a resource for colleagues with less experience while modeling professional behaviors\nCross-Functional Direction: Coordinate work across organizational lines, collaborating with design teams on verification requirements and sign-off criteria\nProblem Resolution: Lead complex debugging efforts across RTL and gate-level simulations with minimal direction, developing resolutions that require in-depth analysis\nCoverage Closure: Drive functional and code coverage closure using advanced verification methodologies to ensure design accuracy\nPost-Silicon Support: Lead post-silicon validation activities, contributing expertise to address critical issues\nCustomer Representation: Serve as principal customer contact on projects, representing ADI's technical excellence and customer commitment\n\nMust Have Skills\nSystemVerilog and UVM Expertise: Expert-level knowledge of SystemVerilog and Universal Verification Methodology for architecting advanced verification environments for complex designs\nTest Planning and Strategy: Demonstrated ability to develop comprehensive verification plans that drive coverage-driven methodologies and verification closure\nMixed-Signal Verification: Deep understanding of mixed-signal design principles and verification methodologies, with experience implementing sophisticated verification approaches\nDebugging Mastery: Advanced debugging skills across multiple design abstractions, with proven ability to resolve complex verification issues with minimal direction\nEDA Tool Proficiency: Extensive experience with electronic design automation tools (Cadence/Synopsys) and formal verification techniques\nScripting and Automation: Advanced proficiency in Python, Perl, TCL, or Shell scripting for creating sophisticated verification automation frameworks\nTechnical Leadership: Demonstrated ability to influence verification direction, mentor junior engineers, and drive methodology adoption across teams\n\nPreferred Education and Experience\nMS/PhD in Electrical Engineering, Computer Engineering, or related field\n7-10+ years of relevant digital design verification experience, with particular emphasis on mixed-signal verification\n\nWhy You'll Love Working Here\nAt Analog Devices, you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on professional growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world.\nYour expertise will shape the future of technology, and you'll be supported by a culture that values continuous advancement and professional growth. Join us and help create the technologies that bridge the physical and digital worlds, making a tangible difference in how people live, work, and connect.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "AMS Verification Engineer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-10-19", "url": "https://careers.skyworksinc.com/job-invite/78524/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 78524\n\nSummary\n\nSkyworks Bengaluru, KA, IND design center has leading R&D and product development capabilities. Our team provides many opportunities to learn from various circuit level designs to system module level for cell phone applications. You’ll be paired with an engineer in Irvine, CA, USA, to support you as an integral part of the team. Working and living in Bengaluru provides a wonderful lifestyle in a vibrant city which is one of the leading tech cities in India.\n\nDescription\n\nSeeking an early-career analog design engineer to develop and verify mixed-signal controllers for custom RF integrated circuits. This role will be part of a design group enabling the next generation of wireless technology through the development of custom RF solutions for mobile devices. Candidate will work closely withand support our US based analog design team. The role will focus on integrating internal IP into custom controllers and running analog IP block and full chipverification. Candidate will gain experience in multiple IC technologies. Responsibilities will also include detailed documentation and automation development +methodology improvement.\n\nResponsibilities\n\n- Perform chip top level verification of RF integrated circuit products\n\n- Integrate Skyworks IP in RF integrated circuit controllers to meet customer requirements\n\n- Collaborate with RF, digital, layout, and systems engineers\n\n- Communicate technical results clearly through design reviews, documentation, presentations\n\n- Develop and maintain scripts, utilities, and automation flows for IC design, simulation, verification, and documentation tasks\n\n- Review layouts and provide guidance on device matching, parasitics, isolation, and die-size tradeoffs\n\n- Maintain effective collaboration by ensuring adequate overlap with the US team and attending off-hours meetings when project needs require\n\nRequired Experience and Skills\n\n- BSEE + 3 years work relevant work experience \n\n- MS or PhD preferred \n\n- Demonstrated Analog IC design experience\n\n- Proficient with Cadence IC design tools\n\n- Solid understanding of general analog circuits such as bias, bandgap, LDO, opamp, charge pump etc.\n\n- Strong understanding of silicon fabrication and how it affects the device physics, device model, and circuit performance\n\n- Layout experience using Cadence flow, including LVS and DRC. Ability to work with CAD engineers and provide guidance on analog layouts\n\n- Excellent communication and presentation skills \n\nDesired Experience and Skills\n\n- Knowledge of RF design concepts and circuits\n\n- Experienced in implementing on-chip ESD protection strategies for HBM/MM/CDM on IC\n\n- Demonstrated experience debugging, resolving and applying techniques to mitigate analog signal noise coupling and optimum layout for performance, and die size trade off\n\n- Experience with a scripting or coding language (Python, Perl, C, C++, etc.)\n\n- Experience working with serial data protocols (I2C, UART, SPI, MIPI)\n\n- Experience with digital design/verification languages and tools (Verilog, VHDL, SystemVerilog, synthesis, etc.)\n\n- Understanding of analog behavioral modeling techniques (VerilogA, VerilogAMS, or Real Number Modeling)\n\n#LI-PR1\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "AMS Verification Engineer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-10-19", "url": "https://careers.skyworksinc.com/job-invite/78522/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 78522\n\nSummary\n\nSkyworks Bengaluru, KA, IND design center has leading R&D and product development capabilities. Our team provides many opportunities to learn from various circuit level designs to system module level for cell phone applications. You’ll be paired with an engineer in Irvine, CA, USA, to support you as an integral part of the team. Working and living in Bengaluru provides a wonderful lifestyle in a vibrant city which is one of the leading tech cities in India.\n\nDescription\n\nSeeking an early-career analog design engineer to develop and verify mixed-signal controllers for custom RF integrated circuits. This role will be part of a design group enabling the next generation of wireless technology through the development of custom RF solutions for mobile devices. Candidate will work closely with and support our US based analog design team. The role will focus on integrating internal IP into custom controllers and running analog IP block and full chip verification. Candidate will gain experience in multiple IC technologies. Responsibilities will also include detailed documentation and automation development + methodology improvement.\n\nResponsibilities\n\n- Perform chip top level verification of RF integrated circuit products\n\n- Integrate Skyworks IP in RF integrated circuit controllers to meet customer requirements\n\n- Collaborate with RF, digital, layout, and systems engineers\n\n- Communicate technical results clearly through design reviews, documentation, presentations\n\n- Develop and maintain scripts, utilities, and automation flows for IC design, simulation, verification, and documentation tasks\n\n- Review layouts and provide guidance on device matching, parasitics, isolation, and die-size tradeoffs\n\n- Maintain effective collaboration by ensuring adequate overlap with the US team and attending off-hours meetings when project needs require\n\nRequired Experience and Skills\n\n- BSEE + 3 years work relevant work experience\n\n- MS or PhD preferred\n\n- Demonstrated Analog IC design experience\n\n- Proficient with Cadence IC design tools\n\n- Solid understanding of general analog circuits such as bias, bandgap, LDO, opamp, charge pump etc.\n\n- Strong understanding of silicon fabrication and how it affects the device physics, device model, and circuit performance\n\n- Layout experience using Cadence flow, including LVS and DRC. Ability to work with CAD engineers and provide guidance on analog layouts\n\n- Excellent communication and presentation skills\n\nDesired Experience and Skills\n\n- Knowledge of RF design concepts and circuits\n\n- Experienced in implementing on-chip ESD protection strategies for HBM/MM/CDM on IC\n\n- Demonstrated experience debugging, resolving and applying techniques to mitigate analog signal noise coupling and optimum layout for performance, and die size trade off\n\n- Experience with a scripting or coding language (Python, Perl, C, C++, etc.)\n\n- Experience working with serial data protocols (I2C, UART, SPI, MIPI)\n\n- Experience with digital design/verification languages and tools (Verilog, VHDL, SystemVerilog, synthesis, etc.)\n\n- Understanding of analog behavioral modeling techniques (VerilogA, VerilogAMS, or Real Number Modeling)\n\n \n\n#LI-PR1\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Analog Design Engineer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-10-19", "url": "https://careers.skyworksinc.com/job-invite/78585/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 78585\n\nDescription\n\nIf you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high-performance analog semiconductors whose solutions are powering the wireless networking revolution. Through our broad technology expertise and one of the most extensive product portfolios in the industry, we are Connecting Everyone and Everything, All the Time. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management, and the freedom to make meaningful contributions in a setting that encourages creative thinking. We value open communication, mutual trust, and respect. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together are changing the way the world communicates.\n\nSummary\n\nSkyworks Bengaluru, KA, IND design center has leading R&D and product development capabilities. Our team provides many opportunities to learn from various circuit level designs to system module level for cell phone applications. Working and living in Bengaluru provides a wonderful lifestyle in a vibrant city which is one of the leading tech cities in India.\n\n \n\nDescription\n\nSeeking an early-career analog design engineer to develop and verify mixed-signal controllers for custom RF integrated circuits. This role will be part of a design group enabling the next generation of wireless technology through the development of custom RF solutions for mobile devices. The role will focus on integrating internal IP into custom controllers and running analog IP block and full chip verification. Candidate will gain experience in multiple IC technologies. Responsibilities will also include detailed documentation and automation development +methodology improvement.\n\nResponsibilities\n\nDesign of Analog/RF FEM circuits such as Bias, bandgap, LDO, opamp, charge pump, LNA, Filters etc. and verification\n\nReview layouts and provide guidance on device matching, parasitic, isolation, and die-size tradeoffs.\n\nPerform chip top level verification of RF integrated circuit products\n\nIntegrate Skyworks IP in RF integrated circuit controllers to meet customer requirements\n\nCollaborate with RF, digital, layout, and systems engineers\n\nCommunicate technical results clearly through design reviews, documentation, presentations\n\nDevelop and maintain scripts, utilities, and automation flows for IC design, simulation, verification, and documentation tasks\n\nMaintain effective collaboration by ensuring adequate overlap with the US team and attending off-hours meetings when project needs require.\n\nRequired Experience and Skills\n\nRequired Experience\n\nBSEE + 3 years work relevant work experience\n\nMS or PhD Preferred\n\n \n\nMinimum Requirements\n\nDemonstrated Analog IC design experience\n\nProficient with Cadence IC design tools\n\nSolid understanding of general analog circuits such as bias, bandgap, LDO, opamp, charge pump etc.\n\nStrong understanding of silicon fabrication and how it affects the device physics, device model, and circuit performance\n\nLayout experience using Cadence flow, including LVS and DRC. Ability to work with CAD engineers and provide guidance on analog layouts\n\nExcellent communication and presentation skills\n\n \n\nDesired Experience and Skills\n\nDesired Experience and Skills\n\nKnowledge of RF design concepts and circuits\n\nExperienced in implementing on-chip ESD protection strategies for HBM/MM/CDM on IC\n\nDemonstrated experience debugging, resolving and applying techniques to mitigate analog signal noise coupling and optimum layout for performance, and die size trade off\n\nExperience with a scripting or coding language (Python, Perl, C, C++, etc.)\n\nExperience working with serial data protocols (I2C, UART, SPI, MIPI)\n\nExperience with digital design/verification languages and tools (Verilog, VHDL, SystemVerilog, synthesis, etc.)\n\nUnderstanding of analog behavioral modeling techniques (VerilogA, VerilogAMS, or Real Number Modeling)\n\n#LI-PR1\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Staff Functional Test Verification/Simulation Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-10-19", "url": "https://careers.arm.com/job/bengaluru/staff-functional-test-verification-simulation-engineer/33099/96153587952", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview:\n \nArm is seeking an experienced and driven  Staff Functional Test Verification/Simulation Engineer to join our engineering hub in Bangalore. In this high-impact role, you will lead the pre-silicon verification and simulation of next-generation Arm CPU/GPU architectures, ensuring world-class quality, performance, and functional correctness for billions of devices worldwide.\nKey Responsibilities\nArchitecture & Subsystem Verification: Spearhead verification/simulation strategies for advanced Arm CPU/GPU designs by partnering with Design/DV to identify the target functional coverage for silicon on top of structural coverage. \nTest Porting & Simulation: Drive functional, datapath, and performance test case porting and executionacross intensive simulation platforms.\nTestbench Development: Design and Scalable, reusable UVM, SystemVerilog, and C-based testbenchesand stimulus generation infrastructures.\nPattern Generation & Silicon Validation: Build advanced pattern generation and simulation flows, and bridge pre-silicon simulation with post-silicon validation to correlate performance and functional expectations on real silicon.\nCoverage & Debug Closure: Own functional coverage analysis, System , debugging complex multi-domain RTL, testbench, and system-level issues efficiently using Python automation.\nRequired Qualifications & Experience\nExperience: 9-13 years of proven hands-on experience in complex  SoC verification.\nDomain Expertise: Solid working knowledge of Arm CPU/GPU architecture, instruction sets, and high-performance datapath pipelines.\nMethodologies & Languages:\nAdvanced proficiency in SystemVerilog, UVM, and C/C++ co-simulation or testbench creation.\nStrong scripting capabilities in Python for test automation, data analysis, and regression tracking.\nVerification Scope: Proven expertise in executing functional/performance stress test cases, pattern generation, simulation, and silicon validation handoffs.\nSimulation Tools: Deep familiarity with industry-standard EDA simulators and debug ecosystems (e.g., Synopsys VCS, Cadence Xcelium/Palladium, Siemens Questa).\nPreferred Skills\nDeep understanding of AMBA protocols (CHI, AXI, AHB) and internal memory hierarchies.\nExperience with power-aware verification, emulation, or performance modeling.\nStrong interpersonal skills with a track record of driving cross-functional alignment across global engineering sites.\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition, and creating impact through technology used by millions.\n \n#LI-SC2\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Staff Structural Test Verification/Simulation Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-10-19", "url": "https://careers.arm.com/job/bengaluru/staff-structural-test-verification-simulation-engineer/33099/102150199088", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview:\n \nArm is seeking a visionary and technical leader for a Staff Structural Test Verification/Simulation Engineer role in Bangalore. In this high-visibility position with 10+ years of experience, you will spearhead structural test, design-for-test (DFT), and test verification methodologies across advanced, world-class Arm products. You will act as a technical authority, ensuring flawless manufacturing test quality, high silicon yield, and robust fault coverage.\nKey Responsibilities\nDFT Verification Leadership: Define and drive the comprehensive pre-silicon verification and simulation strategy for advanced logic and memory test architectures.\nLogic Diagnostics & ATPG: Drive the simulation of ATPG (Automatic Test Pattern Generation) patterns and logic diagnostics flows to guarantee fault coverage and defect detection.\nMemory Diagnostics & MBIST: Drive the simulation of MBIST (Memory Built-In Self-Test) controllers, memory repair algorithms, and memory diagnostics architectures.\nTool & Standard Integration: Utilize industry-standard test methodologies and EDA tools (ICL, PDL, Tessent, and TetraMAX) to validate DFT insertions, boundary scan, and scan compression logic.\nSilicon Validation & Yield Debug: Bridge pre-silicon simulation with post-silicon testing, collaborating closely with manufacturing and test engineering teams on silicon validation and yield debug to root-cause failures and optimize test efficiency.\nRequired Qualifications & Experience\nExperience: 10+ years of extensive experience in design-for-test (DFT), structural test verification, or test engineering for complex ASICs/SoCs.\nCore DFT Skills:\nExpert-level understanding of Logic Diagnostics and ATPG pattern verification/simulation.\nDeep expertise in Memory Diagnostics and MBIST pattern verification/simulation.\nEcosystem & Tool Proficiency: Hands-on mastery of industry-standard DFT languages and tools, including ICL (Instrument Connection Language), PDL (Procedure Description Language), Siemens Tessent, and Synopsys TetraMAX.\nPost-Silicon Execution: Demonstrated track record in silicon validation, ATE pattern bring-up, and yield debug for high-volume semiconductor manufacturing.\nMethodologies & Coding: Strong background in hardware verification languages (SystemVerilog/UVM) and scripting automation (Python, Perl, or Tcl).\nPreferred Skills & Leadership\nExceptional technical leadership, mentoring skills, and ability to drive cross-functional engineering execution across global sites.\nDeep knowledge of advanced process nodes (sub-7nm/5nm/3nm) and low-power DFT challenges.\nExperience with IJTAG (IEEE 1687) and boundary-scan (IEEE 1149.1/4) standards.\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition, and creating impact through technology used by millions.\n \n#LI-SC2\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Staff Hardware Development Engineer - High Speed Board Design", "company": "Nokia", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-10-19", "url": "https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/39911", "is_hardware": true, "platform": "oracle", "jd_text": "The Staff Hardware Development Engineer will be a key member of our team, responsible for designing and developing high-performance hardware solutions. With a focus on board design, testing, and debugging, this role requires a strong understanding of EDA tools and hands-on experience in lab activities. The successful candidate will have the opportunity to work on innovative projects and contribute to the development of cutting-edge technology.\n\nNILightpath\n\nResponsibilities\nOwn hardware development across the full product lifecycle, including concept definition, architecture, detailed design, prototype bring-up, verification, qualification, production introduction, sustaining engineering, and field issue resolution.\nDesign and develop high-speed analog and mixed-signal circuits, including laser drivers, modulator drivers, transimpedance amplifiers (TIAs), bias control circuits, clocking and PLL solutions, ADC/DAC interfaces, and low-noise power delivery systems.\nDevelop high-speed PCB designs for 112G/224G PAM4 and coherent optical applications, including stack-up definition, impedance control, length matching, via and back-drill strategies, and connector selection.\nApply expertise in analog and mixed-signal circuit design, including amplifiers, filters, data converters, PLLs, low-noise design techniques, and power management architectures.\nUtilize knowledge of high-speed serial interfaces, such as 56G/112G/224G PAM4, CEI, and OIF standards, as well as an understanding of coherent modulation concepts including QPSK, 16QAM, phase recovery, and frequency recovery.\nApply RF and microwave fundamentals, including S-parameters, matching networks, noise figure, linearity, signal integrity, and clock distribution principles.\nDrive design-for-manufacturability (DFM), design-for-assembly (DFA), design-for-testability (DFT), reliability, serviceability, and cost optimization initiatives throughout the product lifecycle.\nCollaborate with signal integrity and power integrity specialists to perform SI/PI analysis and channel modeling, including S-parameter characterization, loss and crosstalk assessment, jitter and noise analysis, and power delivery network optimization for coherent DSP and high-speed SerDes applications.\nAnalyze and address deterministic and random jitter, phase noise, clock quality, noise coupling mechanisms, equalization requirements, and timing margin considerations in high-speed systems.\nPartner with cross-functional teams, including system architects, software engineers, product managers, manufacturing engineers, and validation teams, to ensure successful product integration and delivery.\nStay current with emerging technologies, industry standards, and AI-enabled engineering practices. Drive innovation through the adoption of modern design methodologies, automation, and data-driven insights to accelerate product development and improve product quality.\n\nQualifications\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.\n10+ years of experience in high-board design, testing, and debugging.\nProficiency in EDA tools and hands-on experience in lab activities.\nStrong knowledge of hardware design principles and best practices.\nExperience with hardware debugging and troubleshooting techniques.\nFamiliarity with industry-standard design tools and simulation software.\nExcellent problem-solving and analytical skills.\nAbility to work independently and manage multiple projects simultaneously.\nEffective communication and collaboration skills.\nWillingness to learn and adapt to new technologies and industry trends.\n\nAbout the company\nAdvancing connectivity to secure a brighter world.\n\nNokia is a global leader in connectivity for the AI era. With expertise across fixed, mobile and transport networks, powered by the innovation of Nokia Bell Labs, we’re advancing connectivity to secure a brighter world. \n\nLearn more about life at Nokia.\n\nOur recruitment process\n\nWe act inclusively and respect the uniqueness of people. Our employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.\n\nIf you’re interested in this role but don’t meet every listed requirement, we still encourage you to apply. Unique backgrounds, perspectives, and experiences enrich our teams, and you may be just the right candidate for this or another opportunity.\n\nThe length of the recruitment process may vary depending on the specific role's requirements. We strive to ensure a smooth and inclusive experience for all candidates. Discover more about the recruitment process at Nokia.", "jd_status": "stored"}, {"title": "Staff Electrical Engineer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-10-19", "url": "https://careers.skyworksinc.com/job-invite/78576/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 78576\n\nDescription\n\nIf you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high-performance analog semiconductors whose solutions are powering the wireless networking revolution. Through our broad technology expertise and one of the most extensive product portfolios in the industry, we are Connecting Everyone and Everything, All the Time. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management, and the freedom to make meaningful contributions in a setting that encourages creative thinking. We value open communication, mutual trust, and respect. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together are changing the way the world communicates.\n\nResponsibilities\n\nDesign of Analog/RF FEM circuits such as Bias, bandgap, LDO, opamp, charge pump, LNA, Filters etc. and verification\n\nReview layouts and provide guidance on device matching, parasitic, isolation, and die-size tradeoffs.\n\nPerform chip top level verification of RF integrated circuit products\n\nIntegrate Skyworks IP in RF integrated circuit controllers to meet customer requirements\n\nCollaborate with RF, digital, layout, and systems engineers\n\nCommunicate technical results clearly through design reviews, documentation, presentations\n\nDevelop and maintain scripts, utilities, and automation flows for IC design, simulation, verification, and documentation tasks\n\nMaintain effective collaboration by ensuring adequate overlap with the US team and attending off-hours meetings when project needs require.\n\n \n\nRequired Experience and Skills\n\nBSEE + 3 years work relevant work experience\n\nMS or PhD Preferred\n\nDemonstrated Analog IC design experience\n\nProficient with Cadence IC design tools\n\nSolid understanding of general analog circuits such as bias, bandgap, LDO, opamp, charge pump etc.\n\nStrong understanding of silicon fabrication and how it affects the device physics, device model, and circuit performance\n\nLayout experience using Cadence flow, including LVS and DRC. Ability to work with CAD engineers and provide guidance on analog layouts\n\nExcellent communication and presentation skills\n\nDesired Experience and Skills\n\nKnowledge of RF design concepts and circuits\n\nExperienced in implementing on-chip ESD protection strategies for HBM/MM/CDM on IC\n\nDemonstrated experience debugging, resolving and applying techniques to mitigate analog signal noise coupling and optimum layout for performance, and die size trade off\n\nExperience with a scripting or coding language (Python, Perl, C, C++, etc.)\n\nExperience working with serial data protocols (I2C, UART, SPI, MIPI)\n\nExperience with digital design/verification languages and tools (Verilog, VHDL, SystemVerilog, synthesis, etc.)\n\nUnderstanding of analog behavioral modeling techniques (VerilogA, VerilogAMS, or Real Number Modeling)\n\n#LI-PR1\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Electrical Engineer 1", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-10-19", "url": "https://careers.skyworksinc.com/job-invite/78676/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 78676\n\nDescription\n\nIf you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high-performance analog semiconductors whose solutions are powering the wireless networking revolution. Through our broad technology expertise and one of the most extensive product portfolios in the industry, we are Connecting Everyone and Everything, All the Time. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management, and the freedom to make meaningful contributions in a setting that encourages creative thinking. We value open communication, mutual trust, and respect. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together are changing the way the world communicates.\n\nResponsibilities\n\nJob Responsibilities\n\nPerform chip top level verification of RF integrated circuit products\n\nIntegrate Skyworks IP in RF integrated circuit controllers to meet customer requirements\n\nCollaborate with RF, digital, layout, and systems engineers\n\nCommunicate technical results clearly through design reviews, documentation, presentations\n\nDevelop and maintain scripts, utilities, and automation flows for IC design, simulation, verification, and documentation tasks\n\nReview layouts and provide guidance on device matching, parasitic, isolation, and die-size tradeoffs.\n\nMaintain effective collaboration by ensuring adequate overlap with the US team and attending off-hours meetings when project needs require.\n\nRequired Experience and Skills\n\nBSEE Or MS or PhD Preferred\n\nMinimum Requirements\n\nDemonstrated Analog circuit understanding\n\nGoog academic expereince on Analog and Digital verification\n\nProficient with Cadence IC design tools\n\nSolid understanding of general analog circuits such as bias, bandgap, LDO, opamp, charge pump etc.\n\nStrong understanding of silicon fabrication and how it affects the device physics, device model, and circuit performance\n\nLayout experience using Cadence flow, including LVS and DRC. Ability to work with CAD engineers and provide guidance on analog layouts\n\nExcellent communication and presentation skills\n\nDesired Experience and Skills\n\nKnowledge of RF design concepts and circuits\n\nExperienced in implementing on-chip ESD protection strategies for HBM/MM/CDM on IC\n\nDemonstrated experience debugging, resolving and applying techniques to mitigate analog signal noise coupling and optimum layout for performance, and die size trade off\n\nExperience with a scripting or coding language (Python, Perl, C, C++, etc.)\n\nExperience working with serial data protocols (I2C, UART, SPI, MIPI)\n\nExperience with digital design/verification languages and tools (Verilog, VHDL, SystemVerilog, synthesis, etc.)\n\nUnderstanding of analog behavioral modeling techniques (VerilogA, VerilogAMS, or Real Number Modeling)\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Principal Test Engineer – Manufacturing Test Operations", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-10-19", "url": "https://careers.arm.com/job/bengaluru/principal-test-engineer-manufacturing-test-operations/33099/94564327792", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview\n \nThis is a senior leadership opportunity to drive manufacturing test operations for next-generation semiconductor products across high-performance segments including Cloud, Infrastructure, and Automotive.\nAs a Principal Engineer, you will lead the definition and execution of test strategy for complex, high-performance SoCs while remaining highly hands-on with Advantest V93K (93K EXA Scale) platforms and SmarTest (SMT7/SMT8) environments.\nA key aspect of this role is end-to-end ownership of manufacturing test, including lab bring-up and infrastructure development from scratch, enabling characterization and production readiness. You will work closely with OSAT partners to ensure smooth production ramp, yield optimization, and operational excellence.\n \nKey Responsibilities\n \nTest Strategy & Technical Leadership\n- Define and drive end-to-end test strategy for advanced SoCs\n- Lead ATE strategy across bring-up, characterization, qualification, and production\n- Provide leadership on Advantest V93K (EXA Scale) platforms\n- Drive best practices in DFT, yield optimization, and production scalability\n \nHands-On ATE Development\n- ATE test program development using SmarTest (SMT7/SMT8)\n- Test method development (Scan/ATPG, MBIST, HSIO, Functional)\n- Test flow and binning strategy development\n- Silicon bring-up, characterization, debug, and yield analysis\n \nLab & Infrastructure Development\n- Build test labs from scratch (93K testers, probe/loadboards, thermal systems)\n- Develop automation and data infrastructure\n- Define lab processes and workflows\n \nOSAT & Production Engagement\n- Work with OSATs\n- Production transfer, correlation, and ramp\n- Yield monitoring and issue resolution\n \nTeam & Program Leadership\n- Build and lead a test engineering team\n- Drive cross-functional execution\n- Manage vendors and partners\n- Own delivery from architecture to production\n \nRequired Skills & Experience\n- 15+ years in semiconductor test engineering\n- Strong experience with Advantest V93K (EXA Scale)\n- Deep expertise in SmarTest SMT7/SMT8 (required)\n- OSAT experience (production ramp, yield, transfer)\n- Experience with complex/high-performance SoCs\n- Strong in ATE, DFT, bring-up, and yield analysis\n- Proven leadership and team management skills\n \nNice to Have\n- C++, Python, Unix\n- Tools: SmartRDI, YieldExplorer, JMP, Tableau\n- Knowledge of IEEE standards, scan diagnostics, thermal systems\n \nPersonal Attributes\n- Strong leadership and hands-on balance\n- Results-driven mindset\n- Strong debug and analytical skills\n- Ability to build teams and systems from scratch\n- Strong communication across global teams\n \nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\n \n#LI-SC2\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "DFT Engineer / GPU Logic Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-19", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/DFT-Engineer---GPU-Logic-Design-Engineer_JR0287980", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nAs a GPU Logic Design Engineer, you will contribute to the design and validation of cutting-edge graphics IPs, including compute, display, and media units. You will be immersed in the creation of register transfer level (RTL) coding, simulation, and optimization strategies to meet power, performance, area, and timing goals. By leveraging your expertise, you will play a pivotal role in enabling high-quality integration of GPU blocks into larger system-on-chip (SoC) designs, directly impacting Intel's future graphics technologies.\n\nBusiness Group\nYou will be joining Intel's Data Center Group (DCG), a team dedicated to driving innovation and delivering high-performance solutions for data-centric workloads. The group focuses on developing advanced graphics hardware that powers data center GPU solutions, supporting Intel's broader mission of creating world-changing technology that enriches lives. It offers an exciting environment where collaboration and technical excellence intersect to shape the future of visual computing.\n\nKey Responsibilities\n- Develop logic design, RTL coding, and simulation for graphics IPs, ensuring compliance with power, performance, area, and timing requirements.\n- Participate in defining architecture and microarchitecture features for GPU blocks.\n- Optimize logic design to support physical implementation while maintaining design integrity.\n- Review and implement verification plans to ensure design features are accurately tested across verification hierarchies.\n- Drive unit-level verification and resolve RTL test failures to ensure feature correctness.\n- Support SoC customers in integrating GPU blocks effectively for high-quality results.\n\nQualifications:\nMinimum Qualifications\n- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 3+ years of industry experience, OR a Master's degree in the same fields with 2+ years of industry experience, OR a PhD with no prior professional experience.\n- Demonstrated expertise in at least one of the following DFT features: TAP/JTAG, Scan/ATPG, or Array DFT (MBIST/PBIST).\n- Proficiency in EDA tools such as ATPG tools, Mentor Tessent shell, VCS simulation, and debug tools.\n- Experience in silicon enabling debug or test pattern development.\n\nPreferred Qualifications\n- Proficiency in design automation and scripting languages for streamlining workflows.\n- Familiarity with structural design flows, including timing, routing, placement, and clock analysis.\n- Knowledge of high-volume manufacturing requirements and test flows.\n- Understanding of 3D, media, and display graphics pipelines.\n- Awareness of SoC architecture principles and best practices.\n\nBring your expertise to Intel's GPU Hardware IP team and be a driving force behind the future of graphics and visual computing technology. Collaborate with a diverse and innovative team to deliver impactful solutions that redefine the industry.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Global Product Support Engineer – Semiconductor Equipment", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2026-10-19", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/Global-Product-Support-Engineer---Semiconductor-Equipment_R2626276", "is_hardware": true, "platform": "workday", "jd_text": "Who We Are\n\nApplied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI and accelerating the commercialization of next-generation semiconductor chips. Join us and push the boundaries of materials science and engineering in a company at the foundation of the electronics industry. The work we do together advances the world’s technology. \n\nWhat We Offer\n\nLocation:\nBangalore,IND\nYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. \n\nAt Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. \n\nKey Responsibilities\nDevelop new procedures and Best Known Methods (BKMs) to service new products\nParticipate in or own first chamber Build & Test in Apps lab\nSolve issues, or work with Engineering to address issues identified\nWork with Manufacturing to develop procedures and participate (if required) on New Product final test\nDrive resolution of key issues with Engineering.  Own beta site test plans and reporting\nPartner with Quality & Reliability (Q&R) group to review and address Top Field Issues\nParticipate in or own CAPA process\nIdentify new parts that require to be stocked by AGS and work with them to ensure parts are stocked in correct locations\n\nFunctional Knowledge\nDemonstrates expanded conceptual knowledge in own discipline and broadens capabilities\n\nBusiness Expertise\nUnderstands key business drivers; uses this understanding to accomplish own work\n\nLeadership\nNo supervisory responsibilities but provides informal guidance to new team members\n\nProblem Solving\nSolves problems in straightforward situations; analyzes possible solutions using technical experience and judgment and precedents \n\nImpact\nImpacts quality of own work and the work of others on the team; works within guidelines and policies\n\nInterpersonal Skills\nExplains complex information to others in straightforward situations\n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nNew College Grad\nTravel:\nYes, 75% of the Time\nRelocation Eligible:\nYes\n\nApplied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "Sr Staff, Product/Program Management - Semiconductor NPI(Analog/Power)", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-18T13:35:40.883000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000156186829-sr-staff-product-program-management-semiconductor-npi-analog-power-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Responsible for managing the development of New Products (Industrial and Automotive) and delivering on all program commitments from inception through execution to tape out and start of production. \nDevelop and maintain project schedules, budgets, and resource allocations to ensure on-time project completion within budget constraints while maintaining high quality \nDrive cross-functional teams including design, test, product engineering, validation, marketing, systems, applications, operations, planning, various factories, and vendors as Program Manager to meet project milestones and objectives. \nManage several key projects in parallel or singular large program \nContinuously reviews program progress, proactively identify risks and collaboratively develops and drives risk mitigation efforts \nCollaborate with cross-functional and peers from other business groups to drive collaboration and harvest best practices and lessons learned to keep the business group in sync with One Renesas methodologies, tools and systems \nDrive execution initiatives and process improvements at the functional, cross functional and business group level \nMonitor and report on project progress, including key performance indicators and metrics, to senior management and stakeholders. \n\n \nResponsibilities may include: \nCollaborate and work in a team environment with Design, Applications, Test, Marketing, Manufacturing, Quality and Reliability in all aspects of new product development, production release to accomplish goals and objectives \nDesign bench evaluation PCBs (printed circuit boards) and generating characterizations programs for bench evaluations \nPerform evaluation, debug and characterization of integrated circuits to ensure they meet the product requirement specifications and manufacturing requirements \nWork with failure analysis (FA) to determine root cause of any reliability and qualification failures \nKnowledge of statistics and tools (example: Spotfire) to analyze large amounts of characterization data and determine and set production test limits and predict yield data \nWork with process and package technology development to develop and qualify technologies for new product development \nWork closely with the global manufacturing facilities to address customer specific product quality, yield management and cost reductions issues on mature products. Scope of work could include product spins and derivatives \n\nBachelor’s degree in electrical engineering \n\n7+ years of hand`s on technical program/project management experience leading cross functional teams to develop broad market or custom Power/Analog/ Mixed-Signal products for commercial, industrial or automotive applications with at least 10  years of experience working in the Semiconductor domain \n\nSolid understanding of Semiconductor Manufacturing, Development and Management \n\nAbility to work in a team setup comprising of other functional groups \n\nStrong time management skills that enable on-time project delivery \n\nDemonstrated ability to build strong, influential relationships \n\nAbility to work effectively in a fast-paced and rapidly changing environment \n\nAbility to take the initiative and drive for results \n\nStrong problem solving, verbal and written communications skills \n\nAbility to multiplex between projects and be able to maintain project schedules \n\nFamiliarity with JEDEC / AEC Qualification standards \n\nFamiliarity with ATE tester platforms (Teradyne / Eagle) \n\nKnowledge of statistics and tools (example: Spotfire) to analyse large amounts of characterization data and determine and set production test limits and predict yield data \n\nKnowledge of back-end semiconductor processes like Wafer Fabrication, Bump, Packaging, Assembly and Test is an asset. \n\nWorking experience in a high-pressure environment, competing priorities and tight turnaround times. \n\nStrong communication, presentation, and leadership skills; Ability to lead technical discussions and summarize outcome for executive level status reporting. \n\nProficient with industry standard project management tools such as MS Project, Jira, SharePoint, DFMEA, Root Cause Analysis , Confluence, Microsoft OneNote \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "PMTS - DFT Architect", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-18T04:52:00+00:00", "url": "https://global-external-amd.icims.com/jobs/93661/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. PMTS SILICON DESIGN ENGINEER THE ROLE: As a member of Circuit Technologies (CT) Team, you will architect, develop, and lead the DFT Design and Integration of cutting edge DFT structures including SCAN, ATPG, MBIST, BSCAN. In this role, you will work with the lead SoC/chiplet and IP architects to define future DFx architectures and contribute to product specifications, micro-architecture specifications, performance, and power trade-offs. The role will work from early concept development through the development phases to final production. THE PERSON:  In this role, you will collaborate with a network of expert architects and designers around the world where collaboration and communication skills are critical to the success of this role, and excellent organization skills are essential. You will approach sophisticated problems with a firm methodology and problem-solving technique and conduct experiments and analysis to formulate recommendations and next steps for other colleagues, and SOC/chiplet and IP design teams located in across multiple time zones and geographies. You will formally present your findings to co-workers, teams, and customer engineering teams. KEY RESPONSIBILITIES: Develop next-generation SoC/chiplet and IP debug and observability solutions that enable secure, scalable, and robust silicon bring-up, validation, and post-silicon debug. Partner with architecture and SoC/chiplet and IP design teams to define and execute a comprehensive Design-for-Excellence (DFX) strategy spanning debug, test, validation, reliability, and manufacturability. Collaborate with technology, silicon validation, product engineering, and manufacturing teams to establish DFX architectures that support both functional operating modes and manufacturing test requirements. Drive cross-functional alignment on DFX requirements, use cases, and end-to-end implementation flows across AMD engineering organizations. Evaluate and deploy AI-driven methodologies to streamline DFX planning, insertion, verification, coverage analysis, and implementation, improving quality, consistency, and scalability while reducing manual effort and time-to-deployment. Define metrics, methodologies, and automation frameworks to ensure DFX solutions meet product quality, testability, debug, and production readiness objectives across multiple programs and technology generations. PREFERRED EXPERIENCE: 10+ years of experience in SoC/chiplet and IP design, DFX architecture, or related silicon development disciplines. Strong understanding of DFX implementation and integration within complex, large-scale SoC/chiplet architectures. Deep knowledge of DFT methodologies and infrastructure, including scan, ATPG, MBIST, JTAG 1149.x/boundary scan, and advanced debug and test features. Solid understanding of SoC clocking, reset, power management, and low-power design architectures. Strong analytical, organizational, and communication skills with the ability to collaborate effectively across diverse engineering teams and disciplines. Demonstrated ability to decompose complex technical problems, evaluate tradeoffs, and develop solutions from both architectural and implementation perspectives. Experience applying AI and data-driven techniques to improve engineering productivity, including DFX requirement analysis, insertion planning, verification, coverage assessment, validation, and design quality optimization. Ability to leverage modern AI-assisted engineering workflows and tools to accelerate debug, reduce manual effort, improve consistency, and enable earlier identification of design and DFX risks. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-PM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "IC Verification Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-10-18", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/IC-Verification-Engineer_R027363", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nJob Description:\n·       Architect and develop scalable and reusable Testbench environment using the framework of Verification Methodologies.\n·       Drive Test plans for all features for Block/Core/SOC and Write Functional coverage for these features.\n·       Build pseudo-random tests to verify and get to full Functional coverage and bring the Verification to closure\n·       Debug Regression failures, analyze Functional Coverage gaps and improve tests to cover the gaps\n·       Work with other members of the team, guide/mentor junior team members\n·       Lead the documentation of verification strategy including Test plans, Verification Environment, pseudo-random tests, etc. Lead reviews with design/architecture.\n·       Driver Verification quality and Efficiency improvements\n \nMandatory Requirements:\n·       Bachelor’s degree in electrical/Electronics/Equivalent with 12+ years of relevant experience or Master’s degree in Electrical/Electronics/Equivalent with 10+ years of relevant experience\n·       10+ years of experience in developing complex Verification Environments, developing Test plans, Functional coverage and pseudo-random testing\n·       Must have gone through a full ASIC cycle right from Architecture development to Tapeout with full focus on Verification leading a Core\n·       Very proficient in System Verilog and Verification Methodologies like UVM/VMM\n·       Good debug skills in analyzing regression failures and understanding of complex designs\n·       A good understanding of a complex protocol like PCI Express or other multi-layered protocol\n \nThese requirements are a plus:\n·       Experience in PCIe protocol\n·       Comfort with Makefiles\n·       Experience with Verifying with other protocols like AXI\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "IC Verification Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-10-18", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/IC-Verification-Engineer_R027362", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nJob duties include:\n·       Build Test plans with all features for Block/Core/SoC and Write Functional Coverage for the features, participate in Reviews\n·       Write scalable and re-usable test benches, using the framework of the verification methodology\n·       Develop Pseudo-random tests to verify and get to full Functional Coverage\n·       Debug Regression failures, analyze Functional coverage gaps and improve tests to cover the gaps\n·       Document verification strategy including Test plans, Testbench, Random tests, etc.\n \nRequirements:\n·       Bachelor’s degree in electrical engineering or related degree with 5+ years relevant experience or master’s degree in electrical engineering or related degree with 3+ years relevant experience\n·       Must have working knowledge of System Verilog and Verification methodologies like UVM/VMM\n·       Should have good command of Object-Oriented Programming principles.\n·       Have experience writing Functional Coverage, pseudo random tests\n·       Knowledge of PCI Express protocol is a plus\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Senior SOC Design Engineer - Networking Group", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-18", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-SOC-Design-Engineer---Networking-Group_JR2019778", "is_hardware": true, "platform": "workday", "jd_text": "We are currently seeking an expert SOC Design and Integration Engineers with strong design fundamentals to work in Networking chip design group. You'll join a group of hardworking engineers to craft and implement the next generation innovative DPUs and Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing best high-speed communication devices, delivering the highest efficiency and lowest latency! The Networking Chip Design team in India is a new team which is growing at a fast pace.\n\nWhat you'll be doing:\nYou are encouraged to understand all features of a given project and define project milestones based on internal roadmaps, assign them and track them through agile framework\n\nDefine and develop system-level methodologies, tools, and IPs to build subsytems in an efficient and scalable manner.\n\nWork with SOC Assembly team and drive cross-functional teams towards SOC milestone execution.\n\nBe responsible for integrating all the pieces for a given defined project milestone and deliver the model to relevant teams for further verification at cluster/sub-system/SOC/emulation levels.\n\nWhat we need to see:\nBS (or equivalent experience) / MS with 3+ years of practical semiconductor design and architecture experience building complex SoC’s.\n\nMust have firsthand experience & solid understanding of all phases of SOC development in multiple ASIC projects including ASIC architecture, Micro-Architecture, RTL design, verification, timing closure & Physical design.\n\nExposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.).\n\nC/C++ programming or python or any other industry-standard scripting language experience desirable.\n\nExperience working with software teams to tightly define the HW/SW interface including control/status registers, interrupt and error handling.\n\nHands on experience in successful tape outs of multiple sophisticated, high-volume SoCs in advanced process nodes.\n\nExposure to various Chip Design Functions to be able to collaborate and tackle sophisticated cross functional problems.\n\nExcellent verbal and written communication skills to interact with cross functional teams to build consensus.\n\nExperience in synthesis, physical design and DFT is a plus.\n\nExperience in RTL Build and Design Automation is a plus.\n\nWays to Stand out from the crowd:\nChip lead type of technical leadership experience on delivering complex SOCs for enterprise and/or HPC applications.\n\nExperience in RTL coding and debug, as well as performance/power/area analysis and trade-offs\n\nExperience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area.\n\nPrior experience of smartNIC and/or high-speed interconnects.\n\nStrong coding skills in Perl, Python, or other industry-standard scripting languages.\n\nKnown throughout the technology industry as a top employer, NVIDIA delivers highly competitive salaries and a thorough benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/\n\nNVIDIA is committed to encouraging a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior ASIC Design Engineer - XBAR IP", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-18", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-ASIC-Design-Engineer---XBAR-IP_JR2020168", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking passionate, highly motivated, and creative senior design engineers to be part of its Graphics team working on the design of state of the art memory subsystem components used in their industry-leading Graphics Processors. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n\nIn this position, you will be expected to make architectural trade-offs based on features, performance requirements and system limitations, come up with micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. You will work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and backend teams to accomplish your tasks.\n\nWhat you’ll be doing:\nOwn micro-architecture and RTL development of design modules.\n\nMicro-architect features to meet performance, power and area requirements.\n\nWork with HW architects to define critical features.\n\nCollaborate with verification teams to verify the correctness of implemented features.\n\nCo-operate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable.\n\nInteract with FPGA and S/W teams to prototype the design and ensure that S/W is tested.\n\nWork on post-silicon verification and debug.\n\nWhat we need to see:\nBS / MS or equivalent experience.\n\n5+ years of design experience.\n\nExperience in RTL design of complex design units for at least two or three projects.\n\nExposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).\n\nDeep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.\n\nExpertise in Verilog.\n\nWays to stand out from the crowd:\nDesign experience in memory subsystem or network interconnect IP.\n\nGood debugging and problem solving skills.\n\nScripting knowledge (Python/Perl/shell).\n\nLeadership experience in leading small 2-3 member teams.\n\nGood interpersonal skills and ability & desire to work as a part of a team.\n\nNVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.\n\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "CAD Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-18", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/CAD-Engineer_JR2014480-1", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by phenomenal technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. Doing what’s never been done before takes vision, innovation, and the world’s best talent. We are now looking for Design Automation Tool development Engineers for our Tegra SOC development group. As the Lead, you will be responsible for architecting and crafting end-end tool flow to auto-generate system fabrics, sub-systems and SOC hierarchies, keeping user interface, maintainability and scalability in mind.\n\nOne should possess Strong software development skills and a dedication to high quality work. A proven track record to conceptualize, design and implement modular and robust EDA tools with well thought out APIs and interfaces would make you an excellent fit. Having a deep understanding of object oriented programming is a prerequisite for this role. If you have a zeal to make things better, we will have an excellent match for our needs.\n\nWhat you’ll be doing:\nDefine next gen EDA workflows for the world's top chip designers and verification engineers.\n\nArchitect and develop tools, methodologies that bring AI in chip design cycle.\n\nAnalyze productivity bottlenecks, improve data analytics and visualizations of day-to-day workflows\n\nDebug interesting, complex, and important problems that impact the team\n\nWhat we need to see:\nBS/MS in Computer Science or Computer Engineering or Electrical Engineering or equivalent experience\n\n2+ years of relevant work experience\n\nStrong problem-solving abilities and a passion for debugging\n\nSoftware architecture, development, & testing experience\n\nSolid understanding of Linux and excellent coding skills (Perl/Python)\n\nExcellent communication and interpersonal skills\n\nWays to stand out from the crowd:\nExposure to RTL design/verification tools (VCS or equivalent simulation tools, debug tools like Verdi) and methodologies (UVM or equivalent)\n\nExperience implementing scalable infrastructure solutions with frontend UX, RESTful APIs,  database, visualization, and backend automation.\n\nExperience in deploying ML components in various stages of tool.\n\nLinux administration experience, revision control and CI/CD systems such as Jenkins\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "ASIC Design Engineer - Performance Monitoring", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-18", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/ASIC-Design-Engineer---Performance-Monitoring_JR2027619", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA System-On-Chip (SOC) group is hiring for an ASIC Design Engineer! The complexity of the chips we build has increased manifold over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand. We are looking for a top ASIC Design Engineer to join our team. In this role, you should have real passion for RTL design implementation and methodologies that enable high quality system-level IP design.\n\nWhat you'll be doing:\nBe an integral part of the team defining and developing system-level RTL and methodologies to measure performance on the industry's leading GPUs/SOCs.\nDesign and implement RTL features - work through the entire design cycle for SOC.\nRun and debug RTL checks to ensure design quality (e.g. CDC, RDC, Lint, Synthesis, Logic-Equivalence and more)\nDefine, develop, and automate flows and methodologies to efficiently build and support a system-level IP\nWork with architects, designers, verification and SW engineers to accomplish your tasks.\n\nWhat we need to see:\nB.Tech or M.Tech in Electronics or Computer Engineering.\n3+ years of relevant industry experience.\nExperienced in RTL design (Verilog), System-On-Chip design/implementation flows, and design automation.\nGood understanding of SOC/IP (u)architecture (e.g., data flow, control, multiple clock/power domains handling, latency analysis).\nStrong coding skills in Perl, Python or other industry-standard scripting languages.\nExcellent debugging and analytical skills.\nExposure to design and verification tools (dc_shell or equivalent synthesis tools, VCS or equivalent simulation tools, debug tools like Debussy, GDB).\nGreat communication and collaboration skills to interact within the team and with cross functional teams.\nAdept at using AI tools to enhance productivity and solve complicated problems\n\nNVIDIA is widely considered one of the technology world’s most desirable employers. We employ some of the most forward-thinking and innovative people in the world. Are you passionate about joining our life’s work to amplify human imagination and intelligence? If you are creative, collaborative, and have real passion for design, methodology, and automation, we want to hear from you!\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Memory Layout Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-10-18", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Memory-Layout-Design-Engineer_R027427", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nJob Requirements:\n- Bachelor's degree with 12 years of experience or a Master's degree with over 10 years of experience.\n- Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - Calibre & Hercules).\n- Strong layout knowledge in submicron processes (e.g., 7nm, 5nm, 3nm, 2nm).\n\nKey Responsibilities:\n- Understand and apply layout guidelines, new process rules, and technical requirements for high-quality layouts.\n- Manage scheduling, timelines, and layout floor-planning.\n- Ensure end-to-end deliverables are completed with high quality and within the planned schedule.\n- Adapt quickly to new methodologies and communicate effectively with the SOC and library teams.\n\nSkill Set(Memory):\n- Strong experience in memory layout design and physical verification (LVS, DRC, ERC, Antenna, Electro Migration).\n- Experience with Cadence Layout tools (Virtuoso XL, VXL, or EXL) and Calibre verification tools.\n- Proficiency in floor-planning, hierarchy layout, and chip integration.\n- Solid understanding of memory architecture and RC requirements, with the ability to plan signal and power routing.\n- Ability to lead teams, train junior engineers, and manage projects effectively.\n- Strong knowledge of memory layout topology; experience with memory compilers is preferred.\n- Knowledge of AI, layout automation, and script/SKILL programming is preferred.\n- Ability to lead new technology reviews to document layout methodologies, flows, and guidelines.\n- Self-reliant with the ability to work both independently and collaboratively.\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Senior SoC Design Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-18", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-SoC-Design-Engineer_JR2022790", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking a Senior SoC Design Engineer to design the next-generation SoCs. We are looking for special individuals to deliver innovative products. Together, we will build the next generation of life-changing SoCs. If you are a motivated individual who understands how complex SOC and Subsystems are built, has intimate knowledge of client requirements, and understands various development cycles, this is your place to be.\n\nWhat you'll be doing:\nDrive SOC execution working with all multi-functional teams to define, track and drive dependencies working closely with the SoC verification, DFT, STA, Low Power and Validation teams.\n\nDrive SoC Assembly, SoC level quality checks, Connectivity reviews and signoff, SoC level Lint and CDC, Bug Triaging, Code reviews and ECOs.\n\nParticipate in silicon architecture, micro-architecture reviews, collaborate with Architecture, SW/FW, Design, Modeling, Verification, Emulation, and Post-Silicon Validation teams to ensure comprehensive first-time right SoC design.\n\nCollaborate with IP development teams, and participate in, and support soft and hard IP identification, selection and IP licensing.\n\nIdentify candidates, hire, and mentor SoC Design engineers, and as a team, identify problems and inefficiencies in the process and propose solutions.\n\nWhat We Need To See:\nBachelor's or Master's degree or equivalent experience in Electronics and Communication Engineering or Electrical Engineering.\n\n3-12 years of hands on SoC Design experience, expertise in Verilog/System-Verilog, Knowledge of AMBA protocols - AXI, AHB, APB, SoC Clocks/RST/Debug architecture and sound understanding of peripherals ( USB, PCIE and SDCC)\n\nStrong coding skills in Perl, Python, or other industry-standard scripting languages.\n\nExperience in RTL Build flows and Makefiles, Synthesis is a plus.\n\nExperience working with SoC level floorplan team is an added advantage.\n\nBackground in developing tools and infrastructure using Perl or Python.\n\nExcellent analytical and problem-solving skills.\n\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Physical design Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-10-17", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Physical-design-Engineer_R-10067284", "is_hardware": true, "platform": "workday", "jd_text": "Generic Job Description (not Job Level specific): The Digital Physical Design Engineer / Architect is responsible for a physical implementation of IP, Subsystem or IC design. The individual is responsible from RTL synthesis to GDS implementation and optimization of design including floorplanning, routing, timing convergence (STA) including related design ECO and physical verification for fulfilling all Technology & reliability related rules, such as DRC/LVS/Electromigration/IR drops. The individual contributes to problem solving related to physical design. Contributes to define best Physical design strategy per technology node.\nMore information about NXP in India...\n\n#LI-9415", "jd_status": "stored"}, {"title": "Staff Engineer, Design Verification Engineering", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-10-17", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Staff-Engineer--Design-Verification-Engineering_R265644", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nPosition Requirements:\nMinimum BTech/BE degree in Electrical/Electronics/Computer science\n8+  years of solid  digital logic design experience in hands-on and/or technical leadership.\nStrong technical orientation to lead the activities -architecting and Design of key digital blocks in SoC Designs.\nMust have worked with cross-functional product development teams and the designs must be realized in Silicon (ASIC tapeouts, *not* FPGA)\nHands-on experience in the development of optimal micro-architecture by analyzing power, performance, and area tradeoffs\nExperience with Lint, CDC, formal equivalence, ECO flows and scripting\nStrong  Knowledge in Processor/SoC architecture.\nGood verbal and written communication skills to logically drive the  discussions effectively with teams spread geographically\nExperience in  technically mentoring junior engineers\nExperience with participating in Post Silicon issue debug is a definite plus\nKnowledge of DSP fundamentals will be an added advantage.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Senior Staff Digital Design Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-16T08:31:54.611000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000155938750-senior-staff-digital-design-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Job Purpose and Dimensions:\nDevelop micro-architecture and front-end digital design deliverables from concept to silicon with minimal supervision\nDevelop digital functional blocks for various power management ASICs\nPrincipal Accountabilities:\nLead optimized digital blocks design meeting functional and low power constraints and ensure spec compliance.\nMust have experience of defining Digital/Analog boundaries and digital design scope for Power Management ICs/Analog intensive ICs.\nMust have experience of defining the micro-architectures and sub-blocks for the ICs to ensure optimized Digital design, RTL design and Gate level netlist etc.\nMust be able to handle Clock Domain Crossing across multiple clock domains seamlessly and in a glitch free manner\nShould be able to lead/collaborate for Logic Synthesis, Formal verification, Power estimation and STA.\nShould have experience of OTP, MTP, Efuse read/writes, controller design and data bus handling, Register read/write, Trimming of Analog parts/functions, DFT architecture and integration. · Should be an expert of one or more Power Chip Communication I/Ps and protocols e.g. I2C, PMBUS etc.\nVerification test planning, feature extraction and verification test case development.\nMust have done multiple silicon debugs, root cause analysis of issues, design to silicon correlation etc. · Support DFT strategy and implementation.\nInterface with P & R for digital hand-off and post layout verification.\nPerform physical silicon device area and power evaluation where necessary.\nProduce high quality documentation for owned blocks.\nDevelop work-around solutions where necessary to overcome device errata including documentation.\nKey Performance Measures:\nMicro-architecture, functional, test plan specification delivered according to project schedule\nRTL coding using Verilog/System Verilog\nFirst time right success rate Pro-actively taking ownership of responsibilities.\nDeliver work in the agreed timescales as set by program schedule for all assigned tasks.\nKnowledge, Skills and Experience:\nExperience in Logic design /micro-architecture / RTL coding. · Must have hands on experience with Power product design, synthesis and timing analysis for complex Digital Circuits.\nExperience in Verilog/System-Verilog is a must.\nExperience working in semiconductor ideally PMIC with focus on mixed signal integrated circuits ·\nHands on experience developing block and top-level timing constraints for STA and P & R sign off Understanding of design constraints and synthesis scripts\nWork independently on straightforward tasks, with little direction from manager · Ability to propose innovative solutions\nResults-oriented and able to deliver on-time under a tight schedule\nCross cultural awareness and sensitivity\nProactive attitude about own role and contribution to company goals\nAbility to work both independently and part of a team\nExcellent command of verbal and written English\nConcise and precise communication and interpersonal skills within multi-site and multi-cultural environment\n\nDegree level qualification in Electronics Engineering\nKey Relationships:\nDesign team, in particular TPL (Technical Project Leader) and digital leads/manager\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Software Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-16T06:42:10.746000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000155919499-senior-software-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "About the team: Renesas Electronics is a dynamic, multi-cultural tech company where employees can learn, mentor and thrive. RE brings together the strong financial foundation of a multi-billion-dollar global operation and the flexibility and velocity of a smaller organization. We are developing technologies for the latest advances in datacenter computing, mobile computing, secured connected devices, autonomous driving, smart homes and factories and more. Our solutions are at the heart of products developed by the major innovators around the world. Join us and be part of what’s next in electronics.\nThis is an opportunity to join an industry leading Digital Power IC development team with Renesas Electronics leading Infrastructure power management product line. As part of one of Renesas’s most prominent Power Management Groups, you will develop Software to support leading datacenter operators and infrastructure hardware developers as they deploy our digital power control devices.\nWhat we need:\nThe software team is seeking a Senior SW Engineer who is technically savvy and is excited about working within a SoC development team to produce customer facing software to enable our customers. This position involves a wide range of challenges from interfacing with IC and firmware designers to working with marketing to present the IC products in intuitive ways.  As part of one of Renesas’s fastest growing product lines, you will have the opportunity to directly impact customer experience through work on software products that enable feature rich hardware to shine.  If you like problem-solving, working with systems involving SW/FW/HW, and switching between multiple languages and paradigms, we’d like to hear from you. If you seek a place to shine with no artificial barriers apply now!\nWhat You’ll do:\nDesign, develop, test, and maintain software that meets the needs of both customers and internal teams\nGather and drive clarity on software requirements from diverse groups including customers, application engineers, hardware, and firmware engineers\nContribute to both existing and new projects, covering a broad range of languages and scope. We use Python and Pyside(QT).\nAid in code reviews for fellow team members, as required\n\nSkills You’ll Need:\nBachelor’s or master’s degree in computer science or computer engineering\n 5+ years’ experience in software development required with Excellent organizational skills, attention to detail and accuracy.\nExcellent coding skills using Python and Good understanding and coding skills in UI development.\nExecutes creative software solutions, design, development and technical troubleshooting with ability to think beyond routine or conventional approaches to build solutions or break down technical problems.\nStrong understanding of Software Architecture and Design principles, Behavior-Driven Development and unit testing approaches.\nStrong sense of software quality and treats testing, code review and documentation as part of the job.\nSelf-motivated and proactive that be able to take ownership of a feature or module with limited supervision.\nExperience with RESTful API design and web technologies (HTML/JavaScript) is a plus\nExperience with basic electronics, microcontroller programming and bus communications strongly preferred.\nExperience in DevOps including JIRA, Confluence and GitLab preferred.\nMust have highly developed written and verbal cross-functional communication skills.\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, or national origin.\n\nRenesas Electronics Corporation (TSE: 6723) empowers a safer, smarter and more sustainable future where technology helps make our lives easier. A leading global provider of microcontrollers, Renesas combines our expertise in embedded processing, analog, power and connectivity to deliver complete semiconductor solutions. These Winning Combinations accelerate time to market for automotive, industrial, infrastructure and IoT applications, enabling billions of connected, intelligent devices that enhance the way people work and live. Learn more at renesas.com. Follow us on LinkedIn, Facebook, Twitter, YouTube, and Instagram.\nRenesas’ mission, To Make Our Lives Easier, is underpinned by our company culture, TAGIE. TAGIE stands for Transparent, Agile, Global, Innovative and Entrepreneurial. Our goal is to embed this unique culture in everything we do to succeed as a company and create trust with our diverse colleagues, customers and stakeholders.\nWe are committed to creating a diverse culture where everyone is included and feels a sense of belonging. For more information, please read our Diversity & Inclusion Statement.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Staff Digital Verification Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-16T05:36:52.390000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000155911659-staff-digital-verification-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Job Description:\nRenesas is seeking a Staff Digital Design Verification Engineer to join our team developing complex power management SoCs. These products integrate digital control, telemetry, fault management, communication interfaces, configurable peripherals, and advanced power-control functions for AI, datacenter, enterprise computing, networking, and high-performance power delivery applications.\nYou will independently own verification of significant blocks and features from planning through closure. The role combines hands-on UVM development, coverage-driven verification, complex debug, and close collaboration with architecture, RTL design, firmware, analog, validation, and systems teams.\nResponsibilities:\nOwn verification of complex digital blocks or major SoC features from requirements analysis through coverage closure.\nDevelop feature-based verification plans from product, architecture, and microarchitecture specifications; identify gaps, ambiguities, corner cases, and risks.\nBuild and extend reusable SystemVerilog/UVM environments, including sequences, monitors, scoreboards, checkers, assertions, and coverage models.\nDevelop constrained random and targeted tests for normal operation, error handling, recovery, and system-level interactions.\nDrive functional, code, toggle, FSM, and assertion coverage closure using regression and coverage data.\nDebug RTL, testbench, assertion, integration, and regression failures; collaborate with design and firmware teams to isolate issues and verify fixes.\nAutomate regression, triage, reporting, and analysis workflows using scripting and modern engineering tools.\nCommunicate status, risks, dependencies, and closure evidence clearly; provide technical guidance to less-experienced engineers.\n\n \n\nBachelor's or master's degree in electrical engineering, Computer Engineering, Computer Science, or related field.\n7 or more years of relevant digital design verification experience, or equivalent directly applicable experience.\nDemonstrated ownership of a complex block, subsystem, or major feature from verification planning through closure.\nStrong proficiency in SystemVerilog, UVM, constrained random verification, functional coverage, and SystemVerilog Assertions.\nExperience translating specifications into test plans, test scenarios, checkers, scoreboards, assertions, coverage models, and closure criteria.\nHands-on experience developing and debugging reusable UVM environments and analyzing complex regression failures.\nStrong RTL and testbench debug skills, with the ability to distinguish design, environment, test, firmware, and specification issues.\nWorking knowledge of digital design fundamentals, including state machines, clocks and resets, interrupts, register interfaces, memories, and clock-domain crossings.\nProficiency in Linux and at least one scripting language such as Python, Bash, Perl, or Tcl.\nAbility to work independently and collaborate effectively across architecture, design, firmware, analog, validation, and systems teams.\nPreferred Qualifications:\nExperience verifying complex SoCs, power management ICs, voltage regulators, digital controllers, or mixed-signal products.\nExperience verifying RTL interfaces to embedded processors, memory-mapped peripherals, and firmware-controlled hardware features.\nFamiliarity with PMBus, AVSBus, SVID or SVI3, I2C, SPI, or similar control and communication protocols.\nUnderstanding of telemetry, fault and alert handling, power sequencing, multiphase regulation, or digital control loops.\nExperience with Cadence Xcelium, SimVision, vManager, JasperGold, Synopsys VCS, Verdi, or comparable tools.\nExperience with formal verification, gate-level simulation, silicon bring-up, or pre-silicon-to-silicon correlation.\nExperience improving regression infrastructure, coverage analytics, failure triage, or verification automation.\n\n \nWhat You Bring\nStrong technical ownership and a disciplined approach to verification completeness.\nAbility to reason beyond directed requirements and identify meaningful corner cases and feature interactions.\nClear communication of technical risk, progress, and signoff evidence.\nA collaborative mindset and interest in improving verification methodology and productivity.\n\n \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "SOC Verification Engineer-  SOC DDR, UMC", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-16T05:07:00+00:00", "url": "https://global-external-amd.icims.com/jobs/93412/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. THE ROLE (SOC Verification Engineer: SOC DDR, UMC): Work on SOC level verification activities, the person will be responsible for bringup verification of LPDDR5, UMC at SOC. Work with testbench team to bringup required infra Structure to bring up testbench and simulation. He will be responsible to coordinate with Design team for RTL delivery, work with design (IP, Subsystem, SOC) for RTL and TB collaterals and resolve issues. He should have good understanding of LPDDR5, UMC. He will be responsible to create TB collaterals for LPDDR5, UMC and phy bringup. THE PERSON: Engineer with strong self-driving ability. Need excellent communication skills (both written and oral) Strong problem-solving skills, go to person for SOC testbench, DDR verification, C/C++ Coding, UVM coding, Testcase coding, checkers and assertions. KEY RESPONSIBILITIES: DDR Simulation bringup (Has responsibility of TB, Testcase, coordination between design and dv team) Memory verification is key responsibility. Work with Memory architects to resolve issues seen in simulation. PREFERRED EXPERIENCE: Good understanding of LPDDR*, UMC, Nandflash, Nor Flash etc… Expertise in IP, Subsystem and SOC Verification with specialization in NLP Simulation. Strong hands-on experience in different SOC Verification activities, DDR Simulation, UVM, System Verilog, X86, C++, HW/SW co-verification, Scripting (phython) Test plan review, Debug/triage, Coverage, Strong Problem Solving, Automation and Debugging Skills, System bus protocol understanding including some of the common IPs like ACE, CHI, AXI, PCIe, DDR, memory controller etc. Comfortable with design/verification tools and flows like VCS, Verdi, SOC Connectivity, SV assertions, HW-SW co-simulations, UPF/CPF flows etc. Strong understanding of System integration, Make file flow, Verification Methodologies, Boot up sequence. JIRA based project management is a plus. ACADEMIC CREDENTIALS: BE/B.Tech/ME/MTECH/MS or equivalent in ECE/EEE/CSE 8-12 years of strong DV experience in CLK, RST verification, NLP simulation, IP, Sub System & SOC Verification. #LI-AB1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Memory Characterization Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-16T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721390246", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nJD: Memory characterization\n\nCandidate should have worked in memory domain and preferably candidate should have worked on Memory characterization, design and validation. Candidate should be familiar with layout parasitic extraction and challenges in deep submicron technologies.\nCandidates should be familiar with Spice decks and should be able to write spice decks, stimulus and test vectors and validate them.\nCandidates should have good knowledge and should have hands on experience with fast simulator tools.\nCandidate should have good memory design knowledge and should have debugging skills and should be familiar with waveform viewers etc. .\nCandidate should be familiar with NLMD + CCST .libs and should have hands on experience on generating libs and sign off QA checks etc.  .\nCandidate should be familiar with memory compiler flow enablement .\nCandidate should be familiar with validating libs with tight stimulus (sanity ) runs . Candidate should have ability to mentor, drive project independently and guide junior peers . Candidates with scripting knowledge will be preferred .\n \nEducation : Graduate or Post Graduate in Electronics /Electrical engineering with relevant(5-12 years ) experience in VLSI industry \n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Peripherals (Ethernet) Validation Engineer – Staff/ Sr. Lead / Senior Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-16T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721391153", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n\nKey Responsibilities:\n\nDevelop, execute and maintain comprehensive validation plans for Ethernet IP and SoC-level features across pre-silicon, emulation and post-silicon environments.\nCollaborate closely with IP architecture, design and systems teams to understand validation requirements and translate them into robust test content.\nLead bring-up, debug and root-cause analysis for complex cross-functional issues spanning hardware, drivers and platform integration.\nEnsure validation coverage is sufficient to provide high confidence in functional correctness, performance, power behavior, and production readiness.\n\nRequired Skills and Experience:\n\nStrong hands-on experience with any of these IPs like Ethernet controllers, NIC architectures, PCIe.\nProficiency in bare-metal and Linux driver development with strong C/C++ programming and debugging skills.\nSolid understanding of embedded systems, SoC architecture, peripheral subsystems and hardware/software interaction.\nExperience validating complex SoC features across functional, performance, power and system-level scenarios.\nExposure to AI server based interconnects like ESUN/UEC, UALink protocols are preferred.\nHands-on experience with lab and debug tools such as Lauterbach TRACE32, oscilloscopes, protocol analyzers and traffic-generation equipment.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "MTS - Analog Layout", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-10-16T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/44989750", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nKey Responsibilities\n \nTechnical Ownership\nLead full‑custom layout for complex Analog / Mixed‑Signal IP blocks, including but not limited to:Bandgap references, LDOs and regulators, Charge pumps (positive/negative)\nPLLs, delay lines, oscillators, IO & PHY‑related analog blocks\nTemperature sensors, bias circuits\nESD protection devices and clamps\n\nOwn layout quality from floor‑planning to tape‑out, ensuring:Device matching and symmetry, noise isolation and substrate strategies\nRobust power/ground planning\nYield, reliability, and DFM compliance\n\nWork closely with circuit designers to translate performance goals into layout strategies, especially in noise‑sensitive mixed‑signal environments.\n \nAdvanced Technology Expertise\nStrong experience in advanced FinFET nodes such as TSMC 3nm, 5nm, including:Fin quantization awareness\nMulti‑Vt, multi‑fin strategies\nAdvanced metal stack planning\n\nSolid background in planar CMOS technologies (e.g., 40nm, 65nm, 90nm) for analog robustness and legacy IP support.\nDeep understanding of foundry PDKs, layout‑dependent effects (LDEs), and process variability.\nLayout Verification & Signoff\nDrive and close DRC, LVS, ERC, ANTENNA, and reliability checks.\nReview and address issues related to:EM/IR, latch‑up, ESD window compliance\nDevice stress and matching degradation\n\nInterface with foundry and CAD teams for waiver management and signoff convergence.\nLeadership & Mentorship\nProvide technical guidance and design reviews for junior and mid‑level layout engineers.\nEstablish and document best‑known methods (BKMs) for AMS layout across nodes.\nDrive IP reuse, layout template development, and methodology improvements.\nAI usage proficiency\nStrong understanding of AI/ML and Generative AI concepts, with ability to identify high-value applications in circuit layout.\nProficiency in Python/scripting and EDA automation to develop AI-assisted layout and verification solutions.\nAbility to translate layout expertise into constraints, algorithms, datasets, and measurable optimization objectives.\nExperience developing, integrating, and validating AI-driven methodologies against traditional designer-driven flows.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Principal Engineer – Design Engineering", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-10-16", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Principal-Engineer---Design-Engineering_R4111-26-4", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nMicrochip’s Communications Business Unit (CBU) develops high-performance networking, connectivity, and edge compute semiconductor solutions that power communications infrastructure, data centers, automotive systems, aerospace and defense platforms, and industrial applications. Our global team works across the full product lifecycle to deliver innovative products that enable the world’s most demanding connected systems. \n\nThe CBU Product Development team is engaged through the full device R&D cycle from concept, design and implementation stages. Once a prototype is available, we support embedded software development and system validation lab testing through to mass-market production release. We are an experienced chip team working with the latest semiconductor development tools and methodologies in advanced process technologies to develop state-of-the-art network devices.\n\nWe are seeking a Principal Engineer in the CBU Product Development team who will be responsible for the design and implementation of digital integrated circuits at the block or top level of a device, solve challenging engineering problems with innovative solutions. You will collaborate with chip architects, subsystem leads and verification team members to deliver increasingly complex designs in a friendly and professional environment.\n\nResponsibilities may include:\n·         Contribute to the microarchitecture of communication semiconductor devices in partnership with team leads, mentors and device architects\n·         Design digital circuits based on leading-edge industry standards and market requirements\n·         Implement designs in System Verilog RTL code utilizing low-power design principles\n·         Synthesize designs into logic gates taking advantage of industry-leading tools and flows\n·         Provide floor-planning guidance and support to physical design/layout teams\n·         Integrate digital and analog circuits with Design-for-Test (DFT) techniques\n·         Verify physical timing specifications through Static Timing Analysis (STA)\n·         Support of products from Specification through to Production in collaboration with Engineers in Physical Design, Validation, Applications, Software/Firmware, Product Marketing and Production Engineering\n·         Develop areas of technical expertise to contribute to the wider team beyond individual deliverables or responsibilities\n\nRequirements/Qualifications:\n\n•      Bachelor’s or Master’s Degree in Electrical Engineering or Computer Engineering\n•      8+ years related experience\n•      Excellent analytical and debugging skills and the ability to proactively solve issues\n•      Proven ability to thrive on, learn and adapt to new methodologies and technologies\n•      Coding expertise in one or more of SystemVerilog/Verilog or VHDL.\n•      Experience using one or more of Tcl/Perl/Python, C/C++, XML\n•      Excellent verbal and written communication skills in English\n•      Experience with Lint, CDC, formal verification, logic synthesis, and static timing analysis.\n•      Understanding of physical design interactions, including timing, power, and congestion considerations.\n•      Knowledge of DFT, including scan, testability considerations, and DFT sign-off interactions.\n•      Proficiency in scripting languages such as Tcl, Perl, and/or Awk.\n•      Experience with Synopsys or Cadence tool flows for synthesis, verification or STA (an asset)\n•      Experience with 28nm and smaller silicon process technologies (an asset)\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Senior Engineer II - Backend Implementation", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-10-16", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Senior-Engineer-II---Backend-Implementation_R4302-26", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nMicrochip AES Design team looking for an experienced and motivated Backend Implementation Engineer to perform STA for larger SOCs. As a member of Implementation team, you will be responsible for timing constraints (SDC) generation, timing closure and Low Power checks for multiple blocks and top level. The candidate should have strong experience with STA tools like Tempus/Primetime. The candidate should have in depth knowledge of timing constraints.\nLocation: Bangalore, India\nJob Responsibilities:\nThe employee is responsible for implementation activities of multiple large & complex blocks & sub-system implementation from 16nm to 3nm and below technology nodes. The employee is expected to take ownership of Full Chip/Subsystem complex design & flow challenges, which would include:\nPerform Synthesis & STA timing closure for multi-million hierarchical complex designs.\nLead and drive team members to complete Implementation activities.\nComplete timing closure for blocks & top level in advanced nodes.\nDevelop constraints/SDC and perform pre & post-layout timing closure.\nPerform CLP and LEC for both full chip and block level.\nExperience on UPF/CPF would be an added advantage.\nOptimize design performance through timing closure and power optimization.\nDevelop and maintain design constraints and timing models.\nAnalyze and debug timing issues.\nInserting DFT logic for both block and top level.\nAnalyze Physical timing challenges and provide guidance for placement & CTS.\nOccasional travel needed.\nUse metric-driven techniques to help ensure first-pass working silicon.\nCommunicate regularly with the implementation and project team to resolve issues, and communicate status to Project Management.\n\nRequirements/Qualifications:\n\nThis position requires at least B.E/B.Tech/M.Tech in Electronics with 7+ years of Synthesis & STA experience in a fast-paced environment with following experience.\nExpertise in Implementation activities: STA, Crosstalk Analysis and timing closure.\nMust have understanding of DFT insertion.\nExpertise with Synthesis & STA Tools (Genus, Fusion Compiler, Primetime or Tempus).\nExperience on Conformal LEC and CLP will be added advantage.\nStrong programming knowledge in Perl, TCL, and/or Shell and Python Scripting\nExcellent oral and written communications skills to work with teams across the globe\nStrong understanding of timing closure and power optimization techniques\nMust have good understanding of Verilog.\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Lead Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-10-16", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Design-Engineer_R56670-1", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nAbout the Role\nWe are looking for a Lead Design Engineer to provide hands-on execution across Synthesis, LEC, CLP, and UPF/power-intent flows for advanced ASIC/SoC designs. This role is execution-focused with growing ownership: debugging synthesis and LEC issues independently, contributing to CLP sign-off, and writing constraints and ECO scripts, while working closely with the Team on complex escalations.\nKey Responsibilities\nRun and debug LEC sign off on design blocks; investigate and resolve NEQs and constraint mismatches\nWork on Genus synthesis runs to improve QoR, debug SDC/constraint issues.\nSupport CLP flows\nWrite and maintain ECO scripts and timing/power constraints for design blocks\nIndependently triage and document issues, escalating complex or systemic issues as needed.\nCollaborate with PD, DFT, and RTL teams to resolve cross-functional issues affecting synthesis/LEC/CLP closure\nPrepare clear status updates and technical summaries for internal tracking\nRequired Skills\n4–7 years of hands-on experience in ASIC synthesis, LEC, and/or low-power verification flows\nWorking knowledge of Cadence Genus and Conformal (LEC and/or CLP)\nFamiliarity with UPF/CPF-based power intent (IEEE 1801)\nScripting proficiency in Tcl, Perl, or Python; comfortable in Unix/Linux based environments.\nSolid understanding of digital design fundamentals, STA basics, and low-power architecture concepts\nStrong communication skills and ability to work independently on assigned blocks\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Senior System Integration and Validation Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-16", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-System-Integration-and-Validation-Engineer_JR2024494", "is_hardware": true, "platform": "workday", "jd_text": "The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. System Integration sits at the intersection of all of them. It is the layer where every architecture, design, software, and manufacturing decision meets reality. When something breaks late in a program, it usually breaks here first.\n\nWe are hiring a Senior Engineer to lead system validation, debug, and cross-functional alignment on one of our most consequential silicon programs. Your work will sit on the critical path of every flagship build, and the judgment you bring to ambiguous, multi-team failures is the difference between shipping on milestone and slipping! The two hardest, highest-leverage problems in this seat:\n \nWhat you’ll be doing:\nOwn end-to-end system validation of NVIDIA GPU, SoC, and platform programs — feature checks, PVT stress, system-stress campaigns at scale, and multi-unit fleet testing.\n\nLead debug of the hardest cross-stack issues — logic, signal integrity, power delivery, firmware, and software interaction — and drive them to root cause with reusable workarounds and productized fixes.\n\nDevelop test plans, scripts, and automation for next-generation chips ahead of physical builds, translating architecture, boot flows, high-speed I/O, and power and thermal dependencies into executable coverage.\n\nDesign and deploy AI-enabled debug and validation workflows used by the team — with explicit guardrails (evals, regression validation, false-positive handling) and measurable impact on cycle time, debug velocity, or escape rate.\n\nTranslate complex silicon and system risk into decision-ready options for technical and executive audiences — without padding or hand-waving.\n\nPartner with globally distributed teams across silicon design, DFT, firmware, software, manufacturing, and platform engineering — including counterpart engineers in India and other major hubs.\n\nLead crisis-mode debug task forces when a program is stuck, and convert the learnings into reusable methodology for adjacent programs.\n\nFind critical silicon and platform issues before they reach the customer — by shifting validation coverage left with system stress, PVT, and feature-interaction tests that catch escapes before software hardens. Your work shows up in DPPM, escape rate, and ramp confidence.\n\nBuild AI-enabled validation as a real capability, not a demo — by deploying debug, triage, root-cause hypothesis generation, and regression workflows with the evals and guardrails that make them trustworthy enough to gate production decisions.\n\nWhat we need to see:\nBTech/BE or MTech/ME in Electronics, Electrical, or Computer Engineering (or equivalent experience), and 6+ years of post-silicon validation, system integration, or platform debug experience on shipped GPU, CPU, or SoC products.\n\nHands-on debug depth across silicon, board, and software boundaries — logic design, signal integrity, power delivery, high-speed I/O, and PVT behavior — with strong EE fundamentals across SI/PI, power delivery, and thermal, and a working understanding of GPU, CPU, or SoC architecture across PC, Datacenter, or Automotive.\n\nAt least one specific example of taking an ambiguous, multi-team failure to root-cause closure with a productized fix, and a track record of leading a project team end-to-end through a real crisis with decision points you owned.\n\nDemonstrated AI-driven validation workflow you built or scaled, not just used — with adoption beyond yourself and measurable impact on debug velocity, coverage, or escape rate. You can describe the guardrails you put in place and where AI is dangerous in your workflow.\n\nWays to stand out from the crowd:\nA history of building reusable validation methodology, debug playbooks, or test frameworks that were adopted by other programs or teams — backed by patents, conference papers, invited talks, or recognized contributions.\n\nHands-on subsystem depth in HBM, SerDes or high-speed I/O, power and thermal, or advanced packaging — failure modes, debug instrumentation, and the tradeoffs that show up in production.\n\nExperience partnering deeply with a counterpart team in India or another major engineering hub — examples of shared culture, shared metrics, and shared on-call across geographies.\n\nAI work that goes beyond personal-copilot use — agentic workflows, RAG-grounded debug assistants, regression bucketing, or automated triage deployed at team scope with adoption metrics.\n\nNVIDIA is the world leader in accelerated computing, and our work powers AI, gaming, robotics, autonomous systems, and scientific discovery. We invest in our people with competitive benefits, flexible time off, and continuous learning, and we build a team where everyone can do their best work. Come help us build chips that change what is possible!\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior Package Layout Engineer - Hardware", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-16", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Package-Layout-Engineer---Hardware_JR2028204", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nNVIDIA's GPUs and SOCs are the world leaders in power, performance and efficiency. We are continually innovating to deliver new and creative, unusual solutions to extraordinary problems in a wide range of sectors. To this purpose, we are now seeking a hard-working Senior Package Layout Engineer who is committed to making a difference in the world through their contributions! This position will collaborate with Technical Package Lead and different design teams in the design and development of sophisticated, detailed layout of IC substrates for NVIDIA products. In addition, work with design teams to plan schedules, resolve costs, manufacturing, and electrical design issues.\n\nWhat you'll be doing:\nAs part of a Layout team, you will collaborate to implement high speed/density ASIC packages.\n\nPerform substrate breakout patterns for ASIC packages.\n\nOptimize package pinout incorporating system level trade-offs of pins assignment.\n\nHelp perform package routing, placement, stack-up, reference plane and power distribution using Cadence APD or SiP tool suite.\n\nPropose layout design trade-offs to the Technical Package Lead for resolution and implementation.\n\nConduct design feasibility studies to evaluate the Package design goals for size, cost, and system performance.\n\nDevelop symbols and CAD library databases using Cadence APD design tools\n\nDevelop methodologies to improve layout productivity\n\nWhat we need to see:\nHold a B.S. Electrical Engineering or equivalent experience\n\n5+ years experience in PCB Layout of graphics cards, motherboards, line cards or other related technology. Experience with HDI designs is a plus\n\nProven experience in substrate layout of wire bond and flip chip packages, preferred\n\nSignificant background with Cadence APD or SiP and/or PCB layout tools (including Constraint Manager)\n\nSolid understanding of high-speed design signal integrity practices\n\nExperience with Virtuoso and Calibre is a plus\n\nExperience using Valor is helpful\n \n\nNVIDIA is widely considered to be one of the technology world’s most desirable employers! We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative and autonomous, we want to hear from you.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior System Performance Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-16", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-System-Performance-Engineer_JR2027734", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a \"learning machine\" that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life's work to amplify human imagination and intelligence. Make the choice to join us today!\n \nAs part of the Silicon Solutions Team, we architect and deliver groundbreaking solutions for productizing NVIDIA's chips into consumer, professional, server, mobile, and automotive markets. Silicon characterization, correlation to arch & design expectations, finalize product specifications, develop productization techniques and infrastructure around it are part of our responsibilities. Dealing with challenges of the latest process node technologies is also part of the work. Join this dynamic team as a Senior System Perf Engineer, and help craft the future of computing in Bengaluru.\n\nWhat you'll be doing:\nLead the productization of Performance controllers from pre-silicon planning through bring-up, tuning, validation, and production.\nCollaborate with architecture, design, firmware, and software teams to define controller requirements & features , identify improvements and translate new capabilities into production-ready solutions.\nCharacterize and tune controller behaviour across workloads, operating conditions, silicon variation, and product power and thermal limits. Maximize the perf and Perf/Watt with-in architectural bottlenecks & limitations, Power/Thermal system limits to provide best customer experience for the products\nCorrelate silicon behaviour with pre-silicon expectations, debug & resolve complex problems during bring up and final closed loop performance stage involving silicon HW, firmware, software, power delivery network, system thermals etc.\nApply AI/ML and data-driven methods to analyze silicon characterization and HW telemetry data, identify anomalies and trends, accelerate controller tuning and improve debug as well as silicon validation execution efficiency.\n \nWhat we need to See:\nB. Tech or M. Tech in Electronics Engineering stream.\nAt least 5+ years of proven experience in silicon validation, system level design, and power/performance optimization.\nStrong understanding of aspects related to silicon power and performance, technology node impacts, Hardware and Software interactions at system level.\nHands-on experience with silicon bring up, validation and productization\nGood HW architectural understanding and orientation\nVery good problem solving and hardware debugging skills.\nStrong good data analysis and logical reasoning skills.\nStrong familiarity with HW lab environment.\nMust be a great teammate and ready to collaborate with global teams from diverse cultural backgrounds in a high energy environment.\n\nWays to stand out from the crowd:\nExtensive background in DVFS, voltage/frequency management, HW telemetries, Performance throttling, silicon protection mechanisms on advanced ASIC/SoC products.\nContributions that improved controller behaviour, silicon performance, power efficiency, thermal management, bring-up/productization methodologies.\nExperience connecting controller behaviour across simulation, silicon, firmware, and system-level measurements and converting findings into production tuning.\nExperience applying AI/ML to engineering workflows, such as controller tuning, characterization analytics, anomaly detection, or debug assistants deployed beyond personal use.\n\nWith every new architecture and process node, balancing performance against power and thermal limits becomes tougher. Our controllers are at the forefront of this issue: drawing out the performance the silicon was crafted to achieve while shielding it when workloads push its limits. If you like understanding dynamic silicon behaviour, addressing hardware-software challenges, and influencing NVIDIA products at scale, we'd love to connect!\n \n#LI-Hybrid", "jd_status": "stored"}, {"title": "Analog Design, Principal Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-16", "url": "https://careers.synopsys.com/job/bengaluru/analog-design-principal-engineer/44408/102024818528", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent over a decade designing analog circuits that have to move data at speeds most engineers never touch, and you know that the difference between a SERDES that works in simulation and one that works in silicon is a hundred small decisions about layout, process variation, and timing handoff. You are the kind of engineer who reads a SerDes standard and immediately starts sketching architectures that push beyond what the spec requires because you see where the bottleneck will be two years from now.\nYou do not wait for someone to tell you the PLL is the problem. You run the jitter budget, trace it back to the oscillator, and propose three solutions before the next design review. Taped-out circuits in FinFET nodes where a few femtofarads of parasitic capacitance can kill your bandwidth have taught you to work with layout engineers who understand that your redline is not optional.\nPresenting simulation data to a customer review panel and explaining why your adaptive equalizer architecture will handle their worst-case channel without adding another milliwatt is something you do comfortably. Mentoring matters to you, not because it looks good on a review, but because you remember the senior engineer who taught you how to read an eye diagram and you want to be that person for someone else.\nAt Synopsys, you will work on Multi-Gbps SERDES IP that goes into chips that power data centers, automotive networks, and AI accelerators. The problems are hard, the process nodes are cutting-edge, and what you design will ship.\nWhat You'll Be Doing\nReview high-speed SerDes standards (PCIe, Ethernet, USB, CXL) and translate them into transceiver architectures and detailed sub-block specifications for Multi-Gbps NRZ and PAM4 designs\nArchitect and design analog/mixed-signal circuits including TX drivers, RX front-ends, adaptive equalizers, PLLs, DLLs, bandgap references, regulators, oscillators, and ADC/DAC blocks for advanced FinFET and gate-all-around process nodes\nCollaborate with digital design teams on analog/digital co-design, calibration loops, adaptation algorithms, and timing handoff to ensure seamless integration and optimal performance\nWork directly with layout engineers to guide physical implementation, minimize parasitics, manage device stress and process variation, and ensure robust post-silicon performance\nPresent simulation results, design trade-offs, and architectural decisions in internal reviews, customer meetings, and industry panel discussions\nDocument design features, simulation methodologies, test plans, and characterization results, and support post-silicon bring-up and debug with electrical analysis and design iteration proposals\nAnalyze customer silicon data and field performance to identify improvement opportunities and drive post-silicon design updates for next-generation IP releases\nThe Impact You Will Have\nDefine the architectural direction for Synopsys SERDES IP, influencing product roadmaps and enabling next-generation connectivity standards across automotive, data center, and AI markets\nDeliver power, performance, and area improvements that directly affect the competitiveness of Synopsys IP in advanced process nodes and high-speed communication applications\nSolve post-silicon challenges that unblock customer tape-outs and ensure successful deployment of Synopsys IP in high-volume production chips\nMentor analog designers across the team, raising the technical bar for circuit design, simulation methodology, and design-for-reliability practices\nStrengthen Synopsys leadership in Multi-Gbps SERDES by contributing to industry standards bodies, customer engagements, and technical publications\nEnable faster time-to-market for customers by streamlining design and verification flows and reducing silicon respins through robust pre-silicon validation\nShape the future of high-speed analog design at Synopsys by driving innovation in adaptive equalization, low-power PLLs, and signal integrity for next-generation process technologies\nWhat You'll Need\nMTech/MS with 8+ years or BTech/BS with 10+ years of hands-on analog IC design experience in Electrical Engineering, Computer Engineering, or a related field\nProven track record of CMOS tape-outs in FinFET technologies with demonstrable experience in Multi-Gbps high-speed designs using NRZ and PAM4 modulation\nDeep expertise in SERDES sub-circuit design including TX drivers, RX front-ends, adaptive equalizers, PLLs, DLLs, bandgap references, regulators, oscillators, and data converters\nStrong understanding of analog/digital co-design, calibration and adaptation algorithms, and timing handoff between analog and digital domains\nProficiency with schematic entry, physical layout collaboration, design verification tools, and SPICE simulators (Spectre, HSPICE, or similar)\nExperience with scripting languages such as TCL, PERL, or MATLAB for post-processing simulation data and automating design tasks\nSolid grounding in system-level budgeting for jitter, amplitude, and noise, and familiarity with signal integrity challenges including packaging parasitics, crosstalk, and channel loss. Experience with ESD protection, custom digital design, and design-for-reliability considerations (electromigration, IR drop, aging, self-heating) is a plus. Prior experience with high-speed interleaved SAR ADCs is a strong plus.\nWho You Are\nYou can walk into a design review, look at a jitter waterfall plot, and pinpoint the architectural bottleneck in under five minutes without needing a slide deck\nYou push back when a specification does not make sense or when a layout decision will compromise performance, and you do it with data and a proposed alternative\nYou are the engineer others come to when a circuit is not behaving and simulation does not match silicon, because you know how to debug across domains and find the real root cause\nYou write clear, thorough documentation because you know that six months from now, someone else will need to understand your design choices and you want them to succeed\nYou stay current with emerging process technologies, circuit techniques, and industry standards because you know that what works in 7nm will not necessarily work in 3nm\nYou value collaboration and knowledge-sharing, and you take the time to explain a complex trade-off to a junior engineer or a non-technical stakeholder without losing the nuance\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Digital Design Engineer - DFT", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-10-16", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018763", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n In this position, you will be working on high-speed mixed-signal communication circuits using state-of-the art process technology, as well as be involved in the design of high performance digital circuits interfacing to leading edge analog circuitry as part of an overall system.\n\n Your responsibilities will include RTL coding, simulation, synthesis, timing closure, verification, evaluation, debugging of high-speed communication chips both at the circuit level and behavioral level.\n\n As a design engineer, you will prepare test methods and specifications, assist in preparation of application information, data sheets and demo boards. You will develop solutions to complex problems through assessment of various techniques and approaches. You will plan and organize work to ensure timely completion of many independent tasks with general instructions on routine tasks and with detailed instructions on new assignments.\n\n This position involves routine communication with a highly talented team of analog and digital design engineers to solve problems and present information as well as active participation in work groups, providing ideas and collaborative teamwork.\n\nQualifications\nMinimum requirements:\n\n3+ years of relevant experience\n\nA thorough understanding of digital logic design\n\nFamiliarity with the Verilog language and simulators\n\nA good understanding of analog functionality and exposure to analog IC design methods\n\nAbility to solve problems using a systematic approach\n\nPreferred qualifications:\n\nExperience with System Verilog\n\nDemonstrated strong analytical and problem solving skills\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nStrong time management skills that enable on-time project delivery\n\nDemonstrated ability to build strong, influential relationships\n\nAbility to work effectively in a fast-paced and rapidly changing environment\n\nAbility to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Design Verification Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-10-16", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018764", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n Texas Instruments is seeking Design Verification Engineer. In this role you will confirm the accuracy of designs for analog and mixed signal electronic parts, components, or integrated circuitry for analog and mixed signal electronic equipment and other hardware systems before pattern generation/mask development. The role will require working independently from the product development team who designed the devices to confirm adherence to known design rules, procedures, and best practices. Additional job functions include analyzing equipment to establish operating data and conducting experimental tests and evaluating results to confirm the device meets all requirements in the specifications. You may also run software simulations, selecting components and equipment based on analysis of specifications and reliability. As a Design Verification Engineer you may also review vendor capability to support product development. Requires a BS degree or equivalent experience in the design of equipment, components or circuitry.\n\nQualifications\nMinimum requirements\n\nMinimum education (i.e., bachelor's degree in electrical engineering)\n\nMinimum of 3 years of experience\n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "GPU Performance Verification Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-16", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/GPU-Performance-Verification-Engineer_JR0288229", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nBusiness Group:\n\nThe Data Center Group (DCG) is dedicated to advancing Intel's mission of creating world-changing technology. This team focuses on developing and validating GPUs to address the evolving needs of data-centric workloads, including artificial intelligence, machine learning, and high-performance computing. Your contributions will support Intel's broader goals of driving innovation and enabling breakthrough solutions for customers globally.\n\nKey Responsibilities:\n\nPerforms Performance verification of graphics logic components, including 3D graphics, media, and display, to ensure design will meet specification requirements.\nDefines and develops scalable and reusable IP verification plans, test benches, and architecture for verification environment to ensure coverage to confirm to graphics microarchitecture specifications.\nExecutes verification plans and defines and runs system simulation models to verify the design, analyse power and timing, and uncover bugs.\nReplicates, root causes, and debugs issues in the presilicon environment.\nFinds and implements corrective measures to resolve failing tests.\nCollaborates with GPU architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals.\nDocuments test plans and drives technical reviews of plans and proofs with design and architecture teams.\nMaintains and improves existing performance verification infrastructure and methodology.\nParticipates in the definition of verification infrastructure and related TFMs needed for Performance design verification.\n\nQualifications:\nBachelors or Masters with 2-10 years of Experience in Design Verification Experience.\nExperience with Verification of Subsystem and/or SoC having GPU/CPU.\nExperience in writing UVM based Tests, Assembly based tests, tests using high level languages like Open GL AND/OR Open CL.\nKnowledge of Graphics 3D and/or Compute Pipeline.\nKnowledge of Cache Controllers & Memory protocols like HBM, LPDDR, GDDR.\nKnowledge of Industry Standard Emulation Tools like Zebu/Veloce/Palladium.\nExperience of Performance Verification is a Plus.\nKnowledge of Performance Analysis/Bottleneck Analysis of 3D AND/OR Compute workloads is a plus.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Platform Hardware Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-16", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Platform-Hardware-Design-Engineer_JR0287602", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nAs a Platform Hardware Design Engineer, you will be at the forefront of designing and developing cutting-edge platform hardware solutions. In this role, you will drive the development of electronic components, PCBs, and integrated circuitry for advanced hardware platforms. Your work will directly contribute to delivering high-quality boards and systems that meet multidisciplinary requirements, ensuring compatibility and reliability across hardware and software components.\n\nBusiness group\nYou will be joining Intel Corporation, a global leader in technology innovation. Within Intel, the team focuses on hardware systems and subsystems to support Intel's broader goals of delivering industry-leading performance and efficiency. The group plays a critical role in developing and enabling platform hardware solutions that power Intel's technological advancements and deliver impactful results for customers.\n\nKey Responsibilities\n- Translate platform-level requirements into circuit and component-level specifications.\n- Design, develop, modify, and evaluate electronic parts, components, PCBs, and integrated circuitry for hardware platforms.\n- Conduct logical design of printed circuit boards, including component definition, schematic capture, and circuit trace routing rules.\n- Manage board layout activities from feasibility studies to tape out while meeting multidisciplinary platform requirements.\n- Assess BOM cost and availability data, balancing design trade-offs at the board and system levels.\n- Collaborate with architects, design engineers, verification engineers, and technicians to lead platform hardware power-on and debug activities.\n- Incorporate feedback from verification, validation, manufacturing, and customers to enhance development methods.\n- Perform design research, verification, testing, and utilization of components, materials, thermal solutions, and packaging for platform hardware.\n\nMinimum Qualifications\n- Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field with 4+ years of hands-on experience in hardware systems design OR Master's degree in a related field with 3+ years of experience OR PhD with no prior professional experience.\n- Proficiency in electrical schematic capture and PCB layout tools.\n- Hands-on experience designing PCBs, integrated circuitry, and other electronic components.\n- Demonstrated expertise in logical design and component definition.\n- Familiarity with BOM cost analysis and trade-offs at board and system levels.\n- Cadence  Concept HDL\n- BOM Cost Analysis, BOM Optimization\n- Vendor  Interaction & ODM interaction\n- High Speed Board design, TBT, LPDDDR5\n\nPreferred Qualifications\n- Strong communication skills and ability to work in multidisciplinary teams.\n- Experience collaborating with validation, verification, and manufacturing teams.\n- Ability to troubleshoot and debug complex hardware systems.\nWe encourage you to bring your unique perspectives and technical expertise to a team committed to innovation and excellence. Take this opportunity to make a meaningful impact and advance your career with Intel.\n\nQualifications:\nMinimum Qualifications\n- Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field with 4+ years of hands-on experience in hardware systems design OR Master's degree in a related field with 3+ years of experience OR PhD with no prior professional experience.\n- Proficiency in electrical schematic capture and PCB layout tools.\n- Hands-on experience designing PCBs, integrated circuitry, and other electronic components.\n- Demonstrated expertise in logical design and component definition.\n- Familiarity with BOM cost analysis and trade-offs at board and system levels.\n\nPreferred Qualifications\n- Strong communication skills and ability to work in multidisciplinary teams.\n-Hands on AI tool and experience on HW design\n- Experience collaborating with validation, verification, and manufacturing teams.\n- Ability to troubleshoot and debug complex hardware systems.\nWe encourage you to bring your unique perspectives and technical expertise to a team committed to innovation and excellence. Take this opportunity to make a meaningful impact and advance your career with Intel.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Staff Engineer- AMS Verification", "company": "Infineon", "location": "Bangalore (India)", "date_posted": "2026-10-15T15:43:59+00:00", "url": "https://jobs.infineon.com/careers/job/563808969067810", "is_hardware": true, "platform": "eightfold", "jd_text": "#WeAreIn to make sure that our circuits are designed to perfection. Are you in?\nPlay a key role in the development and implementation of advanced System Verilog real-number modelling methodologies for analog/mixed-signal(AMS) verification, optimizing speed and accuracy trade-offs for pre-silicon validation.\n\n Your role\nKey responsibilities in your new role\n\nPlay a key role in the development and implementation of advanced System Verilog real-number modelling methodologies for analog/mixed-signal(AMS) verification, optimizing speed and accuracy trade-offs for pre-silicon validation\nCollaborate with design and verification teams to define and refine functional verification plans for AMS blocks, ensuring proper integration into complex System-on-Chip (SoC) architectures\nDevelop and maintain custom verification frameworks that incorporate mixed-signal and digital simulation environments using industry-leading tools such as Xcelium and VCS\nCreate, validate, and deploy behavioral models for AMS components, ensuring compatibility with the digital verification environment and system-level requirements\nIdentify bottlenecks in current AMS verification flows and proposeinnovative solutions to enhance efficiency, scalability, and coverage\nProvide technical mentorship and training to junior engineers, fostering expertise in AMS verification techniques and best practices\n\nYour profile\nQualifications and skills to help you succeed \n\nA highly motivated AMS Verification Engineer with strong debugging and problem-solving skills, capable of driving verification excellence for advanced mixed-signal and SoC designs while working effectively in cross-functional global teams\n\nMinimum 8+ experience in AMS verification for complex SoCs and subsystem-level designs\n\nStrong proficiency in mixed-signal simulation environments using Cadence, Synopsys, or Mentor Graphics tool suites\nSolid understanding of digital design methodologies, Verilog HDL, RTL design practices, and analog circuit fundamentals; prior analog design experience is an advantage\nHands-on experience with behavioral modeling, including Verilog-D, Verilog-A, and Verilog-AMS\nExposure to SystemVerilog (SV) and UVM testbench development and enhancement from a mixed-signal verification perspective is desirable\nStrong functional knowledge of analog and mixed-signal building blocks, including comparators, op-amps, switched-capacitor circuits, ADCs, DACs, current mirrors, charge pumps, regulators, and clocking circuits\nUnderstanding of power management architectures, data converters, and analog functional specifications; loop analysis knowledge is a plus\nWorking knowledge of scripting languages such as Python, Perl, Tcl, SKILL, or equivalent automation tools\nDemonstrated ability to lead technical projects, collaborate across global teams, and thrive in a multi-site development environment\nExperience with industry-standard AMS verification tools, including:Cadence Xcelium + Spectre\nSynopsys XA-VCS\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "PD Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-15T15:01:00+00:00", "url": "https://global-external-amd.icims.com/jobs/93405/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. Physical Design Lead Job Summary We are seeking a highly motivated Physical Design Engineer to join our Silicon Design team. The candidate will be responsible for implementing high-performance ASIC/SoC blocks from synthesis to tapeout while meeting timing, power, area, and reliability targets. The role requires strong expertise in physical design methodologies, EDA tools, and advanced technology nodes. Key Responsibilities Perform physical implementation of digital blocks from netlist to GDSII. Execute and optimize: Floorplanning Power Planning Placement Clock Tree Synthesis (CTS) Routing Timing Closure Physical Verification Analyze and close: Setup and Hold timing violations Signal Integrity issues Crosstalk violations IR Drop and Electromigration (EM) DRC/LVS violations Work closely with RTL, Synthesis, DFT, STA, Power, and Verification teams. Develop methodologies and automation scripts to improve PD productivity. Support tapeout activities and signoff closure. Debug physical design issues across advanced technology nodes (5nm/3nm/2nm as applicable). Required Qualifications Education Bachelor's or Master's degree in: Electronics Engineering Electrical Engineering VLSI Design Computer Engineering Technical Skills Physical Design Flow RTL-to-GDSII implementation Floorplanning Power Grid Design Placement Optimization CTS Routing ECO Implementation Timing Closure Timing Analysis Static Timing Analysis (STA) OCV/AOCV/POCV concepts Multi-mode Multi-corner (MMMC) analysis Timing Signoff Closure Physical Verification DRC/LVS Antenna Checks Density Checks LEC awareness Low Power Design UPF/CPF concepts Power gating Multi-voltage methodologies Retention and Isolation strategies Scripting Strong scripting skills in: Tcl Perl Python Shell scripting EDA Tools Experience Experience with one or more: Synopsys ICC2 Fusion Compiler PrimeTime StarRC IC Validator Cadence Innovus Tempus Voltus Genus Siemens/Mentor Calibre DRC/LVS Preferred Qualifications Experience with advanced technology nodes (16nm/7nm/5nm/3nm). Knowledge of high-performance DDR, CPU, GPU, PCIE, AI/ML, Networking, or Data Center SoCs. Understanding of package and chiplet integration concepts. Experience in hierarchical and full-chip implementation flows. Strong debugging and problem-solving skills. Excellent communication and collaboration abilities. #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "PD Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-15T14:57:00+00:00", "url": "https://global-external-amd.icims.com/jobs/93404/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. Physical Design Lead Job Summary We are seeking a highly motivated Physical Design Engineer to join our Silicon Design team. The candidate will be responsible for implementing high-performance ASIC/SoC blocks from synthesis to tapeout while meeting timing, power, area, and reliability targets. The role requires strong expertise in physical design methodologies, EDA tools, and advanced technology nodes. Key Responsibilities Perform physical implementation of digital blocks from netlist to GDSII. Execute and optimize: Floorplanning Power Planning Placement Clock Tree Synthesis (CTS) Routing Timing Closure Physical Verification Analyze and close: Setup and Hold timing violations Signal Integrity issues Crosstalk violations IR Drop and Electromigration (EM) DRC/LVS violations Work closely with RTL, Synthesis, DFT, STA, Power, and Verification teams. Develop methodologies and automation scripts to improve PD productivity. Support tapeout activities and signoff closure. Debug physical design issues across advanced technology nodes (5nm/3nm/2nm as applicable). Required Qualifications Education Bachelor's or Master's degree in: Electronics Engineering Electrical Engineering VLSI Design Computer Engineering Technical Skills Physical Design Flow RTL-to-GDSII implementation Floorplanning Power Grid Design Placement Optimization CTS Routing ECO Implementation Timing Closure Timing Analysis Static Timing Analysis (STA) OCV/AOCV/POCV concepts Multi-mode Multi-corner (MMMC) analysis Timing Signoff Closure Physical Verification DRC/LVS Antenna Checks Density Checks LEC awareness Low Power Design UPF/CPF concepts Power gating Multi-voltage methodologies Retention and Isolation strategies Scripting Strong scripting skills in: Tcl Perl Python Shell scripting EDA Tools Experience Experience with one or more: Synopsys ICC2 Fusion Compiler PrimeTime StarRC IC Validator Cadence Innovus Tempus Voltus Genus Siemens/Mentor Calibre DRC/LVS Preferred Qualifications Experience with advanced technology nodes (16nm/7nm/5nm/3nm). Knowledge of high-performance DDR, CPU, GPU, PCIE, AI/ML, Networking, or Data Center SoCs. Understanding of package and chiplet integration concepts. Experience in hierarchical and full-chip implementation flows. Strong debugging and problem-solving skills. Excellent communication and collaboration abilities. #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "PD Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-15T14:48:00+00:00", "url": "https://global-external-amd.icims.com/jobs/93399/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. IR/EM Lead Job Summary The IR/EM Lead will drive reliability signoff and closure for advanced SoC and IP designs, ensuring robust power delivery and electromigration compliance across all project phases. This role requires deep expertise in power integrity, IR drop analysis, electromigration verification, methodology development, and cross-functional technical leadership to enable successful tapeouts at advanced process technologies. Key Responsibilities Lead all IR/EM activities for complex SoC and IP programs from floorplan through tapeout. Define and drive project-wide IR/EM closure strategies, schedules, and signoff criteria. Perform and review static and dynamic IR-drop analysis across full-chip and block-level designs. Lead electromigration analysis and closure for power grids, clock networks, signal routing, and package interfaces. Collaborate closely with Physical Design, Package Design, Power Architecture, Clock, RTL, CAD, and Technology teams. Identify power integrity risks early and drive mitigation plans through implementation and signoff stages. Develop and deploy methodologies, automation, dashboards, and best practices to improve IR/EM convergence. Guide teams in power grid architecture, decap planning, bump assignment, power distribution optimization, and reliability improvements. Drive technical reviews and communicate design health, risks, and recommendations to project leadership. Mentor engineers and provide technical leadership across multiple projects. Technical Requirements Strong expertise in Power Integrity and Electromigration analysis methodologies. Deep understanding of: Static and Dynamic IR Analysis Electromigration Verification Power Grid Design and Optimization Decap Planning and Analysis Voltage Drop Debug and Closure Advanced Node Reliability Requirements Hands-on experience with industry-standard IR/EM signoff tools. Strong scripting and automation skills (Python, Tcl, Perl, or similar). Strong understanding of advanced-node physical design implementation flows. Leadership Expectations Act as the primary technical owner for IR/EM signoff and closure. Drive technical decisions impacting product reliability and design quality. Influence implementation methodology across project and organizational boundaries. Lead root-cause analysis for power integrity issues and drive systematic improvements. Coach engineers and establish technical best practices for reliability signoff. Qualifications BS/MS in Electrical Engineering, Computer Engineering, or related discipline. Typically 5-15 years of experience in Physical Design, Power Integrity, Reliability Analysis, or Signoff Engineering. Proven experience leading IR/EM closure for large SoC designs through successful tapeout. Preferred Qualifications Experience with 5nm, 4nm, 3nm, or newer process technologies. Understanding of package and system-level power delivery networks. Familiarity with thermal analysis and reliability methodologies. Experience developing automation and signoff productivity frameworks. Strong communication and project leadership skills. Success Metrics First-pass IR/EM signoff readiness. Timely closure of power integrity and reliability issues. Improved methodology efficiency and signoff turnaround time. Reduced late-stage design risk and tapeout escapes. Effective mentorship and technical leadership across the organization. #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Sr Engineer, Design Verification", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-15T10:29:18.418000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000155723999-sr-engineer-design-verification", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Opportunity for a talented individual for their memory interface products.\nWe are looking for a candidate with a strong background in verifying complex integrated circuits.\nThe candidate needs to have skills that are up to date with the latest IC verification tools and flow.\nThe candidate will work closely with design, and verification engineering.\nIn addition, strong collaboration and communication skills are a must.\nDuties/Responsibilities:\nDevelop verification testbench components for chip/module level using System Verilog.\nUse high-level concepts (Object-oriented, UVM, etc) to develop an extendable environment.\nDefine and execute detailed verification plan from spec working with architects and designer engineers\nExperience in code coverage, functional coverage, assertions, cover groups, etc to achieve 100% verification completeness before tape-out.\nDebug tests, regression failures and participate in silicon debugging and analysis.\nUnderstanding or prior experience with Industry standard protocols like DDR4/DDR5/LPDDR5/DIMM (Dual In-line Memory Module) knowledge is preferred.\n\nBachelors or Masters in Electronics or Electrical Engineering with a minimum of 4-8 years of experience in design/verification management of highly complex projects.\nOrganized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required.\nMust be good in building verification environments preferably using the verification subset of high-level languages like System Verilog (UVM).\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "IP Networking & F5 Engineer", "company": "Ericsson", "location": "Noida,Uttar Pradesh,India", "date_posted": "2026-10-15T05:57:27+00:00", "url": "https://jobs.ericsson.com/careers/job/563121777428976", "is_hardware": true, "platform": "eightfold", "jd_text": "Join our Team\n\nAbout the Opportunity\nEricsson is looking for an experienced IP Networking & F5 Engineer to design, implement, manage, and troubleshoot enterprise networking and application delivery services, ensuring secure, reliable, and efficient network operations.\nWhat You Will Do\nDesign, configure, implement, and troubleshoot enterprise switching, routing, firewalls, and data center networks.\nManage IP addressing, subnetting, routing, network segmentation, and IP planning.\nAdminister HP ProCurve/Aruba switches, routers, and equivalent enterprise platforms.\nConfigure and support enterprise firewalls, security policies, and troubleshooting.\nImplement and maintain F5 BIG-IP solutions, particularly LTM and GTM.\nMonitor network services, resolve incidents, and perform root-cause analysis.\nCollaborate with infrastructure, security, application, virtualization, and storage teams.\nMaintain network diagrams, technical documentation, operating procedures, and configuration standards.\nParticipate in incident, problem, change management, automation, and continuous improvement activities.\nWhat You Will Bring\n6–8 years of relevant IT infrastructure and networking experience.\nStrong hands-on expertise in enterprise switches, routers, firewalls, and network troubleshooting.\nPractical experience with HP ProCurve/Aruba or equivalent platforms.\nStrong knowledge of IP networking, addressing, subnetting, routing, and IP planning.\nExperience in data center network design and implementation.\nHands-on experience with F5 BIG-IP, especially LTM and GTM.\nExcellent communication, stakeholder management, and collaboration skills.\nAbility to work independently with geographically distributed teams.\nGood to Have:\nVMware, vCenter, vMotion, and DRS experience.\nSAN and enterprise storage knowledge.\nWhat You Will Get at Ericsson\nMeaningful work supporting secure and resilient connectivity.\nGlobal collaboration and continuous learning opportunities.\nCareer growth across technical, architectural, and leadership roles.\nAn inclusive, flexible, and supportive work environment.", "jd_status": "stored"}, {"title": "DFT Architect", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-15T05:21:00+00:00", "url": "https://global-external-amd.icims.com/jobs/90055/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. Job Summary As a key member of the AMD Server CPU engineering team, you will play a critical role in ensuring the testability and manufacturing quality of next-generation EPYC Server SoCs. You will be responsible for Structural Design-for-Test (DFT) implementation, Automatic Test Pattern Generation (ATPG), Logic Built-In Self-Test (LBIST), and silicon bring-up support to achieve high-quality product delivery. Key Responsibilities Collaborate with Architecture teams to understand and define DFT architecture requirements. Work closely with RTL Design teams to ensure compliance with DFT design methodologies, rules, and best practices. Partner with Physical Design teams to implement DFT structures and achieve timing closure for test logic. Develop and execute ATPG strategies for stuck-at, transition, and other fault models using advanced test compression techniques. Generate, simulate, and validate high-quality manufacturing test patterns. Analyze coverage results and drive design enhancements to maximize fault coverage and test quality. Perform debug and root-cause analysis of DFT, ATPG, and LBIST-related issues throughout the design cycle. Collaborate with Product Engineering teams to support manufacturing test program development and qualification. Support silicon bring-up, characterization, yield improvement, and production debug activities. Develop and maintain automation tools, scripts, and flows to improve productivity and test quality. Drive continuous improvements in DFT methodologies, verification strategies, and automation infrastructure. Required Skills & Experience Strong understanding of DFT architecture, scan design, test compression, ATPG, and LBIST methodologies. Hands-on experience with ATPG tools such as Siemens Tessent (Mentor TK) or equivalent. Experience with scan insertion, fault simulation, coverage analysis, and pattern validation. Good understanding of Static Timing Analysis (STA) and timing closure concepts. Strong debugging and problem-solving skills with the ability to identify and resolve complex design issues. Proficiency in scripting languages such as Perl, Python, Tcl, or Shell. Familiarity with ASIC/SoC development flows and semiconductor manufacturing processes. Excellent communication and collaboration skills with the ability to work effectively in a global cross-functional environment. Preferred Qualifications Experience with large-scale CPU, GPU, AI, or Server SoC products. Knowledge of MBIST, JTAG, Boundary Scan, IEEE 1500, IJTAG, or related DFT technologies. Experience supporting silicon bring-up, failure analysis, and production ramp activities. Exposure to Emulation, Verification, or Physical Design flows is a plus. Education B.E./B.Tech., M.E./M.Tech., or equivalent degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field. 5+ years of relevant DFT/ATPG experience for Senior Engineer level. #LI-AA1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior System Verification Engineer", "company": "Ericsson", "location": "Bangalore,Karnataka,India", "date_posted": "2026-10-15T04:52:09+00:00", "url": "https://jobs.ericsson.com/careers/job/563121777110640", "is_hardware": true, "platform": "eightfold", "jd_text": "Join our Team\n\nAbout this opportunity:\nAt Ericsson, we are the world leader in 5G innovation and deployment, powering a connected future where technology improves the way we live and work. With unmatched expertise and market penetration in 5G New Radio (NR), we are shaping the future of communication and pioneering advancements that will lead us into the era of 6G. \n \nThe Opportunity:  \nReliability earns trust. As part of our RAN System Verification team, you will work in advanced lab environments to verify, troubleshoot, and deliver Ericsson’s 5G New Radio (NR) solutions on high‑performance General Purpose Processors (GPP), with sharp focus on performance, scalability and quality. You will validate system behaviour under high‑load traffic scenarios, ensure that capacity and performance targets are met, and influence release decisions across our global product portfolio.  \n\n \nWhat you will do:\nProvide technical leadership for end-to-end system verification of 5G features, shaping verification priorities from feature readiness to release in alignment with business strategy and customer outcomes \nAct as a technical specialist in system performance analysis using logs, traces, and KPIs such as throughput, latency, resource utilization, and QoS/QoE indicators to identify systemic bottlenecks and drive product-level improvements. \nLead complex, cross-layer investigations across PHY, MAC, RLC, PDCP, and IP, applying advanced root-cause analysis to resolve complex performance and capacity issues.  \nPerform requirement analysis for feature integration and verification to ensure alignment with customer expectations and network performance objectives. \nPerform capacity and performance verification of RAN systems under high-load traffic scenarios comprising Max supported UEs per cell/DU, throughput (DL/UL), control plane capacity and mobility under load. \nEstablish verification methodologies and quality standards that represent live network scenarios and provide coverage for performance, capacity, Stability and customer experience. \nProvide technical direction, coaching, and mentorship to verification engineers and contribute to the development of organizational competence in modern (AI) system verification practices. \nDrive continuous improvement of products, verification frameworks, test coverage, automation, CI/CD pipelines, and AI-assisted verification practices, improving efficiency, quality, and time to market. \nLead collaboration across RAN development, integration/CI, product management and other stakeholders organization to resolve issues and secure high-quality deliveries. \nLead customer trials and field issue reproduction, move quickly from symptoms to root cause and provide clear defect reports with actionable next steps.\n\nThe skills you bring\n\nBachelor’s or Master’s in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience. \n8 - 12+ years of hands‑on experience in system-level verification, deployment, integration, and troubleshooting of LTE/5G NR baseband and radio systems, including demonstrated technical leadership. \nStrong understanding of wireless communication systems (LTE/5G NR), RAN architecture and protocol stack, and 5G NR air‑interface technologies. \nDemonstrated experience analyzing and troubleshooting performance issues at PHY/MAC layer, including link curve verification, channel-quality assessment, and evaluation under diverse and adverse channel conditions. \nDeep expertise of system level KPIs (throughput, latency, resource load, QoS/QoE) and the ability to identify performance bottlenecks. \nExperience working with Channel emulators, fading technologies, traffic generation and test tools (for example UE simulators, Viavi, real UEs). \nAdvanced Linux skills and solid knowledge of IP routing, switching, and networking. \nDemonstrated success in influencing product, architecture, and release decisions through data-driven verification insights and technical judgment. \nProgramming, automation, and scripting skills (for example Python, Bash, Java) and solid understanding of CI/CD concepts. \nExperience with configuration management and automation tools (for example Git, Gerrit, Jenkins) in a modern development and integration environment. \nStrong problem solving and troubleshooting skills with a focus on verification improvements and innovation. \nDemonstrated customer focus, including experience supporting customer trials, reproducing field issues and assessing risk. \nNice to have: \nExposure to Cloud-Native RAN, O-RAN Architecture. \nExperience with commercial UE chipset platform testing (Qualcomm, MediaTek etc) and end‑to‑end performance validation. \nKnowledge of cloud‑native principles, containerization, and microservices‑based architectures.  \nFamiliarity with AI/ML tooling for test analytics and anomaly detection. \nSoftware development skills, particularly in Java and Python. \nWhy Join Us:  \nWork with global experts in a high-performing, innovative, and global engineering environment. \nWork on cutting-edge 5G technology and be at the forefront of 6G innovation. \nContribute directly to the quality of live networks and customer experience worldwide. \nBuild deep expertise in system-level performance, capacity and reliability engineering. \nFlexible work environment, career growth and a diverse, inclusive environment.\n“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”\n\nWhy join Ericsson?At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.\n \nWhat happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.\n \nPrimary country and city: India (IN) || Bangalore\nReq ID: 789643", "jd_status": "stored"}, {"title": "Digital Design R&D Engineer (Lead/Staff)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-15T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720749612", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nQCT Strategic PD team is actively seeking candidates skilled in RTL to GDS. You will be part of an elite team that develops innovative solutions and tackles challenging design problems\n\nAs a digital design R&D Engineer some of the key tasks are\nImproving Performance, Power, and Area (PPA) for the performance cores like GPU, AI, Modem and DDR\nDeveloping ML solutions (ECO and otherwise)  for faster and smarter timing closure for the SoC\nUse of Big-Data/ML/Analytics in digital design to guide better design choices, improve convergence times with better PPA metrics\n \nRequired Skills\nWorking knowledge inDigital VLSI implementation (netlist to GDS)\nPNR implementation (primary skill and knowledge)\nSTA (secondary skill)\n\nFamiliarity and understanding of ML algorithms and techniques.\nHands on experience with EDA tools (Primetime, FC, Innovus, Tempus, etc.)\nCoding with Python, TCL\n \nExpected Experience: 3 – 8 years of relevant product industry experience\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NOC DV Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-15T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721283297", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nRole Summary\nSeeking a highly skilled and self-driven Design Verification Engineer to lead verification of complex AI, Networking, Datacenter, HPC, and Interconnect IPs/Sub-systems. The candidate should demonstrate strong ownership, technical depth, and the ability to independently drive verification from architecture understanding through signoff-quality closure.\nKey Responsibilities & Skills\nExpert in SystemVerilog (SV) and UVM, with hands-on experience in building reusable verification environments, UVCs/agents, sequences, scoreboards, checkers, assertions, and coverage infrastructure.\nStrong expertise in verification planning, constrained-random verification, SVA, functional coverage closure, regression management, and signoff methodologies.\nProven ability to independently own and execute IP/Sub-System DV from specification review to verification closure.\nStrong debugging skills across RTL, protocol, architecture, performance, and testbench issues, with demonstrated root-cause analysis capability.\nExperience in verifying NoC, coherent/non-coherent interconnects, memory/cache subsystems, AI accelerators, or complex data movement fabrics.\nDeep protocol verification expertise in one or more of: PCIe (Gen4/5/6)\nUSB (USB3.x/USB4)\nEthernet (10G/25G/100G/400G+)\nCXL\nOther high-speed serial/networking protocols\n\nExperience with AI Scale-Up / Scale-Out Interconnects such as UAL, UMAC, eSUN, or equivalent accelerator cluster fabrics.\nStrong understanding of AMBA protocols (AXI, AHB, ACE, CHI) and coherency architectures.\nKnowledge of performance verification, QoS validation, congestion analysis, scalability testing, and system-level qualification.\nProficiency in Python, Shell, Perl, or Tcl for regression automation, infrastructure development, and productivity enhancement.\nFamiliarity with industry-standard simulators, debug tools, coverage tools, CI/CD workflows, emulation, and verification automation frameworks.\nStrong collaboration, communication, technical leadership, and execution skills with the ability to thrive in a fast-paced environment.\nPreferred Experience\nVerification experience in SoC, AI/ML Accelerators, Networking, Datacenter, Multi-Die, or HPC platforms.\nExposure to SystemC/TLM modeling, performance modeling, emulation/prototyping, and post-silicon correlation.\nTrack record of delivering first-pass verification closure for complex IPs and subsystems.\nQualifications\nB.Tech/M.Tech in Electronics, Electrical Engineering, Computer Science, VLSI, or related disciplines from reputed Tier-1 institutions (IITs, NITs, IIITs, BITS, or equivalent).\nRelevant industry experience aligned with the position level, demonstrating strong expertise in Design Verification, SV/UVM methodologies, protocol verification, and architecture-driven validation.\nProven history of technical ownership and successful delivery of complex IP, Sub-System, or SoC verification programs.\nIdeal Candidate\nA hands-on verification expert with deep protocol knowledge, strong debugging capability, and the ability to independently architect, execute, and close verification of next-generation AI and high-performance silicon designs.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NPU Physical Design Engineer (Lead/Staff/Sr Staff)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-15T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720953655", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nGeneral Summary\nPNR implementation for Qualcomm Hexagon NPU\nGood hands-on  experience on Floorplanning, PNR and STA flows\nGood knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc\nGood understanding on signoff domains– LEC/CLP/PDN knowledge, etc\nGood knowledge on Unix/Linux – Perl/TCL fundamentals/scripting\nPrincipal Duties and responsibilities:\nComplete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes.\nSignoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc)\nQuick learner with good analytical and problem solving skills\nQualifications:\n7+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NOC Design Verification Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-15T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721094633", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nAdditional Job Description\n\nLooking for an experience Verification Architect/ Engineer, who will be responsible Verification of next generation Infrastructure IPs (DDRSS, Memory Controllers etc.)  which goes into System-on-chip (SoC) for smartphones, tablets and other product categories. In this position you will be expected to plan and implement IP/Cluster/Formal verification flows for the Infra IPs. Also expected to coordinate with different Design and SOC teams throughout the IP development cycle.  \n\nJob responsibilities include \n·               Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage) \n·               Develop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench \n·               Work closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure \n·               Debug of regression signatures and identifying bug fixes \n·               Responsible for Quality sign off and required documentation \n·               Developing/Deploying scripts/tools for validation (Certitude, VC Formal, VPlan) \n·               Debug and root cause post silicon issues in collaboration with Design, SW and test teams \n·               Work with SoC level performance modeling team on latency, bandwidth analysis next-generation experiences and drives digital transformation to help create a smarter, connected future for all.\n\nAs a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nRequired skillset include \n·               Strong debugging, Analytical and problem-solving skills \n·               Expertise on UVM based verification  \n·               Knowledgeable about ARM bus protocols, Virtual Memory concepts, SoC system architecture \n·               Experience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved \n·               Communication and collaboration skills to work with a large world-wide design organization \n  \nDesired skillset includes \n·               Experience in designs optimized for low power - Dynamic clock gating, Logic/ Memory power collapse  \n·               Experience in verifying designs meeting Automotive Safety Integrity Levels (ASIL) \n·               Proficiency in Scripting languages (Python or Perl) for Automation initiatives, C/C++/SystemC for performance models \n·         Post-si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage \nQualification : \n·         Bachelor/Master’s Degree in Electronics & Communication / Micro Electronics \n·        3+ Years of Experience in IP verification or related\n·         Experience with UVM and ARM Bus protocols. \n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Serdes PHY Analog Design Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-15T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721526104", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nJob Function\nBDC SerDes Mixed-Signal design team is actively looking for experienced (8+ years) analog circuit designers to work on high speed SerDes PHYs. You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. \n\nResponsibilities\nHands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO, high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc.\nAnalog and or Digital PLLs for frequency synthesis and/or SerDes applications  Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. \nPLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) \n\nAbility to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up.\nWork closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY.\n\nSkills & Experience\nFor lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc.\nUnderstanding of advance Finfet process effects on designs and layout is required.\nExperience in using SPICE simulators, adexl & virtuoso.\nExperience with post-Si bring-up and debug is must.\nGood understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added advantage.\nMaster/Bachelor in Electronics\nShell/Perl-python scripting to automate circuit design and verification work.\nAble to work with teams across the globe and possess good communication and presentation skills.\n\nPreferred  \nMixed signal design experience  \n\nKeywords\nAnalog circuit Design, Rx, Tx, PLL, SerDes, PHY, Serializer, Deserializer, VCO, High-speed Trans receiver\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NPU STA/Timing Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-15T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720953656", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nResponsibilities:\nSTA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.\n\nTiming analysis, validation and debug across multiple PVT conditions using PT/Tempus.\n\nRun Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.\n\nEvaluate multiple timing methodologies/tools on different designs and technology nodes.\n\nWork on automation scripts within STA/PD tools for methodology development.\n\nGood Technical writing and Communication skills, should be willing to work in cross-collaborative environment\n\nExperience in design automation using TCL/Perl/Python.\n\nFamiliar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus\n\nFamiliar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo.\n\nEducation : B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI.\nPreferred Qualification/Skills\n5 - 10 years of experience in STA/Timing\n\nStrong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling\n\nHands-on experience with STA tools - Prime-time, Tempus\n\nHave experience in driving timing convergence at Chip-level and Hard-Macro level\n\nIn-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,\n\nKnowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)\n\nKnowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation.\n\nProficient is scripting languages – TCL, Perl, Awk\n\nBasic knowledge of device physics\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SoC Physical Design Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-15T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721321100", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nJob Description :\nBachelor's degree in Electrical Engineering with 8 to 15 years of experience in physical design.\n\nExperience managing complex Subsystem and Small team.\n\nExperience in synthesis, PnR, sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations.\n\nJob Requirement:\nExperience with demanding PPA requirement of complex sub-systeM/SOC, place and route, IP integration. \n\nExperience in low power design Implementation including UPF, multi-voltage domains, power gating. \n\nExperience with ASIC design flows and methodology of Physical design. \n\nUnderstanding of circuit design, device physics and deep sub-micron technology. Should have worked on multiple TO in advance technology nodes. \n\nPerson should also have good understanding of automation to drive the efforts to improve the PPA\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Principal Verification Engineer", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-10-15", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Principal-Verification-Engineer_R4165-26-8", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nVerificationOwn the verification of complex digital integrated circuits at the block, subsystem, or device level.\nUnderstand the device requirements and functional description to ensure compliance with specifications and error-free operation.\nPlan verification activities, develop testbenches, and execute tests.\nDevelop verification platforms using the UVM methodology and SystemVerilog.\n\nTechnical LeadershipDeliver verified designs at the Device, Subsystem or Block level\nPartner with a dedicated Design Lead to deliver high-confidence designs\nVerify designs implemented in SystemVerilog RTL using industry-standard methodologies.\n\nDomain ExpertiseContribute to the development and enhancement of verification technologies and methodologies.\n\nCross Functional ResponsibilityCollaborate with Software and Validation teams to deliver devices that integrate into a wider system.Participate in Product Validation during the prototype stage of development.\n\nRequirements/Qualifications:\n\nBachelor’s or Master’s Degree in Electrical Engineering or Computer Engineering\n8+ years related experience\nExcellent analytical and debugging skills and the ability to proactively solve issues\nProven ability to thrive on, learn and adapt to new methodologies and technologies\nStrong coding skills\nExperience using one or more of System Verilog/Verilog/VHDL, Tcl/Perl/Python, C/C++\nExcellent verbal and written communication skills in English\nExperience with verification methodologies, including UVM, formal verification, and constrained-random verification.\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Principal Engineer-Verification", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-10-15", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Principal-Engineer-Verification_R4295-26-6", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nMicrochip’s Communications Business Unit (CBU) develops high-performance networking, connectivity, and edge compute semiconductor solutions that power communications infrastructure, data centers, automotive systems, aerospace and defense platforms, and industrial applications. Our global team works across the full product lifecycle to deliver innovative products that enable the world’s most demanding connected systems. \n \nThe CBU Product Development team is engaged throughout the device R&D cycle, from concept and design through implementation. Once a prototype is available, we support embedded software development and system-validation lab testing through mass-market production release. Our experienced chip-development team uses the latest semiconductor tools and methodologies, together with advanced process technologies, to develop state-of-the-art networking devices.\n \nAs a Principal Engineer on the CBU Product Development team, you will be responsible for verifying digital integrated circuits at the block or device level. You will collaborate with chip architects, subsystem leads, and verification team members to deliver increasingly complex designs in a friendly, professional environment.\n \nThe role of the Principal Engineer includes: \nVerification\nOwn the verification of complex digital integrated circuits at the block, subsystem, or device level.\n Understand the device requirements and functional description to ensure compliance with specifications and error-free operation.\nPlan verification activities, develop testbenches, and execute tests.\nDevelop verification platforms using the UVM methodology and SystemVerilog.\n\nTechnical Leadership\nDeliver verified designs at the Device, Subsystem or Block level\nPartner with a dedicated Design Lead to deliver high-confidence designs\nVerify designs implemented in SystemVerilog RTL using industry-standard methodologies.\n\nDomain Expertise\nContribute to the development and enhancement of verification technologies and methodologies.\n\nCross Functional Responsibility\nCollaborate with Software and Validation teams to deliver devices that integrate into a wider system.\n Participate in Product Validation during the prototype stage of development.\n\nRequirements/Qualifications:\n\nBachelor’s or Master’s Degree in Electrical Engineering or Computer Engineering\n8+ years related experience\nExcellent analytical and debugging skills and the ability to proactively solve issues\nProven ability to thrive on, learn and adapt to new methodologies and technologies\nStrong coding skills\nExperience using one or more of System Verilog/Verilog/VHDL, Tcl/Perl/Python, C/C++\nExcellent verbal and written communication skills in English\nExperience with verification methodologies, including UVM, formal verification, and constrained-random verification.\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Sr Staff, Physical Design Architect (Flow & ML Automation)", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-10-15", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Senior-Principal-Engineer--Physical-Design-Methodology---RTL-to-GDS-Architecture_R-101503", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nOverview\nAs the RTL-to-GDS Flow Lead, you will be the primary architect of the physical implementation backbone for our next-generation, high-speed CPU cores. This is a high-visibility role focused on pioneering automated, ML-driven methodologies that push Power, Performance, and Area (PPA) beyond industry standards on N3 and N2 process nodes. You will bridge the gap between architectural intent and physical reality, ensuring predictable, world-class execution.\n\nKey Responsibilities\nMethodology Leadership: Architect, validate, and deploy \"Best-of-Class\" RTL-to-GDS recipes tailored for high-frequency CPU implementation.\nML-Driven Optimization: Lead the integration and scaling of AI/ML optimization tools (e.g., Synopsys DSO.ai) to autonomously navigate the massive PPA design space.\nStrategic EDA Engagement: Serve as the primary technical interface with EDA partners (Synopsys) and IP providers to influence tool roadmaps and co-optimize Standard Cell/SRAM libraries for PPA.\nHierarchical Strategy: Define the global floor planning, budgeting, and integration strategies for multi-million gate, high-speed hierarchical designs.\nPredictability & Scale: Design and maintain robust build systems, automated dashboards, and execution checklists to ensure \"push-button\" predictability and minimize manual intervention.\nPPA Modeling: Early-stage PPA estimation and pathfinding to influence RTL and architectural trade-offs.\n\nRequirements\nExpertise: 10+ years of experience in Physical Design with a proven track record of closing high-speed CPUs (3GHz+).\nEducation Qualification: A Bachelor's, Master's, or PhD in E&E, ECE, CS, or VLSI is required.\nAdvanced Nodes: Deep, hands-on experience with TSMC N3 is required; exposure to N2 is highly preferred.\nTool Mastery: Power-user knowledge of the Synopsys Fusion Design Platform (Fusion Compiler, IC Compiler II, PrimeTime).\nAI/ML Integration: Demonstrated experience deploying ML-based design space optimization tools in a production environment.\nSystemic Automation: Expert-level proficiency in Python, Tcl, or Perl, with a mindset for building scalable, maintainable \"Flows-as-Code.\"\nAnalytical Depth: Deep understanding of timing closure, IR drop, electromigration (EM), and crosstalk challenges unique to high-performance cores.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Senior CAD Engineer - Floor Plan", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-15", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Senior-CAD-Engineer---Floor-Plan_JR0288128", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nWe are seeking a highly motivated Senior CAD Engineer for CPU IP Design Planning Methodology and Automation to support, maintain, enhance, and deploy Design Planning and RTL to Floorplan methodologies for next generation CPU IP development.\n\n The successful candidate will work closely with CPU Physical Design, Architecture, RTL, and CAD teams to enable efficient and scalable Design Planning workflows. This role focuses on methodology development, flow support, automation, infrastructure maintenance, and productivity improvements across multiple CPU programs.\n\n The ideal candidate combines a strong understanding of Physical Design and Design Planning concepts with expertise in CAD methodologies, EDA tools, scripting, and software development.\n\n Key Responsibilities\n\n -Own and support Design Planning and RTL to Floorplan methodology deployment across CPU IP programs.\n\n -Develop, maintain, and enhance automation frameworks supporting RTL to Floorplan, Design Planning, physical aware RTL analysis, floorplan generation flows, PPA estimation methodologies, and early congestion and routability analysis.\n\n -Provide technical support to Physical Design teams by debugging flow, tool, and methodology issues.\n\n -Drive continuous improvements in Design Planning flow quality, robustness, scalability, and usability.\n\n -Develop automation solutions to improve engineering productivity and reduce manual effort.\n\n -Create dashboards, reporting infrastructure, and analytics frameworks to track methodology health, usage, and quality metrics.\n\n -Work closely with implementation teams to identify workflow bottlenecks and deploy automation based solutions.\n\n -Support the adoption and deployment of new EDA tool capabilities, releases, and methodology enhancements.\n\n -Enable methodology correlation and consistency across CPU IP projects and technology nodes.\n\n -Partner with internal CAD organizations and EDA vendors to evaluate and integrate new Design Planning capabilities.\n\n -Drive best practices, documentation, training materials, and user support for Design Planning methodologies.\n\n -Explore Machine Learning, Generative AI, and Agentic AI solutions to improve methodology deployment, flow debugging, and productivity.\n\nQualifications:\nMinimum Qualifications\n\t• M.Tech/MS in Electrical Engineering, Computer Engineering, Computer Science, VLSI, or a related field.\n\t• 4+ years of industry experience in:\n CAD Engineering\n Design Automation\n Physical Design Methodology\n EDA Tool Development\n Physical Design Infrastructure\n\t• Strong understanding of:\n Physical Design flows\n RTL-to-Floorplan methodologies\n Design Planning concepts\n Floorplanning fundamentals\n PPA analysis and optimization\n\t• Experience supporting and deploying implementation tools such as:\n Synopsys Fusion Compiler\n ICC2\n Cadence Innovus\n Equivalent physical implementation platforms\n\t• Strong software development and scripting skills in:\n Python\n Tcl\n Shell Scripting\n\t• Experience building and maintaining production-quality CAD automation and methodology frameworks.\n\nPreferred Qualifications\n\t• Experience supporting CPU Core, Cache, Fabric, or other high-performance IP development teams.\n\t• Experience developing methodologies and automation for:\n RTL-FP\n Design Planning\n Physical-aware design\n Design quality assessment\n Early PPA estimation\n\t• Experience with advanced technology nodes such as Intel 18A/14A, TSMC N3/N2, or equivalent.\n\t• Experience with distributed compute infrastructure, cloud-based design environments, and large-scale CAD systems.\n\t• Familiarity with Machine Learning, Data Analytics, LLMs, and Agentic AI frameworks for EDA applications.\n\t• Working knowledge of timing, power, congestion, routability, and signoff considerations impacting design planning methodologies.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Senior Technical Lead - CPU Physical Design", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-15", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Senior-Technical-Lead---CPU-Physical-Design_JR0288117", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nWe are seeking a highly experienced and motivated Senior Technical Lead - CPU Physical Design to lead the physical implementation of next-generation CPU IPs from floorplanning through signoff. The successful candidate will provide technical leadership across the physical design lifecycle, driving PPA optimization, execution excellence, methodology adoption, and design convergence for high-performance CPU products.\n\nThe ideal candidate brings deep expertise in advanced-node physical design, strong technical leadership, and a proven track record of delivering complex CPU, SoC, or high-performance IP designs.\n\nKey Responsibilities\n\nLead physical design execution for CPU IPs from design planning through signoff.\n\nProvide technical leadership for:\n\nFloorplanning and Design Planning\nPlacement and Optimization\nClock Tree Synthesis\nRouting and Physical Verification\nTiming Closure\nPower and Area Optimization\nSignoff Readiness\n\nDrive PPA convergence and deliver aggressive frequency, power, and area targets.\n\nDefine and execute physical design strategies for advanced CPU architectures and technology nodes.\n\nPartner closely with Architecture, RTL, Circuit Design, DFT, CAD, Power, and Signoff teams to drive implementation success.\n\nLead resolution of complex implementation, timing, congestion, and power challenges.\n\nDrive methodology improvements and adoption of best practices across multiple projects.\n\nEvaluate implementation tradeoffs and provide technical recommendations that influence architecture and design decisions.\n\nMentor and guide engineers across the physical design organization.\n\nCollaborate with CAD teams to improve efficiency through automation, methodology enhancements, and AI-driven workflows.\n\nSupport planning, estimation, risk assessment, and execution tracking for physical design deliverables.\n\nContribute to hiring, technical interviews, and development of engineering talent.\n\nQualifications:\nMinimum Qualifications\n\nM.Tech/MS/PhD in Electrical Engineering, Computer Engineering, VLSI, or a related discipline.\n\n14+ years of industry experience in ASIC or CPU Physical Design.\n\nProven experience delivering successful products through complete physical implementation and signoff cycles.\n\nStrong expertise in:\n\nFloorplanning and Design Planning\nPlacement and Optimization\nClock Tree Synthesis\nRouting and Closure\nStatic Timing Analysis\nSignal Integrity\nPower Integrity and EM/IR\nPhysical Verification\n\nHands-on experience with industry-standard implementation tools such as:\n\nSynopsys Fusion Compiler\nICC2\nCadence Innovus\nPrimeTime\nStarRC\nRedHawk\nCalibre\n\nStrong scripting and automation experience using:\n\nPython\nTcl\nShell\nPreferred Qualifications\n\nExperience delivering high-performance CPU core, cache, fabric, or compute IP designs.\n\nExperience with advanced process technologies such as Intel 18A/14A, TSMC N3/N2, or equivalent.\n\nDeep understanding of:\n\nPhysical design methodologies\nAdvanced timing closure techniques\nHierarchical implementation\nVariation-aware design methodologies\nPower-aware implementation\n\nExperience leading geographically distributed teams.\n\nExperience driving CAD methodology improvements and automation initiatives.\n\nFamiliarity with AI, Machine Learning, and Agentic AI applications for design automation and productivity enhancement.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Senior CAD Engineer – Physical Design Signoff", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-15", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Senior-CAD-Engineer---Physical-Design-Signoff_JR0288131", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nWe are looking for a highly motivated Senior Physical Design Signoff Automation Engineer to develop and deploy signoff methodologies and automation solutions for advanced CPU and SoC designs. The candidate will work closely with Physical Design, Timing, Power, Reliability, and CAD teams to improve signoff quality, productivity, and turnaround time.\n\nThe ideal candidate possesses deep expertise in Parasitic Extraction, Static Timing Analysis (STA), Electrical Rule Checking (ERC), and Power Integrity signoff, along with strong programming and automation skills.\n\nKey Responsibilities\n\nDevelop and enhance automation solutions for Physical Design signoff flows, including:\nRC Extraction\nStatic Timing Analysis (STA)\nElectrical Rule Checking (ERC)\nPower Integrity (IR Drop/EM)\nSignal Integrity (SI)\nCreate scalable automation frameworks to reduce signoff turnaround time and improve engineering productivity.\nDevelop scripts and tools to automate signoff checks, debugging, reporting, and data analysis.\nAnalyze and resolve timing, extraction, ERC, and power signoff issues in collaboration with design teams.\nDrive methodology improvements to improve signoff convergence, quality, and correlation across implementation stages.\nPartner with EDA vendors and internal CAD teams to evaluate and deploy new signoff capabilities.\nBuild dashboards and reporting infrastructure to monitor signoff health and project readiness.\n\nQualifications:\nMinimum Qualifications\n\nM.Tech/M.S. in Electrical Engineering, VLSI, Computer Engineering, or related field.\n8+ years of industry experience in Physical Design, Signoff, CAD, or Design Automation.\n\nStrong proficiency in:\nPython\nTcl\nShell scripting\n\nPreferred Qualifications\n\nExperience working on advanced process technologies (3nm, 2nm, Intel 18A/14A, or equivalent).\nUnderstanding of AOCV/POCV and variation-aware timing methodologies.\nFamiliarity with power delivery networks, EM analysis, and reliability signoff.\nExperience in Machine-learning methods and Agentic AI systems to solve CAD problems\nExposure to CPU core, high-performance compute, or large SoC designs.\nExperience with distributed computing environments and large-scale signoff infrastructure.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "CPU Senior Floor Plan Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-15", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/CPU-Senior-Floor-Plan-Engineer_JR0288124", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nDefines the physical dimensions of the CPU IP with consideration for overall product costs such as die size optimization, die per reticle/good die per wafer maximization, and right technology selection as it pertains to metal layers and reuse strategy across different SKUs in a product family. Performs integration of all dies in a package and completes the relevant checks before tape out. Creates and physical database for the IP. Collaborates with architects to optimize the placement of IPs for latency as well as die area/aspect ratio. Creates specifications and collaterals for the IP blocks to execute the floorplan and automatic place and route (APR) at subsequent hierarchies. Collaborates with the clock design and logic design teams to deliver the physical block level floorplans for APR. Collaborates with the power delivery team on tradeoffs for metal allocation for signal and power.\n\nBusiness group\nYou will join Intel Corporation's team focused on CPU design and development, contributing to the creation of groundbreaking technologies that enable world-class computing solutions. This group thrives on innovation, delivering high-performance designs that support Intel's mission to shape the future of technology through the creation of industry-leading products.\n\nKey Responsibilities\nIn this role you will be responsible for all the aspects of Floorplan and pin placement activities. You will engage with Architecture, DFT and package to arrive at optimal chip planning early in the design cycle. You will work closely with physical design cluster leads to comprehend design challenges and arrive at optimal floorplan. You will play critical role in die size estimation and in evaluating Floorplan tools, methods and flows. Planning boundaries and pin densities to facilitate high confidence timing closure and routability. With your broad understanding of physical design you will play a critical role in identifying and solving multitude design issues at partition/cluster and full chip. Expertise with multiple aspects of ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, IO planning and hard IP integration.\n\nQualifications:\nMinimum Qualifications\n- Bachelor's degree in a relevant field such as Electrical Engineering, Electronics Engineering, or equivalent education, with 4+ years of hands-on experience OR Master's degree in a relevant field with 3+ years of hands-on experience.\n- Proven expertise in using Floor planning, APR flows, Physical Design Verification Flows using Synopsys or Cadence tools.\n- Proficiency in hierarchical design approach, top-down design, budgeting, timing and physical convergence.\n- Strong knowledge of submicron process nodes and layout verification methodologies such as LVS and DRC.\n- Experience at handling IP/partition/block with multiple voltage and clock domains, ESD strategies, mixed signal block integration, and advanced package technologies.\n\nPreferred Qualifications\n- Familiarity with scripting languages such as Tcl, Perl, or Python for automation in physical design workflows.\n- Strong collaboration and communication skills to work effectively in cross-functional teams.\n- Proven ability to work in dynamic and cross-geographical environments.\n- Knowledge of feature feasibility studies and advanced design flow methodologies.\n\nWe're excited to welcome passionate engineers who thrive in innovative environments and are eager to contribute to shaping the future of computing. Join us and make an impact by designing world-class CPUs that power cutting-edge technologies.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "CPU Senior Clock Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-15", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/CPU-Senior-Clock-Design-Engineer_JR0288129", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nJoin a Team That Defines the Heartbeat of Next-Generation CPUs. As a CPU Senior Clock Design Engineer, you will contribute to the design, implementation, analysis, and optimization of clock distribution networks that enable industry-leading performance, power efficiency, and product scalability.\n\nBusiness group\nYou will be part of Intel Corporation, joining a dynamic team dedicated to designing high-performance CPUs that drive Intel's leadership in the semiconductor industry. This group focuses on delivering cutting-edge solutions that support Intel's mission of creating world-changing technologies to enrich lives. Collaborating across multiple domains, the team enables groundbreaking designs that align with Intel's broader goals of innovation and excellence.\n\nKey Responsibilities\n- Design, implement, and optimize clock distribution networks for high-performance CPU and SoC products.\n- Contribute to clock architecture development and clock tree synthesis (CTS) methodologies.\n- Perform timing analysis and support timing closure across complex semiconductor designs.\n- Develop custom circuits, library cells, and clock-related design solutions.\n- Analyze performance, power, area, and timing tradeoffs to improve product efficiency.\n- Create automation solutions using scripting and programming languages to improve design productivity.\n- Collaborate closely with architecture, design, physical implementation, validation, and EDA teams.\n- Support debug, validation, and optimization activities throughout the product development lifecycle.\n- Drive technical issues to closure while maintaining high-quality engineering standards.\n- Influence future methodologies, design flows, and clocking technologies.\n\nQualifications:\nMinimum Qualifications\n- Bachelor's degree in Electrical, Electronics, or relevant field and 3+ years of hands-on experience in physical design implementation OR Master's degree in Electrical, Electronics, or relevant field with 2+ years of experience.\n- Extensive experience in clock tree synthesis (CTS) techniques and methodologies using Synopsys and Cadence platforms.\n- Strong understanding of submicron process node technologies and layout verification methods such as LVS/DRC.\n\nPreferred Qualifications\n- Strong ownership and accountability for technical deliverables.\n- Curiosity and passion for solving complex engineering challenges.\n- Effective problem-solving and analytical thinking skills.\n- Ability to collaborate across multiple engineering disciplines.\n- Strong communication skills with both technical and non-technical stakeholders.\n- Adaptability and willingness to learn new tools, technologies, and methodologies.\n- Ability to balance multiple priorities in a fast-paced environment.\n- Continuous focus on quality, execution, and innovation.\n\nMake an impact in shaping the future of CPU technology. Join us and be part of a world-class team that drives innovation and technological excellence at Intel.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "CPU Senior Floor Plan Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-15", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/CPU-Senior-Floor-Plan-Engineer_JR0288134", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nDefines the physical dimensions of the CPU IP with consideration for overall product costs such as die size optimization, die per reticle/good die per wafer maximization, and right technology selection as it pertains to metal layers and reuse strategy across different SKUs in a product family. Performs integration of all dies in a package and completes the relevant checks before tape out. Creates and physical database for the IP. Collaborates with architects to optimize the placement of IPs for latency as well as die area/aspect ratio. Creates specifications and collaterals for the IP blocks to execute the floorplan and automatic place and route (APR) at subsequent hierarchies. Collaborates with the clock design and logic design teams to deliver the physical block level floorplans for APR. Collaborates with the power delivery team on tradeoffs for metal allocation for signal and power.\n\nBusiness group\nYou will join Intel Corporation's team focused on CPU design and development, contributing to the creation of groundbreaking technologies that enable world-class computing solutions. This group thrives on innovation, delivering high-performance designs that support Intel's mission to shape the future of technology through the creation of industry-leading products.\n\nKey Responsibilities\nIn this role you will be responsible for all the aspects of Floorplan and pin placement activities. You will engage with Architecture, DFT and package to arrive at optimal chip planning early in the design cycle. You will work closely with physical design cluster leads to comprehend design challenges and arrive at optimal floorplan. You will play critical role in die size estimation and in evaluating Floorplan tools, methods and flows. Planning boundaries and pin densities to facilitate high confidence timing closure and routability. With your broad understanding of physical design you will play a critical role in identifying and solving multitude design issues at partition/cluster and full chip. Expertise with multiple aspects of ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I-O planning and hard IP integration.\n\nQualifications:\nMinimum Qualifications\n- Bachelor's degree in a relevant field such as Electrical Engineering, Electronics Engineering, or equivalent education, with 3+ years of hands-on experience OR Master's degree in a relevant field with 2+ years of hands-on experience.\n- Proven expertise in using Floor planning, APR flows, Physical Design Verification Flows using Synopsys or Cadence tools.\n- Proficiency in hierarchical design approach, top-down design, budgeting, timing and physical convergence.\n- Strong knowledge of submicron process nodes and layout verification methodologies such as LVS and DRC.\n- Experience at handling IP/partition/block with multiple voltage and clock domains, ESD strategies, mixed signal block integration, and advanced package technologies.\n\nPreferred Qualifications\n- Familiarity with scripting languages such as Tcl, Perl, or Python for automation in physical design workflows.\n- Effective communication skills for collaboration across multidisciplinary teams.\n- Proven ability to work in dynamic and cross-geographical environments.\n- Knowledge of feature feasibility studies and advanced design flow methodologies.\n\nContribute to groundbreaking advancements in CPU design and innovation by joining Intel Corporation. Take the next step to shape the future of technology-apply now.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "CPU Clock Design Lead", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-15", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/CPU-Clock-Design-Lead_JR0288130-1", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nJoin a Team That Defines the Heartbeat of Next-Generation CPUs. As a CPU Clock Design lead, you will contribute to the design, implementation, analysis, and optimization of clock distribution networks that enable industry-leading performance, power efficiency, and product scalability.\n\nBusiness group\nYou will be part of Intel Corporation, joining a dynamic team dedicated to designing high-performance CPUs that drive Intel's leadership in the semiconductor industry. This group focuses on delivering cutting-edge solutions that support Intel's mission of creating world-changing technologies to enrich lives. Collaborating across multiple domains, the team enables groundbreaking designs that align with Intel's broader goals of innovation and excellence.\n\nKey Responsibilities\n- Design, implement, and optimize clock distribution networks for high-performance CPU and SoC products.\n- Contribute to clock architecture development and clock tree synthesis (CTS) methodologies.\n- Perform timing analysis and support timing closure across complex semiconductor designs.\n- Develop custom circuits, library cells, and clock-related design solutions.\n- Analyze performance, power, area, and timing tradeoffs to improve product efficiency.\n- Create automation solutions using scripting and programming languages to improve design productivity.\n- Collaborate closely with architecture, design, physical implementation, validation, and EDA teams.\n- Support debug, validation, and optimization activities throughout the product development lifecycle.\n- Drive technical issues to closure while maintaining high-quality engineering standards.\n- Influence future methodologies, design flows, and clocking technologies.\n\nQualifications:\nMinimum Qualifications\n- Bachelor's degree in Electrical, Electronics, or relevant field and 6+ years of hands-on experience in physical design implementation OR Master's degree in Electrical, Electronics, or relevant field with 4+ years of experience OR PhD with at least 2 years of experience in domain.\n- Proficiency in clock tree synthesis (CTS) techniques and methodologies using Synopsys and Cadence platforms.\n- Extensive experience in timing signoff, formal verification, and low-power design techniques.\n- Strong understanding of submicron process node technologies and layout verification methods such as LVS/DRC.\n\nPreferred Qualifications\n- Strong ownership and accountability for technical deliverables.\n- Curiosity and passion for solving complex engineering challenges.\n- Effective problem-solving and analytical thinking skills.\n- Ability to collaborate across multiple engineering disciplines.\n- Strong communication skills with both technical and non-technical stakeholders.\n- Adaptability and willingness to learn new tools, technologies, and methodologies.\n- Ability to balance multiple priorities in a fast-paced environment.\n- Continuous focus on quality, execution, and innovation.\n\nMake an impact in shaping the future of CPU technology. Join us and be part of a world-class team that drives innovation and technological excellence at Intel.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Deputy Director - Electrical Engineer", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2026-10-15", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/Deputy-Director---Electrical-Engineer_R2620742-1", "is_hardware": true, "platform": "workday", "jd_text": "Who We Are\n\nApplied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI and accelerating the commercialization of next-generation semiconductor chips. Join us and push the boundaries of materials science and engineering in a company at the foundation of the electronics industry. The work we do together advances the world’s technology.\n\nWhat We Offer\n\nLocation:\nBangalore,IND\nYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. \n\nAt Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. \n \n \nAs an Electrical Engineer, you are responsible for designing, modifying, and troubleshooting electrical or electronic engineering assemblies, layouts, schematics, and drawings to advance the equipment that supports our technology. Using your technical experience and critical thinking skills, you will perform engineering analysis, generate test reports, develop innovative solutions, and create documentation for product releases. You will also coordinate the procurement and assembly of components, identify sources of critical parts, and resolve technical issues to ensure peak performance. \n \nRole Overview\nApplied Materials is seeking a dynamic and experienced Engineering Lead to join our Bangalore team as a Deputy Director – Electrical Engineering. This role will partner closely with Business Unit (BU) stakeholders to drive project scoping, technical strategy, and execution excellence.\nThe ideal candidate will bring deep expertise across design and manufacturing, coupled with strong cross-functional collaboration skills. This leader will play a critical role in strengthening and elevating the technical capabilities of the Electrical Engineering (EE) team in India while contributing to global engineering initiatives.\n\nKey Responsibilities\nStrategic Collaboration\nPartner with Business Unit (BU) leaders and senior engineering stakeholders to define project scope, priorities, and technical direction\nTechnical Leadership\nProvide broad-based leadership across design and manufacturing domains, ensuring robust and scalable engineering solutions\nDomain Expertise\nLeverage strong knowledge in PCB design, motion control systems, software, firmware, high-voltage systems, and RF technologies\nProblem Solving\nLead and drive complex technical problem-solving initiatives across cross-functional teams\nCross-Functional Alignment\nStrengthen collaboration and execution between engineering teams, business units, and global stakeholders\nExecution Excellence\nEnsure timely delivery of projects with high-quality outcomes through effective planning and execution discipline\nPeople Leadership\nBuild, mentor, and lead high-performing engineering teams, fostering a culture of innovation, accountability, and continuous improvement\nCapability Building\nMotivate and develop the India EE team, enhancing technical depth, skills, and organizational capability\n\nOur Ideal Candidate\nProven track record of successful people management, with the ability to hire, develop, and inspire top engineering talent\nDemonstrated ability to deliver results through effective leadership and team development\nStrong experience in working with global stakeholders and cross-functional teams\nAbility to balance strategic thinking with hands-on technical guidance\nExceptional communication and stakeholder management skills\n\nQualifications\nEducation:\nB.E / B.Tech or M.E / M.Tech in Electrical Engineering\nExperience:\n10–15 years of relevant industry experience, with a strong background in electrical engineering and team leadership\n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nAssignee / Regular\nTravel:\nYes, 10% of the Time\nRelocation Eligible:\nYes\n\nApplied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "Director/Sr Director Analog & IO", "company": "NXP", "location": "Bangalore", "date_posted": "2026-10-15", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Director-Sr-Director-Analog---IO_R-10067387", "is_hardware": true, "platform": "workday", "jd_text": "We are looking for an experienced engineering leader to drive development of next-generation analog, power management, IO, and high-speed interface technologies within NXP's Analog Competence Center (ACC). The role combines technical leadership, organizational development, innovation, and business engagement to deliver differentiated semiconductor solutions.\nKey Responsibilities\nLead and develop a high-performing analog and mixed-signal engineering organization.\nDefine and execute technology roadmaps for power management, IO, SerDes, and high-speed interfaces.\nDrive innovation, quality, and first-time-right execution across multiple product programs.\nPartner with business and product teams to translate future market needs into reusable technology platforms.\nBuild technical capabilities, attract top talent, and develop future leaders.\nRepresent the organization in customer, executive, and cross-functional technology discussions.\nQualifications\nMSc or PhD in Electrical Engineering or related field.\n20+ years of semiconductor R&D experience.\nProven leadership experience managing engineering teams and complex product developments.\nStrong expertise in several of the following areas: High-Speed Interfaces / SerDes IO Design Power Management Analog & Mixed-Signal IC Design SoC Subsystems\nWhat We Are Looking For\nA visionary technology leader who combines deep technical expertise with strong people leadership, a passion for innovation, and a track record of delivering business impact through high-performing engineering teams.\nJoin us in shaping the future of power-efficient, connected, and intelligent semiconductor solutions.\n\nMore information about NXP in India...\n\n#LI-9415", "jd_status": "stored"}, {"title": "Senior Hardware Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-10-15", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506929", "is_hardware": true, "platform": "oracle", "jd_text": "The candidate will design hardware systems and solution, bring-up support for ON’s Product Engineering, Software and Frontend team. It is desirable to be familiar with Multimedia processor or mobile phone architectures or Base Band processors and should have good exposure to ASIC/FPGA based hardware designs and its bring-up and validation. \n\n#LI-RG1\n\nResponsibilities\nResponsible for Design of evaluation, reference and interface boards and should support the hardware needs of the internal software and Frontend team\n\nResponsible for all technical issues during Design, Bring-up and follow on support\n\nWork closely with ON’s internal Design team; Troubleshooting reference and evaluation systems, documenting problems, and suggesting solutions. \n\nSupport Mechanical items development by aligning with hardware design expectations.\n\nSupport probe pad design\n\nTechnical support during chip bring-up and validation.\n\nValidation of hardware designs using Signal integrity tools like Hyperlynx / Sigrity.\n\nValidation of IP developed by Digital Design team is an optional expectation.\n\n#LI-RG1\n\nQualifications\nPossess a Bachelor’s degree in Electronics Engineering\n\nMinimum of 10 years experience in Hardware system design or mobile device system applications or cameras. \n\nExperience with Multimedia Processors and Image Signal Processors\n\nShould have worked on mixed signal integrated circuits/devices, high speed digital designs and high speed serial interfaces. \n\nDesirable to have understanding of Image and video fundamentals.\n\nDesirable to have digital camera design knowledge and understanding of solid stage sensors.\n\nShould be capable of handling issues with little assistance and should be an expert in handling test equipments.\n\nExpertise in Schematic capture (OrCAD) and basic knowledge of Allegro layout.\n\nFamiliarity with software development tools, environment and debuggers.\n\nShould have excellent organizational skills, should be a self starter.\n\n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Principal SOC Verification Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-10-15", "url": "https://careers.arm.com/job/bengaluru/principal-soc-verification-engineer/33099/101981079120", "is_hardware": true, "platform": "talentbrew", "jd_text": "About Solutions SoC Engineering\nJoin the Solutions SoC Engineering organization and help shape the future of silicon. We are building a world-class engineering organization focused on delivering innovative, high-performance, and energy-efficient SoC solutions that power next-generation computing across diverse markets.\n\nAs a rapidly growing global team, we bring together expertise across architecture, design, verification, emulation, FPGA, software, and post-silicon validation to deliver first-time-right silicon. Our engineers solve some of the industry's most challenging engineering problems using advanced verification methodologies, automation, and AI-driven tools while maintaining the highest standards of quality and execution.\n\nOur culture is built on technical excellence, ownership, collaboration, and continuous learning. We invest in our people, encourage innovation, and provide opportunities to influence engineering methodologies, contribute across the product lifecycle, and grow alongside an organization that is defining the future of SoC engineering.\nRole Overview\nAs a Design Verification Engineer, you will verify complex Arm-based IPs, subsystems, and SoCs powering next-generation computing platforms. You will develop scalable verification solutions, own end-to-end verification execution, and contribute to advanced SoC methodologies.\nKey Responsibilities\nDevelop and execute verification strategies for IP, subsystem, and SoC designs.\nVerify CPU, PCIe, DDR, Security, coherency, memory subsystem, and interconnect functionality.\nPerform power-aware verification and system scenario/performance validation.\nOwn verification deliverables from planning through verification closure while ensuring quality, schedule, and execution commitments are met.\nArchitect, develop, and maintain reusable verification environments, verification IPs, methodologies, and automation.\nDevelop verification plans, test methodologies, test cases, and coverage closure strategies.\nDrive functional, code, toggle, assertion, and coverage closure.\nDebug RTL, testbench, integration, and system-level issues.\nCollaborate with architecture, design, firmware, emulation, FPGA, validation, and post-silicon teams.\nLeverage automation, scripting, and AI-assisted workflows to improve verification productivity.\nContribute to methodology improvements, documentation, and engineering best practices.\nRequired Skills and Qualifications\nBachelor's or Master's degree in a relevant engineering discipline.\n13+ years of IP, subsystem, or SoC verification experience.\nStrong Verilog, SystemVerilog, UVM, and modern verification methodologies.\nExperience with Arm-based SoC architecture, coherency, interconnects, memory hierarchy, and UPF.\nExperience with C/C++, scripting, coverage closure, and strong RTL/testbench debug.\nExcellent analytical, communication, and collaboration skills.\nDesired Skills and Qualifications\nExperience with CHI, ACE, AMBA, PCIe, DDR, or Security IP.\nArm System Architecture knowledge.\nAssembly programming.\nFormal verification, emulation, FPGA, gate-level simulation, or post-silicon validation.\nAI-assisted verification and globally distributed engineering experience.\n#LI-KR2\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Verification Engineer, PCIE", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-15", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer--PCIE_JR2026568-1", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science.\n\nThe GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nBe responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nExpected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.\n\nYou will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech or equivalent experience\n\n5+ years of relevant experience\n\nExperience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog\n\nExpertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)\n\nExperience in developing and working in functional coverage based constrained random verification environments\n\nBackground in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nExcellent knowledge of PCIE protocol - Gen3 and above\n\nGood understanding of the system level architecture of PCIE/CXL-based designs\n\nPerl, Python or similar scripting and SW programming language experience\n\nGood debugging and analytical skills\n\nGood interpersonal skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "High Speed IO Validation Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-15", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/High-Speed-IO-Validation-Engineer_JR2027937", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. Today, we are tapping into the unlimited potential of AI to define the next era of computing — an era in which our GPUs act as the brains of computers, robots, and self-driving cars that understand the world. Doing what has never been done before takes vision, innovation, and the world’s best talent.\n\nNVIDIA’s Silicon Co-Design Group is the team that gets every GPU, SoC, and CPU silicon program from first power-on to high-volume production. We are hiring an HSIO Validation Engineer to own characterization and qualification of high-speed I/Os — PCIe, NVLink, NVLink-C2C, UCIe, USB, UFS, and Ethernet — on brand-new silicon serving datacenter, AI, and client markets. Your bench is where silicon meets the signal — where every link train, jitter sweep, eye diagram, and protocol corner gets exercised before the part ships. You drive characterization and debug for IO interconnects across silicon, board, firmware, and driver — designing tests that anticipate rack-scale deployment so marginality surfaces at die-and-board scale, never in a rack. Your decisions show up in link margin, BER, power per lane, and the go/no-go calls that gate samples and production.\n\nWhat you will be doing:\nOwn end-to-end characterization and validation of high-speed IO — PCIe, NVLink, NVLink-C2C, UCIe, USB, UFS, Ethernet — from silicon die through package and board, on NVIDIA GPUs, CPUs, and SoCs.\nDevelop and execute validation test plans for silicon and SoC-level HSIO features — bring-up, corner qualification, stress, productization, and structured DOE across PVT, board, cable/connector, thermal, and firmware variables — left-shifting silicon failures before deployment.\nDrive power characterization and optimization across IO interconnects under workload-representative stimuli (MLPerf-class patterns at silicon/board level) — analyze trade-offs across V/F, lane config, and protocol state — and feed back into design, firmware, and binning.\nDrive systematic root-cause analysis for complex HSIO bugs — isolating contributions across silicon, package, board, firmware, and driver, with platform/thermal/mechanical partners when system context matters. Convert rack-observed failures into silicon/board reproducers so future spins fix the root cause upstream.\nAssess manufacturing and yield implications of HSIO margin distributions — identify gaps in scaling from chip to product, and feed back into binning and design.\nDevelop and improve validation methodologies, automation frameworks, and margin-tracking infrastructure — increase efficiency and coverage as platform complexity grows.\n\nWhat we need to see:\nBS or MS in Electrical or Computer Engineering (or equivalent), with 3+ years in post-silicon HSIO validation, characterization, or a closely related discipline.\nDeep understanding of high-speed serial link protocols (PCIe Gen5+, NVLink, NVLink-C2C, UCIe, CXL) and the underlying SERDES architecture — equalization, link training, electrical characterization — with strong signal integrity and jitter knowledge.\nStrong SI and PI fundamentals — S-parameters, eye diagrams, channel margin, crosstalk, return loss, PDN noise, jitter decomposition — and validation experience across silicon and platform boundaries (CoWoS/interposer/substrate, board), translating rack-environment effects into silicon/board characterization.\nHands-on with lab instrumentation (DSOs, BERTs, VNAs, protocol/logic analyzers, TDR), DOE/shmoo/margin-trending, and Python-based test automation — with a track record of driving cross-functional debug across chip, package, board, firmware, driver, and system teams.\n\nWays to stand out from the crowd:\nHands-on experience with PCIe Gen5/Gen6 or NVLink validation on production silicon — link training, equalization tuning, BER margining, or compliance debug.\nPrior SERDES, mixed-signal, or analog circuit design experience — sufficient to independently form hypotheses, design Sim-to-Si correlation experiments, and propose silicon/system-side fixes during debug.\nTrack record of translating rack-environment conditions (thermal, connector reliability, neighbor noise) into silicon/board characterization — finding marginality at die-and-board scale before it appears in the field.\nComfortable using AI productivity tools (Claude, Copilot, or equivalent) to compress log triage, regression analysis, scripting, and reporting workflows.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Hardware Development Engineer", "company": "Nokia", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-10-15", "url": "https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/39875", "is_hardware": true, "platform": "oracle", "jd_text": "As an Hardware Development Engineer, you will play a crucial role in the NI ON PSE HW&TE GX Syst HW & CentEng 5 (L06) department. Your primary focus will be on thermal design, simulation, and optimization for a range of high-speed pluggable transceivers, ensuring they meet power, temperature, and reliability requirements. You will collaborate with various teams and drive thermal architecture decisions throughout the product development lifecycle.\n\nNILightpath\n\nResponsibilities\nOwn thermal design, simulation, and optimization for OSFP, OSFP-XD, QSFP-DD, QSFP112, QSFP56, CFP, and future form factors.\nDevelop thermal solutions for modules supporting 25G to 1.6T applications, ensuring compliance with specifications.\nCollaborate with mechanical, signal integrity, optics, electronics, manufacturing, and reliability teams.\nSelect and optimize thermal solutions such as heat spreaders, sinks, vapor chambers, and heat pipes.\nUnderstand and manage module-to-cage thermal interfaces and host-system cooling interactions.\nPerform thermal simulations using FloTHERM and other thermal analysis tools and optimize airflow paths, pressure drops, and component temperatures.\nCorrelate simulation results with lab measurements and drive design improvements.\nConduct thermal validation and testing, including thermal characterization, airflow analysis, and power dissipation testing.\n\nQualifications\nB.E./B.Tech/M.E./M.Tech in Mechanical, Thermal, Aerospace Engineering, or related field.\n3+ years of electronics cooling and thermal engineering experience.\n2+ years of thermal design for pluggable optical modules (OSFP, QSFP-DD, CFP, SFP family).\nStrong understanding of thermal challenges in DSP/ASIC cooling, optical engines, and laser devices.\nExperience with FloTHERM and other thermal tools for thermal simulations and modeling.\nAbility to correlate simulation results with lab measurements and drive design improvements.\nHands-on experience with thermal validation for optical transceivers or compact networking products.\nProficiency in thermal validation tools and techniques, including thermocouples and IR imaging.\nStrong analytical skills, methodical approach, and excellent technical reporting abilities.\n\nAbout the company\nAdvancing connectivity to secure a brighter world.\n\nNokia is a global leader in connectivity for the AI era. With expertise across fixed, mobile and transport networks, powered by the innovation of Nokia Bell Labs, we’re advancing connectivity to secure a brighter world. \n\nLearn more about life at Nokia.\n\nOur recruitment process\n\nWe act inclusively and respect the uniqueness of people. Our employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.\n\nIf you’re interested in this role but don’t meet every listed requirement, we still encourage you to apply. Unique backgrounds, perspectives, and experiences enrich our teams, and you may be just the right candidate for this or another opportunity.\n\nThe length of the recruitment process may vary depending on the specific role's requirements. We strive to ensure a smooth and inclusive experience for all candidates. Discover more about the recruitment process at Nokia.", "jd_status": "stored"}, {"title": "Senior ASIC Design Engineer", "company": "Nokia", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-10-15", "url": "https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/36569", "is_hardware": true, "platform": "oracle", "jd_text": "In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise\n Join Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.\nInfinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group.\n\nWork as part of a world class ASIC design team, building leading edge chips for the Coherent Optics market.\n\nResponsibilities\nRole:\nIn this role you are expected to work with architects to understand the requirements, document them and implement the functional block or an IP.\nWhat you will be doing:\n• Work closely with Architects to understand the requirements, document them, and implement the functional block or an IP\n• Capture the design intent, uArch, RTL coding, API coding, lint, constraints development, CDC, and synthesis\n• Debug the designs and work with verification team members to get a functionally clean block\n• Integrate blocks and create physical design blocks for place and route\n• Work with Physical Design team to ensure that the design meets area, timing, power requirements\n• Test their design block in the lab and work with lab validation team members\n\nQualifications\nWhat we seek:\n• Ability to abstract complex functions\n• Ability to do the uArch using block diagrams, waveforms and mathematical and logical models/equations\n• Good understanding of use of FIFOs, state machines\n• Exposure to RTL coding using Verilog/system Verilog\n• Good logic design skills with ability to understand timing, area and power reports\n• Experience in timing constraints development, running lint and CDC checks, synthesis using ASIC or FPGA tools\n• Interested in using assertions and formal property verification to develop bug free designs\n• Experience of 5+ years in design (uArch, RTL coding, RTL checks and debug)\nPreferred: Prior experience in Ethernet/Networking domain\n\nAbout the organization\nSome of our benefits in India:\n\nFlexible and hybrid working arrangements to support work–life balance\n\nHealth and well-being support – medical insurance for you and your family, health check-ups, life and accident insurance, well-being programs, and employee resource groups \n\nA minimum of 90 days of Maternity and Paternity Leave based on eligibility\n\nPersonal Support Service 24/7 – a confidential support channel open to all Nokia employees and their families in challenging situations\n\nCareer growth & mobility – technical career paths, job rotations, international assignments, and relocation support\n\nContinuous learning – technical certifications, mentoring programs, coaching, and digital learning platforms\n\nOpportunities to innovate and contribute through Nokia’s research and development environment\n\nRecognition programs that celebrate outstanding contributions\n\nWorkplace support – ergonomic working support and mobile device programs based on eligibility", "jd_status": "stored"}, {"title": "Lead I/O Design Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-10-15", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Lead-I-O-Design-Engineer_R-10066917", "is_hardware": true, "platform": "workday", "jd_text": "Key Responsibilities\nDesign and develop custom IO circuits including:GPIO\nLVDS\nLVCMOS\nSSTL\nHSTL\nDDR Interfaces\nHigh-speed SerDes support circuits\n\nPerform transistor-level design and simulation using advanced CMOS technology nodes.\nDevelop and optimize:ESD protection circuits\nLevel shifters\nInput buffers\nOutput drivers\nOn-chip termination circuits\n\nConduct pre-layout and post-layout simulations for functionality, timing, power, noise, and reliability.\nPerform signal integrity analysis including:IBIS model generation\nPackage-aware simulations\nCrosstalk and reflection analysis\n\nDrive layout reviews and work closely with physical design teams to ensure design quality and performance targets.\nSupport silicon bring-up, characterization, debugging, and production ramp activities.\nCollaborate with system, package, reliability, and product engineering teams.\nDevelop and maintain design documentation, specifications, and verification reports.\n\nRequired Qualifications\nBachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, or related field.\n5-8 years of experience in Analog/Mixed-Signal or IO Circuit Design.\nStrong understanding of:CMOS device physics\nAnalog circuit design fundamentals\nIO architectures and standards\nESD design methodologies\n\nHands-on experience in custom circuit design using Cadence Virtuoso.\nExpertise in SPICE-based simulators such as Spectre, HSPICE, or FineSim.\nExperience with advanced technology nodes (16nm/7nm/5nm preferred).\nGood knowledge of LVS, DRC, EMIR, and reliability checks.\nFamiliarity with process corners, Monte Carlo analysis, and yield optimization techniques.\n\nPreferred Skills\nExperience with DDR4/DDR5, LPDDR, USB, PCIe, MIPI, or Ethernet interfaces.\nKnowledge of package modeling and SI/PI analysis tools.\nUnderstanding of ESD standards such as HBM, CDM, and IEC.\nExperience in silicon validation and lab characterization.\nScripting skills in Python, Perl, Tcl, or SKILL.\nFamiliarity with IBIS and IBIS-AMI model generation.\n\nDesired Competencies\nStrong analytical and debugging skills.\nExcellent communication and cross-functional collaboration.\nAbility to lead technical discussions and mentor junior engineers.\nProven track record of delivering silicon successfully from specification to production.\nSelf-driven with strong problem-solving abilities.\n\nNice to Have\nExperience in automotive, AI/ML, networking, mobile, or data center SoCs.\nExposure to functional safety and reliability requirements.\nPrior ownership of complete IO IP development cycle.\nThis role is ideal for an engineer who has hands-on experience in IO circuit design, ESD, signal integrity, and silicon validation, and is looking to contribute to next-generation semiconductor products.\n\nMore information about NXP in India...\n\n#LI-7013", "jd_status": "stored"}, {"title": "Staff Server Platform Hardware Architecture", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-14T17:52:00+00:00", "url": "https://global-external-amd.icims.com/jobs/93444/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. Staff Server Platform Hardware Architecture WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: Function: Principal Member of Technical Staff | Discipline: High Speed Board Design & Server Platform Architecture | Level: Principal / Staff (Senior Individual Contributor) | Location: Bangalore, India | Department: Server Platform Design / System Hardware Engineering We are looking for an exceptionally skilled and experienced Principal Member of Technical Staff to join our Server platform Hardware Engineering team, specializing in High Speed Board Design. This is a senior individual contributor role that combines deep technical expertise with leadership responsibility across complex, multi-generational hardware programs. The ideal candidate is a seasoned hardware engineer who thrives at the intersection of signal integrity, power integrity, and system-level design — someone who can independently drive technically complex designs from concept to production while also guiding and mentoring the engineers around them. This role operates at the forefront of hardware innovation, working on high-performance computing platforms, data center solutions, or next-generation semiconductor evaluation and validation systems. The engineer in this role will be expected to define technical direction, establish design methodology, and be the go-to authority for high speed board design challenges across the organization. THE PERSON: The ideal candidate brings a rare combination of deep hardware expertise and collaborative leadership. They are recognised as the go-to authority in platform design — someone who can resolve complex problems that others cannot, while remaining humble enough to mentor and grow the engineers around them. They demonstrate full ownership — from concept to production — and approach ambiguous, multi-disciplinary problems with a systematic mindset. They communicate complex technical concepts clearly to both technical and non-technical audiences, and represent the team with confidence in cross-functional and vendor discussions. Above all, they have an innovation mindset — constantly looking for better ways to design, review, and validate hardware — and they actively invest in the growth of the engineers around them. They are collaborative across disciplines (SI, firmware, mechanical, test, silicon) and comfortable navigating shifting priorities and new technology domains. What success looks like: In the first 6 months: Deep understanding of team programs, tools, and design standards; actively contributing to design reviews and board bring-up; identified at least one methodology improvement opportunity. Within the first year: Owning one or more high-speed board designs from specification through layout sign-off; recognised as a trusted technical resource; contributed to or defined updated design standards. Over time: Defining the technical direction for platform architecture within the organisation; producing benchmark designs for quality and reliability; developing the next generation of hardware design engineers on the team. KEY RESPONSIBILITIES: Technical Design & Execution Lead the end-to-end design of high-speed, high-complexity PCBs including schematic capture, component selection, layout guidance, and design verification Design and review high-speed interfaces including PCIe Gen 4/5/6, DDR4/5/LPDDR5, USB 3.x, MIPI, SERDES-based interfaces, Ethernet (1G/10G/25G/100G), and other emerging standards Develop and own design specifications, interface requirement documents, and schematics for complex multi-layer boards (20+ layers) Define and enforce PCB stack-up, impedance control, and routing rules for high-speed signal integrity compliance Drive board bring-up, debug, and validation activities — capable of independently diagnosing and resolving complex hardware issues Perform or guide pre-layout and post-layout signal integrity (SI) and power integrity (PI) simulations using industry-standard tools Work closely with PCB layout engineers to ensure design intent is correctly implemented, performing detailed layout reviews and providing clear, specific guidance Architecture & Innovation Participate in early-stage architecture definition and feasibility assessment for new platform programs Evaluate new silicon devices, connectors, memory technologies, and interface standards and assess applicability to upcoming designs Define reference design guidelines and best practices for high speed board design within the team Identify and propose design improvements that reduce cost, improve reliability, extend product life, or enhance testability Stay current with industry trends, emerging standards, and evolving EDA tool capabilities Technical Leadership & Mentorship Serve as the technical authority and subject matter expert (SME) for high speed board design within the team Provide technical guidance, design reviews, and mentorship to junior and mid-level hardware engineers Lead design reviews — both internal and cross-functional — ensuring design quality, manufacturability, and compliance with system requirements Collaborate with cross-functional teams including signal integrity engineers, firmware engineers, mechanical designers, and test engineers Represent the hardware design team in technical discussions with silicon vendors, EDA tool vendors, PCB fabricators, and assembly partners Process & Quality Define and maintain design standards, checklists, and review processes for high speed board design Champion design for manufacturability (DFM), design for testability (DFT), and design for reliability (DFR) practices Drive continuous improvement in design methodology, tool flows, and review processes Support sustaining engineering activities including ECO management, alternate component qualification, and product improvements PREFERRED EXPERIENCE: REQUIRED TECHNICAL SKILLS Deep expertise in high-speed interface design: PCIe (Gen 4/5 minimum), DDR4/DDR5, USB 3.x, SERDES-based interfaces Strong hands-on experience with signal integrity analysis — pre/post layout simulation, eye diagram analysis, impedance modeling, crosstalk analysis Strong hands-on experience with power integrity analysis — PDN design, decoupling strategy, VRM placement, DC/AC analysis Proficiency in schematic capture tools — Cadence Allegro/OrCAD, Mentor PADS, or equivalent industry tools Practical experience guiding PCB layout engineers — routing rules, layer stack-up, via structures, differential pair routing, length matching, and return path management Experience with board bring-up and hardware debug — oscilloscope, logic analyzer, VNA, TDR, BERT, and protocol analyzers Familiarity with EMI/EMC design practices and compliance requirements (FCC, CE, etc.) Understanding of thermal design considerations for high-power components Knowledge of manufacturing processes — DFM, IPC standards, Gerber review, assembly and test PREFERRED / BONUS SKILLS Experience with FPGA-based boards (Xilinx/AMD or Intel FPGA integration) Exposure to high-speed optical or SerDes interfaces at 112G or beyond Experience with OCP/DC-SCM, OpenBMC, IPMI, or data center platform standards Familiarity with RTL or firmware development for hardware validation or embedded systems Experience with mechanical design tools (ECAD-MCAD co-design) Exposure to AI/ML-based EDA tools or automation of design review and verification processes Experience in JTAG infrastructure design and boundary scan methodology EXPERIENCE 15+ years of hands-on experience in PCB hardware design, with a strong focus on high-speed digital systems Demonstrated experience designing complex, multi-layer PCBs (16+ layers) for high-performance computing, server, networking, or semiconductor test and evaluation platforms Proven track record of successfully delivering hardware designs from concept through mass production or customer deployment ACADEMIC CREDENTIALS: Bachelor's degree or higher in Electrical Engineering, Electronics Engineering, or a closely related field (preferred) Master's degree in Electrical Engineering or related discipline (preferred / desired) LOCATION: Bangalore, India Department: Server Platform Design / System Hardware Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Sr Staff/Principal Application Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-14T09:31:50.135000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000155458821-sr-staff-principal-application-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking a Senior Staff /Principal Applications Engineer with deep expertise in power electronics and power management systems to support Renesas’ India‑focused growth initiatives. This role is hands‑on, customer‑facing, and technically authoritative. \nThe successful candidate will act as the technical backbone between customers, field teams, and internal design groups, owning application architecture, reference designs, competitive analysis, validation methodology, and critical customer debug. This role strongly influences product P&L or roadmap decisions through real system insight. \nYou will be expected to operate autonomously, mentor other applications engineers, and represent Renesas as a trusted technical authority at key customer engagements \nResponsibilities :\nCustomer‑Facing Applications Leadership \nServe as the primary technical interface for key customers in power-related applications (industrial, automotive light EV, inverter/UPS, consumer power, energy storage). \nLead design‑in, bring‑up, and debug activities at customer sites or Renesas labs. \nDiagnose complex system‑level issues across power stage, control loop, sensing, firmware interaction, EMI/thermal behaviour. \nProvide structured technical feedback to product and design teams based on real customer usage. \nReference Designs & Application Enablement \nArchitect and develop reference designs, evaluation platforms, and application demonstrators using Renesas power products (e.g., MOSFETs, DC/DC, PMICs, gate drivers, BMS ICs). \nOwn schematic review, component selection, PCB guidance, and layout best‑practice recommendations. \nGenerate application notes, design guides, and technical collateral that materially improve customer adoption. \nDefine validation plans that reflect real-world corner cases, not just datasheet conditions. \nSystem‑Level Technical Expertise \nUnderstand and analyse full power system behaviour, including:  \nControl loop stability and transient response \nThermal and efficiency trade‑offs \nProtection mechanisms and fault behaviour \nInteraction with MCUs/SoCs and firmware \nPerform and guide system modelling and simulation (SIMPLIS, PLECS, SPICE). \nEvaluate design trade‑offs and clearly articulate why one solution works better than another keeping BOM cost in mind \nLab Ownership & Technical Depth \nHands‑on operation of lab equipment: oscilloscopes, Bode/network analysers, electronic loads, power supplies, thermal setups. \nDevelop automation scripts (Python/C) to accelerate validation and characterization. \nSupport failure analysis and root cause investigation for field issues and RMA trends. \nTechnical Leadership & Mentorship \nAct as a technical mentor for junior and mid‑level applications engineers. \nHelp define best practices, review standards, and debug methodologies across the power applications team. \nInfluence hiring by helping assess deep technical capability (not surface‑level)\n\nRequired skills & Qualifications:\nComfort and ability to collaborate and be effective in an entrepreneurial (fast-paced and ambiguous) environment  \nExcellent interpersonal, communication and presentation skills and comfort in presenting to a wide range of audiences. Capable to communicate issues in a concise and effective way. \nDesire and drive to interact with, as well as ability to build and maintain excellent relationships with internal and external stakeholders.  \nProduct ownership mentality \n12+ years of experience in power management space, ideally including customer facing technical problem solving with semiconductor companies  \nTravel will be required \nBachelor or Masters of Electronics Engineering related discipline  \nAbility to build a strong team and motivate individuals to work out of their comfort zone \nSelf-driven, strongly motivated individual capable to take full ownership of their activities, and to involve other functions in the company or management when needed to bring them to a successful outcome. \nUnderstanding of power management applications and products. \nTechnical proficiency :\nDeep understanding of Power topologies (e.g., buck, boost, buck boost, isolated where relevant), Control loop theory and compensation, Thermal design and power loss modelling (using FEA tools), and EMI/EMC considerations at board and system level \nHands-on experience and ability in lab debugging, probing and characterizing circuit and silicon using a mixture of custom-made and standard equipment such as power supplies, e-load, digital oscilloscopes, spectrum analyzers, etc. \nSIMPLIS or similar ckt simulator  \nProgramming proficiency Python or C for automation and data analysis \nExpertise in board level analog and digital circuit design expertise and PCB schematic design using PCB CAD tools \nProficiency with a full complement of lab equipment including network analysers, oscilloscopes and waveform generators.  Experience with automation of lab testing. \nData analysis using Excel or JMP  \nUnderstanding of AECQ / IATF /ISO26262 (FuSa) (At least basic level) \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Engineer, Design Verification (MCU)", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-14T06:39:45.598000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000155420575-senior-engineer-design-verification-mcu-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Be a part of end‑to‑end verification execution for SOC owning complex digital IP’s and subsystems from specification to sign‑off\nDefine and drive IP‑level verification strategies, including test plans, coverage models, and closure criteria\nDevelop scalable, reusable UVM‑based verification environments for IP and subsystem verification\nLead functional, code, assertion, and cross‑coverage closure, ensuring high‑quality sign‑off with clear metrics\nApply AI/ML‑assisted verification techniques to accelerate coverage convergence, identify stimulus gaps, and optimize regression efficiency\nDrive constraint random and directed test methodologies for thorough protocol, corner‑case, and stress verification\nCollaborate with RTL, Architecture, Emulation, and SoC Verification teams to ensure seamless IP integration\nReview IP specifications and work with architects to translate requirements into robust verification plans and checkers\nDevelop and deploy advanced checkers, scoreboards, assertions (SVA), and protocol monitors\nWork with EDA vendors to evaluate and adopt next‑generation verification, coverage, and analytics tools\nMentor junior engineers and promote best‑in‑class verification practices and continuous improvement\nSupport Gate‑Level Simulation (GLS), low‑power verification, and post‑silicon debug when required.\nEnsure IP deliverables meet quality, schedule, and reusability expectations for SoC integration.\n\nBachelor’s or Master’s degree in Electronics Engineering.\n2 - 4 years of experience in SoC Verification domains and working knowledge of industry-standard EDA toolkits.\nStrong expertise in UVM-based testbench architecture and development.\nProven experience in metric-driven verification, including functional and code coverage closure.\nDeep understanding of SystemVerilog, UVM, assertions (SVA), and verification best practices.\nExperience with directed and constrained-random verification methodologies.\nExperience debugging complex design issues in simulation, emulation, and post-silicon environments.\nProficiency in Verilog/SystemVerilog, with working knowledge of C/C++, and Shell scripting.\nExperience in verification of MCU-based SoCs and subsystems, including CPU cores, AHB/APB/AXI bus protocols, interrupt controllers, GPIO, timers, UART, SPI, I2C, CAN, low-power features, and embedded peripherals.\nStrong understanding of MCU architectures such as ARM Cortex-M, RISC-V, or equivalent embedded processor architectures.\nKnowledge of firmware-driven verification techniques and embedded software interaction with MCU peripherals is desirable.\nStrong analytical, problem-solving, and communication skills.\nPreferred/Plus Qualifications:\nHands-on experience using AI/ML-based verification tools for:\nCoverage gap analysis\nTest stimulus optimization\nRegression triage and coverage acceleration\nScripting expertise in Python, Perl, or TCL for automation and analytics.\nExposure to formal verification and hybrid formal-simulation flows.\nFamiliarity with high-speed or complex IPs, such as:\nH.264\nSecurity, debug, or safety-critical IPs\nExperience with MCU functional safety concepts (ISO 26262), low-power verification, secure boot, and embedded system validation is a plus.\nExperience with firmware development/debugging in Embedded C or RTOS-based environments is desirable.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Engineer, Design Verification", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-14T06:15:02.309000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000155418549-engineer-design-verification", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Be a part of end‑to‑end verification execution for SOC owning complex digital IP’s and subsystems from specification to sign‑off\nDefine and drive IP‑level verification strategies, including test plans, coverage models, and closure criteria\nDevelop scalable, reusable UVM‑based verification environments for IP and subsystem verification\nLead functional, code, assertion, and cross‑coverage closure, ensuring high‑quality sign‑off with clear metrics\nApply AI/ML‑assisted verification techniques to accelerate coverage convergence, identify stimulus gaps, and optimize regression efficiency\nDrive constraint random and directed test methodologies for thorough protocol, corner‑case, and stress verification\nCollaborate with RTL, Architecture, Emulation, and SoC Verification teams to ensure seamless IP integration\nReview IP specifications and work with architects to translate requirements into robust verification plans and checkers\nDevelop and deploy advanced checkers, scoreboards, assertions (SVA), and protocol monitors\nWork with EDA vendors to evaluate and adopt next‑generation verification, coverage, and analytics tools\nSupport Gate‑Level Simulation (GLS), low‑power verification, and post‑silicon debug when required.\nEnsure IP deliverables meet quality, schedule, and reusability expectations for SoC integration.\n\nBachelor’s or master’s degree in Electronics Engineering\n1 - 2 years of experience in SoC Verification domains and have working knowledge of industry standard EDA toolkits.  \nStrong expertise in UVM‑based testbench architecture and development\nProven experience in metric‑driven verification, including functional and code coverage closure\nDeep understanding of SystemVerilog, UVM, assertions (SVA), and verification best practices\nExperience with directed and constrained‑random verification methodologies\nExperience debugging complex design issues in simulation, emulation, and post‑silicon environments\nProficiency in Verilog/SystemVerilog, with working knowledge of C/C++, Shell scripting\nStrong analytical, problem‑solving, and communication skills\nPreferred/Plus Qualifications\nHands‑on experience using AI/ML‑based verification tools for:\nCoverage gap analysis\nTest stimulus optimization\nRegression triage and coverage acceleration\nScripting expertise in Python, Perl, or TCL for automation and analytics\nExposure to formal verification and hybrid formal‑simulation flows\nFamiliarity with high‑speed or complex IPs, such as:\nH.264\nSecurity, debug, or safety‑crititical\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Staff/ Sr Staff/Principal Engineer, STA ", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-14T05:46:40.841000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000155415820-staff-sr-staff-principal-engineer-sta-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking a seasoned Backend Design Expert specializing in Static Timing Analysis (STA) and Logic Synthesis. You will own the RTL-to-Gate conversion, constraint development, and final timing closure, ensuring our chips deliver maximum performance at the lowest possible power and area.  \nKey Responsibilities \nPhysical-Aware Synthesis and PPA optimization: Own and execute hierarchical synthesis flows to translate SystemVerilog RTL into optimized gate-level netlists. Execute physical-aware and floorplan-driven synthesis flows to minimize post-layout congestion and achieve PPA targets, identify bottlenecks and drive optimizations (e.g., critical path restructuring, datapath optimization). Conduct flat and hierarchical synthesis, ensuring seamless interface timing budgets. Manage formal verification (LEC) to ensure logical equivalence between RTL and netlist. UPF management for multiply power domains. \nTiming Closure & STA: Perform block-level and full-chip STA across multi-mode and multi-corner (MMMC) scenarios using industry-standard tools. Collaborate with PNR team, understand the clock tree and provide timely feedback to optimize the clock tree and achieve best QOR and perform STA signoff checks to closure.  \nConstraint Development: Architect, validate, and manage files, addressing both functional and DFT modes. Develop and manage comprehensive block-level and top-level constraints (SDC / UPF). \nLow-Power Implementation: Implement and verify UPF-based (Unified Power Format) low-power architectures and multi-voltage domains \nProgramming/Scripting: Strong scripting skills in Tcl, Python, or Perl to automate flows and improve design methodologies \n\nExperience of about 8-13 years in synthesis and STA closure. \nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. \nAbility to understand design specifications, can contribute to design planning, partitioning, and setup a feasible seed for convergence PD cycle. \nExtensive experience in STA closure on complex design with ability to understand the clocks structure from both functional and DFT side and provide solutions to complete design closure.  \nWorked on synthesis of high frequency designs and come up PPA solutions to meet the targets. \nGood understanding of EDA tools such as Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC. \nStrong understanding of static timing analysis, power analysis, and signal integrity analysis. \nExcellent problem-solving skills and attention to detail. \nExcellent scripting skills and development of utilities to reduce overall TAT. \nAbility to work effectively in a team environment and communicate clearly with cross-functional teams. \nExperience in mentoring and coaching junior engineers is a plus. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Staff Validation Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-14T04:19:29.169000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000155411169-staff-validation-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "The Post-Silicon Validation team within the Performance Computing Power Division is building a world-class organization of highly skilled engineers across multiple global sites. Our mission is to push the boundaries of silicon validation for industry-leading integrated circuits enabling high-power, high-efficiency power management systems.\nWe are committed to delivering the highest level of validation quality by continuously improving test coverage, measurement accuracy, repeatability, automation, and execution efficiency while reducing overall validation time.\nAs a Staff Validation Engineer, you will be part of a multidisciplinary global development team and play a key role in ensuring that every new product fully meets its electrical, functional, and performance specifications before release to production. You will work closely with Design, Applications, Product Engineering, Quality, and System teams to identify, debug, and resolve silicon and system-level issues while supporting aggressive product development and New Product Introduction (NPI) schedules.\nFor our office in Bangalore, we are looking for a hand-on engineer who thrives on innovation, enjoys solving complex technical challenges, and is committed to delivering high-quality results in a fast-paced environment.\nPrincipal Responsibilities\nExecute validation of analog, digital, mixed-signal, and power management ICs against electrical, functional, and performance specifications.\nDevelop and execute comprehensive validation plans, test cases for complex products, platforms, or systems.\nEnsure validation coverage, requirements traceability, and compliance with quality and industry standards.\nIdentify validation gaps, product risks, and potential quality concerns, and work with cross-functional teams to implement corrective actions.\nContribute to test automation, validation infrastructure, and continuous improvement initiatives to enhance quality and efficiency of our advanced laboratory for complex post-silicon evaluation.\nHand-on with design of custom evaluation boards and supporting hardware for silicon characterization.\nHand-on with development of automated validation frameworks and measurement scripts using Python.\nCollaborate with senior engineers and project teams to define validation approaches and debug methodologies.\nEvaluate product readiness through silicon validation results and provide clear recommendations based on data analysis.\nAnalyze and interpret validation results at device, board, and system level, identifying, documenting, and tracking silicon and application issues.\nCollaborate closely with Design, Applications, Firmware, Product Engineering, and Quality teams to investigate and resolve silicon and system-level bugs.\nSupport New Product Introduction (NPI) activities from first silicon through production release.\n \n\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field, with 6-8 years of experience in power conversion, power management, semiconductor applications, or related system design.\nStrong experience in post-silicon validation, characterization, and debug of mixed-signal and power-management ICs.\nExperience developing and executing validation plans and test methodologies for semiconductor products.\nProven track record of hands-on bench validation, characterization, and debugging of complex hardware systems.\nStrong hands-on experience with laboratory instrumentation, including oscilloscopes, power supplies, electronic loads, source meters, digital multimeters, waveform generators, logic analyzers, and thermal characterization equipment.\nProficiency in Python programming, with experience developing automated test solutions and laboratory automation scripts.\nExperience with board level analog and digital circuit design and PCB schematic creation \nStrong analytical and problem-solving skills, with the ability to independently investigate and resolve complex silicon and system-level issues.\nSelf-motivated and proactive, with the ability to effectively prioritize and execute silicon validation activities while delivering high-quality results under demanding project schedules.\nExperience supporting New Product Introduction (NPI) activities from first silicon through production release .\nExcellent communication and interpersonal skills, with the ability to collaborate effectively across global cross-functional teams.\nImportant\nConcise and precise communication, both internal and with customers \nCross cultural awareness and sensitivity within multisite and multicultural environments \nFlexible to undertake occasional international travel \nExcellent command of verbal and written English\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Lead Principal Engineer - Digital Design", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-10-14T02:11:56+00:00", "url": "https://jobs.infineon.com/careers/job/563808972064497", "is_hardware": true, "platform": "eightfold", "jd_text": "You will be responsible for the architecture, design, and delivery of complex digital IP, ASIC, and SoC solutions. This role drives key technical initiatives, leads major subsystem developments, and collaborates across engineering organizations to deliver high-quality silicon products. The individual is expected to provide technical leadership, mentor engineers, and influence design decisions that impact product success.\n\nYour role\nKey responsibilities in your new role\n\nLead architecture, micro architecture, and RTL design of complex digital subsystems, IPs, and SoCs.\nDrive end-to-end design execution from concept, specification, and implementation through silicon bring-up and production.\nMake key technical decisions and trade-offs to optimize performance, power, area, quality, and scalability.\nCollaborate with architecture, verification, physical design, firmware, software, and validation teams to ensure successful product delivery.\nEstablish and drive adoption of digital design methodologies, quality standards, and engineering best practices.\nLead technical reviews, design sign-offs, risk assessments, and root-cause analysis for complex issues.\nDrive innovation, technology roadmap planning, and development of next-generation solutions.\nContribute to patents, technical publications, and strategic technology initiatives.\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor's, Master's, or Ph.D. in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.\n12+ years of industry experience in digital IC design and semiconductor product development.\nExtensive experience in architecture, microarchitecture, RTL design, and SoC/IP development.\nProven success delivering complex semiconductor products from architecture definition through silicon validation and production.\nExpert-level proficiency in Verilog/System Verilog and modern ASIC/SoC development flows.\nStrong understanding of: \nPerformance, Power, and Area (PPA) optimisation\nClocking and reset architectures\nDesign-for-Test (DFT)\nLow-power design methodologies\nTiming closure and physical design considerations\nSemiconductor development and productization processes\nExperience leading technical reviews, design sign-offs, risk assessments, and root-cause investigations.\nStrong stakeholder management, communication, and collaboration skills.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Video IP Design Verification Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-14T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721413344", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field.\n\nLooking for candidates between 3 to 13 years of experience. \nWorked on coverage driven module verification.\nStrong in System Verilog, UVM\nSound experience in testbench (stimulus, agent, monitor, checker) development.\nFailure debugging with Verdi & log file.\nWorked in the verification having c based reference model inside the testbench\nExperience with assertion development.\nFamiliar with the EDA tools IUS, VCS, Verdi etc.\nExposure in scripting(perl, Python).\nGood team player. Need to interact with the designers and other verification engineers proactively.\nPrior experience with video pipeline is added advantage. \nKnowledge of tensilica\nWorked with sub-system verification with tensilica\nExperience in C based system modelling.\nDebug with C based reference model.\nHave exposure to the other verification tasks : gate level simulation, Power aware simulation, formal verification, sub-system verification and emulation.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "DSP / NPU Design Verification Sr Staff Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-14T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720371613", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nJob Summary:          \n·         Position for 12+ years of experience in design verification of complex Qualcomm propriety DSP/NPU IP\n·         DSP team is responsible for delivering high-performance DSP/NPU cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space, AI, Automotive and more.\n·         Qualcomm is one of the largest fabless semiconductor design companies in the world, generating over $35 Billion in annual revenues from chipsets and royalties from intellectual property.\n\n Job Responsibilities: \n·         Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power,  post silicon and back-end teams.\n·         Implement and improve System Verilog/UVM Testbench Architecture.\n·         Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency.\n·         Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals.\n·         Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails and bugs.\n·         Complete all required verification activities at IP level and ensure high quality commercial success of our products.\n·         Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis.\n·         Responsible gate level simulation bring-up, gate level verification with timing simulations.\n·         Responsible for power aware RTL verification and gate level simulation.\n\nSkillset/Experience:          \n·         12+  years experience in processor/ASIC design verification\n·         Solid background and understanding of Digital Design, Processor Architecture , Processor Verification and Power aware verification.\n·         Expertise in System Verilog Testbench Architecture and implementation.\n·         Experience in writing C based and assembly level testcases is preferred.\n·         Exposure to power aware implementation and verification using UPF is a plus.\n·         Experience with advanced verification techniques such as formal and assertions is a plus.\n·         Gate-Level Simulation and Debug — 0-delay, timing annotated  and power aware.\n·         Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence .\n·         Scripting/Automation Skills — Perl, Python, Shell, Make file TCI .\n·         Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts.\n·         Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred.\n·         Experience in verification of Processor subsystems is preferred.\n·         Experience in creating validation suite and building automation.               \n·         Should have excellent inter-personal and communication skills.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NPU Design Verification Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-14T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720711636", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nSummary:          \n·        Position for 2-8 years of experience in design verification of complex Qualcomm propriety DSP/NPU IP\n·        DSP team is responsible for delivering high-performance DSP/NPU cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space, AI, Automotive and more.\n·        Qualcomm is one of the largest fabless semiconductor design companies in the world, generating over $35 Billion in annual revenues from chipsets and royalties from intellectual property.\n Job Responsibilities: \n·        Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power, post silicon and back-end teams.\n·        Implement and improve System Verilog/UVM Testbench Architecture.\n·        Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency.\n·        Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals.\n·        Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails and bugs.\n·        Complete all required verification activities at IP level and ensure high quality commercial success of our products.\n·        Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis.\n·        Responsible gate level simulation bring-up, gate level verification with timing simulations.\n·        Responsible for power aware RTL verification and gate level simulation.\nSkillset/Experience:         \n·        2+ years experience in processor/ASIC design verification\n·        Solid background and understanding of Digital Design, Processor Architecture , Processor Verification and Power aware verification.\n·        Expertise in System Verilog Testbench Architecture and implementation.\n·        Experience in writing C based and assembly level testcases is preferred.\n·        Exposure to power aware implementation and verification using UPF is a plus.\n·        Experience with advanced verification techniques such as formal and assertions is a plus.\n·        Gate-Level Simulation and Debug — 0-delay, timing annotated and power aware.\n·        Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence .\n·        Scripting/Automation Skills — Perl, Python, Shell, Make file TCI .\n·        Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts.\n·        Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred.\n·        Experience in verification of Processor subsystems is preferred.\n·        Experience in creating validation suite and building automation.              \n·        Should have excellent inter-personal and communication skills.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RFIC Circuit Design Engineer, Senior", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-14T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721561410", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nQualcomm's Radio Frequency Integrated Circuit (RFIC) design center in Bangalore designs advanced cellular RFIC's which enable 2G, 3G, 4G and 5G transceivers for the world wide cellular chipset market. We are looking for experienced RF/Analog IC design engineers to join the existing RF design team. We welcome international applicants wishing to relocate to India and Qualcomm provides a highly cosmopolitan and challenging work environment with ample opportunities in innovation & patenting. Qualcomm also collaborates intensely with premium Indian Universities and Institutes in RF/Analog domain. *Please note this position is located in Bangalore, India.\n\nTypical designs that we do in BDC include: Driver Amplifiers, LNA (Low Noise Amplifier), Up/Down Conversion Mixers, Base Band Filters, DLL (Delay Locked Loop), PLL (Phase Locked Loop), High Frequency Dividers, VCO (Voltage Controlled Oscillators), Voltage and Current References.\n\nRequired:\n1. Receivers: LNA, Down conversion Mixers and Base band Filters, Auxiliary Receivers\n2. Transmitters: Transmit Base-Band Filters, Up-conversion Mixers, Driver / Power Amplifiers\n3. Synthesizers: VCO, PLL, Reference Clock Processing, DLL and Clock Multipliers, Clock & Data Recovery\n4. Data Convertors: ADC, DAC\n\nDesired:\n5. Power Management: Bandgap, LDO, Reference Current Generation.\n6. RF Calibration & Implementation\n7. Radio floor planning, Frequency planning & Packaging\n\nResponsibilities/Skills\n- In-depth understanding of Analog/RF IC circuit design, IC design tools and simulators, and IC layout design, techniques, and verification methodologies\n- Expertise in RF/Analog circuit design in sub-90nm CMOS.\n- Experience with front-end RF and Analog circuit blocks such as LNAs and Mixers, TX modulators and driver amplifiers, Frequency Synthesizers/Phase Lock Loops(PLLs), Continuous-Time Filters and ADC/DAC designs.\n- Knowledge of LTE, LTE-NR, CDMA2000, 1X-EVDO, WCDMA, UMTS, and GSM/GPRS/EDGE chipsets is a plus.\n- Knowledge of Wireless Connectivity Technologies is a plus.\n\n3+ years of experience\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "GPU (RTL) Design - Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-14T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720529458", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nMinimum 2  to 4 years of work experience in ASIC RTL Design\nExperience in Logic design/micro-architecture/RTL coding is a must.\nMust have hands on experience with design and integration of complex multi clock domainblocks\nExperience in Verilog/System-Verilog is a must.\nShould have knowledge of AMBA protocols - AXI, AHB, APB, clocking/reset/debug architecture\nHands on experience in Multi Clock designs, Asynchronous interface is a must.\nExperience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.\nUnderstanding of Memory controller designs and microprocessors is an added advantage\nWork closely with the Design verification and validation teams for pre/post Silicon debug\nHands on experience in Low power design is preferable\nExperience in Synthesis / Understanding of timing concepts for ASIC is must\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SOC Design Verification Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-14T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721564644", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field.\n\nPreferred Qualifications:\n•    Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.\n•    3+ years of ASIC design, verification, validation, integration, or related work experience.\n•    2+ years of experience with architecture and design tools.\n•    2+ years of experience with scripting tools and programming languages.\n•    2+ years of experience with design verification methods.\n Principal Duties & Responsibilities:\n•    Applies ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.\n•    Creates architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.\n•    Collaborates across teams (e.g., software architecture, hardware architecture) to develop and execute an implementation strategy that meets system requirements and customer needs.\n•    Evaluates all aspects of process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.\n•    Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable architecture and design of an individual block/SoC or IC Package.\n•    Writes detailed technical documentation for EDA/IP/ASIC projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc.  \n•    Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions).\n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RTL(IPA Design/WRD) - Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-14T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446717803981", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nQualcomm WRD team is looking for world-class RTL design engineers looking to work on Network Packet Processor IP , which will be deployed worldwide in our industry leading devices.\nResponsibilities include:\nMicroarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification.\n\nRTL ownership. Development, assessment, and refinement of RTL design to target power, performance, area, and timing goals\n\nWorking collaboratively with block designers, verification, architecture, implementation, and post-silicon teams to resolve issues and ensure timely project execution.\n\nCollaborating with cross-functional teams, debugging, and identifying issues, providing workarounds, and making recommendations on bug fixes.\n\nLeading and mentoring a team of engineers, providing technical guidance to the team\n\nLeading overall project planning efforts and execution.\n\nSkillset required \nThe candidate must have at least 5-8 years of front-end ASIC RTL design experience. The candidate must be strong in design micro-architecture and RTL coding (System Verilog / Verilog / VHDL).\nExperience in Logic design /micro-architecture / RTL coding is a must.  \n\nMust have hands on experience with SoC design and integration for SoCs. \n\nExperience in Verilog/System-Verilog is a must. \n\nShould have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC.  \n\nOther requirements include:\nHands-on experience with multi-clock designs.\n\nExposure to synthesis and STA.\n\nAwareness of low power and high-speed design.\n\nKnowledge of industry-standard front-end tool flows (lint, CDC, etc.).\n\nStrong critical thinking, problem-solving, and debugging skills.\n\nExcellent leadership, communication and interpersonal skills. Flexible to work with multi-geo teams.\n\nAbility to thrive in a fast-paced, dynamic environment and manage multiple priorities.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Peripherals (Ethernet) Validation Engineer – Senior Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-14T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721391154", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field.\n\nKey Responsibilities\nDevelop, execute and maintain comprehensive validation plans for Ethernet IP and SoC-level features across pre-silicon, emulation and post-silicon environments.\nCollaborate closely with IP architecture, design and systems teams to understand validation requirements and translate them into robust test content.\nLead bring-up, debug and root-cause analysis for complex cross-functional issues spanning hardware, drivers and platform integration.\nEnsure validation coverage is sufficient to provide high confidence in functional correctness, performance, power behavior, and production readiness.\n\nRequired Skills and Experience\nStrong hands-on experience with any of these IPs like Ethernet controllers, NIC architectures, PCIe.\nProficiency in bare-metal and Linux driver development with strong C/C++ programming and debugging skills.\nSolid understanding of embedded systems, SoC architecture, peripheral subsystems and hardware/software interaction.\nExperience validating complex SoC features across functional, performance, power and system-level scenarios.\nExposure to AI server based interconnects like ESUN/UEC, UALink protocols are preferred.\nHands-on experience with lab and debug tools such as Lauterbach TRACE32, oscilloscopes, protocol analyzers and traffic-generation equipment.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RTL Design Engineer -Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-14T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718354168", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Description\nWe are seeking a skilled RTL Design Engineer with a minimum of 7 years of experience in RTL design and verification. The ideal candidate will have hands-on experience with ARM coresight components, APB protocol, and SoC debug architecture. You will be responsible for designing, implementing, and verifying complex digital designs for cutting-edge SoC projects.\n\nKey Responsibilities\nDevelop and implement RTL designs using Verilog/SystemVerilog.\n\nCollaborate with cross-functional teams to define microarchitecture for various subsystems.\n\nPerform synthesis, static timing analysis, and formal verification.\n\nOptimize designs for power, performance, and area.\n\nWork on SoC integration, focusing on ARM-based architectures.\n\nDebug and resolve design issues, ensuring robust and high-quality deliverables.\n\nParticipate in design reviews and provide technical guidance to junior engineers.\n\nQualifications\nBachelor's or Master's degree in Electrical Engineering, Electronics & Communication Engineering, Computer Science, or a related field.\n\nMinimum 5 years of experience in RTL design and verification.\n\nProficiency in Verilog/SystemVerilog and RTL coding techniques.\n\nExperience with ARM coresight components and APB protocol.\n\nStrong understanding of SoC debug architecture.\n\nFamiliarity with industry-standard front-end tools and flows (e.g., Lint, CDC, STA).\n\nExcellent problem-solving skills and ability to work independently and in a team environment.\n\nPreferred Skills\nKnowledge of DFT concepts and design for testability.\n\nExperience with standard interfaces like SPI, I2C, and CAN.\n\nStrong understanding of constraints, timing analysis, and optimization techniques.\n\nExperience with formal verification tools and simulators.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Technical Staff Engineer - Analog & Mixed Signal Design", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-10-14", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Senior-Technical-Staff-Engineer---Analog---Mixed-Signal-Design_R4246-26-4", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nCompany Overview\nAt Microchip, we are at the forefront of technology innovation, committed to delivering cutting-edge solutions to our customers. We specialize in designing and manufacturing high-performance integrated circuits, with a focus on precision analog-to-digital converters (ADCs), DACs, Voltage References (Vrefs),  Op-Amps, Comparators, Current Sense Amplifiers, and Inductive Sensors that serve a wide range of applications in industries such as telecommunications, medical devices, instrumentation, and aerospace. Join our dedicated team of professionals who are passionate about pushing the boundaries of technology and excellence.\n\nJob Summary\nDeliver mixed signal integrated circuits that include amplifiers, references, ADCs, DACs, and digital subsystems.\nSupervise and mentor a team of Design Engineers comprising various disciplines\nInteract with an applications group and provide design expertise to deliver system solutions to our customers.\n\nRequirements/Qualifications:\n\nKey Responsibilities\nProvide senior level technical guidance to the design team through design reviews, modeling strategy, simulation methodology while delivering products on schedule.\nServe as a technical resource and mentor for junior and mid-level designers supporting sound design decisions and skills development.\nWork closely with Test, Applications, Quality, and Product Planning teams to ensure proper handoff to the other disciplines.\nManage projects through schedules, milestones, deliverables, resource allocations, and risk mitigation with the other members of the business unit.\nFamiliarity with scripting and automation tools (Skill, Python, Perl) to increase work efficiency.\nFamiliar with Automotive qualification and process flow ISO26262.\n\nQualifications\n- Bachelor's degree in Electrical Engineering, Electronics, or a related field. A Master's degree is a plus.\n- Minimum of 10+ years of hands-on experience in analog circuit design or design leadership.\n- Strong understanding of semiconductors (Op-Amp, Comparator, DAC, SAR ADC, Delta-Sigma ADC, Pipeline ADC, references, etc.) and their applications as used by our customers.\n- Experience with Cadence and other advanced design tools and flows.\n- Familiarity with RTL design and SystemVerilog / Verilog ensuring designs meet functional, timing, area and power targets.\n- Knowledge of UVM and Formal verification methodologies\n- Excellent analytical and problem-solving skills, with a detail-oriented mindset.\n- Familiarity with electromagnetic interference concepts and how to minimize and eliminate these with circuit and system solutions.\n- Effective communication skills, both written and verbal, with the ability to convey technical concepts to a diverse audience.\n- Ability to work collaboratively in a team environment and mentor more junior engineers.\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "IP RTL Senior Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-14", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/IP-RTL-Senior-Design-Engineer_JR0284056-1", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact:\n\nAs an IP Logic Design Engineer, you will play a pivotal role in developing high-quality intellectual property (IP) for Unified Intel Chassis designs. This position is at the forefront of Intel's innovation, ensuring that our products consistently deliver world-class performance, power efficiency, and reliability. Work closely with architects to define and design complex protocol bridges. Define and implement range-based access control for secured memory and register paths across HBW and LBW. Own privilege qualification and policy propagation across AXI-Lite, APB, IOSF-SB, and HBW request paths. Design and validate parity/ECC generation and checking for request, response, and data channels. Define fault behavior for unauthorized accesses and corrupt transactions, including silent block semantics, RAZWI-style handling, poison propagation, and timeout cleanup. Build or integrate logging, interrupt, and firmware-visible error harvesting flows for local and global RAS handling. Support error injection, diagnostics, and post-silicon debug hooks for both security and reliability validation. Define and implement telemetry capture for fabric load, latency, congestion, error context, and other operational health indicators. Own debug and trace data paths for wrapper-level and fabric-level observability, including data capture, transport, formatting, and handoff to downstream debug infrastructure. Design counters, sticky status, snapshots, and firmware-visible CSRs that make performance and failure analysis practical. Integrate trigger, monitor, and logging hooks needed for bring-up, stress triage, and post-silicon correlation. Work with architecture, validation, firmware, and post-silicon teams to ensure telemetry and debug signals are useful, stable, and diagnosable. Balance observability depth against area, timing, bandwidth, and survivability constraints. Support root-cause analysis of bandwidth loss, latency outliers, protocol stalls, and intermittent field or lab issues using hardware observability features.\n\nKey Responsibilities:\nDevelop logic designs, register transfer level (RTL) coding, and simulations required for IP blocks, functional units, and subsystems.\nDefine architecture and microarchitecture features for the IP block being designed.\nApply strategies, tools, and methods to optimize RTL design for power, performance, area, and timing targets.\nStrong knowledge of AXI, AXI-Lite, APB, parity/ECC schemes, and transaction error handling.\nExperience with secure MMIO, access-control/firewall logic, or privilege-based filtering.\nExperience with RAS concepts such as fault containment, poison, interrupt generation, logging, and recovery-oriented design.\nSupport SoC customers with seamless integration and verification of IP blocks.\nTelemetry and debug are both observability functions rather than primary Datapath functions.\nDrive compliance with quality assurance standards to enable smooth IP handoff within the SoC development process.\n\nQualifications:\nMinimum Qualifications:\nBachelor's degree in electrical engineering, Computer Engineering, or related field.\nA minimum of 8 years of experience in logic design and RTL development.\nProficiency in hardware description languages such as Verilog, System Verilog.\nStrong understanding of digital design principles, including timing analysis, power optimization, and area trade-offs.\nExperience with industry-standard EDA tools for design and simulation (e.g., Synopsys, Cadence, Mentor Graphics).\nKnowledge of IP block integration workflows within SoC designs.\nExpertise in RAS/debug/security/telemetry.\n\nPreferred Qualifications:\nMaster's or PhD degree in Electrical Engineering, Computer Engineering, or related field.\n10+ years of professional experience encompassing complex IP logic design for high-performance applications.\nDemonstrated expertise in architecture and microarchitecture definition.\nFamiliarity with advanced verification methodologies such as UVM or formal verification techniques.\nStrong communication and collaboration skills, with a proven ability to work effectively in cross-functional teams.\nA mindset for continuous learning and improvement, with an eagerness to tackle challenging, innovative design projects.\n\nTake the next step in your career and become part of Intel's world-class engineering team, shaping the future of technology with groundbreaking innovations. Apply today to make an impact.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "GPU Senior Logic Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-14", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/GPU-Senior-Logic-Design-Engineer_JR0288125", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nGPU Senior Logic Design Engineer:\nDevelop logic design, generate/write Register Transfer Level (RTL) code, and perform simulation for Media IP components. This includes generating essential components such as libraries and functional units and delivering complete IP blocks for full chip design integration. Participate in the definition of architecture and microarchitecture features of the block being designed. Apply various strategies, tools, and methods to generate/write RTL and optimize the logic to meet power, performance, area, timing goals, and design integrity for physical implementation. Review the verification plan and the implementation to ensure design features are correctly verified across verification hierarchies. Drive unit level verification and implement corrective measures for failing RTL tests to ensure feature correctness. Supports SoC customers to ensure high-quality integration of Media IP block. Your contributions will directly impact Intel's ability to deliver innovative graphics technologies to our customers, helping shape the future of computing\n\nBusiness group: Intel's Media HW Engineering team\n\nKey Responsibilities\n•\tConduct feature feasibility studies, performance analysis, and microarchitecture design based on landing zone requirements\n•\tDesign a wide variety of digital logic functions with the emphasis on media encoder/decoder design\n•\tDevelop, implement, and validate Register Transfer Level (RTL) design\n•\tPerform power, performance, area, and timing optimization to meet design goals\n•\tDeveloping C or Perl behavioral models to support RTL functionality verification\n•\tUtilize AI models to enhance specification development, RTL code generation, and verification collateral creation\n\nQualifications:\nEducation and Experience\n•\tBachelor's degree in Computer Engineering, Electrical Engineering, or a related field with 8+ years of industry experience in RTL design and logic development with expertise in System Verilog.\nOR\n•\tMaster's degree in Computer Engineering, Electrical Engineering, or a related field with 6+ years of industry experience in RTL design and logic development with expertise in System Verilog.\n\nRequired skills and experience\n•\tComputer system architecture\n•\tDigital electronics and logic design\n•\tVerilog or System Verilog\n•\tLogic verification, synthesis, and timing analysis tools\n•\tC, Perl, and Python programming\n•\tAI-assisted ASIC Design and Verification tools.\n\nPreferred skills and experience\n•\tKnowledge of video codec standards such as H.264, HEVC, VP8/9, AV1, VVC, and other popular codecs\n•\tAdvanced knowledge of microarchitecture fundamentals and logic design verification methodologies.\n•\tStrong communication, collaboration, and problem-solving skills\n•\tSelf-motivated and self-directed, with the ability to work effectively both independently and as part of a team\n•\tProven ability to effectively debug microarchitecture and hardware simulations.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Chassis IP Senior Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-14", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Chassis-IP-Senior-Design-Engineer_JR0287883", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nIntel is seeking an experienced Logic Design engineer for the Intel Chassis Group, which is chartered to deliver the chassis for SoCs within Intel. The role involves logic design of component and foundation IPs which can be used to build an SoC chassis. The ideal candidate will have strong design and Verilog skills and some background in protocol conversion bridges for AMBA/CXL protocols. Understanding of concepts such as QoS, access control, flow control, debug, RAS, security and error handling is a plus.\n\nKey Responsibilities\n- Develop logic designs, register transfer level (RTL) coding, and simulations required for functional units, IP blocks, and subsystems.\n- Define and implement architecture and microarchitecture features for the interconnect IP block and sub-system which includes high-performance data plane and control plane routers, switches, arbiters, protocol conversion bridges, debug/trace components, and clock and power controls.\n- Perform rigorous quality checks and optimization of RTL designs to improve IP power, performance, area, and timing, ensuring delivery of high-quality IP.\n- Evaluate design trade-offs across area, bandwidth, timing, and reliability to achieve balanced and efficient IP functionality.\n- Support Sub-system/SoC customers with high-quality IP integration and verification workflows.\n\nQualifications:\nMinimum Qualifications\n- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with a minimum of 10 years of experience in logic design and RTL development.\n- Proficiency in Verilog/System Verilog and RTL coding.\n- Expertise in AMBA (CHI, AXI, AHB, APB) and PCIe/CXL protocols.\n- Experience with Lint/CDC/RDC tools and methodologies.\n- Strong understanding of power, performance, Timing and area optimization strategies in complex designs.\n\nPreferred Qualifications\n- 5+ years of experience designing network components such as routers, switches, arbiters, or protocol conversion bridges.\n- Knowledge of debug/trace networks, flow control, and hashing methodologies.\n- Experience working with leading-edge semiconductor nodes.\n- Background in DVFS (Dynamic Voltage Frequency Scaling) and UPF (Unified Power Format).\n- Understanding of RAS (Reliability, Availability, and Serviceability) features.\n- Proven ability to collaborate across geographically distributed teams and adapt to multi-time zone working environments.\n- Familiarity with coherency concepts and memory subsystems.\n\nJoin Intel and contribute to transformative innovations in semiconductor design that shape the future of technology.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Chassis IP Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-14", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Chassis-IP-Design-Engineer_JR0287882", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nAs an IP Logic Design Engineer, you will be instrumental in developing and optimizing logic designs for high-performance IP blocks that drive Intel's cutting-edge SoC solutions. Your day-to-day responsibilities will include writing register transfer level (RTL) code, conducting simulations, and ensuring designs meet stringent power, performance, area, and timing goals. You'll play a pivotal role in delivering quality IPs while collaborating across architecture, verification, and SoC integration teams to ensure seamless handoffs and impactful results.\n\nBusiness group\nThe Central Engineering Group (CEG) is Intel's leading innovation hub, focused on designing foundational technologies for integration across Intel's product portfolio. Within this team, the UIC Fabric Design organization specializes in developing reusable IP blocks and subsystems that enhance system-level capabilities. This group contributes to Intel's broader mission of delivering world-class solutions to revolutionize computing across industries.\n\nKey Responsibilities\n- Design and develop RTL code for IP blocks, ensuring functionality, quality, and scalability.\n- Optimize logic designs to meet power, performance, area, and timing objectives.\n- Collaborate with architecture teams to define microarchitecture features of IP designs.\n- Participate in verification plan reviews and implement corrective measures for failing RTL tests.\n- Support SoC integration teams to ensure high-quality integration and verification of IP blocks.\n- Work with physical design teams to address timing and implementation challenges.\n- Drive compliance with quality assurance standards for seamless IP-SoC handoff.\n\nQualifications:\nMinimum Qualifications\n- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 4+ years of experience in state-of-the-art SoC or IP design OR Master's degree with 3+ years of experience.\n- Proficiency in Verilog/System Verilog, including Lint/CDC/RDC tools and methodologies.\n- Demonstrated ability to optimize designs for power, performance, and area trade-offs (PPA).\n\nPreferred Qualifications\n- Familiarity with AMBA (CHI, AXI, AHB, APB) and PCIe/CXL protocols.\n- Experience in designing IP subsystems, including protocol conversion bridges and debug/trace components.\n- Understanding of concepts such as QoS, access control, flow control, RAS, and security/error handling.\n- Proven ability to collaborate across architecture, verification, and SoC integration teams effectively.\n- Familiarity with using AI tools to assist logic design.\n- Strong communication skills and experience working with globally distributed teams across time zones.\n\nWe invite you to join our team, where you'll be empowered to innovate, collaborate, and leave a lasting impact on the future of computing.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Senior Applications Engineer – FPGA Tools", "company": "Lattice", "location": "LSV", "date_posted": "2026-10-14", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/LSV/Applications-Engineer_R-100746", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\n\nJob Description:\n​We are looking for a Senior Applications Engineer – FPGA Tools to join our team. This position requires knowledge and experience in the entire FPGA development tool flow from design entry to place-and-route and timing closure. Preferred skills include simulation, scripting, and RTL design experience. Experience with Lattice FPGA design software tools is a plus. \n\nKey Responsibilities \nEnable FPGA software tool adoption through:  \n\nConducting analysis of tool capabilities and user requirements. \n\nPreparing documentation and best practices for tool usage. \n\nDelivering training sessions and user enablement programs. \n\nProvide ITAR compliant support, ensuring adherence to export control regulations and internal processes. \n\nCollaborate with engineering teams to improve workflows and tool integration. \n\nTroubleshoot and resolve issues related to FPGA development tools and operating environments. \n\nStrong expertise in scripting/programming and comfortable using AI tools and frameworks for automation \n\nAct as a subject matter expert for FPGA design flows, assisting customers and internal teams. \n\nPreferred Qualification (Requirements) \nThe following experience and skills are required for this position: \n\nMust be a U.S. person for Aerospace and Defense market segment support \n\nBSEE or similar degree \n\n5+ years of FPGA design tool experience (e.g., Radiant, Diamond, Quartus, Vivado) \n\nStrong understanding and experience in Verilog/VHDL/SystemVerilog  \n\nStrong understanding and experience in logic synthesis tools such as Synplify Pro \n\nStrong understanding and experience in FPGA implementation flow such as place-and-route, static timing analysis, and timing closure \n\nSolid experience working with Linux environments, with the ability to manage and troubleshoot OS-level issues as needed \n\nOutstanding English communication skills, both written and verbal \n\nAbility to work independently and collaboratively in a team environment \n\nThe following experience and skills are a plus for this position: \nExperience with a variety of EDA software simulation tools for FPGA development, including ModelSim/QuestaSim, VCS, and/or Xcelium \n\nGood understanding of FPGA architecture and applications \n\nHands-on FPGA development experience, including verification \n\nScripting languages such as TCL, Perl, or Python \n\nPay & Benefits\n\nConsistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. \n\nFor candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.  The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.\n\nBase Pay Range\n148753.481\nIn addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! \n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in the United States.\n\nLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.\n \nAs an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.", "jd_status": "stored"}, {"title": "Senior Design Verification Engineer", "company": "Lattice", "location": "LPQ", "date_posted": "2026-10-14", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/LPQ/Senior-Design-Verification-Engineer_R-101078", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation and customer service, and to that focus we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\n\nLattice Semiconductor is seeking a Senior Design Verification Engineer to join the Silicon team. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn and grow.\n\nAccountabilities: \nDevelop comprehensive verification plans, clear metrics and continuously measure progress against the plan throughout the project\nVerify design blocks, sub systems and full chip using assertion-based verification, formal verification, directed tests and randomized tests\nUnderstand the specifications, use cases and develop System Verilog and ‘C’ based testbenches in UVM environment\nDesign and develop testbench components such as Universal Verification Components, BFMs and verification tools\nDefine and design verification regression environment\nPerform Functional coverage, RTL code coverage, assertion coverage, and gate level simulations\nCollaborate with design engineers, IP developers and SW developers to deliver high quality SoC verification on aggressive time schedules\nDevelop best practices and world class methods for SoC verification\n\nRequired Skills\n6-10 years Digital Design Verification Related Experience\nBachelor or Masters Degree in Computer Science, Computer Engineering, Electronics and Electrical Engineer\nSkill in debugging and analyzing complex digital design\nExperience in HDL and HVL Languages and Methodologies\nExperience in ASIC/FPGA/SoC verification or development cycle\nExperience in simulation tools like Cadence IES/XCELIUM, Synopsys VCS or Mentor's Questa\nHands-on experience in Python, Perl or Shell Scripting, TCL and Make.\nStrong communication, analytical and documentation skills and ability to interface with other groups/site\nStay up to date on industry trends and direction of verification technology development\n\nLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.\n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.\n\nLattice\nFeel the energy.\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "System Integration Engineer_SEM (Semiconductor)", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2026-10-14", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/System-Integration-Engineer-SEM--Semiconductor-_R2627245", "is_hardware": true, "platform": "workday", "jd_text": "Who We Are\n\nApplied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI and accelerating the commercialization of next-generation semiconductor chips. Join us and push the boundaries of materials science and engineering in a company at the foundation of the electronics industry. The work we do together advances the world’s technology.\n\nWhat We Offer\n\nLocation:\nBangalore,IND\nYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. \n\nAt Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. \n \n \nAs a Manufacturing Engineer, you are responsible for developing and maintaining methods, operating sequences, and processes in the fabrication of parts, components, subassemblies, and final assemblies. You'll work closely with other engineering functions to coordinate the release of product improvements and new products, and you'll use engineering principles to estimate and reduce manufacturing costs, improve product quality, determine time standards, and make recommendations for tooling and process requirements. Your expertise in lean principles, automation, and continuous improvement will be instrumental in driving operational excellence and achieving higher levels of productivity and cost-effectiveness. You'll develop and use test procedures, evaluate test results, and assess work methods, procedures, and policies to identify root cause issues and solutions that ensure operational success. \n \nWe are looking for a highly talented integration engineer to join our team and integrate complex multi-disciplinary systems modules (Scanning Electron Microscopes).\n\nWhat’s in it for you?\nAs part of our team, you will work together with great people, hands-on with one of the most complex multi-disciplinary systems in the market, putting into practice many of the fields from your studies.\n\nOur Group:\nThe team is responsible for system Scanning Electron Microscopes integration for Applied Materials - Metrology and Inspection tools before shipment to the customer.\nIn addition, we lead R&D prototypes and new products in the organization, with large exposure to the most advanced technologies such as precise mechanics, electronics, motion and optics.\n\nWhat you'll be doing:\nThe system integration engineer gets a fully assembled Scanning Electron Microscopes. His job is to calibrate and test a multi-disciplinary system, in clean room environment, from start to end until shipment to the customer includes complicated troubleshooting, investigation and engineering solutions proposal.\nSince we are talking about a Scanning Electron Microscopes with Very high complexity multi-disciplinary system involving several modules and disciplines, such as E-Beam (Electron-beam Microscopy), high-end optics, lasers, precise mechanics, RF, motion and control etc., the essence of our work requires high system understanding, deep engineering knowledge and high accountability level.\n\nRole and responsibilities: -\n1. Responsible for technical support to meet the system’s specifications & team KPIs: on time delivery, Operational aspects of the tool’s integration process, Lab Tool fleet performance\n2. Performs highly complex operational and functional tests, calibrations, verification of sub-assemblies and/or systems\n3. Troubleshoots modules and fully integrates systems. Performs in-house customer acceptance tests.\n4. Travels to Applied materials - PDC Israel site to install and support tools.\n5. Follow and complete documentation procedures and forms of semiconductor manufacturing equipment. Pursue and develop procedural, safety and process improvements. Identify problems and resolve problems as an individual or as a team.\n6. Working 5 days/week from Bangalore Office (Saturday & Sunday a must).\n\nWhat should you have?\nBachelor's degree  B. Tech Electrical Engineer \n2-4 years of relevant technical experience: System integration experience or other high complex technical background - Advantage\n10 - 30% travelling\nTeam player, Highly Creative and Proactive\nHigh level of independent work with constant drive for improvement\n\nThis is a physically demanding position that often requires extensive walking, standing for extended periods of time, working in tight spaces, bending, squatting, twisting, kneeling, reaching, climbing stairs and ladders, lifting up to 35 lbs., the ability to distinguish between colors, the ability to work in an environment with noise that may be difficult for some individuals with sensitivity to noise, and the use of hand and power tools.\nFunctional Knowledge\nDemonstrates expanded conceptual knowledge in own discipline and broadens capabilities\n\nBusiness Expertise\nUnderstands key business drivers; uses this understanding to accomplish own work\n\nLeadership\nNo supervisory responsibilities but provides informal guidance to new team members\n\nProblem Solving\nSolves problems in straightforward situations; analyzes possible solutions using technical experience and judgment and precedents \n\nImpact\nImpacts quality of own work and the work of others on the team; works within guidelines and policies\n\nInterpersonal Skills\nExplains complex information to others in straightforward situations\n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nAssignee / Regular\nTravel:\nYes, 25% of the Time\nRelocation Eligible:\nYes\n\nApplied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "Senior Principal Engineer, Emulation", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-10-14", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Senior-Principal-Engineer--Emulation_2604369", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nCustom Compute and Storage (CCS) Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. The Emulation Center of Excellence (CoE) team is key part of this group, with global ownership and responsibility for delivering emulation infrastructure, validating the design on emulation and drive left shift of SW and post-silicon readiness for all of CCS products.\n\nAs part of the Emulation CoE leadership, you will drive the emulation strategy, vendor platform enablement, testplan execution for a high-quality design tape-out.\nWhat You Can Expect\nAs part of a strong technical team of emulation experts, define the emulation strategy and platform requirements, develop emulation testplan, and drive execution of the emulation verification for large CCS products on emulation platform such as Veloce, Zebu and Palladium.\nWork with project lead and various stakeholders to define the emulation HW requirements for CCS products, including platforms, hardware/software collaterals, transactors, speed-bridges etc.\nWork closely with emulation hardware vendor application engineers (AEs) to keep the emulation hardware, software ecosystem updated, drive debug and resolution of issues with the vendor and design team.\nDefine and develop new capabilities HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for pre-Silicon and post-Silicon functional validation as well as SW development/validation\nInterface with and provide guidance to pre-silicon Validation teams for optimizing pre-Si validation environments, test suites and methodologies for emulation efficiency\nDevelop and apply automation aids, flows and scripts in support of emulation ease of use and improvement of equipment utilization.\n\nWhat We're Looking For\nBachelor’s degree in Computer Science, Electrical Engineering or related fields and 17+ years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 15+ years of experience.\nSubstantial knowledge of emulation platforms offerings from various vendors such as Synopsys, Cadence, Seimens including extensive experience in building complex SOC emulation models\nWorking knowledge in one or more of the following: Processor architecture, SOC components, SOC inter-connect buses, IO protocols (PCIe, CXL, Ethernet) and memory technologies interfaces (DDR, HBM)\nStrong understanding of product development process of large SOCs and verification/debug experience in emulation platforms.\nStrong experience in coding in scripting languages like Perl, Python, Tcl & UNIX Shell etc\n\nThis role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.\nAdditional Compensation and Benefit Elements\nWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\n\nInterview Integrity \nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\n\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\n\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n\n#LI-CP1", "jd_status": "stored"}, {"title": "Principal Engineer, Emulation", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-10-14", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Principal-Engineer--Emulation_2604370", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nCustom Compute and Storage (CCS) Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. The Emulation Center of Excellence (CoE) team is key part of this group, with global ownership and responsibility for delivering emulation infrastructure, validating the design on emulation and drive left shift of SW and post-silicon readiness for all of CCS products.\nAs part of the Emulation CoE leadership, you will drive the emulation strategy, vendor platform enablement, testplan execution for a high quality design tape-out.\nWhat You Can Expect\nAs part of a strong technical team of emulation experts, define the emulation strategy and platform requirements, develop emulation testplan, and drive execution of the emulation verification for large CCS products on emulation platform such as Veloce, Zebu and Palladium.\nWork with project lead and various stakeholders to define the emulation HW requirements for CCS products, including platforms, hardware/software collaterals, transactors, speed-bridges etc.\nWork closely with emulation hardware vendor application engineers (AEs) to keep the emulation hardware, software ecosystem updated, drive debug and resolution of issues with the vendor and design team.\nDefine and develop new capabilities HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for pre-Silicon and post-Silicon functional validation as well as SW development/validation\nInterface with and provide guidance to pre-silicon Validation teams for optimizing pre-Si validation environments, test suites and methodologies for emulation efficiency\nDevelop and apply automation aids, flows and scripts in support of emulation ease of use and improvement of equipment utilization.\n\nWhat We're Looking For\nBachelor’s degree in Computer Science, Electrical Engineering or related fields and 13+ years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 10+ years of experience.\nProven track record of managing technical teams and leading cross-functional teams for design emulation and verification.\nSubstantial knowledge of emulation platforms offerings from various vendors such as Synopsys, Cadence, Seimens including extensive experience in building complex SOC emulation models\nWorking knowledge in one or more of the following: Processor architecture, SOC components, SOC inter-connect buses, IO protocols (PCIe, CXL, Ethernet) and memory technologies interfaces (DDR, HBM)\nStrong understanding of product development process of large SOCs and verification/debug experience in emulation platforms.\nStrong experience in coding in scripting languages like Perl, Python, Tcl & UNIX Shell etc\n\nThis role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.\nAdditional Compensation and Benefit Elements\nWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\n\nInterview Integrity \nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\n\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\n\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n\n#LI-CP1", "jd_status": "stored"}, {"title": "Senior Staff Engineer - Emulation", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-10-14", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Senior-Staff-Engineer---Emulation_2604372", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nCustom Compute and Storage (CCS) Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. The Emulation Center of Excellence (CoE) team is key part of this group, with global ownership and responsibility for delivering emulation infrastructure, validating the design on emulation and drive left shift of SW and post-silicon readiness for all of CCS products.\nAs part of the Emulation CoE leadership, you will drive the emulation strategy, vendor platform enablement, testplan execution for a high quality design tape-out.\nWhat You Can Expect\nAs part of a strong technical team of emulation experts, define the emulation strategy and platform requirements, develop emulation testplan, and drive execution of the emulation verification for large CCS products on emulation platform such as Veloce, Zebu and Palladium.\nWork with project lead and various stakeholders to define the emulation HW requirements for CCS products, including platforms, hardware/software collaterals, transactors, speed-bridges etc.\nWork closely with emulation hardware vendor application engineers (AEs) to keep the emulation hardware, software ecosystem updated, drive debug and resolution of issues with the vendor and design team.\nDefine and develop new capabilities HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for pre-Silicon and post-Silicon functional validation as well as SW development/validation\nInterface with and provide guidance to pre-silicon Validation teams for optimizing pre-Si validation environments, test suites and methodologies for emulation efficiency\nDevelop and apply automation aids, flows and scripts in support of emulation ease of use and improvement of equipment utilization.\n\nWhat We're Looking For\nBachelor’s/Master's/phd degree in Computer Science, Electrical Engineering or related fields and 8+ years of related professional experience .\nProven track record of managing technical teams and leading cross-functional teams for design emulation and verification.\nSubstantial knowledge of emulation platforms offerings from various vendors such as Synopsys, Cadence, Seimens including extensive experience in building complex SOC emulation models\nWorking knowledge in one or more of the following: Processor architecture, SOC components, SOC inter-connect buses, IO protocols (PCIe, CXL, Ethernet) and memory technologies interfaces (DDR, HBM)\nStrong understanding of product development process of large SOCs and verification/debug experience in emulation platforms.\nStrong experience in coding in scripting languages like Perl, Python, Tcl & UNIX Shell etc\n\nThis role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.\nAdditional Compensation and Benefit Elements\nWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\n\nInterview Integrity \nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\n\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\n\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n\n#LI-CP1", "jd_status": "stored"}, {"title": "Senior Engineer, Logic Equivalence CAD", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-10-14", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Senior-Engineer--Logic-Equivalence-CAD_2604938-1", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nAbout Marvell\n\nMarvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.\n\nYour Team, Your Impact\n\nAs a Staff Logic Equivalence Engineer, you'll be part of Marvell's CAD  team, developing the Equivalence Checking infrastructure that underpins design integrity across Marvell's various Business Units. Your work ensures that RTL-to-Gate and Gate-to-Gate transformations preserve functional correctness, directly enabling confident, high-quality tape-outs across the company's product lines.\nWhat You Can Expect\nDevelop and maintain leading-edge Equivalence Checking flows addressing the needs of Marvell's various Business Units.\nApply strong debugging capabilities to root-cause and resolve equivalence issues.\nContribute to seamless RTL2Gate and Gate2Gate logic equivalence flow development, including understanding of pin constraints, don't-verify points, and other considerations based on DFT requirements.\nWork closely with the synthesis and DFT teams to ensure a seamless handoff into the equivalence flow.\nContribute to functional ECO flows.\nContribute to low-power checks within the equivalence methodology.\nSupport the deployment and ongoing support of these flows.\nCollaborate with the broader team to ensure optimal integration within the overall CAD platform.\nDevelop innovative solutions to address ever-increasing design challenges.\nStay current with evolving processes and tools.\nInterface with EDA vendors to ensure optimal tool usage.\n\nWhat We're Looking For\nBachelor's or Master's degree in EE/CS with 2+ years of hands-on experience in Equivalence Checking and functional ECO flow development.\nRecent experience with either Cadence Conformal or Synopsys Formality toolsets (experience with both is a plus).\nSolid understanding of: Synthesis transforms'-to-Gate level logic equivalence debug. Functional ECO flows. Power intent and multiple power domain management. Basic knowledge of RTL coding. Basic DFT understanding (controllability, observability, scan chain stitching) and the constraints needed for equivalence checking.\nGood level of proficiency in Tcl scripting in the context of flow development.\nStrong analysis and problem-solving skills, with the ability to think outside the box.\nTeam player with good verbal and written communication skills.\n\nThis role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.\nAdditional Compensation and Benefit Elements\nWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\n\nInterview Integrity \nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\n\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\n\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n\n#LI-CP1", "jd_status": "stored"}, {"title": "Senior Silicon Product Definition Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-14", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Silicon-Product-Definition-Engineer_JR2026056", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has transformed computer graphics, PC gaming, and accelerated computing for more than 25 years. Today, we're defining the next era of computing, where GPUs power the computers, robots, and autonomous vehicles that understand the world. NVIDIA's Silicon Co-Design Group (SCG) gets every GPU, SoC, and CPU program from first power-on to high-volume production. We sit at the crossroads of architecture, design, marketing, operations, and productization, serving Datacenter, Server, Gaming, Robotics, Automotive, and Embedded markets.\n\nWe are hiring a Senior Silicon Product Definition Engineer to turn complex silicon and system data into decisions that maximize performance, power efficiency, yield, and quality. You will define product configurations, identify limiting constraints, and drive optimization from early bring-up through production. This is not a pure data-analysis or validation-only role—you will connect silicon behavior, platform requirements, market needs, and manufacturing realities to determine how products are productized. The exceptional hire uses AI deliberately to compress analysis and debug cycles.\n\nWhat you'll be doing:\nOwn product-definition analysis across performance, power, yield, and quality, using large silicon datasets to identify product opportunities, risks, and trade-offs.\n\nDrive product-specific configurations by isolating frequency- power and thermal-limiting constraints and translating findings into silicon, firmware, BIOS, driver, and platform changes.\n\nBuild statistical models, automation, and visualization workflows that improve decision quality.\n\nPartner with Tools and Methodology teams to left-shift data modeling, test procedures, and closed-loop analysis infrastructure from post-silicon learning into future programs.\n\nLead multi-functional root-cause closure with architecture, design, validation, software/firmware, applications engineering, manufacturing, and operations teams from bring-up through production.\n\nEvaluate performance-per-watt, process-voltage-temperature behavior, yield, and quality trade-offs, and drive productized fixes through implementation and confirmation.\n\nTranslate complex silicon and system signals into crisp, decision-ready options that give executive leadership clarity on product configuration, performance targets, and program-impacting risks.\n\nOwn and deliver BIOS-level VF settings across thermal, power, and frequency domains — debugging issues and driving fixes through cross functional teams to close on Power, Thermal, Performance, Yield and Quality gaps.\n\nWhat we need to see:\nBS or MS in Electrical Engineering, Electronics Engineering, Systems Engineering.\n\n5+ years of experience in silicon product definition, post-silicon characterization, product engineering, or performance and power analysis for GPU, CPU, SoC, or other complex silicon products.\n\nHands-on experience with silicon bring-up, performance-per-watt analysis, optimization across process, voltage, and temperature conditions.\n\nStrong programming and data-analysis skills using Python and one or more of Perl, JMP, SQL, or equivalent tools, with practical knowledge of statistics and large-dataset manipulation.\n\nStrong technical foundation in digital design, circuit analysis, computer architecture, critical-path analysis, process technology, and transistor/device physics.\n\nWorking knowledge of the system stack, including firmware, BIOS, drivers, operating-system behavior, and software applications that influence silicon performance and power.\n\nDemonstrated ability to drive ambiguous technical issues to root-cause closure across globally distributed, multi-functional teams.\n\nStrong written and verbal communication; able to translate complex technical issues into crisp, decision-ready options for executive leadership.\n\nWays to stand out from the crowd:\nTrack record of defining and shipping product configurations that measurably improved performance, power efficiency, yield, quality, or time to market.\n\nExperience with advanced process nodes and high-complexity GPU, CPU, AI accelerator, automotive, or datacenter products.\n\nExperience building reusable product-definition methodologies, statistical models, or automation adopted across multiple silicon programs.\n\nProficiency with AI productivity tools such as Claude, Copilot, ChatGPT, or equivalent to accelerate analysis, debug, drafting, and decision-making workflows—with clear outcomes and appropriate guardrails.\n\nComfort navigating ambiguity, building technical structure in speed-of-light silicon programs, and collaborating with global teams from diverse cultural backgrounds.\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered one of the world's most desirable technology employers. We welcome you to join our team and help define the next era of accelerated computing.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Silicon Power & Performance Engineer (System Level Test & Characterization)", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-10-14", "url": "https://careers.arm.com/job/bengaluru/silicon-power-and-performance-engineer-system-level-test-and-characterization/33099/96899126992", "is_hardware": true, "platform": "talentbrew", "jd_text": "Staff System Level Test and Characterization Engineer: \n\nJob Overview: \nJoin Arm as a Engineer/Senior Engineer/Staff System Level Test and Characterization Engineer in Bengaluru, Karnataka, India, and become part of a group that fosters world-class innovation! This outstanding opportunity enables you to work on ambitious projects, ensuring flawless power, performance, and thermal characterization of Arm silicon. \nResponsibilities: \nPlan and execute Silicon PVTF characterization activities across multiple projects and platforms. \nDevelop scalable automation frameworks, regression infrastructure, data collection flows, dashboards, and reporting tools. \nAnalyze leakage/static, active-idle, dynamic, and Silicon boot power to identify bottlenecks and optimization opportunities. \nCharacterize voltage droop and loadline impedance. \nEnable and port industry-standard, customer, and stress workloads required for silicon characterization. \nCollaborate with SoC architecture, firmware, validation, and systems teams to debug and resolve silicon issues. \n\nNecessary Skills and Experience: \nBachelor’s degree in science or engineering; master’s degree Preferred. \n2 to 12 years of experience in post-silicon characterization or validation. \nExperience in characterizing any of the SoC IPs such as CPU, interconnect, DDR, PCIe, UCIe, or high-speed I/O subsystems. \nHands-on experience with lab equipment including oscilloscopes, DAQ systems, thermal chambers, power analyzers, and control units/devices for measurement and debug. \nUnderstanding of power and Performance optimization techniques. \nExperience with benchmarking and profiling tools such as SPEC2017, LMBench, Stress-ng, Fio, iPerf, or equivalent. \nGood understanding of VRMs, PMICs, voltage rails, power delivery networks, and control mechanisms. \nAbility to analyze and interpret large datasets from instrumentation and telemetry systems. \nExperience working with firmware, bootloader, UEFI/BIOS, ACPI, or device tree flows. \n\nPreferred Skills and Experience: \nUS B1/B2 valid Visa. \nProven background in performing VMIN analysis for any of the SoC IPs (CPU, Interconnect etc.) \nExperience with pre-silicon modeling, simulation, emulation, or FPGA platforms. \nExperience closing pre- and post-silicon power and performance correlation. \nScripting experience in Python, Shell, Perl, or similar languages. \nProgramming experience in C/C++ for low-level system software. \nExperience in silicon bring-up, board enablement, validation of power management features such as DVFS, AVS, thermal throttling etc. \nUnderstanding of Arm architecture, SoC architecture, firmware flows, and platform power/performance trade-offs. \n\n#LI-PS2\n \nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\n\n \nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Engineer, Physical Design", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-14", "url": "https://careers.synopsys.com/job/bengaluru/senior-engineer-physical-design/44408/101953613088", "is_hardware": true, "platform": "talentbrew", "jd_text": "Senior Engineer, Physical Design – PnR Implementation & Methodology\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou are an experienced Physical Design engineer with strong expertise in Place and Route (PnR) design implementation and flow methodologies. You have a comprehensive understanding of the complete PnR development flow and hands-on experience using industry-standard physical design tools such as Synopsys Fusion Compiler (FC) or Cadence Innovus.\nYou understand physical design signoff methodologies and have exposure to tools such as IC Validator (ICV), RedHawk, PrimeTime, and StarRC, or equivalent solutions. Along with executing designs, you are interested in continuously improving implementation flows, methodologies, and Power, Performance, and Area (PPA).\nYou bring strong debugging, analytical, and problem-solving capabilities and are comfortable collaborating with cross-cultural, geographically distributed, and matrixed engineering teams.\nWhat You'll Be Doing\nDrive Place and Route (PnR) implementation for complex semiconductor designs.\nExecute and optimize physical design flows across key stages of the PnR lifecycle.\nWork extensively with Fusion Compiler (FC) and/or Innovus for design implementation.\nPerform and support physical design signoff using methodologies and tools such as ICV, RedHawk, PrimeTime, and StarRC, or similar.\nAnalyze implementation results and identify opportunities for PPA improvement.\nContribute to continuous improvement of physical design flows, methodologies, and flow usage.\nDebug complex implementation and flow issues using strong analytical and problem-solving skills.\nCollaborate with engineering teams across different functions, geographies, and cultures.\nExplore productivity improvements through modern engineering and AI-assisted tools such as Cursor.\nThe Impact You Will Have\nHelp deliver high-quality physical design implementation for advanced semiconductor designs.\nImprove Power, Performance, and Area (PPA) through design and flow optimization.\nEnhance the efficiency, robustness, and scalability of PnR implementation methodologies.\nIdentify and resolve complex physical design and signoff issues.\nContribute to continuous improvement and automation of implementation flows.\nEnable effective collaboration across global and cross-functional engineering teams.\nWhat You'll Need\nBS/B.Tech in Electrical Engineering (EE), Electronics & Communication Engineering (ECE), or equivalent with 3+ years of relevant experience, OR\nMS/M.Tech in EE, ECE, or equivalent with 2+ years of relevant experience.\nStrong hands-on experience in PnR design implementation and/or PnR flow methodologies.\nComprehensive understanding of the PnR development flow.\nGood hands-on experience with Fusion Compiler (FC) or Innovus.\nGood understanding of physical design signoff tools and methodologies.\nExperience or exposure to ICV, RedHawk, PrimeTime, StarRC, or similar tools.\nExperience contributing to PPA improvement and flow optimization activities.\nStrong debugging, analytical, and problem-solving skills.\nExcellent collaboration and influencing skills with the ability to work effectively in cross-cultural, multi-geography, and matrixed teams.\nExposure to AI-assisted engineering tools such as Cursor is a plus.\nWho You Are\nYou approach complex physical design challenges methodically and drive them through resolution.\nYou enjoy debugging implementation, timing, physical verification, and flow-related issues.\nYou look beyond basic design closure and continuously seek opportunities to improve PPA and implementation efficiency.\nYou communicate technical issues clearly and collaborate effectively with geographically distributed teams.\nYou are comfortable taking ownership while working as part of a broader engineering organization.\nYou are curious about new methodologies, automation, and AI-assisted engineering approaches.\nThe Team You'll Be Part Of\nYou will be part of a physical design engineering team focused on PnR implementation, design closure, signoff, flow methodology, and PPA optimization. You will collaborate with cross-functional and geographically distributed engineering teams to improve implementation quality, resolve complex design challenges, and continuously enhance physical design methodologies.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Staff Engineer, Physical Design", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-14", "url": "https://careers.synopsys.com/job/bengaluru/staff-engineer-physical-design/44408/101953613072", "is_hardware": true, "platform": "talentbrew", "jd_text": "Staff Engineer, Physical Design – PnR Implementation & Methodology\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou are an experienced Physical Design engineer with strong expertise in Place and Route (PnR) design implementation and flow methodologies. You have a comprehensive understanding of the complete PnR development flow and hands-on experience using industry-standard physical design tools such as Synopsys Fusion Compiler (FC) or Cadence Innovus.\nYou understand physical design signoff methodologies and have exposure to tools such as IC Validator (ICV), RedHawk, PrimeTime, and StarRC, or equivalent solutions. Along with executing designs, you are interested in continuously improving implementation flows, methodologies, and Power, Performance, and Area (PPA).\nYou bring strong debugging, analytical, and problem-solving capabilities and are comfortable collaborating with cross-cultural, geographically distributed, and matrixed engineering teams.\nWhat You'll Be Doing\nDrive Place and Route (PnR) implementation for complex semiconductor designs.\nExecute and optimize physical design flows across key stages of the PnR lifecycle.\nWork extensively with Fusion Compiler (FC) and/or Innovus for design implementation.\nPerform and support physical design signoff using methodologies and tools such as ICV, RedHawk, PrimeTime, and StarRC, or similar.\nAnalyze implementation results and identify opportunities for PPA improvement.\nContribute to continuous improvement of physical design flows, methodologies, and flow usage.\nDebug complex implementation and flow issues using strong analytical and problem-solving skills.\nCollaborate with engineering teams across different functions, geographies, and cultures.\nExplore productivity improvements through modern engineering and AI-assisted tools such as Cursor.\nThe Impact You Will Have\nHelp deliver high-quality physical design implementation for advanced semiconductor designs.\nImprove Power, Performance, and Area (PPA) through design and flow optimization.\nEnhance the efficiency, robustness, and scalability of PnR implementation methodologies.\nIdentify and resolve complex physical design and signoff issues.\nContribute to continuous improvement and automation of implementation flows.\nEnable effective collaboration across global and cross-functional engineering teams.\nWhat You'll Need\nBS/B.Tech in Electrical Engineering (EE), Electronics & Communication Engineering (ECE), or equivalent with 5+ years of relevant experience, OR\nMS/M.Tech in EE, ECE, or equivalent with 3+ years of relevant experience.\nStrong hands-on experience in PnR design implementation and/or PnR flow methodologies.\nComprehensive understanding of the PnR development flow.\nGood hands-on experience with Fusion Compiler (FC) or Innovus.\nGood understanding of physical design signoff tools and methodologies.\nExperience or exposure to ICV, RedHawk, PrimeTime, StarRC, or similar tools.\nExperience contributing to PPA improvement and flow optimization activities.\nStrong debugging, analytical, and problem-solving skills.\nExcellent collaboration and influencing skills with the ability to work effectively in cross-cultural, multi-geography, and matrixed teams.\nExposure to AI-assisted engineering tools such as Cursor is a plus.\nWho You Are\nYou approach complex physical design challenges methodically and drive them through resolution.\nYou enjoy debugging implementation, timing, physical verification, and flow-related issues.\nYou look beyond basic design closure and continuously seek opportunities to improve PPA and implementation efficiency.\nYou communicate technical issues clearly and collaborate effectively with geographically distributed teams.\nYou are comfortable taking ownership while working as part of a broader engineering organization.\nYou are curious about new methodologies, automation, and AI-assisted engineering approaches.\nThe Team You'll Be Part Of\nYou will be part of a physical design engineering team focused on PnR implementation, design closure, signoff, flow methodology, and PPA optimization. You will collaborate with cross-functional and geographically distributed engineering teams to improve implementation quality, resolve complex design challenges, and continuously enhance physical design methodologies.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Sr Engineer - Physical Design & Signoff (Synthesis to GDS2)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-14", "url": "https://careers.synopsys.com/job/bengaluru/sr-engineer-physical-design-and-signoff-synthesis-to-gds2/44408/95856495904", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\n\nYou Are\nYou are an experienced, self-motivated engineering professional with a deep-rooted passion for semiconductor technology and innovation. Your technical expertise spans Physical Design, Physical Verification, and Static Timing Analysis (STA) at the IP/block/full chip level, and you are adept at navigating the complexities of advanced Finfet and GAA process technologies. You thrive in fast-paced, collaborative environments, drawing energy from teamwork and cross-functional problem-solving. You have a strong analytical mindset, coupled with a keen eye for detail, enabling you to deliver robust, high-quality solutions that meet stringent performance and reliability requirements. Your communication skills empower you to clearly articulate technical concepts and collaborate effectively with both local and global teams, as well as external customers. You are proactive, always seeking new ways to improve methodologies and processes, and you are committed to continuous learning and professional growth. Your dedication to excellence and innovation drives you to contribute meaningfully to the development of industry-leading products. If you are eager to work at the cutting edge of chip design and play a pivotal role in shaping the next generation of silicon technologies, Synopsys is the place for you.\n\nWhat You’ll Be Doing\nConceptualizing, designing, and productizing state-of-the-art RTL to GDS implementation for SLM monitors using ASIC design flows. \nDesigning on-chip Process, Voltage, Temperature, glitch, and Droop monitors for silicon biometrics and reliability. \nExecuting digital backend activities, including synthesis, pre-layout STA, SDC constraints development, floor planning, bump placement, power planning, MV design techniques, VCLP, UPF understanding, placement, CTS, and routing.  \nDriving post-layout STA, timing and functional ECO development, and timing signoff methodology for high-frequency IP design closure.  \nPerforming physical verification tasks such as DRC, LVS, PERC, ERC, Antenna, EMIR, and Power signoff. \nCollaborating with architects and circuit design engineering teams to create and refine new flows and methodologies.  \nEnsuring pre-layout and post-layout timing closure and timing model characterizations across various design corners, meeting reliability and aging requirements for automotive and consumer products.\n\nThe Impact You Will Have\nAccelerating the integration of next-generation intelligent in-chip sensors and analytics into Synopsys technology products.\nOptimizing performance, power, area, schedule, and yield at every stage of the semiconductor lifecycle.\nEnhancing product reliability and differentiation in the market, reducing risk for customers and partners.  \nDriving innovation in physical design, verification, STA, and signoff methodologies and tools.\nContributing to industry-leading SLM monitors and silicon biometrics solutions that set new standards.  \nCollaborating with cross-functional teams to ensure successful deployment and adoption of advanced technologies.\n\nWhat You’ll Need\nBS/B.Tech or MS/M.Tech in Electrical Engineering with 3+ years of relevant industry experience.\nStrong knowledge and hands-on experience in Physical Design, Physical Verification, pre- & post-layout STA, and EMIR/Power signoff, including SDC development and UPF/Multivoltage design.\nMandatory experience with DRC, LVS, DFM cleaning, and timing closure.  \nProficiency in digital design tools from any EDA vendor, preferably Synopsys tools (FC/VCLP/PT/PT-PX/ICV/Redhawk).\nSound understanding of Physical Design, Physical Verification, STA, and signoff concepts, with proven track record in generating ECO for DRV cleaning and timing closure.\nExperience with advanced nodes (14nm, 10nm, 7nm, 5nm, 3nm, 2nm) and successful tape-outs.\nGood understanding of OCV, POCV, derates, crosstalk, and design margins. \nExperience in scripting (TCL/PERL) for custom methodologies and flow enhancements.\n\nWho You Are\nProactive and detail-oriented with excellent problem-solving skills.\nAdept at working independently and providing innovative physical design and signoff solutions. \nExcellent communicator and team player, capable of collaborating effectively with diverse teams.\nInnovative thinker with a passion for technology and continuous improvement.\nCommitted to delivering high-quality results and achieving ambitious project goals.\n\nThe Team You’ll Be A Part Of\nYou’ll join a dynamic, collaborative team of engineering professionals focused on advancing the state-of-the-art in chip design and verification. The team works closely with architects, circuit designers, and cross-functional partners to deliver innovative solutions for semiconductor lifecycle monitoring, reliability, and performance. With a culture of continuous learning and knowledge sharing, you’ll be empowered to contribute ideas and play a key role in shaping the future of Synopsys technology.\n#TPG", "jd_status": "stored"}, {"title": "IP TEC Engineer", "company": "Nokia", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-10-14", "url": "https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/40466", "is_hardware": true, "platform": "oracle", "jd_text": "As an IP Technical Expert Center Engineer, you will troubleshoot complex IP network issues, diagnose hardware/software challenges, and provide solutions for customer problems. Collaborating with cross-functional teams, you'll lead deployments, drive root cause analysis, and contribute to product enhancements. Your role includes mentoring, ensuring high-quality standards, and supporting critical production networks while driving innovation and best practices.\n\nResponsibilities\nWork effectively in a mixed environment, using best practices and business knowledge to improve products or services.\nApply in-depth business knowledge of IP product services to understand integration and achieve objectives.\nUse advanced analytical, network, and node-level troubleshooting skills to solve complex customer and field-facing team issues related to specific IP products.\nShare initial ideas for the professional direction of your organizational unit.\nAct as a professional advisor and mentor for staff, work teams, and task forces.\nLead or act as SPOC for customer deployment projects involving specific IP products, new technology areas, or high business potential/impact.\nResolve customer trouble tickets, diagnose complex issues (e.g., hardware, software, or combined), and recommend or provide corrective actions.\nProvide technical requirement inputs based on customers' deployment experience.\n\nQualifications\nYou have:\nBachelor's degree in engineering with 5-10 years of relevant experience.\nProvides technical requirement inputs based on customers’ deployment experience.\nInputs to develop SW/HW build-controlled production releases.\nCreation and release of hardware/software documentation and customer notifications.\nIt would be nice if you also had:\nRetains technical and design knowledge for assigned products and technologies and provides training to the lower support teams.\nFamiliarity with the care process (especially emergency case handling), contributing when needed to the fastest problem restoration.\nExperience with access network nodes, involving the integration of theory and principles with organizational practices and precedents.\nAdvanced network and node-level troubleshooting skills for IP routers/networks and in-depth knowledge.\n\nAbout the company\nAdvancing connectivity to secure a brighter world.\n\nNokia is a global leader in connectivity for the AI era. With expertise across fixed, mobile and transport networks, powered by the innovation of Nokia Bell Labs, we’re advancing connectivity to secure a brighter world. \n\nLearn more about life at Nokia.\n\nOur recruitment process\n\nWe act inclusively and respect the uniqueness of people. Our employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.\n\nIf you’re interested in this role but don’t meet every listed requirement, we still encourage you to apply. Unique backgrounds, perspectives, and experiences enrich our teams, and you may be just the right candidate for this or another opportunity.\n\nThe length of the recruitment process may vary depending on the specific role's requirements. We strive to ensure a smooth and inclusive experience for all candidates. Discover more about the recruitment process at Nokia.", "jd_status": "stored"}, {"title": "Staff Digital Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-10-14", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506950", "is_hardware": true, "platform": "oracle", "jd_text": "Job Description details:\n\n \n\nonsemi (Nasdaq: ON) is driving technology breakthroughs that deliver on the promise of a sustainable future focusing on the automotive and industrial markets. The intelligent sensor group, ISG, focuses on image and time of flight sensors. Our sensors are improving people’s lives through improved safety and automation where our products are used in imaging for information applications like scanning, factory automation, smart office, intelligent appliances, and safety/autonomous systems for automotive. We are market leaders in sensors for automotive and machine vision.\n\n \n\nResponsibilities\n\nWe are looking for engineers to join our team working on some of our most innovative and successful products.\n\n \n\nWhat you would work on\n\nMicro architect, implement and verify the digital processing blocks which are part of a CMOS Image Sensor.\n\nInteract with multiple cross functional teams on requirements and deliverables.\n\n#LI-RT1\n\nResponsibilities\nWhat you need\nBE/ME in electronics or related technical field.\nAt least 6 years of relevant experience in semiconductor product development.\nExperience going through full ASIC development cycle including concept, specification, design, verification and documentation.\nExperience in working on data path elements, control logic, design for synthesis, multi clock domain designs, low power design techniques and behavioural modelling.\nKnowledge of System Verilog and scripting and familiarity with C modelling.\nShould have good analytical skills for debug work needed during verification.\nGood written and verbal communication skills.\n#LI-RT1\n\nQualifications\nExperience with the following is an advantage but not a requirement:\nKnowledge of image sensor design.\nUnderstanding of a typical mixed signal system requirement.\nWhy Join Us\nWe create a diverse set of world-class products in a friendly and team-oriented atmosphere. We provide an environment of continual learning and growth opportunities and support volunteer and charitable programs. We offer competitive benefit package and a great place to work. You will be able to build up a career in a successful international company, and you can participate in interesting international projects.\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Verification Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-10-14", "url": "https://careers.arm.com/job/bengaluru/verification-engineer/33099/101948055264", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview:\nArm’s hardware is at the heart of computing and connectivity revolution that continues to transform the way people live and businesses operate. Working as a team and engaging with the world’s most famous technology companies, we are driving innovation into all areas where compute is possible to help us build better solutions for the billions of people using our technology worldwide. As we continue to grow, we need the best engineers to join a team responsible for the development of sophisticated compute subsystems and solutions. You could be using your talents to develop the technologies that will enable the very latest compute solutions in today's enterprise and client markets.\nResponsibilities:\nSolution engineering team’s mission is to enable our partners by delivering secure, performant and reliable hardware and software that are easy to use. System Validation engineers in this group are responsible for driving validation specifications & methodology and deliver on the validation of subsystems for the next generation of compute solution. Working in a highly focused group within Arm's Solutions Engineering Systems Development team, where you will help validate our next generation compute solutions using innovative technologies, methodologies and tools. Key responsibilities will include design integration.\nRequired Skills and Experience:\n2 to 5 Years of experience\nBachelors (BS) or Masters (MS/MSc) in Electronics.\nKnowledge of Verilog and system Verilog.\nUnderstanding of the fundamentals of computer architecture and systems\nKnowledge of shell programming/scripting (e.g. Tcl, Perl, Python etc.)\n“Nice To Have” skills and experience:\nDemonstrated understanding of CPU, GPU, Peripheral IP (PCI/CXL/USB/UFS/ETH), Memory subsystem in SoC environment.\nHands on Experience in design and integration of multiple sub systems for ASICs/ SoCs in system environment (Emulation, FPGA).\nIn Return:\nWith offices around the world, Arm is a diverse organization of dedicated, innovative and very hardworking engineers. By enabling a vibrant, inclusive, meritocratic, and open workplace, where all our people can grow and succeed, we encourage our people to share their outstanding contributions to Arm's success in the global marketplace.\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Verification Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-10-14", "url": "https://careers.arm.com/job/bengaluru/senior-verification-engineer/33099/101948055232", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview:\nArm’s hardware is at the heart of computing and connectivity revolution that continues to transform the way people live and businesses operate. Working as a team and engaging with the world’s most famous technology companies, we are driving innovation into all areas where compute is possible to help us build better solutions for the billions of people using our technology worldwide. As we continue to grow, we need the best engineers to join a team responsible for the development of sophisticated compute subsystems and solutions. You could be using your talents to develop the technologies that will enable the very latest compute solutions in today's enterprise and client markets.\nResponsibilities:\nSolution engineering team’s mission is to enable our partners by delivering secure, performant and reliable hardware and software that are easy to use. System Verification engineers in this group are responsible for driving verification specifications & methodology and deliver on the verification of SoC for the next generation of compute solution. Working in a highly focused group within Arm's Solutions Engineering Systems Development team, where the candidate will help verify our next generation compute solutions using innovative technologies, methodologies and tools. Key responsibilities will include owning the verification plan, test plan, debug methodology, developing and executing the test content, finding bugs, and running various verification checks for Arm IP and high-speed interfaces like PCIe, DDR, USB, etc.\nExpertise in Arm Architecture, Arm core and system IP.\nExpected to own and lead to enhance the verification methodologies used by the team.\nWill guide other members of the team as needed to enable the successful completion of project activities.\nRequired Skills and Experience:\n4 to 8 Years of experience\nBachelors (BS) or Masters (MS/MSc) in Electronics, Electrical or Computer Engineering\nKnowledge of Verification test content using C, C++ etc.\nExpertise in Arm Architecture, Arm core and Arm system IP (SMMU/GIC/DMS etc.).\nExposure to producing verification specifications and documentation describing sophisticated designs\nAbility to work under time-scale pressure and meet ambitious targets without compromising on quality\nUnderstanding of the fundamentals of computer architecture and systems\nPractical experience of working on Processor based system designs\nKnowledge of shell programming/scripting (e.g. Tcl Perl, Python etc.)\nExpected to own verification and compliance testing for select components of a modern system.\n“Nice To Have” skills and experience:\nDemonstrated understanding of CPU, GPU, Peripheral IP (PCI/CXL/USB/UFS/ETH) , Memory subsystem in SoC environment and proven expertise in owning verification requirements and plan.\nKnowledge of microarchitecture and experience with RTL debugging tools and methodologies is a plus.\nHands on Experience in verification of multiple sub systems for ASICs/ SoCs in system environment (Emulation, FPGA, virtual platform), owning all phases of verification (Test development, Execution and Debug) for owned sub systems.\nUnderstanding of SoC security aspects\nIn Return:\nWith offices around the world, Arm is a diverse organization of dedicated, innovative and very hardworking engineers. By enabling a vibrant, inclusive, meritocratic, and open workplace, where all our people can grow and succeed, we encourage our people to share their outstanding contributions to Arm's success in the global marketplace.\n\n#LI-KR2\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Hardware Development Engineer", "company": "Nokia", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-10-14", "url": "https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/39888", "is_hardware": true, "platform": "oracle", "jd_text": "As an Senior Hardware Development Engineer, you will play a crucial role in our team, focusing on structural and thermo-mechanical simulations for optical transceiver products. Your expertise will be instrumental in identifying structural risks, optimizing designs, and ensuring product reliability throughout its lifecycle. This role offers an exciting opportunity to work with cutting-edge technology and contribute to the development of innovative optical solutions.\n\nNILightpath\n\nResponsibilities\nOwn structural and thermo-mechanical simulations for high-speed optical transceiver products, including OSFP, QSFP-DD, and future form factors.\n Ensure product robustness by identifying structural risks early in the design cycle and proposing mitigation plans.\n Work closely with cross-functional teams, including mechanical, thermal, optics, electronics, and reliability experts, to define critical parameters and drive design optimization.\n Develop detailed finite element models of module housings, heat sinks, optical assemblies, PCBAs, and other critical components.\n Participate in design and product gate reviews, providing structural and reliability sign-offs to ensure product quality and performance.\n Correlate simulation results with physical testing, including mechanical shock, drop, vibration, and thermal cycling, to validate product reliability.\n Support qualification and regulatory testing activities, performing root-cause analysis for field and validation failures.\n Develop simulation methodologies, best practices, and design guidelines to enhance efficiency and consistency in the simulation process.\n Evaluate new materials, manufacturing methods, and packaging technologies to stay at the forefront of industry advancements.\n Foster a culture of innovation by developing reusable simulation templates, automation workflows, and establishing FEA processes.\n\nQualifications\nB.E./B.Tech./M.E./M.Tech. in Mechanical Engineering or equivalent, with 2+ years of experience in FEA and structural reliability engineering.\nStrong expertise in FEA software, including Abaqus, ANSYS Workbench, ANSYS Mechanical, LS-Dyna, and HyperMesh.\nProficiency in linear and non-linear structural analysis, contact non-linearity, material non-linearity, geometric non-linearity, and large deformation analysis.\nExperience with reliability simulations, including drop simulations, mechanical shock analysis, modal analysis, and fatigue assessments.\nKnowledge of optical transceiver architecture, OSFP and QSFP-DD mechanical standards, and high-density packaging constraints.\nWorking knowledge of Creo or equivalent CAD tools, with experience in GD&T interpretation, tolerance analysis, and component design.\nUnderstanding of manufacturing and assembly processes, and experience with optical modules, optics packaging, or compact electronics products is preferred.\nExcellent communication and technical presentation skills, with the ability to collaborate effectively in a cross-functional environment.\nProven track record of delivering products from concept to production release, demonstrating strong analytical and problem-solving abilities.\nPassion for continuous learning and staying updated with industry trends and advancements in FEA and structural reliability engineering.\n\nAbout the company\nAdvancing connectivity to secure a brighter world.\n\nNokia is a global leader in connectivity for the AI era. With expertise across fixed, mobile and transport networks, powered by the innovation of Nokia Bell Labs, we’re advancing connectivity to secure a brighter world. \n\nLearn more about life at Nokia.\n\nOur recruitment process\n\nWe act inclusively and respect the uniqueness of people. Our employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.\n\nIf you’re interested in this role but don’t meet every listed requirement, we still encourage you to apply. Unique backgrounds, perspectives, and experiences enrich our teams, and you may be just the right candidate for this or another opportunity.\n\nThe length of the recruitment process may vary depending on the specific role's requirements. We strive to ensure a smooth and inclusive experience for all candidates. Discover more about the recruitment process at Nokia.", "jd_status": "stored"}, {"title": "GPU Logic Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-14", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/GPU-Logic-Design-Engineer_JR0287990", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nAs a GPU Logic Design Engineer, you will play a pivotal role in developing and refining the graphics IPs that drive Intel's cutting-edge GPUs. You will be responsible for designing, coding, and simulating register transfer level (RTL) logic for critical GPU IP blocks, ensuring they meet stringent power, performance, area, and timing goals. Your contributions will directly impact the quality and functionality of Intel's GPUs, enabling unparalleled visual experiences for users worldwide.\n\nBusiness Group\nThe Data Center Group (DCG) is at the heart of Intel's mission to power the future of computing. Focused on advancing data-centric solutions, DCG develops innovative hardware and software technologies that accelerate workloads for AI, cloud, and enterprise systems. Within this group, the AI SOC SCAN ATPG organization is dedicated to ensuring the delivery of high-quality, high-performance GPU designs that support Intel's leadership in graphics and visual computing.\n\nKey Responsibilities\n- Develop logic design and write RTL code for GPU IP blocks, focusing on graphics, compute, display, and media.\n- Collaborate in defining the architecture and microarchitecture features of GPU blocks.\n- Optimize logic designs to meet power, performance, area, and timing goals for physical implementation.\n- Review verification plans and drive unit-level verification to ensure correctness of design features.\n- Resolve RTL test failures and implement corrective measures to guarantee feature integrity.\n- Support SoC customers in integrating and verifying GPU blocks for high-quality SoC designs.\n\nQualifications:\nMinimum Qualifications\n- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field, with 3+ years of industry experience; OR Master's degree in the same fields, with 2+ years of industry experience; OR PhD with no industry experience.\n- Hands-on experience with at least one key DFT feature, such as TAP/JTAG, Scan/ATPG, or Array DFT (MBIST/PBIST).\n- Proficiency in using EDA tools such as ATPG tools, Mentor Tessent shell, and VCS simulation/debug tools.\n- Background in silicon enabling, debug, or test pattern development.\n\nPreferred Qualifications\n- Proficiency in programming or scripting languages for design automation.\n- Familiarity with structural design flows, including timing analysis, routing, placement, or clocking.\n- Knowledge of high-volume manufacturing requirements and test flows.\n- Understanding of 3D, media, and display graphics pipelines.\n- SoC architecture expertise.\n\nJoin us to shape the future of graphics and visual computing. Bring your expertise to Intel's GPU Hardware IP team, where innovation meets impact.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Sr Staff Engineer- Hardware Development Motor Control Solutions", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-13T12:44:24.637000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000155245952-sr-staff-engineer-hardware-development-motor-control-solutions", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Role Overview :\nThis role is responsible for technical leadership and execution of hardware development for the RH850 Motor Control and Automotive Application Platform, with ownership of solution development spanning hardware and embedded firmware integration. \nThe Sr. Staff Engineer serves as a motor control and power conversion domain expert, driving hardware and solution architecture, design quality, and technical execution in collaboration with cross-functional teams. Success in this role requires strong technical expertise, a hands-on engineering mindset, and a commitment to delivering robust motor control solutions from concept through validation. \nKey Responsibilities :\nLead hardware architecture, design, and implementation for RH850 motor control and automotive application platforms, including development and validation of complete motor control solutions. \n\nDrive hardware technical decisions, ensuring robustness, scalability, cost effectiveness, and alignment with platform requirements. \n\nOwn hardware execution from concept, design, and validation through qualification and production readiness. \n\nCollaborate closely with systems, firmware/software, validation, and product engineering teams to ensure seamless hardware‑software integration and successful delivery of motor control solutions. \n\nSupport regulatory compliance, qualification, and Global Market Access (GMA) readiness for hardware deliverables. \n\nIdentify and mitigate hardware‑related technical risks, ensuring predictable execution and high quality. \n\nContribute to reference designs, development platforms, solution collaterals and documentation to enable broad customer adoption. \n\nAct as a technical mentor, influencing best practices and raising the bar for hardware design excellence. \n\nB. Tech/M. Tech in Electrical Engineering, Electronics, Computer Engineering, or related field with 12+ years of experience. \n\nHands‑on experience with Signal Integrity (SI) and Power Integrity (PI) analysis for high‑speed digital, mixed‑signal, and power‑dense designs. Applying SI/PI best practices in schematic design, PCB layout, stack‑up definition, decoupling strategies, and grounding. \n\nDeep expertise in embedded hardware design, including MCU‑based systems, motor control circuits, and power electronics, embedded firmware development/debugging for system integration, validation, and optimization \n\nProven experience delivering embedded hardware designs from concept through production. \n\nPreferred Qualifications :\nExperience supporting embedded development platforms or reference designs with broad customer adoption. \n\nExposure to regulatory compliance and Global Market Access (GMA) requirements for global automotive markets. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior/Lead Robotics Validation Engineer ", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-13T10:00:00+00:00", "url": "https://global-external-amd.icims.com/jobs/93456/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. Robotics Lead Validation Engineer About the Role Join AMD’s PAVS team as a Robotics Developer experience Usecases Validation Engineer where you will Validate and Execute diverse Robotics platforms, variants and customer usecases for advanced robotics systems across software, hardware, and integrated platforms. Your work will ensure safety, reliability, and performance through rigorous testing in simulation, Gazebo, Isaac sim, SIL/HIL environments, and real-world deployments. Key Responsibilities Validation Strategy & Usecases : Define Usecases and execute validation plans for robotics software stacks (perception, planning, control) and hardware subsystems. Automation & Frameworks: Develop automated test suites for ROS2 nodes, navigation stack (Nav2), and fleet APIs using Python/C++, pytest, gtest/gmock. Simulation & Scenario Testing: Build simulation environments (Gazebo/Ignition, Isaac Sim) for warehouse layouts; author scenarios for obstacle avoidance, dynamic traffic, and multi-robot coordination. SIL/HIL Validation: Set up Software-in-the-Loop and Hardware-in-the-Loop rigs for AMR controllers, LiDAR emulators, and safety sensors; automate provisioning and logging. Sensor QA: Validate LiDAR, depth cameras, IMU, wheel encoders, and odometry accuracy under varying conditions. Navigation & Fleet QA: Test SLAM, localization robustness, path planning, and fleet orchestration (traffic management, task allocation, VDA5050 compliance). Safety & Compliance: Execute safety protocols for AMRs (emergency stop, zone monitoring, speed limits) aligned with ISO 3691-4, ISO 13849, ANSI/RIA R15.06. Performance & Reliability: Measure latency, throughput, and stability under high-load scenarios; validate battery management and docking behaviors. CI/CD Integration: Embed automated tests into pipelines for continuous validation; monitor KPIs like defect escape rate and scenario coverage. Leadership: Act as a strong individual contributor and mentor for robotics validation teams; collaborate with cross-functional stakeholders to ensure customer experience is prioritized. Required Qualifications 6-12 years in QA/Validation, with 7+ years in robotics or AMR systems. Strong Python for automation and C++ for ROS2 integration. Hands-on experience with ROS2, Nav2 stack, colcon, and simulation tools (Gazebo/Ignition, Isaac Sim). Expertise in LiDAR, depth cameras, IMU, odometry, and sensor calibration. Familiarity with fleet management systems, traffic control, and VDA5050 protocol. CI/CD experience with GitHub Actions/GitLab CI/Jenkins; Docker-based test environments. Knowledge of functional safety standards for mobile robots (ISO 3691-4, ISO 13849). Preferred Skills Multi-robot coordination, dynamic obstacle handling, and SLAM algorithms. Robotics AMR safety PLCs, zone scanners, and emergency stop circuits. Warehouse automation workflows, WMS integration, and OPC-UA. Performance benchmarking, reliability testing, and telemetry dashboards. Success Metrics Automated coverage of navigation and fleet scenarios. Reduction in field defect escape rate. Stability and reliability under multi-robot deployments. Compliance with safety standards and successful audits. 🎓 Academic Credentials: Bachelor’s or Master’s degree in Robotics, Electronics, Mechatronics, Computer Science, or a related field. #LI-NR1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "NOC DV Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-13T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721283310", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nLooking for an experience Verification Architect/ Engineer, who will be responsible for verification of next generation Infrastructure IPs (DDRSS, Memory Controllers etc.) which goes into System-on-chip (SoC) for smartphones, tablets and other product categories. In this position you will be expected to plan and implement IP/Cluster/Formal verification flows for the Infra IPs. Also expected to coordinate with different Design and SOC teams throughout the IP development cycle.  \n\nJob responsibilities include \nOwnership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage) \nDevelop test plan and test cases to cover design feature set, follow up with stakeholders on code coverage, functional coverage closure at different levels of test bench \nWork closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure \nDebug of regression signatures and identifying bug fixes \nResponsible for Quality sign off and required documentation \nDeveloping/Deploying scripts/tools for validation (Certitude, VC Formal, VPlan) \nDebug and root cause post silicon issues in collaboration with Design, SW and test teams \nWork with SoC level performance modeling team on latency, bandwidth analysis next-generation experiences and drives digital transformation to help create a smarter, connected future for all.\n\nRequired skillset include \nStrong debugging, Analytical and problem-solving skills \nExpertise on UVM based verification  \nKnowledgeable about ARM bus protocols, Virtual Memory concepts, SoC system architecture \nExperience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved \nCommunication and collaboration skills to work with a large world-wide design organization \n\nDesired skillset includes \nExperience in designs optimized for low power - Dynamic clock gating, Logic/ Memory power collapse  \nExperience in verifying designs meeting Automotive Safety Integrity Levels (ASIL) \nProficiency in Scripting languages (Python or Perl) for Automation initiatives, C/C++/SystemC for performance models \nPost-si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage \nQualification : \nBachelor/Master’s Degree in Electronics & Communication / Micro Electronics \n8 Years of Experience in IP verification or related\nExperience with UVM and ARM Bus protocols. \n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU Design Sr Staff Verification Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-13T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721481033", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nJob Description\nQualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement.\n\nRoles and Responsibilities\n\no   Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling.\no   Work closely with design/verification teams within CPU to develop comprehensive test plan.\no   Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus.\no   Verify power intent through use of methodologies like UPF.\no   Work closely with system architects, software teams and Soc team to validate system use cases.\no   Work closely with emulation team to enable verification on emulators and FPGA platforms.\n\nAdditional Job Description\nBE/BTech degree in CS/EE with 12+ years’ experience.\no   Experience in power management verification.\no   Implementation of assembly and C language embedded firmware.\no   Experience in C/C++, scripting languages, Verilog/system Verilog.\no   Strong understanding of power management features in CPUs and CPU based Socs.\no   Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.\n\nPreferred Requirements:\n\no   Good Understanding of CPU architectures and CPU micro-architectures.\no   In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture\no   Experience with advanced verification techniques such as formal and assertions is a plus\no   Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SOC Power Design -Staff/Sr Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-13T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720291936", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    8+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates complex features and functionality into hardware designs in line with proposals or roadmaps for complex products.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the novel manufacturing of solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for complex Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making is significant in nature and affects work beyond immediate work group.\n•    Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. \n•    Has a moderate amount of influence over key organizational decisions.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RTL Design(Camera) - Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-13T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721072972", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Camera Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Camera Engineer you will work on ideas that touch our daily life – creating everlasting connected memories and assist in building innovative devices through human and computer vision technologies in the Mobile, Automotive, XR, IoT & Compute space. You will have limitless opportunities to learn, grow and lead the world of Imaging.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.\n                                                                    OR\nMaster's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 1+ year of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.\n                                                                    OR\nPhD in Computer Engineering, Computer Science, Electrical Engineering, or related field.\n\nPreferred Qualifications:\n•    Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.\n•    2+ years of experience in programming (e.g., C, C++, Python), computer architecture, or embedded systems.\n•    2+ years of experience in Image Signal Processing design, development, implementation, and verification.\n•    2+ years of experience in camera hardware or systems design and optimization.\n\nPrincipal Duties and Responsibilities:\n•    Leverages advanced Camera Engineering knowledge to research, design, develop, verify, debug, implement, and/or validate complex camera systems, HW or FW tasks (including Camera Image Signal Processor, 3A, Image Quality, Features, and Tuning Tools), algorithms, features, logic design, modeling, design verification, and power optimization.\n•    Performs architecture, IQ modules, algorithm, and feature decomposition to drive complex requirements and specifications for hardware development.\n•    Ensures advanced image quality, system performance, and ISP area and power metrics are met.\nAddresses customer/product requirements in functionality and results. \n•    Collaborates with cross-functional teams to design, develop, and optimize camera systems, hardware, and/or software.\n•    Writes detailed technical documentation and feature descriptions for complex Camera projects to guide users and/or customers to implement output.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Has a moderate amount of influence over key organizational decisions.\n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NOC Design Verification Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-13T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721350824", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nRole Summary\nSeeking a highly skilled and self-driven Design Verification Engineer to lead verification of complex AI, Networking, Datacenter, HPC, and Interconnect IPs/Sub-systems. The candidate should demonstrate strong ownership, technical depth, and the ability to independently drive verification from architecture understanding through signoff-quality closure.\nKey Responsibilities & Skills\nExpert in SystemVerilog (SV) and UVM, with hands-on experience in building reusable verification environments, UVCs/agents, sequences, scoreboards, checkers, assertions, and coverage infrastructure.\nStrong expertise in verification planning, constrained-random verification, SVA, functional coverage closure, regression management, and signoff methodologies.\nProven ability to independently own and execute IP/Sub-System DV from specification review to verification closure.\nStrong debugging skills across RTL, protocol, architecture, performance, and testbench issues, with demonstrated root-cause analysis capability.\nExperience in verifying NoC, coherent/non-coherent interconnects, memory/cache subsystems, AI accelerators, or complex data movement fabrics.\nDeep protocol verification expertise in one or more of: PCIe (Gen4/5/6)\nUSB (USB3.x/USB4)\nEthernet (10G/25G/100G/400G+)\nCXL\nOther high-speed serial/networking protocols\n\nExperience with AI Scale-Up / Scale-Out Interconnects such as UAL, UMAC, eSUN, or equivalent accelerator cluster fabrics.\nStrong understanding of AMBA protocols (AXI, AHB, ACE, CHI) and coherency architectures.\nKnowledge of performance verification, QoS validation, congestion analysis, scalability testing, and system-level qualification.\nProficiency in Python, Shell, Perl, or Tcl for regression automation, infrastructure development, and productivity enhancement.\nFamiliarity with industry-standard simulators, debug tools, coverage tools, CI/CD workflows, emulation, and verification automation frameworks.\nStrong collaboration, communication, technical leadership, and execution skills with the ability to thrive in a fast-paced environment.\nPreferred Experience\nVerification experience in SoC, AI/ML Accelerators, Networking, Datacenter, Multi-Die, or HPC platforms.\nExposure to SystemC/TLM modeling, performance modeling, emulation/prototyping, and post-silicon correlation.\nTrack record of delivering first-pass verification closure for complex IPs and subsystems.\nQualifications\nB.Tech/M.Tech in Electronics, Electrical Engineering, Computer Science, VLSI, or related disciplines from reputed Tier-1 institutions (IITs, NITs, IIITs, BITS, or equivalent).\nRelevant industry experience aligned with the position level, demonstrating strong expertise in Design Verification, SV/UVM methodologies, protocol verification, and architecture-driven validation.\nProven history of technical ownership and successful delivery of complex IP, Sub-System, or SoC verification programs.\nIdeal Candidate\nA hands-on verification expert with deep protocol knowledge, strong debugging capability, and the ability to independently architect, execute, and close verification of next-generation AI and high-performance silicon designs.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Engineer II - CAD", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-10-13", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Engineer-II---CAD_R4354-26-8", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nThe CAD group at Microchip offers global support for technologies and tools used in product development providing innovative solutions for the design community.\nA successful candidate in this role will participate in various aspects of EDA support and developing next-generation ASIC design flow and methodology.\nHe / She will also work closely with various business units across the globe to understand their needs and foster innovative ideas to solve complex problems.\n \n \nKey Requirement :\n \nGood Knowledge of design flows from RTL design through synthesis, formal verification, and timing closure for RTL2GDS delivery.\nundefined\nDesign, benchmark, and deploy automated CAD tool flows focusing on logic synthesis, hierarchical optimization, physical synthesis, and chip sign-off timing.\nAutomation & Tools Customization: Write and optimize highly robust, scalable scripts using Tcl and Python to reduce Flow Turnaround Time (TAT) and build automated tracking tools for timing data.\nSynthesis & Equivalence Verification: Build and optimize front-end flows utilizing advanced tools for logical/physical synthesis and Formal Verification/Logic Equivalence Checking (LEC).\nHands-on experience with one or more of the following industry-standard toolsets: Synopsys Fusion Compiler, DC, PrimeTime Cadence Genus, Tempus or Innovus\nExposure to leveraging AI driven EDA capabilities (e.g., Synopsys FC.ai, Cadence Cerebrus) to automate PPA exploration and timing closure optimization.\nStandardize and automate the validation of Synopsys Design Constraints (SDC) across all functional and test modes. \nPartner directly with major EDA vendors to test next-generation features, troubleshoot internal tool failures, and adapt flows for deep sub-micron advanced process nodes.\nExcellent verbal and written communication skills.\n\nRequirements/Qualifications:\n\nB.E./B.TECH/M.E./M TECH (Electronics/ECE/CS/VLSI).\n2 to 8 Years of relevant experience is required\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Analog Circuit Design Engineering Manager", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-13", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Analog-Circuit-Design-Engineering-Manager_JR0287922", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nAs an Analog Circuit Design Engineering Manager, you will lead a team of talented engineers responsible for designing innovative analog and mixed-signal circuits that power Intel's cutting-edge technologies. You'll oversee the development process, mentor team members, and drive project execution to ensure high-quality deliverables that meet critical design requirements. Your leadership will directly impact the success of Intel's products and help shape industry standards for analog circuit design.\n\nBusiness group\nThis role is part of Intel Corporation's Power Delivery HIP organization, which focuses on providing advanced power delivery solutions to enable efficient and high-performing technologies. The group plays a pivotal role in supporting Intel's broader mission to create world-changing technology that enriches the lives of every person on Earth. By joining this team, you will contribute to groundbreaking innovations that drive the future of computing.\n\nKey Responsibilities\n- Lead, mentor, and develop a team of analog circuit design and layout engineers in executing complex technical projects.\n- Plan and manage resources, schedules, and priorities to meet design objectives and project deadlines.\n- Collaborate with cross-functional teams to align on design specifications, requirements, and deliverables.\n- Oversee the development, validation, and optimization of analog and mixed-signal circuits for power delivery applications.\n- Ensure design quality and reliability while meeting performance and cost targets.\n- Drive technical innovation and process improvements to enhance efficiency and effectiveness within the team.\n- Communicate progress, challenges, and technical insights to stakeholders and senior management.\n\nQualifications:\nMinimum Qualifications\n- Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field with 9+ years of experience in analog circuit design and development, OR Master's degree in a relevant field with 6+ years of experience, OR PhD in a relevant field with 4+ years of experience.\n- Proven expertise in analog and mixed-signal circuit design, including design, simulation, and validation.\n- Proficiency with industry-standard design tools and methodologies.\n- Demonstrated experience managing and mentoring engineering teams.\n- Solid understanding of power delivery solutions and their impact on system performance.\n\nPreferred Qualifications\n- Strong communication, collaboration, and leadership skills to inspire and guide technical teams.\n- Experience driving innovation, process optimization, or strategic initiatives.\n- Ability to build strong cross-functional relationships and effectively communicate technical ideas to diverse audiences.\n\nIf you're ready to take on a leadership role that combines technical excellence with strategic impact, join Intel's Power Delivery HIP organization to shape the future of analog circuit design and contribute to transformative technology solutions.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Principal Engineer, EDA Software Development", "company": "Lattice", "location": "Hyderabad, India", "date_posted": "2026-10-13", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Hyderabad-India/EDA-SW-Dev-Eng--Prin_R-103513", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nThere is energy here…energy you can feel crackling at any of our international locations.  It’s an energy generated by enthusiasm for our work, for our teams, for our results and for our customers.  Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing and support teams, who are developing programmable logic solutions that are changing the industry.  Our focus is on R&D, product innovation and customer service, and to that focus we bring total commitment and a keenly sharp competitive personality. \n\nEnergy feeds on energy.  If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.  \n \nLattice Semiconductor is seeking a Principal EDA engineer to join the EDA tools development team in Pune.  This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn and grow.\nAccountabilities: \nResponsible for development and architecture of Lattice EDA toolchain covering synthesis, place & route and timing analysis.\nCollaborate with Place & Route, Timing, Database & GUI teams to deliver a high quality and standards compliant EDA stack.\nStarting from Marketing requirements, help frame the architectural & engineering specification for new features and ensure that the actual implementation satisfies marketing requirements.\nMaintain high standards of architecture-quality, performance, and reliability.\nOwn Spec and Plan process for EDA suite and contribute to the same for P&R & Timing tool components.\nImprove development methodologies and processes.\nQualifications:\nBS/MS/PhD Electrical Engineering or Computer Science\n15+ years of experience in software development for FPGA or ASIC EDA software.\nDeep familiarity with commercial FPGA tools and operation flow.\nProficiency in FPGA design tools like synthesis, place & route and timing analysis tools.\nStrong background in object-oriented programming, data structures and algorithms\nKnowledge of shell, TCL or Python scripting.\nDetail oriented and must possess independent problem-solving skills.\nMust be able to drive projects and lead a discussion.\nStrong written and verbal communication skills, and collaboration skill with the ability to work with multiple groups.\n \n \nLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.\n \nLattice\nFeel the energy.\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Electrical Engineer (FPGA)", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2026-10-13", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/Electrical-Engineer--FPGA-_R2630877-1", "is_hardware": true, "platform": "workday", "jd_text": "Who We Are\n\nApplied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI and accelerating the commercialization of next-generation semiconductor chips. Join us and push the boundaries of materials science and engineering in a company at the foundation of the electronics industry. The work we do together advances the world’s technology.\n\nWhat We Offer\n\nLocation:\nBangalore,IND\nYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. \n\nAt Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. \n \n \nAs an Electrical Engineer, you are responsible for designing, modifying, and troubleshooting electrical or electronic engineering assemblies, layouts, schematics, and drawings to advance the equipment that supports our technology. Using your technical experience and critical thinking skills, you will perform engineering analysis, generate test reports, develop innovative solutions, and create documentation for product releases. You will also coordinate the procurement and assembly of components, identify sources of critical parts, and resolve technical issues to ensure peak performance. \n \nRole Responsibilities: \nExpert level technical support in the resolution of FPGA design and application issues\nDesign or modify electrical or electronic engineering assemblies, layouts, schematics, drawings or specifications of moderate scope under general supervision\nCreate design and specification documents, test plans and progress reports. \nConduct obsolescence risk assessment for prompt risk mitigation strategy and implementation to ensure product manufacturability and sustenance.\nCoordinate the procurement and assembly of electrical/electronic components/equipment and identify sources of critical parts and subsystems to resolve technical issues.\nParticipate in resolving customer complaints & escalations through root-cause analysis and corrective-preventive actions.\nImplement concepts for product issues and electrical solutions of moderate difficulty \nAssist in the development of electrical product specifications \nClearly communicate complex information in straightforward situations\n\nMinimum Qualifications:\nBachelor's Degree in Electrical Engineering / Electronics & Communication\n1 to 4 years of related experience\n\nPreferred Qualifications:\nA solid understanding of the industry’s key business drivers  \nGood communication/interpersonal skills to explain complex information to others   \n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nAssignee / Regular\nTravel:\n\nRelocation Eligible:\nNo\n\nApplied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "Senior Engineer, Embedded Software", "company": "Analog Devices", "location": "India, Bangalore, Nova", "date_posted": "2026-10-13", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-Nova/Senior-Engineer--Embedded-Software_R266695", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nSenior Embedded Software Engineer – Battery Management Systems\nBuild production software that advances intelligent battery systems across markets\nRole Overview\nAnalog Devices Inc. (ADI) is seeking a Senior Embedded Software Engineer with four to six years of experience to build and productize software across the complete Battery Management Systems (BMS) stack. You will work from MCU platforms and BMS IC device drivers through battery-algorithm implementation and integration, creating scalable solutions for automotive, energy storage, industrial, robotics, and emerging markets.\nThis role offers broad technical ownership and the opportunity to solve demanding hardware–software and algorithm-integration problems. You will combine strong Embedded C and Python skills with mathematics, electrical engineering, and systems thinking to deliver efficient, production-quality software for resource-constrained real-time platforms.\nKey Responsibilities\nBuild the complete BMS software stack, including MCU platform software, hardware abstraction, diagnostics, BMS IC and peripheral device drivers, communication, monitoring, protection, and balancing.\nDeploy battery algorithms on embedded targets, translating models and reference code for SOC, SOH, power capability, diagnostics, anomaly detection, and impedance-based functions into deterministic Embedded C.\nOptimize for real-world constraints, including execution time, memory, power, numerical accuracy, scaling, and fixed- or floating-point behavior.\nScale software across products and markets through reusable architectures and configurable solutions for multiple MCUs, BMS ICs, toolchains, battery topologies, and operating environments.\nCreate robust Python engineering tools for automated testing, data processing, visualization, calibration, profiling, and algorithm validation.\nOwn delivery from concept to release, driving requirements, design, implementation, verification, troubleshooting, reviews, and maintenance in collaboration with multidisciplinary teams.\nRequired Qualifications\nB.E. / B.Tech or M.E. / M.Tech in Electrical Engineering, Electronics, Embedded Systems, Computer Science, Instrumentation, or a related discipline.\nFour to six years of embedded software experience in BMS, battery monitoring, power electronics, automotive, energy, industrial, or another safety- and reliability-focused domain.\nProven delivery of embedded features from requirements and design through integration, verification, and release.\nTechnical Skills\nEmbedded C and Python: Strong programming skills and the ability to independently develop production embedded software and maintainable tools for automation, testing, data analysis, visualization, and algorithm validation.\nEmbedded systems: Strong knowledge of MCU architecture, interrupts, timers, memory, DMA, peripherals, boot flow, RTOS or bare-metal systems, communication protocols, build systems, debugging, version control, and continuous integration.\nBMS and electrical engineering: Understanding of battery cells and packs, sensing, ADCs, isolation, contactors, protection, balancing, diagnostics, filtering, signal integrity, and basic controls; ability to interpret schematics, data sheets, and timing diagrams.\nMathematics and algorithms: Strong quantitative foundation in calculus, probability, statistics, numerical methods, linear systems, and signal processing, with practical understanding of precision, scaling, overflow, error, and computational complexity.\nEngineering quality: Strong debugging and root-cause analysis skills, supported by disciplined requirements, design, review, configuration management, testing, traceability, and defect management practices.\nBehavioral Expectations – Senior Engineer\nTake ownership, exercise sound judgment, and deliver high-quality results.\nUse structured, data-driven thinking to solve complex and ambiguous problems.\nCollaborate effectively and communicate decisions, risks, and results clearly.\nAdapt, share knowledge, support colleagues, and continuously improve.\nPreferred Qualifications\nExperience with SOC, SOH, state-of-power, impedance, estimation, prediction, or diagnostic algorithms.\nExposure to MATLAB/Simulink, model-based development, code generation, calibration, or algorithm prototyping.\nKnowledge of AUTOSAR, functional safety, cybersecurity, Automotive SPICE, MISRA C, static analysis, performance optimization, hardware-in-the-loop testing, or data-driven battery analytics.\nWhy Join ADI?\nOwn meaningful technical challenges across the full BMS software stack and product lifecycle.\nBuild solutions with market impact across automotive, energy storage, industrial, robotics, and emerging applications.\nGrow with a strong engineering community that values technical depth, innovation, collaboration, inclusion, and continuous learning.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Senior Verification Engineer, Switch SoC", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-13", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer--Switch-SoC_JR2027283", "is_hardware": true, "platform": "workday", "jd_text": "We are currently seeking Verification Engineer with strong verification fundamentals to work in Switch Silicon group. You'll join a group of hardworking engineers to craft and implement the next generation innovative Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing best high-speed communication devices, delivering the highest throughput and lowest latency! The Networking Chip Design team in India is a new team which is growing at a fast pace.\n\nWhat you'll be doing:\nVerify Switch design's architecture and micro-architecture using advanced methodologies.\n\nBuild reference models, verify and simulate chip blocks/entities according to specifications.\n\nWork closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW.\n\nYou are encouraged to understand the design and implementation, define the verification scope, develop the verification infrastructure, test plans and tests and verify the correctness of the design at SOC level.\n\nUse sophisticated verification methodologies like e-specman, SV-UVM etc.\n\nWhat we need to see:\nBS (or equivalent experience) / MS with 4+ years of experience in design verification.\n\nExposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.).\n\nPerl/python scripting language experience desirable.\n\nWays to stand out from the crowd:\nPrior experience of Ethernet or InfiniBand Switches, and/or smartNICs or DPUs, and/or high-speed interconnects.\n\nStrong debugging, problem-solving and analytical skills.\n\nScripting knowledge (Python/Perl/shell).\n\nGood social skills and ability & desire to work as an excellent teammate.\n\nWidely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com\n\nNVIDIA is committed to encouraging a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "ASIC Verification Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-13", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/ASIC-Verification-Engineer_JR2024390-1", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.\n\nNVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! In this position, you will be expected to plan and implement IP/Cluster/SOC functional verification of designs that constitute our Graphics Processors and Tegra SOCs. You would work on creating regression plans for code as well as functional coverage closure. You would perform pre-silicon validation activities such as XPROP simulations and GLS.\n\nWhat you’ll be doing:\nOwn ASIC verification of IP/Cluster for complicated designs in RTL.\n\nWork with HW architects and designers to make the right implementation choices.\n\nInteract with the Performance verification teams to augment verification through dynamic simulations and/or Formal verification techniques.\n\nYou will work with the specifications and ensure functional and code coverage of all the RTL which you will verify.\n\nPartner with and enable FPGA and S/W teams to ensure that S/W is tested.\n\nBe involved with post-silicon verification and debug.\n\nWhat we need to see:\nBS / MS or equivalent experience.\n\n1+ years of design experience.\n\nExperience in ASIC verification of complex design units for at least one or two projects.\n\nBackground with design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).\n\nExposure to System Verilog and UVM based methodology for ASIC verification is highly desired.\n\nWays to stand out from the crowd:\nKnowledge of Memory controllers or prior experience with verification of IP/clusters involving access to Memory.\n\nGood debugging and problem solving skills.\n\nScripting knowledge (Python/Perl/shell).\n\nGood interpersonal skills and ability & desire to work as a part of a team.\n\nNVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "ASIC Verification Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-13", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/ASIC-Verification-Engineer_JR2024391", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.\n\nNVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! In this position, you will be expected to plan and implement IP/Cluster/SOC functional verification of designs that constitute our Graphics Processors and Tegra SOCs. You would work on creating regression plans for code as well as functional coverage closure. You would perform pre-silicon validation activities such as XPROP simulations and GLS.\n\nWhat you’ll be doing:\nOwn ASIC verification of IP/Cluster for complicated designs in RTL.\n\nWork with HW architects and designers to make the right implementation choices.\n\nInteract with the Performance verification teams to augment verification through dynamic simulations and/or Formal verification techniques.\n\nYou will work with the specifications and ensure functional and code coverage of all the RTL which you will verify.\n\nPartner with and enable FPGA and S/W teams to ensure that S/W is tested.\n\nBe involved with post-silicon verification and debug.\n\nWhat we need to see:\nBS / MS or equivalent experience.\n\n1+ years of design experience.\n\nExperience in ASIC verification of complex design units for at least one or two projects.\n\nBackground with design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).\n\nExposure to System Verilog and UVM based methodology for ASIC verification is highly desired.\n\nWays to stand out from the crowd:\nKnowledge of Memory controllers or prior experience with verification of IP/clusters involving access to Memory.\n\nGood debugging and problem solving skills.\n\nScripting knowledge (Python/Perl/shell).\n\nGood interpersonal skills and ability & desire to work as a part of a team.\n\nNVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior/Staff Software Engineer – Firmware, Pre/Post-Silicon Boot & Automation", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-10-13", "url": "https://careers.arm.com/job/bengaluru/senior-staff-software-engineer-firmware-pre-post-silicon-boot-and-automation/33099/100755887312", "is_hardware": true, "platform": "talentbrew", "jd_text": "Build the Future of SoC Software Validation!\nDo you enjoy solving complex engineering problems? Are you passionate about automation, embedded systems, and understanding how a chip boots from its first instruction?\nWe are looking for a Senior/Staff Software Engineer to help us build the tools and automation that make firmware development, system boot, and SoC validation faster and more reliable.\nOur team works across the SoC development lifecycle, from early software development to silicon bring-up. We develop and validate firmware across simulation, emulation, FPGA/prototyping environments, and post silicon.\nYou’ll work with engineers across firmware, silicon, architecture, operating systems, and validation to solve technical challenges, improve test coverage, and create automation that can be reused across different platforms.\nWe value engineers who enjoy writing good software, exploring how systems work, and finding practical ways to simplify complex engineering tasks.\nWhat You’ll Do\nYou’ll help us design and build automation that supports firmware development and system validation throughout the SoC lifecycle.\nYour work will include:\nBuild automation frameworks using Python and other programming languages to support firmware testing, system boot, platform bring-up, and regression testing.\nAutomate SoC boot workflows, from firmware builds and deployment to platform configuration, boot execution, log collection, failure detection, and reporting.\nDevelop reusable test solutions that work across simulation, emulation, FPGA/prototyping environments, and post silicon, adapting to platform-specific capabilities.\nValidate firmware and boot components, including Boot ROM, security firmware, trusted firmware, bootloaders, UEFI, Linux, and platform initialization.\nInvestigate complex failures across firmware, operating systems, hardware models, silicon, and automation infrastructure. Build tools that make debugging and failure analysis easier.\nImprove continuous testing by integrating automated validation into CI/CD pipelines and developing reliable regression and release-validation workflows.\nCollaborate and share knowledge with engineers across teams, review technical designs, and help improve our automation architecture and engineering practices.\nAs a Senior/Staff Engineer, you’ll also shape technical decisions, guide framework architecture, mentor engineers, and help define how we approach firmware and platform validation across projects.\nWhat We’re Looking For\nWe are looking for engineers who combine strong software development skills with an interest in firmware, embedded systems, and SoC technology.\nYou should bring:\n8-15 years of strong Python programming skills, experience developing reusable automation frameworks, and working knowledge of C, C++, or Rust.\nExperience in firmware, embedded systems, SoC software, system boot, platform validation, or test automation.\nUnderstanding of SoC boot flows, including Boot ROM, firmware initialization, bootloaders, UEFI, and operating-system boot.\nFamiliarity with the SoC development lifecycle and validation using simulation, emulation, FPGA/prototyping environments, or post-silicon platforms.\nExperience with Linux, shell scripting, debugging tools, source control, and CI/CD systems.\nAbility to investigate technical issues, develop maintainable software, and work effectively with engineers from different teams.\nWe encourage candidates with experience in one or more platform environments to apply. You don’t need to have worked with every stage of the SoC lifecycle.\nA bachelor’s or master’s degree in Computer Science, Electronics, Computer Engineering, or a related field, or equivalent practical experience, will help you succeed in this role.\nExperience That Would Be Helpful\nYou may also have experience in some of these areas:\nArm-based SoCs, Arm Fixed Virtual Platforms (FVPs), RTL simulation, hardware emulation, FPGA platforms, or silicon bring-up.\nFirmware technologies such as Boot ROM, Trusted Firmware-A (TF-A), RSE or similar security firmware, U-Boot, EDK II/UEFI, and Linux.\nSecure boot, trusted execution, device trees, ACPI, and platform security.\nPytest, Robot Framework, or other automation and validation frameworks.\nHardware debugging and management interfaces such as JTAG, serial consoles, BMCs, Redfish, or IPMI.\nContainer-based testing, remote lab management, distributed test execution, dashboards, and automated failure analysis.\nIn Return\nBased in Bangalore India, this is an opportunity to join a dynamic, collaborative, and driven team, and provides a genuine opportunity to craft the best outcomes for Arm.\n \n#LI-SA3\nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Engineer /Senior Engineer (Verification)", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-10-13", "url": "https://careers.arm.com/job/bengaluru/engineer-senior-engineer-verification/33099/101901604352", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job overview:\nExperience : 2-8 years\n \nResponsibilities:\n \nYou’ll be part of a team that builds complete reference systems around Arm IPs and use it for and Arm IP stress verification, giving you exposure far beyond traditional DV roles.\n· Integrate Arm CPU and system IPs into full reference platforms\n· Bring up systems across simulation and emulation\n· Debug real system issues spanning hardware + low-level software\n· Develop system-level tests (C/C++/Assembly driven)\n· Work closely with design, architecture, and global teams\n· Contribute to improving verification flows, tools, and efficiency\n \nWhy This Role Stands Out\n· 🔧 Early System-level exposure – go beyond UVM/testbench work\n· 🧠 Strong learning curve – CPU architecture, AMBA, memory systems\n· 🚀 High ownership – own IP integration, features, debug, and bring-up\n· 🌍 Global collaboration – work with teams across UK, US, and Europe\n· ⚡ Real impact – your work directly influences quality of Arm IPs.\n \nRequired skills and experience:\n \n· 2–8 years of experience in SoC/IP development or verification\n· Solid understanding of verification fundamentals & debug\n· Experience with C/C++ or Assembly-based testing\n· Exposure to pre-silicon environments (simulation/emulation)\n· Basic understanding of CPU or SoC architecture\n \nGood to Have\n· Knowledge of Arm architecture / AMBA protocols\n· Experience in embedded software or firmware bring-up\n· Exposure to SoC integration or system-level validation\n· Scripting in Python/Perl\n· Familiarity with Verilog/SystemVerilog\n \nWho You’ll Fit In Best As\n· You enjoy debugging and figuring out system integration problems\n· You want to work close to real hardware and full systems\n· You’re looking to move beyond pure DV into system understanding\n· You take ownership and can drive tasks end-to-end\n \nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Principal ASIC Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-10-13", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2504389", "is_hardware": true, "platform": "oracle", "jd_text": "About onsemi\n\n  onsemi (Nasdaq: ON) is a global leader in intelligent power and sensing technologies, driving innovation to build a safer, cleaner, and smarter world. With a strong focus on automotive, industrial, and AI data center markets, we are shaping the future of vehicle electrification, sustainable energy, and advanced automation.\n\nAbout the Treo Platform\n\n  The newly launched Treo Platform is a cutting-edge analog and mixed-signal solution built on 65nm Bipolar-CMOS-DMOS (BCD) technology. Supporting voltage ranges from 1–90V and operating temperatures up to 175°C, Treo is engineered for high-performance applications in automotive, medical, industrial, and AI data centers. Its modular architecture simplifies design, reduces system costs, and accelerates time-to-market. All products are manufactured at our state-of-the-art 300mm fab in East Fishkill, NY.\n\nYour Role\n\n  You would be working on a Sub-System of the Treo platform. We are seeking a seasoned Digital Design Expert to lead a Sub-System for the platform. This is a unique opportunity to shape the Sub-System of a transformative technology platform within a dynamic, global organization.\n\n#LI-VS1\n\nResponsibilities\nKey Responsibilities\nMicro architect, implement and verify the digital Sub-System\nInteract with multiple cross functional teams on requirements and deliverables.\nLead design and verification planning and ensure design testability\nPerform hands-on RTL coding and scripting for any automation.\nEnsure the IP meets the ASIL requirements.\nDrive innovation and standardization.\nWhat you need\nBE/ME in electronics or related technical field.\nAt least 7 years of relevant experience in semiconductor product development.\nProven expertise in SoC architecture, IP selection, RTL design and verification\nStrong grasp of digital design principles: FSMs, timing analysis, combinational/sequential logic\nProficiency in Verilog/System Verilog\nFamiliarity with tools: Lint, CDC, RDC, Design Compiler\nExperience with standard interfaces: APB, AHB, AXI, SPI, I2C, DMA\nDesign techniques: pipelining, low latency, power optimization\nExperience writing high-quality technical documentation\nProficiency in scripting languages: Python, PERL\nExperience leading small projects\nAbility to write specifications from high-level requirements\nUnderstanding of DFT, Functional Safety (FuSa)\nShould have good analytical skills for debug work needed during verification.\n#LI-VS1\n\nQualifications\nPreferred Qualifications\nExperience with AI-driven digital design tools\nExposure to platform standardization and IP reuse strategies\nWhy Join Us\nWe create a diverse set of world-class products in a friendly and team-oriented atmosphere. We provide an environment of continual learning and growth opportunities and support volunteer and charitable programs. We offer competitive benefit package and a great place to work. You will be able to build up a career in a successful international company, and you can participate in interesting international projects.\n#LI-VS1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Staff Digital Verification Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-10-13", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506823", "is_hardware": true, "platform": "oracle", "jd_text": "Position Summary\n\nWe are looking for a highly motivated Staff Digital Verification Engineer with 6-10 years of experience in ASIC/SoC verification. The ideal candidate will have strong expertise in System Verilog (SV) and UVM, along with hands-on experience in developing scalable verification environments, coverage-driven verification, and debugging complex RTL and gate-level issues. Exposure to Gate-Level Simulation (GLS) is required, while experience with fault injection simulations will be considered a strong advantage.\n\n#LI-DJ1\n\nResponsibilities\nKey Responsibilities\nExpected to take ownership and lead verification efforts across IP, subsystem, and SoC-level projects and work independently.\nIndependently Architect and develop reusable verification environments using System Verilog and UVM.\nCreate constrained-random, directed, and scenario-based test cases.\nDevelop scoreboards, monitors, protocol checkers, assertions (SVA), and coverage models.\nAnalyze and debug RTL and gate-level simulation failures for timing and functional signoff.\nAnalyze, debug, and enhance C/C++ golden reference models for functional verification.\nExecute, and debug fault injection simulations to validate functional safety requirements and fault handling mechanisms.\nCollaborate closely with design, DFT, physical design, and architecture teams to resolve issues and support sign-off activities.\nWork with AI-assisted engineering tools (e.g., GitHub Copilot, Microsoft Copilot, LLM-based code generation/debug tools, AI-driven verification productivity solutions) to enhance regression infrastructure and verification automation\n#LI-DJ1\n\nQualifications\nMaster's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.\n6-10 years of hands-on experience in Digital/ASIC/SoC Verification.\nStrong expertise in: System Verilog (Mandatory) and UVM (Mandatory)\nFamiliarity with industry-standard simulators such as Xcelium and Questa.\nVerification experience with some or all protocols such I2C, AHB/APB, MIPI\n#LI-DJ1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "SoC PnP Architect", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-10-13", "url": "https://careers.arm.com/job/bengaluru/soc-pnp-architect/33099/96455665696", "is_hardware": true, "platform": "talentbrew", "jd_text": "5+ years of experience in SoC PnP Architecture within the semiconductor industry, with a strong track record of driving system-level performance, power, and efficiency investigations across complex silicon platforms.\n \nStrong expertise in SoC performance architecture and pre-silicon performance analysis, including:\nHands-on experience with simulation and hardware emulation platforms such as Palladium, Veloce, ZeBu, or equivalent\nPerformance analysis using cycle-accurate, transaction-level, and emulation-based environments\nWaveform-based debug and signal-level performance analysis\nLatency, bandwidth, throughput, QoS, and utilization characterization\nTransaction-level tracing and protocol debug across CHI, AXI, PCIe, CXL, or equivalent system protocols\nIdentification of system-level bottlenecks across compute, interconnect, memory, and IO subsystems\nArchitectural tradeoff analysis across performance, power, area, latency, bandwidth, and implementation complexity\nStrong experience with SOC Performance and Power modeling methodologies, including:\nDevelopment and use of SystemC/TLM, analytical, trace-driven architecture models\nBuilding and calibrating models for performance, power, latency, bandwidth, utilization, and efficiency analysis\nModel-to-silicon correlation, including alignment of pre-silicon projections, emulation results, and post-silicon measurements\nEarly-stage architecture exploration to evaluate performance, power, area, thermal, TDP, and efficiency tradeoffs\nUsing models to guide SoC architecture decisions, IP configuration, memory/interconnect sizing, QoS strategy, and platform-level optimization\nAbility to translate modeling insights into clear architectural recommendations and measurable product improvements\nExtensive experience in post-silicon performance and power characterization, including:\nSilicon bring-up support from a performance and PnP perspective\nPerformance counter, PMU, telemetry, and trace-driven investigations\nCorrelation of pre-silicon projections, architectural models, and silicon measurements\nRoot-cause analysis of performance gaps, power inefficiencies, and workload-level bottlenecks\nSystem-level performance tuning under real silicon constraints\nAnalysis of workload behavior under power, thermal, voltage, frequency, and TDP limits\nStrong understanding of SoC system infrastructure and platform-level PnP behavior, including:\nCoherent interconnect fabrics and cache-coherency protocols\nDDR memory subsystems, memory controller behavior, scheduling, QoS, and bandwidth efficiency\nIO subsystems including PCIe, CXL\nPower management architecture, DVFS, clocking, voltage domains, power states, and throttling mechanisms\nProven experience working in both Linux and bare-metal environments, including:\nPerformance profiling and debug in Linux-based systems\nKernel-level performance analysis and tracing using perf, ftrace, PMU-based analysis, or equivalent tools\nLow-level bring-up, debug, and performance characterization in bare-metal environments\nUnderstanding of boot flows, firmware interactions, BIOS/UEFI or bootloader configuration, and system initialization impacts on performance and power\nAbility to debug issues across hardware, firmware, OS, driver, and workload layers\nStrong background in computer architecture and microarchitecture, including:\nCPU/GPU/NPU/DSP or accelerator performance behavior\nPipelines, cache hierarchy, prefetching, coherency, memory systems, and interconnect behavior\nSystem-level performance interactions across compute, memory, IO, and power-management blocks\nWorkload characterization and mapping of application behavior to architectural bottlenecks\nProficiency in C/C++ and Python for developing:\nPerformance and power analysis tools\nAutomation frameworks\nProfiling and telemetry infrastructure\nData analysis and visualization dashboards\nCorrelation flows across model, emulation, and silicon data\nExcellent communication and cross-functional collaboration skills, with the ability to:\nClearly present complex performance and power findings to architecture, design, verification, firmware, software, and leadership teams\nDrive data-based architectural recommendations\nInfluence SoC architecture, platform configuration, and product-level PnP decisions\nLead investigations across multiple teams and convert debug findings into architectural improvements, tuning proposals, or product guidance\n#LI-SC2\n \nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior HPC Cloud Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-13", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-HPC-Cloud-Engineer_JR2026768", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is looking for an exceptional engineer to grow and thrive alongside our HPC Infrastructure team that designs, evaluates, and optimizes the compute inrastructure powering NVIDIA's next-generation silicon design and AI\nworkloads. You will be the primary architecture reviewer and performance champion for new data center clusters being built across multiple sites globally.\n\nWhat you'll be doing:\nIn this position, you will own the build-out and day-to-day operation of NVIDIA's VLSI high-performance compute environments in the public cloud, and the repeatable patterns that let us stand up the next environment faster than the last.\nBring up and operate large compute clusters on Google Cloud end to end - instance provisioning, machine images, OS pipelines, networking, identity and quota management.\nBuild the automation that makes cluster bring-up reproducible: infrastructure-as-code, configuration management, image build pipelines, and host lifecycle automation including hostname and identity preservation across maintenance events.\nExtend the same patterns to new on-premises data centers so cloud and on-prem run on one toolchain rather than two, and work with networking and storage teams on cross-site connectivity, latency budgets, and what is cross-mounted versus kept site-local.\nThis is a hands-on technical role. You will debug at depth when clusters misbehave - image and boot issues, mount failures, scheduler-host interactions, capacity and quota problems - and partner with the scheduling and operations engineers so what you build is operable by the whole team, not only by you.\n\nWhat we need to see:\nB.E./B.Tech/M.Tech in Computer Science, Electrical Engineering, or equivalent experience.\n8+ years in infrastructure engineering, with substantial time running production compute at scale.\nDeep, hands-on expertise with a major public cloud, Google Cloud preferred - compute, networking, IAM, storage, quotas, and the operational realities of running thousands of instances rather than tens.\nStrong infrastructure-as-code and configuration management skills (Terraform, Ansible, Puppet, or equivalent), plus experience with machine image build and OS lifecycle pipelines for large fleets.\nSolid Linux systems administration and troubleshooting: filesystems, NFS mounts and latency, networking, boot and image pipelines.\nWorking understanding of data center and network fundamentals for compute-intensive workloads - topology, bandwidth and latency characterisation, and the practical limits of cross-site operation - along with familiarity with batch schedulers (LSF, Slurm, or equivalent) and how compute nodes join, leave and are managed within them.\nStrong Python automation, experience bringing a new environment, cluster or data center online end to end, and the ability to work effectively across time zones. Semiconductor/EDA exposure is a plus, not a requirement.", "jd_status": "stored"}, {"title": "Senior Hardware Development Engineer", "company": "Nokia", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-10-13", "url": "https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/39889", "is_hardware": true, "platform": "oracle", "jd_text": "The Staff Hardware Development Engineer will play a crucial role in our NI ON department. They will own the mechanical design process, collaborating closely with cross-functional teams to deliver cutting-edge optical transceiver products. This role offers an exciting opportunity to contribute to the development of next-generation pluggable form factors and drive the future of optical networking.\n\nNILightpath\n\nResponsibilities\nOwn mechanical design and packaging for OSFP, OSFP-XD, QSFP-DD, and other pluggable form factors.\n Design high-density, thermally optimized solutions for 100G, 400G, 800G, and 1.6T transceiver modules.\n Work closely with Optics, Electronics, Thermal, and other teams from concept to production.\n Drive design-for-manufacturing (DFM) and cost optimization initiatives.\n Ensure compliance with MSA standards, customer requirements, and manufacturing processes.\n Lead the mechanical architecture decisions for next-generation pluggable products.\n Support product qualification and validation activities, including FAI, DVT, and PVT.\n Perform root-cause analysis and implement corrective actions for manufacturing issues.\n Collaborate with global suppliers and manufacturing partners to ensure smooth operations.\n\nQualifications\nB.E./B.Tech/M.Tech in Mechanical Engineering or a related field.\n5+ years of mechanical product design experience, with a minimum of 3 years in optical modules or compact electronic systems.\nExpertise in Creo Parametric or equivalent 3D CAD tools for part and assembly modeling.\nStrong understanding of mechanical packaging, tolerance engineering, and GD&T.\nHands-on experience with precision machining, sheet metal fabrication, and other manufacturing processes.\nAbility to perform engineering calculations for latch forces, insertion/extraction forces, and more.\nUnderstanding of material properties and selection for various components.\nExcellent communication and problem-solving skills for cross-functional collaboration.\nExperience in a high-volume manufacturing environment is preferred.\nA proven track record of delivering optical transceiver products from concept to production is an asset.\n\nAbout the company\nAdvancing connectivity to secure a brighter world.\n\nNokia is a global leader in connectivity for the AI era. With expertise across fixed, mobile and transport networks, powered by the innovation of Nokia Bell Labs, we’re advancing connectivity to secure a brighter world. \n\nLearn more about life at Nokia.\n\nOur recruitment process\n\nWe act inclusively and respect the uniqueness of people. Our employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.\n\nIf you’re interested in this role but don’t meet every listed requirement, we still encourage you to apply. Unique backgrounds, perspectives, and experiences enrich our teams, and you may be just the right candidate for this or another opportunity.\n\nThe length of the recruitment process may vary depending on the specific role's requirements. We strive to ensure a smooth and inclusive experience for all candidates. Discover more about the recruitment process at Nokia.", "jd_status": "stored"}, {"title": "Senior Engineer -Performance Verification", "company": "Ericsson", "location": "Bangalore,Karnataka,India", "date_posted": "2026-10-12T10:50:43+00:00", "url": "https://jobs.ericsson.com/careers/job/563121777063764", "is_hardware": true, "platform": "eightfold", "jd_text": "About this opportunity\n\nWe specialize in the top-level verification of cutting-edge ASICs that power complex high-performance systems. Our designs are either monolithic ASICs or integrated multi-chip-modules holding several hundreds of processor cores, DSPs as well as ARM cores, tailored hardware accelerator IPs and many high-speed interfaces, including Ethernet, CPRI, and PCIe.\nAs an Performance Verification Engineer, you'll be part of a team tackling some of the most challenging verification tasks in the industry, ensuring that our ASICs meet our high standards for performance, functionality, and security.\nYou will play an important role in the team developing environments and/or tests run in SystemC/TLM simulation, RTL environments, hardware emulation, and eventually on Silicon.\n\nWhat you will do\n\nWe are looking for people who can do ASIC Top level verification with special focus on Performance Verification.\nYour responsibilities will include:\nPerform RTL performance analysis , analyze throughput, latency, bandwidth, QoS, cache efficiency and memory utilization\nImplement performance verification plans at SoC-level and performance debug using both simulation and emulation environments.\nCollaborate with architecture, design, software and verification teams to define performance requirements and ensure alignment with overall system goals\nAnalyze and optimize system performance, including DDR, CPU, Interconnects and high-speed interface like PCIe, UCIe etc\nUnderstanding of cache coherency, memory hierarchy, DDR, NoC, and interconnect architectures\nExperience with high-speed protocols such as PCIe, Ethernet, AXI or DDR\nExperience with performance simulation tools\nLeverage AI-based tools and automation to improve engineering productivity and performance analysis workflows\nRole in the Team:\nParticipate in defining/documenting verification strategies for the parts of the ASIC assigned to you as a verifier.\nDebug RTL designs/Testcases with help of EDA simulation tools, HW emulator and SW debuggers.\nContribute to keeping tests clean in the CI regren running on all platformsssio.\nDevelop of tests involving UVM VIPs (used in some of our tests)\nDo formal connectivity verification and gate level simulation (GLS)\nto compile the ASIC designs to run in HW emulators, like Siemens Veloce and Cadence Palladium\ninterested in scripting and in developing and maintaining the TLV CI flow in projects, including visualization of results.\n\nYou will bring\n\nGeneral skills you must possess:\nSolid C programming skills targeting ASICs or other type of embedded software programming.\nSolid skills in RTL debugging issues in simulations of SystemVerilog or VHDL designs.\nDesired knowledge and experience in:\nUsing SW debuggers, waveforms windows etc. for HW/SW co-debugging of C-code running in the ASIC. Experience of multi core designs is a plus.\nGLS\nCoresight and other JTAG TAP related features\nCompiling designs for HW emulation\nFormal connectivity verification\nHigh speed interfaces like Ethernet, PCIe, CPRI\nARM CPUs/cores, SMMU\nAMBA interconnect, preferably using Cadence STG or IWB\nBonus knowledge and experiences are:\nXPROP\nGLS with timing, Power aware GLS\nDebugging tests running on HW Emulators and or Silicon\nSimulating and debugging tests running on SystemC/TLM platforms.\nPower aware verification (digital, not mixed signal)\nUsing Formal tools for power verification\nLab experience suitable for bring-up of ASIC Silicon prototypes\n\n.\n\n“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”\n\nWhy join Ericsson?At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.\n \nWhat happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.\n \nPrimary country and city: India (IN) || Bangalore\nReq ID: 789165", "jd_status": "stored"}, {"title": "DFT DV Lead", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-12T10:17:00+00:00", "url": "https://global-external-amd.icims.com/jobs/93665/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. MTS SILICON DESIGN ENGINEER  THE ROLE: The focus of this role is to plan, build, and execute the DFT verification of new and existing features for AMD’s Chiplets , resulting in no bugs in the final design.     THE PERSON:  As a DFx Verification Engineer, you will be primarily responsible for verification of architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products and will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference.   KEY RESPONSIBILITIES:  Collaborate with architects, design engineers, and firmware engineers to understand the new DFT features to be verified Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random DFT verification tests Debug test failures to determine the root cause; work with RTL/DFT and firmware engineers to resolve design defects and correct any test issues  Analyze and enhance legacy DFT test plans to accommodate new Design for Debug feature developments Write complex Perl scripts to update simulation files in a deterministic manner Recreate post-silicon failures in pre-silicon environment Conduct silicon debug and root cause analysis with minimal logging support Utilize JTAG protocols for debugging and validation   PREFERRED EXPERIENCE:  8+ years of experience in DFT Design Verification with strong debug capabilities Experienced with SystemVerilog/UVM testbench development for complex SoCs Including GLS & SDF verifications Advanced scripting skills (Python, Perl, etc.) for automation and testbench infrastructure Deep knowledge of digital design, RTL design, and verification flows Strong troubleshooting and analytical debugging skills with ability to debug without logs Ability to quickly adapt to complex infrastructure environments Excellent hands-on debug skills and attention to detail Proficient in debugging firmware and RTL code using simulation tools  Exposure to leadership or mentorship is an asset ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-PM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior SW Validation Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-12T09:57:40.135000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000154975409-senior-sw-validation-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "The Sr System Software Validation Engineer serves as embedded and system software domain expert, driving software quality, evaluation and validation objectives, and technical execution while collaborating closely with systems, firmware/software, validation, and platform develop teams.\nAs part of one of Renesas’s fastest growing product lines, you will have the opportunity to directly impact customer experience through work on software products that enable feature rich hardware to shine.  If you like problem-solving, working with systems involving SW/FW/HW, and switching between multiple languages and paradigms, we’d like to hear from you. If you seek a place to shine with no artificial barriers apply now!\nKey Responsibilities\nLead software and system validation planning and execution of embedded products, applications and solutions utilizing a wide portfolio of Renesas products\nDrive system level software technical decisions, ensuring robustness, usability and completeness of embedded solutions\nCollaborate closely with systems, firmware/software, validation, and product engineering teams to ensure seamless hardware‑software integration.\nIdentify and mitigate system-level technical risks, ensuring highest user experience\nPlanning and execution of new product prototype bring-up, bench-testing, and evaluation. \nSupport creation and review of technical documentation (Datasheets, User Manuals/Guides, Application Notes)\nContribute to reference designs, development platforms, and documentation to enable broad customer adoption.\nGather and drive clarity on software requirements from diverse groups including customers, application engineers, hardware, and firmware engineers\n\nBachelor’s or Master’s degree in Electronics Engineering, Computer Science or Computer Engineering\n 5-7 years experience in embedded firmware/software development required across multiple IoT application segments\nStrong understanding of Software Architecture and Design principles, Behavior-Driven Development and unit testing approaches\nKnowledge of ARM and RISC processors\nHigh-level of proficiency in C/C++, Embedded C programming\nProven experience delivering production‑quality embedded software for MCU and MPU based platforms.\nGood understanding of motor control software, real‑time systems, and embedded development workflows.\nWorking knowledge (hands‑on preferred) of one or more host-side technology stacks, such as:C/C++/ RTOS (FreeRTOS, Zephyr)\nC#/.NET / Python (automation/tools, GUIs, packaging)\n\nExperience integrating host utilities with embedded targets over common interfaces (e.g., USB, UART, SPI, I2C, Ethernet) across OS environments.\nExperience in developing Agentic Tools\nExcellent organizational skills, attention to detail and accuracy \nDemonstrates creative thinking in debug and troubleshooting skills and building solutions\nExperience in DevOps including JIRA, Confluence and GitLab preferred\nMust have highly developed written and verbal cross-functional communication skills\nAbility to work effectively in a multicultural, cross-functional environment.\nPreferred qualifications\nExperience supporting embedded development platforms or reference designs with broad customer adoption across Robotics, Edge AI and Industrial IoT applications\nExecute firmware validation of boot flows, power/clock/reset, memory subsystems, interconnects, and interfaces across stress, corner, and fault scenarios.\nDrive system bring‑up on evaluation boards, development boards and reference designs\nAnalyze validation data and logs, track issues through structured closure, and contribute to quality metrics.\nMentor junior engineers and provide technical guidance within the validation team.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "DFT Integration Lead", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-12T09:12:00+00:00", "url": "https://global-external-amd.icims.com/jobs/93447/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. SMTS DFT Design Engineer THE ROLE: · As a member of the S3 SoC DFx Team, the successful candidate will own/lead the DFT Design and Integration of cutting edge DFT structures including SCAN, ATPG, MBIST, BSCAN. · Position includes DFT design development, data analysis and silicon debug of DFT in leading process technologies. · Strong self-driving ability, should have excellent communication skills (both written and oral) · Strong problem-solving skills KEY RESPONSIBILITIES: · Working closely with the DFT Architecture and the various IP Design teams to align on the DFT requirements and successfully implementing the DFT design · Design and develop correct by construction DFT design and support DFT verification · Working closely with the RTL designers, Verification Engineers, and PD team to find creative ways to accelerate the identification of functional defects. PREFERRED EXPERIENCE: · Experience and an understanding of ASIC DFT, synthesis, simulation and verification flow · Experience is End-to-End DFT flow development/creation. · Expert in Perl, Python, TCL, and ability to create complex flows/scripts. · Strong EDA tools experience (Tessent, Design Compiler, Spyglass,) · Experience in DFT architecture for complex chips · Experience in RTL development using Verilog/System Verilog having worked on RTL for IP and SoC integration · Proficient in doing basic unit-level verification using simulations. · Experience with RTL quality check tools/methodologies such as Spyglass, CDC, Lint is required. · Must have experience with integration of various IPs into complex SOCs. · Exposure to Static timing analysis & Timing closure is required. · Scan/ATPG patterns & test flows development, debug, test, and characterization · Excellent hands-on debug skills and scripting skills are critical. · Must have good communication skills and the ability to work in a worldwide team environment. · Knowledge & experience of low power concepts, clock gating, power gating is a plus · Experience with post-silicon bring up is a plus ACADEMIC CREDENTIALS: · B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering · 11+ years’ experience in DFT Design #LI-RR1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Staff Software Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-12T07:49:04.652000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000154942389-staff-software-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "The software team is seeking a Staff SW Engineer who is technically savvy and is excited about working within a SoC development team to produce customer facing software. This position involves a wide range of challenges from interfacing with IC, firmware designers, Renesas internal cloud infrastructure team, product definition team and other stake holders.  As part of one of Renesas’s fastest growing product lines, you will have the opportunity to directly impact customer experience through work on software products that enable feature rich hardware to shine.  If you like problem-solving, working with systems involving software/firmware/hardware, and switching between multiple languages and paradigms, we’d like to hear from you. If you seek a place to shine with no artificial barriers, apply now!\nResponsibilities:\nDesign, develop, test, and maintain software that meets the needs of both customers and internal teams\nGather and drive clarity on software requirements from diverse groups including customers, application engineers, hardware, firmware and cloud infrastructure engineers\nContribute to both existing and new projects, covering a broad range of languages and scope. We use Java, Kotlin and Python.\nAid in code reviews for fellow team members, as required\n\nBachelor’s or master’s degree in computer science or computer engineering\n9+ years of software development experience\nTechnical expertise in cloud technologies like Java, python, Kotlin, Spring\nAssist in the upkeep of code quality, reusability, and continual code evaluation\nInvestigate and apply new technologies to enhance the user experience\nAbility to design, develop, and troubleshoot software solutions using creative, unconventional approaches\nStrong understanding of Software Architecture and Design principles, Behavior-Driven Development and unit testing\nExcellent written and verbal communication skills, with the ability to work across teams\n \nPreferred Skills:\nExperience with Generative and Agentic AI for software development.\nExperience working with JavaScript, JavaFX or GUI development\nUnderstanding of DevOps including JIRA, Confluence and GitLab preferred\nUnderstanding of basic electronics, microcontroller programming and bus communication.\n\nRenesas Electronics Corporation (TSE: 6723) empowers a safer, smarter and more sustainable future where technology helps make our lives easier. A leading global provider of microcontrollers, Renesas combines our expertise in embedded processing, analog, power and connectivity to deliver complete semiconductor solutions. These Winning Combinations accelerate time to market for automotive, industrial, infrastructure and IoT applications, enabling billions of connected, intelligent devices that enhance the way people work and live. Learn more at renesas.com. Follow us on LinkedIn, Facebook, Twitter, YouTube, and Instagram.\nRenesas’ mission, To Make Our Lives Easier, is underpinned by our company culture, TAGIE. TAGIE stands for Transparent, Agile, Global, Innovative and Entrepreneurial. Our goal is to embed this unique culture in everything we do to succeed as a company and create trust with our diverse colleagues, customers and stakeholders.\nWe are committed to creating a diverse culture where everyone is included and feels a sense of belonging. For more information, please read our Diversity & Inclusion Statement.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Sr Software Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-12T07:45:40.228000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000154941819-sr-software-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "The software team is seeking a Sr SW Engineer who is technically savvy and is excited about working within a SoC development team to produce customer facing software to enable our customers. This position involves a wide range of challenges from interfacing with IC, firmware designers, Renesas internal cloud infrastructure team, product definition team and other stake holders.  As part of one of Renesas’s fastest growing product lines, you will have the opportunity to directly impact customer experience through work on software products that enable feature rich hardware to shine.  If you like problem-solving, working with systems involving SW/HW, and switching between multiple languages and paradigms, we’d like to hear from you. If you seek a place to shine with no artificial barriers apply now!\nResponsibilities:\nDesign, develop, test, and maintain software that meets the needs of both customers and internal teams\nDrive clarity on software requirements from diverse groups including application engineers, hardware, firmware engineers\nContribute to both existing and new projects, covering a broad range of languages and scope. We use Java, Kotlin and Python.\nAid in code reviews for fellow team members, as required\n\nBachelor’s or Master’s degree in Computer Science or Computer Engineering\n2 to 7 years of software development experience\nTechnical expertise in Java, Kotlin programming languages\nAssist in the upkeep of code quality, reusability, and continual code evaluation\nAbility to design, develop, and troubleshoot software solutions using creative, unconventional approaches\nStrong understanding of Software Architecture and Design principles, Behavior-Driven Development and unit testing\nExcellent written and verbal communication skills, with the ability to work across teams.\nPreferred Skills:\nExperience with Generative and Agentic AI for software development.\nExperience working with JavaScript, JavaFX or GUI development\nUnderstanding of DevOps including JIRA, Confluence and GitLab preferred\nUnderstanding of basic electronics, microcontroller programming and bus communication\n\nRenesas Electronics Corporation (TSE: 6723) empowers a safer, smarter and more sustainable future where technology helps make our lives easier. A leading global provider of microcontrollers, Renesas combines our expertise in embedded processing, analog, power and connectivity to deliver complete semiconductor solutions. These Winning Combinations accelerate time to market for automotive, industrial, infrastructure and IoT applications, enabling billions of connected, intelligent devices that enhance the way people work and live. Learn more at renesas.com. Follow us on LinkedIn, Facebook, Twitter, YouTube, and Instagram.\nRenesas’ mission, To Make Our Lives Easier, is underpinned by our company culture, TAGIE. TAGIE stands for Transparent, Agile, Global, Innovative and Entrepreneurial. Our goal is to embed this unique culture in everything we do to succeed as a company and create trust with our diverse colleagues, customers and stakeholders.\nWe are committed to creating a diverse culture where everyone is included and feels a sense of belonging. For more information, please read our Diversity & Inclusion Statement.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "IP Verification Lead Engineer, Sr", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-12T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720255664", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\n1. Minimum Exp Level should be 6+ years in IP level verification\n2. Good in system Verilog and UVM Concept.\n3. Should have good understanding and in hand experience in developing testbench from scratch and aware of all TB environment concept.\n4. Should be good in Debugging design by using VCS tool.\n5. Good understanding of digital and Verilog concept.\n6. Preferrable to have experience in Security related IP like cryptography and prng and RSA algorithms.\n7. Preferrable to have understanding in SiFive RISC processor.\n8. Good understanding in basic bus protocol like AHB/AXI/APB.\n9. Good understanding in Functional/Code coverage.\n10. Good to have Formal tool knowledge either VCF or Jasper gold.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NOC DV Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-12T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721283289", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nLooking for an experience Verification Architect/ Engineer, who will be responsible Verification of next generation Infrastructure IPs (DDRSS, Memory Controllers etc.)  which goes into System-on-chip (SoC) for smartphones, tablets and other product categories. In this position you will be expected to plan and implement IP/Cluster/Formal verification flows for the Infra IPs. Also expected to coordinate with different Design and SOC teams throughout the IP development cycle.  \n\nJob responsibilities include \n·               Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage) \n·               Develop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench \n·               Work closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure \n·               Debug of regression signatures and identifying bug fixes \n·               Responsible for Quality sign off and required documentation \n·               Developing/Deploying scripts/tools for validation (Certitude, VC Formal, VPlan) \n·               Debug and root cause post silicon issues in collaboration with Design, SW and test teams \n·               Work with SoC level performance modeling team on latency, bandwidth analysis \nnext-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\nAdditional Job Description\nRequired skillset include \n·               Strong debugging, Analytical and problem-solving skills \n·               Expertise on UVM based verification  \n·               Knowledgeable about ARM bus protocols, Virtual Memory concepts, SoC system architecture \n·               Experience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved \n·               Communication and collaboration skills to work with a large world-wide design organization \n  \nDesired skillset includes \n·               Experience in designs optimized for low power - Dynamic clock gating, Logic/ Memory power collapse  \n·               Experience in verifying designs meeting Automotive Safety Integrity Levels (ASIL) \n·               Proficiency in Scripting languages (Python or Perl) for Automation initiatives, C/C++/SystemC for performance models \n·         Post-si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage \nQualification : \n·         Bachelor/Master’s Degree in Electronics & Communication / Micro Electronics \n·        3+ Years of Experience in IP verification or related\n·         Experience with UVM and ARM Bus protocols. \n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NOC DV Staff Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-12T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721283296", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nLooking for an experience Verification Architect/ Engineer, who will be responsible Verification of next generation Infrastructure IPs (DDRSS, Memory Controllers etc.)  which goes into System-on-chip (SoC) for smartphones, tablets and other product categories. In this position you will be expected to plan and implement IP/Cluster/Formal verification flows for the Infra IPs. Also expected to coordinate with different Design and SOC teams throughout the IP development cycle.  \n\nJob responsibilities include \n·               Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage) \n·               Develop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench \n·               Work closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure \n·               Debug of regression signatures and identifying bug fixes \n·               Responsible for Quality sign off and required documentation \n·               Developing/Deploying scripts/tools for validation (Certitude, VC Formal, VPlan) \n·               Debug and root cause post silicon issues in collaboration with Design, SW and test teams \n·               Work with SoC level performance modeling team on latency, bandwidth analysis \nnext-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\nAdditional Job Description\nRequired skillset include \n·               Strong debugging, Analytical and problem-solving skills \n·               Expertise on UVM based verification  \n·               Knowledgeable about ARM bus protocols, Virtual Memory concepts, SoC system architecture \n·               Experience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved \n·               Communication and collaboration skills to work with a large world-wide design organization \n  \nDesired skillset includes \n·               Experience in designs optimized for low power - Dynamic clock gating, Logic/ Memory power collapse  \n·               Experience in verifying designs meeting Automotive Safety Integrity Levels (ASIL) \n·               Proficiency in Scripting languages (Python or Perl) for Automation initiatives, C/C++/SystemC for performance models \n·         Post-si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage \nQualification : \n·         Bachelor/Master’s Degree in Electronics & Communication / Micro Electronics \n·        3+ Years of Experience in IP verification or related\n·         Experience with UVM and ARM Bus protocols. \n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NPU Staff Design Verification Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-12T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720711644", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nJob Summary:          \n·         Position for 8+ years of experience in design verification of complex Qualcomm propriety DSP/NPU IP\n·         DSP team is responsible for delivering high-performance DSP/NPU cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space, AI, Automotive and more.\n·         Qualcomm is one of the largest fabless semiconductor design companies in the world, generating over $35 Billion in annual revenues from chipsets and royalties from intellectual property.\n\n Job Responsibilities: \n·         Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power,  post silicon and back-end teams.\n·         Implement and improve System Verilog/UVM Testbench Architecture.\n·         Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency.\n·         Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals.\n·         Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails and bugs.\n·         Complete all required verification activities at IP level and ensure high quality commercial success of our products.\n·         Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis.\n·         Responsible gate level simulation bring-up, gate level verification with timing simulations.\n·         Responsible for power aware RTL verification and gate level simulation.\n\nSkillset/Experience:          \n·         12+  years experience in processor/ASIC design verification\n·         Solid background and understanding of Digital Design, Processor Architecture , Processor Verification and Power aware verification.\n·         Expertise in System Verilog Testbench Architecture and implementation.\n·         Experience in writing C based and assembly level testcases is preferred.\n·         Exposure to power aware implementation and verification using UPF is a plus.\n·         Experience with advanced verification techniques such as formal and assertions is a plus.\n·         Gate-Level Simulation and Debug — 0-delay, timing annotated  and power aware.\n·         Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence .\n·         Scripting/Automation Skills — Perl, Python, Shell, Make file TCI .\n·         Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts.\n·         Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred.\n·         Experience in verification of Processor subsystems is preferred.\n·         Experience in creating validation suite and building automation.               \n·         Should have excellent inter-personal and communication skills.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU EMIR CAD Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-12T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446717373753", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\n​As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\n6 to 15 years of experience in EM/IR and PDN domain is mandatory for this role\nExpert user of  Synopsys Redhawk SC/ Cadence Voltus power integrity analysis tool and have exposure to PNR/STA and extraction industry standard tools and  flow\nSupport and enhance static IR, dynamic IR, and electromigration flows at the block-level and  subsystem levels\nProvide guidance and feedback to PDN  analysis engineers on EMIR best practices, rules, and methodologies.\nTroubleshoot and debug EMIR issues and provide solutions to improve accuracy and efficiency.\nDevelop, support, enhance scripts that can postprocess EMIR results to dashboard and summarize actionable results for design team\nMaintain and release qualified flow releases for large and complex SoCs design implementation and analysis work.\nMaximize design productivity with strong/efficient python/tcl/perl scripting skills and customization of tool flows\nQualify EMIR tools with regression management systems and create tests.\nEngage with EDA vendors in providing cutting edge out of box solutions for new features and flows.\nCollaborate with EDA partners to determine/drive optimal and cutting-edge solutions for effective & efficient CAD solutions\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NPU Physical Design Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-12T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719660316", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nGeneral Summary\nPNR implementation for Qualcomm Hexagon NPU\nGood hands-on  experience on Floorplanning, PNR and STA flows\nGood knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc\nGood understanding on signoff domains– LEC/CLP/PDN knowledge, etc\nGood knowledge on Unix/Linux – Perl/TCL fundamentals/scripting\nPrincipal Duties and responsibilities:\nComplete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes.\nSignoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc)\nQuick learner with good analytical and problem solving skills\nQualifications:\n3+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NPU Physical Design Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-12T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720953649", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nGeneral Summary\nPNR implementation for Qualcomm Hexagon NPU\nGood hands-on  experience on Floorplanning, PNR and STA flows\nGood knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc\nGood understanding on signoff domains– LEC/CLP/PDN knowledge, etc\nGood knowledge on Unix/Linux – Perl/TCL fundamentals/scripting\nPrincipal Duties and responsibilities:\nComplete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes.\nSignoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc)\nQuick learner with good analytical and problem solving skills\nQualifications:\n2+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "ASIC RTL Design Engineer (Sr. Engr / Sr. Lead Engr", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-12T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720514637", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Description\n\nThis role offers a position in system power management IP cores and subsystem design, targeted for variety of industry leading Snapdragon SoCs for mobile, compute, IoT and Automotive markets.\n\nKey Responsibilities\nMicro-architecture and RTL design for IP Cores / subsystems.\nWork in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence.\nEnable SW teams to use HW blocks.\nQualify designs using static tool checks including Lint, CDC, CLP etc.\nSynthesis, LEC and Netlist CLP\nReport status and communicate progress against expectations.\n\n Preferred Qualifications\n3 to 8 years of strong experience in RTL design for ASICs\nExpertise in RTL coding in Verilog/SV of complex designs with multiple clock domains and multiple power domains\nFamiliar with UPF and power domain crossing\nExperience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP\nFamiliarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI\nExperience in low power design methodology and clock domain crossing designs\nExperience in Spyglass Lint/CDC checks and waiver creation\nExperience in formal verification with Cadence LEC\nUnderstanding of full RTL to GDS flow to interact with DFT and PD teams\nExpertise in Perl/TCL/Python language\nExperienced in database management flows with Clearcase/Clearquest.\nExpertise in post-Si debug is a plus\nExcellent oral and written communications skills to ensure effective interaction with Engineering Management and team  members.\nTeam player, self-motivated, should be able to work with minimal supervision.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Engineer - DFT", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-12T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720245596", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a DFT engineer you will be working on end-to-end Custom Silicon Design cycle, from DFT-architecture planning to delivering qualified Si parts to our customers. You will be using some the best industry-standard tools and company specific workflows to implement full chip level advanced Scan and MBIST insertion, verification, and pattern generation. Your role will involve collaborating closely with customers, working hand-in-hand with RTL/PD teams and supporting Test/Product Engineering teams.\n\nWhat you'll do:\n\n· Develop and implement comprehensive DFT architectures, collaborating on early planning stages.\n· Implement scan and MBIST using industry-standard EDA tools.\n· Develop and execute DFT verification plans (pattern generation, fault simulation).\n· Collaborate with cross-functional teams to resolve DFT-related issues.\n· Document DFT architecture and verification results.\n· Serve as the primary point of contact for DFT-related inquiries and lead the implementation efforts, ensuring alignment with customer requirements.\n\nWhat you'll need:\n\n· BTech/MTech in EE or related field, 2+ years DFT experience.\n· Proven leadership in complete DFT implementation and team guidance.\n· Deep understanding of advanced DFT techniques.\nNice to have\n· Experience driving DFT implementation on large designs.\n· Familiarity with advanced DFT techniques (e.g. In-system test, SSN, multi-die testing).\n· Silicon debug experience related to DFT.\n· Tool and methodology development related to DFT.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Infra Design Verification Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-12T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721243350", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nAdditional Job Description\nKey Responsibilities:\nDevelop and maintain UVM-based verification environments for high-speed interconnect protocols (PCIe, CXL, AXI).\nCreate and execute verification plans for high-speed interconnect protocols including PCIe, CXL, AXI, and CHI.\nPerform block-level and top-level verification, including functional coverage, assertion-based verification, and regression testing.\nCollaborate with RTL designers, architects, and validation teams to ensure design correctness and coverage closure.\nWork closely with design and architecture teams to understand specifications and derive verification strategies.\nUse third-party VIPs (e.g., Synopsys, Mentor) for protocol compliance and simulation.\nImplement and enhance scoreboards, agents, monitors, and sequences.\nIntegrate and validate SMMU and Coresight components in Subsystem environments.\nDrive verification closure through coverage convergence and assertion-based verification.\nContribute to performance, power, and cost optimization considerations during verification.\nMentor junior engineers and contribute to verification methodology improvements.\nDebug failures at RTL and gate-level simulations.\nRequired Skills:\nStrong proficiency in System Verilog, UVM, and verification methodologies.\nDeep understanding of PCIe Gen3/Gen4/Gen5/Gen6, CXL 1.1/2.0/3.0, AXI/CHI protocols, and SMMU/Coresight architecture.\nFamiliarity with Synopsys/Mentor VIPs for PCIe/CXL and AMBA protocols.\nExpertise in assertion-based verification (SVA) and coverage-driven testing.\nProficiency in Perl/Python/Tcl scripting for automation.\nKnowledge of power-aware verification (UPF), formal verification, and performance/power optimization.\nExperience with coverage-driven verification and random constraint-based testing.\nExperience with scripting languages like Python, Perl, or Tcl.\nPreferred Qualifications:\nBachelor’s/Master’s/Ph.D. in Electrical, Electronics, or Computer Engineering.\n3+ years of ASIC/Subsystem/SoC verification experience.\nExperience with PCIe, USB, Ethernet, or other peripheral protocols is a plus.\nExposure to post-silicon validation and lab bring-up is desirable.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NPU Design Verification Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-12T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720711658", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nAdditional Job Description\n\nSummary:          \n·        Position for 5+ years of experience in design verification of complex Qualcomm propriety DSP/NPU IP\n·        DSP team is responsible for delivering high-performance DSP/NPU cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space, AI, Automotive and more.\n·        Qualcomm is one of the largest fabless semiconductor design companies in the world, generating over $35 Billion in annual revenues from chipsets and royalties from intellectual property.\n Job Responsibilities: \n·        Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power, post silicon and back-end teams.\n·        Implement and improve System Verilog/UVM Testbench Architecture.\n·        Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency.\n·        Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals.\n·        Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails and bugs.\n·        Complete all required verification activities at IP level and ensure high quality commercial success of our products.\n·        Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis.\n·        Responsible gate level simulation bring-up, gate level verification with timing simulations.\n·        Responsible for power aware RTL verification and gate level simulation.\nSkillset/Experience:         \n·        2+ years experience in processor/ASIC design verification\n·        Solid background and understanding of Digital Design, Processor Architecture , Processor Verification and Power aware verification.\n·        Expertise in System Verilog Testbench Architecture and implementation.\n·        Experience in writing C based and assembly level testcases is preferred.\n·        Exposure to power aware implementation and verification using UPF is a plus.\n·        Experience with advanced verification techniques such as formal and assertions is a plus.\n·        Gate-Level Simulation and Debug — 0-delay, timing annotated and power aware.\n·        Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence .\n·        Scripting/Automation Skills — Perl, Python, Shell, Make file TCI .\n·        Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts.\n·        Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred.\n·        Experience in verification of Processor subsystems is preferred.\n·        Experience in creating validation suite and building automation.              \n·        Should have excellent inter-personal and communication skills.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Customer Support Engineer, Physical Design", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-10-12", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Senior-Customer-Support-Engineer--Physical-Design_R-101162-1", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nAbout the Role\n\nWe are seeking an experienced Senior Customer Support Engineer to provide deep technical expertise and resolve our customers' most complex Physical Design (PD) challenges. You will act as a critical technical escalation point and advisor. In this role, you will leverage your hands-on expertise in the RTL-to-GDSII flow to debug intricate implementation issues, recommend optimal PD recipes, and create robust reference documentation to ensure customer tape-out success.\n\nKey Responsibilities\nTechnical Escalation & Debugging: Act as a senior technical escalation point for challenging customer issues, actively debugging and resolving complex physical design roadblocks spanning from synthesis to post-route closure.\n\nCustomer Guidance & Optimization: Collaborate with the broader support and account teams to provide expert-level guidance on Physical Design (PD) recipes, helping customers tailor their implementation strategies to meet specific Power, Performance, and Area (PPA) targets.\n\nDocumentation & Reference Design: Develop, maintain, and publish comprehensive user guides, application notes, and reference physical implementation flows to empower both customers and internal support teams.\n\nCross-Functional Collaboration: Work closely with customer support leadership to synthesize and relay critical technical feedback on tool and flow performance to internal R&D and platform engineering teams.\n\nRequired Qualifications\nEducation & Experience: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with 4+ years of relevant industry experience.\n\nPhysical Design Expertise: 4+ years of hands-on experience in the digital Physical Design flow, with a strong understanding of all stages from RTL synthesis through Place and Route (P&R) to post-route signoff.\n\nProblem-Solving Skills: Exceptional analytical and debugging capabilities, with a proven track record of troubleshooting complex implementation and EDA tool issues.\n\nCommunication & Collaboration: Excellent verbal and written communication skills, with the ability to translate complex technical findings into clear, actionable guidance for internal stakeholders and external customers.\n\nPreferred Qualifications\nApplication Engineering Background: Prior experience in an applications engineering or technical support role within the semiconductor or EDA industry.\n\nIndustry-Standard Tools: Hands-on experience with major industry-standard physical design and synthesis tools (e.g., Synopsys Fusion Compiler/ICC2, Cadence Innovus, or Genus).\n\nScripting: Proficiency in scripting languages (TCL, Python) to automate debugging processes, build workarounds, or analyze customer design databases.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "SoC Design Verification Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-12", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/SoC-Design-Verification-Engineer_JR0287997", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nAbout the Team:\nYou will be joining Intel's cutting-edge product development group, a team focused on designing and verifying advanced semiconductor solutions. This group is at the forefront of innovation, delivering high-quality, scalable products that drive Intel's leadership in technology and performance. By contributing your skills here, you will help shape the future of computing and enable groundbreaking advancements in the industry.\n\nPosition Overview:\nAs a SoC Design Verification Engineer, you will play a pivotal role in ensuring that Intel's complex System-on-Chip (SoC) designs meet functional specifications and deliver high-quality performance. You will design scalable and reusable verification plans, develop test environments, and execute tests to uncover issues and improve functionality. Your contributions will directly enhance Intel's product quality and ensure optimal performance in presilicon development.\n\nKey Responsibilities:\nCreate and update UVM-based test bench generation and test case creation\nDefine and develop scalable and reusable block, subsystem, and SoC verification plans\nCreate test benches and verification environments that align with microarchitecture specifications\nExecute verification plans, including emulation and system simulation models, to ensure design functionality and uncover bugs\nDebug and root cause issues in presilicon environments, implementing corrective measures to address failures\nCollaborate with architects, RTL developers, postsilicon teams, and physical design teams to improve verification of complex architectural features\nDocument and maintain test plans, driving technical reviews with design and architecture teams\nIntegrate security coverage activities within test plans, including regression and debug tests\nMaintain and improve existing functional verification infrastructure and methodologies\nAbsorb learnings from postsilicon development and incorporate feedback into improved verification strategies.\n\nTo Be Successful, You Should Demonstrate the Following:\nAbility to work collaboratively across interdisciplinary teams\nStrong communication skills with the ability to work across interdisciplinary teams\nPassion for tackling complex problems and delivering innovative solutions\n\nQualifications:\nMinimum Qualifications:\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 7+ years of hands-on experience in SoC design verification, including demonstrated expertise in OVM/UVM methodologies, debugging, and test planningOR\nMaster's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 6+ years of hands-on experience in SoC design verification, including demonstrated expertise in OVM/UVM methodologies, debugging, and test planning.\n\nThe experience must include:\nAMBA protocols such as CHI, AXI, AHB, and APB with industry-standard VIP from various EDA vendors\nCreation and updating of UVM-based test benches and test case creation\nPreferred Qualifications:\nExperience with postsilicon validation and incorporating feedback into presilicon test plans\nFamiliarity with emulation models and system simulation tools for performance analysis\n\nWe invite you to bring your expertise and creativity to Intel, where your contributions will make a lasting impact on future technology. Join us and shape the future of computing with your skills and dedication.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "SoC Design Verification Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-12", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/SoC-Design-Verification-Engineer_JR0287499", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nAbout the Team:\nYou will be joining Intel's cutting-edge product development group, a team focused on designing and verifying advanced semiconductor solutions. This group is at the forefront of innovation, delivering high-quality, scalable products that drive Intel's leadership in technology and performance. By contributing your skills here, you will help shape the future of computing and enable groundbreaking advancements in the industry.\n\nPosition Overview:\nAs a SoC Design Verification Engineer, you will play a pivotal role in ensuring that Intel's complex System-on-Chip (SoC) designs meet functional specifications and deliver high-quality performance. You will design scalable and reusable verification plans, develop test environments, and execute tests to uncover issues and improve functionality. Your contributions will directly enhance Intel's product quality and ensure optimal performance in presilicon development.\n\nKey Responsibilities:\nCreate and update UVM-based test bench generation and test case creation\nDefine and develop scalable and reusable block, subsystem, and SoC verification plans\nCreate test benches and verification environments that align with microarchitecture specifications\nExecute verification plans, including emulation and system simulation models, to ensure design functionality and uncover bugs\nDebug and root cause issues in presilicon environments, implementing corrective measures to address failures\nCollaborate with architects, RTL developers, postsilicon teams, and physical design teams to improve verification of complex architectural features\nDocument and maintain test plans, driving technical reviews with design and architecture teams\nIntegrate security coverage activities within test plans, including regression and debug tests\nMaintain and improve existing functional verification infrastructure and methodologies\nAbsorb learnings from postsilicon development and incorporate feedback into improved verification strategies.\n\nTo Be Successful, You Should Demonstrate the Following:\nAbility to work collaboratively across interdisciplinary teams\nStrong communication skills with the ability to work across interdisciplinary teams\nPassion for tackling complex problems and delivering innovative solutions.\n\nQualifications:\nMinimum Qualifications:\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 7+ years of hands-on experience in SoC design verification, including demonstrated expertise in OVM/UVM methodologies, debugging, and test planningOR\nMaster's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 6+ years of hands-on experience in SoC design verification, including demonstrated expertise in OVM/UVM methodologies, debugging, and test planning.\n\nThe experience must include:\nAMBA protocols such as CHI, AXI, AHB, and APB with industry-standard VIP from various EDA vendors\nCreation and updating of UVM-based test benches and test case creation\nPreferred Qualifications:\nExperience with postsilicon validation and incorporating feedback into presilicon test plans\nFamiliarity with emulation models and system simulation tools for performance analysis\n\nWe invite you to bring your expertise and creativity to Intel, where your contributions will make a lasting impact on future technology. Join us and shape the future of computing with your skills and dedication.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "SoC Design Verification Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-12", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/SoC-Design-Verification-Engineer_JR0287501", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nAbout the Team:\nYou will be joining Intel's cutting-edge product development group, a team focused on designing and verifying advanced semiconductor solutions. This group is at the forefront of innovation, delivering high-quality, scalable products that drive Intel's leadership in technology and performance. By contributing your skills here, you will help shape the future of computing and enable groundbreaking advancements in the industry.\n\nPosition Overview:\nAs a SoC Design Verification Engineer, you will play a pivotal role in ensuring that Intel's complex System-on-Chip (SoC) designs meet functional specifications and deliver high-quality performance. You will design scalable and reusable verification plans, develop test environments, and execute tests to uncover issues and improve functionality. Your contributions will directly enhance Intel's product quality and ensure optimal performance in presilicon development.\n\nKey Responsibilities:\nCreate and update UVM-based test bench generation and test case creation\nDefine and develop scalable and reusable block, subsystem, and SoC verification plans\nCreate test benches and verification environments that align with microarchitecture specifications\nExecute verification plans, including emulation and system simulation models, to ensure design functionality and uncover bugs\nDebug and root cause issues in presilicon environments, implementing corrective measures to address failures\nCollaborate with architects, RTL developers, postsilicon teams, and physical design teams to improve verification of complex architectural features\nDocument and maintain test plans, driving technical reviews with design and architecture teams\nIntegrate security coverage activities within test plans, including regression and debug tests\nMaintain and improve existing functional verification infrastructure and methodologies\nAbsorb learnings from postsilicon development and incorporate feedback into improved verification strategies.\n\nTo Be Successful, You Should Demonstrate the Following:\nAbility to work collaboratively across interdisciplinary teams\nStrong communication skills with the ability to work across interdisciplinary teams\nPassion for tackling complex problems and delivering innovative solutions\n\nQualifications:\nMinimum Qualifications:\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 7+ years of hands-on experience in SoC design verification, including demonstrated expertise in OVM/UVM methodologies, debugging, and test planningOR\nMaster's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 6+ years of hands-on experience in SoC design verification, including demonstrated expertise in OVM/UVM methodologies, debugging, and test planning.\n\nThe experience must include:\nAMBA protocols such as CHI, AXI, AHB, and APB with industry-standard VIP from various EDA vendors\nCreation and updating of UVM-based test benches and test case creation\nPreferred Qualifications:\nExperience with postsilicon validation and incorporating feedback into presilicon test plans\nFamiliarity with emulation models and system simulation tools for performance analysis\n\nWe invite you to bring your expertise and creativity to Intel, where your contributions will make a lasting impact on future technology. Join us and shape the future of computing with your skills and dedication.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Senior SoC Design Engineer", "company": "Lattice", "location": "Shanghai, China", "date_posted": "2026-10-12", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Shanghai-China/Senior-SoC-Design-Engineer_R-103247", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\n\nAccountabilities: \nIdentify the domain specific requests for certain solution/application, define and develop the IP accordingly.\n\nIntegrate all IPs into SOC and verify the implementation flow.\n\nSOC level functional verification and performance evaluation based on SOC.\n\nBoard level setup/bootup.\n\nCo-work with software engineer for co-verification and system debug.\n\n针对具体的解决方案或者应用，评估并找出特定需求，并以此定义和开发IP；\n\n集成IP并构建合适的SOC，并验证整个实现流程；\n\nSOC级别的功能验证及性能评估；\n\n建立板级开发环境并初步启动SOC；\n\n和软件工程师合作完成软硬联合验证及系统级调试。\n\n \nRequired Skills:\nMaster's degree or above, majored in ME/EE/CS etc, and should have at least 3 years of working experience in FPGA related design.\n\nFamiliar the concept of Embedded System (SoC) design or digital/FPGA design.\n\nFamiliar with verilog/SystemVerilog.\n\nFamiliar with simulation tools like Ncsim, Modelsim/Questasim.\n\nFamiliar with system bus (AXI, AHB, Wishbone etc. ).\n\nExperiences in one or more of the following area will be a plus:\n\na. RISC architecture and micro-architecture (RISCV , ARM);\nb. Peripheral and legacy IP (PCIE, SPI, I2C, UART etc);\nc. Embedded  programming with C language;\nd. FPGA design flow;\nMust possess independent problem solving skills.\n\nStrong written and verbal communication skills and the ability to work with multiple groups.\n\nMust be a sense of responsibility and work actively.\n\n研究生及以上学历，电子、通信、计算机、自动化等相关专业，3年以上FPGA相关设计工作经验。\n\n熟悉嵌入式系统/SOC，或数字/FPGA设计。\n\n熟悉Verilog/SystemVerilog。\n\n熟悉仿真工具，如Ncsim，Questasim。\n\n熟悉系统总线，包括AXI，AHB，wishbone等。\n\n对以下项目有所掌握的优先：\n\na. RISC体系结构和微架构（RISCV，ARM）；\nb. 常用外设或IP，如PCIE, SPI，I2C，UART等；\nc. 基于C的嵌入式软件编程；\nd. FPGA开发流程；\n独立解决问题的能力。\n\n英文书写和口语能能力，能跨部门协作。\n\n有强烈的责任心。\n\n#LI-DNP\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nChinaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "EDA Staff SW Dev Eng (C++,PNR/Synthesis)", "company": "Lattice", "location": "Pune, India", "date_posted": "2026-10-12", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Pune-India/EDA-Staff-SW-Dev-Eng--C---PNR-Synthesis-_R-103460", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nThere is energy here…energy you can feel crackling at any of our international locations.  It’s an energy generated by enthusiasm for our work, for our teams, for our results and for our customers.  Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing and support teams, who are developing programmable logic solutions that are changing the industry.  Our focus is on R&D, product innovation and customer service, and to that focus we bring total commitment and a keenly sharp competitive personality. \n\nEnergy feeds on energy.  If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.  \n \nLattice is seeking candidates for the position of EDA Staff Software Development Engineer.  This is a full-time position located in Pune, India.\nAccountabilities: \n \n·         Develop and deliver state-of-art and software infrastructure for world-class ease-of-use FPGA software tool for small, mid-range and large FPGA products.\n·         Develop software capabilities for next generation of FPGA products.\n·         Support and maintain existing FPGA design tools.\n·         Contribute to Spec and Plan process - review marketing requirement documents, generate functional specifications and developer unit test plans to ensure quality software.\n·         Improve development methodologies and processes.\n·         Candidate will work on developing advanced security flows, like Isolation Design Flow and partial reconfiguration flows\n \nQualifications:\nBS/MS/PhD Electrical Engineering or Computer Science\n12+ years of experience in large-scale software development for engineering application domains preferably in FPGA/ASIC EDA domains.\nMust be proficient with C++. Modern C++ proficiency is a plus.\nExperience in partial reconfiguration flow is a plus\nStrong background in object-oriented programming, data structures and algorithms, and graph theory\nExperience of working on multiple platforms – at least Linux and Windows – is required.\nKnowledge of shell, TCL or Python scripting is a plus.\nFamiliarity with commercial FPGA software tools and design flow is a plus. Knowledge in FPGA logic design is a plus.\nMust be detail oriented and possess independent problem-solving skills. Must be able to drive projects and lead a discussion.\nStrong written and verbal communication skills, and collaboration skill with the ability to work with multiple groups.\n \n \nLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.\n \nLattice\nFeel the energy.\n \n \nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Senior Physical Design Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-12", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Physical-Design-Engineer_JR2026183", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel NVIDIA is a \"learning machine\" that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life's work, to amplify human creativity and intelligence. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nNVIDIA is seeking passionate, highly motivated, and creative design engineers to be part of a team working on industry-leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n\nWhat you'll be doing:\nIn this position, you will expected to be part of the physical design methodology team supporting top level timing closure flows. PD activities includes floorplanning, Placement, CTS, Postroute Optimization, STA, EMIR drop, IO Timing, ECO & DRC closure.\nWork in collaboration with design team for addressing design challenges. Help team members in debugging tool/flow/design related issues. Constantly look for improvement in top level timing optimization and closure flows to improve TAT. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention.\nBuild flows based on industry standard and custom EDA tools to implement designs efficiently and improve PPA. Support flows for chip design teams across tapeouts and tech nodes.\nWork closely with EDA vendors to improve toolchains to fix bugs and implement innovative ideas\n\nWhat we need to see:\nBE/BTECH/MTECH, or equivalent experience. 4+ years of experience in Physical Design, preferably with methodology/flow experience.\nWorking experience with tools like ICC2/Innovus, Aspen, PrimeClosure, Tempus, Seahawk etc used in the RTL2GDSIl implementation.\nStrong algorithmic thinking with good automation skills in Python, TCL, tool specific scripting on one of the industry leading Place & Route tools.\nAbility to multi-task and flexibility to work in global environment. Good communication skills and strong motivation, Strong analytical & Problem Solving skills\nWillingness to learn and master new techniques quickly. Innovate and drive changes across teams & workflows\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior Test Engineer, Hardware Compute Group", "company": "Amazon", "location": "Bengaluru, Karnataka, IND", "date_posted": "2026-10-12", "url": "https://www.amazon.jobs/en/jobs/10575479/senior-test-engineer-hardware-compute-group", "is_hardware": true, "platform": "amazon", "jd_text": "Amazon Devices is an inventive research and development company that designs and engineer high-profile devices like the Kindle family of products, Fire Tablets, Fire TV, Health Wellness, Amazon Echo & Astro products. This is an exciting opportunity to join Amazon in developing its next generation SOC’s for the machine learning enabled consumer products. We are looking for exceptional engineers to join the SOC development team and help develop the next generation of chips based on a revolutionary architecture.\n\nWork hard. Have Fun. Make History.\n\nThe Role:\nAt Amazon, as a Manager - Test engineer you will be instrumental in bringing New Product from first silicon testing, ramp up to be ready for Production Volume Test and improving the Product Yield at all stages of manufacturing the product working with the OSAT (Outsourced Semiconductor Assembly & Test) vendors. Design, collect and Analyze Test Data during Verification and Correlation Process to meet Product Specification and Manufacturability Criteria, while working closely with Test Engineer from the OSAT. Support Test Operations to test and ship Engineering Samples and Production quantities.\n\nKey job responsibilities\n• First silicon debug with Design and OSAT Test Engineering.\n• Defines test program flows and methods for solid test coverage.\n• Drive final test yield analysis and corrective actions\n• First silicon debug with Design and OSAT Test Engineering.\n• Finalize wafer-sort and final test programs in support of production\n• Drive product to meet yield and test time/cost goals.\n• Analyze yield at Engineering Sample phase and Characterize NPI product performances and manufacturing yield window including bench correlation to meet product requirements.\n• Identify and implement root cause solutions to yield loss mechanisms through statistical data analysis and failure analysis techniques.\n• Transfer product knowledge to OSAT sustaining engineer\n• Manage Test Contractor (OSAT) in early production stage\n\nBasic qualifications\n- Bachelor's degree in engineering, computer science or equivalent\n- Knowledge of the semiconductor industry, processes, technologies and key suppliers\n- 10+ years or more experience in semiconductor digital design, test and/or product engineering for complex SoC’s\n- Must have hands on experience & solid understanding of SOC development cycle in multiple ASIC projects\n- Hands on experience in successful new product introductions for multiple complex, high-volume SoCs in advanced process nodes\n- Strong knowledge of new product introduction from first silicon through product qualification and characterization\n- Good analytical, communication, team work, and troubleshooting and problem solving skills required\n- Managing a team of Test Engineers\n\nPreferred qualifications\n- Master's degree or Ph.D. degree in Electrical Engineering or related field\n- Good knowledge and debugging skill on ATE (J750 & Advantest 93K is preferred)\n- Chip design background in circuit/physical design (timing closure, power, etc.) or DV (correlating SW signatures to block level tests) is desirable\n- Post silicon physical debug background in speed-path/Vmin, memory arrays, clocking, or yield improvements\n- Post silicon logic debug background in exercising various DFX features, analyzing scan-dump/mem-dump, suggesting tests in both system level and in DV\n- Product engineering background and familiarity with ATE coverage, margin, binning, scan pattern generation, etc\n- Knowledge of CPU, DDR4/LPDDR4/LPDDR5, USB, eMMC, CSI/DSI & MIPI characterization is a highly desired\n\nOur inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "jd_status": "stored"}, {"title": "Vulnerability Management Analyst — Semiconductor IP", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-12", "url": "https://careers.synopsys.com/job/bengaluru/vulnerability-management-analyst-semiconductor-ip/44408/101868933504", "is_hardware": true, "platform": "talentbrew", "jd_text": "Vulnerability Management Analyst - Semiconductor IP\nWe Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nYou are someone who builds trust with product and engineering teams when the topic is risk. You listen first, explain complex findings in clear language, and own your conclusions. You help people understand what a vulnerability means for their work and what they should do next.\nYou are practical when information is incomplete. You stay focused on timely action, challenge unclear choices in a respectful way, and keep looking for better ways to reduce risk. You care about teamwork, follow-through, and leaving guidance that others can use.\nThis is a full-time role.\nWhat You’ll Be Doing:\nAnalyze vulnerabilities affecting semiconductor IP products, firmware, and related interfaces, and determine residual risk with clear assumptions.\nPrioritize findings so product teams can act in a timely way: severity, exploitability, affected assets, and recommended mitigations.\nWork with design, verification, firmware, and product teams to explain vulnerabilities, walk through impact, and agree how the team will mitigate.\nAdvise those teams on practical mitigations, compensating controls, and verification or test evidence that shows the risk is reduced.\nWork in semiconductor IP development and associated test flows, using the tools those teams use to design, verify, and test IP, so analysis matches how the product is actually built.\nBuild and maintain your own analysis, intake, scoring, and reporting tools, including in Python, when existing tools are not enough. Scripts and tools should be readable and usable by other analysts.\nTrack open risk through the cybersecurity lifecycle, from intake through analysis, treatment, verification, and internal release decisions, and keep status current.\nFacilitate working sessions so similar IP classes get consistent analysis, risk language, and mitigation guidance.\nLook for new and practical ways to detect, assess, and mitigate risk, including improved methods, automation, and lessons from prior findings.\nUse agentic workflows (AI agents, structured prompts, and human-in-the-loop review) to speed research and first drafts without handing off ownership of risk conclusions.\nRun the job in Jira, Confluence, Git, and GitLab: track vulnerability and risk work, keep documentation current, and version work products through review.\n\nThe Impact You Will Have:\nGive product teams vulnerability analysis and risk determinations they can trust and act on without re-deriving the work.\nReduce time-to-mitigation by explaining findings clearly and agreeing practical next steps with the teams that own the product.\nLeave mitigation and test guidance that design, verification, and firmware teams can execute.\nKeep residual risk visible and current so internal release and treatment decisions are based on evidence, not stale status.\nImprove consistency of vulnerability handling and risk language across similar IP classes.\nRaise the quality of risk reduction over time by bringing new methods, better mitigations, and fit-for-purpose tools into the workflow.\nWhat You’ll Need:\nBachelor’s degree in electrical engineering, computer engineering, computer science, cybersecurity, or a related field, or equivalent practical experience. An advanced degree is welcome, not required.\nTypically 3 or more years in vulnerability management, product cybersecurity, embedded security, or a closely related engineering role. Stronger evidence on vulnerability analysis and risk determination can offset fewer years. Title (Analyst or Senior Analyst) will match demonstrated depth.\nStrong practical experience in vulnerability analysis on real products, not only scanning or training exercises.\nAbility to determine risk: severity, exploitability, affected assets, likelihood, impact, and residual risk after proposed mitigations.\nAbility to explain vulnerabilities and recommended mitigations to engineering teams so they can act in a timely way.\nWorking familiarity with semiconductor IP development and associated testing, including the tools used to design, verify, and test IP. Specific commercial tool names are not required.\nAbility to write and maintain your own tools, including in Python, for analysis, intake, scoring, and reporting when existing tools are not enough. This is not a software-engineering role. Tools should be readable and usable by other analysts.\nExperience working with incomplete information and stating assumptions when the end-system is not fully known.\nExperience applying a cybersecurity lifecycle across planning, design, implementation, verification, and internal release, including tracking open risk to closure.\nHands-on understanding of embedded systems enough to reason about hardware-rooted and firmware vulnerabilities: SoC or MCU integration, firmware, interfaces, registers, boot and debug, and interconnects.\nExperience delivering analysis inside product-team cadence, including re-prioritizing when new findings or design changes arrive.\nPractical experience using AI agents and agentic workflows to speed research, drafting, and repetitive analysis, while keeping the human as owner of technical conclusions.\n\nHands-on use of Jira, Confluence, Git, and GitLab (or an equivalent Git forge) for tickets, documentation, and review.\nClear written and spoken English; able to lead technical sessions with geographically distributed teams.\nWorking knowledge of common vulnerability scoring and handling practice (for example CVSS) is helpful, as is ISO/SAE 21434 or a comparable product-cybersecurity standard, digital design or verification background (including RTL), semiconductor IP product experience, or applied embedded cryptography.\nWho You Are:\nYou build trust with design and product teams and keep working relationships strong when the discussion is about risk.\nYou own the technical conclusion. You do not hand off judgment to a scanner, a score, a tool, or the loudest voice in the room.\nYou write and speak clearly so engineers can understand a vulnerability and how to mitigate it without you in the room.\nYou work well with incomplete information, and you state assumptions instead of hiding them.\nYou drive timely action. You keep risk visible until it is treated or accepted with a clear rationale.\nYou challenge unclear practices in a respectful way and recommend mitigations teams can actually adopt.\nYou keep learning. You look for new and practical ways to assess and reduce risk, not only the methods you already know.\nYou are collaborative and non-disruptive with product teams, including when you need them to change course.\nYou are structured and detail-oriented, and you keep evidence current as findings and designs change.\nThe Team You’ll Be A Part Of:\nYou will join the CySec Vulnerability Management Team that supports Synopsys semiconductor IP products. You work with IP product teams in their delivery cadence. You collaborate with digital, analog, mixed-signal, firmware, and verification engineers, and with cybersecurity architects, to analyze vulnerabilities, determine risk, and agree mitigations through the cybersecurity lifecycle. The team works across regions. Your written work products are used by internal product and engineering teams.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Layout Design, Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-12", "url": "https://careers.synopsys.com/job/bengaluru/layout-design-staff-engineer/44408/101868933456", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in the trenches of physical design, where a misplaced power ring or a routing bottleneck can turn a promising memory macro into a timing nightmare. Layout is not just drawing rectangles to you, it is solving a puzzle where every micron counts and every decision ripples through verification, performance, and yield. You know that the difference between a memory compiler that ships and one that gets stuck in debug is usually a floor plan decision made two weeks earlier, and you are the kind of engineer who sees that coming.\nYou are comfortable moving between Calibre or ICV verification runs, XARA power analysis, and sitting with circuit designers to understand why a bitcell is behaving the way it is. When a DRC violation shows up at tape-out minus two days, you do not panic, you methodically trace it back, fix it, and document it so it does not happen again. You have strong opinions about power grid design and you can back them up with IR drop numbers.\nAt Synopsys, you will work on memory IP that goes into chips powering everything from AI accelerators to automotive systems. The layouts you own will be used by customers worldwide, and the quality bar is exactly as high as you would expect.\nWhat You'll Be Doing\nDesign and own full custom layouts for embedded memory blocks, including SRAM, register files, and ROM compilers across advanced process nodes\nDevelop floor plans, place memory cells and periphery blocks, route power grids and signal interconnects to meet area, performance, and power targets\nRun IR drop and electromigration analysis using tools like XARA, back-annotate layout parasitics, and iterate with circuit teams to close timing and power\nExecute physical verification using DRC and LVS tools such as ICV or Calibre, debug violations, and drive layouts to clean signoff\nCollaborate with memory compiler architects and circuit designers to translate specifications into manufacturable, verified layout deliverables\nScript layout automation flows using TCL, Perl, or C-shell to improve productivity and ensure consistency across memory variants\nSupport formal release cycles, including documentation, design rule checks, and handoff to product engineering and customers\nThe Impact You Will Have\nEnable Synopsys memory IP to meet aggressive PPA targets that directly affect customer chip performance and power efficiency\nReduce layout development cycle time through automation and reusable design practices, accelerating time to market for new memory products\nEnsure memory macros pass physical verification and reliability checks on the first pass, minimizing costly respins and customer escalations\nContribute to the quality and competitiveness of Synopsys memory compiler offerings used in high-volume production across automotive, mobile, and AI markets\nInfluence layout methodology and best practices that shape how the team approaches next-generation process nodes\nMentor junior layout engineers and share knowledge that raises the overall capability of the physical design team\nSupport customer engagements by delivering robust, well-documented layouts that integrate cleanly into complex SoC designs\nWhat You'll Need\nDiploma in Electronics Engineering with 8+ years of layout design experience, or BE/BTech with 6+ years, or MS with 4+ years in a directly relevant role\nDeep hands-on experience with full custom layout design for embedded memories including floor planning, placement, power grid design, and signal routing\nProficiency with layout tools such as Cadence Virtuoso or Custom Compiler, and physical verification tools like Mentor Calibre or Synopsys ICV\nStrong understanding of IR drop and electromigration analysis, including use of tools like XARA or RedHawk, and ability to close power integrity issues\nSolid knowledge of physical design methodologies across all phases: floor planning, place and route, DRC/LVS verification, and signoff\nScripting capability in TCL, Perl, or C-shell to automate layout tasks and improve design flow efficiency\nExperience with memory compiler development, block placement, and parasitic-aware layout optimization is a strong plus\nWho You Are\nYou can look at a layout and immediately spot the power grid weakness or the routing congestion that will cause problems three steps downstream\nWhen a circuit designer asks for a layout change that breaks your carefully optimized floor plan, you do not just say no, you explain the tradeoff and propose an alternative that works for both of you\nYou keep your manager informed without being asked, you know when a schedule is slipping and you surface it early with a plan, not just a problem\nYou are the person the team comes to when a tough DRC violation will not go away, because you have the patience and the methodology to track it down\nYou adapt quickly when process rules change or a new node brings unexpected challenges, and you help the rest of the team do the same\nYou take initiative to learn new tools and techniques, and you share what you learn so the whole team gets better\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process", "jd_status": "stored"}, {"title": "Analog Design - Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-12", "url": "https://careers.synopsys.com/job/bengaluru/analog-design-staff-engineer/44408/97550666512", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in the trenches of analog design, working on circuits that move data at speeds most people cannot fathom. SerDes is not just a buzzword to you, it is the domain where you have built voltage-mode drivers, tuned PLLs until they locked cleanly, and debugged equalization schemes that looked perfect in simulation but needed three more iterations in layout. You know that a well-designed CDR is the difference between a link that works and one that fails margin at the customer site.\nYou do not wait for a reference design to be handed to you. When you see a spec, you already start sketching topologies and thinking through tradeoffs between power, area, and performance. Layout is not something that happens after you finish the schematic, it is part of your design process from day one. A long metal run or poor device placement catches your eye in a floorplan review because you know exactly how it will show up in post-layout simulation.\nAt Synopsys, you will work on SerDes IP that ships in AI accelerators, data center switches, automotive SoCs, and consumer electronics. The circuits you design will be measured in gigabits per second, and the decisions you make will matter in millions of devices.\nWhat You'll Be Doing\nDesign and optimize analog front-end building blocks for SerDes IP, including voltage and current-mode drivers, equalizers (CTLE, FFE, DFE), CDR circuits, PLLs, DLLs, VCOs, phase interpolators, bandgaps, and regulators\nRun SPICE simulations across PVT corners and create verification test benches that validate performance against PCIe 6.0, PCIe 7.0, PAM4, Ethernet, USB, HDMI, or other high-speed protocol specifications\nCollaborate closely with layout engineers to minimize parasitic resistance and capacitance, reduce mismatch, and account for proximity effects in sub-micron CMOS processes\nWork with digital RTL engineers to verify calibration loops, adaptation algorithms, and control logic that tune your analog circuits in real time\nPresent simulation results, design tradeoffs, and performance data in peer reviews and customer-facing technical discussions\nDocument circuit architecture, design features, verification strategies, and test plans for integration into larger SerDes products\nOwn the full lifecycle of your blocks from spec to silicon, including post-layout verification, characterization support, and design-for-reliability checks for electromigration, IR drop, aging, and ESD\nThe Impact You Will Have\nYour circuits will enable multi-gigabit data transfer in AI accelerators, data center switches, automotive SoCs, and consumer electronics shipping in millions of units\nYou will help Synopsys deliver SerDes IP that meets the performance and power targets our customers depend on to win in competitive markets\nYour layout optimization and simulation rigor will reduce respins, saving months of schedule and significant engineering cost\nThe verification strategies you define will catch corner-case failures before tapeout, improving first-pass silicon success rates\nYour collaboration with digital and system teams will ensure analog-digital co-design works seamlessly, not just in theory but in real integrated test chips\nYou will contribute to the technical foundation of next-generation high-speed standards, influencing how the industry builds faster, more efficient links\nYour documentation and knowledge sharing will raise the design quality and speed of the entire analog team\n\nWhat You'll Need\nPhD with 2+ years of hands-on SerDes or high-speed analog design experience, or BTech/MTech with 5 to 10 years in the same domain\nSilicon-proven experience designing and bringing up analog or mixed-signal blocks in production chips, you have seen your circuits work in real silicon\nDeep expertise in at least several of these building blocks: analog front-end transceivers, voltage/current-mode drivers, PLLs, DLLs, VCOs, CDR circuits, bandgaps, regulators, CTLE, FFE, DFE, impedance calibrators, serializers, deserializers, or phase interpolators\nStrong proficiency with SPICE simulation tools and sub-micron CMOS design methodologies, you know how to set up corners, sweep parameters, and interpret results that matter\nExperience optimizing layout for performance, including parasitic extraction, device matching, stress effects, and design-for-reliability considerations like electromigration, IR drop, and aging\nFamiliarity with scripting languages such as TCL or Perl for automation and simulation flow setup is a strong plus\nWorking knowledge of high-speed serial standards like PAM4, PCIe 6.0, PCIe 7.0, Ethernet, USB, SATA, HDMI, or MIPI is highly valued\nWho You Are\nYou can take a specification document and translate it into a circuit architecture without waiting for someone to hand you a reference design\nYou catch layout issues early, you review floorplans and flag where a long metal run or poor device placement will degrade performance before it becomes a post-layout surprise\nYou are comfortable presenting technical data to peers and customers, you can walk someone through a Bode plot or an eye diagram and explain what it means for margin and yield\nYou push back when a requirement does not make sense or when a verification plan has gaps, you care about getting it right more than checking a box\nYou work well across teams, coordinating with digital designers on control loops, with layout on physical implementation, and with characterization engineers on test plans\nYou stay current on process technology and circuit techniques, not because it is trendy but because it helps you design better blocks\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Power Architecture Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-12", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Power-Architecture-Engineer_JR2027560", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.\n\nNVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nWhat you’ll be doing:\nBe part of NVIDIA Power Architecture Group that owns end-to-end power aspects such as - ASIC power analysis, power architecture, low power design, power-aware verification, advanced power methodologies, UPF methodologies, power feature bring-up on silicon, and post-Si power correlation for NVIDIA's family of products.\nContributing to power analysis by helping to architect, develop, verify & correlate power estimation models/tools for NVIDIA's products\nBe part of the team that architects & designs system-level power features for optimizing the dynamic and leakage power dissipation for different usecases.\nWork on power verification which includes structural, functional & power aware verification of power features of NVIDIA products by coming up with test plans, write testcases, build test bench components like Monitors, assertions and coverage points & own verification convergence across RTL, Gates and Silicon.\nValidate the effectiveness of the power features on silicon, conduct studies and contribute to the Performance/Watt improvement ideas.\nHelp build power management solutions and drive innovation in energy efficiency across NVIDIA’s product portfolio.\n\nWhat we need to see:\nB.Tech./M.Tech with 2+ years of experience related to Power such as Power analysis, Power Design, Power Aware Verification, UPF methodologies and Power Correlation\nStrong fundamentals in power including transistor-level leakage/dynamic characteristics of VLSI circuits\nStrong fundamentals in digital design and verilog\nFamiliarity with low power design techniques such as multi-VT, Clock gating, Power gating, Voltage Islands and Dynamic Voltage-Frequency Scaling (DVFS)\nGood background in power estimation techniques, flows and algorithms\nKnowledge of power intent formats - UPF/CPF or similar\nExperience in Static Power check tools like VCLP/CLP or similar & Dynamic Power verification tools like VCS-NLP or equivalent\n\nWays to stand out from the crowd:\nStrong debugging and problem-solving skills\nGood communication skills and ability & desire to work as a great teammate\nGood programming skills - Python preferred (Good skills with object-oriented programming & design) preferred.\nExposure to Power analysis tools (such as PTPX, EPS) or exposure to lab setups for power measurements like scope/DAQ with ability to analyze board level power issues is a plus\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.", "jd_status": "stored"}, {"title": "Design Engineer II", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-10-12", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Design-Engineer-II_R56249", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nBE/BTECH/ME/MTECH\n\nJob Description\n2-5 yrs of work experiences in VLSI domain with Master’s/bachelor’s degree in engineering Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology Expertise in assertions development/closure, constraint randomization, functional and code coverages, formal verification Expertise in test-bench development Strong RTL and GLS (w/ or w/o SDF) sim debug skills Should be able to manage project schedule and delivery independently\n\nShould be good in Perl/Tcl scripting and automation\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Principal ASIC Design Engineer", "company": "Nokia", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-10-12", "url": "https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/41320", "is_hardware": true, "platform": "oracle", "jd_text": "This role is for a ASIC design Lead for deep submicron technology with strong experience in end-to-end ASIC development, microarchitecture definition, RTL design, and technical leadership. The role requires ownership of a major ASIC/function from requirements analysis through implementation, verification, and silicon qualification.Experience with low-power ASIC design techniques and clock domain crossing\nKnowledge of AMS verification methodologies\nExposure to silicon bring-up and lab validation\nFamiliarity with EDA tools from Synopsys, Cadence, or Mentor\n\nResponsibilities\nAbility to interpret and map documents from standard bodies to requirements/functions\nWork with the architecture and other cross functional teams like SDK, verification, emulation teams.\nAbility to comprehend high level requirements and create a microarchitecture document\nProvide technical leadership to a team of designers and be responsible for delivery by taking it through planning, definition and implementation phase.\nHandson experience with various aspects of ASIC design including RTL coding and design checks including lint, CDC, RDC, synthesis\nStrong design skills - should be able to review the arch, requirements and micro-arch, synthesis and timing reports.\nWork with verification and lab validation teams to debug and qualify the implementation.\n\nQualifications\nCandidate must have a bachelor's degree or higher in CS or EE with very good academics. Master's degree preferred\n10+  years of experience and hands-on experience in delivery of a major function/ASIC\nPreferred: Prior experience in Ethernet/Networking domain\nAbility to mentor and bring together engineers with differing but valid technical viewpoints", "jd_status": "stored"}, {"title": "DV Power Vectors & Window Extraction Engineer (Staff/Sr Staff)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-11T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721152333", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nWe are looking for a talented engineer to join our team and drive power-vector development, execution, analysis, and window extraction across simulation, emulation, and silicon-validation environments.\nThis role is ideal for someone passionate about Design Verification, low-power design, power analysis, waveform debugging, and cross-functional execution.\n\nKey Responsibilities:\n[1]. Develop and execute DV power vectors covering key workloads, power states, transitions, boot flows, retention, reset, and stress scenarios.\n[2]. Bring up and maintain simulation, emulation, and power-aware verification environments.\n[3]. Analyze waveforms, activity dumps, power reports, and execution logs to identify meaningful power-analysis windows.\n[4]. Extract and document windows for peak power, average power, dynamic voltage drop, thermal analysis, and pre-silicon/post-silicon correlation.\n[5]. Debug vector failures, power-state sequencing issues, missing activity, waveform mismatches, and unexpected power behavior.\n[6]. Collaborate closely with DV, Design, Power, Physical Design, Emulation, PTE, and Post-Silicon teams.\n[7]. Maintain traceability between test cases, configurations, waveforms, extracted windows, and delivered vector collateral.\n\nRequirements :\nBachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.\n7-15 years of experience in Design Verification, power-aware verification, vector development, or power analysis.\nStrong understanding of: RTL simulation and waveform analysisSystemVerilog/UVM or equivalent verification environmentsLow-power concepts, power states, clock gating, retention, and isolationSimulation, emulation, GLS, or silicon-validation flowsPower estimation and activity analysis\nProficiency with scripting languages such as Python, Perl, Shell, or Tcl.\nExperience using waveform-debug and power-analysis tools.\nAbility to identify representative, peak, and corner-case power windows.\nStrong debugging, analytical, documentation, and communication skills.\nExperience working across multiple engineering teams in a fast-paced environment.\n\nGood to Have :\nExperience with UPF and power-intent verification.\nKnowledge of CPU, SoC, memory, interconnect, or subsystem power behavior.\nExperience with dynamic voltage drop, IR-drop, VMIN, or thermal analysis.\nFamiliarity with emulation platforms and large-scale workload execution.\nExperience correlating pre-silicon power results with post-silicon measurements.\nUnderstanding of frequency-voltage operating points and power-performance tradeoffs.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Director, Physical Design (Custom Silicon Group)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-11T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720216198", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next generation experiences and drives digital transformation to help create a smarter, connected future for all. As an ASIC Design Manager (Principal / Director-Level) in the Custom Silicon Group, you will lead the development and delivery of next-generation, high-performance SoCs from concept to tapeout. You will be responsible for driving the complete silicon development lifecycle, spanning architecture, RTL design, integration, physical design, verification, silicon bring-up, and production readiness. In addition to providing technical and organizational leadership, you will serve as a key customer-facing engineering leader, partnering with strategic customers and stakeholders to translate business requirements into successful silicon solutions.\n\nYou will lead a team of engineers and work closely with cross-functional groups across geographies -- including RTL design, verification, CAD, and integration teams. Your role will be pivotal in shaping the physical design strategy, ensuring design convergence, and maintaining signoff integrity across timing, power, and area metrics.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n\nPrincipal Duties and responsibilities:\nDemonstrate proven experience in executing responsibilities across multiple sites.\nLead and manage a team across multiple functions.\nDesign closure and tapeout expertise in advanced technology nodes.\nComplete ownership of PnR implementation, including Floor planning, Placement, CTS, and post-route activities on the cutting-edge nodes.\nPossess mandatory signoff knowledge, including STA, Power Analysis, FV, Low Power Verification and PV.\nCollaborate effectively to resolve issues related to constraints validation, verification, STA, Physical Design and tapeout\nUnderstand deep sub-micron design challenges, including leakage power, signal integrity, and DFM.\nSupport pre-sales and business development activities by evaluating technical feasibility and providing design expertise.\nProvide technical leadership during design reviews and executive-level customer engagements.\nDrive resolution of customer-reported issues by coordinating across design, verification, firmware, software, and validation teams.\n\nMinimum Qualifications\n• Bachelor's or Master’s degree in Electrical/Electronics Engineering and 20+ years of Hardware/VLSI Engineering specializing in Physical Design and timing signoff for high-speed SoCs.\n \nPreferred Qualifications:\nExcellent hands-on experience on Floor planning, PnR and STA flows\nGood knowledge of Placement/Clock Tree Synthesis (CTS), Low Power/High Performance optimization etc.\nThorough understanding of signoff domains– LEC/CLP/PDN etc.\n18+ years of experience with Physical Design and timing signoff expertise in latest tech nodes (e.g., 2nm/3nm/4nm/5nm)\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "IC Verification Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-10-11", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/IC-Verification-Engineer_R027134-3", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nJob duties include:\n·       Develop Test plans for all features for Block/Core/SOC and Write Functional coverage for these features.\n·       Architect and develop scalable and re-usable test benches, using the framework of the verification methodology\n·       Build pseudo-random tests to verify and get full Functional coverage\n·       Debug Regression failures, analyze Functional Coverage gaps and improve tests to cover the gaps\n·       Lead the documentation of verification strategy including Test plans, Verification Environment, pseudo-random tests, etc. Lead reviews with design/architecture.\n·       Drive improvements in Verification in terms of quality and efficiency.\n \nRequirements:\n·       Bachelor's degree in Electrical Engineering or related degree with 8+ years relevant experience or Master's degree in Electrical Engineering or related degree with 6+ years related experience\n·       6+ years of experience in writing and debugging complex test benches\n·       Must have deep understanding of all aspects of Verification from building Testbenches, developing Test plans and pseudo-random tests, Functional coverage.\n·       Must have proficiency in System Verilog and Verification Methodologies like UVM/VMM/OVM\n·       Should have exceptionally good command of Object-Oriented Programming principles.\n·       A good understanding of a complex protocol like PCIe or other multi-layered protocol\n·       Capability to work independently and deliver.\n·       Knowledge of PCI Express protocol is desired\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Subsystem/SoC Level Verification Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-10-11", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Staff-Engineer_R026384-4", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nHe/she should have strong knowledge of the following with 6+ years of experience in Ethernet Subsystem/SoC Level Functional verification\nWorking experience in Ethernet Subsystem/SoC verification\nExpertise to develop verification environments using System Verilog and UVM \nExpertise to develop BFMs / Checkers / monitors / Scoreboards\nMust have developed block/system level verification plans and tests.\nMust have capability to debug test failures to find the root cause.\nMust have worked on code / functional coverage.\nExperience in constrained random verification.\nDomain skills: Ethernet (MAC, PCS and SerDes)/SoC verification\nGate-level /SDF simulations\nKnowledge of scripting languages like Perl, Tcl\nFlexible to work in any IP/Subsystem/SoC projects\n\nCAD Tools: Cadence/Synopsys\n\nEducation Qualification: Bachelors/Master’s in Electrical/Electronics/VLSI\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Lead AI/ML Software Use Cases Validation Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-10T15:56:00+00:00", "url": "https://global-external-amd.icims.com/jobs/93308/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. AI/ML Software Use Cases Validation Engineer (Lead) About the Role Join AMD’s PAVS team as a Robotics Usecases Validation Engineer where you will Validate and Execute diverse Robotics platforms, variants and customer usecases for advanced robotics systems across software, hardware, and integrated platforms. Your work will ensure safety, reliability, and performance through rigorous testing in simulation, SIL/HIL environments, and real-world deployments. Job Summary We are seeking a Lead AI/ML Member of Technical Staff (MTS) with 8–12 years of experience to own and drive validation of AI/ML compute stacks and Physical AI SDKs. This role leads end‑to‑end AI pipeline validation, benchmarking, and performance optimization on Linux platforms, working closely with architecture, compiler, runtime, and hardware teams to deliver production‑quality AI solutions aligned to real customer use cases. Key Responsibilities Lead validation and quality ownership of AI/ML compute stacks on Ubuntu and Yocto Define validation strategy, test architecture, and coverage across functional, performance, stress, regression, and scalability testing Own and drive the defect lifecycle, including triage, root cause analysis, and closure Validate end‑to‑end AI pipelines, including: Model training, conversion, and optimization (e.g., PyTorch → ONNX) Kernel execution, memory transfers, and inference accuracy Define and execute AI benchmarking and profiling strategies for training and inference workloads Analyze compute, memory, and latency bottlenecks and drive system‑level and model‑level optimizations Validate AI frameworks and runtimes (PyTorch, TensorFlow, ONNX Runtime) Execute and optimize workloads on ROCm/HIP, CUDA, OpenCL, and heterogeneous accelerators Design and own Python‑based automation frameworks for validation, benchmarking, and reporting Drive improvements in validation scalability, efficiency, and performance coverage Collaborate closely with compiler, runtime, driver, and hardware teams Provide technical leadership and mentorship to senior and junior engineers Communicate validation status, performance metrics, and quality risks to stakeholders Required Skills & Qualifications Technical 8–12 years of experience in AI/ML software validation or performance engineering Strong expertise in Python scripting and test automation Strong ML fundamentals including deep learning and LLMs Hands‑on experience with ROCm validation, performance profiling, and optimization Experience with HIP, CUDA, OpenCL, and TensorFlow/PyTorch integrations Proven experience validating end‑to‑end AI pipelines Strong Linux expertise (Ubuntu, Yocto) Validation & Process Performance‑driven validation mindset with focus on production readiness Ability to lead initiatives independently with strong ownership Soft Skills Strong analytical and problem‑solving skills with clear written and verbal communication, and the ability to collaborate effectively with global, cross‑functional teams. Education Bachelor’s or Master’s degree in AI/ML, Robotics, Electronics, Computer Science, or a related field. #LI-NR1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Network Platform Development Engineer (Switch, SAI, NOS/SDK, Routing/Tunneling/Overlay protocols, L2/L3 Development, C, Linux Kernel, DPDK)", "company": "Marvell", "location": "Hyderabad", "date_posted": "2026-10-10", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Hyderabad/Network-Platform-Development-Engineer--Switch--SAI--NOS-SDK--Routing-Tunneling-Overlay-protocols--L2-L3-Development--C--Linux-Kernel--DPDK-_2604998", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nMarvell is a leading provider of innovative technologies, including ultra-fast read channels, high-performance processors, leading edge transceivers, highly efficient analog designs, and powerful cryptographic engines. These solutions address all segments of the hard disk drive (HDD) and solid-state drive (SSD) electronics markets, providing complete solutions including controllers, product firmware, and reference board designs. Many of the same technologies have been utilized in Marvell system solutions products, powering PCs, servers, cloud, and enterprise systems.\nWhat You Can Expect\nArchitect next-generation switching and DPU-based solutions tailored for enterprise and cloud-scale environments.\nImplement and optimize control plane and data plane functionalities for switch platforms.\nAdvance Layer 2/3 networking capabilities including VLANs, VXLAN, L2GRE, MPLS, BGP, OSPF, and multicast for scalable, resilient infrastructure.\nDesign high-performance switching fabrics with sophisticated packet processing pipelines, QoS, congestion control, and telemetry support.\nDevelop and integrate robust security features such as 802.1X, MACsec, NAC, micro-segmentation, and threat detection mechanisms.\nContribute to and influence open-source initiatives (e.g., SONiC, SAI, OVS, DPDK, ODP, Linux kernel) and help define future networking standards.\nCollaborate with hardware teams to bring up new Switch SoC platforms and ensure seamless hardware-software integration.\nParticipate in code reviews, design discussions, and continuous integration processes.\n\nWhat We're Looking For\nBachelor’s degree in Computer Science, Electrical Engineering, or a related field with 10+ years of experience. OR Master’s degree with 8+ years of relevant experience.\nProficiency in C, C++, Python, and Lua scripting.\nDeep understanding of Ethernet switching, Layer 2/3 protocols, DPUs and networking standards.\nStrong hands-on experience with SONiC, SAI, Cumulus Linux, OVS, DPDK, ODP, and DPU technologies.\nFamiliarity with ARM multicore SoC architecture and high-speed packet I/O.\nSolid grasp of networking constructs such as ACLs, LPM, EM, routing, MAC learning, QoS, bridging, and load balancing.\nExposure to cloud networking, SDN, or network virtualization technologies.\nStrong analytical and problem-solving abilities.\nExcellent communication and collaboration skills, especially in distributed team environments.\nProven ability to independently plan, execute, and deliver complex technical projects.\nA passion for continuous learning and thriving in fast-paced, innovation-driven settings.\n\nThis role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.\nAdditional Compensation and Benefit Elements\nWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\n\nInterview Integrity \nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\n\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\n\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n\n#LI-MN1", "jd_status": "stored"}, {"title": "Staff RAS Validation Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-09T11:28:00+00:00", "url": "https://global-external-amd.icims.com/jobs/89522/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. BIOS RAS SME THE ROLE AMD is looking for a highly motivated BIOS RAS Subject Matter Expert (SME) to join the Embedded x86 Validation Team. In this role, you will lead end-to-end validation, debug, and enablement of Reliability, Availability, and Serviceability (RAS) features across next-generation Embedded x86 Programs. You will partner with Architecture, BIOS, Firmware, Silicon Design, Product Engineering, and Validation teams to ensure industry-leading quality, reliability, and resiliency of AMD products. The ideal candidate possesses deep expertise in x86 platform architecture, BIOS/UEFI, memory subsystems, and system-level RAS validation. THE PERSON The successful candidate is passionate about platform quality and enjoys solving complex system-level challenges. You are a technical leader who thrives in cross-functional environments and has a proven track record in BIOS, firmware, silicon, or platform validation. You possess strong analytical and debugging skills and are comfortable driving technical discussions across architecture, development, validation, and customer-facing teams. KEY RESPONSIBILITIES Own validation strategy and quality sign-off for BIOS-driven RAS features across AMD APU platforms. Define feature coverage plans, validation methodologies, and automation strategies for RAS testing. Validate system resiliency, error detection, error containment, recovery, and reporting mechanisms. Drive validation and debug of: Memory ECC MCA architecture Error injection frameworks PCIe Advanced Error Reporting (AER) Platform-first and OS-first error handling Watchdog, reset, and recovery mechanisms Collaborate with BIOS, Firmware, Silicon Design, Architecture, and Customer Engineering teams to diagnose and resolve complex platform issues. Develop and execute automated regression suites to improve validation coverage and efficiency. Analyze failures, perform root cause investigations, and drive resolution through closure. Define quality metrics and release readiness criteria for program milestones. Mentor engineers and contribute to best practices across the validation organization. These responsibilities align with internal AMD RAS validation expectations and platform quality ownership. PREFERRED EXPERIENCE 8+ years of experience in BIOS, Firmware, System Validation, Platform Validation, or related fields. Strong understanding of: x86 architecture BIOS/UEFI DDR4/DDR5 memory architecture ECC mechanisms Reliability and error-handling architectures PCIe and advanced I/O subsystems Experience with silicon bring-up, platform enablement, and production-quality validation. Hands-on experience with system debug tools, error injection frameworks, and log analysis. Strong knowledge of Linux-based validation environments. Experience using Jira, source control systems, and validation automation frameworks. Proficiency in Python or similar scripting languages for automation. Academic Credentials Bachelor’s degree in Computer Engineering, Computer Science, Electronics Engineering, Electrical Engineering, or a related field required. Master’s degree preferred. Equivalent industry experience may be considered where applicable. #LI-DB2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Staff Engineer Design ", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-10-09T10:23:43+00:00", "url": "https://jobs.infineon.com/careers/job/563808972039685", "is_hardware": true, "platform": "eightfold", "jd_text": "Passionate about PLLs, DLLs, Oscillators, Clock Generation, and Silicon Debug? Join our team to develop next-generation Analog and Mixed-Signal IPs for cutting-edge semiconductor products. If you have 5–8 years of experience in Analog IC Design and enjoy solving complex design challenges, we'd love to hear from you!\n#Hiring #AnalogDesign #MixedSignal #PLL #DLL #Oscillator #Semiconductor #VLSI #StaffEngineer\n\nYour role\nKey responsibilities in your new role\n\nDesign and develop Analog/Mixed-Signal Clock IPs from specification to silicon validation.\nContribute to the design of RC Oscillators, Crystal Oscillators, PLLs, DLLs, Precision Comparators, Reference Circuits, Regulators, and Signal Chains.\nPerform architecture evaluation, circuit design, simulation, and performance optimization for clocking solutions.\nDerive block-level specifications from system requirements and ensure robust implementation.\nSupport silicon bring-up, characterization, validation, and debug activities.\nCollaborate with cross-functional teams including Digital, Verification, Physical Design, and Product Engineering.\nAnalyze design issues, drive root-cause identification, and implement effective solutions.\nSupport IP qualification and integration into SoC products.\nPrepare design documentation, review reports, and contribute to continuous process improvements.\nStay updated on emerging technologies and contribute to innovation in analog and mixed-signal design.\n\nYour profile\nQualifications and skills to help you succeed \n\nB.E./B.Tech/M.E./M.Tech/MS in Electronics, Electrical Engineering, VLSI, Microelectronics, or related disciplines.\n\n5–8 years of experience in Analog/Mixed-Signal IC Design.\nStrong understanding of analog circuit fundamentals and clock generation architectures.\nHands-on experience with Oscillators (RC/Crystal), PLLs, DLLs, Comparators, Reference Circuits, Regulators, and Signal Chains.\nGood knowledge of PMU circuits, Switching Regulators, and Temperature Sensors.\nExperience in silicon bring-up, validation, characterization, and debug.\nStrong problem-solving and analytical skills with the ability to troubleshoot complex circuit issues.\nFamiliarity with industry-standard analog design and simulation tools.\nExposure to switching converter design is a plus.\nPatents, publications, or technical contributions in clocking or analog IP design are an added advantage.\nExcellent communication and collaboration skills.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\n\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nkeerthini M H", "jd_status": "stored"}, {"title": "Staff Engineer ", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-10-09T10:11:50+00:00", "url": "https://jobs.infineon.com/careers/job/563808972125579", "is_hardware": true, "platform": "eightfold", "jd_text": "Looking for experienced engineers with 5+ years of experience in Semiconductor Product/Yield Engineering and a strong understanding of silicon characterization, manufacturing processes, and reliability analysis.\nBe part of a team that solves complex challenges and delivers high-quality semiconductor products to customers worldwide.\n#Hiring #Semiconductor #YieldEngineering #ProductEngineering #VLSI #SiliconCharacterization\n\nYour role\nKey responsibilities in your new role\n\nSupport semiconductor products throughout the product lifecycle, ensuring quality, reliability, and manufacturing excellence.\nInvestigate manufacturing, yield, reliability, and customer-return issues and drive timely resolution.\nAnalyze production data to identify yield excursions, process variations, and quality concerns.\nPerform root cause analysis (RCA) using statistical methods and failure analysis results.\nCollaborate with cross-functional teams to implement Corrective and Preventive Actions (CAPA).\nMonitor product health metrics and drive yield improvement and continuous improvement initiatives.\nSupport product qualifications, engineering change orders (ECOs), and product change management activities.\nGenerate reports and dashboards on yield, quality, reliability, and manufacturing performance.\nDevelop and enhance automation solutions for data collection, reporting, and analytics.\nDocument engineering findings, best practices, and sustainment procedures.\n\nYour profile\nQualifications and skills to help you succeed \n\nMaster’s degree in Electronics & Communication Engineering, VLSI, Microelectronics, or a related field.\n\n5+ years of experience in Semiconductor Product Engineering, Yield Engineering, or Sustaining Engineering.\nStrong knowledge of semiconductor manufacturing processes and silicon characterization.\nExperience in yield analysis, process monitoring, and product reliability assessment.\nHands-on experience with data analysis, root cause investigation, and statistical techniques.\nExposure to failure analysis, qualification activities, and product lifecycle management.\nFamiliarity with scripting or analytics tools for data automation and reporting.\nStrong problem-solving, communication, and stakeholder management skills.\nAbility to work effectively with design, test, manufacturing, quality, and reliability teams.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\n\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nKeerthini M H", "jd_status": "stored"}, {"title": "Staff/Principal Automative Use Cases Validation Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-09T10:08:00+00:00", "url": "https://global-external-amd.icims.com/jobs/91863/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. MTS SOFTWARE SYSTEM DESIGN ENGINEER Lead Automative Use Cases Validation Engineer THE ROLE: Join AMD’s PAVS team as an Automotive Infotainment Stack Validation Engineer, leading validation strategies and end to end use case validation for AMD’s Automotive Virtualization on AMD platforms. The role focuses on validating Xen based virtualization, multi OS domains (Android, Yocto, FreeRTOS/SafeRTOS), IVI features, graphics, and Ryzen AI workloads. You will work across the hypervisor, OS domains, drivers, and system level performance to enable next generation automotive compute platforms. THE PERSON: Your curiosity will drive your learning and innovation to improve how we as a group, and an organization, can get better every day. Your peers will provide you a results-oriented and encouraging environment for your career growth, fueling your opportunity to be a part of Delighting Our Customers.   KEY SKILLS: Virtualization (Xen): Multi VM Validation (Android/Yocto/FreeRTOS), virtio (camera/audio/media/GPU/NPU), passthrough (UART/I2C/SPI), AVIC, QoS. Boot Optimization testing with core boot for S3 & S5 OS Domains: Validation of Safe Linux, SDV AAOS, Yocto, and FreeRTOS/SafeRTOS including graphics workflows, automotive use cases, and IVI related feature validation. FreeRTOS/SafeRTOS: Control-domain validation, CRC, safe rendering, crash fallback, mixed criticality flows. Graphics/Display: AMD compositor (superframes, gestures, clone, virtual outputs), projection (Android Auto, CarPlay). Debug/Recovery: Full stack debug using Unified Debugger, system recovery validation. Cloud & AI: VAS on AWS/Google Cloud, V710; Ryzen AI workloads Audio: HiFi5 pipelines, ACP validation Security: Secure Boot to DomU, validation KEY RESPONSIBILITIES: Validate Xen based virtualized platforms across Android, Yocto, FreeRTOS. Optimize and validate boot flows across firmware → hypervisor → OS. Validate virtio pipelines and device passthrough. Validate compositor, display, GPU, and projection workflows. Lead system-level debug, performance tuning, mixed criticality validation. Support Secure Boot, safety flows, and cybersecurity validation. Collaborate with firmware, kernel, virtualization, graphics, and AI teams. Drive automating features PREFERRED EXPERIENCE: Strong in C/C++, Python, Shell automation. Deep experience with Linux kernel, hypervisors, drivers, bootloaders, SoC power states. Hands-on with Xen, multi VM orchestration, and automotive compute platforms. Test Automation: Development and automate test suites for virtualization, boot flows, OS domains, and IVI features. Frameworks & Tools: PyTest, Framework, custom Python/Shell-based automation, Jenkins/GitLab CI pipelines.  ACADEMIC CREDENTIALS: Bachelor’s or Master's degree in Computer or Electrical Engineering or equivalent #LI-NR1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Sr. Manager Physical Design Engineering", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-09T09:52:00+00:00", "url": "https://global-external-amd.icims.com/jobs/93397/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. Physical Design Lead (PNR) THE ROLE The Physical Design (PNR) Senior Manager is responsible for leading end-to-end Physical Design execution for complex SoC and ASIC programs, driving delivery from floorplanning through tapeout signoff. The role requires strong technical leadership in Place & Route, Timing Closure, Power, EMIR, Clocking, Physical Verification, and Design Methodology while managing multi-site engineering teams. The successful candidate will build and lead high-performing physical design teams, drive execution excellence across multiple programs, develop organizational capability, and partner with cross-functional stakeholders to deliver best-in-class silicon products. KEY RESPONSIBILITIES Technical Leadership Lead full-chip and block-level Physical Design execution. Drive Floorplanning, PNR, CTS, Timing Closure, Power Optimization, EMIR and Physical Verification signoff. Define and institutionalize scalable PD methodologies, flows, automation and best practices. Review technical quality, design readiness, milestone criteria, and signoff status. Drive technology enablement across new process nodes and advanced packaging technologies. Program Execution Own PD schedules, deliverables, and milestone commitments. Track execution across multiple SoC programs and ensure tapeout readiness. Identify technical risks and drive mitigation plans. Partner with Program Management and Engineering leadership to resolve execution bottlenecks. Present program status, risks, recovery plans and resource needs to senior management. Organization & People Leadership Build, mentor and retain a high-performing PD organization. Manage managers, technical leads, and senior engineers. Drive hiring strategy, succession planning, organizational scaling and capability development. Conduct performance reviews, career planning and growth discussions. Foster a culture of ownership, innovation, collaboration and engineering excellence. Cross-Functional Collaboration Partner with RTL, Architecture, DFT, FCT, DV, Power, Packaging, Silicon Validation and Product Engineering teams. Drive alignment across global engineering teams and external partners. Influence technical strategy and execution decisions across organizational boundaries. Strategic Initiatives Define long-term PD roadmap and capability growth plans. Drive productivity improvements through automation, AI-enabled workflows and flow enhancements. Develop execution strategies for future products, process technologies and emerging methodologies. Represent the organization in engineering reviews and leadership forums. REQUIRED EXPERIENCE Proven experience leading large-scale PNR teams and complex tapeouts. Deep expertise in: Floorplanning Place & Route CTS Timing Closure Power Optimization IR/EM Analysis Physical Verification Signoff Methodologies Strong understanding of advanced technology nodes. Experience leading multi-site and geographically distributed teams. Demonstrated people-management experience including managing managers and technical leads. Strong executive communication and stakeholder management skills. PREFERRED QUALIFICATIONS Experience with AI, Datacenter, Automotive, GPU, CPU or High-Performance SoC products. Expertise in advanced packaging and/or 3DIC technologies. Experience driving methodology, automation, and flow-development initiatives. Strong understanding of cross-functional domains including DFT, FCT, Power, Architecture and Silicon Validation. #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Engineer ", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-10-09T09:45:35+00:00", "url": "https://jobs.infineon.com/careers/job/563808972168113", "is_hardware": true, "platform": "eightfold", "jd_text": "Join us to drive semiconductor product quality, yield improvement, and reliability initiatives. If you have experience in silicon characterization, yield analysis, root cause investigation, and semiconductor manufacturing, we’d love to connect with you.\n\nYour role\nKey responsibilities in your new role\n\nSupport semiconductor products through the product lifecycle, ensuring quality and reliability.\n\nPerform silicon characterization, validation, and yield analysis.\nInvestigate manufacturing, reliability, and customer-return issues.\nConduct root cause analysis and drive corrective actions (CAPA).\nMonitor yield and product health metrics to support continuous improvement.\nCollaborate with design, test, quality, and manufacturing teams.\nSupport product qualifications, ECOs, and process changes.\nGenerate reports on yield, quality, and manufacturing performance.\nAutomate data analysis and reporting using scripting tools.\nDocument engineering findings and best practices for product sustainment.\n\nYour profile\nQualifications and skills to help you succeed \n\nMaster’s degree in Electronics & Communication Engineering, VLSI, Microelectronics, or a related field.\n\n3-5 years of experience in Semiconductor Product Engineering, Sustaining Engineering, Yield Engineering, or Manufacturing Support.\nGood understanding of semiconductor manufacturing processes, silicon characterization, and product lifecycle management.\nStrong analytical and problem-solving skills with experience in data analysis and root cause investigation.\nExcellent communication and collaboration skills to work with global cross-functional teams.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\n\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nkeerthini M H", "jd_status": "stored"}, {"title": "Senior Staff Engineer ", "company": "Infineon", "location": "Bangalore MG", "date_posted": "2026-10-09T08:46:09+00:00", "url": "https://jobs.infineon.com/careers/job/563808972174975", "is_hardware": true, "platform": "eightfold", "jd_text": "Join us to design and develop next-generation UWB PHY/MAC firmware, drive RTOS-based solutions, and work on cutting-edge wireless technologies. If you're passionate about embedded systems, low-level firmware, RF technologies, and scalable software architecture, we'd love to hear from you.\n\nYour role\nKey responsibilities in your new role\n\nLead the architecture and high-level design of scalable and modular firmware for UWB Radio/PHY platforms.\nDevelop and optimize firmware for UWB PHY/MAC in compliance with IEEE 802.15.4 standards.\nDesign and implement analog front-end and RF chain control/sequencing.\nPort, integrate, and optimize firmware on RTOS-based systems.\nDrive firmware bring-up, debugging, and validation using RTL models, simulations, and silicon platforms.\nDevelop and maintain unit test frameworks, HAL example applications, and software validation environments.\nIntegrate firmware development with CI/CD pipelines to enable continuous testing and quality assurance.\nBuild and execute automated regression, integration, and qualification test suites to ensure product reliability and performance.\nCollaborate with cross-functional teams to deliver high-quality embedded solutions and resolve complex technical challenges.\n\nYour profile\nQualifications and skills to help you succeed \n\n8+ years of experience in Embedded Software/Firmware Development.\nBachelor's or Master's degree in Electronics, Electrical Engineering, Computer Science, Computer Engineering, or a related field.\nStrong expertise in embedded system architecture, design, C programming, MATLAB, and object-oriented concepts.\nHands-on experience developing low-level device drivers (SPI, I2C, UART, DMA, Timers, GPIO) on ARM Cortex-M or similar platforms.\nSolid experience with RTOS environments such as FreeRTOS, Zephyr, ThreadX, or equivalent, including task scheduling, synchronization mechanisms, and system integration.\nGood understanding of UWB MAC/UCI or wireless technologies including BLE, Bluetooth, Wi-Fi, and LoRa.\nExperience translating hardware specifications, register maps, timing diagrams, and state machines into robust firmware implementations.\nProficiency with embedded debugging tools such as JTAG/SWD, logic analyzers, and protocol analyzers.\nKnowledge of low-power embedded design, including clock management, power sequencing, and sleep/wake mechanisms.\nStrong communication, leadership, and stakeholder management skills, with the ability to collaborate effectively across cross-functional teams.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\n\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nKeerthini M H", "jd_status": "stored"}, {"title": "ASIC Top Level Verification-SW/C Testcase Developer", "company": "Ericsson", "location": "Bangalore,Karnataka,India", "date_posted": "2026-10-09T06:19:58+00:00", "url": "https://jobs.ericsson.com/careers/job/563121775551107", "is_hardware": true, "platform": "eightfold", "jd_text": "About this opportunity\n\nJoin our new ASIC top level verification team.\nWe specialize in the top-level verification of cutting-edge ASICs that power complex high-performance systems. Our designs are either monolithic ASICs or integrated multi-chip-modules holding several hundreds of processor cores, DSPs as well as ARM cores, tailored hardware accelerator IPs and many high-speed interfaces, including Ethernet, CPRI, and PCIe.\nAs an ASIC Top-Level Verification Engineer, you'll be part of a team tackling some of the most challenging verification tasks in the industry, ensuring that our ASICs meet our high standards for performance, functionality, and security.\nYou will play an important role in the team developing environments and/or tests run in SystemC/TLM simulation, RTL environments, hardware emulation, and eventually on Silicon.\n\nWhat you will do\n\nWe are looking for people with focus in various areas in ASIC TLV. Exactly what you will do depends on your experience and the needs in the different projects, but typically includes\nSoC level testcase development with possibilities to specialize in special areas related to traffic on external interfaces and/or ASIC internal functionality involving DSPs, MCUs, CPU cores, ARM infrastructure, switches, security, SerDes, DDR and other types of external memory and much more.\nPreparing and setting up designs to run in Hardware Emulators, and update and maintain existing emulator platforms.\nParticipate in defining/documenting verification strategies for the parts of the ASIC assigned to you as a verifier.\nAs input you have documents and information from interaction with various type of stakeholders.\nParticipate in specification and development of software driven tests written in C.\nDebug RTL designs with help of EDA simulation tools and SW debuggers.\nBut also debug failing test cases using the SystemC/TLM platform or using the hardware emulator, depending on the situation\nBeside RTL simulations you will debug failing test cases running on any of our other run-platforms, SystemC/TLM simulation, Hardware emulation and on Silicon mounted on boards in the lab.\nIn case you lack experience of some platform you are expected to develop skills for such tasks.\nContribute to keeping tests clean in the CI regression running on our four platforms.\nwho occasionally can develop of tests involving UVM VIPs (used in some of our tests)\nwho from time to time will work with gate level simulation (GLS)\nto work with formal connectivity verification\nto compile the ASIC designs to run in HW emulators, like Siemens Veloce and Cadence Palladium\ninterested in scripting and in developing and maintaining the TLV CI flow in projects, including visualization of results.\n\nYou will bring\n\nSW/C testcase developers, some with SystemVerilog / UVM experience.\nPreferably experience in one or several areas:\nAMBA protocols\nARM cores/MCUs or processors\nJTAG and Coresight\nExternal interfaces: PCIe, XGMII/Ethernet, xSPI, I3C, UART, GPIO\nMemory interfaces: DDR, HBM\nClock and reset verification\nSoft Skills\nOpen, inclusive mindset, embracing diversity in culture, nationality, gender, etc.\nCollaborative approach, with a focus on team productivity and mutual growth.\nStrong drive for innovation, with a proactive interest in refining verification methodologies.\nClear communication skills for effective teamwork and coordination across diverse teams.\n\n.\n\n“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”", "jd_status": "stored"}, {"title": "PD Lead", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-09T06:12:00+00:00", "url": "https://global-external-amd.icims.com/jobs/93546/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. PMTS SILICON DESIGN ENGINEER 🔹 THE ROLE As a PHY‑V Lead, you will own physical verification sign-off, full-chip integration, and packaging interface (RDL) planning for advanced SoC programs. You will drive DRC/LVS clean tapeouts, integration quality, and sign-off predictability across complex multi-IP designs. This role requires strong expertise in physical verification, top-level integration, and advanced packaging alignment, along with the ability to lead cross-functional execution across PD, Analog, and Packaging teams. 🔹 THE PERSON Strong technical leader with deep PD + Physical Verification understanding Proven ownership of sign-off closure for complex SoCs Ability to drive execution across multiple teams and dependencies Detail-oriented with focus on quality, manufacturability, and schedule predictability Comfortable operating in high-pressure tapeout environments 🔹 KEY RESPONSIBILITIES ✅ Physical Verification & Sign-off Ownership Drive end-to-end DRC, LVS, ERC, antenna closure at block and full-chip level Define and enforce sign-off methodology and quality criteria Own foundry rule decks, waivers, and risk assessments Deliver sign-off clean GDS for tapeout ✅ SoC / Full-Chip Integration Lead top-level integration of IPs/macros into SoC Own: GDS assembly Hierarchical LVS reconciliation Resolve: Boundary issues Connectivity mismatches Integration conflicts Ensure robust integration across internal and third-party IPs ✅ RDL & Packaging Integration Drive RDL planning and bump mapping strategy Define IO escape routing and die–package interface Collaborate with Packaging, SI/PI, and system teams Enable flip-chip / 2.5D / 3D integration readiness ✅ Tapeout Execution & Tracking Own sign-off checklist, closure tracking, and tapeout readiness Lead tapeout reviews and milestone tracking Drive cross-team closure to meet schedule and quality targets ✅ Methodology & Flow Development Define and improve physical verification flows (Calibre/ICV/Pegasus) Drive: Automation (TCL/Python) Runtime optimization Debug efficiency Establish best practices for hierarchical and incremental sign-off ✅ Debug & Issue Resolution Lead debug of: Complex DRC violations LVS mismatches (shorts/opens/connectivity issues) Drive closure with PD/layout teams Minimize waivers and ensure risk-managed sign-off ✅ Leadership & Collaboration Lead and mentor PHY‑V engineers Act as primary escalation point for sign-off issues Interface with: PD / PnR teams Analog/layout teams Packaging and foundry teams 🔹 REQUIRED QUALIFICATIONS B.Tech / M.Tech in Electronics / Electrical Engineering 10–15+ years in Physical Design / Physical Verification / SoC Integration Strong expertise in: DRC, LVS, ERC, antenna checks Tools: Calibre / ICV / Pegasus Solid understanding of: Full PD flow (RTL → GDS → sign-off) Advanced process nodes (7nm and below) 🔹 PREFERRED QUALIFICATIONS Experience in: Full-chip SoC integration and GDS assembly RDL planning and advanced packaging flows Exposure to: IR/EM, SI/PI, PEX, reliability checks Chiplet / 2.5D / 3D-IC methodologies Strong scripting (TCL/Python) for automation #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "CPU Verification Engineer - Core Enablement", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-09T04:20:00+00:00", "url": "https://global-external-amd.icims.com/jobs/93558/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.     THE PERSON:  You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.   KEY RESPONSIBILITIES:  Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues  Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements   PREFERRED EXPERIENCE:  Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools  Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++   Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment.   Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience.   Scripting language experience: Perl, Ruby, Makefile, shell preferred.   Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions.     ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "SoC Sr Validation Engineer - Power Management", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-09T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721466219", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field.\n\nJob Description:\n2 to 5 years of relevant experience (A must)\nExtensive hands-on experience in Pre/Post Silicon Validation.\nProficient in Power Management, PMIC, or PVTC.\nStrong proficiency in C programming.\nPython scripting is an added advantage.\nSolid understanding of ARM architecture concepts.\nIn-depth knowledge of embedded systems concepts.\n\nPrincipal Duties and Responsibilities:\nLeverages Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\nIntegrates features and functionality into hardware designs in line with proposals or roadmaps.\nConducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\nCollaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\nEvaluates, characterizes, and develops the manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\nEvaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\nEvaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\nWrites detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\nWorks independently with minimal supervision.\nProvides supervision/guidance to other team members.\nDecision-making may affect work beyond immediate work group.\nRequires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \nTasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Peripherals Design Verification - Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-09T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446717223125", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\n8+ years’ experience in unit and IP level verification.\nWorked on coverage driven constraint random verification.\nKnowledge of standard protocols such as PCIe, CXL, USB, Ethernet.\nStrong in System Verilog, UVM, Test planning\nSound experience in testbench (stimulus, agent, monitor, checker) development.\nWorked in the verification having c based reference model inside the testbench\nExposure in scripting(perl, Python).\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU Design Verification - Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-09T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446717387171", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nRole Overview:\n\nWe are looking for an experienced CPU/SoC Validation Engineer with strong knowledge of ARM Generic Interrupt Controller (GIC) architecture and hands-on experience in post-silicon validation, system-level debugging. The engineer will own validation of interrupt-controller functionality across CPU, firmware, power-management, and OS interactions.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nKey Responsibilities\nDevelop and execute post-silicon validation plans for ARM GICv3/GICv4 and CPU interrupt subsystems.\nValidate GIC components including: Distributor (GICD)Redistributor (GICR)CPU interface and system registersInterrupt Translation Service (ITS)SGI, PPI, SPI and LPI interrupt flows\nValidate interrupt routing, prioritization, masking, preemption, affinity, acknowledgement and EOI behavior.\nDevelop stress scenarios covering: Concurrent interrupt generationHigh interrupt ratesMulti-core interrupt routingSGI broadcast and targeted SGIsInterrupt migration and CPU hotplugInterrupt handling during CPU idle and low-power transitions\nValidate GIC behavior across CPU power collapse, suspend/resume, reset and DVFS transitions.\nDebug complex issues involving lost interrupts, unexpected routing, interrupt latency, stuck interrupts and incorrect GIC state.\nAnalyze key GIC registers such as GICD, GICR, ICC system registers, ICH virtualization registers and ITS state.\nValidate interactions between the GIC and OS/kernel, firmware, hypervisor and power-management software.\nWork closely with CPU architecture, firmware, kernel, power-management, design and verification teams to root-cause silicon issues.\nUse hardware/software debugging techniques including register dumps, trace, kernel logs, crash dumps and waveform/trace correlation.\nDevelop automation and stress workloads for interrupt validation and regression testing.\nTrack validation coverage, defects, risks and closure status through engineering tracking systems.\n\nRequired Technical Skills\nStrong understanding of ARMv8/ARMv9 architecture.\nStrong understanding of ARM GICv3/GICv4 architecture.\nGood knowledge of: SGI / PPI / SPI / LPIInterrupt affinity and routingPriority masking and preemptionGroup 0 / Group 1 interruptsSecure and Non-secure interrupt handlingGIC Distributor and RedistributorCPU interface registersITS and MSI-based interruptsVirtual interrupts / vGIC concepts\nUnderstanding of CPU power states, clock/power collapse, reset sequences and low-power entry/exit.\nProgramming/scripting experience with C/C++, Python and shell scripting.\nExperience with JTAG/debuggers and SoC debug methodologies is desirable.\n\nPreferred Experience\n7 to 16 years of relevant experience - A Must\nCPU/SoC post-silicon validation or silicon bring-up experience.\nValidation of ARM-based multicore SoCs.\nKnowledge of virtualization, hypervisors and virtual interrupt handling.\nExperience debugging interactions among GIC, CPU low-power states, DVFS and firmware.\nAbility to convert architectural requirements into validation scenarios, stress tests and measurable coverage.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Principal Engineer", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-10-09", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Principal-Engineer_R3911-26-6", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nMicrochip AES Design team in Bangalore is looking for an experienced and motivated Design-For-Test Principal Engineer to provide test\nhardware solution for various microchip Business units. As a member of test development team, you will be responsible for understanding the\nexisting DFT test structures and clock strategy used across multiple business units and provide architectural improvements to improve test\ncoverage. The candidate should have experience with ATPG and MBIST. The candidate should have in depth knowledge of Tessent/Modus\ntool execution.\n\nRequirements/Qualifications:\n\nHands on expertise on handling DFT on hierarchical designs.\nHands on expertise on Tessent/Modus ATPG tool for DFT setup and pattern generations.\nHands on expertise on Tessent/Modus MBIST tool for MBIST hardware generation.\nHands on expertise on Tessent/Modus diagnosis tool for on-silicon debug.\nHands on expertise SCAN pattern simulations and debug.\nATPG with the pattern delivery to the test engineering team.\nSound knowledge of Scan Stitching, Scan Compression, MBIST & JTAG Techniques.\nShould have good post silicon DFT bring-up and debug experience.\nShould have a good knowledge of simulation debug and prior experience at SoC level.\nExcellent written and verbal communication skills.\nSelf-motivated team player with strong problem-solving skills to collaborate with various teams to achieve desired goals.\nExperience:\nBachelors/Masters in Electronics or equivalent degree with 9+ years of experience\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Staff Engineer, Physical Design - High Speed Interconnects", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-10-09", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Staff-Engineer--Physical-Design---High-Speed-Interconnects_R-101166", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nAbout the Role -\n\nAs a Staff Physical Design Engineer (High-Speed Interconnects), you will be responsible for the end-to-end implementation of high-bandwidth Network-on-Chip (NoC) and Uncore subsystems. \nThis is not a traditional \"siloed\" backend role; you will operate at the intersection of architecture, design and physical implementation. You will drive PPA (Power, Performance, Area) outcomes by influencing RTL structures and floorplanning strategies early in the design cycle. Your expertise in advanced process nodes and system-level data flow will be critical in delivering scalable, high-frequency IP that forms the backbone of our next-generation compute platforms.\n\nResponsibilities - What You’ll Do\nEnd-to-End Implementation: Execute the full physical design flow (RTL-to-GDSII) for complex NoC and Uncore subsystems, ensuring timing closure and routability for interconnects.\n\nArchitecture & PD Co-Design: Partner with RTL and Architecture teams to perform early-stage feasibility analysis. Identify physical bottlenecks in the microarchitecture and propose RTL restructuring, such as optimized pipelining or bus-width adjustments, to meet PPA targets.\n\nAdvanced Floorplanning: Own hierarchical partitioning and macro placement. You will define the physical blueprint for massive die areas, optimizing pin assignments and global routing tracks to minimize latency across the fabric.\n\nInterconnect Problem Solving: Solve unique NoC challenges, including long-wire RC compensation, repeater strategy for global signals, and complex clock/reset distribution across hierarchies.\n\nMethodology Innovation: Develop and refine automated flows for hierarchical implementation. You will identify gaps in existing scripts and tools to improve turnaround time and design quality across multiple technology nodes.\n\nTechnical Mentorship: Provide technical guidance to mid-level engineers, leading design reviews and establishing best practices for high-performance physical implementation.\n\nRequirements - What You’ll Bring\nDeep Experience: 7+ years of hands-on physical design experience, with a proven track record of closing complex blocks or subsystems on FinFET nodes (7nm and below).\n\nSystems-Level Mindset: Understanding of NoC designs. You should be comfortable navigating RTL and understanding how logic structures translate to physical layout.\n\nHierarchical Expertise: Proven ability to manage top-level integration, including budget constraints, hierarchical P&R and timing closure.\n\nTool Mastery: Expert-level proficiency with industry-standard EDA suites - Synopsys and/or Cadence implementation and sign-off tools.\n\nAnalytical Rigor: A data-driven approach to PPA tradeoff optimization; accompanied by a detail-oriented mindset and clear communication.\n\nEducation: BS or MS in Electrical Engineering, Computer Engineering, or a related field.\n\nWhy Join Us?\nBe part of the RISC-V movement and help define the future of computing architecture.\n\nWork on industry-leading IP adopted by top customers and shipped in high volumes worldwide.\n\nCollaborate with world-class engineers in a supportive, fast-paced, learning environment.\n\nEnjoy a culture that values innovation, ownership, and technical excellence.\n\nOur large IP portfolio offers opportunities to engineer solutions across multiple IPs and product families over time.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Sr Engineer - Physical Design", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-10-09", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Sr-Engineer---Physical-Design_R-101430", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nAbout the Role\n\nAs a Senior Physical Design Engineer, you will be a core technical contributor responsible for the physical design implementation of our next-generation IPs. In this role, you will implement RTL2GDS ensuring the architecture and design achieve their peak physical potential.\n\nWe are looking for a \"full-stack\" physical design engineer who is deeply curious about the logic they are building. You should be the type of engineer who thrives at the convergence of microarchitecture and physical layout, enjoying the challenge of analyzing how an architectural datapath affects timing closure and how to push the boundaries of Power, Performance, and Area (PPA).\n\nKey Responsibilities\nEnd-to-End Implementation: Own and execute the complete physical design flow (Synthesis, Floorplanning, P&R, Signoff) for major sub-systems and diverse IP blocks, ensuring they meet or exceed aggressive targets for PPA.\n\nArchitectural & RTL Co-Optimization: Partner with RTL and Architecture teams from early-stage design to signoff. Identify physical and structural bottlenecks early—such as routing congestion in complex crossbars, dynamic power hot-spots in execution units, and interconnect span limits—and collaborate on microarchitectural or structural solutions to overcome them.\n\nCross-Product PPA Execution: Apply advanced physical design techniques customized to the unique demands of different design classes. This includes implementing extreme leakage/dynamic power efficiency for edge IPs, rigorous reliability and redundancy structures for automotive standards, or maximizing bandwidth and throughput for high-speed fabrics.\n\nTechnical Ownership: Take ownership of complex implementation challenges, contribute to the improvement of flows, methodology, and automation, and assist in mentoring junior engineers while promoting best practices.\n\nRequirements - What you’ll bring\n\nExperience: 4+ years of hands-on physical design experience on advanced process nodes (7nm and below preferred).\n\nIP Implementation Expertise: Solid experience with the physical implementation of at least one major IP domain (such as CPUs, high-speed interconnects/fabrics, cache/memory hierarchies, or specialized accelerators) and a proven ability to adapt to new logic classes.\n\nCo-Design Mindset: Understanding of the interplay between physical implementation and microarchitecture, coupled with the curiosity to learn and adapt to different product architectures.\n\nTool Proficiency: Strong proficiency with industry-standard EDA tools—specifically Synopsys (Fusion Compiler, PrimeTime) and/or Cadence (Innovus, Tempus) implementation and sign-off suites.\n\nAdvanced Problem Solving: Ability to debug complex physical design challenges, including structural timing violations, routing congestion etc. with minimal supervision.\n\nEducation: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.\n\nWhy join us?\n\nIn this role, you will play a pivotal part in driving aggressive PPA optimizations across significant design sections, operating at the critical intersection of physical layout, RTL design, and hardware architecture. You will have the autonomy to make a substantial impact across our entire product portfolio—from highly efficient IoT cores and dense memory systems to demanding high-performance platforms. We offer a direct path for technical growth, allowing you to collaborate with world-class engineers in a supportive, fast-paced, and learning-rich environment.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Integration Design Engineer", "company": "Lattice", "location": "Manila, Philippines", "date_posted": "2026-10-09", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Manila-Philippines/Design-Eng-3_R-103205", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nThe position is for Integration Design Engineer at Lattice Semiconductor (PH) Corp. The design engineer will be part of the Silicon Integration Team and will mainly be responsible for the integration of different IPs to build the chip utilizing both custom and digital design flows.\n\nAccountabilities: \nDesign engineer will generally be responsible for the integration of different IPs to build the fullchip. This extends to the delivery of all the corresponding models, views and collaterals to different functional teams and the completion of all the required checks and simulations for sign-off.\nCollaborate with Architecture, SW, IP Design, and Physical Design Teams to generate fullchip logical floorplan. Generate fullchip behavioral model by integrating the various IP models in alignment to the logical floorplan and the requirements of SW and Verification teams. Responsibility extends to the delivery of fullchip synthesized netlist and fullchip schematics.\nDesign and implement (custom and digital) density-specific IPs (such as clock networks) and sectors (group of IPs) suitable for fullchip integration. Perform all flows and checks such as elaboration/compilation, synthesis, equivalence, DFT, timing closure (spice simulation and/or STA), power and performance analysis.\nWork closely with other functional teams to debug and resolve issues.\nPerform fullchip tapeout-gating audits such as Electromigration and IR drop (EMIR) Analysis, Netlist Electrical Rule Checks (NetERC), Power Distribution Network (PDN) Extraction, Simultaneously Switching Outputs (SSO) simulations, and ESD checks.\n\nRequired Skills:\nBS or MS in Electronics/Computer/Electrical Engineering\nAt least 5 years of proven in-depth experience in Custom and Digital Design Implementation. Expertise in Verilog and System Verilog is a must.\nExperience in FPGA/CPLD design and integration is a plus.\nExpertise/Solid understanding of the following:Custom Design Flow\nSemiconductor principles and transistor-level analysis\nIndustry standard tools for schematic and layout Entry (Cadence Virtuoso)\nCharacterization, performance, and power simulations (spice is preferred)\nDigital Design FlowRTL coding and verification\nLint Check, Elaboration/Compilation, Synthesis, Equivalence Check, SDC, and STA using industry standard tools (Xcelium, Genus, Innovus, Tempus)\nKnowledge in DFT flow and ATPG generation is an advantage.\n\nExperience in IP and Fullchip functional verification is a plus.\nExpertise in coding/scripting (Perl, TCL, Shell, Skill, Phyton)\nExperience in project leadership and product development cycle (planning, resourcing, tapeout, silicon characterization/validation) is a plus.\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nPhilippinesLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Design Verification Engineer 2", "company": "Lattice", "location": "Pune, India", "date_posted": "2026-10-09", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Pune-India/Design-Verification-Engineer-2_R-103075", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nLattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n \nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\n \nResponsibilities\n \nInviting candidates with a passion for invention and self-challenge. This position gives you an opportunity to be a part of one of the most cutting edge and key projects that Lattice’s Silicon Engineering team has embarked upon to date. As part of our team, you will have the opportunity to contribute to verifying complex FPGAs. This team will allow you to integrate multiple sophisticated IP level Design and Verification (DV) environments, craft highly reusable best-in-class UVM TB, implement effective coverage driven and directed test cases, deploy new tools and implement methodologies to improve quality of tape-out readiness. By collaborating with other product development teams across Lattice, you can push the industry boundaries of what FPGA systems can do and improve the product experience for our customers across the world! You will be able to learn all aspects of a FPGA, different types of SOC architecture, many highspeed layered protocols, industry’s standard methodologies on low power architecture, best in class DV methodology, verification on accelerated platforms, FW-HW interactions, complexities of FPGA and SOC debug architecture, etc. You'll be at the center of the design verification effort within our silicon design SOC verification team responsible for crafting and productizing state-of-the-art FPGAs. This position requires someone comfortable will all areas of FPGA design verification engineering. Someone that thrives in a dynamic multi-functional organization and is not afraid to take on challenges and solve complex problems using state of the art verification methodologies.\n \nRequired Skills\nBS/MS Electrical Engineering, Computer Science, Computer Systems Engineering, or equivalent degree\nAt least 3+ years DV experience in  IP/SoC verification\nProven track record of working full ASIC verification from concept to tape-out\nAdvanced knowledge of System Verilog and UVM methodology\nHands-on verification experience in verifying IPs like PCIExpress or Ethernet or USB in UVM environment will be preferred\nHands-on verification experience in verifying IPs using AMBA bus architecture in UVM environment.\nExposure on working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification will be plus.\nAbility to create IP level module and sub-system verification plans, TBs, portable test benches, sequences, verification infrastructure.\nDevelop UVM based highly reusable test benches for IP verification and achieved targeted coverage numbers.\nWork with design, architecture, SW, FW, and IP delivery teams to efficiently integrate and verify overall FPGA design.\nShould be a great team member with excellent communication and problem-solving skills and the desire to seek diverse challenges.\n\nLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.\n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1000+ strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.\n\n#LI-DNP\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Analog Layout Principal Engineer", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-10-09", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Analog-Layout-Principal-Engineer_2604997", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nAs an Analog Layout Principal Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of a small analog team making a big impact on this organization. Additionally, Marvell has the perfect size and scale for you to learn several aspects of engineering that will be new to you, but also have the time and freedom to dive deep into the details of your specialization on most projects.\nWhat You Can Expect\nDesign and develop complex analog, mixed-signal, and custom layouts independently using Cadence Virtuoso and similar EDA tools across advanced nodes (deep sub-micron, FinFET, GAA). \nDrive end-to-end physical verification of closure, resolving DRC, LVS, ERC, and antenna violations within project timelines. \nDrive layout architecture, shielding, isolation, EM/IR optimization, and parasitic management. \nOwn layout planning from floor planning to final tapeout. \nCoordinate across design, verification, package, and physical implementation teams for successful project execution. \nSupport tapeout activities and resolve critical design issues under aggressive schedules. \nLead technical discussions, layout reviews, and contribute to knowledge sharing and process improvement initiatives. \nServe as the technical focal point for domain expertise within the team. \nOwn cluster, including high-level integration and top-level layout decisions. \nProvide critical layout feedback influencing circuit quality, performance, and architecture. \nApply strong engineering judgment to select optimal layout techniques across projects. \nRepresent the layout team in cross-functional discussions and decision-making forums. \nLead big teams or coordinate multiple macro owners to drive project convergence. \nAct as the key interface between layout and design teams, ensuring clear communication and alignment. \nStay updated with evolving semiconductor technologies, tools, and methodologies. \n\nWhat We're Looking For\nBachelor's or master's degree (BE/B.Tech or MS/M.Tech) in Electronics & Communication, Electrical & Electronics, or a related field from a reputed institution. \n15+ years of strong experience in high-speed analog, mixed-signal, and custom layout design. \nBroad exposure across multiple projects, technology nodes, and layout architectures. \nDeep understanding of electrical engineering fundamentals and layout behavior across advanced nodes. \nProven experience in handling complex and critical IPs with end-to-end ownership. \nExpert-level proficiency in EDA tools, with the ability to influence layout flows and methodologies. \nDemonstrated ability to introduce innovative and optimized layout solutions for complex designs. \nStrong track record of delivering high-speed and/or precision analog layouts across multiple process technologies. \nExpertise in critical layout techniques such as device matching, signal flow optimization, clock routing, shielding, parasitic minimization, biasing, and robust power routing. \nSolid understanding of reliability considerations including EM/IR, latch-up prevention, ESD protection, and power planning. \nStrong communication and collaboration skills, with the ability to present to global teams and effectively engage stakeholders across organizational levels. \n\nThis role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.\nAdditional Compensation and Benefit Elements\nWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\n\nInterview Integrity \nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\n\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\n\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n\n#LI-MN1", "jd_status": "stored"}, {"title": "R&D Engineer, Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-09", "url": "https://careers.synopsys.com/job/bengaluru/r-and-d-engineer-staff-engineer/44408/101731559136", "is_hardware": true, "platform": "talentbrew", "jd_text": "Alternate Job TitlesLibrary Validation Engineer\nLibrary Development and Release Engineer\nPower Library Modeling Engineer\nSemiconductor Library Engineer\nIP Library Validation Staff Engineer\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years building and validating semiconductor libraries that have to work in production, not just pass a test suite. You know that a library view delivered without proper power modeling or incomplete validation creates a cascade of problems for design teams three months later, and you are the kind of engineer who catches those gaps before they ship. You think in terms of flows, not just files. When you see a library deliverable, you are already mapping the characterization chain, the build dependencies, the APL model generation steps, and the release checkpoints that need to happen for it to land correctly.\nDebugging does not intimidate you. Whether it is a SPIPROF model mismatch, a CDEV extraction issue, or a release flow that broke overnight, you dig in, trace the root cause, and fix it with clarity. You automate the repetitive parts because you have better things to do than run the same validation script manually for the tenth time. Python and Shell are tools you reach for without thinking, and you have built enough automation to know what makes a script maintainable versus what makes it a liability six months later.\nAt Synopsys, you will work on libraries and power models that enable real chips to tape out. The work is technical, the standards are high, and what you validate matters.\nWhat You'll Be Doing\nCreate and validate library views across multiple formats and technology nodes to support diverse design and signoff requirements\nDevelop, validate, and package library deliverables for internal teams and external customer releases, ensuring completeness and correctness\nGenerate and validate Apache Power Library models including SPIPROF, Current, CDEV, and PWCDEV for power integrity and signoff flows\nExecute comprehensive quality checks across library builds, APL models, and release packages to catch issues before they reach downstream users\nDebug and resolve complex issues in characterization flows, APL model generation, build validation, and release processes\nBuild and maintain Python and Shell automation to improve validation coverage, reduce manual effort, and increase release velocity\nCollaborate with characterization, design, CAD, QA, and release teams to align on requirements, troubleshoot blockers, and deliver on schedule\nThe Impact You Will Have\nEnable design teams and customers to meet tape-out schedules by delivering high-quality, validated library deliverables on time\nReduce downstream design issues by catching library and APL model inconsistencies early through rigorous validation\nAccelerate release cycles by building automation that replaces manual validation steps and improves flow reliability\nImprove power signoff accuracy by delivering validated SPIPROF, CDEV, and PWCDEV models that reflect real silicon behavior\nDrive quality improvements across the library development pipeline by identifying gaps in validation coverage and closing them\nSolve customer-reported library and APL issues quickly, reducing support escalations and maintaining customer trust\nContribute to continuous improvement efforts that make validation flows faster, more robust, and easier to maintain\nWhat You'll Need\nBachelor's or Master's in Electronics Engineering, Computer Science, or equivalent practical experience\n5+ years of hands-on experience in library development, validation, or characterization for semiconductor IP or EDA flows\nStrong proficiency in Python and Shell scripting for automation, validation, and workflow orchestration\nDeep understanding of library views, formats, and their role in digital and custom design flows\nExperience with Apache Power Library models such as SPIPROF, Current, CDEV, or PWCDEV is a strong plus\nSolid debugging skills across complex multi-step flows involving characterization, model generation, and release processes\nAbility to work across teams and communicate technical issues clearly to design, CAD, QA, and release stakeholders\nWho You Are\nYou can trace a library issue from a customer report back through the build flow, characterization run, and source data without getting lost\nYou write automation that other engineers can actually use, not just scripts that work on your machine\nYou know when to escalate and when to dig deeper, and you do not let blockers sit unresolved while you wait for someone else to fix them\nYou can explain a complex APL model discrepancy to a design engineer in two minutes without losing the technical detail that matters\nYou care about the quality of what ships, not just whether it passed the checklist\nYou are comfortable working in a global team across time zones, asynchronously when needed and in real time when it helps\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Technical Staff Engineer-Design", "company": "Microchip", "location": "Germany - Neu-Ulm", "date_posted": "2026-10-09", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/Germany---Neu-Ulm/Technical-Staff-Engineer-Design_R790-26", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nThe Wireless Solutions Group is seeking an experienced Design Engineer for our next generation high-performance, low-power wireless SoC and attach solutions. In this role, you will be responsible for the design of System-on-Chip (SOC) solutions for wireless applications. You will collaborate closely with cross-functional teams, including verification, analog, validation, and software engineers, to deliver high-quality products. Successful candidates require strong collaboration across sites and functions, excellent communication, and the ability to thrive in a fast-paced, dynamic environment.\n\nKey Responsibilities:\nContribute to SOC design from concept to tape-out.\nImplement SOC designs according to micro-architecture specifications and design documentation, performing RTL coding, synthesis, timing analysis, and executing the SOC design flow to ensure IC qualification meets required standards.\nCollaborate with verification teams to ensure thorough design verification according to test plans.\nWork with physical design teams to ensure successful integration and implementation.\nParticipate in design reviews to ensure compliance with design standards and project requirements.\nSupport the validation team in qualifying silicon ICs and debugging potential issues.\nContribute to the development and optimization of low-power design techniques and power estimation methodologies.\nInterfacing with external vendors and IP sources to resolve problems.\nAbility to work well in a team and excellent problem solving, verbal and written communication skills.\nWorking with members from international design and implementation teams.\n\nRequirements/Qualifications:\n\nBachelor's degree in computer engineering, electrical engineering, or related field.\nMinimum 12+ years of experience in digital SOC design, with a focus on low-power design.\nProficient in RTL design (Verilog/System Verilog), Low-power design, synthesis, timing constraint (SDC) and timing analysis.\nExperience with ASIC design flow including LINT, Formal, CDC/RDC, power estimations, MBIST/DFT concepts, and low-power design techniques.\nStrong understanding of SOC architecture (ARM/MIPS), bus protocols (AMBA, AXI, etc.), and peripheral IPs (USB, Ethernet, I2C, SPI, etc).\nExperience with Bus Matrix design.\nExperience with script Language such as TCL, Perl, and Python.\nExcellent English reading, writing and verbal communication skills.\nStrong analytical and problem-solving skills.\nWe are looking for candidates who are self-motivators, energetic, and team players.\n\nPreferred Skills and Experience:\nMaster’s degree in computer engineering, electrical engineering, or related field.\nKnowledge of Bluetooth/BLE/Wi-Fi communication theory and standard specifications.\nKnowledge of security features and principles of functional safety–compliant design.\nExperience with verification methodologies (UVM/OVM).\nExperience with validation methodologies, including debugging on FPGA and silicon IC boards.\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Sr. Memory Layout Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-10-09", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Sr-Memory-Layout-Design-Engineer_R026848", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nJob Requirements:\n- Minimum 8 years of experience with strong layout knowledge\n- Bachelor's degree required.\n- Proficiency in using Cadence tools (virtuotso layout, layotu XL, Cadence schematic capture, and verification tools - CALIBRE & Hercules).\n- Strong layout knowledge in submicron processes (e.g. 7nm, 5nm, 3nm, 2nm).\n- Experience in digital layout (Standard cell, Memory, I/O); analog layout experience is a plus.\n\nJob Description:\n- Understand and apply layout guidelines, new process rules, and technical requirements for good quality layout.\n- Manage scheduling, timelines, and layout floor-planning.\n- Responsible for start to end deliverables with quality within the planned schedule.\n- Adapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the SOC/library team.\n- Able to think and help in layout scripting and automation\n\nSkill Set (Memory):\n- Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes.\n- Experience with Cadence Layout tools (VIRTUOSO XL, VXL, or EXL) and CALIBRE verification tools.\n- Proficiency in floor-planning, hierarchy layout, and chip integration.\n- Understanding of memory architecture, RC requirement, ability to plan signal and power, based on the layout guidelines\n- Knowledge of AI, automation in layout, Script Programming and SKILL Programming\n- Ability to lead, train junior engineers, and manage projects effectively.\n- Good knowledge of memory layout topology; experience with memory compilers is a plus.\n- Ability to lead new technology reviews to document layout methodologies, flows, and guidelines.\n- Self-reliant with the ability to work both independently and collaboratively.\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Electrical Engineer", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2026-10-09", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/Electrical-Engineer_R2628394", "is_hardware": true, "platform": "workday", "jd_text": "Who We Are\n\nApplied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI and accelerating the commercialization of next-generation semiconductor chips. Join us and push the boundaries of materials science and engineering in a company at the foundation of the electronics industry. The work we do together advances the world’s technology.\n\nWhat We Offer\n\nLocation:\nBangalore,IND\nYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. \n\nAt Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. \n \n \nAs an Electrical Engineer, you are responsible for designing, modifying, and troubleshooting electrical or electronic engineering assemblies, layouts, schematics, and drawings to advance the equipment that supports our technology. Using your technical experience and critical thinking skills, you will perform engineering analysis, generate test reports, develop innovative solutions, and create documentation for product releases. You will also coordinate the procurement and assembly of components, identify sources of critical parts, and resolve technical issues to ensure peak performance. \n \nRole Responsibilities: \nDesign or modify electrical or electronic engineering assemblies, layouts, schematics, drawings, or specifications of difficult scope \n\nIdentify and troubleshoot a variety of complex electrical problems with limited supervision \n\nDefine, coordinate, perform and generate engineering test reports with limited supervision \n\nPerform engineering analysis of difficult scope with limited supervision \n\nTechnically lead or execute engineering projects, including the development of key suppliers \n\nImplement concepts for a variety of complex product issues and electrical solutions of difficult scope \n\nGenerate electrical product specifications; specify and review engineering documentation \n\nServe as a resource for junior colleagues; lead project teams, as needed\n\nClearly communicate difficult or sensitive information; build consensus \n\nMinimum Qualifications: \nBachelor’s degree\n\n4-7 years of experience in a related field\n\nPreferred Qualifications: \nStrong knowledge of industry best practices, key business drivers, competition in the marketplace, and how your area of expertise integrates with others  \n\nDemonstrated leadership skills to lead small projects as needed  \n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nAssignee / Regular\nTravel:\nYes, 10% of the Time\nRelocation Eligible:\nYes\n\nApplied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "Experienced Engineer - ASIC Backend Synthesis", "company": "Ericsson", "location": "Bangalore,Karnataka,India", "date_posted": "2026-10-08T17:16:16+00:00", "url": "https://jobs.ericsson.com/careers/job/563121776493670", "is_hardware": true, "platform": "eightfold", "jd_text": "Grow with us\n\nJoin Ericsson’s cutting-edge journey to shape the future of 5G networks! As an Physical Synthesis Engineer, you’ll work on pioneering digital ASIC designs vital to Ericsson’s mobile network infrastructure. Our team, responsible for the final critical stage of chip design before fabrication, thrives on Lean and Agile principles, promoting close collaboration, daily progress-sharing, and continuous improvement. If you’re passionate about advanced technology and ready to make a meaningful impact in telecom, this role is crafted just for you. \nAt Ericsson, we support your growth, offering opportunities to advance your skills while contributing to game-changing 5G/6G technologies. Here, you’ll find a supportive, innovative environment focused on quality, teamwork, and career development. Join us and help shape the future of telecom! \nWe are hiring a Physical Synthesis Engineer to own the synthesis flow and constraint development on high-performance, low-power SoC designs. Your primary focus will be physical-aware synthesis, floorplan-driven netlist optimization, and QoR closure — while also contributing to static timing analysis (STA) signoff as well. You will work closely with RTL design, place-and-route, and DFT teams throughout the full design cycle. \n\nWhat you will do:\n\nPhysical-Aware Synthesis (PAS) \nExecute physical-aware and floorplan-driven synthesis flows to minimize post-layout timing and congestion surprises. \nIntegrate synthesis with P&R tools for early physical feedback loops — congestion-aware optimization, placement-aware buffering, and pre-CTS timing. \nCollaborate with P&R engineers on DEF/floorplan hand-off; iterate on netlist quality to reduce downstream ECO effort. \nPerform flat and hierarchical synthesis for large designs; manage partitioning and interface timing budgets. \nPerform formal or equivalence check on the netlist at block or top level. \nQoR & Optimization \nTrack and report key QoR metrics — timing slack, area, cell count, power — across design iterations and process corners. \nIdentify and resolve synthesis bottlenecks: critical path restructuring, datapath optimization, and register retiming. \nProvide RTL coding guideline feedback to design teams to improve synthesizability and QoR from the source. \nManage technology library characterization inputs: Liberty (.lib), LEF, and UPF/CPF for multi-voltage designs. \nOwn synthesis QoR sign-off checklist and contribute to tape-out readiness reviews. \nStatic Timing Analysis  \nRun block-level and full-chip STA using PrimeTime (PT) for timing analysis across PVT corners. \nSupport MMMC (Multi-Mode Multi-Corner) timing closure; analyze and triage timing violations with P&R and synthesis teams. \nReview and validate SDC constraints developed during synthesis against post-layout STA results. \nContribute to clock domain crossing (CDC) checks and timing exception audits during signoff. \n\nThe skill you bring:\n\n5+ years in physical synthesis or logic design implementation \nExpert-level use of Fusion Compiler \nStrong SDC constraint authoring and management skills \nExperience with physical-aware synthesis flows and P&R hand-off \nWorking knowledge of STA (PrimeTime) \nProficiency in Tcl; Python scripting a strong plus \nAt least one tape-out on 7nm or below\n\nNice to have:\n\nFamiliarity with low-power methodologies (UPF/CPF, multi-Vt, clock gating) \nUnderstanding of PTPX-based power analysis flows \nDFT synthesis experience (scan, BIST, boundary scan) \nFamiliarity with congestion-aware and timing-driven P&R closure \nEDA Tools & Environment \nDesign Compiler, Fusion Compiler, Synopsys PrimeTime, Formality, Tcl/Python.\n\n.\n\n“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”\n\nWhat happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.We encourage you to consider applying to jobs where you might not meet all the criteria. We recognize that we all have transferrable skills, and we can support you with the skills that you need to develop.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.\n \nPrimary country and city: India (IN) ||\nJob details: Developer\nJob Stage: Job Stage 5\nPrimary Recruiter: Ashwini Manda\nHiring Manager: Govinda Raju", "jd_status": "stored"}, {"title": "Staff Test Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-08T11:48:05.739000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000154416319-staff-test-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "The Embedded Processing organization is seeking a Staff Test Engineer to define and deliver robust, cost-effective production test solutions for new semiconductor products from concept through mass production and sustaining support. In this lead role, the Staff test engineer owns the test strategy, ATE test development, test hardware, test validation, qualification and production release, test-cost optimization and industrial activities.\nKey Responsibilities\nDefine the production test strategy and manufacturing test flow for assigned products including tester selection\nOwn the test planning\nProvide testability input to DFT, DFM and design reviews before tapeout\nDefine detailed test plan covering ATE implementation\nLead test hardware requirements and development, including loadboards, probe cards, sockets, interface hardware and related fixtures.\nDevelop and review ATE test programs, test methods, production patterns and supporting software.\nLead first-silicon ATE bring-up, test program debug and sample generation.\nExecute ATE characterization across process, voltage and temperature conditions in alignment with the product characterization plan.\nSupport qualification and customer sample generation by developing dedicated test programs\nIdentify test coverage gaps and potential escapes, then implement containment and permanent corrective actions\nRelease qualified test software and hardware into production and support OSAT manufacturing start-up.\nReview and sign off test deliverables\nDrive production ramp readiness reviews and close test-related release risks.\nReduce test time through method optimization, improved sequencing, multisite efficiency and instrumentation utilization.\nSupport customer-return and RMA investigations by reproducing failures and assessing production test coverage.\nTechnical Leadership\nProvide technical direction, sign off reviews\nLead technical decisions and risk resolution across Design, Product Engineering, Operations, suppliers and OSAT teams including DFX topics\nFully independent and recognized as subject-matter-expert\nInfluence cross-functional teams without direct authority and communicate clearly to the stakeholders.\n\nBachelor's or Master's degree in Electronics Engineering, Electrical Engineering or a related discipline.\nAt least 8+ years of relevant semiconductor test engineering experience spanning NPI, characterization, qualification, production release and sustaining support.\nStrong knowledge of semiconductor production test methodologies and practical experience developing ATE test solutions.\nExperience with Advantest V93000 or equivalent ATE platforms.\nExperience developing production test solutions for RF-SOC devices\nExperience with test hardware development, including loadboards, probe cards, sockets and handler/prober interfaces.\nStrong programming skills\nExperience driving manufacturing release at OSATs\nExperience with data-analysis and yield-management tools such as JMP, Spotfire or equivalent platforms.\nStrong analytical, technical leadership, planning, communication and problem-solving skills.\n\nWe recognise and appreciate the value and contributions of individuals with diverse backgrounds and experiences and welcome all qualified individuals to apply. Equal Opportunity Employer.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Test Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-08T11:28:05.119000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000154412314-senior-test-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Position Summary:\nThe Embedded Processing organization is seeking a Senior Test Engineer to define and deliver robust, cost-effective production test solutions for new semiconductor products from concept through mass production and sustaining support. In this senior role, the Senior test engineer owns the test strategy, ATE test development, test hardware, test validation, qualification and production release, test-cost optimization and industrial activities.\nKey Responsibilities:\nDefine the production test strategy and manufacturing test flow for assigned products including tester selection\nOwn the test planning\nProvide testability input to DFT, DFM and design reviews before tapeout\nDefine detailed test plan covering ATE implementation\nLead test hardware requirements and development, including loadboards, probe cards, sockets, interface hardware and related fixtures.\nDevelop and review ATE test programs, test methods, production patterns and supporting software.\nLead first-silicon ATE bring-up, test program debug and sample generation.\nExecute ATE characterization across process, voltage and temperature conditions in alignment with the product characterization plan.\nSupport qualification and customer sample generation by developing dedicated test programs\nIdentify test coverage gaps and potential escapes, then implement containment and permanent corrective actions\nRelease qualified test software and hardware into production and support OSAT manufacturing start-up.\nReview and sign off test deliverables\nDrive production ramp readiness reviews and close test-related release risks.\nReduce test time through method optimization, improved sequencing, multisite efficiency and instrumentation utilization.\nSupport customer-return and RMA investigations by reproducing failures and assessing production test coverage.\n\nBachelor's or Master's degree in Electronics Engineering, Electrical Engineering or a related discipline.\nAt least 6 years of relevant semiconductor test engineering experience spanning NPI, characterization, qualification, production release and sustaining support.\nStrong knowledge of semiconductor production test methodologies and practical experience developing ATE test solutions.\nExperience with Advantest V93000 or equivalent ATE platforms.\nExperience developing production test solutions for RF-SOC devices\nExperience with test hardware development, including loadboards, probe cards, sockets and handler/prober interfaces.\nStrong programming skills\nExperience driving manufacturing release at OSATs\nExperience with data-analysis and yield-management tools such as JMP, Spotfire or equivalent platforms.\nStrong analytical, technical leadership, planning, communication and problem-solving skills.\n\nWe recognize and appreciate the value and contributions of individuals with diverse backgrounds and experiences and welcome all qualified individuals to apply. Equal Opportunity Employer.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Specialist IP Core - GSD", "company": "Ericsson", "location": "Pune,Maharashtra,India", "date_posted": "2026-10-08T11:21:52+00:00", "url": "https://jobs.ericsson.com/careers/job/563121777358454", "is_hardware": true, "platform": "eightfold", "jd_text": "Join our Team\n\nAbout this opportunity:\nThe Network Engineer performs design, optimization and audit of a network to meet the customer requirements. The role is focused on executing design, audit and optimization services, where the network engineer is responsible for part of the solution and part of the service process. The Network Engineer is responsible to upkeep time, performance and quality according to Ericsson requirements and Customer contract.\n.What you will do:\nAccountable for day-to-day delivery of the assigned project towards the MA.\nCustomer facing role\nAnalyzing & troubleshooting different network related issues\nInteract with internal and external stakeholders for delivery execution\nExcellent communication skills\nTroubleshoots network problems and implements corrective action\nResponsible for IP Networks Design, Deployment/configuration, troubleshooting, root cause analysis and workaround / solution definition activities for the assigned project.\nAnalysis of KPIs, ensure all project KPI(s) are met as per agreed targets/SLA’s.\nOptimization of MPBN and ISP networks.\nSupport for field tests as required for new features and/or HW.\nThe skills you bring:\n7-9 years industry experience with excellent exposure on Design, Planning, Deployment & Troubleshooting in IP networks / MPBN Backbone on Telecom / ISP based networks.\nExtensive hands-on experience on IP routing protocols / technologies L2/L3 IP/MPLS VPNs, VPLS & EVPN, IGPs (All) on Cisco & Juniper routers.\nExcellent understanding & experience on Routing Protocols like OSPF, BGP, IS- IS, MPLS, Traffic Engineering, QoS (Quality of Service) in IP networks.\nGood hands-on experience in Configuration of IP Networks (Routing/Switching) – Cisco, Juniper, Ericsson Network / Security Devices.\nGood hands-on experience in Troubleshooting of IP Networks – Network related issues.\nShould have hands-on experience with Cisco, Ericsson & Juniper IP products.\nPrepares High-level design / Low-level design (HLD/LLD) independently.\nIP Professional Certifications (CCNP / Cisco Encore) on Cisco/ Juniper (JNCIP) is required.\nGood understanding of Segment routing.\nStrong Technical and Communications skills with excellent conceptual knowledge.\nExcellent verbal and written communication skills.\nOpen to work for a Global operator with rotational night shifts.\nSubject matter expertise on operator network and understanding.\nSuccessful track record and strong background in large-scale network operational organizations.\nExcellent customer handling skills.\nAbility to learn the working of new nodes which are added in the network.\nExperience on automation & scripting would be a plus.\nAbility to guide and support other engineers\nProfessional IP Certification. (CCNP, JNCIP)\n\nWhy join Ericsson?At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.\n \nWhat happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.\n \nPrimary country and city: India (IN) || Noida\nReq ID: 792116", "jd_status": "stored"}, {"title": "Senior Engineer IP Core - GSD", "company": "Ericsson", "location": "Pune,Maharashtra,India", "date_posted": "2026-10-08T11:20:33+00:00", "url": "https://jobs.ericsson.com/careers/job/563121777358444", "is_hardware": true, "platform": "eightfold", "jd_text": "Join our Team\n\nAbout this opportunity:\nrequirements. The role is focused on executing design, audit and optimization services, where the network engineer is responsible for part of the solution and part of the service process. The Network Engineer is responsible to upkeep time, performance and quality according to Ericsson requirements and Customer contract.\nWhat you will do:\nAccountable for day-to-day delivery of the assigned project towards the MA.\nCustomer facing role\nAnalyzing & troubleshooting different network related issues\nInteract with internal and external stakeholders for delivery execution\nExcellent communication skills\nTroubleshoots network problems and implements corrective action\nResponsible for IP Networks Design, Deployment/configuration, troubleshooting, root cause analysis and workaround / solution definition activities for the assigned project.\nAnalysis of KPIs, ensure all project KPI(s) are met as per agreed targets/SLA’s.\nOptimization of MPBN and ISP networks.\nSupport for field tests as required for new features and/or HW.\nThe skills you bring:\n5-7 years industry experience with excellent exposure on Design, Planning, Deployment & Troubleshooting in IP networks / MPBN Backbone on Telecom / ISP based networks.\nExtensive hands-on experience on IP routing protocols / technologies L2/L3 IP/MPLS VPNs, VPLS & EVPN, IGPs (All) on Cisco & Juniper routers.\nExcellent understanding & experience on Routing Protocols like OSPF, BGP, IS- IS, MPLS, Traffic Engineering, QoS (Quality of Service) in IP networks.\nGood hands-on experience in Configuration of IP Networks (Routing/Switching) – Cisco, Juniper, Ericsson Network / Security Devices.\nGood hands-on experience in Troubleshooting of IP Networks – Network related issues.\nShould have hands-on experience with Cisco, Ericsson & Juniper IP products.\nPrepares High-level design / Low-level design (HLD/LLD) independently.\nIP Professional Certifications (CCNP / Cisco Encore) on Cisco/ Juniper (JNCIP) is required.\nGood understanding of Segment routing.\nStrong Technical and Communications skills with excellent conceptual knowledge.\nExcellent verbal and written communication skills.\nOpen to work for a Global operator with rotational night shifts.\nSubject matter expertise on operator network and understanding.\nSuccessful track record and strong background in large-scale network operational organizations.\nExcellent customer handling skills.\nAbility to learn the working of new nodes which are added in the network.\nExperience on automation & scripting would be a plus.\nAbility to guide and support other engineers\nProfessional IP Certification. (CCNP, JNCIP)\n\nWhy join Ericsson?At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.\n \nWhat happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.\n \nPrimary country and city: India (IN) || Noida\nReq ID: 792113", "jd_status": "stored"}, {"title": "IP Design Lead - Sr Staff", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-08T11:06:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92150/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. SMTS SILICON DESIGN ENGINEER THE PERSON:  You have a passion for modern, complex processor architecture, digital design as well as verification/design quality. You are a team player who has excellent communication skills, strong analytical & problem-solving skills and are willing to learn and ready to take on problems. A global mindset and ability to work in a multi – site environment are keys to being successful in this role. KEY RESPONSIBILITIES:  RTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design Architect and design of power management features, cache, coherency. Design optimization for implementing power efficient IP, implementing the RTL using low power techniques Responsible for the inter IP integration issues resolution Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem. Work closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design Architecting, micro-architecting and documentation of the design features Lead design team from all aspects of the RTL deliverables. Mentor the junior members of the RTL team to meet the team goals Represents AMD to the outside technical community, partners and vendors Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion. PREFERRED EXPERIENCE: 12+ years of experience in Digital IP/ASIC design and Verilog RTL development Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification. Should be well versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation. Expert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects. Should possess expertise in front-end EDA tools sign-off and its flows. Familiarity with low power design and low power flow is an added plus. Ability to program with scripting languages such as Python or Perl is a plus; Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements; Proven interpersonal skills, leadership and teamwork; Excellent writing skills in the English language, editing and organizational skills required; Skilled at prioritization and multi-tasking; Good understanding of engineering terminology used within the semiconductor industry; Good understanding of digital design concepts; Knowledge of, or experience in, functional design verification or design is highly desired. ACADEMIC CREDENTIALS: Master’s degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or VLSI design Engineering. #LI-RR1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Engineer", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-10-08T11:03:53+00:00", "url": "https://jobs.infineon.com/careers/job/563808972123710", "is_hardware": true, "platform": "eightfold", "jd_text": "We are hiring Semiconductor Test Engineer with expertise in ATE test development, DFT, and IoT connectivity products (BT/BLE/Wi-Fi). The role involves silicon bring-up, characterization, production testing, and test automation using Teradyne UltraFLEX-RF platforms, while driving product quality, yield improvement, and manufacturing readiness through close collaboration with cross-functional engineering teams.\n\nYour role\nKey responsibilities in your new role\n\nDevelop, debug, and optimize ATE test programs for IoT products, including Bluetooth (BT), BLE, and Wi-Fi solutions.\nDesign and execute characterization and production testing for Digital, Mixed-Signal, PMU, and RF blocks.\nLeverage expertise in DFT methodologies, including ATPG, PMU, BUCLK, LDOs, and trimming procedures, to improve test coverage and quality.\nDevelop semiconductor test solutions using Teradyne UltraFLEX-RF platforms; experience with UltraFLEX+ is an advantage.\nTroubleshoot ATE hardware and software issues, ensuring efficient root-cause analysis and problem resolution.\nProvide technical support and test engineering expertise to internal teams, manufacturing partners, and customers.\nDevelop automation solutions using scripting and programming languages such as Perl, Python, C, C++, Java, and Visual Basic.\nCollaborate with cross-functional teams including IP Design, Applications, DFT, Product Engineering, and Test Engineering to support successful product development and production release.\nUtilize UNIX/Linux environments and shell scripting for test automation, debugging, and workflow optimization.\nDrive continuous improvements in test quality, yield, and manufacturing efficiency.\n\nYour profile\nQualifications and skills to help you succeed \n\nStrong understanding of semiconductor device fundamentals, including Analog, Digital, and Circuit Theory.\nHands-on expertise in DFT, ATPG, PMU, BUCLK, LDO, and trimming methodologies.\nExperience with Teradyne UltraFLEX-RF / UltraFLEX+ test platforms.\nStrong programming and debugging skills for ATE test development.\nProficiency in Perl, Python, C, C++, Java, and Visual Basic.\nExperience testing Digital, Mixed-Signal, RF, PMU, and Connectivity products.\nWorking knowledge of UNIX/Linux operating systems, shell scripting, and automation tools.\nExcellent analytical, problem-solving, troubleshooting, and debugging skills.\nStrong communication and collaboration skills with the ability to work effectively in cross-functional and global teams.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nAnand Rawal", "jd_status": "stored"}, {"title": "Staff Validation Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-08T06:55:50.062000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000154355579-staff-validation-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "About the Role:\nWe are seeking a highly experienced and deeply hands-on Staff Validation Engineer to join our dynamic Silicon Validation team in Bengaluru. In this critical role, you will serve as a technical lead and mentor, driving the post-silicon validation of cutting-edge DC-DC converter products. Your profound expertise in power electronics, silicon validation methodologies, and PCB design will be instrumental in ensuring the quality, performance, and reliability of our next-generation power management ICs. You will not only lead complex validation efforts but also guide and technically ramp up junior validation engineers, fostering a culture of technical excellence.\nResponsibilities:\nTechnical Leadership & Architecture:Technical lead for post-silicon validation of complex DC-DC converter products (e.g., LDO, Buck, Boost, Buck-boost, Drivers, Controllers, etc…).\nDevelop comprehensive validation test plans and methodologies from silicon bring-up to characterization, focusing on performance, reliability, and robust operation across various load and environmental conditions (including load transient, ripple, parasitic effects).\nDrive the definition and implementation of validation techniques, including automated test development and data analysis.\n\nHands-on Validation & Debug:Perform hands-on initial silicon bring-up, debugging, and characterization on the bench using advanced lab equipment (oscilloscopes, multimeters, logic analyzers, power supplies, SMUs, spectrum analyzers, network analyzers, thermal chambers, etc.).\nLead root cause analysis of complex silicon issues, collaborating closely with design, system, and test engineering teams to drive timely resolutions.\nDevelop custom test setups, validation boards (PCB schematics and layout review), and fixtures to thoroughly test DC-DC converter performance.\n\nMentorship & Guidance:Provide technical mentorship and guidance to junior validation engineers on DC-DC converter principles, validation methodologies, test planning, debugging techniques, and best practices.\nFoster a technical learning environment within the team, promoting knowledge sharing and continuous improvement.\n\nTest Development & Automation:Define requirements for, and potentially contribute to, the development of automated test scripts and frameworks for efficient validation execution.\nContribute to the selection, adoption, and optimization of validation tools and infrastructure to improve overall team efficiency.\n\nCross-Functional Collaboration:Act as a lead between the Silicon Validation team and cross-functional teams including IC Design, System Design, Firmware, Product Engineering, and Application Engineering.\nDrive effective communication of validation findings, risks, and recommendations to various stakeholders.\n\nQuality & Compliance:Ensure validation activities adhere to rigorous quality standards, functional safety requirements, and operational protocols (e.g., ESD, safety).\nContribute to the continuous improvement of validation processes (e.g., SWIFT process adoption) and documentation standards.\n\nRequired Skills & Experience:\n9+ years of extensive, hands-on experience in Electrical/Electronic Post-Silicon Validation, with a significant focus on DC-DC converters and power management ICs.\nStrong technical experience in DC-DC converter topologies (e.g., Buck, Boost, Buck-Boost, LDOs, Gate Drivers), control schemes, and their critical performance parameters (efficiency, ripple, load transient, stability, EMI/EMC).\nGood proficiency in PCB schematics, layout review, and design considerations for high-frequency, high-current power circuits. Experience with validation board design is a significant plus.\nExpert of bench validation methodologies and debugging techniques. Highly skilled in using and interpreting data from lab equipment such as high-bandwidth oscilloscopes, arbitrary waveform generators, electronic loads, network analyzers, spectrum analyzers, power meters, etc.\nProven ability to perform root cause analysis of complex silicon issues and drive solutions collaboratively with design teams.\nExperience with test planning and execution for silicon validation across various corners (PVT), operating modes, and stress conditions.\nFamiliarity with industry-standard EDA tools for schematic/layout viewing, simulation analysis, and potentially test pattern generation (e.g., Cadence Virtuoso/Spectre, Siemens Calibre, Synopsys Verdi, etc.).\nExcellent communication, interpersonal, and mentorship skills.\nAbility to work effectively in a hybrid work environment with a strong presence in the Bengaluru lab.\n\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.\nWhy Join Our Team:\nThis is a unique opportunity to be a lead in our growing Silicon Validation team in India. You will play a pivotal role in bringing cutting-edge DC-DC products to market, shaping our validation methodologies, and directly contributing to the technical growth of your team members. If you are passionate about power electronics, enjoy hands-on validation, and thrive in a mentorship role, we encourage you to apply.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Physical design architecture", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-08T03:17:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92748/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. THE ROLE: The focus of this role in the AECG ASIC organization is to lead physical design architecture and flow development for next generation ASICs that meet Engineering, Business and Customer requirements. THE PERSON: AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanning and physical design flows for best in class ASIC solutions. KEY RESPONSIBILITIES: Technical Physical Design lead on AECG ASIC solutions, focused on driving the best Power, Performance, Area for customers. Work with customers and internal teams to evaluate IP choices, analyze die size and provide floorplan tradeoffs during customer acquisition phase. Provide expert guidance to physical design execution teams within AMD and with external partners to drive delivery to customer commitments. Develop technical relationships with broader AMD Design/CAD community and peers. PREFERRED EXPERIENCE: Strong understanding of development of custom ASICs for external customers. Strong background in physical design with exposure to circuit and logic design. Proven track record of delivering SOCs in process technologies 7nm and below. Expert user of P&R, Timing and Physical verification tools from top EDA vendors. Proven expertise in developing physical implementation flows as required. Ability to co-optimize and make appropriate tradeoff across architecture, front-end design, and back-end design. Experience in leading a small team of high performing individuals.   EDUCATION & EXPERIENCE: BS or MS degree in in Electrical Engineering or Computer Science. 16+years of experience in physical design role leading to an understanding of RTL to GDS development. #LI-SR4 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "RTL Design Engineer - Security /Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-08T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719198695", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nDevelop micro-architecture and RTL design for Cores related to security. Responsible for block level design.\n·  Micro architecture and enabling SW teams to use HW blocks.\n·  Running ASIC development tools including Lint and CDC.\n·  Report status and communicate progress against expectations.\n \nMinimum Qualifications\n·  Bachelor's degree in Engineering, Electronics, Computer Science, or related field.\n·  2+ years Hardware Engineering experience or related work experience.\nPreferred Qualifications\n·  10+ years of work experience in ASIC/SoC Design\n·  Experienced in RTL design using Verilog / System Verilog.\n·  Knowledge of cryptography, public/private key, hash functions, random number generator, encryption/signatures algorithms (AES, SHA, GMAC, etc.) will be a plus.\n·  Experienced in Linting, CDC and LEC.\n·  Experienced in database management flows with Clearcase/Clearquest.\n·  Ability to program effectively in Verilog, C/C++, Python, Perl\n·  Excellent oral and written communications skills\n·  Proactive, creative, curious, motivated to learn and contribute with good collaboration\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Video Design Verification - Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-08T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721415865", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field.\n\nPreferred Qualifications:\n•    Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.\n•    3+ years of ASIC design, verification, validation, integration, or related work experience.\n•    2+ years of experience with architecture and design tools.\n•    2+ years of experience with scripting tools and programming languages.\n•    2+ years of experience with design verification methods.\n Principal Duties & Responsibilities:\n•    Applies ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.\n•    Creates architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.\n•    Collaborates across teams (e.g., software architecture, hardware architecture) to develop and execute an implementation strategy that meets system requirements and customer needs.\n•    Evaluates all aspects of process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.\n•    Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable architecture and design of an individual block/SoC or IC Package.\n•    Writes detailed technical documentation for EDA/IP/ASIC projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc.  \n•    Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions).\n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Digital Design Engineer, DMTS/SMTS/MTS", "company": "Micron", "location": "Hyderabad, Telangana, India", "date_posted": "2026-10-08T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/44796674", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nKey Responsibilities\nDesign, develop, and deliver high-quality RTL for complex DRAM, memory, and mixed-signal digital blocks, driving projects from architecture and specification through implementation handoff while meeting performance, power, area, and quality targets.\nOwn front-end ASIC design activities, including RTL development, linting, CDC/RDC verification, functional validation, logic synthesis, static timing analysis (STA), timing constraint definition, and timing closure across multi-mode, multi-corner operating conditions.\nDevelop, maintain, and optimize design constraints (SDC), including clock definitions, timing exceptions, I/O constraints, UPF-based power intent, and low-power implementation methodologies to achieve optimal PPA.\nCollaborate closely with architecture, verification, circuit design, and physical implementation teams to resolve integration challenges, improve design robustness, and ensure successful product execution.\nAnalyze synthesis and timing reports, identify critical bottlenecks, and drive design improvements to meet performance, power, area, and schedule objectives.\nChip in to the development and enhancement of design methodologies, automation frameworks, and RTL-to-GDS implementation flows, improving engineering productivity, design quality, and time-to-market.\nApply strong expertise in CMOS digital and mixed-signal concepts, Verilog/System Verilog, and industry-standard EDA tools to develop scalable and reliable silicon solutions.\nChampion continuous improvement initiatives by demonstrating automation, AI-assisted engineering technologies, and generative AI tools to enhance design efficiency, collaboration, and overall engineering effectiveness.\nDemonstrate strong problem-solving, communication, and collaboration skills while mentoring peers and chipping in to a culture of technical excellence and innovation.\n\nQualifications:\nBachelor’s or Master’s degree or equivalent experience in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.\n10+ years of relevant ASIC or SoC design experience, with significant ownership of complex front-end design projects. For a principal or senior technical-lead position, 12–15+ years may be preferred.\nAdvanced proficiency in RTL design and microarchitecture development using Verilog and SystemVerilog.\nValidated ability to take designs from architecture and specification through RTL implementation, verification support, synthesis, timing closure, and implementation handoff.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Analog Design Engineer, DMTS/SMTS/MTS", "company": "Micron", "location": "Hyderabad, Telangana, India", "date_posted": "2026-10-08T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/44796702", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nKey Responsibilities\nLead the architecture, design, integration, and silicon validation of complex analog and mixed-signal circuits for advanced DRAM products, including amplifiers, comparators, references, LDOs, charge pumps, oscillators, DLLs, I/O circuits, and on-chip monitors.\nDrive development of custom analog and digital IP from concept through tape-out, silicon bring-up, and production.\nDefine architectures and design methodologies to optimize power, performance, area (PPA), reliability, yield, and manufacturability.\nLead verification, modeling, parasitic analysis, silicon correlation, and design signoff across PVT and reliability corners.\nGuide physical implementation, including floorplanning, matching, placement, routing, and reliability-aware layout practices.\nCollaborate with Product, Process, Test, Probe, Assembly, and Manufacturing teams to ensure successful product qualification and high-volume production.\nDrive design quality, standardization, and continuous improvement through advanced CAD, modeling, automation, and verification methodologies.\nMentor and develop engineering talent while providing technical leadership across projects and product generations.\nDrive innovation through reusable IP development, patents, technology roadmaps, and differentiated circuit architectures.\nLeverage engineering tools powered by AI and agentic AI workflows to improve build efficiency, accelerate verification, optimize PPA, and reduce product development cycle time.\nQualifications\n10+ years of experience in analog and mixed-signal IC design, with significant expertise in advanced memory products such as DRAM.\nProven track record in the development, inventing, combination, silicon validation, and production of complex analog and mixed-signal circuits.\nDeep understanding of semiconductor device physics, CMOS technologies, and advanced process nodes.\nStrong experience with circuit design, verification, modeling, silicon correlation, and product qualification.\nDemonstrated technical leadership, mentoring, and multi-functional collaboration skills.\nExperience driving innovation through the creation of reusable intellectual property, patent portfolios, and advanced build methodologies.\nFamiliarity with AI-driven engineering tools and automation techniques for semiconductor design workflows.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Verification Engineer, DMTS/SMTS/MTS", "company": "Micron", "location": "Hyderabad, Telangana, India", "date_posted": "2026-10-08T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/44796871", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nKey Responsibilities\nLead verification strategy, architecture, and execution across RTL, AMS (Analog Mixed-Signal), and Transistor-Level Verification (TAV) domains, driving key technical decisions throughout the product lifecycle.\nDefine and implement verification methodologies, test plans, coverage strategies, and debug flows to ensure first-pass silicon success and high product quality.\nCollaborate with global cross-functional teams including design, product engineering, validation, and CAD/EDA groups to establish and deploy best-known verification practices.\nDevelop, maintain, and enhance verification environments using SystemVerilog, UVM, SPICE/HSPICE, FineSim, Verilog, and related industry-standard tools.\nPerform root-cause analysis and debugging across digital, mixed-signal, and transistor-level designs, correlating simulation results with silicon behavior.\nDrive verification closure through functional, code, assertion, and mixed-signal coverage analysis.\nEvaluate, develop, and deploy innovative tools, automation frameworks, and AI-assisted solutions to improve verification efficiency, productivity, and quality.\nApply strong knowledge of CMOS design fundamentals, semiconductor device behavior, circuit analysis, and mixed-signal architectures to solve complex verification challenges.\nMentor and provide technical leadership to engineers while leading strategic verification initiatives across multiple teams and projects.\nStrong programming and scripting skills (Python preferred) with experience in automation, data analysis, and EDA workflow optimization.\nDemonstrated ability to lead technical projects, influence architecture decisions, and be recognized as a subject matter expert in verification methodologies and design quality.\nProven ability to demonstrate AI‑assisted (vibe) coding techniques to improve efficiency or automate design and analysis methodologies\nLeverage AI tools to automate the tools and workflow applying Artificial Intelligence in workflows to improve build efficiency\nQualifications:\nBachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field; Master’s or PhD preferred.\n10+ years of experience in semiconductor verification with expertise in RTL verification, AMS verification, transistor-level verification, memory, SoC, or advanced CMOS products.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Infra Design Verification Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-08T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720202486", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nKey Responsibilities:\nDevelop and maintain UVM-based verification environments for high-speed interconnect protocols (PCIe, CXL, AXI).\n\nCreate and execute verification plans for high-speed interconnect protocols including PCIe, CXL, AXI, and CHI.\n\nPerform block-level and top-level verification, including functional coverage, assertion-based verification, and regression testing.\n\nCollaborate with RTL designers, architects, and validation teams to ensure design correctness and coverage closure.\n\nWork closely with design and architecture teams to understand specifications and derive verification strategies.\n\nUse third-party VIPs (e.g., Synopsys, Mentor) for protocol compliance and simulation.\n\nImplement and enhance scoreboards, agents, monitors, and sequences.\n\nIntegrate and validate SMMU and Coresight components in Subsystem environments.\n\nDrive verification closure through coverage convergence and assertion-based verification.\n\nContribute to performance, power, and cost optimization considerations during verification.\n\nMentor junior engineers and contribute to verification methodology improvements.\n\nDebug failures at RTL and gate-level simulations.\n\nRequired Skills:\nStrong proficiency in System Verilog, UVM, and verification methodologies.\n\nDeep understanding of PCIe Gen3/Gen4/Gen5/Gen6, CXL 1.1/2.0/3.0, AXI/CHI protocols, and SMMU/Coresight architecture.\n\nFamiliarity with Synopsys/Mentor VIPs for PCIe/CXL and AMBA protocols.\n\nExpertise in assertion-based verification (SVA) and coverage-driven testing.\n\nProficiency in Perl/Python/Tcl scripting for automation.\n\nKnowledge of power-aware verification (UPF), formal verification, and performance/power optimization.\n\nExperience with coverage-driven verification and random constraint-based testing.\n\nExperience with scripting languages like Python, Perl, or Tcl.\n\nPreferred Qualifications:\nBachelor’s/Master’s/Ph.D. in Electrical, Electronics, or Computer Engineering.\n\n3–6 years of ASIC/Subsystem/SoC verification experience.\n\nExperience with PCIe, USB, Ethernet, or other peripheral protocols is a plus.\n\nExposure to post-silicon validation and lab bring-up is desirable.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NOC Emulation Staff Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-08T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720502289", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nWe are seeking a highly motivated Emulation Engineer to join our IP verification team. The candidate will be responsible for developing and executing hardware-assisted verification solutions using industry-leading emulation platforms. The role involves enabling pre-silicon validation of complex SoCs, accelerating verification cycles, debugging complex system-level issues, and collaborating closely with Design, DV, Architecture, Software, and Post-Silicon teams.\nThe ideal candidate should possess strong expertise in SystemVerilog/UVM, emulation technologies, SoC architectures, and verification methodologies.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nKey Responsibilities\nEmulation Environment Development\nPort simulation-based verification environments to emulation platforms.\nDevelop synthesizable testbench components, transactors, and BFMs for hardware-assisted verification.\nOptimize testbenches and verification flows for emulation performance and scalability.\nEnable execution of long-running use cases that are impractical in simulation.\nDebug and Analysis\nAnalyze failures observed in emulation runs and root-cause RTL, testbench, or software issues.\nGenerate and analyze waveforms, transaction traces, and performance metrics.\nWork with design teams to resolve functional and performance-related bugs.\nCompare emulation results against simulation and silicon behavior when required.\nInfrastructure and Automation\nDevelop automation scripts for regression execution, result collection, and reporting.\nImprove compile and runtime efficiency of emulation environments.\nDrive continuous improvements in hardware-assisted verification methodologies.\nCross-Functional Collaboration\nWork closely with RTL, Design Verification, Architecture, Firmware, and Post-Silicon teams.\nParticipate in verification planning, coverage reviews, and signoff discussions.\nMentor junior engineers and contribute to team-wide best practices.\nRequired Qualifications\nBachelor's or Master's degree in Electronics Engineering, Computer Engineering, Electrical Engineering, or related field.\n4 to 10 years of experience in Design Verification and/or Emulation.\nStrong understanding of digital design fundamentals and computer architecture.\nExpertise in SystemVerilog and UVM.\nExperience with hardware-assisted verification platforms such as:Cadence Palladium\nSynopsys ZeBu\nSiemens Veloce\n\nExperience with:Synthesizable testbench development\nTransaction-based acceleration\nHybrid/emulation verification methodologies\n\nStrong debugging skills using:Verdi\nDVE\nSimVision\nWaveform analysis tools\n\nGood scripting knowledge in:Python\nPerl\nShell scripting\n\nPreferred Qualifications\nExperience with one or more protocols:PCIe\nCXL\nAXI/AHB/APB\n\nExperience with:SoC-level verification\nFirmware validation\nEmbedded software bring-up\nPerformance validation\nLow-power verification\nPost-silicon correlation\n\nExposure to GPU, AI/ML, Automotive, Mobile, Networking, or Datacenter SoCs.\nTechnical Skills\nMust Have\nSystemVerilog\nUVM\nEmulation Platforms (ZeBu/Palladium/Veloce)\nRTL Debug\nFunctional Coverage\nAssertions (SVA)\nLinux/Unix Environment\nGood to Have\nC/C++\nSystemC/TLM\nPython Automation\nFormal Verification\nFPGA Prototyping\nFirmware/Embedded Software\nDesired Soft Skills\nExcellent analytical and problem-solving abilities.\nStrong verbal and written communication skills.\nAbility to work in a fast-paced cross-functional environment.\nOwnership mindset with strong execution focus.\nAbility to mentor junior engineers and drive technical initiatives.\nSuccess Metrics\nReduction in verification turnaround time through emulation.\nImproved bug discovery at subsystem and SoC levels.\nSuccessful execution of software-driven and long-running workloads.\nVerification closure with high quality and predictable schedules.\nContribution to reusable and scalable emulation infrastructure.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Associate Engineer – CAD AI/ML", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-08T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721332822", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nPosition Overview\nWe are looking for a motivated Associate Engineer – CAD AI/ML with a strong foundation in Computer Science and an interest in applying artificial intelligence and machine learning to semiconductor design automation and CAD engineering workflows.\nThe successful candidate will work with CAD and design teams to develop automation, data-driven solutions, and intelligent tools that improve engineering productivity, tool efficiency, and design-flow quality. This is an entry-level position suitable for candidates with 0–1 year of experience.\nKey Responsibilities\nDevelop scripts, utilities, and automation solutions for CAD and design workflows.\nApply machine learning and data analytics techniques to CAD data, tool logs, reports, and engineering metrics.\nAssist in building models for:Tool runtime and resource prediction\nFailure classification and root-cause analysis\nLog analysis and anomaly detection\nQuality and performance trend analysis\nFlow optimization and productivity improvement\n\nProcess and analyze large datasets generated by EDA tools and semiconductor design flows.\nDevelop data-preprocessing pipelines for extracting meaningful information from logs and reports.\nSupport the integration of AI/ML models into existing CAD automation frameworks and engineering tools.\nCollaborate with CAD, RTL, verification, synthesis, physical design, and methodology teams.\nDebug scripts, data pipelines, and model-related issues.\nCreate dashboards, reports, and visualizations to communicate engineering insights.\nConduct experiments, evaluate model performance, and document results.\nFollow software development best practices, including version control, testing, code reviews, and documentation.\nStay current with developments in AI/ML, automation, and semiconductor design technologies.\nRequired Qualifications\nBachelor’s degree in Computer Science, Information Technology, Artificial Intelligence, Machine Learning, or a related field.\n0–1 year of experience in software development, CAD automation, data analytics, or AI/ML.\nStrong programming skills in Python.\nGood understanding of:Data structures and algorithms\nObject-oriented programming\nMachine learning fundamentals\nStatistics and probability\nData preprocessing and analysis\nLinux/Unix environments\nDatabase concepts and SQL\n\nFamiliarity with Python libraries such as NumPy, Pandas, Scikit-learn, and Matplotlib or similar tools.\nAbility to read, analyze, and troubleshoot software logs and engineering reports.\nStrong analytical and problem-solving skills.\nGood written and verbal communication skills.\nAbility to work effectively in a multidisciplinary engineering environment.\nPreferred Qualifications\nAcademic projects, internships, or coursework in AI/ML, data science, or automation.\nFamiliarity with TensorFlow, PyTorch, Keras, or other ML frameworks.\nKnowledge of natural language processing, generative AI, large language models, or retrieval-augmented generation.\nExposure to semiconductor design and verification concepts, including:RTL and SystemVerilog\nSynthesis and implementation flows\nStatic analysis, formal verification, or simulation\nDesign-for-test and low-power methodologies\nEDA tools and CAD flows\n\nExperience working with structured and unstructured engineering data.\nFamiliarity with Git, REST APIs, CI/CD, Docker, or cloud-based development environments.\nExposure to shell scripting, Perl, Tcl, or other automation languages.\nUnderstanding of software testing and automation methodologies.\n\nMinimum Qualifications:\n•    Associate's degree in Computer Science, Electrical/Electronic Engineering, Engineering, or related field.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Sr Engineer - DFT", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-08T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720381553", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    5+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Pre-Silicon SoC Validation - Technical Lead", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-08", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Pre-Silicon-SoC-Validation---Technical-Lead_JR0287738", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nRole Summary:\n\nSeeking an experienced SoC Validation Engineer to define, drive, and execute validation strategies across the full silicon lifecycle, from architecture definition and pre-silicon planning through silicon power-on, post-silicon debug, stepping readiness, and PRQ quality convergence.\n\nThe role requires deep expertise in complex SoC validation, security validation, coherency flows, firmware and hardware interaction, disaggregated architecture, and cross-functional technical leadership.\n\nThe engineer will be responsible for ensuring early risk identification, high-quality milestone readiness, predictable silicon bring-up, rapid sighting debug, and continuous feedback from post-silicon learnings into earlier validation phases.\n\nKey Responsibilities:\n\nDefine and drive end-to-end SoC validation strategy across the full lifecycle, including architecture definition, pre-silicon validation planning, RTL milestone readiness, silicon power-on preparation, post-silicon debug, stepping readiness, and PRQ quality convergence.\n\nDevelop comprehensive validation plans, execution strategies, coverage goals, debug plans, and sign-off criteria aligned to program milestones and product quality targets.\n\nDrive validation of critical SoC flows across security, coherency, memory, fabric, IO, and cross-die interactions in disaggregated architectures.\n\nValidate complex hardware, firmware, and software interactions with specific focus on security handshakes, coherency protocols, cache and fabric ordering, access control, isolation, attestation, fuse/security policy behavior, and multi-die/domain interactions.\n\nReview architecture and microarchitecture specifications to identify validation gaps in security, coherency, shared-resource behavior, cross-die communication, firmware sequencing, and lifecycle readiness from pre-silicon through post-silicon execution.\n\nDrive debug of complex pre-silicon and post-silicon failures, identify root cause across RTL, firmware, microcode, platform software, validation content, security policy, coherency behavior, and system-level configuration.\n\nPartner with architecture, design, verification, firmware, post-silicon, security, coherency, platform, manufacturing, and program teams to ensure high-quality validation readiness, silicon bring-up efficiency, and timely closure of issues across product milestones.\n\nUse post-silicon sightings, customer issues, stepping feedback, defect trends, security observations, and coherency escapes to strengthen earlier validation strategies, improve coverage, and prevent repeated escapes across programs.\n\nDefine validation quality metrics, execution dashboards, risk indicators, milestone readiness reports, and sign-off recommendations for leadership reviews.\n\nDrive innovation in validation efficiency, including automation, test grading, coverage-driven execution, AI/ML-assisted bug hunting, regression optimization, and shift-left methodologies.\n\nMentor senior and mid-level engineers, build technical depth in the team, and contribute to reusable validation methodologies, collateral, and best practices across programs.\n\nQualifications:\nBachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, VLSI, Embedded Systems, Computer Science, or a related discipline.\n\n12-20 years of relevant industry experience in pre-silicon validation, SoC validation, design verification, silicon validation, firmware validation, or hardware/software co-validation.\n\nStrong understanding of SoC architecture, microarchitecture, CPU/core integration, fabrics, memory subsystem, security, coherency, cache hierarchy, firmware-driven security flows, and disaggregated/multi-die architectures.\n\nHands-on experience defining and executing validation strategies across the product lifecycle, including architecture review, pre-silicon planning, RTL milestone readiness, silicon power-on preparation, post-silicon sighting debug, stepping feedback, and PRQ quality convergence.\n\nProven experience in developing validation plans, test strategies, debug methodologies, coverage closure plans, post-silicon feedback loops, and milestone sign-off criteria for complex SoCs and disaggregated silicon products.\n\nRequired Technical Skills:\n\nDeep knowledge of SoC architecture, system architecture, disaggregated and multi-die architecture, microarchitecture fundamentals, IP/subsystem integration, fabrics, memory hierarchy, and cross-die communication.\n\nStrong expertise in validation methodologies across the pre-silicon to post-silicon continuum, including test planning, content development, coverage closure, milestone readiness, silicon bring-up support, sighting reproduction, and lifecycle feedback loops.\n\nStrong technical depth in security validation, coherency validation, cache/fabric ordering, access-control flows, isolation mechanisms, firmware-authenticated flows, fuse/security policy behavior, and multi-domain system interactions.\n\nStrong debug skills using waveform analysis, logs, traces, checkers, assertions, firmware instrumentation, and platform-level debug tools.\n\nExperience with one or more programming or scripting languages such as C, C++, Python, Perl, SystemVerilog, UVM, or similar validation automation languages.\n\nKnowledge of firmware and microcode flows, manageability firmware, or other SoC firmware interactions.\n\nUnderstanding of validation quality metrics, functional coverage, test effectiveness, regression health, bug trends, and milestone readiness indicators.\n\nLeadership and Collaboration Expectations\n\nOperate as a senior technical leader who can independently define technical direction, influence stakeholders, and drive convergence across multiple teams.\n\nLead cross-functional discussions with architecture, design, verification, firmware, post-silicon, platform, manufacturing, and program management teams.\n\nIdentify program risks early, propose mitigation plans, and drive technical decision-making to protect milestone predictability and product quality.\n\nCommunicate complex technical issues clearly through reviews, dashboards, status reports, debug summaries, and leadership updates.\n\nMentor engineers, build validation capability within the organization, and help establish scalable processes for future SoC programs.\n\nPreferred Qualifications:\n\nPrior Intel Xeon product validation experience across one or more server SoC generations, including pre-silicon planning, silicon power-on, post-silicon debug, stepping readiness, or PRQ quality convergence.\n\nExposure to Cheetah-based validation methodologies, including validation environment integration, filelist/dependency setup, methodology quality checks, simulation build/run readiness, or SoC/IP integration collateral checks.\n\nExposure to security, coherency, cache hierarchy, fabric, memory validation.\n\nExperience with lifecycle-driven validation improvements, including shift-left strategies, post-silicon sighting reproduction in pre-silicon environments, reusable validation content, formal-assisted validation, collateral consistency checks, and AI/ML-driven validation efficiency improvements.\n\nPrior experience driving A0/TI readiness, milestone sign-off, or post-silicon sighting reproduction in pre-silicon environments.\n\nDemonstrated ability to deliver results through ambiguity, influence without authority, and enable technical convergence across distributed teams.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Microarchitecture and Design Engineer - AI SoC", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-08", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Microarchitecture-and-Design-Engineer---AI-SoC_JR0287606-1", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.\n\nJoin Intel's AI Revolution Intel's AI SoC organization develops cutting-edge products powering a wide range of AI applications, from edge devices to data center accelerators. If you are an engineer with strong technical and communication skills who thrives in a fast-paced environment with abundant learning opportunities, you are the ideal candidate for this role. Join us to shape the future of AI hardware.\n\nThis role is at the heart of Intel's product development process, combining technical expertise, creative problem-solving, and disciplined execution. By joining our team, you will contribute to the design and development of next-generation technologies that power the future of computing, enabling transformative experiences for billions of users worldwide. This is your opportunity to work alongside some of the brightest minds in the industry, leveraging innovative methodologies to overcome challenging design problems and shaping the future of technology.\n\nKey Responsibilities:\nDevelop logic design, RTL coding, and simulation for SoC designs.\nDefine and implement architecture and microarchitecture features for logic blocks.\nPerform quality checks across RTL, timing, power, and design integrity to meet performance goals.\nOptimize RTL logic to ensure compliance with power, performance, area, and timing targets.\nCollaborate with IP providers to integrate and validate IPs at the SoC level.\nReview and contribute to verification plans and ensure design features are comprehensively tested.\nIdentify and resolve RTL test failures to ensure feature correctness.\nEmploy secure development practices to address security objectives and threats in the design.\nDrive quality assurance compliance for seamless IP and SoC handoff throughout the design flow.\n\nQualifications:\nYou must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.\n\nMinimum Qualifications:\nBachelor's or Masters/Phd in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 3+ years of experience.\nExpertise in microarchitecture, RTL design, coding, and simulation using SystemVerilog.\nStrong knowledge of system-level design principles, including power, performance, and area optimization.\nDemonstrated experience with timing/power convergence methodologies and tools.\n\nPreferred Qualifications:\n\nExperience with SoC architecture and SoC microarchitecture.\nPassion for continuous learning, including an understanding of AI models and how they shape AI hardware architectures\nProficiency in clock domain crossing analysis and implementation techniques.\nHands-on experience with quality assurance practices and secure development in logic design.\nProven ability to effectively communicate across multidisciplinary teams.\nTrack record of disciplined execution and delivering high-quality designs under tight deadlines.\nExperience in driving innovative solutions to complex design challenges.\nPassion for continuous learning and staying current with advancements in SoC design methodologies and technologies.\n\nJoin us to push the boundaries of technology and make a lasting impact on the future of computing.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Product Engineer", "company": "Lattice", "location": "Manila, Philippines", "date_posted": "2026-10-08", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Manila-Philippines/Product-Engineer_R-103347", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nResponsibilities\nDevelop ATE test and characterization programs.\nDevelop characterization test plans using established methodologies targeted on chip IP functions and features.\nExecute characterization of target chip IP features using wafer-level ATE, package-level ATE, and package-level bench platforms across process, temperature, and voltage conditions.\nApply statistical analysis on collected characterization data to define key product datasheet parameters and report out results.\nIdentify and analyze to root cause product marginalities, communicating and coordinating root cause closure to appropriate cross-functional team (eg. Applications Engineering, Design Engineering, etc.)\nDesign and implement test circuits using FPGA fabric and embedded IP.\nDevelop bench automation and data collection scripts and programs.\nDesign and develop ATE and bench HW.\nDrive all product issues to resolution.\nPlan and execute testing of samples (ie. AS, ES), ensuring timely delivery of tested samples to internal and external customers.\nAnalyze and report out on test yield and test time. \n \nRequired Skills\nAt least 2 years individual contributor in Product Engineering or Si Validation / Characterization\nBS degree (ECE, CoE, EE, Physics)\nGood working knowledge of semiconductor devices and test methodologies\nExperience in ATE test program development, integration and debug on Nextest Magnum and Advantest T2K\nExperience in hardware development (bench board)\nExperience in IC validation and characterization using various bench tools (i.e. Oscilloscope, Pattern Generators, Data Timing Generator, Multimeters, etc)\nExperience with WAT/etest, wafer sort, package assembly, final test (i.e. full backend IC process)\nExperience in Programmable Logic is desired\nExperience in RTL Design, Design Verification an advantage\nKnowledge in test, DFT methodologies (ie. scan, BIST), and fault grade methodologies an advantage\nKnowledge in Hardware Description Language such as Verilog or VHDL an advantage\nKnowledge in programming languages (ie. Python, C++)\nKnowledge of Statistical Process Control\nProficient in the use statistical analysis SW (ie. SAS JMP, R)\nKnowledge in Yield Analysis\nExcellent verbal and written English skills.  Demonstrated ability to work with multiple groups and across cultures\nGood analytical and problem solving abilities\nStrong Windows, Unix, and MS Office skills\nCurious with strong self-motivation to learn and explore\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nPhilippinesLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Senior Lead Design Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-10-08", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Design-Engineer_R-10064874", "is_hardware": true, "platform": "workday", "jd_text": "NXP's MCU/MPU Engineering (MME) team is a central engineering organization responsible for developing and delivering Systems-on-a-Chip (SoCs) for NXP's Automotive, Edge, Radar Processing and Advanced Analog business lines.\nMME's SoC Front End team produces design solutions covering the very wide range of SoCs required by the business lines. The team is challenged to produce industry-leading solutions covering very cost-sensitive, low-power devices to highly integrated, high-performance, multi-cohort devices compliant with the latest automotive and industrial safety and security standards.\nScope of Responsibilities/Expectations\nLeading SOC debug , micro-architecture, and integration of the System on Chip (SOC) from initial specification till tape out and beyond\nDrive and implement best SoC design methodology/practices and scale it across different business lines.\nSigning off RTL, timing constraints, CDC, RDC and work with different functions like verification, DFT, synthesis, etc. to get to a production quality Silicon.\nDocumenting the SOC design and micro-architecture for usage by other SOC functions\nProvide debug design support for any silicon related debugs of chips in post-silicon phase.\n\nSpecific Knowledge/Skills\nASIC designers with experiences in all aspects of RTL design flow from Specification/Micro-architecture definition to design.\nExperience with Arm Cortex-M/A/R processor-based SoC debug infrastructure handling\nARM CoreSight, ETM, STM, DAP, CTI, JTAG, SWD, Trace32, ARM Debug, ARM Trace integration exposure\nExperience: 5-10 Years in IP/SOC design with successful delivery of production quality chips\nGood knowledge of Digital Design and hands-on experience with Verilog RTL coding/integration of debug logic\nShould have a firm understanding and hands-on experience on Chip Assembly, IP Integration, RTL signoff tools and CDC/RDC/Lint/Synthesis.\nFamiliarity with Computer architecture: knowledge of microprocessors (ARM, RISC-V), bus protocols preferred (AXI/ACE/APB/ATB). Knowledge on CPU architecture, Core-sight and peripherals like PCIe, USB, DDRs is highly desirable.\nStrong domain knowledge of Clocking, Reset, System modes, debug, interconnect, safety, security and other architectures Know-how of Serial Interfaces, Multimedia, External Bus Interfaces\nSelf-motivated to drive issues to closure. Should be a team player and willing to work with cross functional teams on issues resolution.\nExcellent written and verbal communication skill.\nCreative problem-solving skills, logic analysis skills, ability to logically break complex problems down to manageable components.\n\nMore information about NXP in India...\n\n#LI-29f4", "jd_status": "stored"}, {"title": "DFT Engineer - Hardware", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-08", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/DFT-Engineer---Hardware_JR2018054", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. Make the choice to join us today. NVIDIA is an equal opportunity employer. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. We are looking for a DFT Engineer.\n\nWhat you'll be doing:\nAs a member in our team, you will be responsible for end-to-end DFT from RTL design to Gate level scan insertion to Verification (including JTAG, boundary scan, security mechanisms, and test clocking—across various test modes, including multiple ATPG configurations) to silicon bring-up.\n\nYour responsibility will also include verification and silicon bringup of Scan ATPG and other DFT features.\n\nIn addition, you will help develop and deploy DFT methodologies for our next generation products.\n\nBe apart of innovation to strive improve the quality of DFT methods.\n\nYou will also need to work with multi-functional teams to incorporate DFT features into the chip.\n\nOccasional travel and also some late hours online meetings involved during critical milestones.\n\nWhat we need to see:\nBSEE or MSEE from reputed institutions or equivalent experience with 2+ years of experience\n\nYou should be well versed with static timing Analysis, ECO, ASIC/Logic Design Flow, HDL and Digital logic design.\n\nExperience in RTL and Gates verification and simulation.\n\nYou need to be familiar with BIST architecture and JTAG/IEEE1149.1/IEEE1500.\n\nStrong DFT knowledge in Scan ATPG, compression techniques and memory test.\n\nStrong analytical and problem solving skills with good scripting knowledge (either Perl / Python)\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "HSIO Execution Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-08", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/HSIO-Execution-Engineer_JR2026991", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. Today, we are tapping into the unlimited potential of AI to define the next era of computing — an era in which our GPUs act as the brains of computers, robots, and self-driving cars that understand the world. Doing what has never been done before takes vision, innovation, and the world’s best talent.\n\nNVIDIA's Silicon Co-Design group is seeking Execution engineers who will be supporting development and validation of product and engineering platforms for Nvidia GPUs and SOCs. You will get to work hands on across various high speed IOs such as PCI-E Gen5, USB SS gen2, System level functional testing for performance and system stability. You will be part of a highly motivated, talented, global HW team and play a crucial role in delivering a high quality, state of the art products to serve various key markets.\n\nWhat you’ll be doing :\nAs part of platform validation team, you will be running various test cases on engineering systems that involve stress testing, electrical testing, functional testing, environmental testing which involves Windows, Linux and Android based stress tests\nCollect data from large number of systems, identify failures, classify failures based on symptoms and first level of debug. Preparing and filing test reports, bugs\nAssembly and testing of complex systems for stability testing\nUnderstand and execute test procedures across process, voltage, temperature corners, do required modifications to test scripts to suite the environment, drive prelim debugs and triage.\nRun functional tests for GPU and SoC interfaces like PCIe, USB, eMMC, DP, HDMI,\nParticipate in Platform Bring up and perform board screening, FW programming, fusing, power rail checkouts, IO peripherals checkout\n\nWhat we need to see:\nB.E with 4+ years of experience in hardware platform testing and validation\nExperience in board validation, electrical SI measurement concepts\nHands-on experience with lab/measurement equipment (DSOs, BERT, VNA, Protocol analyzers, Data Acquisition units) is required\nStrong familiarity with executing tests under Linux environment. Must be able to do prelim debug analysis\nFamiliarity with basic debugging using tools like WinDBG, ADB etc\nStrong understanding of PC system components and various buses and interconnects, PCB components.\n\nWays to stand out from the crowd :\nIn-depth working knowledge of complex platforms in semiconductor companies\nFamiliarity with tools for data analysis.\nStrong collaborative and communication skills, specifically a shown ability to effectively guide and influence within a dynamic environment.\nStrive to be a standout colleague and be ready to work with global teams from diverse cultural backgrounds in a high energy environment.", "jd_status": "stored"}, {"title": "Sr. Principal Firmware Engineer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-10-08", "url": "https://careers.skyworksinc.com/job-invite/78601/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 78601\n\nDescription\n\nAre you looking for the next step to advance your career in the world of audio technology? Skyworks is seeking team members to help innovate market-specific mixed-signal system on chips (SoCs) for audio and voice applications spanning smart speakers and microphones, wired/wireless headsets, virtual assistants and intelligent gaming controllers. Our advanced audio, voice, speech and artificial intelligent solutions combine breakthrough ultra-low power analog circuits, highly efficient power management systems and custom hardware accelerators to enable smart acoustic signal processing and AI functionality. Come be part of a team that is changing the way the world communicates and who is at the forefront of audio and voice technology innovation! Our proprietary technology achieves the highest level of integration in the industry and sets a new performance standard for low power consumption and minimal footprint.\n\nResponsibilities\n\nCreate mixed signal ASICs targeted at audio and wireless audio applications.\n\nThese are highly integrated designs incorporating audio codecs, amplifiers, battery chargers, DSP processors, peripherals, and power control systems that support a wide range of communication interfaces.\n\nThe Firmware group works with the hardware team to help specify these custom systems. From there, we create the core operating system and driver components and follow this through to finished silicon and SDK packages that we provide to application teams.\n\nOur goal is to address all the elements the processor controls and simplify the task of using these parts in a wide range of designs.\n\nYour role will be as an embedded firmware designer as part of this design group, writing, testing and debugging code for embedded processors on our SoCs. Our engineering team works closely to solve difficult problems, and your ability to collaborate with others will be important to the success of the projects to which you contribute.\n\nRequired Experience and Skills\n\nBachelor’s 15+ year or Master's degree in Electrical or Computer Engineering with 12+ years of experience\n\n10+ years’ experience in programming with C and assembly in deeply embedded systems\n\n6+ years with real-time operating systems (RTOS)\n\n3+ years’ experience with/exposure to Python preferred\n\nARM Cortex-M experience is preferred\n\nExperience with Security/Secure boot/Cryptographical algorithms and methods preferred.\n\nUSB, SPI, I2C, I2S, Bluetooth experience is a plus\n\nExperience working with electrical hardware interfacing preferred\n\nWorking knowledge of JTAG debug interface\n\nExperience with ARC architecture desirable\n\nUnderstanding of RTL/simulation tools a plus\n\n#LI-CB1\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Applications Engineering, Sr Staff Engineer (Physical Verification)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-08", "url": "https://careers.synopsys.com/job/bengaluru/applications-engineering-sr-staff-engineer-physical-verification/44408/101731559168", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology powers the Era of Pervasive Intelligence, enabling breakthroughs in AI, high-performance computing, automotive, mobile, and cloud infrastructure. We deliver industry-leading silicon design, verification, IP, and software solutions that help customers bring innovative products to market faster and with greater confidence.\nOur Physical Verification Applications Engineering team partners closely with semiconductor companies, foundries, and internal engineering organizations to solve the industry's most complex signoff challenges. We develop advanced methodologies, drive technology adoption, and help customers achieve predictable design closure on the most advanced process nodes.\nYou Are\nYou are a seasoned Physical Verification expert with deep experience in signoff verification and semiconductor design methodologies. You understand that successful tapeout requires more than running verification decks. It demands technical leadership, scalable methodologies, automation, and close collaboration across multiple engineering disciplines.\nYou thrive on solving complex DRC, LVS, ERC, Density, Antenna, and reliability verification challenges at advanced technology nodes. You are comfortable working directly with customer engineering teams, understanding their design bottlenecks, and driving solutions that improve productivity and accelerate design closure.\nYou enjoy mentoring engineers, influencing technical strategy, and developing innovative verification methodologies that scale across projects and organizations.\nWhat You'll Be Doing\nLead Physical Verification signoff activities for strategic Synopsys customers across advanced semiconductor technologies.\nDrive DRC, LVS, ERC, Density, Antenna, PERC, and Reliability Verification closure for large-scale SoC and custom design projects.\nDevelop and deploy scalable PV methodologies, automation frameworks, and productivity-enhancing verification flows.\nCollaborate with Physical Design, Custom Design, Technology, Foundry, CAD, Product Engineering, and R&D teams to resolve complex signoff challenges.\nAnalyze technical risks and proactively identify verification bottlenecks that may impact project schedules and tapeout milestones.\nProvide technical leadership and mentorship to engineering teams while promoting verification best practices.\nSupport customer engagements by understanding design challenges and proposing innovative verification solutions.\nDrive feedback into Synopsys product development teams to enhance Physical Verification technologies and customer workflows.\nInfluence roadmap decisions and adoption of next-generation verification methodologies for advanced process technologies.\nContribute to customer success by improving verification turnaround time, design quality, and signoff predictability.\nWhat You'll Need\nB.Tech with 8+ years or M.Tech with 6+ years of experience in Physical Verification, Physical Design, or related VLSI domains.\nStrong expertise in Physical Verification signoff flows including: DRC\nLVS\nERC\nPERC\nDensity Verification\nAntenna Verification\nReliability Verification\n\nHands-on experience with industry-leading EDA tools such as: Synopsys IC Validator (ICV)\nSiemens Calibre\nCadence Pegasus\nOr equivalent Physical Verification platforms\n\nDeep understanding of advanced semiconductor technologies such as 7nm, 5nm, 3nm, and beyond.\nStrong knowledge of: Semiconductor manufacturing processes\nDevice physics\nPhysical layout design\nDesign-for-Manufacturing (DFM)\nAdvanced process-node signoff methodologies\n\nProven experience debugging complex PV violations and driving signoff closure across large-scale projects.\nStrong scripting and automation skills using Python, Perl, Tcl, Shell, or similar programming languages.\nExperience developing reusable methodologies, automation solutions, and verification process improvements.\nExposure to cloud computing, distributed verification environments, or large-scale compute infrastructures is desirable.\nWho You Are\nA strong technical leader who can influence engineering decisions without direct authority.\nAn exceptional problem solver who enjoys tackling complex silicon signoff challenges.\nA collaborative professional capable of working across global and cross-functional teams.\nA customer-focused engineer who understands both technical and business priorities.\nA mentor who actively develops and guides junior engineers.\nA proactive and self-driven individual with strong ownership and accountability.\nSomeone who can manage multiple priorities while consistently delivering high-quality results.\nThe Team You'll Be Part Of\nThe Physical Verification Applications Engineering team develops, enhances, and deploys industry-leading verification solutions that enable reliable signoff and manufacturability for advanced semiconductor designs.\nThe team works closely with customers, foundries, and internal engineering organizations to address emerging technology challenges, accelerate adoption of Synopsys verification products, and drive innovation in methodology development, automation, and design closure.\nThe Impact You Will Have\nEnable customers to achieve faster, more predictable silicon signoff using Synopsys Physical Verification solutions.\nImprove customer productivity, verification quality, and time-to-market through technical excellence and automation.\nDrive innovation in Physical Verification methodologies and signoff technologies.\nStrengthen Synopsys' leadership position in advanced-node semiconductor verification.\nBridge customer requirements, technology advancements, and product development initiatives.\nContribute directly to business growth by helping customers successfully deploy and scale Synopsys verification solutions.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Hardware Lab Technician - Silicon Validation", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-08", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Hardware-Lab-Technician---Silicon-Validation_JR2027119-1", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. Today, we are tapping into the unlimited potential of AI to define the next era of computing — an era in which our GPUs act as the brains of computers, robots, and self-driving cars that understand the world. Doing what has never been done before takes vision, innovation, and the world’s best talent.\n\nNVIDIA's Silicon Co-Design group is seeking lab Technician who owns end-to-end hardware setup and validation support for assigned chip/silicon programs within the Hardware Validation Farm. This role requires deep hands-on expertise in board bring-up, thermal attachment, and hardware diagnostics, along with the judgment to independently troubleshoot and resolve complex hardware issues with minimal supervision. Technicians in this role carry setups through their full lifecycle — from board receipt through sanity validation and ongoing post-enablement support — and are relied on to preserve technical continuity across program cycles.\n\nWhat you’ll be doing :\n\nFull Setup Lifecycle Ownership — Own board receipt, pre-enablement checks, thermal attachment, peripheral bring-up, and sanity validation for assigned programs; provide ongoing post-enablement support.\nHardware Diagnostics & Root Cause Analysis — Troubleshoot device-under-test (DUT) failures beyond surface-level symptoms, trace issues to true root cause, and make informed calls on whether a setup is recoverable.\nThermal Attachment Expertise — Execute thermal attachment procedures across varying cooler head configurations, applying mechanical adjustments as needed to achieve reliable thermal performance.\nIndependent Program Ownership — Carry assigned chip programs end-to-end with minimal supervision, including issue triage, sanity runs, and full closure documentation (failure analysis summaries and issue/bug filing).\nProcess Improvement — Proactively identify gaps in lab setup, preparation, or validation procedures, and contribute to process improvements that strengthen farm readiness.\nLab Safety — Identify and report safety hazards or incidents promptly to prevent hardware damage or injury.\nCross-Team Collaboration — Work closely with Farm Engineers, Program Leads, and functional validation teams to align on setup requirements and technical escalations.\n\nWhat we need to see:\nDiploma/ITI, Associate's degree, or equivalent technical certification in Electronics, Mechanical, Electrical, or a related field, with 2+ years of hands-on experience in a hardware lab, server/board-level bring-up, or validation environment.\nDemonstrated experience with thermal solution attachment (heat sinks, cold plates, liquid cooling, or similar) and strong hardware troubleshooting skills with the ability to independently isolate root cause.\nExperience supporting multiple concurrent hardware or chip validation programs with minimal supervision, including the judgment to triage issues and make sound technical calls independently.\nExperience authoring closure documentation, failure analysis reports, or formal issue/bug tracking, along with familiarity with lab safety protocols and incident reporting procedures.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior Physical Design Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-08", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Physical-Design-Engineer_JR2010048", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel NVIDIA is a \"learning machine\" that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life's work, to amplify human creativity and intelligence. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nNVIDIA is seeking passionate, highly motivated, and creative design engineers to be part of a team working on industry-leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n\nWhat you'll be doing:\nIn this position, you will expected to be part of the physical design methodology team. PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EMIR DROP, DRCs & schematic to layout verification.\n\nWork in collaboration with design team for addressing design challenges. Help team members in debugging tool/design related issues. Constantly look for improvement in RTL2GDS flow to improve PPA. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention.\n\nWrite scripts (TCL/Python) to help design teams move forward with their design and chip goals\n\nBuild flows based on industry standard EDA tools to implement designs efficiently and improve PPA. Support flows for chip design teams across tapeouts and tech nodes.\n\nWhat we need to see:\nBE/BTECH/MTECH, or equivalent experience.\n\n3+ years of experience in Physical Design, preferably with methodology/flow experience.\n\nStrong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSIl concepts related to synthesis, place & route, CTS, timing convergence, layout closure.\n\nExpertise on high frequency design methodologies. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification.\nWorking experience with tools like ICC2/Innovus, Primetime/Tempus/Seahawk etc used in the RTL2GDSIl implementation.\n\nStrong knowledge and experience in standard place and route flows\nICC2/Synopsys and Innovus/Cadence flows preferred. Well versed with timing constraints, STA, IR and ECO timing closure.\n\nStrong algorithmic thinking with good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools. Python will be helpful too.\n\nAbility to multi-task and flexibility to work in global environment.\n\nGood communication skills and strong motivation, Strong analytical & Problem Solving skills\n\nWillingness to learn and master new techniques quickly\n\nInnovate and drive changes across teams & workflows\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Physical Design Layout Engineer ICE", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-08", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Physical-Design-Layout-Engineer-ICE_JR0287940-1", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nIn this role, you will perform physical design integration of custom GPU designs, including Gfx, Media, and SOC. You will be responsible for layout verification, reviewing designs at various milestones, and providing timely feedback to cross-domain teams such as Floorplan, RDL, PDN, and Clock. Your contributions will ensure high-quality Tape-in results with timely fixes and a correct-by-construction approach, directly impacting the success of Intel's cutting-edge GPU solutions.\n\nBusiness group\nThis position is part of the Data Center Group (DCG), which drives innovation to deliver industry-leading data center solutions. The group focuses on developing high-performance, scalable technologies to power the architecture, integration, and operation of Intel's next-generation systems. By joining DCG, you'll play a key role in advancing solutions that support Intel's broader mission to fuel the world's digital transformation.\n\nKey Responsibilities\n- Perform physical design integration for GPU blocks, including Gfx, Media, and SOC.\n- Conduct layout verification and reviews at key milestones.\n- Provide detailed and timely feedback to cross-domain teams, including Floorplan, RDL, PDN, and Clock.\n- Ensure Tape-in quality with timely fixes and correct-by-construction methodologies.\n- Collaborate with other teams to achieve design goals and maintain project timelines.\n\nQualifications:\nMinimum Qualifications\n- Bachelors degree in a relevant field with 0-1 years of hands-on experience in physical design integration, demonstrated through internships, academic projects, coursework, or hands-on training OR a Masters degree in a relevant field with no prior professional experience.\n- Proficiency in physical design tools and methodologies, such as layout verification and design rule checks.\n- Understanding of floorplan, RDL, PDN, and clocking techniques.\n\nPreferred Qualifications\n- Strong analytical and problem-solving skills with a focus on technical accuracy and attention to detail.\n- Effective communication and collaboration skills to work closely with cross-domain teams.\n- Enthusiasm for contributing to complex design projects and advancing GPU technologies.\n\nWe invite you to bring your skills and creativity to Intel, where you'll be part of a dynamic team that drives innovation and shapes the future of technology.\n          \n\nJob Type:\nIntel Contract Employee\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Analog and Mixed Signal Layout Engineer", "company": "Lumilens", "location": "Bengaluru, India", "date_posted": "2026-10-07T20:21:39.274000+00:00", "url": "https://jobs.ashbyhq.com/lumilens/ff1c4bac-e6e8-44df-8c11-c54152ccdbfd", "is_hardware": true, "platform": "ashby", "jd_text": "Analog and Mixed Signal Layout Engineer\nAbout Lumilens\nAt Lumilens, we’re building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. Our technology enables faster, cooler, and more efficient computing through cutting-edge optical solutions and high-performance connectivity IPs. If you’re driven by innovation and eager to shape the future of AI infrastructure, we invite you to join our world-class engineering team.\n \nWhat You Can Expect\nPlay a key role in developing high-speed connectivity IPs using advanced semiconductor process technologies.\n\nDesign and implement complex analog, mixed-signal, and RF layouts for high-performance connectivity IPs, including floorplanning, device placement, and routing.\n\nWork closely with circuit designers to translate schematics into robust physical implementations from floorplanning through tapeout.\n\nOwn physical verification and signoff closure including DRC, LVS, ERC, antenna, DFM, and EMIR.\n\nOptimize layouts using extraction results to meet performance, matching, noise, and reliability targets.\n\nContribute to layout reviews and help drive effective layout methodologies and best practices.\n\nImprove layout productivity and quality through automation, scripting, and AI-assisted workflows.\n\nDevelop high-performance connectivity IPs used in AI, networking, and next-generation compute systems.\n\n \nWhat We’re Looking For\nBE/B.Tech or MS/M.Tech in Electrical/Electronics Engineering, Microelectronics, or a related field with 5–10 years of experience in analog, mixed-signal, RF, or custom layout development.\n\nHands-on experience with layouts for SerDes, data converters, clocking circuits, power management, transceiver building blocks, or related connectivity IPs.\n\nProven experience in full-custom layout and signoff including RC extraction, DRC, LVS, ERC, DFM, and EMIR.\n\nExposure to silicon photonics, co-packaged optics (CPO), near-package optics (NPO), optical transceivers, or high-bandwidth connectivity solutions is a strong plus.\n\nExperience with advanced semiconductor technologies including CMOS, FinFET, BiCMOS, or SiGe.\n\nStrong understanding of semiconductor process technologies, device physics, and layout-dependent effects.\n\nProficiency with Cadence Virtuoso and industry-standard EDA tools.\n\nExperience leveraging automation, scripting, or AI-assisted methodologies to improve layout productivity and quality.\n\nSolid understanding of layout techniques including matching, shielding, clock distribution, power planning, ESD protection, latch-up prevention, manufacturability, and reliability-aware design.\n\nDemonstrated success delivering complex layouts through tapeout.\n\nAbility to work effectively with globally distributed design, verification, CAD, and technology teams.\n\nExperience supporting multiple projects in a fast-paced product development environment.\n\n \nWhy Join Lumilens?\nWork alongside leaders and innovators in the photonics and semiconductor industry\n\nOpportunity to make an impact on the infrastructure powering next-generation AI and high-performance computing\n\nFast-paced, collaborative, and mission-driven environment\n\nCompetitive compensation and benefits\n\n \nJoin us at Lumilens and help shape the future of compute connectivity!", "jd_status": "stored"}, {"title": "Functional Test Pattern Development Engineer", "company": "Infineon", "location": "Bangalore BTP (India)", "date_posted": "2026-10-07T16:21:12+00:00", "url": "https://jobs.infineon.com/careers/job/563808971598280", "is_hardware": true, "platform": "eightfold", "jd_text": "#WeAreIn to leverage synergies contributing to Infineon’s product development. Are you in?\n\nYour role\nKey responsibilities in your new role\nAs a Functional Test Pattern Development Engineer, you will be responsible for developing, debugging, and optimizing functional test patterns for complex semiconductor and SoC products. You will work closely with Test Engineering and Bench teams to troubleshoot RTL simulation issues, enable successful silicon bring-up, and ensure seamless transition to volume production.\nDevelop and maintain functional test patterns based on design specifications and product requirements. \nDebug and analyse RTL simulation failures and drive issue resolution with Design and Verification teams. \nExecute and validate functional patterns in RTL simulation environments. \nSupport Test Engineering (TE) teams in vector bring-up and debug during silicon validation. \nWork closely with Bench and Silicon Validation teams to enable successful pattern execution on silicon. \nAnalyse pattern mismatches and silicon failures, identify root causes, and recommend corrective actions. \nDevelop automation utilities and scripts to improve pattern generation, execution, and debug efficiency. \nCollaborate with cross-functional teams including Design, Validation, Product Engineering, and Test Engineering.\n \n\n \n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related discipline.\n3 to 8 years of experience in Design Verification, Functional Test Pattern Development, Silicon Validation, Post-Silicon Validation, or Semiconductor Test Engineering.\nProficiency in C and/or C++ programming is preferred.\nStrong scripting expertise in Perl and Shell scripting.\nHands-on experience with RTL simulation, debug, and analysis.\nSolid understanding of digital design fundamentals, semiconductor architectures, and product development lifecycles.\nExperience working in Linux/Unix-based development environments.\nExcellent problem-solving, debugging, and cross-functional collaboration skills.\n \n\n \n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nGowri Shenoy\nGowri.Shenoy@infineon.com\n\nhttps://www.linkedin.com/in/gowri-shenoy-33894217/", "jd_status": "stored"}, {"title": "Staff Package Design Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-07T08:46:55.174000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000154042759-staff-package-design-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are looking for a Package Design Engineer to join our advanced silicon packaging design and simulation team and contribute to the design and delivery of high‑performance 2.5D/3D, chiplet‑based, FCBGA, SiP, wire bond and QFP/QFN packages used in industry‑leading products. The role requires strong technical depth in package layout execution, manufacturability, and cross‑domain co‑design with silicon, SI/PI, thermal, and reliability teams.\nKey Responsibilities\nPerform package layout design and development for advanced packages including 2.5D/3D IC, FCBGA, SiP, and multi‑chip modules.\nDevelop and maintain package CAD databases, ensuring accuracy and adherence to design guidelines, Design for Manufacturing (DFM), and Design for Assembly (DFA) requirements to ensure producibility.\nManage end-to-end design cycle, including schematic creation, netlist import, footprint assignment, and generation of manufacturing outputs (Gerbers, drill data, fabrication/assembly drawings).\nCreate and modify substrate/RDL layouts, bump maps, escape routing, and power/ground structures.\nWork closely with SI/PI, thermal, reliability, and DFT teams to support co‑design and optimization and participate in design reviews.\nEnsure designs comply with foundry, OSAT, and manufacturing design rules (DRC, LVS).\nSupport ECO cycles, design updates, and version control throughout the project lifecycle.\n\nMinimum Qualifications\n6+ years of hands‑on experience in package CAD layout and development.\nStrong experience with 2.5D / 3D IC packaging, FCBGA and advanced substrate‑based packages, multi‑die and chiplet‑based designs.\nProficiency in industry‑standard tools such as: Cadence Allegro Package Designer (APD / SiP), Siemens Xpedition / Innovator 3D IC, or equivalent.\nExperience working with advanced manufacturing design rules and interface with OSATs.\nGood understanding of Signal Integrity (SI) and Power Integrity (PI) fundamentals and High‑Speed Design concepts.\nStrong communication, presentation, and documentation skills with the ability to work effectively in a team environment.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "NPU Design implementation (Synthesis) Principal/Manager", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-07T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446715068593", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nRole Overview\nThe NPU Synthesis Lead will be responsible for driving synthesis and timing closure for Neural Processing Unit (NPU) IP and subsystems in cutting-edge SoCs. This role involves leading synthesis flows, optimizing for PPA (Performance, Power, Area), and collaborating with architecture, RTL, and physical design teams to ensure high-quality netlists for advanced technology nodes.\nKey Responsibilities\nSynthesis Ownership\nLead RTL-to-gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler, Cadence Genus).\n\nDevelop and maintain synthesis scripts and flows for hierarchical and flat designs.\n\nTiming Closure\nDrive pre-layout and post-layout timing closure across multiple voltage and process corners.\n\nCollaborate with STA teams to resolve setup/hold violations.\n\nPower & Area Optimization\nApply physical-aware synthesis techniques to meet aggressive PPA targets.\n\nImplement low-power strategies using UPF/CPF flows.\n\nConstraint Management\nValidate and maintain SDC constraints for clocks, I/O delays, multi-cycle paths, and false paths.\n\nCross-Functional Collaboration\nWork closely with RTL design, DFT, and physical design teams for seamless handoff.\n\nProvide feedback to architecture and RTL teams for QoR improvements.\n\nQuality Checks\nPerform LEC (Logical Equivalence Check), CLP (Clock/Power checks), and linting.\n\nFlow Innovation\nExplore advanced synthesis methodologies and EDA tool capabilities for better QoR.\n\nTeam Leadership\nMentor junior engineers and drive best practices across synthesis and timing teams.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nRequired Skills\nTechnical Expertise\nStrong knowledge of ASIC design flow: RTL → Synthesis → STA → P&R.\n\nProficiency in synthesis tools (Design Compiler, Genus) and STA tools (PrimeTime).\n\nLow-Power Design\nExperience with UPF/CPF-based flows and multi-voltage designs.\n\nScripting\nAdvanced skills in Tcl, Perl, Python for automation.\n\nEDA Tools\nFamiliarity with Spyglass, Lint, CDC tools, and power analysis tools.\n\nLeadership\nAbility to lead synthesis teams and coordinate with cross-functional groups.\n\nEducation\nBachelor’s/Master’s in Electrical Engineering, Computer Engineering, or related field.\n\nExperience\n15+ years in ASIC synthesis and timing closure, with at least 3 years in NPU or AI processor design.\n\nPreferred\nExperience with advanced nodes (5nm/3nm), hierarchical synthesis, and physical-aware flows.\n\nPrior tape-out experience for NPU or DSP cores.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "PMIC Design Verification Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-07T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719430772", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nDigital Verification Engineer for IPs, ASICs and Chipsets used in Qualcomm Snapdragon power solutions.      \n \nQualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives.\nBut this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in.\n \nDigital Verification Engineer for for Mixed-Signals IPs, ASICs and Chipsets used in Qualcomm Snapdragon power solutions. IPs include telemetry ADCs, 100W+ charging (Quick Charge 5.0), 5G power (mmW, envelope tracking, high performance low noise oscillators etc…) and high efficiency power management (DC-DC charge pumps, bucks and linear regulators).\n* Work includes partnering with international teams in all stages of development from system definition to high-volume (100M+) OEM launches.\n* Digital Verification aspects include all stages of the verification process from test planning, UVM-compliant test-bench architecture, constrained-random stimulus creation, score-boarding and coverage closure.\n* Work includes verification of digital and mixed-signals IPs and exposure to analog behavioral models is a plus.\n* Work includes debugging of complex embedded systems including SOCs, firmware, embedded sequencers.\n* Position includes IP or chip DV ownership including task planning and project risk mitigation.\n* Work in a dynamic team environment with aggressive schedule towards metrics-based high quality target.\n \nPreferred Qualifications\nStrong troubleshooting skills across embedded systems disciplines (digital RTL, Firmware, analog behavioral models)\nStrong communication and organizational skills\nStrong process-oriented mindset.\nExpert-level System Verilog Programming\nAdvanced UVM/SV (Universal Verification Methodology using System Verilog)\nPython or Perl scripting\n \nMinimum Qualifications\nBachelor's degree in Science, Engineering, or related field.\n3+ years ASIC design, verification, or related work experience\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU SRAM Design Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-07T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721337509", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > CPU Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm CPU Engineer, you will lead innovative Central Processing Unit (CPU) design efforts that have a critical impact on industries across the world. Qualcomm Engineers collaborate with cross-functional teams to design, verify, and implement multi-core CPU operations for all Qualcomm Business Units.\n\nMinimum Qualifications:\n•    Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.\n                                                                    OR\nMaster's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.\n                                                                    OR\nPhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.\n\nCPU SRAM Design Engineer\n\nQualcomm is a company of inventors seeking to revolutionize the CPU market in an age of new possibilities. Are you interested in joining Qualcomm’s high performance CPU team as a Memory Designer? You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.\nAs a CPU SRAM Design Engineer, you will design, improve, and analyze digital circuits for memories. The role involves full ownership of custom SRAM and RF designs from schematic capture to analysis and model generation.\n\nMinimum qualifications\nBA/BS degree in Electrical Engineering with 5+ years of practical experience\nExperience with designing SRAM circuits \nExperience in industry standard custom design tools and flows\nExperience with circuit simulation and monte carlo analysis.  \nExperience with static timing analysis.\n\nPreferred qualifications\nMS degree in Electrical Engineering; 7+ years of practical experience\nStrong knowledge of SRAM and Register File techniques with advanced custom circuit implementations\nStrong knowledge of high-performance and low-power design features and techniques\nStrong knowledge of semiconductor device fundamentals\nFamiliar with variation-aware simulation in FinFet and Nanosheet technology nodes\nExperience with custom memory layout designs\nExperience with all memory analysis steps including design entry, functional verification, layout guidance, simulation, timing, power and electrical characterization.\nGood understanding of physical implementation impact on circuit performance\nProficiency with the following tools: NanoTime, Ansys EMIR analysis, ESP-CV,  Liberate power analysis\n\nRoles and Responsibilities\nDevelop custom digital circuits for high-speed and low-power SRAM designs\nSchematic capture\nLayout planning and supervision\nFunctional verification\nSimulation and margin verification\nTiming characterization\nPerforming analysis steps necessary to generate all deliverable collateral models\nInteracting with CAD team to ensure proper and efficient model generation\nInteracting with Physical Design team resolve memory PPA challenges\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Memory Circuit Design Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-07T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721369977", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field.\n\nAdditional Job Description\nWorking experience (2+ years) in preferably Memory design\nCompiler approach of developing embedded SRAM/ROM development\nFundamental know how on bit cell and its characteristics (SNM, WM, Cell current, Standby current, data retention)\nFundamentals of process variability and its effect on memory design\nStrong understanding of Digital/Memory circuit design/layouts\nCritical path modeling concept, various type of models ( RC, C, Pai, ladder, distributive, etc)\nGood knowledge of semiconductor physics in general. Knowledge of and affinity to IC technology and IP design is mandatory\n \n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Memory Circuit Designer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-07T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721370002", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nWorking experience (5+ years) in preferably Memory design\nCompiler approach of developing embedded SRAM/ROM development\nFundamental know how on bit cell and its characteristics (SNM, WM, Cell current, Standby current, data retention)\nFundamentals of process variability and its effect on memory design\nStrong understanding of Digital/Memory circuit design/layouts\nCritical path modeling concept, various type of models ( RC, C, Pai, ladder, distributive, etc)\nGood knowledge of semiconductor physics in general. Knowledge of and affinity to IC technology and IP design is mandatory\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Director , Engineering (GPU Physical Design)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-07T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721434660", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.\n\nMinimum Qualifications\nBachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution\n20+ years of experience in Physical Design/Implementation\n10 years of experience in leading  a team working on high performance cores\nMinimum Requirements:\nPhysical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification,  Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization.\nShould have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions.\nStrong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts\nWell versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes\nGood understanding of clocking architecture.\nShould be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc.\nWell versed with Tcl/Perl Scripting\nExperience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers.\nStrong problem-solving skills and good communication skills.\n \n \n \n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU Core Validation Engineer (Staff/Senior Staff) - CPU Pipeline and uarch experts", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-07T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721035544", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nAs a “CPU Core Validation Engineer(Staff/Sr. Staff)” you would be part of CPU Validation team in CPU org working on validation of CPU core pipeline arch and micro arch features.\n \nRoles and Responsibilities:       \n\nDevelop detailed test plan considering the IP arch and uarch features. \nWork with CPU design and verification teams to develop CPU bring up and functional validation test plans for the IP owned.  \nDevelop validation methodology and test contents to exercise on emulators during pre-Si phase and on Silicon.\nWork with SOC bring up teams, software teams to plan CPU core features bringup and end to end validation. \nTriage and debug failures on Silicon.\nDevelop test contents and testing strategies to assist validation of CPU on silicon.\nWork with CPU verification teams to reproduce silicon fails on emulators and FPGAs. \nWork with design team to suggest, architect new debug features to improve future CPU bringup’s.\n \nMinimum Requirements: \n\nBA/BS degree in CS/EE with 7 to 16 years’ experience.  \n7+ Experience in Silicon Validation and bring up. \nImplementation of assembly, C/C++ language embedded firmware \nExperience with software tool chain including assemblers, C compilers, Makefiles, and source code control tools.\n\nPreferred Requirements: \n\nGood understanding of micro-processor architecture, in domains such as: Cache Coherence, Memory ordering and Consistency, Prefetching, Branch Prediction, Renaming, Speculative execution, and Address Translation/Memory Management.\nKnowledge of Random Instruction Sequencing (RIS) and testing a given design, at the Block/Unit-level and Subsystem/Chip-level for proving correctness.\nExperience in writing Test plans and Assembly code.\nAbility to develop and work independently on a block/unit of the design.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Engineer - ESD Design", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-10-07T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/41220655", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nResponsibilities will include, but are not limited to ESD Architecture Leadership & Strategy\nDefine and own ESD architecture and protection strategy for high-speed I/O portfolios including:\nHBM (High Bandwidth Memory) / DDR / LPDDR PHY I/Os\nPCIe, USB, Ethernet, MIPI, and proprietary interfaces\nLead ESD–I/O co‑design trade‑off decisions, balancing: Aggressive ESD targets (HBM / CDM / MM).Ultra‑low capacitance and leakage requirements\nEye margin, jitter, bandwidth, return loss, and impedance matching\nDrive architectural choices for: Snapback clamps, rail clamps, diode steering networks. Triggered and advanced ESD devices (technology‑dependent). Domain isolation and sequencing protection for sophisticated SoCs\nAdvanced Circuit Design, Modeling & Signoff: Perform and guide ESD circuit design and analysis at block and full‑chip level.\nEstablish simulation methodologies for: Transient ESD stress (TLP‑equivalent behavior). Dynamic clamp triggering and current handling. I/O performance impact (cap loading, ringing, overshoot/undershoot.\nOwn ESD modeling correlation: Work with device/modeling teams on compact models (dynamic R, triggering, CV behavior). Drive correlation between SPICE simulations, TLP/VF‑TLP, and silicon results. Act as the final technical authority for ESD Design reviews and signoff.\nSilicon Debug, Reliability & Qualification Ownership: Lead silicon-level ESD failure analysis across products and generations.\nDrive root cause analysis for: HBM/CDM failures. Leakage and performance degradation. Latch‑up and substrate‑coupling issues\nCollaborate deeply with reliability: Define corrective actions and preventive methodologies. Own ESD qualification strategies and ensure first‑pass silicon success.\nPhysical Design, Layout & Technology Engagement: Define company-wide layout guidelines for ESD devices. Current uniformity, ballasting, guard rings. Substrate/well engineering and isolation standard processes. Power clamp placement and return path integrity\nPartner with technology, process, and PDK teams to: Influence ESD-friendly process features. Enable scalable ESD solutions in sophisticated node & Ensure ESD robustness across multiple packages and IO ring configurations.\nMulti-functional & Interpersonal Leadership: Serve as the ESD subject-matter guide (SME) across the organization.\nProvide strategic guidance to: I/O and PHY design teams. PDN, package, and board-level engineers. Product engineering and manufacturing. Mentor and technically develop junior and senior ESD/design engineers & Drive methodology reuse, IP standardization, and design standard processes across programs.\nConsistent track record of: Delivering production silicon meeting aggressive ESD and performance targets. Leading ESD technical decisions for sophisticated, high‑volume products.\nDeep expertise in: HBM, CDM, MM, latch‑up mechanisms & High-speed signal integrity fundamentals and constraints\nStrong command of: SPICE-based simulators (Spectre, HSPICE) & Physical layout review and ESD signoff flows\nLeadership & Soft Skills: Recognized technical authority with strong executive‑level interpersonal skills. Ability to make and defend data‑driven architectural trade‑offs. Mentor‑first attitude with passion for growing technical talent. Comfort operating in ambiguous, fast‑paced, first‑principles problem spaces.\nProven ability to leverage AI‑assisted (vibe) coding techniques to improve efficiency or automate design and analysis methodologies\nLeverage AI tools to automate the tools and workflow\nApplying Artificial Intelligence in workflows to improve build efficiency\nWhat Success Looks Like\nESD requirements consistently met without compromising high-speed I/O performance.\nPredictable, silicon‑correlated ESD signoff across projects.\nReusable ESD IP and methodologies deployed across multiple products and nodes.\nRequirements/Qualification\nB.Tech / M.Tech / PhD in Electrical / Electronic Engineering or related team.\n8+ years of hands‑on experience in: ESD circuit design and protection architecture& High-speed I/O or mixed-signal chip environments Department Intro... A few sentences about the department here.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Layout Engineer, Senior", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-07T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718021620", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Services Group, Engineering Services Group > Layout Engineer\nGeneral Summary:\nDevelops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues.\n\nMinimum Qualifications:\n•    Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.\n                                                                    OR\nAssociate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.\n                                                                    OR\nHigh School diploma or equivalent and 8+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.\n\n•    4+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap).\n\n8 to 12 years of expertise in high speed / Analog / Mixed signal layouts in lower nodes with Bachelor's in Electrical or Electronics Engineering or equivalent. Owning and delivering top‑level physical layout for complex analog, digital, or mixed‑signal designs across technology nodes.\nProficient in meeting layout performance, reliability, manufacturability, and quality requirements, adhering to foundry DRC/LVS and internal design guidelines. Proficient in Cadence Virtuoso layout XL / GXL / EXL and Calibre physical verification flow and expertise in debugging skills.\nAbility to work & communicate effectively with global engineering teams. Effectively multitask and lead parallel projects, coordinating execution and priorities by well collaborating with the team members.\nCapable of leveraging automation and having scripting expertise to eliminate repetitive manual tasks, improving efficiency and reducing total turnaround time. Act as a technical point of contact for layout‑related discussions with design, verification, CAD, and technology teams.\nIdentify risks early and proactively develop mitigation plans to ensure on‑time delivery of layout milestones.\nMentor junior layout engineers by reviewing work, sharing best practices, and promoting design quality and efficiency\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SoC Verification", "company": "NXP", "location": "Noida", "date_posted": "2026-10-07", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Noida/SoC-Verification_R-10066969", "is_hardware": true, "platform": "workday", "jd_text": "Job Summary\nThe Verification role will involve many aspects of functional verification using most effective methodologies in context of Subsystem/SoC/System Level. A strong ability to map requirements into a traceable verification plan is important. Responsibilities encompass the development of verification test bench, development of verification components, test case development for simulation , debugging failures and creating simulation cases for various scenarios\nExpectations include:\nVerification planning;\nDevelopment of verification test bench components such as drivers, monitors, response checkers as well as use most advanced UVM VIPs\nDevelopment of direct and constrained-random stimulus\nUnderstands and analyzes RTL code, functional, assertion coverage results\nUnderstands and develops system Verilog assertions\nStrong skills in debug, failure re-creation and root cause analysis\nApplicant should have efficient debugging and logic skills\n \nJob Qualifications\nBTech/MTech with 5-10 years experience in SOC/Subsystem verification of complex multi-million gate designs with multiple clocks/power domains. Experience in below areas with strong hands on knowledge in below areas is needed\nC and UVM/SV based test environment,\nHDLs (Verilog/VHDL), simulators (Synopsys/Cadence/Mentor)\nUnderstanding of the design/architecture and ability to debug RTL/Gate netlist\nCoverage driven verification , regression management\nMicrocontroller architecture, ARM Cores, Interconnect(NIC, FlexNoC), Cache Coherency\nBus Protocols like AHB, AXI, ACE\nFollowing skills will have additional value:Memory controllers (Flash, SRAM,DDR3/4/LPDDR) \nProtocols like PCIe, MIPI, GPU (Graphics processing), VPU (Video Processing), Ethernet, USB, Image\nFormal verification methodologies and Apps, AVIP, PinMuxing Verification, Randomization\nLow Power intent verification using CPF, UPF\n\n \n\nMore information about NXP in India...\n\n#LI-2734", "jd_status": "stored"}, {"title": "Senior Physical Verification Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-07", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Physical-Verification-Engineer_JR2027234", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking passionate, highly motivated, and creative design engineers to be part of a team working on industry-leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n \nWhat you’ll be doing:\nIn this position, you'll own physical verification for the full chip — taking designs from block-level assembly through full-chip integration and tapeout on the latest process nodes like TSMC A16 and TSMC 3nm.\nOwn full-chip physical verification signoff — DRC, LVS, antenna — across block, partition, and top levels, and drive convergence to a clean tapeout database.\nPush the frontier of 3D die stacking and heterogeneous integration — verifying die-to-die interfaces and stitching together dies built on entirely different process nodes into a single working system.\nBe at the leading edge of Angstrom class technology, enabling signoff for breakthroughs like Super Power Rail backside power delivery and nanosheet GAA transistors.\nReinvent how signoff is done with AI — building ML- and LLM-powered automation for root-cause analysis, and flow optimization.\nPartner with the methodology and CAD/technology groups to define and deploy correct-by-construction flows that catch issues early and reduce signoff iterations.\nCross-functional collaboration with P&R, Timing, IR, Library team to drive design closure on time.\n\nWhat we need to see:\nBE/BTECH/MTECH, or equivalent, with 5+ years of experience in Physical Design Verification, full chip integration and tapeouts on the latest technology nodes.\nStrong understanding of  Physical Implementation and VLSI design concepts.\nExpertise in signoff tools like Calibre, ICV, EDI, FC.\nGood understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure.\nGood problem-solving skills.", "jd_status": "stored"}, {"title": "Senior Physical Design AI Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-07", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Physical-Design-AI-Engineer_JR2026884", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, creating demand for the highly scalable and massively parallel computing capabilities in which NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities—challenges that are difficult to solve, that only we can address, and that matter to the world. This is our life’s work: amplifying human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nNVIDIA is seeking passionate, highly motivated, and creative engineers to join our Physical Design AI team. In this role, you will combine deep physical design knowledge with modern AI technologies to build intelligent, scalable solutions for our Physical Design Implementation teams. You will work closely with domain experts to understand complex implementation challenges and develop agentic AI solutions that improve productivity, efficiency, and quality across NVIDIA product lines. This position offers the opportunity to make a real impact in a dynamic, technology-focused company whose products span consumer graphics, accelerated computing, self-driving cars, and the rapidly growing field of artificial intelligence. We have built a team of exceptional people across the globe whose mission is to push the boundaries of what is possible today and define the platform for the future of computing.\n\nWhat you’ll be doing:\nWork with Physical Design Implementation teams to understand complex problems and build agentic AI solutions for all product lines.\nDeliver efficient, token-optimized AI solutions that consistently produce high-quality outputs.\nProvide continuous support, maintenance, and enhancements for AI solutions.\nBenchmark solutions across various AI models to evaluate and improve their effectiveness.\nResearch and innovate new AI methods to address evolving physical design challenges.\nBuild robust regression testbenches to validate the quality, reliability, and performance of AI solutions.\n\nWhat we need to see:\n4+ years of experience in Physical Design with BE/BTech/MTech degree, or equivalent experience.\nStrong understanding of the RTL-to-GDSII flow and design implementation in leading process technologies, including synthesis, place and route, clock tree synthesis, timing convergence, and layout closure.Good understanding of AI concepts such as tokens, KV cache, context windows, skills, agents, subagents, and hooks.\nHands-on experience with AI tools such as Claude, Codex, and Cursor. Strong knowledge and experience in standard place-and-route flows. Experience with Synopsys ICC2 and Cadence Innovus flows is preferred.\nGood automation skills in Tcl, Python, and tool-specific scripting for one or more industry-leading place-and-route tools.\nAbility to multitask and work effectively in a global environment. Excellent communication skills, strong motivation, and strong analytical and problem-solving abilities.\n\nWidely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer you and your family at NVIDIA Benefits.\n\nNVIDIA is committed to encouraging a diverse work environment and is proud to be an equal opportunity employer. As we highly value diversity among our current and future employees, we do not discriminate—including in our hiring and promotion practices—on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law. We will ensure that individuals with disabilities are provided reasonable accommodations to participate in the job application or interview process, perform essential job functions, and receive other benefits and privileges of employment. Please contact us to request accommodation.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "FPGA Prototyping Applications Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-07", "url": "https://careers.synopsys.com/job/bengaluru/fpga-prototyping-applications-engineer/44408/101661090720", "is_hardware": true, "platform": "talentbrew", "jd_text": "Alternate Job Titles\nFPGA Prototyping Applications Engineer\nStaff Application Engineer, Verification\nHAPS Prototyping Solutions Engineer\nSenior Technical Applications Engineer, FPGA-Based Prototyping\nField Applications Engineer, FPGA Prototyping\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nYou are at your best when the work is real—when the design is enormous, the schedule is unforgiving, and “good enough” isn’t good enough because someone needs the prototype to boot, run, and reveal the truth. You thrive in the messy middle between theory and reality, where success comes from making smart tradeoffs, staying relentlessly organized, and refusing to let details slip through the cracks. You don’t romanticize late nights or fire drills, but you stay steady under pressure and bring a calm, practical energy that helps everyone else keep moving.\nYou approach prototyping like a product, not a one-time stunt. You think constantly about who will use it next—software teams, validation engineers, architects—and you shape decisions around usability, repeatability, and speed of iteration. You’re the person who turns vague goals into crisp plans, sets expectations early, and communicates progress in a way that builds confidence rather than surprise. When something fails, you get curious, not defensive. You narrow the problem, test assumptions, and keep digging until the root cause is understood and the fix is durable.\nYou’re also deeply collaborative. You listen hard, read the room, and adapt your style to the audience—whether you’re guiding a customer through a tough constraint conversation or aligning internal teams around a path forward. You take ownership naturally, you follow through, and you leave people feeling supported, informed, and ready for the next milestone.\nWhat You'll Be Doing\nProvide pre-sale and post-sale technical support for Synopsys HAPS-based prototyping solutions, including HAPS hardware and ProtoCompiler software\nWork directly with customers to prototype multi-million gate ASIC designs, guiding them through design partitioning, FPGA synthesis, system planning, and RTL debug\nLead technical evaluations of HAPS products at customer sites, diagnosing complex design issues, resolving timing closure problems, and optimizing prototyping flows\nDevelop and deliver customer training materials, application notes, and technical articles based on real deployment experience and customer use cases\nCollaborate with R&D teams to escalate product quality issues, propose new features, and contribute to improving quality of results in HAPS tools and flows\nTravel to customer sites as needed to support product deployments, troubleshoot critical issues, and enable successful prototype bring-up\nScript automation solutions in TCL and Python to streamline customer workflows and improve prototype performance\nThe Impact You Will Have\nEnable customers to catch critical bugs in multi-million gate SoCs before tape-out, saving them months of schedule risk and the cost of silicon respins\nAccelerate time-to-market for products across smartphones, network devices, and medical instrumentation by delivering working FPGA prototypes that software teams can develop against\nShape the roadmap of HAPS products by feeding real customer pain points and deployment challenges directly back to engineering teams\nBuild reusable methodologies, flows, and training content that scale across Synopsys's global customer base and reduce time to first prototype\nAct as the technical expert for HAPS within Synopsys, influencing how sales teams position the product and how customers adopt it\nHelp customers navigate the complexity of Xilinx Ultrascale and Versal architectures, turning prototyping from a bottleneck into a competitive advantage\nEstablish long-term technical relationships with the engineering teams at the world's leading chip companies\nWhat You'll Need\nBachelor's degree with 5+ years of relevant experience, or Master's degree with 3+ years\nHands-on experience with FPGA-based prototyping, including taking complex ASIC designs and successfully mapping them to FPGA hardware\nDeep knowledge of digital design fundamentals, VHDL, Verilog, or SystemVerilog, and experience with synthesis and simulation flows\nProven ability to debug FPGA designs and handle complex timing constraints, particularly on Xilinx Ultrascale or Versal device families\nStrong scripting skills in TCL and Python for automation and flow development\nExperience working directly with customers in a technical support, field applications, or consulting capacity is a strong plus\nFamiliarity with Synopsys verification tools such as VCS, Verdi, or VC Formal is a plus\nWho You Are\nYou can walk into a customer meeting, quickly assess where their prototype effort is stuck, and propose a concrete path forward without needing perfect information\nYou are comfortable explaining a complex partitioning tradeoff to a customer architect in a way that makes the technical and business implications clear\nYou do not get rattled when a customer escalation lands on your desk at 4 p.m. on a Friday, you treat it as a puzzle to solve, not a crisis to panic over\nYou write clear, useful documentation because you have been on the receiving end of bad app notes and refuse to inflict that on others\nYou know when to push back on a customer request that will lead them down a dead end, and you do it in a way that builds trust instead of burning it\nYou are organized enough to juggle multiple customer engagements, travel schedules, and internal projects without dropping threads\nThe Team You'll Be Part Of\nYou will join the HAPS Application Engineering team within Synopsys's Go-to-market organization. This team acts as the technical experts for HAPS FPGA-based prototyping products across Synopsys. You will work closely with sales teams during pre-sale evaluations, directly with customers during deployments and support engagements, and with R&D teams to influence product direction. The team supports customers globally, and you will collaborate with application engineers in other regions to share knowledge and solve complex prototyping challenges.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior Verification Engineer", "company": "Nokia", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-10-07", "url": "https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/40962", "is_hardware": true, "platform": "oracle", "jd_text": "As a Senior Verification Engineer for Optical Transport, you will play a crucial role in ensuring the quality and reliability of DWDM transmission systems. Your responsibilities will include designing and executing test cases, automating testing processes, and collaborating closely with architects and developers to enhance product performance. This is an excellent opportunity to deepen your expertise in optical networking and automation.\n\nResponsibilities\nDesign and execute comprehensive test plans to validate new DWDM transmission system features.\nIdentify, analyze, and report software defects, collaborating with architects and developers for resolution.\nDevelop and implement automated test scripts to enhance efficiency and coverage.\nConduct regression testing with various network configurations to ensure system stability.\nGain expertise in optical networking technologies, including DWDM and high-speed data transmission.\nEnhance debugging and troubleshooting skills by working with complex networking scenarios.\nWork closely with cross-functional teams to drive continuous quality improvements.\nStay updated with the latest advancements in automation and optical transport systems.\n\nQualifications\nYou have:\nB.E/M.Tech in Engineering, with a strong background in telecommunications, networking, or related fields with 8-12 years of experience in testing and validating optical networking technologies, including DWDM and OTN.\nExperience in designing and executing comprehensive test plans to validate new DWDM transmission system features.\nDeep domain expertise with a strong system-level understanding and Data-driven decision-making skills.\nAwareness of AI/ML technologies and practical experience using Generative AI tools and Strong strategic thinking and execution excellence.\n \nIt would be nice if you also had:\nExperience in developing and implementing automated test scripts to enhance efficiency and test coverage.\nExperience in conducting regression testing across various network configurations to ensure system stability and performance.\nFamiliarity with industry-standard tools and technologies related to optical transport networks.\nAbility to identify, analyze, and report software defects, collaborating with architects and developers to resolve issues.\n\nAbout the company\nAdvancing connectivity to secure a brighter world.\n\nNokia is a global leader in connectivity for the AI era. With expertise across fixed, mobile and transport networks, powered by the innovation of Nokia Bell Labs, we’re advancing connectivity to secure a brighter world. \n\nLearn more about life at Nokia.\n\nOur recruitment process\n\nWe act inclusively and respect the uniqueness of people. Our employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.\n\nIf you’re interested in this role but don’t meet every listed requirement, we still encourage you to apply. Unique backgrounds, perspectives, and experiences enrich our teams, and you may be just the right candidate for this or another opportunity.\n\nThe length of the recruitment process may vary depending on the specific role's requirements. We strive to ensure a smooth and inclusive experience for all candidates. Discover more about the recruitment process at Nokia.\n\nAbout the organization\nSome of our benefits in India:\n\nFlexible and hybrid working arrangements to support work–life balance\n\nHealth and well-being support – medical insurance for you and your family, health check-ups, life and accident insurance, well-being programs, and employee resource groups \n\nA minimum of 90 days of Maternity and Paternity Leave based on eligibility\n\nPersonal Support Service 24/7 – a confidential support channel open to all Nokia employees and their families in challenging situations\n\nCareer growth & mobility – technical career paths, job rotations, international assignments, and relocation support\n\nContinuous learning – technical certifications, mentoring programs, coaching, and digital learning platforms\n\nOpportunities to innovate and contribute through Nokia’s research and development environment\n\nRecognition programs that celebrate outstanding contributions\n\nWorkplace support – ergonomic working support and mobile device programs based on eligibility", "jd_status": "stored"}, {"title": "Subsystem/SoC Level Verification Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-10-07", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Subsystem-SoC-Level-Verification-Engineer_R026376", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nHe/she should have strong knowledge of the following with 12-15 years of experience in Ethernet Subsystem/SoC Level Functional verification\nWorking experience in Ethernet Subsystem/SoC verification\nExpertise to develop verification environments using System Verilog and UVM \nExpertise to develop BFMs / Checkers / monitors / Scoreboards\nMust have developed block/system level verification plans and tests.\nMust have capability to debug test failures to find the root cause.\nMust have worked on code / functional coverage.\nExperience in constrained random verification.\nDomain skills: Ethernet (MAC, PCS and SerDes)/SoC verification\nGate-level /SDF simulations\nKnowledge of scripting languages like Perl, Tcl\nFlexible to work in any IP/Subsystem/SoC projects\n\nCAD Tools: Cadence/Synopsys\nEducation Qualification: Bachelors/Master’s in Electronics/Computer Engg\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Analog Circuit Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-07", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Analog-Circuit-Design-Engineer_JR0287856", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact:\n\nAs an Analog Circuit Design Engineer, you will play a pivotal role in designing advanced analog circuits for cutting-edge technologies. Your day-to-day work will focus on creating high-performance, power-optimized circuits for analog and mixed-signal IPs in advanced process nodes. By collaborating with cross-functional teams, you will shape Intel's ability to deliver robust and innovative solutions that meet global technology demands.\n\nBusiness Group:\n\nYou will join the Central Engineering Group (CEG), a team dedicated to enabling Intel's success through world-class engineering capabilities. CEG is focused on the development of state-of-the-art technologies, contributing to Intel's leadership in innovation and product excellence.\n\nKey Responsibilities:\n\n- Design, develop, and optimize analog circuits for high-speed SerDes, memory interfaces, and advanced process nodes.\n- Extract key chip parameters, simulate analog behavior models, and validate designs against block specifications.\n- Create and execute comprehensive test plans to ensure functionality, reliability, and performance.\n- Collaborate with architecture and layout teams to optimize circuits for power, area, timing, and electrical robustness.\n- Perform post-silicon debug to analyze and resolve circuit issues, ensuring readiness for high-volume manufacturing.\n- Continuously improve design methodologies to enhance innovation, efficiency, and turnaround times.\n- Utilize industry-standard tools such as Cadence Virtuoso, SPICE simulators, and post-layout extraction tools.\n\nQualifications:\nMinimum Qualifications:\n\n- Bachelor's degree in Electrical Engineering or a related field with 6+ years of experience, or Master's degree with 4+ years of experience, or PhD with 2+ years of experience in analog circuit design.\n- Proficiency in designing high-speed analog/mixed-signal circuits, including PLLs, SerDes, regulators, and clocking circuits.\n- Expertise in CMOS design fundamentals, circuit simulation tools, and modeling.\n- Experience with EDA tools such as Cadence Virtuoso, Spectre, PrimeSim, DRC, LVS, and post-layout extraction.\n- Familiarity with optimizing circuits for power efficiency, area, and yield goals.\n\nPreferred Qualifications:\n\n- Experience in post-silicon validation, reliability testing, and debugging.\n- Knowledge of scripting languages such as Python, TCL, or Perl for design automation tasks.\n- Familiarity with high-speed interface interconnect modeling and simulation.\n- Strong analytical and problem-solving skills, along with a demonstrated ability to lead technical initiatives.\n- Proven ability to work in fast-paced environments and mentor junior engineers.\n\nIf you are excited about driving innovation and crafting impactful analog designs, we encourage you to apply and contribute to transforming technology at Intel.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "ASIC Digital Design - Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-07", "url": "https://careers.synopsys.com/job/bengaluru/asic-digital-design-staff-engineer/44408/101661090704", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nYou have spent years learning that the hardest bugs to catch are the ones simulation will never hit, and you have built the muscle to prove they cannot happen at all. Formal verification is not a side skill for you, it is the primary tool you reach for when correctness matters more than coverage metrics. You know that a well-written assertion is worth a thousand directed tests, and you have debugged enough counterexamples at 3 a.m. to tell the difference between a real bug, a missing assumption, and a property that was just worded wrong.\nReading RTL is second nature. You can look at a state machine or a FIFO controller and start sketching the properties in your head before anyone asks. When a proof will not close, you do not give up, you add a cut point, split the case, tighten the constraint, or abstract the helper logic until the engines can finish. You have worked with designers who trust formal and designers who do not yet, and you have learned how to bring both groups along.\nAt Synopsys, you will own formal sign-off for real blocks that ship in customer silicon, and you will help build the next generation of verification engineers who think proof-first.\n\nWhat You'll Be Doing\nOwn formal property verification end to end for assigned digital RTL blocks, from clocks and resets through proof closure and final sign-off\nRead design specifications and RTL to write SystemVerilog Assertions, assumptions, and cover properties that capture the intended behavior and legal input space\nBuild and maintain formal testbenches including bind files, helper logic, abstraction wrappers, and constraint sets in SystemVerilog\nRun formal tools, tune solver engines and effort settings, and push proof bounds on hard properties until they close or you root-cause why they cannot\nDebug counterexamples to determine whether the issue is in the RTL, the property, or the constraint set, and work directly with designers to resolve it\nApply targeted abstractions such as cut points, case splits, blackboxing, and over-constraints when a proof will not converge, then systematically relax them to restore completeness\nReview simulation testbenches and specifications to identify missing legal-input assumptions, and keep formal constraints aligned with how the block is actually used\nTrack and report property status across proven, covered, falsified, and inconclusive buckets, and clearly communicate coverage gaps and open issues to the design and verification leads\nMentor and guide recent graduate engineers on the team, helping them build practical formal verification skills and develop sound debugging instincts\n\nThe Impact You Will Have\nCatch corner-case bugs before tapeout that simulation would never reach, preventing costly respins and field failures\nDeliver mathematically proven correctness guarantees on critical control logic, protocol interfaces, and safety-critical paths that customers depend on\nReduce verification closure time by proving entire classes of behavior exhaustively, instead of writing thousands of constrained-random tests\nBuild a library of reusable formal testbench components and assertion IP that accelerates bring-up on future blocks and projects\nRaise the formal verification capability of the team by teaching engineers how to think in properties, not just in tests\nImprove design quality upstream by surfacing ambiguous specifications and unintended corner cases early, before RTL is frozen\nEnable faster design iteration by providing rapid feedback on whether a proposed RTL change breaks proven invariants\n\nWhat You'll Need\n3 to 5 years of hands-on experience in semiconductor verification with substantial ownership of formal property verification, not just exposure or side projects\nStrong working knowledge of SystemVerilog and SystemVerilog Assertions including concurrent assertions, sequences, properties, assume, assert, cover, bind, and clocking blocks\nPractical experience closing formal proofs including constraint debugging, counterexample trace analysis, reset and clock modeling, and tuning engines to reach useful proof bounds\nAbility to read and understand synthesizable RTL in SystemVerilog or Verilog, and to trace waveforms and formal counterexamples back to design intent\nComfort working in Tcl-based formal tool flows including compile, elaborate, check commands, and automated reporting\nExperience with at least one commercial formal verification tool such as Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, or OneSpin is a strong plus\n\nWho You Are\nYou can look at a block specification and start writing the top five assertions before the RTL is even written, because you have learned to think in invariants and legal transitions\nWhen a proof fails, you do not immediately assume it is a bug, you methodically check the property wording, the assumptions, the clock and reset modeling, and the abstraction before escalating\nYou can explain to a designer why their fix broke a proven property, or why a counterexample trace shows a real issue, in a way that builds trust instead of defensiveness\nYou are comfortable working with recent graduates and walking them through a counterexample step by step, showing them how to read the trace and connect it back to the RTL\nYou keep your formal testbenches organized and documented well enough that someone else can pick up your work mid-project without starting over\nYou know when to push a proof harder and when to split the problem, abstract a submodule, or bring in the design team for a sanity check on intent\n\nThe Team You'll Be Part Of\nYou will be part of the IPG Customer Engagement and Infrastructure team, working on formal verification for IP blocks that are delivered to customers and integrated into their silicon designs. This team supports the quality and correctness of Synopsys IP products used across a wide range of customer applications.\n\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "SoC Logic Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-07", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/SoC-Logic-Design-Engineer_JR0286603", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nAs a SoC Logic Design Engineer, you will play a pivotal role in developing and integrating logic designs into complex System-on-Chip (SoC) architectures. Your day-to-day efforts will focus on RTL coding, simulation, and quality checks to ensure designs meet power, performance, timing, and area targets. You will collaborate cross-functionally to validate design features and drive corrective actions, ensuring the highest standards of performance and reliability for Intel's cutting-edge technologies.\n\nBusiness group\nYou will be part of Intel's Technology Development Group. As part of this team you will work on Foudnational IP TestChip designs that drive innovation and support Intel's broader mission to shape the future of technology. This group focuses on the development of advanced methodologies, tools, and design solutions for next-generation products, fostering collaboration and excellence across diverse technical domains.\n\nKey Responsibilities\n- Develop RTL designs and integrate logic components into SoC architectures.\n- Perform simulations and quality assurance checks to ensure design reliability and compliance with power, performance, area, and timing goals.\n- Collaborate with IP providers to integrate and validate IPs at the SoC level.\n- Review verification plans to ensure design features are thoroughly tested and implement corrective actions for failing RTL tests.\n- Optimize logic designs using advanced strategies, tools, and methods.\n\nQualifications:\nMinimum Qualifications\n- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 3+ years of relevant experience OR Master's degree with 2+ years of experience OR PhD with no prior professional experience.\n- Proficiency in RTL coding, logic design, and System Verilog.\n- Hands-on experience with digital design fundamentals and SoC integration.\n- Familiarity with scripting languages like Perl or TCL for design automation.\n\nPreferred Qualifications\n- Experience with timing/power convergence tools and methodologies.\n- Knowledge of design closure techniques for advanced technology nodes (e.g., 10nm or lower).\n- Exposure to synthesizable Verilog/System Verilog and simulation tools.\n- Strong analytical and problem-solving skills, coupled with clear and proactive communication.\n\nWe invite you to bring your skills, curiosity, and passion for innovation to Intel and join a collaborative environment where your contributions will drive meaningful advancements in technology.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Staff Field Applications Engineer", "company": "Lattice", "location": "China - Remote", "date_posted": "2026-10-07", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/China---Remote/Senior-Field-Applications-Engineer_R-103355", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\n\nWe are seeking an experienced Staff FAE to join our South China team, based in Shenzhen, China. This role is responsible for supporting the design-in and production deployment of Lattice FPGA solutions across key markets, including automotive, industrial, video, and server applications. The successful candidate will work closely with customers, channel partners, sales teams, and global R&D organizations to help drive customer success and business growth.\n \nKey Responsibilities:\n\n1. Pre-Sales Technical Support (Design-in)\nServe as the primary technical interface for customers, providing application support for Lattice FPGA, CPLD solutions.\nRecommend device selection and solution architectures based on customer requirements and application scenarios, including industrial control, automotive, video bridging, video processing, server, and medical applications.\nPartner with sales teams on customer visits, technical training, solution demonstrations, and validation activities to drive new design opportunities.\n\n2. Customer Project Support (Design-win)\nSupport customers throughout the FPGA development lifecycle, including design reviews, tool training, debugging, and board-level troubleshooting.\nResolve technical challenges related to timing closure, resource utilization, device configuration, and system integration.\nundefined.\n\n3. Post-Sales Production Support\nProvide technical and quality support for customers during production and post-production phases.\nCollaborate with Applications Engineering and Quality teams to investigate issues, perform root cause analysis (RCA), and implement corrective actions. \n\n4. Channel Enablement and Market Intelligence\nDeliver technical training and project support to distributor FAE teams to enhance their technical capabilities.\nCollect customer feedback, competitive intelligence, and industry trends to provide input on product planning and market strategies.\n\nQualifications:\n\nBachelor's degree or above in Electrical Engineering, Microelectronics, Communications Engineering, Computer Science, or a related field.\n10+ years of electronics industry experience, including at least 5 years in FPGA development or technical support (FAE/AE).\nStrong knowledge of the Lattice FPGA portfolio, including Avant, Nexus, ECP, and MachXO device families.\nProficiency with Lattice development tools such as Radiant, Diamond, and Propel.\nHands-on experience with FPGA design flows, including RTL design, simulation, timing analysis, implementation, and debugging.\nProficient in Verilog, System Verilog, or VHDL.\nExperience designing, integrating, or debugging high-speed interfaces such as PCIe, SerDes, MIPI, DDR, Ethernet, HDMI, and DP/eDP.\nStrong board-level debugging skills with hands-on experience using oscilloscopes, logic analyzers, and other test equipment.\nKnowledge of at least two application areas, including automotive electronics, industrial automation, video processing and bridging, or server systems.\nStrong analytical and problem-solving skills with a proactive and self-motivated mindset.\nExcellent customer-facing communication and cross-functional collaboration skills.\nStrong written and verbal English communication skills, with the ability to collaborate effectively with global R&D teams.\n\n我们正在寻找一位资深现场应用工程师，工作地点位于深圳，加入Lattice华南区团队，负责支持 Lattice FPGA 产品在汽车电子、工业控制、视频及服务器等重点市场的设计导入与量产项目。候选人需具备扎实的 FPGA 技术能力、丰富的行业应用经验以及良好的客户沟通技巧，并能够与销售、代理商及全球研发团队协作，推动客户项目成功落地。\n \n岗位职责：\n\n1. 售前技术支持（Design-in）\n作为客户技术接口，负责 Lattice FPGA、CPLD 等产品的技术推广和应用支持；\n根据客户的具体项目场景（如工业控制、车载、视频桥接、视频处理、服务器、医疗设备等）提供精准的器件选型与方案评估；\n配合销售团队进行客户拜访、技术培训、方案演示及测试验证，推动新项目导入。\n\n2. 客户项目落地支持（Design-win）\n\n跟进客户 FPGA 项目开发全过程，包括原理图审查、工具培训、时序约束、工程移植、代码调试及板级调试；\n协助解决开发及量产过程中遇到的技术问题，包括时序收敛、资源优化、配置加载及现场故障分析。\n\n3. 售后量产技术维护\n负责客户量产后的质量与技术支持，妥善处理量产异常、批次差异及工艺适配等问题；\n负责收集客户一线的失效现象与测试数据，进行故障复现，并积极配合 应用工程师团队和质量团队完成问题定位、根因分析（RCA）、对策输出与闭环跟进。\n\n4. 渠道赋能与市场反馈\n为代理商 FAE 提供技术培训与项目支持，提升整体技术能力；\n收集客户需求、竞争动态及行业趋势，为产品规划和市场策略提供建议。\n \n任职要求：\n电子工程、微电子、通信工程、计算机科学或相关专业本科及以上学历；\n10年以上电子行业经验，其中至少5年 FPGA 研发或高级技术支持（FAE/AE）经验。\n熟悉 Lattice FPGA 产品生态，包括 Avant、Nexus、ECP、MachXO 等系列；\n熟练使用 Lattice Radiant、Diamond、Propel 等开发工具；\n具备 FPGA 全流程开发经验，包括 RTL 设计、仿真、时序分析与调试；\n熟练掌握 Verilog/System Verilog 或 VHDL。\n具备高速接口（PCIe、SerDes、MIPI、DDR、Ethernet、HDMI、DP/eDP 等）设计或调试经验；\n具备板级硬件调试经验，能够熟练使用示波器、逻辑分析仪等测试设备；\n对汽车电子、工业控制、视频处理/桥接、服务器等领域中的至少两个行业有较深入理解。\n具备较强的分析问题和解决问题能力，自驱力强；\n良好的客户沟通和跨团队协作能力；\n具备良好的英语读写及口语沟通能力，能够与全球研发团队进行技术交流。\n\n#LI-DNP\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nChinaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Staff Engineer Verification -IP Digital Functional Verification ", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-10-06T16:18:49+00:00", "url": "https://jobs.infineon.com/careers/job/563808972118487", "is_hardware": true, "platform": "eightfold", "jd_text": "#WeAreIn to make sure that our circuits are designed to perfection. Are you in?\n\nYour role\nKey responsibilities in your new role\n\n         Lead\nsubtasks in IP/SoC verification. Contribute significantly to the verification\nof complex IPs/SoCs\nCreate\nverification requirements at the IP/SoC level based on design requirements and\ndevelop UVM test benches and formal verification environments\nSupport\nthe development of verification infrastructure at the IP/chip level as required\nSupport\ndifferent areas of IP verification, including RTL simulation, formal\nverification, power-aware verification, and gate-level simulation\n\n \n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor's degree (B.E./B.Tech.) in Electrical/Electronics Engineering or Master's degree (M.E./M.Tech.) in VLSI Design or a related field\n\nMinimum 5+years of relavent experince \nStrong understanding of ASIC verification methodologies, concepts, and industry best practices\n\nProficient in Verilog, SystemVerilog,and UVM with hands-on experience in verification environment development\n\nProven ability to develop and maintain IP and SoC-level testbenches for complex semiconductor designs\n\nExperience in IP/SoC verification across a variety of applications and design domains\n\nKnowledge of power-aware verification and gate-level verification (GLS) is highly desirable\n\nFamiliarity with industry-standard protocols and interfaces is an added advantage\n\nExposure to formal verification techniques and tools is considered a plus\n\nStrong analytical, debugging, and problem-solving skills, with the ability to work effectively in both independent and collaborative environments\n\nExcellent communication and stakeholder collaboration skills, with a focus on delivering high-quality verification solutions\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nGowri Shenoy\n\nhttps://www.linkedin.com/in/gowri-shenoy-33894217/", "jd_status": "stored"}, {"title": "Senior Staff  Engineer - DFT", "company": "Infineon", "location": "Bangalore", "date_posted": "2026-10-06T15:39:31+00:00", "url": "https://jobs.infineon.com/careers/job/563808972098222", "is_hardware": true, "platform": "eightfold", "jd_text": "#WeAreIn to leverage synergies contributing to Infineon’s product development. Are you in?\n\nYour role\nKey responsibilities in your new role\n\nResponsible for SoC DFT Architecture definition/implementation/verification/silicon debug of SoC/Full Chip\nNeed to implement Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures\nResponsible for ATPG, DRC analysis, Test coverage debug, Memory BIST implementation and verification\nOwner ship of JTAG/BSCAN/iJTAG, P1500  implementation and verification, Stuck at/TDF/Bridging/Cell-aware/iddq fault models\nGood debug skills in ZERO delay and SDF based scan/MBIST/JTAG simulations\nHands on experience in analysis and debug of above-mentioned test domains\nHands of experience in post silicon debug of  scan/MBIST patterns/yield fall out\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor's degree (B.E./B.Tech.) in Electrical/Electronics Engineering or Master's degree (M.E./M.Tech.) in VLSI Design or a related field\n\n12+ years of experience in DFT implementation, verification, and post-silicon debug\n\nStrong understanding of the complete ASIC design flow\n\nHands-on experience with LEC, CLP, and power analysis methodologies is highly desirable\n\nProven expertise in delivering complex SoC designs, encompassing DFT specification development, implementation, verification, and post-silicon debug\n\nSelf-driven professional with a passion for continuously improving DFT methodologies and design processes\n\nExcellent analytical and problem-solving abilities, with the capability to work independently, manage multiple priorities, and collaborate effectively within cross-functional teams\n\nStrong interpersonal and teamwork skills, with the ability to thrive in a diverse and dynamic work environment\n\nProficiency in scripting languages such as Perl, Tcl, and Python is preferred\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nGOWRI SHENOY\n\nhttps://www.linkedin.com/in/gowri-shenoy-33894217/", "jd_status": "stored"}, {"title": "Server platform design architect", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-06T13:09:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92579/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. Server platform design architect THE ROLE: Function: Principal Member of Technical Staff | Discipline: High Speed Board Design & Server Platform Architecture | Level: Principal / Staff (Senior Individual Contributor) | Location: Bangalore, India | Department: Server Platform Design / System Hardware Engineering We are looking for an exceptionally skilled and experienced Principal Member of Technical Staff to join our Server platform Hardware Engineering team, specializing in High Speed Board Design. This is a senior individual contributor role that combines deep technical expertise with leadership responsibility across complex, multi-generational hardware programs. The ideal candidate is a seasoned hardware engineer who thrives at the intersection of signal integrity, power integrity, and system-level design — someone who can independently drive technically complex designs from concept to production while also guiding and mentoring the engineers around them. This role operates at the forefront of hardware innovation, working on high-performance computing platforms, data center solutions, or next-generation semiconductor evaluation and validation systems. The engineer in this role will be expected to define technical direction, establish design methodology, and be the go-to authority for high speed board design challenges across the organization. THE PERSON: The ideal candidate brings a rare combination of deep hardware expertise and collaborative leadership. They are recognised as the go-to authority in platform design — someone who can resolve complex problems that others cannot, while remaining humble enough to mentor and grow the engineers around them. They demonstrate full ownership — from concept to production — and approach ambiguous, multi-disciplinary problems with a systematic mindset. They communicate complex technical concepts clearly to both technical and non-technical audiences, and represent the team with confidence in cross-functional and vendor discussions. Above all, they have an innovation mindset — constantly looking for better ways to design, review, and validate hardware — and they actively invest in the growth of the engineers around them. They are collaborative across disciplines (SI, firmware, mechanical, test, silicon) and comfortable navigating shifting priorities and new technology domains. What success looks like: In the first 6 months: Deep understanding of team programs, tools, and design standards; actively contributing to design reviews and board bring-up; identified at least one methodology improvement opportunity. Within the first year: Owning one or more high-speed board designs from specification through layout sign-off; recognised as a trusted technical resource; contributed to or defined updated design standards. Over time: Defining the technical direction for platform architecture within the organisation; producing benchmark designs for quality and reliability; developing the next generation of hardware design engineers on the team. KEY RESPONSIBILITIES: Technical Design & Execution Lead the end-to-end design of high-speed, high-complexity PCBs including schematic capture, component selection, layout guidance, and design verification Design and review high-speed interfaces including PCIe Gen 4/5/6, DDR4/5/LPDDR5, USB 3.x, MIPI, SERDES-based interfaces, Ethernet (1G/10G/25G/100G), and other emerging standards Develop and own design specifications, interface requirement documents, and schematics for complex multi-layer boards (20+ layers) Define and enforce PCB stack-up, impedance control, and routing rules for high-speed signal integrity compliance Drive board bring-up, debug, and validation activities — capable of independently diagnosing and resolving complex hardware issues Perform or guide pre-layout and post-layout signal integrity (SI) and power integrity (PI) simulations using industry-standard tools Work closely with PCB layout engineers to ensure design intent is correctly implemented, performing detailed layout reviews and providing clear, specific guidance Architecture & Innovation Participate in early-stage architecture definition and feasibility assessment for new platform programs Evaluate new silicon devices, connectors, memory technologies, and interface standards and assess applicability to upcoming designs Define reference design guidelines and best practices for high speed board design within the team Identify and propose design improvements that reduce cost, improve reliability, extend product life, or enhance testability Stay current with industry trends, emerging standards, and evolving EDA tool capabilities Technical Leadership & Mentorship Serve as the technical authority and subject matter expert (SME) for high speed board design within the team Provide technical guidance, design reviews, and mentorship to junior and mid-level hardware engineers Lead design reviews — both internal and cross-functional — ensuring design quality, manufacturability, and compliance with system requirements Collaborate with cross-functional teams including signal integrity engineers, firmware engineers, mechanical designers, and test engineers Represent the hardware design team in technical discussions with silicon vendors, EDA tool vendors, PCB fabricators, and assembly partners Process & Quality Define and maintain design standards, checklists, and review processes for high speed board design Champion design for manufacturability (DFM), design for testability (DFT), and design for reliability (DFR) practices Drive continuous improvement in design methodology, tool flows, and review processes Support sustaining engineering activities including ECO management, alternate component qualification, and product improvements PREFERRED EXPERIENCE: REQUIRED TECHNICAL SKILLS Deep expertise in high-speed interface design: PCIe (Gen 4/5 minimum), DDR4/DDR5, USB 3.x, SERDES-based interfaces Strong hands-on experience with signal integrity analysis — pre/post layout simulation, eye diagram analysis, impedance modeling, crosstalk analysis Strong hands-on experience with power integrity analysis — PDN design, decoupling strategy, VRM placement, DC/AC analysis Proficiency in schematic capture tools — Cadence Allegro/OrCAD, Mentor PADS, or equivalent industry tools Practical experience guiding PCB layout engineers — routing rules, layer stack-up, via structures, differential pair routing, length matching, and return path management Experience with board bring-up and hardware debug — oscilloscope, logic analyzer, VNA, TDR, BERT, and protocol analyzers Familiarity with EMI/EMC design practices and compliance requirements (FCC, CE, etc.) Understanding of thermal design considerations for high-power components Knowledge of manufacturing processes — DFM, IPC standards, Gerber review, assembly and test PREFERRED / BONUS SKILLS Experience with FPGA-based boards (Xilinx/AMD or Intel FPGA integration) Exposure to high-speed optical or SerDes interfaces at 112G or beyond Experience with OCP/DC-SCM, OpenBMC, IPMI, or data center platform standards Familiarity with RTL or firmware development for hardware validation or embedded systems Experience with mechanical design tools (ECAD-MCAD co-design) Exposure to AI/ML-based EDA tools or automation of design review and verification processes Experience in JTAG infrastructure design and boundary scan methodology EXPERIENCE 15+ years of hands-on experience in PCB hardware design, with a strong focus on high-speed digital systems Demonstrated experience designing complex, multi-layer PCBs (16+ layers) for high-performance computing, server, networking, or semiconductor test and evaluation platforms Proven track record of successfully delivering hardware designs from concept through mass production or customer deployment ACADEMIC CREDENTIALS: Bachelor's degree or higher in Electrical Engineering, Electronics Engineering, or a closely related field (preferred) Master's degree in Electrical Engineering or related discipline (preferred / desired) LOCATION: Bangalore, India Department: Server Platform Design / System Hardware Engineering #LI-SK3 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Staff Engineer Digital Design", "company": "Infineon", "location": "Bangalore BTP (India)", "date_posted": "2026-10-06T11:24:24+00:00", "url": "https://jobs.infineon.com/careers/job/563808971368855", "is_hardware": true, "platform": "eightfold", "jd_text": "We are hiring for Physical Design Engineer with strong hands Physical Design and Timing Closure of complex, low power SoCs targeted for IOT and MCU markets.\n\nYour Role\n\nKey responsibilities in your new role:\n\nThis position is for Physical Design and Timing Closure of complex, low power SoCs targeted for IOT and MCU markets.\nCandidate will be responsible to drive die area, performance, power goals for hierarchical blocks/Top.\nCandidate will work on various stages of physical design implementation which includes floor planning, IO planning, packager co-design, power grid design, place and route, clock tree synthesis, timing closure, Static/Dynamic IR drop, physical verification checks.\nCandidate is expected to have deep understanding and hands-on experience in implementing SOCs with multiple voltage islands, power islands and other power reduction techniques.\nCandidate should have good understanding of IO planning, package co-design aspects.\nCandidate is expected to drive flow/methodology activities to improve upon QoR.\n\nYour Profile\n\nQualifications and skills to help you succeed\n\nBachelor's or Master's degree with specialization in VLSI design\nMust have 8+ years of hands-on experience in physical design and timing closure of SoCs\nExperience of industry standard tools for physical design and signoff\nExperience in scripting languages (shell, perl, tcl) and Make flow\nUnderstanding of 40nm/28nm/22nm technologies and associated physical design challenges\nMust be a good team player and should have desire to learn and explore\nStrong commitment and determination in area of expertise\nMust be well organized, methodical and detail oriented\nTakes initiatives and overcomes challenges through creativity and innovation\nCoordinates with colleagues and actively shares expertise with others\nShares information comprehensively and effectively\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\nThis means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.\nPlease let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.\nClick here for more information about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Senior Staff/Principal Engineer, AMS Verification (Power & Analog ICs)", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-06T10:24:04.972000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000153721255-senior-staff-principal-engineer-ams-verification-power-analog-ics-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking an AMS Verification Engineer to lead verification of the digital content embedded within power, analog, and mixed-signal IC products. This is a senior individual-contributor role requiring ownership of verification architecture, methodology, execution, and sign-off at block and full-chip level. \nThe successful candidate will build scalable verification environments from specifications, develop verification plans and coverage strategies, and verify control, protection, diagnostics, communication, trimming, test, and safety-related digital functions that interact closely with analog circuitry. \nYou will be expected to work autonomously, resolve ambiguous specification issues, establish verification flows from scratch where required, mentor engineers, and provide clear evidence that the design meets functional and product requirements before tape-out. \nResponsibilities  \nVerification Strategy & Ownership \nOwn block-level and full-chip digital verification strategy for power, analog, and mixed-signal IC products. \nDevelop verification plans from product and design specifications, including feature extraction, test intent, coverage goals, assumptions, and sign-off criteria. \nDecompose complex functions into reusable verification components and scalable environments. \nIdentify specification gaps and drive closure with architecture, analog design, digital design, applications, and test teams. \nEnvironment Development & Execution \nDesign and develop SystemVerilog/UVM-based testbenches, agents, scoreboards, reference models, assertions, sequences, and coverage models. \nSet up verification flows from scratch where needed and own regression execution, triage, debug, and closure. \nApply simulation, assertion-based verification, formal verification, and FPGA or emulation techniques where they provide practical value. \nVerify digital behavior across reset, clock, power-state, fault, trim, communication, test-mode, and analog-interaction scenarios. \nMixed-Signal, DFT & Post-layout Support \nCollaborate with analog and digital teams to define appropriate models and verify analog-digital interactions at the required abstraction level. \nSupport DFT verification, scan and ATPG-related checks, production-test vector development, and test-mode verification. \nSupport gate-level simulation, timing-aware verification, and post-layout verification where required. \nContribute to silicon bring-up, device evaluation, root-cause analysis, and documented workarounds for device errata. \nTechnical Leadership & Methodology \nDrive reusable verification methodology, automation, metrics, documentation, and review standards across projects. \nMentor and train verification engineers through reviews, debug support, and technical guidance. \nProvide concise status, coverage, risk, and sign-off assessments to project and technical leadership. \nInfluence architecture and design choices by identifying verification complexity, observability gaps, and product risks early. \n\nBachelor or Masters degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline. \n10+ years of experience in AMS verification, including substantial hands-on experience with SystemVerilog and UVM. \nProven ownership of block-level and full-chip verification environments and sign-off for complex semiconductor products. \nStrong knowledge of functional verification, assertion-based verification, formal verification, regression frameworks, coverage closure, and debug methodologies. \nExperience verifying digital logic embedded in PMICs, power-management, automotive, audio, or other mixed-signal integrated circuits. \nGood understanding of RTL, microarchitecture, clocks, resets, low-power states, register interfaces, and common serial interfaces such as SPI, I2C, or UART. \nWorking knowledge of synthesis, STA, DFT, scan insertion, ATPG, and gate-level verification to collaborate effectively across the development flow. \nExperience with scripting or automation using Python, TCL, Perl, shell, or similar languages. \nProven ability to mentor engineers, establish verification methodology, and lead technical reviews without requiring formal people-management authority. \nSelf-driven, results-oriented, and able to deliver under tight schedules in a multisite and multicultural environment. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Staff Engineer – Analog/Mixed Signal Design ", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-06T10:09:49.884000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000153716222-senior-staff-engineer-analog-mixed-signal-design-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking an experienced Senior Staff Engineer – Analog/Mixed-Signal Design with 10+ years of expertise in transistor-level analog IC design and a strong foundation in analog circuit design fundamentals. The ideal candidate has a proven track record of architecting, designing, integrating, and delivering complex analog IPs and mixed-signal subsystems from concept through production. Experience developing power management ICs is a plus.\nAs part of Renesas' $2.6B Power Business Unit, you will help develop next-generation analog and mixed-signal solutions for multi-phase controllers and power management products that enable AI infrastructure and hyperscale computing platforms.\nKey Responsibilities\nArchitect, design, own, and deliver high-performance analog and mixed-signal IPs, including:Source/sink LDOs\nPositive and negative charge pumps\nRelaxation and other oscillator architectures\nTemperature sensors\nCurrent-sense circuits\nSAR ADCs\nProtection circuits (UVLO, OVLO, OCP, thermal protection, etc.)\nCore analog building blocks, including bandgap references, operational amplifiers, comparators, analog buffers, V-to-I converters, and high-speed level shifters\n\nDrive innovative circuit architectures and design optimizations to meet challenging performance, power, area, yield, and reliability targets.\nLead analog IP development through the complete product lifecycle—from architecture and transistor-level implementation through silicon validation, production qualification, and manufacturing support.\nCollaborate closely with layout engineers from floorplanning through chip-level integration, ensuring optimal analog layout, parasitic-aware design, and performance trade-offs.\nDevelop and optimize simulation methodologies across pre- and post-layout verification, balancing simulation accuracy, convergence, runtime, and debugging efficiency.\nEstablish and drive robust analog design methodologies, review processes, and quality checklists to maximize first-pass silicon success.\nDefine and review chip-level ESD, latch-up, and I/O protection strategies to ensure product robustness and reliability.\nMentor junior engineers and foster a culture of technical excellence across the team.\nLead or manage a small team of engineers, driving execution, mitigating technical risks, and delivering high-quality silicon on schedule.\n\nMinimum Qualifications\nBachelor's or Master's degree in Electrical Engineering or a related discipline.\n10+ years of hands-on experience in analog and mixed-signal IC design.\nDemonstrated ownership of complex transistor-level analog IP from specification through silicon validation.\nStrong understanding of:Analog circuit design fundamentals\nSemiconductor device physics and transistor-level design\nProcess corners, Monte Carlo analysis, mismatch, and noise\nExtraction, post-layout simulation, and parasitic optimization\nAnalog layout techniques and layout-dependent effects (LDE)\nESD, latch-up, and chip-level reliability considerations\n\nProven experience across the complete IC development lifecycle, including architecture, design, verification, silicon bring-up, debugging, qualification, and production support.\nStrong technical leadership, mentoring, communication, and cross-functional collaboration skills, with a passion for building high-performing engineering teams.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Staff/ Senior Staff /Principal Engineer, Analog Design (Power & Analog ICs)", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-06T09:57:25.870000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000153715233-staff-senior-staff-principal-engineer-analog-design-power-analog-ics-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking a Staff/Senior Staff/ Principal - Analog Design Engineer with deep expertise in power management, analog, and mixed-signal IC development. This is a senior individual-contributor role requiring ownership of complex analog IP, subsystem architecture, converter design, and silicon execution from concept through production. \nThe successful candidate will lead the design of key analog and power-management functions including switching converters, LDOs, charge pumps, references, sensors, protection circuits, data converters, and signal-conditioning blocks used across Renesas power and analog products. The role requires strong technical judgment, architecture ownership, cross-functional collaboration, and the ability to drive first-silicon success. \nYou will be expected to operate independently, resolve ambiguous technical challenges, establish design methodology, mentor engineers, and influence product architecture and execution through deep technical expertise. \nResponsibilities:  \nAnalog Architecture & Circuit Design \nDefine and own the architecture of complex analog and power-management IP used in PMICs, converters, battery-management products, and mixed-signal devices. \nDesign and own blocks such as positive and negative charge pumps, buck converters, source-sink LDOs, ultra-low-power oscillators, temperature sensors, current-sense circuits, SAR ADCs, voltage and current references, op-amps, comparators, analog buffers, level shifters, and protection circuits. \nTranslate product and top-level chip requirements into detailed block specifications, architecture decisions, circuit implementations, and verification plans. \nPerform block-level error budgeting and system-level trade-off analysis across performance, area, power, cost, robustness, and manufacturability. \nConverter & Control Loop Design \nIndependently architect and design complete switching converters including buck, boost, and buck-boost converters, as well as LDOs and point-of-load devices. \nDemonstrate deep understanding of analog feedback loops, control-loop stability, compensation implementation, and trade-offs across compensation strategies. \nEvaluate control architectures such as constant-frequency, constant-on-time, constant-off-time, voltage-mode, and current-mode control, and select the appropriate approach for product requirements. \nEnsure robust converter performance across process, voltage, temperature, load, line, startup, shutdown, and fault conditions. \nVerification, Silicon & Production Support \nDrive analog verification and simulation strategy across schematic, extracted, pre-layout, and post-layout environments. \nOptimize simulation setups based on speed, convergence, accuracy, and parasitic conditions, and resolve simulator, model, and tool-related challenges. \nOwn or support silicon validation, characterization, debug, qualification, production readiness, and root-cause analysis for silicon issues. \nCollaborate with product engineering, test engineering, applications, reliability, and manufacturing teams across the complete product lifecycle. \nPhysical Design, Reliability & Sign-off \nCollaborate closely with layout engineers from floor planning through chip-top completion, extraction, verification, and tape-out. \nGuide layout trade-offs related to matching, noise, parasitics, isolation, current density, electromigration, IR drop, thermal behavior, and high-current operation. \nDemonstrate strong understanding of ESD, latch-up, I/O-ring protection, and other IC-level reliability requirements. \nReview physical implementation and extracted performance to ensure the design meets electrical, yield, reliability, and manufacturability targets. \nTechnical Leadership & Methodology \nDrive analog design methodology, checklists, design reviews, reusable IP practices, and quality standards from concept through silicon success. \nLead technical reviews and provide clear architecture, design, verification, risk, and sign-off assessments to project leadership. \nMentor junior and mid-level engineers through architecture reviews, circuit design, simulation strategy, layout collaboration, and silicon debug. \nInfluence product architecture and technical roadmap decisions through demonstrated technical depth, while operating as a senior individual contributor rather than a formal people manager. \n\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related discipline. \n\n6 to 15 years of relevant experience in analog, mixed-signal, or power-management IC design. \n\nDemonstrated ownership of complex analog IP, converter subsystems, or complete smaller ICs from architecture through silicon and production. \n\nDeep hands-on expertise in PMICs, switching regulators, LDOs, charge pumps, and complex analog IP development. \n\nStrong understanding of analog feedback loops, control-loop compensation, stability analysis, and converter-architecture trade-offs. \n\nExperience with references, op-amps, comparators, buffers, level shifters, oscillators, sensors, current sensing, ADCs, and protection circuitry. \n\nExperience with industry-standard schematic design, simulation, extraction, and post-layout verification flows and tools. \n\nStrong understanding of analog layout effects, parasitics, matching, noise, reliability, ESD, latch-up, and IC-level robustness. \n\nExperience taking products through design, verification, tape-out, silicon validation, debug, qualification support, and production release. \n\nProven ability to establish design methodology, lead technical reviews, mentor engineers, and influence cross-functional decisions without requiring formal people-management authority. \n\nStrong communication and collaboration skills across global, multisite, and multicultural teams. \n\nSelf-driven, results-oriented, and able to deliver high-quality designs under tight schedules with limited supervision. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Lead Principal Engineer Design", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-10-06T09:32:26+00:00", "url": "https://jobs.infineon.com/careers/job/563808971792094", "is_hardware": true, "platform": "eightfold", "jd_text": "#WeAreIn for jobs that impact everyone's life.\nWhat if your ideas could change the way the world connects, powers up, or\nthinks? \n \nAs a Lead Principal Engineer Design] in our Research &\nDevelopment team, you'll have the opportunity to merge creativity with your\ntechnical expertise by shaping the future of technology, driving groundbreaking\nprojects, and bringing new ideas to life.\n \nAre you in?\n\nKey responsibilities in your new role\n\nResponsible for leading Physical Design and Timing Closure of lowpower SoCs targeted for IoT/MCU markets. -\nResponsible to achieve die area, performance, power goals forhierarchical blocks and top. \nDrive physical design implementation which includes package co-design,floorplanning, power grid design and signoff, place and route, timingclosure, physical verification checks. - Influence tools, flows and methodology activities to improve upon QoR. \nInteract with cross-functional team members to improve design,methodology and process aspects.\n\nQualifications and skills to help you succeed \n\nTechnical Expertise: - Deep and broad understanding of physical design and timing convergence of hierarchical SoCs \nExpert user of industry standard tools and flow/automation forphysical design and signoff \nIn-depth knowledge of process technologies and associated physicaldesign challenges \nDeep understanding of low power design techniques and implementation methodologies IFX Behaviours:\nAbility to solve complex problems by proactively involving expert networks \nDrives technical decisions in area of expertise and takesresponsibility for implementation \nCoordinates with colleagues and actively shares expertise with others \nFacilitates and encourages innovation within own domain of expertise \nCooperates across boundaries and appreciates the contributions ofother people\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Sr Staff Engineer – Analog/Mixed Signal Design", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-06T09:04:41.202000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000153701929-sr-staff-engineer-analog-mixed-signal-design", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking an experienced Senior Staff Engineer – Analog/Mixed Signal Design with 10+ years of expertise in transistor-level analog IC design and a strong foundation in analog circuit design fundamentals. The ideal candidate has a proven track record of architecting, designing, integrating, and delivering complex analog IPs and mixed-signal subsystems from concept through production. Experience developing power management ICs is a plus.\nAs part of Renesas Power Business Unit, you will help develop next-generation analog and mixed-signal solutions for multi-phase controllers and power management products that enable AI infrastructure and hyperscale computing platforms.\nKey Responsibilities\nArchitect, design, own, and deliver high-performance analog and mixed-signal IPs, including:Source/sink LDOs\nPositive and negative charge pumps\nRelaxation and other oscillator architectures\nTemperature sensors\nCurrent-sense circuits\nSAR ADCs\nProtection circuits (UVLO, OVLO, OCP, thermal protection, etc.)\nCore analog building blocks, including bandgap references, operational amplifiers, comparators, analog buffers, V-to-I converters, and high-speed level shifters\n\nDrive innovative circuit architectures and design optimizations to meet challenging performance, power, area, yield, and reliability targets.\nLead analog IP development through the complete product lifecycle—from architecture and transistor-level implementation through silicon validation, production qualification, and manufacturing support.\nCollaborate closely with layout engineers from floorplanning through chip-level integration, ensuring optimal analog layout, parasitic-aware design, and performance trade-offs.\nDevelop and optimize simulation methodologies across pre- and post-layout verification, balancing simulation accuracy, convergence, runtime, and debugging efficiency.\nEstablish and drive robust analog design methodologies, review processes, and quality checklists to maximize first-pass silicon success.\nDefine and review chip-level ESD, latch-up, and I/O protection strategies to ensure product robustness and reliability.\nMentor junior engineers and foster a culture of technical excellence across the team.\nLead or manage a small team of engineers, driving execution, mitigating technical risks, and delivering high-quality silicon on schedule.\n\nMinimum Qualifications\nBachelor's or Master's degree in Electrical Engineering or a related discipline.\n10+ years of hands-on experience in analog and mixed-signal IC design.\nDemonstrated ownership of complex transistor-level analog IP from specification through silicon validation.\nStrong understanding of:Analog circuit design fundamentals\nSemiconductor device physics and transistor-level design\nProcess corners, Monte Carlo analysis, mismatch, and noise\nExtraction, post-layout simulation, and parasitic optimization\nAnalog layout techniques and layout-dependent effects (LDE)\nESD, latch-up, and chip-level reliability considerations\n\nProven experience across the complete IC development lifecycle, including architecture, design, verification, silicon bring-up, debugging, qualification, and production support.\nStrong technical leadership, mentoring, communication, and cross-functional collaboration skills, with a passion for building high-performing engineering teams.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Sr. Staff Engineer - Physical Design", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-06T08:54:25.571000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000153699479-sr-staff-engineer-physical-design", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking an experienced and highly technical Backend Physical Design Engineer to drive the physical implementation of our next-generation, high-performance SoCs. You will own the complete RTL-to-GDSII flow, focusing heavily on power recovery, clock tree optimization, and pushing aggressive PPA metrics on advanced technology nodes\nKey Responsibilities\nRTL-to-GDSII Execution: Own and drive the end-to-end physical design implementation, including floor planning, synthesis, placement, Clock Tree Synthesis (CTS), and routing.\nPPA Optimization: Fine-tune the design to meet stringent Power, Performance, and Area (PPA) targets. Employ advanced techniques like multi-voltage domains, power gating (UPF), and datapath optimization to minimize power while maximizing speed.\nTiming Closure & STA: Drive Static Timing Analysis (STA) across multiple corners and operating modes. Resolve setup/hold violations, signal integrity issues, and clock domain crossing constraints.\nPhysical & Formal Verification: Execute Design Rule Checks (DRC), Layout Versus Schematic (LVS), electromigration/IR drop (EMIR) analysis, and Equivalence Checking (LEC/Formality) to ensure design reliability and manufacturability.\nCross-Functional Collaboration: Work closely with RTL (Frontend), DFT, and Signoff teams to iterate on designs and structural changes for optimal PPA.\nProgramming/Scripting: Strong scripting skills in Tcl, Python, or Perl to automate flows and improve design methodologies\n\nExperience of about 10+ years in Physical design implementation \nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. \nAbility to understand design specifications, can contribute to design planning, partitioning, and setup a feasible seed for convergence PD cycle. \nExtensive experience in physical design PPA activities, including floorplanning, placement, clock tree synthesis, routing, and timing closure. \nGood understanding of EDA tools such as Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC, Calibre, Red Hawk. \nStrong understanding of static timing analysis, power analysis, and signal integrity analysis. \nExcellent problem-solving skills and attention to detail. \nAbility to work effectively in a team environment and communicate clearly with cross-functional teams. \nExperience in mentoring and coaching junior engineers is a plus. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Staff Product Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-06T08:33:51.114000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000153694619-senior-staff-product-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Position Summary \nRenesas Electronics is seeking an experienced Product Engineer ( Senior Staff level) to lead the development, qualification, release, and sustaining of advanced semiconductor power products. This role is responsible for driving product engineering execution across the full lifecycle, from silicon bring-up through high-volume production, with a strong focus on product quality, yield optimization, reliability, and customer success. The ideal candidate will bring deep expertise in power semiconductor technologies (e.g., Point of loads (POL), Hotswap/Efuse, Drivers solutions) and demonstrate strong ownership of complex technical challenges while influencing cross-functional teams. \nKey Responsibilities \nOwn product engineering activities across the full lifecycle, including silicon bring-up, characterization, qualification, production release, and sustaining \n\nDefine and execute comprehensive product qualification strategies aligned to JEDEC and industry standards \n\nDrive reliability stress planning and interpretation, including HTOL, HAST/uHAST, TC, ELFR, and associated qualification methodologies. \n\nLead ESD and latch-up qualification strategy, data analysis, and failure resolution in alignment with product requirements. \n\nLead root cause analysis and resolution of complex product, test, and manufacturing issues \n\nDrive improvements in yield, test efficiency, product performance, and cost of quality \n\nDefine and execute characterization and qualification strategies to ensure robust product release \n\nPartner with design and test engineering teams to optimize DFT, test coverage, and correlation (bench vs ATE vs system) \n\nLead cross-functional efforts to resolve customer issues and field escalations \n\nAnalyse yield, parametric, and reliability data to identify trends and drive corrective actions \n\nInfluence product, test, and manufacturing decisions through strong technical judgment and data-driven insights \n\nServe as a recognized subject matter expert in product engineering, statistical analysis, reliability, and failure analysis. \n\nLead cross-functional efforts across design, applications, reliability, and test teams to resolve highly complex technical challenges. \n\nProvide leadership in defining characterization plans, qualification strategies, and analysis methodologies. \n\nCommunicate complex analytical findings, qualification results, and failure analysis conclusions to diverse stakeholders, including senior leadership. \n\nInfluence product release decisions through data-driven insight, technical expertise, and sound engineering judgment. \n\nAct as a key authority on product readiness, with accountability for decisions impacting product quality and business outcomes. \n\nWork on complex, ambiguous problems requiring evaluation of incomplete or conflicting data, applying conceptual and statistical thinking to determine optimal solutions. \n\nAnticipate technical risks in product performance, qualification adequacy, and reliability margins, and proactively drive improvements. \n\nContribute to development of best practices in qualification methodology, data analysis, and engineering decision frameworks. \n\nMentor junior engineers in advanced statistical techniques, reliability interpretation, and structured problem solving and contribute to development of best practices \n\nBachelor’s or Master’s degree in Electrical Engineering or Microelectronics Engineering \n\n10+ years of experience in semiconductor product engineering, test engineering, or related roles \n\nStrong experience in semiconductor industry, with preference for power / analog / mixed-signal products \n\nDeep understanding of product lifecycle (NPI through sustaining) \n\nStrong working knowledge of JEDEC standards (e.g., JESD47, JESD22 series) and industry qualification practices. \n\nHands-on experience with ESD qualification (HBM, CDM) and latch-up testing/analysis. \n\nExperience with reliability stress planning and interpretation (HTOL, HAST, TC, ELFR, etc.). \n\nProven track record solving complex technical and yield-related issues \n\nStrong data analysis skills (JMP, Python, MATLAB or similar) \n\nDemonstrated success driving efficiency improvements in characterization, qualification, and yield analysis workflows. \n\nExperience with ATE, silicon characterization, and production environments \n\nDeep expertise in statistical analysis, including distribution analysis, correlation analysis, and limit optimization. \n\nStrong background in product characterization and electrical performance evaluation. \n\nExtensive experience in reliability qualification, ESD, and latch-up methodologies. \n\nDemonstrated expertise in failure analysis and root cause investigation across multiple failure modes. \n\nProven leadership in solving highly complex technical problems using data-driven approaches. \n\nExperience influencing engineering decisions and leading cross-functional technical initiatives. \n\nStrong communication and cross-functional collaboration skills \n\nKey Performance Indicators (KPIs)  \nSuccessfully lead on-time product releases with robust characterization and qualification coverage \n\nDrive measurable improvements in yield, test cost, and product quality \n\nAchieve timely resolution of critical product and customer issues \n\nEstablish strong correlation between bench, ATE, and system-level performance \n\nInfluence key product and test decisions to improve competitiveness \n\nContribute to team capability growth through mentorship and technical leadership \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Validation Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-06T08:20:00.040000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000153690054-senior-validation-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Role Summary\nCollaborator should be able to evaluate full PMICs through bench silicon validation techniques, including the hardware and software setup preparation. As part of silicon validation and delivery of results, the collaborator shall prepare evaluation plans for each specific product and provide documents to report results within planned and agreed time scales.\nThe collaborator will be part of a Silicon Validation Engineering team reporting directly to a Group Manager or Team Lead. It will require to closely work with other colleagues, meaning that teamwork mentality is very welcome, expected to be able to develop/improve existing techniques and enhance bench silicon validation.\nKey Skills\nRequired:\nBachelor’s in electrical engineering or computer science\nKnowledge of Power Management (PMICs), with 4+ years of post-silicon bench validation experience\nMedium/High level expertise in lab instruments and measurement methods, mainly for DCDCs and LDOs\nAbility to debug any unexpected issue and identify root cause\nMedium level expertise in Embedded Systems, including C/C++\nGood proficiency with Python programming with particular use for lab automation hardware environments\nAbility to work with minimal instructions and capable of supporting team members\nGood English verbal and written communication skills\nGoals-oriented and able to deliver on-time results under tight schedules\n\nNice-to-have:\nMaster’s in electrical engineering or computer science\nSelect/propose innovative methods/techniques to improve existing solutions\nSupport other teams, such as Designers, Systems, Applications and Test/Quality/Product Engineers\nBoard level analog and digital circuit design expertise for PCB schematic design (Altium)\nCross cultural awareness and sensitivity within multisite and multicultural environments\nFlexible to undertake occasional international travel\nKnowledge on verbal/written on other languages\nRenesas Electronics India\nRenesas Electronics India is an equal opportunity and affirmative action employer, committed to celebrating diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by federal, state or local law.\nRenesas Electronics India delivers trusted embedded design innovation with complete semiconductor solutions that enable billions of connected, intelligent devices to enhance the way people work and live. Our mission is to help develop a safer, healthier, greener, and smarter world by bringing technology into four segments: Automotive, Industrial, Infrastructure, and IoT (Internet of Things).\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Staff Engineer, STA", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-06T06:44:37.147000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000153671539-staff-engineer-sta", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Senior/Staff STA (Static Timing Analysis) Engineer \nThe STA Engineer is responsible for ensuring robust timing closure and signoff readiness for block- and full-chip designs across all modes and corners. This role owns timing constraint development and validation, performs detailed setup/hold and variation-aware analysis, and partners closely with Synthesis, CTS, Physical Design, and Design teams to debug violations and drive ECO-based optimizations through tapeout. \nWhat you’ll do \nPerform full-chip and block-level Static Timing Analysis (STA) across all modes and corners. \nAnalyze and debug setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations. \nWork closely with Physical Design, Synthesis, CTS, and Design teams to achieve timing closure. \nDevelop and maintain timing constraints including SDC creation, validation, and signoff readiness. \nDrive timing closure through ECO implementation and timing optimization. \nAnalyze timing impact due to process, voltage, and temperature variations. \nSupport timing signoff for pre-layout and post-layout stages. \nPerform cross-functional reviews for timing convergence and provide recommendations. \nGenerate timing reports and communicate closure status to project stakeholders. \n\nWhat we’re looking for \n4–12 years of experience in Static Timing Analysis (STA) and timing closure for block and/or full-chip designs. \nStrong understanding of CMOS fundamentals, timing concepts, and semiconductor design flow. \nHands-on experience in setup/hold analysis, path-based analysis, OCV/AOCV/POCV, derates, and MMMC concepts. \nGood understanding of clock tree, clock uncertainty, latency, skew, and jitter. \nExperience in timing constraints development and debugging. \nStrong knowledge of SDC, timing exceptions, false paths, multicycle paths, and case analysis. \nFamiliarity with timing closure techniques and ECO methodologies. \nHands-on experience with industry-standard STA tools such as Synopsys PrimeTime or Cadence Tempus. \nGood scripting skills in Tcl, Perl, or Python. \nAbility to analyze and resolve timing violations independently. \nNice to have \nExposure to low-power timing analysis and UPF/CPF-aware STA. \nFamiliarity with SI-aware timing, Crosstalk analysis, and IR-drop-aware timing closure. \nKnowledge of advanced technology nodes and variation-aware signoff methodologies. \nExposure to automation and flow development. \nExperience in cross-functional collaboration with PD, RTL, and Signoff teams. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Staff Engineer Layout and Mask Design", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-10-06T06:23:52+00:00", "url": "https://jobs.infineon.com/careers/job/563808972071869", "is_hardware": true, "platform": "eightfold", "jd_text": "Join us to design and deliver cutting-edge analog and power layouts for next-generation PMICs, DC-DC converters, LDOs, bandgaps, and high-voltage power management solutions. You'll drive the complete layout journey from floor planning and device placement to sign-off and tape-out, while solving complex challenges in matching, parasitics, noise isolation, EM/IR, reliability, ESD, and latch-up prevention. Collaborate with world-class design and verification teams to create high-performance, silicon-proven products powering automotive, industrial, and consumer applications.\n\nYour role\nKey responsibilities in your new role\n\nOwn\nand deliver analog/power layouts for DC-DC converters, LDOs, bandgaps,\nreferences, and supporting PMIC blocks. \nPerform\nfloor planning, device placement, routing, and layout optimization considering\nmatching, parasitics, noise, EM/IR, and reliability requirements. \nImplement\nhigh-voltage layout techniques including isolation structures, guard rings,\nESD, and latch-up prevention. \nDrive\nDRC, LVS, ERC, extraction, and layout sign-off activities to ensure successful\ntape-out. \n\nCollaborate\nclosely with design, verification, and CAD teams to resolve layout-related\nissues and meet project schedules.\n\nYour profile\nQualifications and skills to help you succeed \n\nDiploma/Bachelor’s/Master’s\nDegree in Electrical/Electronics Engineering, Physics, or related field. 5+\nyears of Analog/Mixed-Signal Layout experience, including High Voltage\nBCD/Power Management technologies.\nProven\nexperience in DC-DC Converter, PMIC, LDO, and power block layouts from floor planning\nto tape-out. \nStrong\nunderstanding of analog layout fundamentals including matching, parasitic\noptimization, shielding, EM/IR, and current-density considerations.\n\nProficiency\nwith industry-standard layout and verification tools such as Cadence Virtuoso\nand Calibre.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nVidhi Thakkar", "jd_status": "stored"}, {"title": " RTL Design Engineer", "company": "Infineon", "location": "Bangalore", "date_posted": "2026-10-06T05:10:21+00:00", "url": "https://jobs.infineon.com/careers/job/563808972069167", "is_hardware": true, "platform": "eightfold", "jd_text": "Join us to design and bring cutting-edge digital silicon solutions from architecture to silicon validation.\nWork on RTL development using Verilog/SystemVerilog, CDC and quality checks, and FPGA prototyping.\nContribute to digital verification, AMS test development, and post-silicon debugging activities.\nIf you're passionate about digital design and semiconductor innovation, we’d love to hear from you!\n\nYour role\nKey responsibilities in your new role\n\nMicro-Architecture & Coding: Translate high-level system requirements into detailed micro-architectures and write clean, modular Verilog, System Verilog, or VHDL.\n\nQuality & Checks: Perform linting, Clock-Domain Crossing (CDC) analysis, and formal equivalence checks.\n\nSilicon Bring-Up: Assist with FPGA prototyping, lab testing, and post-silicon root-cause debugging.\n\nDigital DV and AMS : Basic DV of the RTL using python based flow, and writing digital specific AMS testcases\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor’s or Master’s degree in Electrical Engineering, Electronics, or VLSI with 2+ Year of Experience.\n\nDeep proficiency in Verilog, System Verilog, and digital fundamentals.\n\nTools: Experience with EDA tools for linting, synthesis, and CDC (added advantage).\n\nProtocols: Familiarity with standard serial interfaces like I2C, SPI, UART etc.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nMalthesh K P", "jd_status": "stored"}, {"title": "Senior Analog/Mixed-Signal Layout Engineer - SERDES", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-06T04:05:00+00:00", "url": "https://global-external-amd.icims.com/jobs/93238/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. MTS SILICON DESIGN ENGINEER    THE ROLE: As a member of IO & PHY Group, you will help develop layout designs. As a member of the team, you will work closely with the architecture, IP design, Physical Design teams to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Implementation Layout of blocks and macros Own and deliver the high-quality macros with help of team Mentor and groom the juniors in the team Work with contractor team and the planned work done as per aligned schedule Enable release flows as required PREFERRED EXPERIENCE: 8+ yrs of hands-on experience in layout design Experience with Cadence virtuoso, Caliber and other verification tools as required for layout development Preferrable experience in high speed SERDES blocks ACADEMIC CREDENTIALS: Bachelors or Masters degree in Electrical Engineering or equivalent #LI-PK2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Sr Staff Engineer, AI/ML Applications", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-06T03:53:21.657000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000153658256-sr-staff-engineer-ai-ml-applications", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Job Summary \nRenesas is seeking a Sr Staff Engineer to build AI-powered engineering applications and data platforms that improve semiconductor development productivity, accelerate decision-making, and reduce engineering cycle time. \nThe ideal candidate will lead the development of scalable full-stack solutions that transform engineering data into actionable insights through AI-driven workflows, analytics, and modern web applications. This role spans data engineering, backend services, AI integration, and React-based user experiences, enabling solutions such as engineering copilots, design exploration agents, workflow automation, and digital-thread platforms. \n \nJob Responsibilities \nLead development of AI-powered engineering applications and platforms. \n\nIntegrate LLMs, RAG systems, vector databases, and agent frameworks into production solutions. \n\nDesign and implement scalable data ingestion, transformation, and serving pipelines for engineering data. \n\nBuild backend services and APIs supporting AI agents, workflow orchestration, analytics, and decision-support systems. \n\nDevelop modern web applications using React.js and TypeScript. \n\nDesign data models connecting requirements, architecture, implementation, verification, and sign-off results into a unified engineering knowledge platform. \n\nBuild dashboards, analytics, and workflow automation solutions that improve engineering productivity and reduce cycle time. \n\nCollaborate with Architecture, Design, Verification, and Product Engineering teams to identify and deliver high-impact AI solutions. \n\nDrive technical direction, architecture reviews, and engineering best practices. \n\nMentor engineers and influence technology strategy across teams. \n\nQualifications \nBS/MS in Computer Science, Electronics, AI/ML, or related field. \n\n10+ years of software engineering experience. \n\nExperience developing AI-enabled applications using LLMs, RAG, vector databases, or agent-based architectures. \n\nStrong experience in Data Engineering, including ETL pipelines, data modelling, data quality, and large-scale data processing using Azure Data Bricks. \n\nStrong proficiency in Python and backend application development. \n\nHands-on experience with React.js, TypeScript, HTML, and modern web technologies. \n\nExperience building REST APIs, microservices, and distributed systems. \n\nStrong software design, problem-solving, and communication skills. \n\nDemonstrated technical leadership and mentoring experience. \n\nNice-to-Have \nExperience with semiconductor design flows, EDA tools, or engineering productivity platforms. \n\nFamiliarity with physical design, verification, PPA analysis, or silicon development workflows. \n\nExperience with graph databases, knowledge graphs, and engineering knowledge-management systems. \n\nExperience with docker, cloud-native platforms, and workflow orchestration frameworks. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "PMIC Design Verification Lead (Sr Staff Engineer)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-06T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721181542", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.\n\nDigital Verification Lead (Senior Staff Engineer) for PMIC IPs, ASICs and Chipsets used in Qualcomm Snapdragon power solutions.      \nQualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives.\nBut this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the invention age and this is where you come in.\nAs a Digital Verification Sr. Staff Engineer you will be leading digital verification for next gen PMIC technologies, Mixed-Signals IPs, ASICs and Chipsets used in Qualcomm Snapdragon power solutions. IPs include telemetry ADCs, 100W+ charging (Quick Charge 5.0), 5G/6G power (mmW, envelope tracking, high-performance low noise oscillators etc…) and high efficiency power management (DC-DC charge pumps, bucks and linear regulators).\n* Work includes partnering with international teams in all stages of development from system definition to high-volume (100M+) OEM launches.\n* Digital Verification aspects include all stages of the verification process, from test planning, UVM-compliant test-bench architecture, constrained random stimulus creation, score-boarding and coverage closure.\n* Work includes verification of digital and mixed-signals IPs and exposure to analog behavioral models is a plus.\n* Work includes debugging complex systems including SOCs, firmware, embedded sequencers.\n* Position includes IP or chip digital DV ownership including task planning and project risk mitigation.\n* Work in a dynamic team environment with an aggressive schedule towards metrics-based high-quality target.\n* Experience in leading a team is a plus.\nPreferred Qualifications\nStrong troubleshooting skills across ASIC systems disciplines (digital RTL, Firmware, analog behavioral models)\nExperience in writing Test Plans independently, planning Verification architecture, review testbench/ testplans with juniors, identify coverage gaps, propose alternate methods for coverage\nStrong communication and organizational skills\nStrong process-oriented mindset.\nExpert-level System Verilog Programming\nAdvanced UVM/SV (Universal Verification Methodology using System Verilog)\nPython or Perl scripting\nMinimum Qualifications\nBachelor's degree in Science, Engineering, or related field. Masters preferred\n10+ years ASIC design, verification, or related work experience\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Silicon Validation Senior Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-06T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721355825", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field.\n\nExperience: 3 to 5 years\nThe candidate should have good understanding of analog and mixed signal circuits with experience in high-speed links such as DDR PHY and/or Serdes \nExperience with high-speed digital circuits, memories and lab. testing is desirable\nExperience with Tx/Rx equalization techniques and circuits like de-emphasis, CTLE, DFE is desirable\nKnowledge of DDR protocols is desirable \nAbility to work in a dynamic environment and interact well with cross-functional teams such as design, boards, ATE etc.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SOC Architect / uArchitect", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-06T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721283499", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Systems Engineering\nGeneral Summary:\nResponsibilities includes but not limited to:\nCreate highly scalable SoC architecture for RTOS based SOCs for IOT/XR\nComprehend product requirements to steer generation of proper architecture.\nPerform trade-off analysis in the solution space to produce the most optimal architecture\nCollaborate with architects, technical leads, hardware and software engineers from various functional areas in deriving the architectural solution that can best integrate in the overall SoC\nGenerate detail architectural specification and work closely with design team to implement the architecture\n\nSkills/Experience:\nExcellent communication, documentation, and interpersonal skills with ability to convey proposals and interact effectively across a distributed multi-discipline organization\nStrong foundation of silicon design principles and architectural trade-offs\nAbility to span and connect levels of abstraction across system-design, high-level languages, OS, HW/SW interface, micro-architecture, and silicon implementation\nBackground in architecture (IP or SoC), and/or front-end design/verification (micro-architecture)\nDemonstrated deep technical knowledge and achievements at the SoC, sub-system or large IP levels as micro-architect or architect\nAbility to apply appropriate abstractions and quantitative analysis for problem definition and solutions\nExperience in using, improving, and developing a variety of tools for analysis and modeling, such as functional and performance simulators, profilers, etc.\nProgramming ability for modeling and automation (OOP C++, Python preferred) with experience in software development best practices including reviews, unit-testing, version control, etc.\nAbility and desire to develop and improve architecture methodologies for experiments and analysis\nPreferred with experience in the area of general SoC architecture (SoC Arch lead).\n\nQualifications:\nBachelor’s degree in Electronic Engineering, Computer Science or related field required; Master’s degree or PhD highly desired\n12-18 years of SoC/IP architecture or micro-architecture/front-end-design\nCandidates with primarily a micro-architecture/design background must have contributions that demonstrate higher-level analysis and design\n\nAdditional Experience and Expertise (the more the better)\nSoC architectures including heterogeneous compute, NoC/interconnect, memory-systems, multicore, multi-die, cache hierarchies, shared memory, I/O, coherency, compression, security\nResource and Power Management\nSecurity Architecture\nSystem-level debug\nAI & Machine Learning\nControl and Real-time systems\nReal-time operating systems (e.g., Zephyr, FreeRTOS)\nFront-end Digital Hardware Design or Verification\nArm system architectures (e.g., Cortex-A, Cortex-R, Cortex-M, SMMU, GIC, CoreSight)\nRISC-V architecture\nHigh-speed I/O (USB, PCIe)\nExternal memory and storage architectures (e.g., LPDDR, NAND Flash, NOR Flash)\nNetworking & Connectivity (e.g., Ethernet, WLAN, Cellular, CAN)\nBehavioral, functional and performance modeling\nPower and/or performance optimization through simulation & modeling\nAnalytical modeling for performance and power\n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Systems Engineering or related work experience.\n                                                                    OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Systems Engineering or related work experience.\n                                                                    OR\nPhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "GPU (RTL) Design - Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-06T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720529477", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nMinimum 3 to 4 years of work experience in ASIC RTL Design\nExperience in Logic design/micro-architecture/RTL coding is a must.\nMust have hands on experience with design and integration of complex multi clock domainblocks\nExperience in Verilog/System-Verilog is a must.\nShould have knowledge of AMBA protocols - AXI, AHB, APB, clocking/reset/debug architecture\nHands on experience in Multi Clock designs, Asynchronous interface is a must.\nExperience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.\nUnderstanding of Memory controller designs and microprocessors is an added advantage\nWork closely with the Design verification and validation teams for pre/post Silicon debug\nHands on experience in Low power design is preferable\nExperience in Synthesis / Understanding of timing concepts for ASIC is must\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "AMS Silicon Validation Engineer, Senior Staff/Manager", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-06T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718665705", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n\nExperience: 12 to 16 years with some Managerial experience in handling a team(A MUST)\n\nJob Description:\nExperienced in post silicon bring-up and validation for Mixed Signal PHYs. Pre-silicon experience in emulation is desirable.\n\nThe candidate should have good understanding of analog and mixed signal circuits with experience in high-speed links such as DDR PHY and/or Serdes \n\nExperience with high-speed digital circuits, memories and lab. testing is desirable\n\nExperience with Tx/Rx equalization techniques and circuits like de-emphasis, CTLE, DFE is desirable\n\nKnowledge of DDR protocols is desirable \n\nAbility to work in a dynamic environment and interact well with cross-functional teams such as design, boards, ATE etc.\n\nExperience in lab. measuring instruments such as Oscilloscope, BERT etc.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Turing-IP Design Verification - Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-06T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719367655", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nAbout the Role\nWe are looking for a skilled and motivated DV Engineer to join our IP verification team. In this role, you will be responsible for the functional verification of complex IPs and subsystems that form the building blocks of our next-generation SoCs. You will work closely with design, architecture, and SoC integration teams to define verification strategies, build robust testbenches, and drive coverage closure to deliver high-quality silicon.\n \nKey Responsibilities\nOwn and drive functional verification of IPs and subsystems from planning through sign-off.\nDevelop verification plans, testbench architecture, and test cases based on design and architecture specifications.\nBuild and enhance reusable, scalable verification environments using System Verilog and UVM.\nDevelop and maintain constrained-random and directed test scenarios, assertions, and functional coverage models.\nDrive coverage closure (code + functional) and debug failures using waveform/log analysis.\nCollaborate with design, architecture, and SoC integration teams to resolve issues and ensure verification completeness.\nContribute to regression setup, triage, and maintenance to ensure verification quality and throughput.\nSupport IP-to-subsystem-to-SoC integration and reuse of verification collateral across levels.\n \nRequired Qualifications\n3 to 5 years of hands-on experience in ASIC/SoC functional verification.\nStrong proficiency in System Verilog and UVM methodology.\nProven experience in IP, subsystem, and/or SoC-level verification.\nSolid understanding of verification concepts: constrained-random stimulus, functional coverage, assertions (SVA), and scoreboarding.\nStrong debug skills using simulation logs and waveform tools (e.g., Verdi/FSDB).\nGood understanding of digital design fundamentals, bus protocols, and SoC architecture.\nStrong analytical, problem-solving, and communication skills.\n \nPreferred / Good-to-Have Skills\nExperience in integration of C/C++ models into SV UVM Testbench using SV<->C DPI calls\nFamiliarity with formal verification(C2RTL, FPV..) and performance verification.\nExperience with industry-standard bus protocols (AXI/AHB/APB, etc.).\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Sr Engineer - Post Si Validation", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-06T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721139077", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\n\nResponsibilities\nYou will be part of Qualcomm Snapdragon SoC - Silicon Validation team, particularly in the bring up of SVE convex infra, IST framework for the enablement of VI content in production.\n\nUnderstand the IP architecture,  work with IP validation teams and Systems validation Lead/system content engineer to understand the validation requirements, develop/port/enhance the validation software content and bring up.\n\nOwn SoC frequent regression and execute end-to-end regression suite by considering SoC design corner cases wrt power and performance.\n\nExecuting SOC validation releases on bench in lab and supporting the SLT teams in Debug and enabling different features in the framework.\n\nUse silicon debug hooks to measure power/performance/coverage and other KPI metrics\n\nWork with a relevant team member for regular reporting of issues and failure of debugs.\n\n    \nMandatory Skills:\n\n- Basics of processor architecture, Multicore/Multiprocessor with SMP/MTE/heterogenous cores.\n- C language expertise for low level programming, Assembly language for any processor, C-assembly interworking\n- Operating systems/RTOS/Linux kernel internals, scheduling policies, locking mechanism, MMU/paging etc\n- Exposure to working on emulation/pre-si environment is added advantage\n- Using JTAG based debuggers, compilers/linkers\n- Should have good exposure to software development life cycle\n \nDesired Skills\n\n- Exposure to SoC architecture paradigms – interconnects, power management,\n- Software development for silicon enablement, silicon validation\n- Bring-up of hardware-software solution on FPGA/emulation platforms and on fresh SOC designs\n- Software for power/performance KPIs\n- Good knowledge of ARM Cortex-A7/A8) / x86 / PowerPC CPU and memory system architecture\n- Weakly ordered memory model/pipelining of memory systems/memory barriers\n- Software development towards higher performance of multi-threaded applications using lower power\n- Top level of ASIC design methodology is an added skill\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Technical Staff Engineer-Verification", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-10-06", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Technical-Staff-Engineer-Verification_R4056-26", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nMicrochip’s Communications Business Unit (CBU) develops high-performance networking, connectivity, and edge compute semiconductor solutions that power communications infrastructure, data centers, automotive systems, aerospace and defense platforms, and industrial applications. Our global team works across the full product lifecycle to deliver innovative products that enable the world’s most demanding connected systems. \nThe CBU Product Development team is engaged through the full device R&D cycle from concept, design and implementation stages. Once a prototype is available, we support embedded software development and system validation lab testing through to mass-market production release. We are an experienced chip team working with the latest semiconductor development tools and methodologies in advanced process technologies to develop state-of-the-art network devices.\nWe are seeking a Verification focused Technical Staff Engineer in the CBU Product Development team who will be responsible for the verification strategy and technical leadership of communication semiconductor devices and subsystems. We are looking for an experienced hands-on technical leader who can directly contribute to all aspects of verification from planning, testbench architecture to coverage closure and sign-off readiness at the block and top level of a device. The individual should be to solve challenging engineering problems with innovative solutions and mentor engineers. The individual will be a key member of the CBU’s Silicon Design Center in India with technical leadership and mentoring responsibilities.\nResponsibilities may include:\nVerification Architecture and Strategy\nOwn or contribute to verification architecture for leading-edge communications devices\n\nBuild system-level understanding of device applications and use it to define complete, risk-based verification plans\n\nCollaborate with Product Marketing, Applications Engineers, System Architects, Designers and Customers to identify, record, track and verify device requirements\n\nPartition verification scope across block, subsystem and device levels, including reusable verification components and coverage models\n\nParticipate in concept and feasibility studies for next-generation products by identifying verification risks, methodology needs and validation alignment early in the development cycle\n\nTechnical Leadership\nLead delivery of verified digital integrated circuits at the device, subsystem or block level as a Verification Architect, Verification Lead or Technical Leader\n\nMentor and provide technical direction to a small team of Verification Engineers\n\nPartner with Design Leads and Architects to align implementation intent, verification strategy and sign-off expectations\n\nTranslate industry standards, market requirements and functional specifications into executable verification plans, coverage goals and measurable closure criteria\n\nDevelop verification platforms guided by UVM methodology and implemented with SystemVerilog, assertions and reusable verification components\n\nDrive verification execution, debug, regression quality, coverage closure and sign-off readiness using industry-leading tools and flows\n\nDomain Expertise\nDevelop or enhance technical expertise in technologies, verification methodologies, flows or standards\n\nContribute to verification best practices for industry standards such as Ethernet, OTN and related networking technologies\n\nProvide subject-matter guidance to development teams within CBU on verification strategy, methodology, debug and closure\n\nEnhance internal, proprietary verification flows and practices to improve efficiency, completeness, reuse and sign-off quality\n\nCross Functional Responsibility\nCollaborate with Software, Validation, Applications, Production Engineering and Design teams to deliver production-worthy devices that integrate into a wider system and are supported by robust verification evidence\n\nRequirements/Qualifications:\n\nBachelor’s or Master’s Degree in Electrical Engineering or Computer Engineering\n12+ years related experience\nExcellent analytical and debugging skills and the ability to proactively solve issues\nProven ability to thrive on, learn and adapt to new methodologies and technologies\nStrong coding skills\nExperience using one or more of SystemVerilog/Verilog/VHDL, Tcl/Perl/Python, C/C++, XML\nDemonstrated experience verifying complex digital integrated circuits using SystemVerilog, UVM, assertions, constrained-random testing, coverage-driven verification, formal verification or related methodologies\nExcellent verbal and written communication skills in English\nFamiliarity with communication protocols such as Ethernet, ASA and others (an asset)\nExperience with Synopsys, Cadence or similar verification, simulation, formal, debug, coverage or regression management tool flows (an asset)\nExperience with state-of-the-art silicon process technologies and complex SoC verification environments (an asset)\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Design Verification Infrastructure Engineer - Software and Build", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-10-06", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Sr-Design-Verification-Infrastructure-Engineer---Build_R-101099", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nJoin SiFive’s Design Verification Infrastructure team to develop and maintain the Verification Platform build system used across SiFive. An ideal candidate will have experience architecting complex build systems for large software organizations. You will be expected to collaborate with multiple teams to shape the build system for Design Verification and other teams.\n\nResponsibilities:\nArchitect, develop, and maintain the Verification Platform build system to provide a common infrastructure that scales with the growth of SiFive for Design Verification and other verification and validation activities\n\nDevelop Verification Platform tools, build flows, and methodologies to support end-to-end flows used by Design Verification and other verification and validation teams\n\nDevelop Verification Platform build recipes in the Wake language\n\nEducate the Design Verification and other verification and validation teams on best practices and how to achieve them with the Verification Platform\n\nRequirements:\nBuild system architecture, development, and maintenance in a production environment\n\nSoftware engineering with 5+Years of experience in at least one scripting language\n\nDesired:\nExperience with Wake or functional programming languages\n\nUnderstanding of hermetic build systems like Bazel, Buck, etc.\n\nFamiliarity with EDA tools and flows for Design Verification\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Silicon Packaging Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-06", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Silicon-Packaging-Design-Engineer_JR0286703", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nJoin our team as a Silicon Packaging Design Engineer in the Data Center Group, where you will play a pivotal role in crafting cutting-edge silicon packaging solutions that drive Intel's innovation and technological leadership. In this role, you will be engaged in the end-to-end development of substrate designs, from concept to tapeout, ensuring optimized performance and manufacturability. Collaborating closely with cross-functional teams, your contributions will directly impact product quality, cost efficiency, and time-to-market for Intel's next-generation technologies. This is an exciting opportunity to start your career in a collaborative environment that fosters learning and professional growth.\n\nKey Responsibilities\n- Drive the complete development of substrate designs, starting from initial concept through tapeout.\n- Perform physical layout and routing of package designs, ensuring adherence to design requirements.\n- Conduct substrate fit and routing studies to establish optimal tradeoffs between design, performance, and cost.\n- Collaborate with silicon and hardware teams to optimize silicon-package-board performance and pinout configurations.\n- Define and implement substrate design rules to meet product and manufacturing requirements.\n- Perform internal and external design reviews, analyze data, and resolve design rule violations (DRCs).\n- Integrate design documentation and collateral into the product lifecycle management system.\n- Continuously seek opportunities to improve package design for manufacturability (DFM) and quality assurance.\n\nQualifications:\nMinimum Qualifications\n- Diploma in Electronic/ Electrical Engineering or a related field.\n- six months or more years of work experience in Semiconductor field related to design of silicon packaging or PCB.\n- Novice to intermediate proficiency in substrate design and development, including physical layout and routing.\n- Basic understanding of I/O fundamentals, package interconnect, and power delivery principles.\n- Familiarity with design for manufacturability (DFM) and quality assurance processes.\n- Strong problem-solving skills with a disciplined approach to execution.\n\nPreferred Qualifications\n-Preferred experience into E-CAD tool.\n- Effective communication skills to convey technical information and collaborate with cross-functional teams.\n- A proactive mindset to identify design improvement opportunities and ensure alignment with project goals.\n- Passion for driving innovation and contributing to complex engineering challenges.\nThis is your opportunity to be part of Intel's legacy of innovation while developing your skills and advancing your career. Apply now and help us shape the future of technology.\n\n          \n\nJob Type:\nCollege Grad\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Senior Staff Integration Design Engineer", "company": "Lattice", "location": "San Jose, CA", "date_posted": "2026-10-06", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/San-Jose-CA/Senior-Staff-Integration-Design-Engineer_R-103326", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\n\nJob Description:\nLattice Semiconductor is looking for: Senior Staff Integration Design Engineer for our San Jose Office.\n\nKey Responsibilities\n\nIntegrate IP blocks — including DDR PHY — into shared HPIO sectors to build sector- and full-chip-level views for FPGA platforms, utilizing both digital (synthesis, STA, DFT) and custom (physical/custom cell) design flows. This extends to the delivery of all corresponding models, views, and collaterals to different functional teams and the completion of all required checks and simulations for sign-off.\nOwn creation and maintenance of sector-level design constraints (SDC), including flat SDC generation for STA that reconciles clock frequency and constraint conflicts across multiple IP sources.\nRun and maintain the digital implementation flow for the sector: RTL updates, synthesis (white-box/black-box), logical equivalence checking (LEC), static timing analysis (STA), and DFT scan integration (OPCG, scan port relocation, gating cells), coordinating with DFT and third-party IP teams.\nSupport custom/physical design integration tasks for the sector, including custom cell design and reuse across sectors, parasitic (SPEF) extraction with dummy fill for STA sign-off, and clock-critical signal routing/shielding review ahead of tapeout.\nTrack and resolve sector-level design issues through the engineering issue tracker (JIRA), maintain sector release notes and schedules, and publish regular status updates to cross-functional stakeholders (Design, DFT, Verification, Product Engineering).\nRun full design verification (DV) regressions and sign-off checks for each sector release, and manage version-controlled releases of sector netlists, SDC, and related collateral.\nCollaborate with IP Design, Product Engineering, and Test teams to integrate IP-level power data into full-chip power models, and to generate and validate current/power assumptions per supply domain to support board- and system-level power budgeting.\nReview and cross check IP design's SPICE-level circuit simulation and PnR power results to characterize static and dynamic power across process, voltage, and temperature corners, and assess the power impact of any design changes.\nCorrelate simulated power models against silicon bench and production test data; support production test screen definition (e.g., leakage and worst-case process/voltage/temperature step screening) and resolve power data discrepancies tracked through the engineering issue tracker.\n\nQualifications\n\nBS or MS in Electronics/Computer/Electrical Engineering.\n15+ years of experience in ASIC, SoC, or FPGA design and product-development. \nProven in-depth experience in Custom and Digital Design Implementation for IP/sector integration. Expertise in Verilog and System Verilog is a must.\nExperience in FPGA/CPLD design and integration is a plus.\nExpertise on the following:\nDigital Design Flow\nRTL coding and verification\nLint check, elaboration/compilation, synthesis, equivalence check, SDC, and\nDFT flow and ATPG generation\nCustom Design Flow\nSemiconductor principles and transistor-level analysis\nIndustry standard tools for schematic and layout entry (Cadence Virtuoso)\nCharacterization, performance, and power simulations (SPICE preferred)\nExperience in IP and full-chip functional verification is a plus.\nExpertise in coding/scripting (Perl, TCL, Shell, Skill, Python).\nFamiliarity with issue tracking and release workflows (e.g., JIRA) in a hardware engineering environment.\nExperience in project leadership and product development cycle (planning, resourcing, tapeout, silicon characterization/validation) is a plus.\nWorking knowledge of SPICE-class circuit simulation, CMOS low-power design concepts (leakage, dynamic power, corner analysis), and correlating simulation results to silicon/bench measurement data.\nExperience with multiple process nodes/foundries (e.g., TSMC, Samsung) is a plus.\nStrong written and verbal communication skills; able to work across design, test, DFT, verification, and product engineering teams.\n\nPay & Benefits\n\nConsistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. \n\nFor candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.  The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.\n\nBase Pay Range\n220800\nIn addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! \n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in the United States.\n\nLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.\n \nAs an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.", "jd_status": "stored"}, {"title": "Firmware Engineer II", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-10-06", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Firmware-Engineer-II_R56564", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Description\nBe part of the Cadence DDR PHY IP Front End Design team responsible for -\n•             Develop firmware for DDR5 PHY using microcontrollers\n•             Developing firmware in C typically involving bare-metal programming and developing low-level APIs on Microcontrollers.\n•             Responsible for collaborating with hardware designers and memory subsystem architects to derive training algorithms and implement them.\n•             Responsible for collaborating with the verification team to deduce firmware-hardware co-verification plan.\n•             Develop and Debug firmware in RTL based hardware simulations (C +Verilog simulations)\n•             Develop and Debug on Silicon bring-up boards.\nRequired Skills:\n•             Good Knowledge of DDR5 JEDEC spec, knowledge of different DIMM configurations and specifications.\n•             Relevant experience in developing bare-metal firmware for High-speed SerDes or Memory interface Physical Layer blocks.\n•             Good Knowledge of C programming language for embedded software development and use of relevant IDE.\n•             Comfortable debugging RTL simulations involving firmware and microcontroller subsystem.\n•             Good knowledge of Shell/Perl/Python/TCL scripting\n•             Good experience on Verification EDA Tools like simulators and waveform viewers\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Firmware Engineer II", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-10-06", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Firmware-Engineer-II_R56563", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Description\nBe part of the Cadence DDR PHY IP Front End Design team responsible for -\n•             Develop firmware for DDR5 PHY using microcontrollers\n•             Developing firmware in C typically involving bare-metal programming and developing low-level APIs on Microcontrollers.\n•             Responsible for collaborating with hardware designers and memory subsystem architects to derive training algorithms and implement them.\n•             Responsible for collaborating with the verification team to deduce firmware-hardware co-verification plan.\n•             Develop and Debug firmware in RTL based hardware simulations (C +Verilog simulations)\n•             Develop and Debug on Silicon bring-up boards.\nRequired Skills:\n•             Good Knowledge of DDR5 JEDEC spec, knowledge of different DIMM configurations and specifications.\n•             Relevant experience in developing bare-metal firmware for High-speed SerDes or Memory interface Physical Layer blocks.\n•             Good Knowledge of C programming language for embedded software development and use of relevant IDE.\n•             Comfortable debugging RTL simulations involving firmware and microcontroller subsystem.\n•             Good knowledge of Shell/Perl/Python/TCL scripting\n•             Good experience on Verification EDA Tools like simulators and waveform viewers\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "RTL Design Specialist", "company": "Samsung", "location": null, "date_posted": "2026-10-06", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/RTL-Design-Specialist_R121197", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.\n\nRoles and Responsibilities\n\nCreating the power architecture and specification for the SoC to achieve low power targets and meet all KPIs\n-        Setup environment for the RTL level and gate level power analysis at the pre-silicon stage\n-        Determine tests and benchmarks to run on all IP blocks for pre-silicon power analysis\n-        Identify areas of improvement at the architecture-level, RTL-level, and during synthesis\n-        Determine and set power optimization budgets for IP blocks and execute simulations to validate them during the design stage\n-        Work with industry standard power analysis tools like Power Artist and PrimePower\n-        Document and communicate results with key SoC development and project management personnel\nSkill Requirements\n-        Good understanding of clock gating, power-gating, DVFS for power optimization\n-        Hands on working experience with power definition, estimation, planning, partitioning, analysis, and optimization\n-        Ability to work in highly competitive consumer SoC designs with strict deadlines and quality standards\n-        Worked on Lower power designs throughout the SoC development cycle from RTL, to gate-level and post-silicon correlation\n-        Good understanding of PMIC, Power electronics, digital electronics concepts\n-        Good to have\n-        Experience with power analysis and power debug tools like PTPX and Power artist\n-        Good programming and scripting skills using Perl, Python/, and TCL\n-        Understanding of CPU, GPU, SoC design\n-        Familiarity with the design flow (synthesis, place & route, power, timing)\n-        Understanding of UPF based low power verification and defining low power strategies\n\nExperience – 5 to 14 Years of Experience\n\nQualifications\n-        B.Tech/B.E/M.Tech/M.E\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\nConfidentiality Notice: Candidates are reminded that all proprietary information, trade secrets or confidential materials belonging to or obtained from their past or current employers must not be shared or used in connection with their application, interviews, or future employment with our organization\nRole and Responsibilities\n\n Define an efficient IP structure and oversee the task of designing an organically related structure for the IP blocks.\n\nSkills and Qualifications\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "Staff Engineer, Test Engineering", "company": "Analog Devices", "location": "India, Bangalore, Nova", "date_posted": "2026-10-06", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-Nova/Senior-Engineer--Test-Engineering_R262549-1", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nStaff Engineer, Test Engineering - Product Development\n \nJob Description\nADI’s Hearable Audio Solutions Business Unit is looking for a Senior engineer in test product development at our Bangalore location. The candidate will become an integral part of the Product & Test Engineering (PTE) activities for the development of mixed signal audio edge processors and battery management power products. The candidate will also be part of pre & post-silicon phase of the silicon development from DFT to silicon bring up / characterization to high volume production. The ideal candidate will be technically strong and will have demonstrated experience in testing both Digital and Analog/Mixed-Signal (AMS) Products, working with cross functional teams like Design, Bench Eval, PD, etc., with ability to collaborate with ADI global teams and off-shore subcons. \nJob Responsibilities:\n·        Design of innovative, reliable, and efficient Probe and Test solutions with highly parallel multi-site test capability using mixed signal/Digital ATE platforms (primarily ultra-flex or NI or 93K)\n·        Development of the ATE software solutions as per the specifications.\n·        Play a role in DFT/BIST definition & development, through direct involvement with the Design Team early in the New Product Development, to reduce FFC and improve testability.\n·        Execution of the Test development phases of the projects including Silicon functionality, Characterization, Yield Analysis, Correlation & Offshore Production release.\n \nQualifications:\n·        Have a degree in Electrical/Electronic Engineering\n·        Have 7-8 years’ of hands-on experience in mixed signal or digital test.\n·        Have knowledge of the ATE software development and working knowledge of Teradyne Flex, NI and/or 93K ATE systems.\n·        Have good analytical & statistical skills and knowledge of the Perl/C++ programming.\n·        Be experienced in ATE highly parallel multi-site test digital h/w design & layout, with lead skills in understanding the problems/limitations in hardware development.\n·        Be experienced in releasing multi-site test programs to offshore production test houses.\n·        Be well versed with the usage of bench equipment such as Oscilloscope, VI-meter, Signal generator and analyzers.\n·        Be capable of working with the reliability engineers on the product qual\n·        Be proactive and work under own supervision.\n·        Be self-motivated, and willing to accept responsibility.\n·        Possess strong interpersonal, teamwork & communication skills.\nWhy You'll Love Working at ADI\nAt Analog Devices, you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on professional growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world.\nYou'll have access to continuous learning opportunities and mentorship from industry experts. Join us and help create the technologies that bridge the physical and digital worlds, making a tangible difference in how people live, work, and connect.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Senior Silicon Power Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-06", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Silicon-Power-Engineer_JR2021637", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been redefining computer graphics, PC gaming, and accelerated computing for more than 25 years. Today, we are tapping into the unlimited potential of AI to define the next era of computing. As an NVIDIAN, you will address challenges spanning architecture, silicon, firmware, software, and production — and excellent judgment matters as much as technical depth! We are the Silicon Power Team within the Silicon Co-Design Group. We architect and deliver groundbreaking solutions for productizing NVIDIA's chips across consumer, professional, server, embedded, mobile, and automotive markets. Silicon characterization, correlation to arch and design expectations, product spec finalization, and productization techniques and infrastructure are our day-to-day work — always on the bleeding edge of the industry. Small decisions here have outsized impact on performance, efficiency, reliability, bring-up speed, and ultimately what the product delivers in the field.\n\nWe are hiring a Senior Silicon Power Engineer to own power-feature productization on a flagship silicon program. This is not a coordination role, and it is not a compliance role — it is the seat where power features either work at scale or become the reason a program slips. The two highest-leverage problems in this seat:\nClose the hardest multi-functional power failures before they gate a program. Take ambiguous, cross-boundary issues across architecture, firmware, validation, and platform to root-cause closure — with productized fixes and reusable methodology the next program can inherit.\n\nBuild AI-enabled characterization as a real capability, not a demo. Every bring-up generates terabytes of characterization, shmoo, and telemetry data. Deploy AI workflows for data analysis, metric extraction, trend detection, and cross-bring-up correlation — with the guardrails and validation discipline to make them trustworthy enough to gate production decisions!\n\nWhat you’ll be doing:\nLead the effort across architecture, validation, firmware, software, and production teams to keep the program's power and low-power productization strategy clear, executable, and on track.\n\nCharacterize and validate new power-saving features, debug silicon issues, and work with SW/FW teams to productize industry-defining capabilities.\n\nResolve complex silicon issues through structured hypotheses, measurement plans, and root-cause closure — and codify the fixes as reusable methodology across programs.\n\nDesign and deploy AI-enabled workflows to automate data analysis, metric extraction, trend checks, and report generation across multiple bring-ups — with explicit guardrails and measurable workflow impact.\n\nServe as the key technical owner for multi-functional decisions, issues, and tradeoffs across power, thermal, performance, firmware, and schedule constraints.\n\nPartner with globally distributed teams — system architects, chip and board designers, SW/FW engineers, applications, reliability specialists, ATE engineers, and PMs — including counterpart engineers in India and other major hubs.\n\nWhat we need to see:\nBS + 5 years, or MS + 4 years, in Electrical Engineering, Computer Engineering, or a related field (or equivalent experience), with a proven track record in post-silicon bring-up and validation of silicon power features on complex ASIC or SoC programs.\n\nDeep hands-on expertise in power-saving mechanisms, power characterization, tester-to-system correlation, and lab fundamentals (oscilloscopes, DMM, DAQ, debuggers) — with at least one specific example of taking an ambiguous power failure to root-cause closure with a productized fix.\n\nStrong end-to-end understanding of silicon behavior across architecture, firmware, validation, and platform interactions, and a demonstrated ability to make sound tradeoff decisions across power, thermal, performance, firmware, design, validation, and schedule constraints.\n\nDemonstrated AI-enabled workflow you built or scaled for silicon characterization or validation — with adoption beyond yourself, measurable workflow impact, and clear validation discipline, observability, and guardrails.\n\nWays to stand out from the crowd:\nDeep hands-on subsystem expertise across Windows and Linux low-power states, silicon power behavior, transistor/device physics, silicon reliability, and aging mechanisms — including original power-analysis methodology adopted by other programs.\n\nSilicon-level impact you personally drove — faster bring-up, stronger characterization coverage, better debug turnaround, or methodology improvements that reduced risk across programs, backed by artifacts, patents, or published technical work.\n\nExperience partnering deeply with a counterpart team in India or another major engineering hub — shared on-call, shared metrics, and shared culture across geographies.\n\nAI work that goes beyond personal-copilot use — agentic workflows, RAG-grounded debug assistants, ML-driven characterization analytics, or automated trend detection — deployed at team scope with adoption metrics\n\nIf you want to solve ambiguous silicon problems, build original methodology rather than inherit it, and use AI with the rigor required for production decisions, this role offers unusually broad ownership and unusually high leverage ! We are looking for someone who improves how NVIDIA characterizes, validates, and productizes power features across ASIC programs.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "ASIC Digital Design Manager", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-06", "url": "https://careers.synopsys.com/job/bengaluru/asic-digital-design-manager/44408/101601440336", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nYou have spent a decade building IP that ships, not just passes verification. You know that the best microarchitecture is the one that survives contact with timing closure, power constraints, and the realities of a 5nm process node. You have been the person in the room who catches the CDC issue before it becomes a silicon respin, and you have learned that the hardest part of leading a design team is not writing the cleanest RTL, it is teaching five engineers to think three steps ahead without micromanaging their every line of code.\nYou are equally comfortable reviewing a timing report at 9 a.m. and having a career conversation with a junior engineer at 3 p.m. You do not just manage projects, you grow people. When someone on your team hits a wall on a complex AXI bridge implementation, you know when to step in with technical guidance and when to let them work through it. You have strong opinions about what makes good SystemVerilog and you are not afraid to push back when an architecture decision does not make sense for the product or the schedule.\nAt Synopsys, you will lead a team building Ethernet MAC and PCS controllers that power networking silicon across the industry. The work is technically hard, the team is real, and what you build will matter.\n\nWhat You'll Be Doing\nLead a team of digital design engineers developing Ethernet MAC and PCS IP from microarchitecture specification through customer release\nDrive architectural and microarchitectural decisions for next-generation Ethernet controllers, translating customer requirements into robust, scalable RTL implementations in SystemVerilog\nOversee design reviews, timing closure strategy, CDC/RDC sign-off, and synthesis quality across multiple concurrent IP development projects\nManage resource allocation, project execution, and cross-functional collaboration with verification, physical design, and product teams to meet schedule and quality commitments\nConduct technical interviews, assess candidate capabilities in RTL design and microarchitecture, and build a high-performing team through hiring and onboarding\nMentor engineers on complex implementation challenges including high-speed interface design, multi-voltage domain architectures, and UPF-based low-power methodologies\nOwn performance reviews, career development planning, and succession planning for your team while fostering a culture of technical excellence and continuous learning\n\nThe Impact You Will Have\nDeliver Ethernet IP that powers networking products across the semiconductor industry, enabling high-speed connectivity in data centers, automotive, and AI systems\nBuild and scale a digital design team capable of executing complex IP development projects with quality, predictability, and technical rigor\nStrengthen Synopsys IP portfolio by driving architectural innovation and design reuse across Ethernet MAC, PCS, and related high-speed interface technologies\nReduce time-to-market for customers by ensuring IP releases meet timing, power, and area targets without late-stage surprises or silicon respins\nGrow the next generation of RTL design talent through mentorship, technical coaching, and hands-on leadership in real product development\nInfluence cross-functional execution by providing clear technical direction, risk assessment, and tradeoff analysis that keeps projects on track\nShape the technical culture of the Ethernet IP group by setting standards for design quality, code reviews, and engineering discipline\n\nWhat You'll Need\n10+ years of hands-on ASIC digital design experience with deep expertise in RTL development, microarchitecture, and IP design\n3+ years in a technical leadership or engineering management role, with demonstrated ability to lead, mentor, and grow design teams\nExpert-level proficiency in SystemVerilog and Verilog for synthesis, with a strong track record of delivering production-quality RTL\nDeep knowledge of high-speed interfaces and protocols such as Ethernet, PCIe, DDR, or AMBA AXI/AHB/APB\nStrong understanding of Static Timing Analysis, synthesis, timing closure, and the ability to make microarchitectural tradeoffs that meet timing and power goals\nHands-on experience with CDC and RDC verification flows, linting, and static sign-off methodologies\nExperience with low-power design techniques, UPF-based power intent definition, and multi-voltage domain architectures is a strong plus\nFamiliarity with advanced process nodes (7nm, 5nm, or below) or hardware/software co-verification using emulation platforms like Palladium or Zebu is a plus\n\nWho You Are\nYou can look at a timing report, identify the critical path, and explain to your team why the fix is not just about adding pipeline stages but rethinking the datapath architecture\nYou know the difference between mentoring someone through a tough technical problem and solving it for them, and you default to the former unless the schedule truly demands the latter\nYou ask the right questions in design reviews, the ones that uncover assumptions, expose risks, and make the team think harder about corner cases before they become bugs\nYou are comfortable having hard conversations about performance, technical gaps, or missed commitments, and you do it in a way that builds trust rather than defensiveness\nYou can explain a complex microarchitectural tradeoff to a product manager in two sentences without losing the technical nuance that matters\nYou treat hiring as seriously as you treat design reviews because you know that the quality of your team determines the quality of the IP you ship\n\nThe Team You'll Be Part Of\nYou will join the Synopsys Ethernet IP Group in Bengaluru, a team focused on designing and developing Ethernet MAC and PCS controllers that power networking solutions across the industry. This is a core IP design team, not an SoC integration group. The work centers on complex ASIC and IP development requiring deep RTL expertise, microarchitecture skills, and a strong understanding of high-speed interface technologies. You will collaborate closely with verification, physical design, and product teams to deliver IP that meets rigorous customer requirements for performance, power, and quality.\n\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Staff Applications Engineer ( ASIC, Physical Design, TCL / Python )", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-06", "url": "https://careers.synopsys.com/job/bengaluru/staff-applications-engineer-asic-physical-design-tcl-python/44408/101601440208", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent the last few years deep in the RTL2GDS flow, and you know that the real work happens in the messy middle where verification meets implementation and theory meets timing closure. You understand that a clean ECO is not about clever tricks, it is about knowing the tools well enough to make the right call under pressure when a customer's tapeout schedule depends on it.\nYou are comfortable debugging complex place-and-route issues, timing convergence challenges, congestion problems, power optimization opportunities, and physical implementation bottlenecks using Fusion Compiler. Advanced nodes do not intimidate you because you have seen what breaks at 5nm and 3nm, and you have learned how to anticipate and solve those challenges.\nYou can work directly with senior design engineers and technical leads, understand their implementation constraints, and provide practical solutions that help them reach tapeout goals. Knowledge of complementary tools such as Formality, PrimeTime, and other Synopsys signoff solutions is highly valued.\nYou also embrace modern AI-assisted workflows and understand how to leverage AI tools to improve productivity, accelerate debug, automate repetitive tasks, and deliver faster, more effective customer support. At Synopsys, you will work directly with customers building the chips that power everything from AI accelerators to automotive systems, and the solutions you deliver will matter.\nWhat You'll Be Doing\nSupport customers through physical design implementation and design closure using Synopsys tools\nDebug complex design challenges across timing, power, area, congestion, routing, and runtime optimization at advanced process nodes including 5nm and below\nHelp customers achieve implementation closure while meeting aggressive tapeout schedules and design quality requirements\nProvide technical guidance on best practices for synthesis, place-and-route, timing closure, power optimization, and advanced implementation methodologies\nBuild and maintain automation scripts in TCL to streamline workflows and improve turnaround time for customer engagements\nUtilize AI-powered tools and workflows to improve productivity, accelerate issue resolution, and enhance customer support effectiveness\nCollaborate with internal R&D teams to reproduce customer issues, validate tool behavior, and feed real-world use cases back into product development\nPresent technical solutions and recommendations to senior customer engineers and design leads during critical project phases\nWork across the full RTL-to-GDS flow, from implementation through signoff and tapeout readiness\nThe Impact You Will Have\nEnable customers to achieve first-pass silicon success on high-performance chips powering AI, automotive, networking, and mobile applications\nImprove customer productivity by helping them maximize the value of Fusion Compiler and advanced implementation methodologies\nReduce customer tapeout risk by identifying and resolving implementation challenges early in the design cycle\nInfluence Synopsys tool development by bringing real customer pain points and use cases directly to engineering teams\nAccelerate customer productivity through automation, AI-assisted workflows, and best-practice methodologies that become adopted across their organizations\nBuild long-term technical relationships with leading semiconductor companies in the region, becoming their trusted advisor for implementation and design closure challenges\nHelp shape how advanced-node designs are implemented by solving problems at the edge of what today's tools and methodologies can achieve\nStrengthen Synopsys's reputation as the partner that shows up when the hard problems need solving\nWhat You'll Need\nBachelor's degree in Electrical Engineering, Computer Engineering, or related field with at least 5 years of hands-on ASIC, physical design, implementation, or CAD engineering experience\nDirect experience with RTL-to-GDS implementation flows, including synthesis, place-and-route, timing closure, and physical design optimization\nStrong working knowledge of Fusion Compiler, ICC2, or equivalent digital implementation tools\nUnderstanding of timing, power, congestion, routing, and design closure methodologies\nWorking knowledge of Formality, PrimeTime, or related EDA tools is a strong advantage\nProficiency in scripting with TCL and Python to automate design tasks and improve workflow efficiency\nExperience with advanced process nodes (7nm and below) is a strong plus, especially if you have worked through design closure challenges at those nodes\nDemonstrated ability to leverage AI tools and automation technologies to improve engineering productivity and problem-solving effectiveness\nBusiness-level English proficiency with the ability to communicate technical concepts clearly in written and spoken form\nWillingness to engage directly with customers, including senior engineers and design managers, in both remote and onsite settings\nWho You Are\nYou can explain a complex timing, congestion, or implementation issue to a customer in two sentences without losing the technical nuance that matters\nWhen a customer escalation comes in at 4pm on a Friday, you do not panic, you prioritize, engage the right people, and drive the issue to resolution\nYou do not wait for perfect documentation or complete requirements, you ask the right questions, make reasonable assumptions, and move forward\nDetail matters to you, whether it is a script that needs to handle edge cases or a customer presentation that has to be technically accurate and clear\nYou continuously look for ways to improve efficiency and know how to leverage AI, automation, and analytics tools to increase productivity and accelerate problem-solving\nYou are comfortable working across time zones and cultures, adjusting your communication style to match the audience without losing clarity\nYou treat customer problems like they are your own, not because it is your job, but because you care about delivering solutions that actually work\nThe Team You'll Be Part Of\nJoin a dynamic team focused on Fusion Compiler deployment, advanced-node implementation, design closure, and achieving best-in-class PPA results. We value collaboration, continuous learning, innovation, and helping customers solve their most challenging physical design problems.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.", "jd_status": "stored"}, {"title": "Layout Design , Sr Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-06", "url": "https://careers.synopsys.com/job/bengaluru/layout-design-sr-staff-engineer/44408/101644992976", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in the trenches of layout design, working at nodes where every micron matters and where a floorplan decision made in week one determines whether your PHY meets timing, power, and area targets six months later. You know the difference between a layout that passes DRC and one that actually survives EMIR, latch-up, and real-world ESD events, and you have debugged enough tapeout issues to spot trouble before it becomes a showstopper.\nLeading a team does not mean delegating and disappearing. You stay technical. You jump into Calibre when someone is stuck on a PERC violation at 3nm. You review floorplans with the same rigor you expect from your team. Mentoring junior engineers is not a checkbox activity for you, it is how you scale your impact, and you know how to push senior engineers to do their best work without micromanaging them.\nYou think in tradeoffs. FinFET versus GAA at 5nm. Matching topology versus routing congestion. Customer pitch requirements versus your team's bandwidth. You do not wait for perfect specs, you work with what you have, clarify what is critical, and move the project forward. At Synopsys, you will lead layout development for DDR and HBM PHY IP that powers the memory subsystems in everything from data centers to AI accelerators.\nWhat You'll Be Doing\nLead layout development for next generation DDR and HBM PHY IP across 7nm, 5nm, 3nm, and future nodes using FinFET and GAA process technologies\nDrive floorplanning, layout matching, ESD hardening, latch-up mitigation, and PERC/EMIR closure for analog and mixed-signal blocks in high-speed memory interfaces\nOwn effort estimation, schedule planning, and execution for layout projects, coordinating across design, verification, and customer engagement teams\nMentor junior layout engineers on deep submicron effects, DFM best practices, and advanced layout techniques while challenging senior engineers to deliver higher quality on tighter timelines\nConduct layout reviews, manage quality checks using Calibre and internal flows, and drive LEF generation, bond-pad layout, IO frame design, and release processes\nTranslate PHY-level customer requirements into actionable layout constraints and work directly with customers to resolve pitch, area, and integration challenges\nStay hands-on, jumping into critical layout tasks when schedules tighten or technical problems require deep expertise to unblock the team\nThe Impact You Will Have\nYour leadership will directly shape the performance, power, and area of memory PHY IP used in flagship SoCs across hyperscale data centers, AI training systems, and mobile platforms\nThe floorplans and layout techniques you establish will become the foundation for future generations of DDR and HBM IP, influencing how Synopsys scales to next-node technologies\nYour mentorship will build a stronger, more capable layout team that can tackle increasingly complex process nodes and customer requirements with less escalation\nThe quality and turnaround time improvements you drive will accelerate customer tapeouts and reduce costly respins, strengthening Synopsys relationships with top-tier semiconductor companies\nYour ability to translate ambiguous customer specs into executable layout plans will reduce integration risk and improve first-pass success rates for memory subsystems\nThe cross-functional collaboration you foster between layout, design, and verification will break down silos and make the entire PHY development process more efficient\nYour hands-on problem solving during critical project phases will keep schedules on track and ensure that hard-won layout optimizations actually make it into silicon\nWhat You'll Need\nBachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or related field\n8+ years of hands-on layout design experience in deep submicron CMOS technologies, with direct exposure to 7nm or below\nDemonstrated ability to lead layout projects from floorplan through tapeout, including effort estimation, resource planning, and cross-functional coordination\nDeep technical expertise in layout matching techniques, ESD design, latch-up prevention, PERC/EMIR analysis, DFM rules, LEF generation, and IO frame layout\nStrong understanding of FinFET and GAA process effects, including fin quantization, middle-of-line routing constraints, and advanced node design rules\nExperience working with memory PHY IP (DDR, HBM, LPDDR, or similar high-speed interfaces) and translating customer requirements into layout constraints is a strong plus\nProficiency with Cadence Virtuoso, Calibre, and other industry-standard layout and verification tools\nWho You Are\nYou can walk into a layout review, spot a matching issue or an EMIR hotspot in thirty seconds, and explain the fix in a way that teaches the engineer something they will use on the next block\nWhen a customer asks for a 10% area reduction with no performance hit, you do not say yes or no immediately, you go back to the floorplan, run the numbers, and come back with two options and the tradeoffs for each\nYou hold your team to high standards, but you also know when someone is stuck because the problem is genuinely hard versus when they need to dig deeper, and you adjust your coaching accordingly\nSchedules slip when dependencies break, you are the person who sees it coming, pulls the right people into a room, and gets the project back on track without drama\nYou write clear, concise technical summaries that a design lead, a verification engineer, and a customer can all read and understand without needing three follow-up meetings\nYou stay current on process technology trends, not because it is required, but because you want to know what is coming at 2nm and how it will change the way you approach layout\nThe Team You'll Be Part Of\nYou will join the Silicon IP team in Hyderabad, working on DDR and HBM PHY IP development that serves customers across automotive, data center, mobile, and AI markets. This is a cross-functional environment where layout, design, and verification engineers collaborate closely to deliver cutting-edge memory interfaces on aggressive schedules. The team operates globally, with engineering centers across multiple time zones, and you will work with senior technical leaders who have been driving memory IP innovation for years. Your recruiter will share more about the team structure and current project portfolio during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Principal Engineer - Verification", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-10-06", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Senior-Technical-Staff-Engineer---Verification_R3268-26-7", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nThe dsPIC Business Unit is seeking a Senior Technical Staff Engineer – Verification to join our team in Chandler, Arizona. In this role, you will lead IP-level verification for dsPIC products using formal verification and UVM testbenches. You will work closely with cross-functional teams across the USA, India, and other global corporate teams to ensure high-quality verification results and timely project execution.\nKey Responsibilities\nArchitect, develop, and maintain UVM verification environments and Formal verification environments.\nDefine verification plans and implement constrained-random UVM Testbench and/or Formal Testbench.\nDevelop assertions and coverage in System Verilog language, analyze coverage metrics, and drive coverage closure.\nDebug RTL and testbench issues, perform root cause analysis, and collaborate with design and architecture teams to resolve defects.\nCollaborate with SoC development teams to integrate IP-level testbenches and tests into SoC-level verification environments.\nCollaborate with architects, designers, and applications teams to verify IP and product requirements and deliver quality results on schedule.\nProvide technical support and mentoring to verification engineers and drive projects to completion on schedule.\nContinuously improve verification methodologies by leveraging AI/ML automation to reduce the cycle time of verification.\n\nRequirements/Qualifications:\n\nRequired Qualifications\nBachelor’s or master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.\nMinimum 10+ years of experience in functional verification.\nStrong expertise in SystemVerilog language, assertions, and UVM methodology.\nProven experience building IP-level and SoC-level verification environments using UVM and/or formal verification Testbenches.\nExcellent understanding of digital design, RTL fundamentals, and ARM/RISC SoC architectures.\nStrong communication, teamwork, and problem-solving skills.\nHighly motivated, detail-oriented, and committed to delivering quality results on time.\n\nPreferred Qualifications\nDemonstrated success in mentoring engineers and leading verification efforts across global teams.\nExperience driving methodology improvements and automation initiatives.\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Senior ASIC Design Engineer - XBAR IP", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-06", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-ASIC-Design-Engineer---XBAR-IP_JR2027193", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking passionate, highly motivated, and creative senior design engineers to be part of its Graphics team working on the design of state of the art memory subsystem components used in their industry-leading Graphics Processors. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n\nIn this position, you will be expected to make architectural trade-offs based on features, performance requirements and system limitations, come up with micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. You will work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and backend teams to accomplish your tasks.\n\nWhat you’ll be doing:\nOwn micro-architecture and RTL development of design modules.\nMicro-architect features to meet performance, power and area requirements.\nWork with HW architects to define critical features.\nCollaborate with verification teams to verify the correctness of implemented features.\nCo-operate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable.\nInteract with FPGA and S/W teams to prototype the design and ensure that S/W is tested.\nWork on post-silicon verification and debug.\n\nWhat we need to see:\nBS / MS or equivalent experience.\n4+ years of design experience.\nExperience in RTL design of complex design units for at least two or three projects.\nExposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).\nDeep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.\nExpertise in Verilog.\n\nWays to stand out from the crowd:\nDesign experience in memory subsystem or network interconnect IP.\nGood debugging and problem solving skills.\nScripting knowledge (Python/Perl/shell).\nLeadership experience in leading small 2-3 member teams.\nGood interpersonal skills and ability & desire to work as a part of a team.\n\nNVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.\n\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior IP Design Verification Engineer - XBAR IP", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-06", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-IP-Design-Verification-Engineer---XBAR-IP_JR2027192", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of memory subsystem units for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n\nThe GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nYou will be responsible for verifying the ASIC design, architecture and micro-architecture of memory sub-systems/units using advanced verification methodologies.\n\nUnderstand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.\n\nComing up come up with test plans, tests and verification infrastructure for complex IPs/sub-systems.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nWork on advanced verification methodologies like SV/UVM.\n\nPerform functional coverage driven verification closure.\n\nWorking with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech., or equivalent experience.\n\n4+ years of relevant experience.\n\nExperience in verification of complex IPs/units and sub-systems.\n\nBackground in verification using random stimulus along with functional coverage and assertion-based verification methodologies.\n\nExpertise in Verilog.\n\nKnowledge in SystemVerilog or similar HVL / UVM or VMM.\n\nWays to stand out from the crowd:\nExperience in memory subsystem or network interconnect IP verification.\n\nDebugging and analytical skills with sound scripting knowledge.\n\nGood communication and excellent team player.\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "IP Design Verification Engineer - XBAR IP", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-06", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/IP-Design-Verification-Engineer---XBAR-IP_JR2027230", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of memory subsystem units for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n\nThe GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nYou will be responsible for verifying the ASIC design, architecture and micro-architecture of memory sub-systems/units using advanced verification methodologies.\nUnderstand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.\nComing up come up with test plans, tests and verification infrastructure for complex IPs/sub-systems.\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\nWork on advanced verification methodologies like SV/UVM.\nPerform functional coverage driven verification closure.\nWorking with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech., or equivalent experience.\n1+ years of relevant experience.\nExperience in verification of complex IPs/units and sub-systems.\nBackground in verification using random stimulus along with functional coverage and assertion-based verification methodologies.\nExpertise in Verilog.\nKnowledge in SystemVerilog or similar HVL / UVM or VMM.\n\nWays to stand out from the crowd:\nExperience in memory subsystem or network interconnect IP verification.\nDebugging and analytical skills with sound scripting knowledge.\nGood communication and excellent team player.\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior SOC Verification Engineer - Networking", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-06", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-SOC-Verification-Engineer---Networking_JR2026871-1", "is_hardware": true, "platform": "workday", "jd_text": "We are now looking for a SOC Verification Engineers! NVIDIA is seeking outstanding SOC Verification Engineers to verify world’s leading Smart Network Interface Cards (Smart-NICs) and Data Processing Units (DPUs). NVIDIA’s Networking Chip Design group works on Smart-NICs and DPUs which help accelerate network performance while reducing the CPU overhead of Internet Protocol (IP) packet transport, freeing more processor cycles to run applications. These networking processors also embed innovative hardware engines that offload and accelerate security with in-line encryption/decryption.With unmatched RDMA over Converged Ethernet (RoCE) performance, NVIDIA Smart-NICs and DPUs deliver efficient, high-performance remote direct-memory access (RDMA) services to bandwidth- and latency-sensitive applications!\n\nThe Networking Chip Design in India is a new team which is growing at a fast pace! We are currently seeking Verification Engineers with strong verification fundamentals to work in NVIDIA Networking Group's SOC team. As a SOC Verification Engineer at NVIDIA, be responsible for verification of the design, architecture and micro-architecture with opportunities for pre-silicon, emulation, and post-silicon activities. You will be working closely with architects, designers, emulation team, Software teams, pre and post silicon verification teams to accomplish your tasks.\n\nWhat you’ll be doing:\nBe responsible for integrating all the pieces for a given defined project milestone and deliver the model to relevant teams for further verification at cluster/sub-system/SOC/emulation levels.\nCome up with verification infrastructure and automated flows to ease the process of integrating multiple IPs\nUse advanced verification methodologies like e-specman, SV-UVM etc. and have good grasp of scripting languages like python,perl etc.\nPartnering closely with our design team to understand our architecture and the collaborate with Quality Assurance engineers to deliver excellent test coverage and improve the Hardware quality.\nCoordinate with internal and external teams across time zones.\n\nWhat we need to see:\nBS or MS in EEE or ECE with 4+ years of experience in design verification\nGood understanding of Logic Design and Architecture.\nStrong coding skills in SV, scripting languages (Perl/python) and C++.\nAbility to collaborate and work with multiple groups\nExposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.).\nExposure to Cluster/Sub-system/Fullchip/SOClevel verification environments\n\nWays to stand out from the crowd:\nPrior experience of SmartNICs (or DPU) and/or high-speed interconnects.\nStrong debugging, problem-solving and analytical skills.\nScripting knowledge (Python/Perl/shell).\nGood interpersonal skills and ability & desire to work as an excellent teammate.\n\nWidely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/\n\nNVIDIA is committed to encouraging a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "IP Design Verification Engineer - XBAR IP", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-06", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/IP-Design-Verification-Engineer---XBAR-IP_JR2027178-1", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of memory subsystem units for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n\nThe GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nYou will be responsible for verifying the ASIC design, architecture and micro-architecture of memory sub-systems/units using advanced verification methodologies.\nUnderstand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.\nComing up come up with test plans, tests and verification infrastructure for complex IPs/sub-systems.\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\nWork on advanced verification methodologies like SV/UVM.\nPerform functional coverage driven verification closure.\nWorking with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech., or equivalent experience.\n2+ years of relevant experience.\nExperience in verification of complex IPs/units and sub-systems.\nBackground in verification using random stimulus along with functional coverage and assertion-based verification methodologies.\nExpertise in Verilog.\nKnowledge in SystemVerilog or similar HVL / UVM or VMM.\n\nWays to stand out from the crowd:\nExperience in memory subsystem or network interconnect IP verification.\nDebugging and analytical skills with sound scripting knowledge.\nGood communication and excellent team player.\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Applications Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-10-06", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25017143", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n  Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\n  Our business has very high growth in TI and is in a segment where the market is fast growing. We're searching for applications engineer who have the passion and excitement to grow, innovative, take an active role in product definition, execute the characterization until ramp, and provide post ramp application support to customers.\n\n  This role is responsible for application support for high speed amplifiers. Key responsibilities include:\n\nAnswer customer questions and supporting design-in activities for released products. This includes:\n\nForum and email questions from customers\n\nSchematic and Layout Review of customer application\n\nDebug of customer problems by re-creating issues in our evaluation boards and/or customer boards\n\nOn-site support for customer board as required\n\nDesign EVM and internal evaluation boards to support correlation and evaluation activities of new products\n\nCreate user guides, test procedures and proper release of EVM boards for customer consumption\n\nParticipate in datasheet review to ensure completeness of datasheet being developed by the Systems Engineer\n\nPerform Bench Characterization for High Speed Amplifiers devices, including bench automation, hardware design and develop test techniques\n\nParticipate in new silicon testing from an application perspective to ensure robustness of the product (i.e. destructive testing)\n\nWork with systems engineer to provide support to early design in activities for new products\n\nCreate custom reference designs targeting relevant applications to be used as customer implementation ideas\n\nWrite application notes that explain different use cases, implementation and/or flexibility of our products\n\nQualifications\nMinimum requirements\n\nBachelor's degree in Electrical Engineering, ECE, or related field\n\n3 years of relevant experience\n\nExperience in applications support of analog products\n\nSolid hardware and software debugging skills\n\nStrong technical background, with the ability to produce high quality technical documentation\n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Senior Technical Staff Engineer-Verification", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-10-06", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Senior-Technical-Staff-Engineer-Verification_R4057-26", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nMicrochip’s Communications Business Unit (CBU) develops high-performance networking, connectivity, and edge compute semiconductor solutions that power communications infrastructure, data centers, automotive systems, aerospace and defense platforms, and industrial applications. Our global team works across the full product lifecycle to deliver innovative products that enable the world’s most demanding connected systems. \n\nThe CBU Product Development team is engaged through the full device R&D cycle from concept, design and implementation stages. Once a prototype is available, we support embedded software development and system validation lab testing through to mass-market production release. We are an experienced chip team working with the latest semiconductor development tools and methodologies in advanced process technologies to develop state-of-the-art network devices.\n\nWe are seeking a Verification focused Technical Staff Engineer in the CBU Product Development team who will be responsible for the verification strategy and technical leadership of communication semiconductor devices and subsystems. We are looking for an experienced hands-on technical leader who can directly contribute to all aspects of verification from planning, testbench architecture to coverage closure and sign-off readiness at the block and top level of a device. The individual should be to solve challenging engineering problems with innovative solutions and mentor engineers. The individual will be a key member of the CBU’s Silicon Design Center in India with technical leadership and mentoring responsibilities.\n\nResponsibilities may include:\nVerification Architecture and Strategy\nOwn or contribute to verification architecture for leading-edge communications devices\n\nBuild system-level understanding of device applications and use it to define complete, risk-based verification plans\n\nCollaborate with Product Marketing, Applications Engineers, System Architects, Designers and Customers to identify, record, track and verify device requirements\n\nPartition verification scope across block, subsystem and device levels, including reusable verification components and coverage models\n\nParticipate in concept and feasibility studies for next-generation products by identifying verification risks, methodology needs and validation alignment early in the development cycle\n\nTechnical Leadership\nLead delivery of verified digital integrated circuits at the device, subsystem or block level as a Verification Architect, Verification Lead or Technical Leader\n\nMentor and provide technical direction to a small team of Verification Engineers\n\nPartner with Design Leads and Architects to align implementation intent, verification strategy and sign-off expectations\n\nTranslate industry standards, market requirements and functional specifications into executable verification plans, coverage goals and measurable closure criteria\n\nDevelop verification platforms guided by UVM methodology and implemented with SystemVerilog, assertions and reusable verification components\n\nDrive verification execution, debug, regression quality, coverage closure and sign-off readiness using industry-leading tools and flows\n\nDomain Expertise\nDevelop or enhance technical expertise in technologies, verification methodologies, flows or standards\n\nContribute to verification best practices for industry standards such as Ethernet, OTN and related networking technologies\n\nProvide subject-matter guidance to development teams within CBU on verification strategy, methodology, debug and closure\n\nEnhance internal, proprietary verification flows and practices to improve efficiency, completeness, reuse and sign-off quality\n\nCross Functional Responsibility\nCollaborate with Software, Validation, Applications, Production Engineering and Design teams to deliver production-worthy devices that integrate into a wider system and are supported by robust verification evidence\n\nRequirements/Qualifications:\n\nQualifications:\nBachelor’s or Master’s Degree in Electrical Engineering or Computer Engineering12+ years related experience\nExcellent analytical and debugging skills and the ability to proactively solve issues\nProven ability to thrive on, learn and adapt to new methodologies and technologies\nStrong coding skills\nExperience using one or more of SystemVerilog/Verilog/VHDL, Tcl/Perl/Python, C/C++, XML\nDemonstrated experience verifying complex digital integrated circuits using SystemVerilog, UVM, assertions, constrained-random testing, coverage-driven verification, formal verification or related methodologies\nExcellent verbal and written communication skills in English\nFamiliarity with communication protocols such as Ethernet, ASA and others (an asset)\nExperience with Synopsys, Cadence or similar verification, simulation, formal, debug, coverage or regression management tool flows (an asset)\nExperience with state-of-the-art silicon process technologies and complex SoC verification environments (an asset)\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Principal Verification Engineer", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-10-06", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Principal-Verification-Engineer_R4160-26-6", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nMicrochip’s Communications Business Unit (CBU) develops high-performance networking, connectivity, and edge compute semiconductor solutions that power communications infrastructure, data centers, automotive systems, aerospace and defense platforms, and industrial applications. Our global team works across the full product lifecycle to deliver innovative products that enable the world’s most demanding connected systems. \n \nThe CBU Product Development team is engaged throughout the device R&D cycle, from concept and design through implementation. Once a prototype is available, we support embedded software development and system-validation lab testing through mass-market production release. Our experienced chip-development team uses the latest semiconductor tools and methodologies, together with advanced process technologies, to develop state-of-the-art networking devices.\n \nAs a Principal Engineer on the CBU Product Development team, you will be responsible for verifying digital integrated circuits at the block or device level. You will collaborate with chip architects, subsystem leads, and verification team members to deliver increasingly complex designs in a friendly, professional environment.\n \nThe role of the Principal Engineer includes: \nVerification\nOwn the verification of complex digital integrated circuits at the block, subsystem, or device level.\nUnderstand the device requirements and functional description to ensure compliance with specifications and error-free operation.\nPlan verification activities, develop testbenches, and execute tests.\nDevelop verification platforms using the UVM methodology and SystemVerilog.\n\nTechnical Leadership\nDeliver verified designs at the Device, Subsystem or Block level\nPartner with a dedicated Design Lead to deliver high-confidence designs\nVerify designs implemented in SystemVerilog RTL using industry-standard methodologies.\n\nDomain Expertise\nContribute to the development and enhancement of verification technologies and methodologies.\nCross Functional Responsibility\n\nCollaborate with Software and Validation teams to deliver devices that integrate into a wider system.\nParticipate in Product Validation during the prototype stage of development.\n\nRequirements/Qualifications:\n\nBachelor’s or Master’s Degree in Electrical Engineering or Computer Engineering\n8+ years related experience\nExcellent analytical and debugging skills and the ability to proactively solve issues\nProven ability to thrive on, learn and adapt to new methodologies and technologies\nStrong coding skills\nExperience using one or more of System Verilog/Verilog/VHDL, Tcl/Perl/Python, C/C++\nExcellent verbal and written communication skills in English\nExperience with verification methodologies, including UVM, formal verification, and constrained-random verification.\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Physical Design  Lead - CPU Team", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-05T14:14:00+00:00", "url": "https://global-external-amd.icims.com/jobs/89739/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. MTS Design Engineer   THE ROLE: The position will involve working with a very experienced CPU physical design team. The person is responsible for delivering the physical design of critical CPU units to meet challenging goals for frequency, power, and other design requirements for AMD's next-generation processors in a fast-paced environment with cutting-edge technology. THE PERSON: Engineer with a good attitude, strong analytical skills, effective communication, and excellent problem-solving abilities. KEY RESPONSIBILITIES: Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure. Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA. Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff. Handling different PNR tools - Synopsys fusion compiler, Cadence, PrimeTime, StarRC, Calibre, Apache Redhawk PREFERRED EXPERIENCE: 7+ years of professional experience in physical design, preferably with high-performance designs. Must have closed high-performance IPs- CPU/GPU/DPU/memory controller, etc. Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality; familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow - Perl/Tcl/Python Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in advanced sub 7nm nodes Excellent physical design and timing background. A good understanding of computer architecture is preferred. Strong analytical/problem-solving skills and pronounced attention to detail. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering #LI-RR1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Staff Engineer ", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-10-05T11:46:22+00:00", "url": "https://jobs.infineon.com/careers/job/563808972123711", "is_hardware": true, "platform": "eightfold", "jd_text": "Seeking a Semiconductor Test Engineer with expertise in ATE test development, DFT, and SoC validation for RF, connectivity, and IoT products. The role focuses on silicon bring-up, characterization, production testing, yield improvement, and test automation using Teradyne UltraFLEX platforms. The ideal candidate will combine strong technical problem-solving skills with cross-functional collaboration to deliver high-quality, scalable test solutions for volume manufacturing.\n\nYour role\nKey responsibilities in your new role\n\nShould have strong knowledge of semiconductor device fundamentals, including analog/digital circuits and circuit theory, to support product test development and validation.\nUtilize expertise in Design for Test (DFT) methodologies, including ATPG, PMU blocks, BUCLK, LDOs, and trimming techniques.\nDevelop and execute semiconductor test solutions using Teradyne UltraFLEX-RF platforms; experience with UltraFLEX+ is an added advantage.\nCreate, debug, and optimize ATE test programs, while troubleshooting hardware- and software-related test issues.\nProvide technical support and test engineering expertise to internal teams, manufacturing partners, and customers.\nDevelop automation and test solutions using programming and scripting languages such as Perl, Python, C, C++, Java, and Visual Basic.\nDevelop and debug characterization and production test programs for SoC connectivity products, including Digital, Mixed-Signal, PMU, NVM, and RF blocks.\nCollaborate closely with cross-functional teams including IP Design, Applications, DFT, Product Engineering, and Test Engineering to ensure smooth product development and production release.\nLeverage UNIX/Linux environments, shell scripting, and command-line tools for test automation, debugging, and workflow optimization.\nDemonstrate strong communication, problem-solving, and teamwork skills while working in a global engineering environment.\n\nYour profile\nQualifications and skills to help you succeed \n\nDevelop and document comprehensive test plans and validation strategies for next-generation IoT products.\nDesign, develop, and debug ATE hardware and software solutions for production and reliability testing.\nPerform silicon bring-up, characterization, and debugging on Automated Test Equipment (ATE) platforms.\nDeliver high-quality, cost-effective test solutions to support high-volume manufacturing.\nCoordinate and oversee test-related hardware and software activities with both internal teams and external test houses.\nDevelop, optimize, and release production test programs for offshore manufacturing and production sites.\nDrive continuous improvements in test coverage, yield, quality, and manufacturing efficiency.\nBachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical & Electronics Engineering (EEE), or a related discipline.\nStrong team player with a proactive approach and passion for continuous learning and innovation.\nQuick learner with strong analytical and problem-solving abilities.\nOpen-minded, transparent, and collaborative in approach.\nEffective communicator with strong interpersonal and stakeholder management skills.\nDemonstrates ownership, accountability, and a results-driven mindset.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nAnand Rawal", "jd_status": "stored"}, {"title": "Senior Staff Engineer", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-10-05T11:33:18+00:00", "url": "https://jobs.infineon.com/careers/job/563808972123712", "is_hardware": true, "platform": "eightfold", "jd_text": "Seeking a Senior ATE Test Engineer with 10+ years of experience in semiconductor test development for RF SoC, wireless connectivity, and IoT products. The role involves leading ATE test solution development, silicon bring-up, characterization, production testing, yield improvement, and product qualification using Teradyne UltraFLEX/UltraFLEX Plus or Advantest V93K platforms. The ideal candidate will possess strong expertise in Digital, Analog, and RF testing, DFT methodologies, automation, and technical leadership, with the ability to drive high-quality test solutions from product development through volume manufacturing.\n\nYour role\nKey responsibilities in your new role\n\nLead the development and ownership of ATE test solutions and hardware for wafer-level and package-level testing of SoC, RF, wireless connectivity, and IoT products.\nDevelop, debug, and enhance characterization and production test programs for RF SoCs, wireless connectivity devices, and microcontrollers.\nDesign and implement multi-site ATE hardware solutions on Teradyne UltraFLEX and UltraFLEX Plus platforms.\nUtilize strong expertise in DFT, circuit design, ATE methodologies, DOE, and SPC to drive robust test coverage and product quality.\nTroubleshoot customer application challenges, manage RMA investigations, and ensure timely issue resolution through effective root-cause analysis.\nCreate and optimize test programs while driving yield improvement, test cost reduction, and manufacturing efficiency initiatives.\nValidate product performance and ensure compliance with datasheet specifications throughout design optimization and customer qualification phases.\nProvide technical leadership and test engineering support to both internal teams and external customers.\nDrive device and package qualification activities for new product introductions and production transfers.\nSupport first silicon bring-up, debug, yield enhancement, and test-time optimization, working closely with design and test teams to achieve production readiness.\nCollaborate with cross-functional teams including IP Design, Applications, DFT, Product Engineering, and Test Engineering across global development sites to ensure successful product delivery.\n\nYour profile\nQualifications and skills to help you succeed \n\nMust have minimum 10+ years of experience in ATE test solution development and semiconductor product testing.\nBachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Science, or a related discipline.\nHands-on experience developing multi-site test solutions on Teradyne UltraFLEX, UltraFLEX Plus, and/or Advantest V93K platforms.\nStrong expertise in Digital, Analog, and RF test development.\nProficiency in programming languages such as VB, C, C++, and Java, with automation scripting experience in Perl, Python, and/or MATLAB.\nWorking knowledge of Teradyne IG-XL (Version 9 and above) is preferred.\nExperience using electronic laboratory equipment, including oscilloscopes, logic analyzers, signal generators, power supplies, and source-measure units (SMUs).\nProven ability to lead projects, drive manufacturing improvements, manage change, and implement effective test solutions.\nStrong presentation and communication skills with the ability to clearly convey technical concepts and project objectives.\nComfortable working in a fast-paced, collaborative, and cross-functional environment.\nDemonstrated technical leadership, mentoring capabilities, and excellent interpersonal skills.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nAnand Rawal", "jd_status": "stored"}, {"title": "Principal Engineer", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-10-05T11:21:45+00:00", "url": "https://jobs.infineon.com/careers/job/563808972123713", "is_hardware": true, "platform": "eightfold", "jd_text": "We are seeking an experienced ATE Test Engineer with 12+ years of expertise in semiconductor test development for SoC, RF, IoT, and connectivity products. The role involves owning end-to-end ATE test solutions, including silicon bring-up, characterization, production testing, yield improvement, and product qualification. The ideal candidate will have hands-on experience with Teradyne UltraFLEX/UltraFLEX Plus or Advantest V93K platforms, strong knowledge of DFT, mixed-signal and RF testing, and proven ability to collaborate across design, product engineering, and test teams to deliver robust, high-quality manufacturing solutions.\n\nYour role\nKey responsibilities in your new role\n\nOwn and drive ATE test solutions and hardware development for wafer-level and package-level testing of SoC, RF, and IoT products.\nDevelop, debug, and maintain characterization and production test programs for wireless connectivity, PSoC Edge, and microcontroller devices.\nDesign and support multi-site ATE hardware solutions on Teradyne UltraFLEX and UltraFLEX Plus platforms.\nApply strong expertise in DFT, circuit analysis, process-design-test integration, DOE, and SPC to improve product quality and test effectiveness.\nLead the resolution of customer application issues and RMA investigations, ensuring timely root-cause analysis and closure.\nCreate and enhance test programs, driving manufacturing improvements and production efficiency across existing and new products.\nValidate product performance and ensure compliance with datasheet specifications throughout design optimization and customer sampling phases.\nProvide technical guidance and troubleshooting support to internal teams, manufacturing partners, and customers.\nDrive device and package qualification, supporting new product introduction and successful production transfers.\nParticipate in first silicon bring-up, debug, yield improvement, and test time optimization to enable high-volume manufacturing.\nCollaborate closely with cross-functional teams including IP Design, Applications, DFT, Product Engineering, and Test Engineering to ensure successful product development and production release.\n\nYour profile\nQualifications and skills to help you succeed \n\nMust have minimum 12+ years of experience in ATE test development and semiconductor product testing.\nBachelor's or Master's degree in Electronics, Electrical Engineering, Computer Science, or related fields.\nHands-on experience with Teradyne UltraFLEX, UltraFLEX Plus, and/or Advantest V93K platforms.\nStrong expertise in Digital, Analog, Mixed-Signal, and RF testing.\nSound knowledge of DFT, ATPG, PMU, DOE, SPC, and semiconductor test methodologies.\nProficiency in C, C++, Java, Visual Basic, Perl, Python, MATLAB, or similar programming languages.\nExperience with IG-XL (v10+) and lab equipment such as oscilloscopes, logic analyzers, signal generators, and SMUs.\nStrong analytical, problem-solving, communication, and technical leadership skills.\nProven ability to mentor teams and drive manufacturing and test process improvements.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Staff Engineer", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-10-05T10:56:44+00:00", "url": "https://jobs.infineon.com/careers/job/563808972123716", "is_hardware": true, "platform": "eightfold", "jd_text": "Seeking a Semiconductor Test Engineer with expertise in DFT, ATE testing, silicon bring-up, and SoC validation. The role involves developing and optimizing test solutions for IoT and connectivity products, supporting production, characterization, and reliability testing using Teradyne UltraFLEX-RF platforms. Ideal candidates will have strong programming, debugging, and cross-functional collaboration skills, along with a Bachelor's or Master's degree in ECE, EEE, or a related field.\n\nYour role\nKey responsibilities in your new role\n\nMust have strong understanding of semiconductor device fundamentals, including analog and digital circuits, as well as circuit theory.\nApply in-depth knowledge of Design for Test (DFT) methodologies, including ATPG and PMU blocks such as BUCLK and LDOs, along with trimming procedures.\nLeverage expertise in semiconductor testing methodologies using Teradyne UltraFLEX-RF platforms; experience with UltraFLEX+ is an added advantage.\nDevelop, debug, and optimize ATE test programs while resolving hardware-related test issues.\nProvide technical support, root-cause analysis, and test engineering expertise to both internal and external stakeholders.\nUtilize scripting and programming skills in languages such as Perl, Python, C, C++, Java, and Visual Basic to enhance test development and automation.\nDevelop and debug characterization and production test programs for SoC connectivity products encompassing digital, mixed-signal, PMU, NVM, and RF blocks.\nCollaborate closely with cross-functional teams across design centers, including IP Design, Applications Engineering, DFT, Product Engineering, and Test Engineering to ensure successful product development and qualification.\nWork effectively in UNIX/Linux environments, leveraging shell scripting and command-line tools for automation and debugging.\nDemonstrate strong verbal and written communication skills while working in a global and cross-functional environment.\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor's or Master's degree in Electronics & Communication (ECE), Electrical & Electronics (EEE), or related fields is must.\nStrong team player with a passion for continuous learning and technology.\nDevelop and execute test plans for IoT devices.\nDesign, develop, and debug ATE hardware and software for production and reliability testing.\nPerform silicon bring-up and debug on ATE platforms.\nDeliver cost-effective, high-quality test solutions for mass production.\nCoordinate test activities with internal teams and external test houses.\nDevelop, optimize, and release production test programs.\nQuick learner with strong analytical and problem-solving skills.\nOpen-minded, transparent, and collaborative.\nStrong communication and interpersonal skills.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": " ASIC Physical Design & Implementation Lead", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-05T09:58:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92749/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. ASIC Physical Design & Implementation Lead : THE ROLE: The focus of this role in the AECG ASIC organization is to lead physical design for next generation ASICs that meet Engineering, Business and Customer requirements. Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. KEY RESPONSIBLITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Deft at Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus. Tasks to include Full Chip Level Floor planning, Bus / Pin Planning, feed-thru planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, Physical Verification and Sign Off Identify complex technical problems, break them down, summarize multiple possible solutions, Drive and hands-on flow development and scripting PREFERRED EXPERIENCE: 12+years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: BS or MS degree in in Electrical Engineering or Computer Science. 12years of experience in physical design role leading to an understanding of RTL to GDS development. #LI-SR4 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Physical Design Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-05T09:56:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92753/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. THE ROLE: The position will involve working with a very experienced physical design team and is responsible for delivering the physical design of blocks/tiles to meet challenging goals for frequency, power and other design requirements for AMD next generation chips in a fast-paced environment on cutting edge technology.   THE PERSON: Engineer with a good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus Provide technical support to other teams PREFERRED EXPERIENCE: 3-5 years of professional experience in physical design, preferably ASIC designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Strong analytical/problem solving skills and pronounced attention to details ACADEMIC CREDENTIALS: Bachelors or Masters degree in Computer Engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Staff Engineer Analog Mixed-Signal Verification", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-10-05T09:26:45+00:00", "url": "https://jobs.infineon.com/careers/job/563808971219634", "is_hardware": true, "platform": "eightfold", "jd_text": "Highly skilled AMS Verification Engineer with expertise in SystemVerilog RNM modeling, AMS verification, and Automotive mixed-signal products. Proven track record in leading subsystem and full-chip (AoT) verification, developing high-performance behavioral models, AMS test plans, checkers, assertions, and coverage solutions. Strong knowledge of BGR, LDO, Buck-Boost regulators, Cadence/Synopsys simulation environments, SoC power analysis, and automation using Python, Perl, and Shell scripting. Recognized for driving verification efficiency, enabling system-level validation, and mentoring engineering teams.\n\nYour role\nKey responsibilities in your new role\n\nDeveloping AI based Advance\nbehavioral Real Number Model using system Verilog for analog/mixed-signal\n(AMS) verification, optimizing speed and accuracy trade-offs for\npre-silicon validation.\nLead AMS verification of Automotive products at sus system & Full\nchip (Analog on top).\n Develop AMS test plan by understanding requirements and AMS checkers.\n Behavioral model development for analog blocks using System Verilog (RNM).\n\nGood understanding on EDA\ntools/simulators (Cadence - virtuoso schematic editor, Xcelium, APS/XPS OR\nSynopsys – VCS).\nGood understanding of\nanalog design concepts – BGR, LDO, Buck – Boost Regulators.\n\nExperience in Python, Perl, Shell scripting is added\nadvantage.\n\nYour profile\nQualifications and skills to help you succeed \n\nGood working experience in Analog & mixed signal verification\ndomain.\nGood understanding of analog circuits and ability to write SV RNM models\nusing SV.\nAbility to develop AMS test plan, implement TB components, integrate\nspice netlists, develop checkers, assertions, coverage, and debugging AMS\nsimulations.\nInteract with Analog, RTL & DV teams to bring up system level\nscenarios in AMS environment.\nEfficient working knowledge on EDA tools/simulators (Cadence - virtuoso\nschematic editor, Xcelium, APS/XPS OR Synopsys – VCS, Customsim).\nProvide support to characterization teams during post-silicon\nvalidation.\nSelf-motivated to work effectively & incorporate next generation AMS\nmethodologies.\nHandling\nproject dynamics on scope, schedule and effort – coming up with alternative\nverification plans, Mentoring Junior engineer.\nAbility\nto perform Power analysis at SOC level.\nAutomation\nusing shell/Perl/Python script.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nVidhi Thakkar", "jd_status": "stored"}, {"title": "Physical Design Lead(High Speed IP's)", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-05T09:19:00+00:00", "url": "https://global-external-amd.icims.com/jobs/93149/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. SMTS SILICON DESIGN ENGINEER THE ROLE: AMD is looking for an experienced and highly motivated Senior Member of Technical Staff (PMTS) to join the CT Physical Design team. In this role, you will drive the physical implementation of industry-leading high-speed interface IPs including DDR, LPDDR, GDDR, PCIe, and other next-generation mixed-signal PHY solutions used across client, server, and graphics products. As a technical leader, you will work closely with architects, circuit designers, RTL, package, power integrity, signal integrity, SoC, and methodology teams to define and implement innovative physical design solutions that achieve aggressive PPA, frequency, power, and schedule goals on advanced process nodes. The ideal candidate combines deep physical design expertise with strong leadership capabilities and a proven track record of delivering complex, high-performance IPs to production. THE PERSON: You are passionate about solving complex physical design challenges in advanced semiconductor technologies. You thrive in fast-paced environments, influence technical direction beyond your immediate team, and enjoy mentoring engineers while driving innovation in implementation methodologies. You possess deep understanding of high-speed digital and mixed-signal design implementation and have successfully delivered multiple tape-outs in advanced technology nodes. KEY RESPONSIBLITIES: Lead physical design implementation of complex high-speed IPs such as DDR/LPDDR/GDDR PHYs, PCIe, SerDes, and related subsystems. Own end-to-end implementation activities Drive high-frequency timing closure for challenging datapaths and clock distribution networks. Partner with architects and circuit designers to optimize PHY architectures for performance, power, and implementation efficiency. Develop and deploy innovative implementation methodologies to improve design quality, productivity, and scalability. Collaborate with cross-functional teams including Architecture, RTL, AMS, Package, SI/PI, Product Engineering, SoC, CAD, and EDA vendors. Provide technical leadership for multiple projects and influence implementation strategies across organizational boundaries. Mentor junior engineers and help grow the technical capability of the organization. Drive continuous improvement initiatives in automation, AI-assisted design methodologies, and signoff flows. PREFERRED EXPERIENCE: 12+ years of industry experience in Physical Design for advanced semiconductor products. Proven track record delivering multiple successful tape-outs on advanced technology nodes (N3/N4/N5 or equivalent). Extensive experience with high-performance and high-speed interface IPs Deep expertise in one of the fields: Timing, EMIR, clock tree, physical verification Expertise with industry-standard EDA tools including Cadence and Synopsys implementation/signoff flows. Experience driving methodology development and automation. Demonstrated leadership across cross-functional teams and geographies. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-PM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Lead Server Performance Architect", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-05T08:52:00+00:00", "url": "https://global-external-amd.icims.com/jobs/91616/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. Lead Server Performance Architect: AMD is looking for an outstanding technical contributor to help architect, validate & optimize performance of new features through full chip simulation & emulation platforms for AMD-based next-generation servers. As a passionate and dedicated Server Systems Performance Architect in the Server Performance Group, you will identify new opportunities to optimize server silicon for throughput and latency by identifying opportunities across all parts of silicon micro architecture and design spanning CPU, Data Fabric, Memory subsystem and IO. You will validate and analyze performance of various design features in pre silcon design env and correlate the profiling data with AMD performance model and eventually AMD silicon. You will quantify and isolate performance bottlenecks and share the insights to help new drive features into the next generation of server CPUs. The ideal candidate is expected to be well informed on latest trends in server design and verification, have a well-rounded understanding of performance requirements for server market and be able to quickly ascertain, in a data-driven manner, how next generation server CPUs and platforms should be engineered to support those needs Key Responsibilities: Team Leadership Lead and mentor a high-performing team of performance verification engineers. Foster a culture of innovation, technical rigor, and continuous improvement. Provide strategic direction across multiple concurrent verification programs. Program Leadership Define and execute the performance verification strategy for high-performance x86 server CPU. Collaborate with architecture, u-arch, RTL, performance modeling, firmware, and software teams to define and validate performance KPIs. Ensure timely delivery of simulation/emulation results, and optimization feedback loops. Performance Analysis & Correlation Develop and execute performance verification plans targeting IPC, latency, throughput, and power efficiency. Capability to debug performance outliers thru Performance Monitoring Counters (PMC). Drive correlation between RTL and performance models, ensuring architectural intent is met. Analyze performance bottlenecks using simulation, emulation, and silicon data. Toolchain & Methodology Build and maintain scalable, modular performance verification infrastructure. Lead emulation-based performance setup and debug, enabling early performance validation. Integrate performance regression, profiling, and analysis flows using industry-standard and custom tools. Collaborate with compiler and OS teams to ensure software stack alignment with hardware performance goals. AI-Driven Infrastructure Drive the development of AI/ML-based infrastructure to automate performance analysis, anomaly detection, and efficiency improvements. Leverage data-driven techniques to optimize verification coverage and reduce debug cycles. Cross-Functional Collaboration Partner with x86 architecture, RTL design, physical design, and software teams to ensure performance targets are met. Influence design decisions through data-backed performance insights. Stakeholder Management Align verification goals with business and product roadmaps. Communicate performance status, risks, and trade-offs to executive leadership and stakeholders. Industry Awareness Stay current with trends in CPU architecture, performance modeling, and verification technologies. Evaluate and adopt emerging tools and techniques to maintain a competitive edge. Preferred Experience 15+ years of industry experience with performance modeling and simulation tools (e.g., cycle-accurate simulators, emulators) with strong background in CPU microarchitecture, performance analysis, and system-level performance verification. Proven leadership in managing large, cross-functional engineering teams. Familiarity with PMC DV, latency and throughput validation, emulation platforms, and performance debug flows. Deep understanding of x86 ISA, microarchitecture, and performance metrics. Experience in developing performance test suites, performance triage tools, and simulation/emulation infrastructure. Expertise in performance analysis tools, correlation techniques, and workload optimization. Strong analytical and problem-solving skills with a data-driven mindset. Deep knowledge of modern out-of-order CPU cores, memory subsystems, and performance modeling is a plus. Experience with ML/AI techniques/frameworks for performance triage, infrastructure automation and prediction is a plus. Exposure to high-performance computing (HPC), virtualization, or server-class CPUs. Background in hardware/software co-design and performance-aware compiler optimizations. Familiarity with pre-silicon and post-silicon debug methodologies. Position Requirements: Should have executed Emulation based functional and performance verification for multimillion gate SoC designs Should have strong exposure to RTL coding and SOC bringup debug Exceptional foundation in systems architecture, cutting across CPU, memory, storage and I/O subsystems Experience with hardware performance counter monitoring tools Should have exposure to performance profiling tools, preferably x86 based (e.g. linux perf, Windows perfmon) MS/PhD in Computer Engineering / relevant coursework / thesis Excellent communication skills (verbal, written, and presentation) > 12 years relevant industry experience #LI-PK1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "CPU Post Si Validation Engineer(Power and Performance)", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-05T07:19:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92801/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. CPU Post Si Validation Engineer(Power and Performance)   THE ROLE: The AMD Cores system validation team is looking for a dynamic, energetic CPU Cores Validation engineer to join our growing team focused on the Zen CPU. Cores Systems Validation Engineer will architect, drive and perform hands-on system level debug to isolate functional failures to a specific IP or domain. Exposure begins at the architecture level, working with pre-silicon teams to maximize pre-silicon coverage, post-silicon bring-up and enablement, and engagement through production and working with customer facing teams for best adoption. You will work in a dynamic environment, directly with the product, tools, motherboards, and BIOS/OS. THE PERSON: As a key contributor to the success of AMD’s Cores roadmap, you will be driving and directing a high performing team towards the delivery of high quality, industry-leading processors to the market. The validation team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. KEY RESPONSIBILITIES: Orchestrate the validation of CPU Cores by participating in the Test plan definition, Content generation, Execution and Debug of critical Power and Perfromance issues. Drive debug and resolution of Zen CPU Power and Performance validation issues across silicon, firmware/BIOS, and coordinating with memory partners as needed Develop x86 content to exercise new features and reproduce complex bugs in silicon Devise validation strategy from pre-silicon through customer adoption working across architecture, silicon design, firmware, validation, and debug teams Proactively participating in project planning, developing, and maintaining schedules, managing dependencies, and ensuring quality of deliverables at committed milestones. Generates/Maintains regular status representing the Cores Validation team in program meetings providing status to program management Experienced in applying AI/ML techniques to drive data‑driven insights and optimize system performance and improve team efficiency and throughout for execution and debug. PREFERRED EXPERIENCE: Programming/scripting skills (e.g. C/C++, Perl, Ruby, Python) x86 assembly programming Debug techniques and methodologies Extensive experience with board/platform-level debugging, including delivery, sequencing, analysis, and optimization Extensive knowledge of system architecture, technical debug, and validation strategy Strong analytical/problem-solving skills and pronounced attention to details Must be a self-starter, and able to independently drive tasks to completion   ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "LEAD PLATFORM EMULATION ENGINEER", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-05T06:59:00+00:00", "url": "https://global-external-amd.icims.com/jobs/75117/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. LEAD PLATFORM EMULATION ENGINEER: THE ROLE: The focus of this role is to plan, build, execute the verification, validation/emulation and debug of new and existing features for AMD’s SOCs, resulting in no bugs in the final SOC design and the firmware/BIOS. This senior role will stretch you as you lead emulation team in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design teams, marketing, and business unit executives. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification/debugging in general. You are a team player who has experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Drive Emulation Methodologies, SOC Design Model and Test Architecture for full chip SOC and hybrid models Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed Pre-Silicon Emulation tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test or infra issues Responsible for writing directed tests to verify features in a co-simulated and emulated/FPGA hardware environment Responsible for writing monitors and checkers to support end-to-end firmware/hardware validation Responsible for running emulator workloads to test new features and debug technical issues using logs, waveform dumps and RTL debug PREFERRED EXPERIENCE: Experience with BIOS/OS bring up on full X86 SOC emulation platform Proficient in IP level ASIC verification, experience working with CPU, GPU, and Memory subsystem Proficient in debugging firmware and RTL code using simulation tools  Good understanding of PCIe/USB/Ethernet standards; safety concepts/IPs Must have hands-on experience on Zebu/Palladium/Veloce platform to bring-up SOC SOC design model build experience Experienced with Verilog, System Verilog, C, and C++   Experience in writing and debugging testbenches Scripting language experience: Perl, Ruby, Makefile, shell preferred Experience on debugging SOC IO interfaces with Transactor solutions in Emulation platform Think differently and out of the box to stress the DUT in Emulation platform and verify it in efficient way Should be open to learning verification methodologies and working closely with design, verification, validation, architecture and firmware teams Excellent communication, management, and presentation skills Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies ACADEMIC CREDENTIALS: Bachelor’s or Master’s degree in Computer/Electronics/Electrical Engineering with 18+ years of experience #LI-RG2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Staff Engineer", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-10-05T06:45:35+00:00", "url": "https://jobs.infineon.com/careers/job/563808972100101", "is_hardware": true, "platform": "eightfold", "jd_text": "We are seeking a highly experienced Technical Leader to drive the development and optimization of next-generation WLAN MAC solutions. The ideal candidate will possess deep expertise in wireless communication systems, embedded software development, IEEE 802.11 standards, and low-level programming in Assembly and C. This role requires strong technical leadership to guide architecture, debugging, validation, and performance optimization activities while collaborating closely with global cross-functional teams across firmware, hardware, and system domains. The successful candidate will combine hands-on technical excellence with mentoring, problem-solving, and stakeholder management skills to deliver innovative, high-performance wireless connectivity solutions.\n\nYour role\nKey responsibilities in your new role\n\nDesign, develop, maintain, and optimize WLAN L-MAC microcode using custom assembly language for IEEE 802.11 standards.\nDrive system-level power optimization initiatives to ensure compliance with WLAN protocol and performance specifications.\nPerform pre-silicon verification of MAC-layer designs using scripting languages such as TCL and Python, validating functionality in simulation environments.\nCollaborate with cross-functional teams including PHY Systems, Firmware, and Hardware Design teams to define, document, and verify interfaces with the L-MAC layer.\nSupport silicon bring-up, validation, and performance tuning to achieve key MAC performance indicators, including packet processing latency and power-saving targets.\nDebug and resolve complex customer and product issues across multiple layers, including WLAN MAC, PHY, and Chip-level subsystems, ensuring effective root-cause analysis and resolution.\nIdentify design, process, and workflow gaps, and drive improvements in architecture, methodologies, and engineering practices while ensuring adherence to established design flows.\nPropose and implement design enhancements to improve performance, quality, scalability, and product reliability.\nMentor, coach, and train team members, fostering technical excellence and knowledge sharing across the organization.\nCreate and maintain technical documentation, design collateral, training materials, and internal/external technical content as required.\nWork closely with stakeholders and global engineering teams to ensure successful project execution and product delivery.\nContribute to continuous improvements in MAC architecture, system performance, verification methodologies, and overall product development lifecycle.\n\nYour profile\nQualifications and skills to help you succeed \n\n10+ years of industry experience with a Master’s degree, or 12+ years with a Bachelor’s degree in Electronics, Computer Science, Electrical Engineering, or a related discipline.\nStrong expertise in Wireless Communication Systems, Embedded Systems, and low-level software/firmware development.\nProven hands-on experience in Assembly Language and C programming for real-time and performance-critical wireless applications.\nDeep understanding of IEEE 802.11 (Wi-Fi) standards, protocols, MAC architecture, and feature implementation.\nStrong experience in Wi-Fi protocol analysis, debugging, and performance optimization using tools such as Wireshark and other industry-standard diagnostic tools.\nDemonstrated expertise in silicon bring-up, system validation, and root-cause analysis within complex embedded wireless systems.\nAdvanced debugging and troubleshooting skills, including the use of GDB, crash dump analysis, stack trace investigation, and performance profiling tools.\nAbility to analyze and resolve complex issues across multiple layers spanning MAC, PHY, firmware, and SoC/chip subsystems.\nProficiency in scripting and automation using Python and Tcl; exposure to SystemC is a strong advantage.\nStrong understanding of software development methodologies, verification flows, and engineering best practices.\nProven ability to lead technical initiatives, drive innovation, and influence architecture and design decisions.\nExperience working effectively within global, cross-functional, and matrixed engineering organizations.\nExcellent communication, presentation, stakeholder management, and interpersonal skills.\nStrong mentoring and leadership capabilities with a passion for developing engineering talent and fostering technical excellence.\nSelf-driven problem solver with exceptional analytical skills and the ability to thrive in a fast-paced, innovation-focused environment.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nAnand Rawal", "jd_status": "stored"}, {"title": "Lead Principal Engineer", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-10-05T06:16:59+00:00", "url": "https://jobs.infineon.com/careers/job/563808972100107", "is_hardware": true, "platform": "eightfold", "jd_text": "We are seeking for a Lead Principal Engineer - WLAN Systems to drive the architecture, design, validation, and successful commercialization of advanced WLAN PHY solutions. In this leadership role, you will work closely with cross-functional teams across RF, MAC, Firmware, and Hardware domains to deliver innovative wireless technologies through both pre-silicon and post-silicon development phases. The ideal candidate will possess deep expertise in wireless communications, signal processing, PHY-layer design, RF systems, and silicon bring-up, along with a proven track record of technical leadership, problem-solving, and mentoring teams to bring cutting-edge wireless products from concept to market.\n\nYour role\nKey responsibilities in your new role :\n\nServe as a technical expert within the WLAN Systems team, leading the design, development, and commercialization of advanced WLAN PHY solutions.\nDrive system architecture, design enhancements, and implementation of key PHY design blocks across multiple projects.\nProvide technical recommendations and proposals to support strategic technology and product decisions.\nLead cross-functional teams in translating system requirements into robust PHY implementations and RTL deliverables.\nIdentify post-silicon bring-up issues and drive PHY-layer design improvements based on silicon learnings.\nCollaborate with RF and Analog teams to define RF specifications and develop accurate system-level simulation models.\nWork closely with MAC, Firmware, Hardware, and RF teams to define, document, and validate PHY interfaces.\nDrive continuous improvements in workflows, methodologies, and design processes to enhance productivity and quality.\nSupport silicon bring-up, validation, and characterization activities to verify design updates and enhancements.\nAnalyze and resolve complex cross-layer issues involving WLAN PHY, MAC, RF, Firmware, and board-level systems.\nIdentify design and process gaps, propose corrective actions, and ensure adherence to established design methodologies.\nMentor and train team members, fostering technical growth and knowledge sharing within the organization.\nCreate technical documentation, design collateral, training material, and customer-facing content as required.\nPartner with stakeholders across global teams to ensure successful project execution and product delivery.\n\nYour profile\nQualifications and skills to help you succeed \n\nProven experience leading wireless systems or design teams and successfully delivering products from concept to commercial deployment.\nStrong foundation in Communication Theory, Signal Processing, and Wireless Communication Systems, with the ability to analyze and resolve complex system-level challenges.\nDeep understanding of PHY-layer design and algorithms, including carrier detection, timing and frequency synchronization, AGC, filters, demodulators, tracking loops, decoders, and their implementation in wireless and wireline modem systems.\nIn-depth knowledge of RF architectures, RF impairments, and their impact on overall system performance.\nHands-on experience in post-silicon chip bring-up, validation, and debugging, with proficiency in using lab equipment such as spectrum analyzers, signal generators, and lab automation tools.\nExpert-level proficiency in MATLAB and C programming, including fixed-point model development and validation.\nStrong debugging and troubleshooting skills using C, GDB, crash analysis, and stack trace debugging techniques.\nGood understanding of wireless communication standards, including IEEE 802.11, IEEE 802.15, and 3GPP specifications.\nWorking knowledge of C++, Python, Tcl, SystemC, and High-Level Synthesis (HLS) tools is an added advantage.\nAbility to collaborate effectively within large, global, and cross-functional engineering teams.\nExcellent communication, presentation, analytical, and problem-solving skills.\nDemonstrated ability to mentor engineers and drive technical excellence across projects.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nAnand Rawal", "jd_status": "stored"}, {"title": "Sr. Silicon Design Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-05T05:36:00+00:00", "url": "https://global-external-amd.icims.com/jobs/91050/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. SENIOR SILICON DESIGN ENGINEER   THE ROLE: We are looking for a talented individual to join our team in an RTL design role. Our intellectual property (IP) design team creates IP cores for use in high performance AMD products. Our designers work on industry-leading technologies for communications. Your expertise will be deployed in ASIC projects targeting networking, security, storage, and other applications.     THE PERSON:  You are very proficient in Verilog RTL coding, and front-end design flows. You have experience with data networking and communications protocols, ASIC architecture and RTL design, and EDA design processes. You have demonstrated your technical skill through prior experience delivering ASIC and/or FPGA solutions to the market, and leverage this experience to design and code innovative, high quality IP products. You are a team player who has excellent written and verbal communication skills with experience collaborating across multiple design sites and time zones. You have strong analytical and problem-solving skills and enjoy tackling new challenges. You are a self-starter with a desire to learn and an ability to solve complex, novel, and non-recurring problems. You pay attention to details. You enjoy working amongst a multi-disciplinary team of professionals with diverse skills and experiences to complete projects in an efficient manner.   KEY RESPONSIBILITIES:  Develop synthesizable RTL for IP cores targeting advanced technology nodes Utilize modern AI tools to achieve a high level of RTL design productivity through code generation, refactoring, documentation, and debug Collaborate directly with IP Architecture, IP Verification, and SoC integration teams Contribute to design specifications for IP cores Resolve IP simulation regression failures through close collaboration with IP Verification Team and work with Verification Team members to ensure achievement of verification quality metrics Work with SoC team and Physical Design (PD) team to meet Power/Performance/Area goals by providing synthesis and timing closure support Support the activities of the Emulation Team Coach and mentor less experienced designers Attend and contribute to regular technical status meetings   PREFERRED EXPERIENCE:  6+ Years experience in RTL (Verilog / System Verilog) ASIC design experience through implementations targeting leading edge ASIC technologies Proven experience with industry-leading ASIC design tools, synthesis tools, flows, and timing closure Experience driving AI-powered tools (VS Code, GitHub Copilot, Cursor) that integrate LLMs (Claude, Codex/GPT) for RTL design Experience executing design checks such as lint, CDC, and LEC using industry standard ASIC tools Skilled in simulation and debugging with functional verification tools from Synopsys, Cadence, and/or Siemens (Mentor) including Gate-level simulations Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA) Experience in modern, complex networking architecture and digital design in general Experience with networking protocols (such as Ethernet) and standards for digital communication systems, optical communications, and packet processing applications Familiarity with encryption protocols (such as MACsec and IPsec) and security technologies for digital communication systems Proficient with workplace AI tools (Microsoft M365 Copilot, ChatGPT, Atlassian Rovo) Proficient with scripting languages such as Python, Perl, TCL, Makefile, and csh/bash     ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-DB2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "SOC Design Verification Staff Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-05T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721372043", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.\n•    6+ years of ASIC design, verification, validation, integration, or related work experience.\n•    2+ years of experience with architecture and design tools.\n•    2+ years of experience with scripting tools and programming languages.\n•    2+ years of experience with design verification methods.\n•    1+ year of work experience in a role requiring interaction with senior leadership (e.g., Director level and above).\n\nPrincipal Duties & Responsibilities:\n•    Leverages advanced ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.\n•    Creates advanced architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.\n•    Collaborates across functional teams (e.g., software architecture, hardware architecture, product management, program management teams) to develop and execute an implementation strategy that meets system requirements and customer needs.\n•    Evaluates all aspects of complex process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.\n•    Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable advanced architecture and design of multiple complex blocks/SoC or IC Packages.\n•    Writes and reviews detailed technical documentation for complex EDA/IP/ASIC projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making is significant in nature and affects work beyond immediate work group.\n•    Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. \n•    Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions).\n•    Tasks do not have defined steps; planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Engineer, ASIC Gen AI", "company": "Micron", "location": "Hyderabad, Telangana, India", "date_posted": "2026-10-05T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/44740680", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nKey Responsibilities \nGenAI System Development: Design, build, and improve GenAI-powered and agentic systems supporting ASIC semiconductor engineering workflows such as code generation, data extraction, analytics, documentation automation, failure triage, root cause analysis, and technical knowledge retrieval.  \nLLM Workflow Engineering: Build, evaluate, and optimize LLM-based workflows, including prompting, developing skills, retrieval-augmented generation (RAG and Graph-RAG), benchmarking, and quality evaluation.  \nMachine Learning Production: Develop and implement machine learning and deep learning models for classification, regression, anomaly detection, failure analysis, and engineering decision support.  \nCross-Functional Collaboration: Partner with domain experts and cross-functional teams to translate complex engineering problems into scalable AI/ML and analytics solutions.  \nProduction Deployment: Support deployment, monitoring, and operationalization of AI/ML solutions in cloud and enterprise environments.  \nTechnical Communication: Communicate technical findings, recommendations, and model outcomes clearly to both technical and non-technical stakeholders.  \nInnovation Leadership: Identify and drive high-impact opportunities where GenAI, machine learning, and analytics can improve engineering productivity and business outcomes! \n\nMinimum Qualifications \nBachelor's with 10+ years or Master’s degree with 8+ in Electrical Engineering, Computer Science, Data Science, Statistics, Artificial Intelligence, or a related field\nMinimum 4 years of hands-on experience developing and deploying AI applications in semiconductors, electronics, or other engineering industries. \nStrong programming proficiency in Python.  \nFamiliarity with modern AI coding tools / agentic coding harnesses, such as Claude Code, Cursor,  Gemini CLI, or similar tools.  \nPractical experience in developing and implementing AI/ML systems involving LLMs, including RAG, agentic workflows, and frameworks.  \n\nPreferred Qualifications \nExperience building agentic systems or AI solutions for ASIC semiconductor pre-silicon and post-silicon workflows. \nDeep understanding of semiconductor-specific AI/ML applications \nCloud experience with GCP, AWS, or Azure, including deploying ML pipelines in production. \nExperience with LLM training, inference, and evaluation workflows, including prompt design, benchmarking, validation, or retrieval-augmented systems.  \nExperience with data analytics and visualization to deliver actionable engineering insights using tools and libraries such as pandas, scikit-learn, matplotlib, plotly, or similar ecosystems. \nExperience with web application technologies such as JavaScript, HTML, and CSS.  \nExperience designing scalable, enterprise-grade AI/ML systems with attention to reliability, traceability, and operational readiness. \nFamiliarity with document-processing pipelines, technical knowledge platforms, or retrieval systems for engineering content.\nExperience working in multi-functional environments spanning systems architecture, engineering, data science, and IT.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Staff ENGINEER, HIG HBM-ARCHITECTURE", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-10-05T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/44786422", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nOur vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\nWe are part of Micron’s HBM design organization, building the test architectures that enable the most advanced memory products in the world. Our team works at the intersection of design, manufacturing, and silicon learning to make 3D‑stacked memory reliable at scale. We thrive on deep technical challenges and close collaboration across disciplines!\nAs an HBM Design Architect, you will define how next‑generation HBM products are tested from wafer to system. This role is critical to ensuring quality, yield, and performance across complex multi‑die architectures. You’ll influence product success early, work hands-on with silicon, and partner closely with design, test, and manufacturing teams.\nResponsibilities:\nDefine and implement end-to-end DFT architectures for HBM base die and DRAM die\nDevelop DFT strategies for stacked-die, cube-level, and system-level test flows\nArchitect test access mechanisms supporting wafer probe through final test\nEnable silicon observability for yield learning, debug, and failure analysis\nCollaborate across design, verification, layout, test, and manufacturing teams\nLeveraging AI for design quality improvement and DFT\nMinimum Qualifications:\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field\nStrong knowledge of scan, MBIST, JTAG, and boundary scan concepts\nExperience with wafer probe and final test semiconductor flows\n5+ years of experience in DRAM or ASIC DFT design or verification\nPreferred Qualifications:\nExperience with HBM, DRAM, or advanced memory products\nKnowledge of TSV-based 3D integration and stacked-die test challenges\nHands-on experience with at-speed test or advanced DFT techniques\nExposure to DFT security features or custom customer test interfaces\nPrior experience using AI to improve DFT coverage is higher desiired\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Memory Electrical Validation Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-05", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Memory-Electrical-Validation-Engineer_JR0287713", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact:\n\nAs a Memory Electrical Validation Engineer, you will play a pivotal role in optimizing and validating electrical performance for memory IO interfaces. You'll focus on ensuring compliance with industry standards, analyzing margins for stable operation, debugging electrical issues, and driving system-level improvements. Your expertise will directly contribute to delivering high-quality, reliable products that meet production goals while advancing Intel's innovative memory solutions.\n\nBusiness group\nThe Silicon and Platform Engineering (SPE) Group leads Intel's efforts in designing, developing, and validating advanced silicon and platform technologies. This team is committed to delivering cutting-edge solutions that drive Intel's leadership in the semiconductor industry. By joining SPE, you'll be part of a collaborative environment that tackles challenging problems and powers Intel's success in creating transformative technologies for the future.\n\nKey Responsibilities\n- Define electrical validation strategies for memory IO interfaces to ensure optimized electrical performance and alignment with production goals.\n- Validate circuit analog performance, signal integrity compliance, and system-level margins against industry standards.\n- Analyze, debug, and optimize Memory Reference Code (MRC) requirements to improve margins and overall product quality.\n- Collaborate on multidisciplinary research for testing, validation, and optimization of memory IO and mixed-signal architectures.\n- Develop procedures and designs for validation processes, systems margin evaluation, and test infrastructure.\n- Debug functional and triage failures to identify root causes and resolve electrical issues.\n- Test electrical interactions between design features using advanced validation infrastructure.\n- Prepare validation specifications, evaluate intellectual property (IP), and generate detailed test reports.\n- Partner with architecture, design, and presilicon verification teams to ensure effective Design for Testability (DFT) and Design for Manufacturability (DFM) capabilities for IO architectures.\n\nQualifications:\nMinimum Qualifications:\n\n- Master's degree in Electrical Engineering, Computer Engineering, or a related field.\n- 3+ years of hands-on industry experience in electrical validation or debugging\n- Proficiency in validating signal integrity and electrical performance of memory IO interfaces.\n- Experience with debugging electrical and system-level issues.\n- Demonstrated ability to analyze, design, and optimize validation procedures and test infrastructure.\n- Familiarity with compliance testing against industry-standard specifications.\n\nPreferred Qualifications:\n\n- Familiarity with memory validation tools, techniques, and methodologies.\n- Strong collaborative skills, particularly in multidisciplinary research and cross-functional teamwork.\n- Proven ability to develop and refine validation strategies for complex architectures.\n- Passion for delivering innovative solutions and driving continuous improvement.\n\nWe're looking for someone eager to make a meaningful impact while solving complex challenges in memory validation. If you're ready to join a team that values collaboration, innovation, and excellence, we encourage you to apply today.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Electrical Engineer II Senior", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2026-10-05", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/Electrical-Engineer-II-Senior_R2626842-1", "is_hardware": true, "platform": "workday", "jd_text": "Who We Are\n\nApplied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI and accelerating the commercialization of next-generation semiconductor chips. Join us and push the boundaries of materials science and engineering in a company at the foundation of the electronics industry. The work we do together advances the world’s technology. \n\nWhat We Offer\n\nLocation:\nBangalore,IND\nYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. \n\nAt Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. \n\nRole Responsibilities: \nDesign or modify electrical or electronic engineering assemblies, layouts, schematics, drawings or specifications of moderate scope under general supervision \n\nPerform basic engineering analysis under general supervision \n\nPerform and generate basic engineering test reports; generate related alpha/gamma documentation for product releases \n\nCoordinate the procurement and assembly of electrical or electronic components and equipment, and identify sources of critical parts and subsystems to resolve technical issues \n\nTroubleshoot a variety of moderately complex electrical problems \n\nImplement concepts for product issues and electrical solutions of moderate difficulty \n\nAssist in the development of electrical product specifications \n\nClearly communicate complex information in straightforward situations\n\nMinimum Qualifications:\nBachelor’s degree\n\n5 - 8 years of related experience\n\nPreferred Qualifications:\nA solid understanding of the industry’s key business drivers  \n\nGood communication/interpersonal skills to explain complex information to others  \n\nResponsibilities\n·Designing of electrical control panels, interfacing & knowledge in various Power sources\n·Cable & Harness designing for AC modules / capital equipment / Sensors / Temp Controllers etc.\n·Design electrical / electronic engineering assemblies, layouts / schematics and detailed drawings\n·Preparing engineering specification documents, Test specs., interface with other BU engineering depts., software teams and manufacturing teams.\n·Documentation for product release.\n·Reliability Testing\n·To work closely with North America group and suppliers / contract manufacturers\n·Coordinate the procurement and assembly of electrical/electronic components/equipment.\n·Identify sources of problems in critical parts and subsystems to resolve technical issues. Troubleshoot a variety of complex issues, electrical problems.\n·Perform engineering analysis on Field issues, Module Failures, Interact with Filed Engineers for bug resolution\nJob Specific Knowledge\n·Hands on experience in Electronic, Electrical Hardware designs, capital equipment control panel designing.\n·Knowledge in Analog & Digital circuit design.\n·Knowledge in Semi, IEC, ANSI, NEC protocols / Standards\n·Knowledge of component Obsol. & selection, schematic generation, layout reviews\n·Interconnect, Schematic design, cable and harness design\n·Knowledge in UL / CE, Semi Safety requirements\n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nAssignee / Regular\nTravel:\nYes, 10% of the Time\nRelocation Eligible:\nYes\n\nApplied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "Electrical Engineer", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2026-10-05", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/Electrical-Engineer_R2628188", "is_hardware": true, "platform": "workday", "jd_text": "Who We Are\n\nApplied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI and accelerating the commercialization of next-generation semiconductor chips. Join us and push the boundaries of materials science and engineering in a company at the foundation of the electronics industry. The work we do together advances the world’s technology.\n\nWhat We Offer\n\nLocation:\nBangalore,IND\nYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. \n\nAt Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. \n \n \nAs an Electrical Engineer, you are responsible for designing, modifying, and troubleshooting electrical or electronic engineering assemblies, layouts, schematics, and drawings to advance the equipment that supports our technology. Using your technical experience and critical thinking skills, you will perform engineering analysis, generate test reports, develop innovative solutions, and create documentation for product releases. You will also coordinate the procurement and assembly of components, identify sources of critical parts, and resolve technical issues to ensure peak performance. \n \nRole Responsibilities: \nDesign or modify electrical or electronic engineering assemblies, layouts, schematics, drawings, or specifications of difficult scope \n\nIdentify and troubleshoot a variety of complex electrical problems with limited supervision \n\nDefine, coordinate, perform and generate engineering test reports with limited supervision \n\nPerform engineering analysis of difficult scope with limited supervision \n\nTechnically lead or execute engineering projects, including the development of key suppliers \n\nImplement concepts for a variety of complex product issues and electrical solutions of difficult scope \n\nGenerate electrical product specifications; specify and review engineering documentation \n\nServe as a resource for junior colleagues; lead project teams, as needed\n\nClearly communicate difficult or sensitive information; build consensus \n\nMinimum Qualifications: \nBachelor’s degree\n\n4-7 years of experience in a related field\n\nPreferred Qualifications: \nStrong knowledge of industry best practices, key business drivers, competition in the marketplace, and how your area of expertise integrates with others  \n\nDemonstrated leadership skills to lead small projects as needed  \n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nAssignee / Regular\nTravel:\n\nRelocation Eligible:\nNo\n\nApplied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "Staff SoC Verification Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-10-05", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Staff-SoC-Verification-Engineer_R-10064254", "is_hardware": true, "platform": "workday", "jd_text": "NXP is seeking highly qualified candidates to join SOC Verification team as Staff Engineer SoC Verification.\nIn this role, you will be responsible for functional Verification of NXP SOCs and Sub-Systems using state of the art technology and methodologies, should be able to work independently and drive to closure of assigned tasks. You will be engaged with the design, Architecture, IP providers, FW/SW, DFT and backend teams to collaborate and execute to ensure First time right silicon.\nExpectations include:\nUnderstand the product requirements and Develop Verification plans to meet the Specification.\nDevelopment of Pre-Silicon Verification environment.\nRigorously executing Verification Plans to ensure Right First Time Success of our Products.\nDevelopment of Subsystem/SoC Verification and Coverage plans.\nDemonstrate excellent Self–motivation, communication, strong problem solving and teamwork skills.\nFlexible enough to work in a dynamic environment and multitask seamlessly.\nAbility to work well as part of a team both locally, and with remote or multi-site teams\n \nKey Skills\n7+ years of experience on SOC/Chip level/Cluster/Sub-System Verification\nExperience in Microcontroller and Microprocessor architecture, ARM Cores A/M/R series, Interconnect (NIC, FlexNoC), Cache Coherency.\nExperience in protocols like AHB/AMBA, AXI, ACE, OCP, Memory (Flash, SRAM, LPDDR/DDR3/4, SD, eMMC) and memory controllers\nExperience in automotive protocols like LIN, CAN, Multimedia/Networking protocols like PCIe gen3, MIPI CSI2, GPU, Automotive Ethernet (TSN), USB, DSP, Image/RADAR processing would be an advantage\nExperience with System Verilog/UVM for IP/Subsystem and SOC development environment.\nVerification using formal methods will be an added advantage.\nAssembly and C programming skills\nScripting and Automation (Perl, TCL, Python) to continuously improve operational efficiency\n \nJob Qualifications\nBSEE / MSEE with 7+ years’ experience in Semiconductor industry. \n\nMore information about NXP in India...\n\n#LI-29f4", "jd_status": "stored"}, {"title": "PRINCIPAL  PHYSICAL VERIFICATION ENGINEER", "company": "NXP", "location": "Bangalore", "date_posted": "2026-10-05", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/PRINCIPAL--PHYSICAL-VERIFICATION-ENGINEER_R-10064795", "is_hardware": true, "platform": "workday", "jd_text": "We are seeking a talented Physical Verification Design Engineer to join our VLSI design team. This role involves ownership of full-chip and block-level physical verification (PV) signoff, ensuring designs meet foundry and reliability requirements. The candidate will collaborate closely with physical design, PDK, CAD, and tapeout teams to deliver high-quality silicon.\nKey Responsibilities\nPerform physical verification (PV) for block-level and full-chip designs, including:Design Rule Check (DRC)\nLayout Versus Schematic (LVS)\nElectrical Rule Check (ERC)\nAntenna, density, and reliability checks\n\nDrive signoff closure by identifying and resolving PV violations efficiently.\nWork with physical design and layout teams to debug and fix violations.\nDevelop and maintain runsets, decks, and automation flows using industry-standard tools.\nAnalyze foundry decks and PDK updates, ensuring compliance with process requirements.\nLead tapeout readiness reviews and ensure high-quality database delivery.\nPerform hierarchical verification and regression management.\nParticipate in improving verification methodologies, runtime, and capacity optimization.\nInterface with foundry and EDA vendors to resolve tool or deck-related issues.\nMentor junior engineers and review their work as needed.\n\nPreferred / Added Advantage Skills\nExposure to Physical Design (PD) concepts, including:Floorplanning (macro placement, block shaping, congestion awareness)\nPower Delivery Network (PDN) design (power grid, IR drop considerations)\n\nUnderstanding of:Placement, CTS, routing flows\nPD-PV interaction and impact of layout decisions on DRC/LVS closure\n\nKnowledge of:EM/IR, latch-up, ESD reliability checks\nMulti-patterning / EUV constraints\n\nExperience with full-chip integration and SoC-level challenges\nAbility to correlate PV issues with PD root causes (e.g., spacing, density, routing hotspots)\nExposure to flow automation and methodology development\nSoft Skills\nStrong analytical and problem-solving ability\nEffective communication across cross-functional teams\nOwnership mindset with focus on quality and timelines\nAbility to work independently and guide team members\n\nMore information about NXP in India...\n\n#LI-29f4", "jd_status": "stored"}, {"title": "Safety Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-10-05", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Safety-Engineer_R-10066846", "is_hardware": true, "platform": "workday", "jd_text": "Company Description\n\nNXP Semiconductors N.V. enables secure connections for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets.\n\nBusiness Unit Description\n\nNXP’s Functional Safety Competence Center empowers all business units to deliver functionally safe and standard compliant solutions, addressing current and emerging challenges in the automotive and industrial safety markets.\n\nJob Summary\n\nThis Safety Engineer position is part of the Functional Safety Competence Center and contributes to the development of safety-compliant semiconductor products. Key responsibilities are defining, analyzing, and validating safety concepts and architectures, including developing safety requirements and performing Safety Analyses. The Safety Engineer collaborates with implementation teams, systems, hardware, and software teams to deliver robust, certifiable solutions and to ensuring a Functional Safety compliant development process.\nCandidates with strong experience in Microcontroller and Microprocessor architecture and Safety product development are preferred. Exceptions may be made for candidates having no prior safety experience but have strong background in chip design architecture and are motivated to learn Functional Safety.\n\nRequired:\nBachelor’s degree in Electronics/Electrical/Computer Engineering or equivalent.\n5–8 years of experience in semiconductor product development with exposure to functional safety.\nStrong understanding of microcontroller and microprocessor architectures and their application in automotive or industrial safety domains.\nStrong understanding of IP and SoC level Safety mechanisms.\nUnderstanding safety standards (ISO 26262 or IEC 61508) and associated development lifecycles and work products.\nExperience with safety analysis techniques such as FTA, DFA, and FMEDA.\nAbility to collaborate effectively in cross-functional and global teams.\n\nPreferred:\nExperience in functional safety design and development within Tier 1 or Tier 2 automotive suppliers.\nBroad exposure to semiconductor product development (e.g., IP design, verification, DFT, physical implementation, tools, and methodologies).\nHands-on experience with safety analysis and modeling tools (e.g., Medini).\nExperience in safety audits, assessments, and certification activities.\n Familiarity with requirements management tools such as ELM7.\n\nResponsibilities:\nDefine and develop functional and technical safety concepts based on product architecture, technology, and intended functionality.\nContribute to the capture and management of requirements using appropriate requirements management tools.\nCollaborate with cross-functional teams to ensure consistent and effective implementation of safety concepts.\nPerform safety analyses at IP and product levels, including FTA, DFA, and FMEDA.\nSupport the definition and review of safety verification and validation strategies.\nContribute to safety audits, assessments, and internal reviews.\nSupport customers in the integration and application of NXP safety products, including tailored solutions where required.\n\n#LI-DNI", "jd_status": "stored"}, {"title": "CAD Engineer (Digital)", "company": "Analog Devices", "location": "India, Bangalore, Nova", "date_posted": "2026-10-05", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-Nova/Senior-Engineer--Digital-Design-Engineer_R264659", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nPosition           : CAD Engineer (Digital)\nExperience      : 5+ years\nEducation        : Bachelors/Masters engineering degree in Computer Science/Electrical/Micro-Electronics\nLocation          : Bangalore (ADBL)\nJob Grade       : P3                  \nResponsibilities\nDevelop and drive Design-for-Test methodologies emphasizing on best-in-class Methodologies for corporate wide digital flows using EDA tools from leading vendors like Siemens and Cadence\nWork with global CAD methodology development team to automate and integrate the above CAD flows for centralized deployment\nProvide strong technical expertise and consultations on Design-for-Test and front-end design EDA flows to ADI’s Business Units and ensure successful tapeouts of their products\n\nDesired Skills:\nExpertise in developing CAD Solutions in the areas of dft and synthesis using Siemens, Cadence or Synopsys EDA tool suite\nExperience in overall digital implementation flows (RTL to GDS II) and has a well-proven track record of being involved in successful multi-million gate SOC design tapeouts in nanometer technology.\nExperience in working on advanced nanometer and finfet process technologies.\nSound Knowledge in Cadence EDA synthesis and formal equivalence checking (Genus, Conformal)\nStrong experience in automation of methodologies/solution using TCL, Python, PERL and Tk.\nDebugging experience to debug vendor tool problems and interacting with designers to help tackle their problems\nPossess excellent interpersonal and communication skills to collaborate and influence design development groups across the globe\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "ASIC Verification Engineer - Clocks", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-05", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/ASIC-Verification-Engineer---Clocks_JR2026417", "is_hardware": true, "platform": "workday", "jd_text": "The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification. The NVIDIA Clocks Team is committed to deliver high-quality clocking and reset logic to various units in SOC automotive and datacenter ASICs. The complexity of the clocks and resets design has increased many folds. This requires sophisticated verification to deliver a bug free clocks design to power our product lines ranging from Data Centers, Consumer graphics to Self-driving cars and the growing field of artificial intelligence. Modern clocking verification solutions need to be innovative, ensure quality in covering the complex design specifications and balance the constraints on infrastructure, re-usability, testing speed and multi-platform support.\n\nWhat you'll be doing:\nOwn validation of Clocking structures in Tegra automotive and datacenter products from start to finish, including test plan development, automation, validation flows development, coverage metrics, test execution, bug identification/fix and productization.\n\nTackle Sophisticated problems and develop a scalable solution that works across platform.\n\nHands on industry-standard tools and state of the art verification methodologies. This includes coding in System Verilog, UVM, C++, Perl, Python and NVIDIA custom compilers and tools.\n\nPartnering closely with our clocks architecture and design team to validate our clocks design.  \n\nCoordinate with internal and external teams across time zones.\n\nWhat we need to see:\nBS or MS in EE/ECE or equivalent experience.\n\n3+ years of relevant industry work experience.\n\nGood understanding of Logic Design and Architecture.\n\nExpertise in industry-standard verification flows like SV constraint random verification, UVM, Formal Verification, Coverage metrics, profiling tools, X prop, etc.\n\nExposure on block level and system-level verification.\n\nStrong coding skills in System Verilog, scripting languages (Perl/python) and C++.\n\nAbility to collaborate and work with multiple groups.\n\nPrior experience in implementing Test plans for pre-silicon platforms.\n\nUnderstanding of DFT/IST is optional.\n\nWe have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our world-class engineering teams are growing fast. If you are creative, curious, and motivated with real passion for technology, we want to hear from you!\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "ASIC Digital Design , Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-05", "url": "https://careers.synopsys.com/job/bengaluru/asic-digital-design-staff-engineer/44408/101558471904", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have built verification environments that catch bugs before they become customer issues. Whether you have been doing this for three years or closer to ten, you have learned that verification is not about running tests; it is about thinking through what could go wrong and building the infrastructure to prove it won't. You understand that a well-written testbench is half the battle, and the remaining is knowing which corner cases matter, and which ones are just noise.\n\n You are comfortable working in System Verilog and UVM, writing test cases that exercise real scenarios, not just the ones in the specification. You have debugged enough simulations to recognize patterns in waveforms, and you know when to dig deeper versus when to loop in the design team. Protocols like MIPI UFS/UniPro, DDR, PCIe, Ethernet or USB are not just acronyms to you; you have worked with at least one of them closely enough to understand how transactions flow and where things typically break.\n\n Working on a verification team means asking questions when the test plan does not make sense, writing assertions that catch issues, and tracking coverage in a way that tells you what you have validated and what you have not. At Synopsys, you will work on IP cores that go into AI systems, automotive platforms, and data centers. The verification work you do will determine whether that IP works when it ships.\nWhat You'll Be Doing\nBuild and maintain UVM-based verification environments for DesignWare IP cores across USB, PCI Express, Ethernet, and AMBA protocols\nDevelop test plans by analyzing specifications, identifying coverage holes, and defining verification strategies at both unit and system levels\nWrite SystemVerilog testbenches, constrained-random tests, directed tests, and functional coverage models that drive quality metrics to closure\nDebug RTL and testbench issues using VCS, NC, or MTI simulators, trace waveforms, and work with design engineers to resolve root causes\nManage regressions, analyze coverage reports, close functional and code coverage gaps, and drive IP to signoff quality\nCollaborate with a global verification team, participate in reviews, and contribute to methodology improvements across the DesignWare IP portfolio\nIntegrate and work with Verification IP (VIP) for industry-standard protocols to accelerate environment bring-up and test development\nThe Impact You Will Have\nEnsure DesignWare IP cores meet the quality and reliability standards that customers depend on for their SoC designs\nCatch critical bugs before tapeout, reducing costly respins and protecting Synopsys reputation for silicon-proven IP\nDrive coverage closure and verification signoff for IP that ships in high-volume applications across automotive, mobile, data center, and AI markets\nContribute verification methodology improvements that make the entire DesignWare team more efficient and effective\nEnable faster time-to-market for customers by delivering thoroughly verified, reusable IP blocks\nInfluence design quality through early feedback, test plan reviews, and cross-functional collaboration with RTL and architecture teams\nHelp scale verification processes and environments that support one of the industry's broadest IP portfolios\nWhat You'll Need\nBachelor's or Master's in Electrical Engineering or Computer Engineering with 5+ years of hands-on verification experience for IP cores or SoC designs (or Master's with 3+ years)\nStrong SystemVerilog and HVL coding skills with proven ability to build testbenches, write constrained-random tests, and implement functional coverage\nDirect experience with UVM, VMM, or OVM methodologies applied to real verification projects\nHands-on proficiency with industry-standard simulators such as VCS, NC (Xcelium), or MTI (Questa) and their associated debugging tools\nSolid understanding of functional coverage and code coverage concepts, and how to use them to drive verification closure\nExperience with Verilog for reading and understanding RTL is highly desired\nFamiliarity with scripting languages like Perl or Python for automation and regression management is a strong plus\nWho You Are\nYou can read a protocol specification, identify the verification-critical scenarios, and turn that into a test plan without someone walking you through it\nWhen a regression fails, you do not wait for someone else to triage it, you pull the logs, check the waveforms, and narrow down the root cause\nYou communicate clearly with design engineers about bugs, coverage gaps, and quality risks without creating unnecessary friction or noise\nYou are self-driven enough to manage your own verification tasks, track your coverage metrics, and escalate when you are blocked, not after you are stuck\nYou can work across time zones with a global team, contribute to reviews, and share what you learn without needing constant oversight\nYou understand that verification is a team effort, you help others debug, review test plans, and contribute to shared infrastructure when it makes the team better\nThe Team You'll Be Part Of\nYou will join the DesignWare IP Verification R&D team at the Bangalore Design Center, working as part of a global team of verification engineers responsible for ensuring the quality of Synopsys' industry-leading IP portfolio. The team verifies synthesizable cores across multiple high-speed interface and interconnect protocols including USB, PCI Express, Ethernet, and AMBA. You will collaborate closely with RTL design teams and contribute to verification environments and methodologies that support one of the broadest IP portfolios in the semiconductor industry.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Digital Design Verification, Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-05", "url": "https://careers.synopsys.com/job/bengaluru/digital-design-verification-staff-engineer/44408/101580799616", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\n \n Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nYou have spent over a decade in verification, and you have learned that the difference between a verification flow that works and one that collapses under pressure is usually a decision made at the architecture stage. You are the engineer who catches that decision before it becomes technical debt. You think in systems, not scripts. You know that building verification infrastructure is not about assembling tools, it is about creating an environment where teams can move fast without breaking things.\n \n You have built verification environments from scratch using VCS, Verdi, VMS Execution Manager, and UVM, and you know where each tool shines and where it does not.\n \n What You'll Be Doing\n* Implement unified verification flows for Synopsys digital IP products using VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs\n* Build scalable verification infrastructure from the ground up, designing environments that support complex IP and SoC projects across global teams\n* Define, document, and propagate verification methodologies and best practices that become the standard across Synopsys digital IP projects\n* Lead and mentor verification engineers, providing technical guidance on UVM, SystemVerilog, flow optimization, and debugging strategies\n* Drive technical initiatives independently, managing high-impact assignments from concept through deployment and adoption\n* Collaborate with EDA tool development teams to influence product roadmaps, provide feedback, and optimize verification workflows for real-world use cases\n* Troubleshoot and refine verification processes for internal teams and customers, diagnosing flow bottlenecks and delivering solutions that stick\n \nThe Impact You Will Have\n * Establish verification methodology standards that accelerate time-to-market for Synopsys digital IP and SoC products\n* Enable global verification teams to deliver higher quality results faster by providing robust, reusable flows and infrastructure\n * Shape the verification strategy for next-generation Synopsys IP offerings, directly influencing product quality and customer satisfaction\n* Reduce verification cycle time and resource overhead across multiple projects by standardizing tooling and best practices\n* Develop the next generation of verification engineers at Synopsys, building a culture of technical excellence and continuous learning\n* Influence the evolution of Synopsys EDA tools by providing critical, field-tested feedback to product teams\n* Strengthen Synopsys' leadership position in semiconductor verification by driving adoption of cutting-edge methodologies across the organization\n \nWhat You'll Need\n * 4+ years of hands-on experience in IP or SoC verification, with a proven track record of leading technical initiatives and delivering complex verification environments\n* Deep expertise with Synopsys verification tools including VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and Verification IP (VIP)\n * Strong programming and scripting skills in SystemVerilog, UVM, Tcl, and Python for automation and flow development\n* Demonstrated ability to architect verification flows and infrastructure for complex digital designs, from initial concept to production deployment\n* Bachelor's degree in Electronics, Electrical, or Computer Engineering; advanced degrees are a plus\n * Experience managing multiple technical projects independently, balancing priorities and delivering high-quality results on schedule\n * Ability to document and communicate technical methodologies clearly across global, cross-functional teams\n \nWho You Are\n * You can explain a complex verification tradeoff to a product manager in two sentences without losing the nuance, and then turn around and debug a UVM testbench with a junior engineer\n* You take ownership of problems that do not have clear owners, and you see them through to resolution even when it means coordinating across time zones and teams\n* You push back when a methodology does not make sense for the use case, and you do it with data and a better alternative, not just criticism\n* You are organized enough to manage five verification projects at once and strategic enough to know which one needs your attention today\n* You teach by showing, not just telling, and you measure your success by how much your team grows, not just what you deliver personally\n* You stay current with verification trends and tools, and you bring new ideas to the table backed by practical understanding of what will actually work in production\n\n The Team You'll Be Part Of\n You will be a core member of the newly established Digital IP Verification Methodology (COE) team, a group of forward-thinking engineers dedicated to advancing verification excellence at Synopsys. The team collaborates across global sites, driving innovation in methodology, tool integration, and best practices. Together, you will shape the future of digital IP verification, enabling Synopsys and its customers to deliver world-class silicon solutions.\n \nRewards and Benefits\n We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Principal ASIC Digital Design Engineer (Verification)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-05", "url": "https://careers.synopsys.com/job/bengaluru/principal-asic-digital-design-engineer-verification/44408/101580799552", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\n Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n \n You Are\nYou have spent over a decade in verification, and you have learned that the difference between a verification flow that works and one that collapses under pressure is usually a decision made at the architecture stage. You are the engineer who catches that decision before it becomes technical debt. You think in systems, not scripts. You know that building verification infrastructure is not about assembling tools, it is about creating an environment where teams can move fast without breaking things.\n \nYou have built verification environments from scratch using VCS, Verdi, VMS Execution Manager, and UVM, and you know where each tool shines and where it does not.\n \nWhat You'll Be Doing\n  * Architect and implement unified verification flows for Synopsys digital IP products using VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs\n* Build scalable verification infrastructure from the ground up, designing environments that support complex IP and SoC projects across global teams\n* Define, document, and propagate verification methodologies and best practices that become the standard across Synopsys digital IP projects\n * Lead and mentor verification engineers, providing technical guidance on UVM, SystemVerilog, flow optimization, and debugging strategies\n * Drive technical initiatives independently, managing high-impact assignments from concept through deployment and adoption\n* Collaborate with EDA tool development teams to influence product roadmaps, provide feedback, and optimize verification workflows for real-world use cases\n* Troubleshoot and refine verification processes for internal teams and customers, diagnosing flow bottlenecks and delivering solutions that stick\n \nThe Impact You Will Have\n  * Establish verification methodology standards that accelerate time-to-market for Synopsys digital IP and SoC products\n* Enable global verification teams to deliver higher quality results faster by providing robust, reusable flows and infrastructure\n * Shape the verification strategy for next-generation Synopsys IP offerings, directly influencing product quality and customer satisfaction\n* Reduce verification cycle time and resource overhead across multiple projects by standardizing tooling and best practices\n* Develop the next generation of verification engineers at Synopsys, building a culture of technical excellence and continuous learning\n* Influence the evolution of Synopsys EDA tools by providing critical, field-tested feedback to product teams\n* Strengthen Synopsys' leadership position in semiconductor verification by driving adoption of cutting-edge methodologies across the organization\n \nWhat You'll Need\n* 10+ years of hands-on experience in IP or SoC verification, with a proven track record of leading technical initiatives and delivering complex verification environments\n* Deep expertise with Synopsys verification tools including VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and Verification IP (VIP)\n * Strong programming and scripting skills in SystemVerilog, UVM, Tcl, and Python for automation and flow development\n* Demonstrated ability to architect verification flows and infrastructure for complex digital designs, from initial concept to production deployment\n* Bachelor's degree in Electronics, Electrical, or Computer Engineering; advanced degrees are a plus\n * Experience managing multiple technical projects independently, balancing priorities and delivering high-quality results on schedule\n * Ability to document and communicate technical methodologies clearly across global, cross-functional teams\n \nWho You Are\n  * You can explain a complex verification tradeoff to a product manager in two sentences without losing the nuance, and then turn around and debug a UVM testbench with a junior engineer\n* You take ownership of problems that do not have clear owners, and you see them through to resolution even when it means coordinating across time zones and teams\n* You push back when a methodology does not make sense for the use case, and you do it with data and a better alternative, not just criticism\n* You are organized enough to manage five verification projects at once and strategic enough to know which one needs your attention today\n* You teach by showing, not just telling, and you measure your success by how much your team grows, not just what you deliver personally\n* You stay current with verification trends and tools, and you bring new ideas to the table backed by practical understanding of what will actually work in production\n \nThe Team You'll Be Part Of\n You will be a core member of the newly established Digital IP Verification Methodology (COE) team, a group of forward-thinking engineers dedicated to advancing verification excellence at Synopsys. The team collaborates across global sites, driving innovation in methodology, tool integration, and best practices. Together, you will shape the future of digital IP verification, enabling Synopsys and its customers to deliver world-class silicon solutions", "jd_status": "stored"}, {"title": "Sr Staff Digital Design Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-10-05", "url": "https://careers.synopsys.com/job/bengaluru/sr-staff-digital-design-engineer/44408/101580799344", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:\n\n At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\n\nYou Are:\n\n You are a passionate and accomplished digital design engineer with an unyielding drive for excellence. You thrive in technically challenging environments, where your deep understanding of RTL design and system architecture allows you to craft innovative solutions for complex problems. With a solid foundation in electrical engineering or VLSI, you have accumulated over five years of hands-on experience in designing and implementing ASIC solutions, particularly focusing on high-performance protocols such as DDR PHY, PCIe, USB, or HBM. Your expertise extends beyond individual contribution—you are equally comfortable leading and mentoring small design teams, fostering an environment of collaboration and shared learning.\n\nYou are adept at translating functional specifications into detailed micro-architecture and design documents, always ensuring clarity and precision. Your technical toolkit includes mastery of Verilog/SystemVerilog, and you are well-versed in industry-standard flows encompassing linting, CDC analysis, synthesis, and static timing. You’re not just a Sr technical expert; you are a proactive communicator, an enthusiastic collaborator, and a natural problem solver who takes initiative and ownership of deliverables. Your ability to adapt to a global, multi-site team environment is matched only by your commitment to continuous learning and professional growth. If you’re ready to take on a pivotal role in shaping next-generation silicon IP, Synopsys is where your aspirations and impact can soar.\n\nWhat You’ll Be Doing:\n\n * Lead and Drive all aspects of complete IP Design execution from start to end.\n * Architecting, designing, and implementing state-of-the-art RTL for the next-generation high-performance DDR PHY and related IP cores.\n * Translating standard and functional specifications into detailed architecture, micro-architecture, and design documentation for medium- to high-complexity features.\n * Contributing as an individual designer and also lead other engineers in —handling RTL coding, lint/CDC analysis, synthesis, debug, and test plan development. \n * Collaborating with global teams across multiple sites, ensuring cohesive project execution and knowledge sharing.\n * Lead and mentor teams of RTL designers, providing technical guidance and fostering professional development.\n * Engaging in continuous process improvement, proposing and implementing enhancements to design flows and methodologies.\n * Troubleshooting and resolving design and verification issues, ensuring robust and high-quality deliverables.\n\nThe Impact You Will Have:\n\n * Directly contributing to the design and delivery of high-performance IP cores that power industry-leading semiconductor solutions worldwide.\n * Elevating Synopsys’ reputation for technical excellence and innovation in the IP design space.\n * Accelerating the adoption of advanced protocols and interfaces in cutting-edge technologies.\n * Enabling customers to achieve faster time-to-market and superior silicon performance.\n * Mentoring and uplifting team members, fostering a culture of knowledge sharing and technical growth.\n * Driving continuous improvement in design methodologies, enhancing efficiency and product quality.\n * Supporting Synopsys’ mission to remain at the forefront of the Era of Pervasive Intelligence through breakthrough silicon solutions.\n\nWhat You’ll Need:\n\n * Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related discipline.\n * 10+ years of relevant industry experience in ASIC digital design, with a focus on protocols like DDR, PCIe, USB, or HBM.\n * Past experience of leading IP deign projects, team.\n * In-depth experience with RTL coding in Verilog/SystemVerilog and simulation tools for ASIC design.\n * Strong command of design flows, including lint, CDC, synthesis, static timing analysis, and formal verification.\n * Hands-on expertise in architecting and implementing control path-oriented designs (e.g., asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces).\n * Familiarity with scripting languages such as Perl or Shell—an advantage.\n * Demonstrated ability to technically lead or mentor small teams of engineers.\n\nWho You Are:\n\n * A collaborative team player who thrives in a multi-site, multicultural environment.\n * An effective communicator, able to translate complex technical concepts for diverse audiences.\n * A proactive problem-solver with strong analytical and troubleshooting skills.\n * Self-motivated, showing high initiative and ownership of responsibilities.\n * Adaptable and eager to learn, always seeking opportunities for personal and professional growth.\n * Committed to fostering a positive, inclusive, and innovative team culture.\n\nThe Team You’ll Be A Part Of:\n\n You will join the R&D Solutions Group at our Bengaluru Design Center, a dynamic and diverse team dedicated to the design and development of industry-leading DesignWare IP cores. As a Technical Individual Contributor, you will collaborate with global experts in a multi-site environment, contributing to technically challenging projects that push the boundaries of silicon design. The team values innovation, continuous learning, and the sharing of knowledge, offering ample opportunities for growth and leadership.\n\nRewards and Benefits:\n\n We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "R&D Hardware Project Manager", "company": "Nokia", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-10-05", "url": "https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/39819", "is_hardware": true, "platform": "oracle", "jd_text": "In the role of an R&D Hardware Project Manager at Nokia, you will collaborate with a diverse team of experts dedicated to innovating our Coherent Optical Modules' product line. You will thrive in a dynamic and agile environment that encourages creativity and fast-tracked execution of ideas. You'll engage with cross-functional teams, fostering strong relationships while driving projects from concept to completion. Nokia offers a hybrid work model with a flexible schedule, enabling a balance between office collaboration and remote focus time. Your contributions will be recognized and rewarded, with access to professional development opportunities, competitive compensation, and comprehensive benefits packages, including healthcare, retirement plans, and generous leave policies. Join us in shaping the future of communication technology.\n \nNILightpath\n\nResponsibilities\nCreate and execute project schedules for hardware development, ensuring alignment with requirements, design, and verification.\nFacilitate communication among cross-functional teams and manage risks related to project timelines and deliverables.\nTrack and report on development milestones and weekly project progress to stakeholders.\nIdentify potential issues and develop mitigation plans to address them proactively.\nCoordinate prototype hardware builds, including managing Purchase Orders with suppliers.\nFoster collaboration and a positive working environment among team members and stakeholders.\nConduct project performance analysis to ensure goals are met within time and budget constraints.\nLead post-mortem reviews to capture insights and improve future project execution.\n\nQualifications\nMust-Have:\nB.Eng./B.Sc. in a technical field (Electrical, Mechanical, Computer Science or related)\n5+ years of hardware project/product management experience\nProven ability to deliver complex projects on time and within scope\nStrong leadership skills with a focus on relationship building\nProficient in project planning tools like MS Project and Excel\n \n\nNice-To-Have:\nM.Sc. in a technical field\nPMP Certification\nExperience in the telecommunications industry\nFamiliarity with Confluence and Jira tools\nAgile project management experience\n\nAbout the company\nAdvancing connectivity to secure a brighter world.\n\nNokia is a global leader in connectivity for the AI era. With expertise across fixed, mobile and transport networks, powered by the innovation of Nokia Bell Labs, we’re advancing connectivity to secure a brighter world. \n\nLearn more about life at Nokia.\n\nOur recruitment process\n\nWe act inclusively and respect the uniqueness of people. Our employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.\n\nIf you’re interested in this role but don’t meet every listed requirement, we still encourage you to apply. Unique backgrounds, perspectives, and experiences enrich our teams, and you may be just the right candidate for this or another opportunity.\n\nThe length of the recruitment process may vary depending on the specific role's requirements. We strive to ensure a smooth and inclusive experience for all candidates. Discover more about the recruitment process at Nokia.\n\nAbout the organization\nSome of our benefits in India:\n\nFlexible and hybrid working arrangements to support work–life balance\n\nHealth and well-being support – medical insurance for you and your family, health check-ups, life and accident insurance, well-being programs, and employee resource groups \n\nA minimum of 90 days of Maternity and Paternity Leave based on eligibility\n\nPersonal Support Service 24/7 – a confidential support channel open to all Nokia employees and their families in challenging situations\n\nCareer growth & mobility – technical career paths, job rotations, international assignments, and relocation support\n\nContinuous learning – technical certifications, mentoring programs, coaching, and digital learning platforms\n\nOpportunities to innovate and contribute through Nokia’s research and development environment\n\nRecognition programs that celebrate outstanding contributions\n\nWorkplace support – ergonomic working support and mobile device programs based on eligibility", "jd_status": "stored"}, {"title": "Analog Layout Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-10-05", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506499", "is_hardware": true, "platform": "oracle", "jd_text": "We are seeking a Analog Layout Engineer to join our Image Sensor team. The ideal candidate will have strong expertise in analog and mixed-signal layout design, with the ability to independently own layout blocks and work closely with circuit designers to deliver layouts with quality.\n\n #LI-RT1\n\nResponsibilities\nImplement layout of analog and mixed-signal blocks including ADCs, PLLs, Bandgaps, References, LDOs, Bias circuits, and image sensor IPs.\nPerform and resolve DRC, LVS, ERC, EM/IR, density, and reliability checks using EDA tools like Calibre\nClosely work with circuit designers to ensure design goals and schedules are met.\nSupport layout reviews and contribute to methodology and automation.\n#LI-RT1\n\nQualifications\n5-8 years of experience in analog and mixed-signal layout design.\nStrong hands-on experience with Cadence Virtuoso Layout Suite.\nGood understanding of analog layout verification and signoff flows.\nStrong knowledge of:Device matching and common-centroid layout techniques\nSymmetry and critical analog routing\nShielding and noise isolation methodologies\nParasitic-aware layout practices\n\nEffective communication skills.\nExposure to layout automation, scripting, or productivity enhancement initiatives is desirable.\n#LI-RT1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Staff Analog IC Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-10-05", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506826", "is_hardware": true, "platform": "oracle", "jd_text": "Analog Staff Design Engineer \n\nAbout Us\n\nAt onsemi, we help improve lives through silicon solutions every day. Our intelligent power and sensing technologies solve the world’s most complex challenges and lead the way in creating a safer, cleaner, and smarter world. Our team in Bangalore develops high speed communications chips for automotive applications. We invite you to join our innovative team and contribute to the growth of Bangalore design center.\n\nThe Role\n\nAs part of the Sensor Interface Division, the Design Team in Bangalore develops and brings to production low-power high speed mixed-signal ICs for automotive Ethernet and automotive serdes. We are looking to expand our design team with an Analog IC Design Engineer with PLL design experience. You will architect, specify and implement PLL and other sub systems and help in PLL chip-level integration, chip-level simulations and silicon validation for the above mentioned high speed communication chips.\n\nWhy Join Us\n\nWe create a diverse set of world-class products in a friendly and team-oriented atmosphere. We provide an environment of continual learning and growth opportunities and support volunteer & charitable programs. You will be entitled a very competitive benefit package. You will be able to build up a career in successful international company, and you can participate in interesting international projects.\n\n#LI-VS1\n\nResponsibilities\nWhat You’ll Do\n\nParticipate in feasibility studies and architecture definitions of new products.\n\nGenerate detailed specifications and verification plans for analog blocks and systems especially PLL \n\nDevelop Matlab & Verilog A models of analog blocks related to PLL.\n\nDevelop low-power high speed analog systems Design, verification & Layout supervision.\n\nIntegrate analog blocks into complex mixed-signals System-on-Chip (SoC) designs.\n\nPerform top-level Mixed-Signal simulations.\n\nSilicon Evaluation and characterization of designed blocks in the lab.\n\nSupport the production test development and qualification.\n\nContribute to design methodology and design flow improvements.\n\n#LI-VS1\n\nQualifications\nWhat You’ll Need\n\nMust have a BSEE, MSEE or Ph.D. with at least 6-10 + years of IC design work experience\n\nExtensive experience in high performance complete PLL design from scratch is required with at least 1 tape out & silicon success. \n\nExperience in designing low phase noise/jitter integer PLLs, fractional-N synthesizers.\n\nGood knowledge of band gaps, bias, opamps, LDOs, feedback and compensation techniques.\n\nExperience in VCO design including but not limited to LC VCOs.\n\nMust have Strong knowledge of loop design to optimize for phase noise/jitter, lock time, reference spur, area, power.\n\nGood knowledge of low noise design techniques.\n\nGood knowledge of high precision techniques in presence of device mismatch\n\nExperience in C/Matlab/VerilogA modeling\n\nUnderstand device physics and demonstrated ability to apply that to optimize noise, power, area, and frequency of PLL blocks.\n\nSystem knowledge of Automotive serdes/ethernet and its link budget analysis will be added advantage \n\nGood working experience in using spectrum analyzers, oscilloscopes, signal generators, etc. to validate analog designs.\n\nExperience in working with production test engineers to firm up test plans and design for testability details.\n\nExperience with IP integration and Mixed-Signal IC verification\n\nGood English written and verbal communication skills.\n\nWhat Else You May Bring \n\nExperience with:\n\nLeading project activities\n\nLab measurements and characterization equipment\n\nScripting languages\n\nDigital design\n\nIf you match our profile and you are interested in joining our dynamic team of professionals, please contact - Venugopal.Shetty@onsemi.com\n\n#LI-VS1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Sr Principal Analog IC Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-10-05", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506827", "is_hardware": true, "platform": "oracle", "jd_text": "Analog Principal IC Design Engineer About Us\nAt onsemi, we help improve lives through silicon solutions every day. Our intelligent power and sensing technologies solve the world’s most complex challenges and lead the way in creating a safer, cleaner, and smarter world. Our team in Bangalore develops high speed communications chips for automotive applications. We invite you to join our innovative team and contribute to the growth of Bangalore design center.\nThe Role\nAs part of the Sensor Interface Division, the Design Team in Bangalore develops and brings to production low-power high speed mixed-signal ICs for automotive Ethernet and automotive SerDes. We are looking to expand our design team Analog IC Staff / Principal Design Engineer with high-speed Class-AB Line driver expertise or high-speed Receiver chain or high speed PLL design experience. You will architect, specify and implement one of the above blocks, help in chip-level integration, chip-level simulations and silicon validation for the above-mentioned high-speed communication chips.\nWhy Join Us\nWe create a diverse set of world-class products in a friendly and team-oriented atmosphere. We provide an environment of continual learning and growth opportunities and support volunteer & charitable programs. You will be entitled to a very competitive benefit package. You will be able to build up a career in successful international company, and you can participate in interesting international projects.\nWhat You’ll Do\n\nParticipate in feasibility studies and architecture definitions of new products.\n\nGenerate detailed specifications, Architect, circuit design and verification plans for high speed Class-AB Line driver or high-speed Receiver chain (PGA, Filters, hybrid) or high speed PLL.\n\nDevelop MATLAB & Verilog A models of analog blocks related to the above blocks.\n\nGuide and help in Layout.\n\nIntegrate analog blocks into complex mixed-signals System-on-Chip (SoC) designs.\n\nPerform top-level Mixed-Signal simulations.\n\nSilicon Evaluation and characterization of designed blocks in the lab.\n\nSupport the production test development and qualification.\n\nContribute to design methodology and design flow improvements.\n\n#LI-VS1\n\nResponsibilities\nWhat You’ll Need\n\nMust have a BSEE, MSEE or Ph.D. with at least 6-15 + years of IC design work experience\n\nExtensive experience in high speed and high performance in any one of the above mentioned blocks from scratch is required with at least 1 tape out & silicon success. \n\nGood knowledge of low noise design techniques.\n\nGood knowledge of high precision techniques in presence of device mismatch\n\nExperience in C/MATLAB/Verilog A modeling\n\nUnderstand device physics and demonstrated ability to apply that to optimize noise, power, area, and performance.\n\nSystem knowledge of Automotive SerDes/ethernet and its link budget analysis will be added advantage \n\nGood working experience in using spectrum analyzers, oscilloscopes, signal generators, etc. to validate analog designs.\n\nExperience in working with production test engineers to firm up test plans and design for testability details.\n\nExperience with IP integration and Mixed-Signal IC verification\n\nGood English written and verbal communication skills.\n\n#LI-VS1\n\nQualifications\nWhat Else You May Bring \n\nExperience with:\n\nLeading project activities\n\nLab measurements and characterization equipment\n\nScripting languages\n\nDigital design\n\nIf you match our profile and you are interested in joining our dynamic team of professionals, please contact \n\nVenugopal.Shetty@onsemi.com\n\n#LI-VS1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Senior Digital Verification Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-10-05", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506824", "is_hardware": true, "platform": "oracle", "jd_text": "We are looking for a highly motivated Senior Digital Verification Engineer with 5-7 years of experience in ASIC/SoC verification. The ideal candidate will have strong expertise in System Verilog (SV) and UVM, along with hands-on experience in developing scalable verification environments, coverage-driven verification, and debugging complex RTL and gate-level issues. Exposure to Gate-Level Simulation (GLS) is a plus\n\n#LI-DJ1\n\nResponsibilities\nDevelop and execute comprehensive verification plans for subsystem, and SoC-level designs.\nIndependently develop and work on reusable verification environments using System Verilog and UVM.\nCreate constrained-random, directed, and scenario-based test cases.\nDevelop scoreboards, monitors, protocol checkers, assertions (SVA), and coverage models.\nAnalyze and debug RTL and gate-level simulation failures for timing and functional signoff.\nAnalyze, debug, and enhance C/C++ golden reference models for functional verification.\nExecute, and debug fault injection simulations to validate functional safety requirements and fault handling mechanisms.\nCollaborate closely with design, DFT, physical design, and architecture teams to resolve issues and support sign-off activities.\nWork with AI-assisted engineering tools (e.g., GitHub Copilot, Microsoft Copilot, LLM-based code generation/debug tools, AI-driven verification productivity solutions) to enhance regression infrastructure and verification automation\n#LI-DJ1\n\nQualifications\nMaster's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.\n5-7 years of hands-on experience in Digital/ASIC/SoC Verification.\nStrong expertise in: System Verilog (Mandatory) and UVM (Mandatory)\nFamiliarity with industry-standard simulators such as Xcelium and Questa.\nVerification experience with some or all protocols such I2C, AHB/APB, MIPI\n#LI-DJ1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Electrical Engineer II RF Engineering", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2026-10-05", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/Electrical-Engineer-II-RF-Engineering_R2629800", "is_hardware": true, "platform": "workday", "jd_text": "Who We Are\n\nApplied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI and accelerating the commercialization of next-generation semiconductor chips. Join us and push the boundaries of materials science and engineering in a company at the foundation of the electronics industry. The work we do together advances the world’s technology.\n\nWhat We Offer\n\nLocation:\nBangalore,IND\nYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. \n\nAt Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. \n \n \nAs an Electrical Engineer, you are responsible for designing, modifying, and troubleshooting electrical or electronic engineering assemblies, layouts, schematics, and drawings to advance the equipment that supports our technology. Using your technical experience and critical thinking skills, you will perform engineering analysis, generate test reports, develop innovative solutions, and create documentation for product releases. You will also coordinate the procurement and assembly of components, identify sources of critical parts, and resolve technical issues to ensure peak performance. \n \nRole Responsibilities: \nDesign or modify electrical or electronic engineering assemblies, layouts, schematics, drawings or specifications of moderate scope under general supervision \n\nPerform basic engineering analysis under general supervision \n\nPerform and generate basic engineering test reports; generate related alpha/gamma documentation for product releases \n\nCoordinate the procurement and assembly of electrical or electronic components and equipment, and identify sources of critical parts and subsystems to resolve technical issues \n\nTroubleshoot a variety of moderately complex electrical problems \n\nImplement concepts for product issues and electrical solutions of moderate difficulty \n\nAssist in the development of electrical product specifications \n\nClearly communicate complex information in straightforward situations\n\nMinimum Qualifications:\nBachelor’s degree\n\n2-4 years of related experience\n\nPreferred Qualifications:\nA solid understanding of the industry’s key business drivers  \n\nGood communication/interpersonal skills to explain complex information to others   \n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nAssignee / Regular\nTravel:\n\nRelocation Eligible:\nNo\n\nApplied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "Electrical Engineer II Senior", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2026-10-05", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/Electrical-Engineer-II-Senior_R2629799", "is_hardware": true, "platform": "workday", "jd_text": "Who We Are\n\nApplied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI and accelerating the commercialization of next-generation semiconductor chips. Join us and push the boundaries of materials science and engineering in a company at the foundation of the electronics industry. The work we do together advances the world’s technology.\n\nWhat We Offer\n\nLocation:\nBangalore,IND\nYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. \n\nAt Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. \n \n \nAs an Electrical Engineer, you are responsible for designing, modifying, and troubleshooting electrical or electronic engineering assemblies, layouts, schematics, and drawings to advance the equipment that supports our technology. Using your technical experience and critical thinking skills, you will perform engineering analysis, generate test reports, develop innovative solutions, and create documentation for product releases. You will also coordinate the procurement and assembly of components, identify sources of critical parts, and resolve technical issues to ensure peak performance. \n \n                                      Electrical Engineer\n \n \nEducational Qualification:\n \n       Degree / master’s in electrical / Instrumentation Engineering with Below criteria.\n \n \nKey Responsibilities:\n \n·       Good understanding of electrical concepts like three phase power calculations.\n·       Good understanding of complex polar and cartisan calculations for power calculation and estimation.\n·       Good understanding of working principle of electrical and electronic components.\n·       Good understanding of electrical circuit protection concepts and components.\n·       Good understanding of working principle of different types of sensors.\n·       Develop an expertise in AC power distribution design in short span of time.\n·       Creates and modifies detailed drawings using Computer Aided Design (E3S CAD) hardware and software from sketches, layouts or notes provided by engineering in the investigation and solution of technical problems\n·       Contributes design modifications to facilitate manufacturing operation or quality of product.\n \nJob Specific Knowledge :\n \n·       Knowledge of Electrical engineering design concepts and techniques and ability to read and\nunderstand Electrical Schematics.\n·       Knowledge on Electrical CAD tools: E3s, AutoCAD Electrical would be an advantage.\n·       Knowledge on PLC’s, drives, and other electrical components and equipment.\n·       Ability to work on electrical panel schematics and related documentation.\n·       Basic knowledge on Electrical engineering discipline\n·       Willing to learn and adapt to new BKM quickly.\n·       Knowledge on PLC’s, drives, and selection of other electrical components.\n \nProblem Solving\n·       Medium/complex problems solver; uses sophisticated analytical thought to exercise judgment and identify innovative solutions\nImpact\nImpacts the achievement of customer, operational, project or service objectives; work is guided by functional policies\nInterpersonal Skills\nCommunicates difficult concepts and negotiates with others to adopt a different point of view\nExperience:\n3- 5years in Electrical HW design, troubleshooting\nKnowledge of the Semiconductor industry, hands-on experience working lab, test stand setup\n\n \n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nAssignee / Regular\nTravel:\n\nRelocation Eligible:\nNo\n\nApplied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "Technical Staff Engineer-Design", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-10-05", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Technical-Staff-Engineer-Design_R4199-26", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nThe Wireless Solutions Group is seeking an experienced Design Engineer for our next generation high-performance, low-power wireless SoC and attach solutions. In this role, you will be responsible for the design of System-on-Chip (SOC) solutions for wireless applications. You will collaborate closely with cross-functional teams, including verification, analog, validation, and software engineers, to deliver high-quality products. Successful candidates require strong collaboration across sites and functions, excellent communication, and the ability to thrive in a fast-paced, dynamic environment.\n\nKey Responsibilities:\nContribute to SOC design from concept to tape-out.\nImplement SOC designs according to micro-architecture specifications and design documentation, performing RTL coding, synthesis, timing analysis, and executing the SOC design flow to ensure IC qualification meets required standards.\nCollaborate with verification teams to ensure thorough design verification according to test plans.\nWork with physical design teams to ensure successful integration and implementation.\nParticipate in design reviews to ensure compliance with design standards and project requirements.\nSupport the validation team in qualifying silicon ICs and debugging potential issues.\nContribute to the development and optimization of low-power design techniques and power estimation methodologies.\nInterfacing with external vendors and IP sources to resolve problems.\nAbility to work well in a team and excellent problem solving, verbal and written communication skills.\nWorking with members from international design and implementation teams.\n\nRequirements/Qualifications:\n\nBachelor's degree in computer engineering, electrical engineering, or related field.\nMinimum 12+ years of experience in digital SOC design, with a focus on low-power design.\nProficient in RTL design (Verilog/System Verilog), Low-power design, synthesis, timing constraint (SDC) and timing analysis.\nExperience with ASIC design flow including LINT, Formal, CDC/RDC, power estimations, MBIST/DFT concepts, and low-power design techniques.\nStrong understanding of SOC architecture (ARM/MIPS), bus protocols (AMBA, AXI, etc.), and peripheral IPs (USB, Ethernet, I2C, SPI, etc).\nExperience with Bus Matrix design.\nExperience with script Language such as TCL, Perl, and Python.\nExcellent English reading, writing and verbal communication skills.\nStrong analytical and problem-solving skills.\nWe are looking for candidates who are self-motivators, energetic, and team players.\n\nPreferred Skills and Experience:\nMaster’s degree in computer engineering, electrical engineering, or related field.\nKnowledge of Bluetooth/BLE/Wi-Fi communication theory and standard specifications.\nKnowledge of security features and principles of functional safety–compliant design.\nExperience with verification methodologies (UVM/OVM).\nExperience with validation methodologies, including debugging on FPGA and silicon IC boards.\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Electrical Engineer", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2026-10-05", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/Electrical-Engineer_R2628187", "is_hardware": true, "platform": "workday", "jd_text": "Who We Are\n\nApplied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI and accelerating the commercialization of next-generation semiconductor chips. Join us and push the boundaries of materials science and engineering in a company at the foundation of the electronics industry. The work we do together advances the world’s technology.\n\nWhat We Offer\n\nLocation:\nBangalore,IND\nYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. \n\nAt Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. \n \n \nAs an Electrical Engineer, you are responsible for designing, modifying, and troubleshooting electrical or electronic engineering assemblies, layouts, schematics, and drawings to advance the equipment that supports our technology. Using your technical experience and critical thinking skills, you will perform engineering analysis, generate test reports, develop innovative solutions, and create documentation for product releases. You will also coordinate the procurement and assembly of components, identify sources of critical parts, and resolve technical issues to ensure peak performance. \n \nRole Responsibilities: \nDesign or modify electrical or electronic engineering assemblies, layouts, schematics, drawings, or specifications of difficult scope \n\nIdentify and troubleshoot a variety of complex electrical problems with limited supervision \n\nDefine, coordinate, perform and generate engineering test reports with limited supervision \n\nPerform engineering analysis of difficult scope with limited supervision \n\nTechnically lead or execute engineering projects, including the development of key suppliers \n\nImplement concepts for a variety of complex product issues and electrical solutions of difficult scope \n\nGenerate electrical product specifications; specify and review engineering documentation \n\nServe as a resource for junior colleagues; lead project teams, as needed\n\nClearly communicate difficult or sensitive information; build consensus \n\nMinimum Qualifications: \nBachelor’s degree\n\n4-7 years of experience in a related field\n\nPreferred Qualifications: \nStrong knowledge of industry best practices, key business drivers, competition in the marketplace, and how your area of expertise integrates with others  \n\nDemonstrated leadership skills to lead small projects as needed  \n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nAssignee / Regular\nTravel:\n\nRelocation Eligible:\nNo\n\nApplied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "Senior Design Engineer - Memory Subsystem", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-05", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Design-Engineer---Memory-Subsystem_JR2026759", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking passionate, highly motivated, and creative senior design engineers to be part of a team working on the design of state of the art memory sub-system components used in their industry-leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nIn this position, you will be encouraged to make architectural trade-offs based on features, performance requirements and system limitations, come up with micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. You will work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and backend teams to accomplish your tasks.\n\nWhat you’ll be doing:\nOwn micro-architecture and RTL development of design modules.\nMicro-architect features to meet performance, power and area requirements.\nWork with HW architects to define critical features.\nCollaborate with verification teams to verify the correctness of implemented features.\nInteract with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable.\nCo-operate with FPGA and S/W teams to prototype the design and ensure that S/W is tested.\nWork on post-silicon verification and debug.\n\nWhat we need to see:\nBS / MS or equivalent experience.\n4+ years of design experience.\nExperience in micro-architecture and RTL development of complex designs.\nExposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).\nDeep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping,, timing analysis, floor-planning, ECO, bring-up & lab debug.\nExpertise in Verilog.\n\nWays to stand out from the crowd:\nDesign experience in memory subsystem or network interconnect IP.\nGood debugging and problem solving skills.\nScripting knowledge (Python/Perl/shell).\nGood interpersonal skills and ability & desire to work as a part of a team.\n\nNVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.", "jd_status": "stored"}, {"title": "Verification Engineer, PCIE", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-10-05", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Verification-Engineer--PCIE_JR2025159", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science.\n\nThe GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nBe responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nExpected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.\n\nYou will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech or equivalent experience\n\n1+ years of relevant experience\n\nExperience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog\n\nExpertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)\n\nExperience in developing and working in functional coverage based constrained random verification environments\n\nBackground in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nExcellent knowledge of PCIE protocol - Gen3 and above\n\nGood understanding of the system level architecture of PCIE/CXL-based designs\n\nPerl, Python or similar scripting and SW programming language experience\n\nGood debugging and analytical skills\n\nGood interpersonal skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Static Timing Analysis Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-10-05", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Static-Timing-Analysis-Engineer_JR0284206", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact:\nAs a Physical Design Timing Engineer, you will play a pivotal role in advancing Intel's next-generation SoCs by ensuring their optimal performance and efficiency. Your expertise will directly impact the success of Intel's products, enabling innovation across high-performance computing, AI, and beyond. You will work on cutting-edge designs, collaborating with cross-functional teams to tackle complex challenges while delivering high-quality timing models that empower the physical design team to excel. This is an exciting opportunity to contribute to Intel's mission of shaping the future of technology.\n\nKey Responsibilities:\n- Perform timing analysis and optimization to ensure design functionality and performance at the chip and block levels.\n- Generate and verify timing constraints, addressing and resolving timing violations during SoC development.\n- Conduct timing rollups, develop and implement power-optimized clock networks, and ensure alignment with high-performance, low-power guidelines.\n- Define and implement methodologies to deliver quality timing models that enhance the efficiency of the physical design process.\n- Set process, voltage, and temperature (PVT) conditions for timing analysis based on product plans and operating conditions.\n- Collaborate with architecture, clock design, logic design, and backend teams to achieve clocking balance, power delivery optimization, and efficient partitioning.\n- Partner closely with the clocking team to refine methodologies and validate integration flows for chip-level timing solutions.\n\nQualifications:\nMinimum Qualifications:\n- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.\n- 8+ years of experience in Physical Design with a Bachelor's degree, 6+ years with a Master's degree, or 4+ years with a PhD.\n- Proficiency in static timing analysis tools and methodologies.\n- Demonstrated expertise in timing modeling, verification, constraint generation, and optimization techniques.\n- Technical understanding of PVT conditions and their application in timing analysis.\n\nPreferred Qualifications:\n- Advanced knowledge of SoC development, clocking design principles, and timing methodologies.\n- Strong collaboration skills, with a proven ability to work across architecture, logic design, and physical design teams.\n- Experience in high-performance computing or low-power design environments.\n- Commitment to continuous learning and staying updated on industry advancements.\n\nJoin us and be part of a team shaping the future of technology. Apply today to make your mark.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "CPU RTL Design-Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-04T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718325973", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nIf you enjoy deep micro‑architecture, high‑quality RTL, and solving hard performance and efficiency problems that ship at scale, we’d love to talk.\nWe’re expanding our CPU Core RTL Design team and are looking for experienced micro‑architecture / RTL engineers across multiple core domains to work on cutting‑edge, high‑performance processors.\nThis is hands‑on, high‑ownership work — not maintenance.\n\n🔧 What you’ll work on\n- Architect, design, and optimize CPU core micro‑architecture\n- Own end‑to‑end RTL in one or more domains: Fetch | Decode | Rename | Execute | Vector | Load‑Store | Memory Management\n- Collaborate closely with Architecture, DV, Physical Design, Post-Silicon, Power and Performance teams\n- Drive performance, power, and area trade‑offs using real data\n- Deliver production‑ready, high‑quality RTL that goes into silicon\n\n🧠 What we’re looking for\n- Strong fundamentals in CPU micro‑architecture and RTL design\n- Deep expertise in one or more pipeline stages (Front‑end or Back‑end)\n- Proficiency in SystemVerilog\n- Experience with debugging, optimization, and performance analysis\n- 5–12 years of CPU experience (senior engineers very welcome)\n\n🌟 Why join us?\nYou’ll work on core IP that truly matters, alongside world‑class engineers, in a team that values technical rigor, clean design, and engineering excellence.\nThis is an opportunity to shape the future of high‑performance computing — not just contribute to it.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Lead Engineer - DFT", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-04T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720239637", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-04T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720513974", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    5+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Sr. Memory Designer", "company": "Lattice", "location": "San Jose, CA", "date_posted": "2026-10-04", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/San-Jose-CA/Principal-Design-Engineer_R-100739-1", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\n\nJob Description:\n\nSr. Memory Designer\n\nKey Responsibilities:\nDesign and Development: Lead the design and development of custom circuits for high-speed and low-power SRAM and low-power configuration RAM (CRAM)\n\nArchitecture and Implementation: Develop memory architectures and implement them in advanced semiconductor technologies, including FinFET and nanometer CMOS\n\nSimulation and Verification: Perform schematic capture, simulation, and margin verification of major memory blocks\n\nLayout Planning: Oversee layout planning and ensure tight pitch-matched memory layout designs\n\nCollaboration: Work closely with architecture and design teams to define memory PPA (Performance, Power, Area) and yield targets\n\nFull Design Flow: Manage the full embedded memory design flow, including architecture, circuit design, physical implementation, compiler usage, characterization, timing, and model generation\n\nInnovation: Bring innovative and revolutionary ideas to life in our products, influencing various parts of our FPGA designs\n\nQualifications:\nEducation: Bachelor’s degree in electrical engineering, or a related field. A Master’s or PhD is preferred\n\nExperience: Over 10 years of experience in memory design, verification, validation, and integration\n\nTechnical Skills:\nStrong knowledge of custom memory design, high speed, low power as well as custom memory design for configuration of FPGA\n\nExpertise in high-performance and low-power design techniques\n\nFamiliarity with variation-aware design in advanced semiconductor technologies\n\nSoft Skills: Excellent problem-solving skills, strong communication abilities, and the ability to work collaboratively in a team environment\n\nPreferred Qualifications:\nExperience with large density memory cell design for high yield\n\nKnowledge of semiconductor device fundamentals\n\nPay & Benefits\n\nConsistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. \n\nFor candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.  The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.\n\nBase Pay Range\n220800\nIn addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! \n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in the United States.\n\nLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.\n \nAs an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.", "jd_status": "stored"}, {"title": "PD PNR Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-02T18:01:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92544/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. MTS Silicon Design Engineer – Tile PnR Role Summary Responsible for end-to-end physical implementation and convergence of complex SoC/IP tiles. The engineer will drive floorplanning, place-and-route, timing closure, power and area optimization, physical verification readiness, and ECO implementation while collaborating closely with RTL, architecture, CAD, timing, clocking, and full-chip teams. Expected to independently own critical tiles, deliver high-quality milestones, and contribute to methodology and automation improvements. Key Responsibilities Own end-to-end implementation and convergence of assigned tiles from netlist handoff to signoff. Drive floorplanning, placement, CTS, routing, timing, power, congestion, and area optimization. Perform timing analysis and implement setup/hold/ECO fixes to achieve QoR targets. Debug implementation issues related to timing, congestion, DRC, EMIR, CDC, and physical integration. Collaborate with RTL, Architecture, Clocking, DFT, Integration, and CAD teams to resolve design challenges. Support milestone deliveries and ensure quality execution aligned with project schedules. Develop automation, scripts, and improved methodologies to enhance productivity and convergence efficiency. Mentor junior engineers and contribute to technical reviews, best practices, and knowledge sharing. Required Qualifications Bachelor’s or Master’s degree in Electrical/Electronics Engineering, VLSI, Computer Engineering, or related field. 7 to 10 years of experience in Physical Design or ASIC implementation. Strong understanding of digital design fundamentals and VLSI implementation flows. Hands-on experience with floorplanning, placement, CTS, routing, timing closure, and ECO implementation. Good understanding of STA concepts, timing optimization, and physical design signoff requirements. Proficiency in scripting using Tcl, Python, Perl, or Shell. Strong debugging, analytical, and problem-solving skills. Excellent communication and cross-functional collaboration abilities. Preferred Experience Experience in converging large and complex CPU, GPU, NOC, AI/ML, or networking tiles. Exposure to advanced technology nodes (5nm, 4nm, 3nm or below). Knowledge of power optimization, EMIR, CDC, RDC, and physical verification methodologies. Experience with Synopsys Fusion Compiler, ICC2, PrimeTime, RedHawk, or equivalent EDA tools. Proven track record of independently leading critical tiles and driving milestone deliveries. Experience in PPA optimization, methodology development, AI-assisted PD flows, and automation initiatives. Ability to guide junior engineers and act as a technical lead for assigned tiles. #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Lead STA / Timing analysis Design Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-02T08:54:00+00:00", "url": "https://global-external-amd.icims.com/jobs/87964/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.   MTS SILICON DESIGN ENGINEER  (STA/Timing) KEY RESPONSIBILITIES: Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Ensuring constraints quality (SDC) using industry tools like Fishtail , GCA Well versed with timing signoff methodology and corner definitions Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts) Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip. Ensuring full chip level Interface timing closure along DRV closure Generating timing ECO using tools DMSA/Tweaker and leading subsystem/Subchip/FC timing closure PREFERRED EXPERIENCE: 8+ years of experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. Experience with analyzing the timing reports and identifying both the design and constraints related issues. Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc. Experience in timing closure of high frequency blocks & subsystems (> Ghz range ) Strong Understanding of DFT modes requirements for timing signoff Good understanding of physical design flow and ECO implementation. Strong understanding of SDC constraints, OCV,AOCV,POCV analysis. Strong TCL/scripting knowledge is mandatory.   ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "FPGA Architecture Engineer", "company": "Lattice", "location": "San Jose, CA", "date_posted": "2026-10-02", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/San-Jose-CA/FPGA-Architecture-Engineer_R-103311", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\n\nJob Description:\nLattice Semiconductor, “the low power programmable leader,” is seeking an experienced FPGA Architecture Engineer to help define, evaluate, and realize next-generation FPGA architectures. This role connects architectural exploration with hardware implementation and software/CAD enablement, emphasizing power efficiency while balancing performance, area, and software quality of results.\n \n\nWhat You'll Do:\n \nEvaluate and define next generation FPGA fabric architectures\nAI-accelerated FPGA architectural exploration and optimization\nFPGA architectural modeling and evaluation\nWork closely with SW CAD development and IC HW design teams to ensure the architecture can meet SW QOR (Quality of Results) and HW PPA (Power, Performance, Area) goals\n \n\nWhat We Are Looking For:\n\nBS, MS, or PhD in electrical engineering, computer engineering, computer science, or a related field.\nTypically, 10 years of relevant experience; candidates with strong relevant accomplishments and fewer years will also be considered.\nExperience in FPGA architecture, FPGA CAD, or ASIC/chip design, with demonstrated ability to reason about architectural tradeoffs.\nUnderstanding of digital design and the relationship between architecture, implementation, and power, performance, and area.\nProgramming and modeling skills for architectural research and analysis, including Python; familiarity with Verilog or VHDL.\nInitiative, clear technical communication, and effective cross-functional collaboration.\n \n \nEspecially Valuable:\n\nExperience with commercial FPGA architectures and CAD tools.\nExperience connecting architectural decisions to hardware implementation, CAD behavior, or customer workloads.\nRelevant FPGA architecture research supported by models, experiments, or publications.\nExperience applying AI/ML or generative-AI tools to engineering problems, with an interest in advancing their practical use.\n\nPay & Benefits\n\nConsistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. \n\nFor candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.  The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.\n\nBase Pay Range\n201600\nIn addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! \n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in the United States.\n\nLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.\n \nAs an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.", "jd_status": "stored"}, {"title": "Principal Post-Silicon System Validation Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-10-02", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506724", "is_hardware": true, "platform": "oracle", "jd_text": "Principal Post-Silicon System Validation Engineer\n\nPosition Summary\n\nThe Principal Post-Silicon System Validation Engineer is responsible for defining and executing system-level validation strategies for Power Management Devices (PMD), ensuring robust product performance and quality from first silicon through production release. This individual contributor role requires deep expertise in semiconductor validation, power electronics, automation, characterization, and silicon debug.\n\n#LI-VS1\n\nResponsibilities\nKey Responsibilities\n\nDevelop and execute comprehensive validation plans covering functional, electrical, system, reliability, and application-level requirements.\n\nLead silicon characterization, system validation, and root cause analysis of complex product and application issues.\n\nDesign and implement automated validation solutions using LabVIEW, Python, NI PXI, and related platforms.\n\nValidate PMD products including SmartFETs, eFuses, power switches, gate drivers, and automotive power solutions.\n\nCollaborate with Design, Systems, Product Engineering, Applications, Quality, and Reliability teams to drive product readiness and issue resolution.\n\nDevelop validation methodologies, best practices, and reusable automation frameworks.\n\nInfluence future product designs through data-driven technical insights and validation expertise.\n\n#LI-VS1\n\nQualifications\nQualifications\n\nBS/MS/PhD in Electrical Engineering or related discipline.\n\nGrade 12: 5+ years of post-silicon validation, characterization, or systems engineering experience.\n\nGrade 13: 8+ years of experience with recognized technical leadership in validation and power management systems.\n\nStrong knowledge of analog/mixed-signal circuits, power electronics, automotive systems, and semiconductor validation methodologies.\n\nExpertise with laboratory instrumentation, automation, and debug techniques.\n\nExperience with LabVIEW, Python, and automated test systems.\n\nPreferred\n\nSmartFET, eFuse, Gate Driver, SBC, or automotive validation experience.\n\nFunctional Safety, ISO 26262, ISO 21780, SiC/GaN, and AI-assisted validation experience.\n\n#LI-VS1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Solution Owner, EDA", "company": "Nokia", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-10-02", "url": "https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/41164", "is_hardware": true, "platform": "oracle", "jd_text": "The Solution Owner, EDA will play a crucial role in our FIT ITIS DO C&BA HW Engineering department. They will be accountable for the installation, maintenance, and compatibility testing of EDA tools. This role requires expertise in managing EDA environments, tool installation, and working with various industry-leading tools and software. The successful candidate will ensure the efficient and effective use of EDA tools, driving tool installation processes and running sanity test cases.\n\nResponsibilities\nAccountable for EDA tool installation, maintenance, and compatibility testing and maintenance for RF, ASIC, Analog and FPGA design.\nImplement and maintain regression tools from Synopsys and Siemens.\nConduct compatibility testing of open-source tools in a Linux environment.\nDrive and oversee the tool installation process for RF EDA tools.\nRun end-user sanity test cases for RF EDA tools from Ansys, Siemens, Dassault, and Keysight.\nMaintain service support documents and ensure proper documentation.\nCollaborate with Infra teams to resolve day-to-day issues and provide support.\nDebug EDA tool issues in a Linux GRID environment using Altair Accelerator, LSF, or SLURM.\nStay updated with the latest advancements in EDA tools and technologies.\nEnsure smooth operations and efficient utilization of EDA resources.\n\nQualifications\n5+ years of experience in supporting EDA environments globally.\nProficiency in installing EDA tools in Linux environments, specifically RHEL8 or RHEL9.\nFamiliarity with digital design flow for Digital IC design from Synopsys, Cadence, or Siemens.\nWorking knowledge of digital EDA tools from Synopsys, Cadence, and Siemens.\nExperience with RF design tools from Ansys, Keysight, Dassault, and Modelithics.\nUnderstanding of FPGA design tools from AMD and Altera.\nStrong working knowledge of the Linux environment.\nExperience with EDA tools in GRID environments, such as LSF or Altair Accelerator.\nScripting knowledge is a plus (e.g., shell scripting, Python, or Perl).\n\nAbout the company\nAdvancing connectivity to secure a brighter world.\n\nNokia is a global leader in connectivity for the AI era. With expertise across fixed, mobile and transport networks, powered by the innovation of Nokia Bell Labs, we’re advancing connectivity to secure a brighter world. \n\nLearn more about life at Nokia.\n\nOur recruitment process\n\nWe act inclusively and respect the uniqueness of people. Our employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.\n\nIf you’re interested in this role but don’t meet every listed requirement, we still encourage you to apply. Unique backgrounds, perspectives, and experiences enrich our teams, and you may be just the right candidate for this or another opportunity.\n\nThe length of the recruitment process may vary depending on the specific role's requirements. We strive to ensure a smooth and inclusive experience for all candidates. Discover more about the recruitment process at Nokia.\n\nAbout the organization\nSome of our benefits in India:\n\nFlexible and hybrid working arrangements to support work–life balance\n\nHealth and well-being support – medical insurance for you and your family, health check-ups, life and accident insurance, well-being programs, and employee resource groups \n\nA minimum of 90 days of Maternity and Paternity Leave based on eligibility\n\nPersonal Support Service 24/7 – a confidential support channel open to all Nokia employees and their families in challenging situations\n\nCareer growth & mobility – technical career paths, job rotations, international assignments, and relocation support\n\nContinuous learning – technical certifications, mentoring programs, coaching, and digital learning platforms\n\nOpportunities to innovate and contribute through Nokia’s research and development environment\n\nRecognition programs that celebrate outstanding contributions\n\nWorkplace support – ergonomic working support and mobile device programs based on eligibility", "jd_status": "stored"}, {"title": "Lead Full Chip Floorplan Design Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-01T16:05:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92824/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. THE ROLE: We at AECG SSD Custom Silicon are seeking a highly motivated and experienced Full-Chip Floorplan Engineer to drive physical implementation planning for complex SoCs and ASICs. The candidate will be responsible for developing and optimizing full-chip floorplans, partitioning strategies, power planning, interconnect planning, and physical architecture to achieve aggressive PPA (Power, Performance, Area) targets while ensuring design convergence and manufacturability. The role requires close collaboration with Architecture, RTL, Physical Design, DFT, Power, Package, and Verification teams throughout the SoC development lifecycle. Industry full-chip floorplanning activities commonly include die shaping, macro placement, IO planning, power-domain planning, pin assignment, feedthrough planning, and physical integration strategy development. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Full-Chip Floorplanning Develop and own top-level SoC floorplan architecture. Define chip aspect ratio, die size, partitioning strategy, and hierarchy planning. Perform macro placement and optimization for timing, congestion, power, and thermal considerations. Drive floorplan refinement through design milestones. Define floorplan topology for large-scale SoCs containing multiple subsystems, hard IPs, memories, and third-party IPs. Physical Architecture Planning Develop and optimize: Power domain strategy Voltage island planning Power grid architecture Isolation and retention planning Feedthrough strategy Repeater insertion strategy Boundary and channel planning IO and Package Planning Define chip-level IO placement strategy. Collaborate with package teams on bump map optimization. Drive chip-package co-design activities. Optimize high-speed interface placement (PCIe, SerDes, C2C, DDR, Ethernet, etc.). Interconnect & Timing Planning Develop timing-driven floorplans. Define physical partitions and timing boundaries. Establish timing budgeting methodology across subsystems. Plan clock distribution architecture and clock-domain placement. Congestion, Power & Thermal Optimization Identify congestion hotspots and implement mitigation strategies. Drive early power estimation and thermal-aware floorplanning. Optimize placement for PPA convergence. Support EMIR-aware floorplan planning. Cross-Functional Collaboration Work closely with : Architecture teams RTL designers Physical Design teams DFT engineers Packaging teams Power methodology teams Verification teams Review subsystem floorplans and ensure full-chip integration readiness. Methodology and Automation Develop scripts and automation for floorplan generation and analysis. Drive methodology improvements and best practices. Enable scalable planning methodologies for next-generation SoCs. PREFERRED EXPERIENCE: 12+ years of ASIC/SoC Physical Design experience with strong expertise in Full-Chip Floorplanning. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Systems Design Engineer - Memory Enablement", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-10-01T13:56:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92698/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. Systems Design Engineer - Memory Enablement   THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.     THE PERSON:  You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.   KEY RESPONSIBILITIES:  Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues  Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements   PREFERRED EXPERIENCE:  Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools  Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++   Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment.   Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience.   Scripting language experience: Perl, Ruby, Makefile, shell preferred.   Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions.     ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SK3 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Principal Engineer- Digital Design", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-01T06:54:00.193000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000152847287-senior-principal-engineer-digital-design", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Job Summary:\nWe are seeking an experienced Senior Principal Engineer - Digital Design to lead the micro-architecture, design, and execution of next-generation UA Link Switch solutions within the Memory Interface Division (MID). The ideal candidate will bring deep expertise in high-speed digital system design and SoC development, with a proven track record delivering complex silicon products from architecture through production. \nThis role requires strong technical leadership in defining and implementing scalable switching and interconnect architectures that enable high-bandwidth, low-latency connectivity for AI, HPC, and memory-centric systems.\nKey Responsibilities:\nLead digital architecture and design activities for UA Link Switch products. \nDefine and drive microarchitecture, RTL design, integration, and performance optimization of high-speed switching fabrics and interconnect subsystems. \nCollaborate with architecture, verification, firmware, physical design, signal integrity, and system teams to ensure successful product execution. \nDrive end-to-end development from requirements definition through silicon bring-up and product qualification. \nProvide technical leadership across multiple engineering teams and mentor senior engineers. \nAnalyze performance, power, area, and scalability trade-offs to meet aggressive product goals. \nParticipate in architectural reviews, design audits, and technical roadmap planning. \nWork closely with ecosystem and standards teams to align product implementation with evolving industry standards. \n\nBachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or related discipline. \n15+ years of experience in digital ASIC/SoC development. \nStrong experience in one or more of the following areas:  \nHigh-speed digital design \nSoC architecture and integration \nSwitching fabric design \nNetwork-on-Chip (NoC) \nHigh-speed interconnects \nMemory subsystem design \nMicrocontroller-based systems \nHigh-bandwidth data movement architectures \nDeep understanding of RTL design using Verilog/SystemVerilog. \nExperience with modern ASIC development flows including synthesis, STA, low-power methodologies, and silicon bring-up. \nStrong debugging and performance analysis skills. \nDemonstrated ability to lead complex technical programs and influence cross-functional teams. \nPreferred Qualifications:\nPrior experience in: High-speed SerDes-based systems, Switching fabrics and packet processing architectures, Memory interface technologies, AI/HPC interconnect solutions, PCIe, CXL, Ethernet, UCIe, or related high-speed protocols. \nExperience developing large-scale SoCs for networking, compute, storage, or memory applications. \nUnderstanding of system-level architecture and board-level considerations for high-speed designs. \nExperience leading geographically distributed engineering teams. \nStrong communication and stakeholder management skills. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Sr Staff engineer- Hardware Development Motor Control Solutions", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-01T05:53:32.590000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000152831002-sr-staff-engineer-hardware-development-motor-control-solutions", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Role Overview :\nThis role is responsible for technical leadership and execution of hardware development for the RH850 Motor Control and Automotive Application Platform, with ownership of solution development spanning hardware and embedded firmware integration. \nThe Sr. Staff Engineer serves as a motor control and power conversion domain expert, driving hardware and solution architecture, design quality, and technical execution in collaboration with cross-functional teams. Success in this role requires strong technical expertise, a hands-on engineering mindset, and a commitment to delivering robust motor control solutions from concept through validation. \nKey Responsibilities :\nLead hardware architecture, design, and implementation for RH850 motor control and automotive application platforms, including development and validation of complete motor control solutions. \n\nDrive hardware technical decisions, ensuring robustness, scalability, cost effectiveness, and alignment with platform requirements. \n\nOwn hardware execution from concept, design, and validation through qualification and production readiness. \n\nCollaborate closely with systems, firmware/software, validation, and product engineering teams to ensure seamless hardware‑software integration and successful delivery of motor control solutions. \n\nSupport regulatory compliance, qualification, and Global Market Access (GMA) readiness for hardware deliverables. \n\nIdentify and mitigate hardware‑related technical risks, ensuring predictable execution and high quality. \n\nContribute to reference designs, development platforms, solution collaterals and documentation to enable broad customer adoption. \n\nAct as a technical mentor, influencing best practices and raising the bar for hardware design excellence. \n\nB. Tech/M. Tech in Electrical Engineering, Electronics, Computer Engineering, or related field with 12+ years of experience. \n\nHands‑on experience with Signal Integrity (SI) and Power Integrity (PI) analysis for high‑speed digital, mixed‑signal, and power‑dense designs. Applying SI/PI best practices in schematic design, PCB layout, stack‑up definition, decoupling strategies, and grounding. \n\nDeep expertise in embedded hardware design, including MCU‑based systems, motor control circuits, and power electronics, embedded firmware development/debugging for system integration, validation, and optimization \n\nProven experience delivering embedded hardware designs from concept through production. \n\nPreferred qualifications :\nExperience supporting embedded development platforms or reference designs with broad customer adoption. \n\nExposure to regulatory compliance and Global Market Access (GMA) requirements for global automotive markets. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Staff AMS Design Verification Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-10-01T05:47:17.457000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000152831319-senior-staff-ams-design-verification-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Senior project lead of a team of engineers in the tasks of guaranteeing specification compliance of analog & mixed signal design by means of advanced verification methodologies and concepts. It involves definition, deployment, and improvement of state-of-the-art verification methodologies.\nPrincipal Accountabilities:\nTake responsibility for design verification to achieve first pass silicon success and to ensure design meets performance, power, and timescale constraints.\nLead analog & mixed signal verification of complex integrated circuits or sub-systems.\nProvide a technical interface between AMS DV teams and any local contract DV resources.\nDevelop verification strategy for mixed signal IPs and implement the verification IP following object-oriented programming principles and methodologies including UVM.\nVerification planning, maintenance, feature extraction, verification tests, coverage and checker development.\nDevelop efficient, reusable state-of-the-art verification environments and testbench structures.\nInitiate and participate in review meetings with all functional disciplines such as analog & digital design teams, systems team, test & validation team, and other verification engineers.\nAble to debug the RTL for design intent and interface with cross-functional teams and collaboration in all verification related activities.\nMentor verification team and provide technical support for verification activities.\nDelegate project tasks appropriately, ensuring the entire team follows procedures and analog practices that are required by internal methodology guidelines.\nMake significant contribution into Renesas's Analog verification strategy, through representation at group management meetings, customer reviews and cross-site initiatives.\nKeep abreast of industry developments, driving continual improvements within team through effective change management.\nAny ad hoc tasks as deemed reasonable by your manager. \nKey Performance Measures:\nDevelop the technical and non-technical skillset of the team, ensuring clear career development and progression. Demonstrate effective performance management.\nEnsure budget is appropriately managed and resource is utilized to maximize success of deliverables.\nEnsure high quality deliverables in project through effective leadership and risk management.\nAppropriate planning and delegation of tasks to ensure project timescales and quality expectations are met.\nEnsure impactful dissemination of knowledge across teams.\nDriving strategic changes within analog function that positively impact the business - e.g., resource, cost and performance.\nEnsure effective team profiling, through succession planning, development, and strategic talent acquisition.\nDemonstrate elements of Spirit of Renesas in all aspects of work\nInstils culture of innovation, professionalism, and collaboration throughout team. \n\nQualifications\nDegree level qualification in electrical engineering, electronics, computer engineering, computer science, or equivalent.\nThe ideal candidate has an experience of 10+ years in advanced verification methodologies, owning the verification of complex digital and mixed signal designs.\nStrong fundamentals in analog and mixed signal circuit concepts and topologies.\nExperience working with mixed signal verification environment, simulation, and regression tools such as Cadence Virtuoso, xCelium, Incisive, vManager, IMC.\nAbility to read analog schematics and extract related main functionality.\nFamiliar with Verilog based RTL coding and ASIC design methodology.\nExpert in System Verilog for advanced verification methodologies such as assertions, constrained randomization, metric driven, and UVM.\nFamiliar with behavioral modelling of analog blocks using System Verilog (RNM) and Verilog AMS.\nExperience in modelling mixed signal blocks including biasing networks, power regulators, bandgaps, simple amplifiers, comparators, data converters, mixers, multiplexers, switches, power converters, etc.\nExperience of modelling power converters is desired.\nGood knowledge of UNIX shell scripting, Perl, and TCL scripting.\nProven experience in writing verification plans and test bench development, simulation and debugging.\nGeneral:\nConcise and proactive communication skills within a multi-site and multi-cultural environment\nAbility to persuade and influence others based on technical facts.\nAbility to interact with customers · Ability to successfully work with 3rd party contractors.\nTakes responsibility for solutions and makes them happen, self-motivated.\nLooks for continuous improvement in own and Renesas work practices.\nGood analytical and problem-solving skills.\nResults-oriented and able to deliver on-time under tight schedule pressure.\nAbility to propose innovative solutions.\nCross cultural awareness and sensitivity\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Principal Engineer - Digital Design", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-10-01T03:34:19+00:00", "url": "https://jobs.infineon.com/careers/job/563808972064498", "is_hardware": true, "platform": "eightfold", "jd_text": "The Senior Principal Engineer is a recognized as a technical lead and responsible for driving the architecture, design, and delivery of complex digital IP, ASIC, and SoC solutions. This role provides strategic technical direction across multiple programs, leads critical design initiatives, influences product road maps, and mentors engineering teams to achieve business and technology objectives.\n\nYour role\nKey responsibilities in your new role\n\nTechnical Architecture & Design Leadership\nDefine and drive SoC, subsystem, and IP architectures aligned with product and technology roadmaps.\nLead microarchitecture development for complex digital systems with a strong focus on scalability, power efficiency, performance, and manufacturability.\nOwn critical design decisions and guide architectural trade-offs across performance, power, area (PPA), reliability, and cost objectives.\nTranslate product requirements into robust architectural specifications and implementation plans.\nRTL Development & Design Execution\nLead RTL design and implementation using Verilog/System Verilog for complex digital subsystems and SoCs.\nDrive design quality through comprehensive reviews, sign-off processes, and engineering best practices.\nEnsure successful execution across synthesis, timing closure, linting, CDC/RDC analysis, power intent validation, DFT integration, and low-power implementation.\nPartner closely with verification teams to develop highly effective verification strategies and achieve first-pass silicon success.\nCross-Functional Collaboration\nWork closely with architecture, verification, physical design, firmware, software, validation, and product engineering teams throughout the development lifecycle.\nDrive technical alignment across global teams and serve as the primary technical authority for major design initiatives.\nSupport silicon bring-up, system integration, root-cause analysis, and post-silicon debugging activities.\nTechnical Leadership & Innovation\nLead and mentor senior engineers and technical teams, fostering a culture of technical excellence and innovation.\nEstablish engineering methodologies, design standards, quality frameworks, and development processes.\nDrive risk identification, mitigation planning, and technical decision-making across key projects.\nContribute to technology strategy, patent generation, and development of next-generation semiconductor solutions.\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor's, Master's, or Ph.D. in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.\n15+ years of industry experience in digital IC design and semiconductor product development.\nExtensive experience in architecture, microarchitecture, RTL design, and SoC/IP development.\nProven success delivering complex semiconductor products from architecture definition through silicon validation and production.\nExpert-level proficiency in Verilog/System Verilog and modern ASIC/SoC development flows\nStrong understanding of: \nPerformance, Power, and Area (PPA) optimisation\nClocking and reset architectures\nDesign-for-Test (DFT)\nLow-power design methodologies\nTiming closure and physical design considerations\nSemiconductor development and productization processes\nExperience leading technical reviews, design sign-offs, risk assessments, and root-cause investigations.\nStrong stakeholder management, communication, and collaboration skills.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "SoC Physical Design Engineer (Lead/Staff/Senior Staff) - HM PD team", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-01T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721321127", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nJob Description :\nBachelor's degree in Electrical Engineering with 6 to 15 years of experience in physical design.\nExperience managing complex Subsystem and Small team.\nExperience in synthesis, PnR, sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations.\n\nJob Requirement:\nExperience with demanding PPA requirement of complex sub-systeM/SOC, place and route, IP integration. \nExperience in low power design Implementation including UPF, multi-voltage domains, power gating. \nExperience with ASIC design flows and methodology of Physical design. \nUnderstanding of circuit design, device physics and deep sub-micron technology. Should have worked on multiple TO in advance technology nodes. \nPerson should also have good understanding of automation to drive the efforts to improve the PPA\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Engineer, SoC Performance", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-10-01T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721353066", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Systems Engineering\nGeneral Summary:\nJob Overview\nQualcomm's Multimedia System Performance team is responsible for system-level performance validation, analysis, and optimization across compute and mobile SoCs. The Engineer will work on pre-silicon and post-silicon platforms to validate multimedia use cases, analyze system performance metrics, debug bottlenecks, and collaborate with cross-functional teams to ensure performance goals are achieved.\n \nKey Responsibilities\nPerform system-level performance validation and analysis on pre-silicon (RUMI, emulation, simulation) and post-silicon platforms.\nDevelop and execute multimedia and system-level performance workloads, test vectors, and concurrency use cases.\nCollect, analyze, and debug performance metrics including bandwidth, latency, throughput, and QoS indicators.\nInvestigate performance bottlenecks across multimedia IPs, SMMU, cache, NoC, memory controller, DDR, power, and software domains.\nCollaborate with Architecture, Design, DV, Software, Power, and Multimedia teams to drive issue resolution and performance optimization.\nContribute to automation, performance sign-off activities, technical reviews, and project deliverables.\nMinimum Qualifications\nMaster's/Bachelor's degree in Electronics and Communications Engineering, Computer Science, or related field.\n1-2 years of experience in embedded systems, SoC validation, system performance, or a related domain.\nStrong analytical and system-level debugging skills.\nGood programming skills in C and familiarity with Python/Shell scripting.\nUnderstanding of Linux/Android OS fundamentals, scheduling, memory management, and kernel concepts.\nBasic understanding of SoC architecture, memory hierarchy, interconnects (NoC), and performance analysis.\nPreferred Qualifications\nExperience with pre-silicon platforms such as RUMI, emulation, FPGA, or simulation environments.\nExposure to multimedia subsystems including Display, Video, Camera, or Graphics.\nFamiliarity with performance profiling tools, counters, traces, and workload analysis.\nExperience debugging system-level performance issues in mobile or compute SoCs.\nLevel of Responsibility\nWorks under general supervision to execute assigned validation and debugging tasks.\nIndependently analyzes performance issues and collaborates with cross-functional teams to drive resolution.\nContributes to project execution, documentation, and performance sign-off activities.\n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "IC Verification Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-10-01", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/IC-Verification-Engineer_R027159-5", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nJob duties include:\n·       Build Test plans with all features for Block/Core/SoC and Write Functional Coverage for the features, participate in Reviews\n·       Write scalable and re-usable test benches, using the framework of the verification methodology\n·       Develop Pseudo-random tests to verify and get to full Functional Coverage\n·       Debug Regression failures, analyze Functional coverage gaps and improve tests to cover the gaps\n·       Document verification strategy including Test plans, Testbench, Random tests, etc.\n \nRequirements:\n·       Bachelor’s degree in electrical engineering or related degree with 5+ years relevant experience or master’s degree in electrical engineering or related degree with 3+ years relevant experience\n·       Must have working knowledge of System Verilog and Verification methodologies like UVM/VMM\n·       Should have good command of Object-Oriented Programming principles.\n·       Have experience writing Functional Coverage, pseudo random tests\n·       Knowledge of PCI Express protocol is a plus\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Design Architect", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-10-01", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Design-Architect_R56292", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nCadence HSV group is responsible for development of the Palladium and Protium emulation hardware and software system.  This includes developing design and verification components for complex protocols, to be used for emulation, for e.g. System Verilog/Verilog components and SW components written in C/C++ and SV-UVM.  It also requires development of system level RTL methodologies for stitching together large complex RTL designs in a scalable and reusable manner using and developing advanced tools including those that use AI and ML techniques. \n\nA critical element with building these SoC models is performance, encompassing performance of the AVIP, the underlying hardware-software design/integration, the compiler and the processor-based Palladium emulator hardware system. \n\n \n\nJob Description: \n\nWe are seeking a skilled HW and/or Design Engineering Architect to lead building representative SoC sub-systems using partner systems (ARM, others) and Cadence design and verification collateral. The main task is to build ARM CSS based systems using Cadence AVIPS and IP, port these to Palladium/Protium hardware and software and ensure functional correctness and make recommendations for performance improvements.  Experience with SoC design, verification, ARM bus protocols and performance analysis is required. Familiarity with or interest in developing new methodologies for SoC Integration and Verification Automation is a plus. \n\nSkills needed: \n\n15-18 years of hands-on HW RTL development and verification experience  \n\nEmulation experience on Palladium/Protium  \n\nExpertise in AMBA and CHI protocols \n\nKnowledge with design/integration of SoC systems \n\nExperience with performance analysis of complex hardware-software systems.  \n\nFamiliarity with standard communication protocols PCIe, CXL is a plus \n\nGood communication skills, excellent inter-personal skills, motivated individual  \n\nAbility to analyze and propose solutions to complex problems. \n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Process Development Engineer - Scribe Module Electrical Design", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-10-01", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018404", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\n This is a great opportunity to be part of an established team that's continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electronics, mobile computing and communications.\n\nAbout the Job:\n\nThe Scribe Development team is responsible for designing test structures for components which provide electrical and physical quality information to process development and manufacturing teams. The scribe engineer is responsible for developing the component test structures in conjunction with the process integration engineer, fab engineer, scribe build engineer, and layout designer. The engineer will be exposed to a variety of technologies and components from deep-submicron and analog CMOS to RF heterojunction bipolar and high-voltage SOI BiCMOS to Power BiCMOS/DMOS. This position provides an excellent opportunity to work with many teams within Analog Technology Development organization and beyond, including the process integration/development, layout, device characterization, fabrication, and scribe build teams.\n\n Specific responsibilities include, but are not limited to:\n\nDeveloping and documenting test structures to be instituted into silicon\n\nBuild automated scripts and/or programs to organize information\n\nPursue new ways to improve test structure design and verification methods\n\nIdentify opportunities to streamline the scribe development flow through scripting and/or developing standards\n\nIdentify potential opportunities of improvement\n\nParticipate in technical meetings when needed and develop new opportunities or new approaches that the scribe team can use in the future\n\nQualifications\nMinimum requirements: \nBachelor's degree in Electrical Engineering, Electrical and Computer Engineering, Computer Engineering, Mechanical Engineering, Materials Engineering, Physics, or related degree\nMinimum of 2 years of experience\nPreferred Qualifications:\nFamiliarity with basic semiconductor electrical fundamentals (through coursework or employment)\nFamiliarity with basic semiconductor device characterization (through coursework or employment)\nExperience or exposure to computers, scripting, Microsoft tools (Excel)\nExperience and proficiency in the following areas: Design environment (schematic & layout, Cadence preferred); basic programming experience with PERL, TCL/TK, C, Ruby, SKILL, and Unix Shell; and an aptitude for running various software scripts and utilities.\nDemonstrated strong analytical and problem solving skills\nDetail oriented with the ability to balance multiple critical path and time sensitive jobs on a regular basis.\nStrong verbal and written communication skills\nAbility to work in teams and collaborate effectively with people in different functions\nStrong time management skills that enable on-time project delivery\nDemonstrated ability to build strong, influential relationships \nAbility to work effectively in a fast-paced and rapidly changing environment\nAbility to take the initiative and drive for results\nSound decision-making capabilities and the ability to prioritize tasks and adapt accordingly\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Layout Engineer, Power Modules", "company": "onsemi", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-10-01", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506796", "is_hardware": true, "platform": "oracle", "jd_text": "We are looking for a hands-on Layout Engineer to join our AI-native product development team at onsemi. You will design silicon interposer and power-module layouts, and help turn that design practice into layout-authoring capabilities on our internal engineering platform.\n\nThe role covers the path from floorplan and PDK-based layout through verification and tapeout, with enough automation knowledge to define what an AI agent must be able to do at each step.\n\nYou will own selected module layouts, judge whether generated or edited layouts are electrically and physically sound, and work with software engineers on the tool actions, checks, and review flow the platform needs. AI experience is useful, but layout judgment and knowledge of the onsemi design flow are the core of the role.\n\n# LI-VS1\n\nResponsibilities\nKey Responsibilities\nDesign and edit power-module and silicon-interposer layouts, including die placement, power and signal routing, pads, and top-level assembly, using the relevant PDK and IP views.\nOwn assigned module layouts from floorplan through implementation, and keep layout decisions traceable across variants and revisions.\nRun and interpret DRC, LVS, and parasitic extraction, and use the results to correct layout before it moves downstream.\nPrepare layouts for design release: stream-out, database transfer, and the evidence expected at tapeout.\nUse KLayout for layout review and scripted edits, and help extend the same workflow to Cadence Virtuoso and the other tools used for power-module development.\nIdentify the tool actions an AI agent needs in order to create, edit, inspect, and check a layout, including required inputs, safe bounds, and expected outputs.\nValidate AI-produced layouts against the source design, PDK rules, connectivity, and known-good results. Reject output that is geometrically valid but electrically or physically wrong.\nContribute layout requirements to platform feature discussions, including candidate review, violation markup, net tracing, and revision comparison.\nCapture layout practices, layer and design-rule knowledge, and tapeout checks that currently depend on individual designers, so they can be reused by engineers and AI agents.\nWork with simulation, model-generation, and software engineers so layout, extraction, and model inputs stay consistent through the design flow.\n# LI-VS1\n\nQualifications\nRequired Skills\n4 to 8 years of hands-on IC or power-module layout, including released or tapeout-ready work.\nStrong Cadence Virtuoso Layout experience, including Layout XL, schematic-driven layout, and PDK or PCell-based design.\nPractical use of Siemens Calibre for DRC and LVS, and working knowledge of PEX or another parasitic-extraction flow.\nUnderstanding of how floorplan, placement, routing, pads, and top-level assembly affect resistance, loop inductance, current density, and thermal behavior in a power module.\nExperience taking a layout through stream-out and database transfer, with familiarity with Cliosoft SOS or an equivalent design-data system.\nAbility to inspect GDS or OASIS and make controlled edits with KLayout, Calibre DESIGNrev, or equivalent layout tooling.\nEnough Python or SKILL to automate repetitive layout, query, or checking tasks, and to explain a manual tool action clearly enough for a software engineer to implement it.\nCareful review of generated layout against design intent, design rules, and connectivity, including the judgment to reject a result that only looks correct.\nClear communication with layout, simulation, CAD, and software engineers, and comfort working from Linux design environments.\nPreferred Skills\nLayout experience with SiC or other wide-bandgap multi-die power modules, silicon interposers, or heterogeneous integration.\nFamiliarity with the onsemi power-module flow across die, interposer, package, and system, including Ansys Q3D, R3D, and thermal or mechanical checks driven by layout.\nExperience with Virtuoso SKILL, Python layout APIs, or batch verification flows.\nExposure to pads and ESD, bonding-diagram generation, reticle or database release, and fab or process feedback.\nInterest in AI-assisted layout, AI agent tool use, or reviewing AI-generated engineering output. Prior AI product experience is not required.\nExperience contributing design-rule, PDK, or layout-review knowledge to an internal platform or automation project.\n# LI-VS1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Senior Digital Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-10-01", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018257", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n In this position, you will be working on high-speed mixed-signal communication circuits using state-of-the art process technology, as well as be involved in the design of high performance digital circuits interfacing to leading edge analog circuitry as part of an overall system.\n\n Your responsibilities will include RTL coding, simulation, synthesis, timing closure, verification, evaluation, debugging of high-speed communication chips both at the circuit level and behavioral level.\n\n As a design engineer, you will prepare test methods and specifications, assist in preparation of application information, data sheets and demo boards. You will develop solutions to complex problems through assessment of various techniques and approaches. You will plan and organize work to ensure timely completion of many independent tasks with general instructions on routine tasks and with detailed instructions on new assignments.\n\n This position involves routine communication with a highly talented team of analog and digital design engineers to solve problems and present information as well as active participation in work groups, providing ideas and collaborative teamwork.\n\nQualifications\nMinimum requirements:\n\n5+ years of relevant experience\n\nA thorough understanding of digital logic design\n\nFamiliarity with the Verilog language and simulators\n\nA good understanding of analog functionality and exposure to analog IC design methods\n\nAbility to solve problems using a systematic approach\n\nPreferred qualifications:\n\nExperience with System Verilog\n\nDemonstrated strong analytical and problem solving skills\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nStrong time management skills that enable on-time project delivery\n\nDemonstrated ability to build strong, influential relationships\n\nAbility to work effectively in a fast-paced and rapidly changing environment\n\nAbility to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Verification Engineer - Media IP", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-10-01", "url": "https://careers.arm.com/job/bengaluru/verification-engineer-media-ip/33099/101393917664", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview\n \nThis position is an excellent opportunity for an experienced and highly motivated verification engineer to join the Arm Systems Media IP team! The team is responsible for the development of Image Signal Processors (ISPs), Display Processors, and Video codecs for deploying within Arm Compute Subsystems for various end markets, including automotive, IoT, and client market segments. Our intellectual property encompasses RTL, reference drivers, tools, and libraries, enabling our customers to build upon our work to create innovative products!\n \nYou will specify and develop new hardware verification testbenches for future generation hardware IP. You will improve existing testbenches to increase performance, quality and efficiency. You will also identify areas for improvement in processes and methodologies, then implement those changes to advance our best-practices for hardware verification. This is a new team with plenty of opportunities to shape its future, and your own growth and career progression.\nResponsibilities\nDepending on prior experience, the responsibilities of the role can include:\nVerification ownership of unit level or multi-unit hierarchy or alternatively verification lead of an overall IP (ISP, Display, Video).\nArchitecting verification IP and full verification environments.\nReviewing and assessing proposed design changes from a verification complexity point of view.\nAnalysis of data from simulation runs using machine learning and data science techniques to drive efficient bug discovery and debug.\nIdentify cross Media IP process or methodology improvement opportunities, implementing changes to advance hardware verification efficiency.\nClose collaboration with other Arm engineering teams leading to high quality IP that works well in a complete system.\nMentor & support other members of the team.\nRequired skills and experience:\n9+ years of experience in working with constrained-random verification including ownership of a suitably complex verification environment and creating testbenches.\nExperience developing reusable and scalable code whilst having in-depth knowledge of SV-UVM.\nStrong scripting skills – being able to develop scripts to support new and existing flows.\nSolid software engineering skills including understanding of object-oriented programming, data structures, and algorithms.\nFamiliar with the tools and processes for developing testbenches and finishing all aspects of the verification process.\nPrior technical and/or team leadership skills required for more senior positions.\n'Nice to Have' skills and Experience:\nTeam leadership and mentoring experience.\nMultiprocessing microarchitecture experience including knowledge of bus protocols (e.g. AMBA APB/AHB/AXI).\nPast experience in Formal Verification testbenches.\nExperience in video codec, ISP, or display projects, including knowledge of advanced image processing algorithms, such as local tone mapping, noise reduction, motion estimation, transform coding, etc.\nExperience of Functional Safety product development for the Automotive market (applying standards such as ISO 26262 and/or IEC 61508).\nExperience with Continuous Integration flows.\nIn Return:\nYou will get to utilise your engineering skills to build support for the technologies and influence millions of devices for years to come. You will be able to drive and bring your ideas to a wider audience, while building your technical leadership and influencing skills.\nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\n \n \n#LI-SA3\nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Principal Engineer Design", "company": "Infineon", "location": "Bangalore", "date_posted": "2026-09-30T14:25:17+00:00", "url": "https://jobs.infineon.com/careers/job/563808971628578", "is_hardware": true, "platform": "eightfold", "jd_text": "#WeAreIn to transform theoretical concepts into real hardware designs. Are you in?\n\nYour role\nKey responsibilities in your new role\nAs\nan engineer, Timing Closure, and Constraints Coding/Validation Engineer, you\nwill own the architectural timing intent, constraint hygiene, and complete\ntiming sign-off for complex, multi-million gate SoCs. You will drive multi-mode\nmulti-corner (MMMC) timing closure from block-level implementation up to\nfull-chip integration. A core focus of this role is using advanced optimization\ntools to fix critical setup, hold, transition and crosstalk violations across\nboth functional and complex DFT modes (Scan, At-Speed, MBIST etc).\n\nTiming Closure & ECO Sign-off: Lead and execute block-level and full-chip     flat/hierarchical timing closure across advanced process nodes. Generate     engineering change orders (ECOs) to fix setup, hold, max transition, and     signal integrity violations\nTool-Driven Optimization: Demonstrate expert mastery over automated ECO fixing     tools (Tweaker, PT DMSA/Primeclosure, Cadence Tempus) drive rapid     convergence of complex bottleneck violation\nMulti-Signoff STA Infrastructure: Architect, set up, and execute robust MMMC sign-off     environments using Synopsys PrimeTime (PT/PT-PX) and Cadence     Tempus. Ensure complete correlation across different timing engines\nHierarchical Constraint Management: Architect, generate, and maintain clean SDC files at     both the Block/IP level and the Full-Chip Top level. Manage constraint     promotion, demotion, and validation\nSignal Integrity & Noise Analysis: Strong understanding of crosstalk-induced noise,     glitch propagation, signal electromigration (Signal EM), and managing reconvergent     timing paths affected by crosstalk delay\nDFT Mode Timing Validation: Define, audit, and validate constraints across     multiple operational modes, specifically targeting Scan Shift &     Capture, At-Speed Testing, Memory BIST (MBIST), and Logic BIST (LBIST)     concurrent execution modes\nCross-Functional Leadership: Collaborate with DFT Engineers to resolve test mode     constraints, RTL Designers to fix structural CDC/RDC violations, and     P&R Teams to guide placement, clock-tree synthesis (CTS), and routing     optimization\nAutomation & Flow Development: Write advanced, production-grade Tcl scripts     for PrimeTime/Tempus environments\nUtilize Python or Perl to     build regression suites, analyze timing violations, and compare SDC     variations\n \n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor’s or Master’s degree in Electrical/Electronics Engineering, VLSI, Microelectronics, or a related field.\nMinimum 13+ years of relavent experience in STA  full chip \nCore Tool Expertise (Mandatory):Sign-off STA: Synopsys PrimeTime (PT/PT-PX) and Cadence Tempus.\n Timing Closure / ECO: Cadence Tempus, Synopsys PrimeTime/PrimeClosure & Tweaker\n Constraints Validation: Synopsys TCM/GCA, Ausdia TimeVision, SpyGlass Constraints, or Cadence CCD\n\nRun strict constraints verification using  industry-standard tools (Synopsys TCM, SpyGlass Constraints, or Cadence CCD) to eliminate unconstrained paths, incorrect     clock-gating checks, and conflicting case analysis settings between     functional and DFT model\nHands-on experience reading, writing, and parsing Unified Power Format (UPF) constraints to validate low-power design architectures (e.g., power-gating, isolation cells, retention registers,     and level-shifter placement\nFamiliarity with Logic Equivalency Checking using industry tools like Cadence Conformal LEC or Synopsys Formality  to verify that optimization/ECO steps maintain  functional equivalence \nDeep understanding of advanced node variation models (POCV/LVF),  temperature inversion, crosstalk/noise analysis, and hierarchical     top-level clock distribution networks\nSolid comprehension of DFT architecture, test clock structures,     multiplexer-heavy clock networks, and asynchronously driven test logic\nExpert proficiency in Tcl (highly critical for runtime timing script customization) and Python/Perl for automated data mining and constraint auditing\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nGowri Shenoy\n\nhttps://www.linkedin.com/in/gowri-shenoy-33894217/", "jd_status": "stored"}, {"title": "Principal Engineer Design-Synthesis, LEC & CLP", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-09-30T13:32:54+00:00", "url": "https://jobs.infineon.com/careers/job/563808971873735", "is_hardware": true, "platform": "eightfold", "jd_text": "#WeAreIn to transform theoretical concepts into real hardware designs. Are you in?\nWe are looking for an experienced RTL2GDS Frontend expert with 10+ years of hands-on experience in Synthesis, LEC, and Low Power Verification (CLP) for complex SoC designs. \n\nYour role\nKey responsibilities in your new role\n\nDevelop, enhance, and maintain front-end design flows and automation frameworks to improve productivity and design quality\n\nDrive synthesis convergence and support design optimization across advanced technology nodes\nPerform design bring-up, debug, and issue resolution throughout the implementation cycle\nExecute and close Logic Equivalence Check (LEC) and low-power verification activities\nCollaborate closely with RTL, STA, DFT, and Physical Design (PD) teams to ensure seamless design integration and execution\nAnalyze and debug design, flow, and tool-related issues, providing timely and scalable solutions\nDevelop reusable methodologies, automation solutions, and best practices to improve design efficiency and scalability\nSupport design signoff activities and ensure adherence to project timelines and quality goals\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Microelectronics, or a related field\n10+ years of experience in RTL-to-GDS (RTL2GDS) front-end implementation for complex SoC designs\nStrong technical expertise across the complete RTL2GDS design flow, with a deep understanding of front-end implementation methodologies\nHands-on experience in Synthesis, LEC, and Low Power Verification (CLP) for large-scale and complex SoC projects\nProven ability to proactively manage cross-functional dependencies, resolve technical conflicts, and effectively prioritize issues across multiple stakeholders\nExtensive experience with both Cadence (Genus, Conformal LEC/CLP) and Synopsys (Design Compiler/Fusion Compiler, Formality) tool flows\nSolid understanding of MCMM methodologies, UPF/CPF, timing constraints, power intent verification, and advanced-node implementation flows\nStrong programming and automation skills using Tcl, Python, and/or Perl, with demonstrated expertise in developing scalable and reusable automation solutions\nExcellent debugging and problem-solving skills, with the ability to drive synthesis convergence, closure activities, and design quality improvements\nExperience working closely with STA, DFT, Physical Design (PD), and RTL teams to ensure seamless project execution and successful tape-out\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nGowri Shenoy \n\nhttps://www.linkedin.com/in/gowri-shenoy-33894217/", "jd_status": "stored"}, {"title": "Staff Test Engineer", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-09-30T12:27:26+00:00", "url": "https://jobs.infineon.com/careers/job/563808972023553", "is_hardware": true, "platform": "eightfold", "jd_text": "Join us in shaping the future of connected devices by developing advanced test solutions for next-generation IoT products. Work on silicon bring-up, ATE hardware and test program development, and Digital, Mixed-Signal, PMU, NVM, and RF technologies. Collaborate with global engineering teams to deliver high-quality, cost-efficient semiconductor solutions for volume production.\n\nYour role\nKey responsibilities in your new role\n\nDevelop, implement, and maintain comprehensive test plans for next-generation IoT devices.\nDesign, validate, debug, and improve ATE (Automated Test Equipment) hardware to ensure robust and reliable testing.\nPerform silicon bring-up and debug activities on ATE platforms for new semiconductor products.\nDrive high-quality, cost-efficient test solutions suitable for volume manufacturing.\nCoordinate and oversee test hardware and software activities with internal teams and external test houses.\nDevelop, optimize, release, and support production test programs at offshore manufacturing sites.\nProvide technical expertise and troubleshooting support related to semiconductor test engineering for internal and external stakeholders.\nDevelop and debug characterization and production test programs for SoC connectivity products incorporating Digital, Mixed-Signal, PMU, NVM, and RF blocks.\nCollaborate closely with cross-functional teams including IP Design, Applications Engineering, DFT, Product Engineering, and Test Engineering across global development sites.\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical & Electronics Engineering (EEE), or related disciplines.\nRequired Skills & Experience\nStrong understanding of semiconductor fundamentals, including analog and digital circuits, device physics, and circuit theory.\nSound knowledge of Design-for-Test (DFT) methodologies, including ATPG and PMU-related blocks such as BUCLK and LDO trimming techniques.\nHands-on experience with semiconductor testing methodologies using Teradyne UltraFLEX RF platforms; experience with UltraFLEX+ is a strong advantage.\nProficiency in developing, debugging, and optimizing ATE test programs and resolving hardware-related issues.\nStrong programming and scripting skills in languages such as Python, Perl, C, C++, Java, or Visual Basic.\nFamiliarity with UNIX/Linux operating systems, shell scripting, and command-line environments.\nExcellent problem-solving, analytical, and debugging capabilities.\nStrong verbal and written communication skills.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nAnand Rawal", "jd_status": "stored"}, {"title": "Principal Logic Design Engineer", "company": "Astera Labs", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-30T02:27:58-04:00", "url": "https://job-boards.greenhouse.io/asteralabs/jobs/4735008005", "is_hardware": true, "platform": "greenhouse", "jd_text": "Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\n\nPrincipal Logic Design Engineer \n\nExperience - 10+ years \n\nJob Summary \n\nWe are seeking a Principal Logic Design Engineer with deep expertise in micro-architecture and RTL design to lead the development of complex IPs/subsystems. The candidate will provide technical ownership across architecture, microarchitecture, RTL implementation, integration, and silicon bring-up. \n\nKey Responsibilities \n\nLead RTL/microarchitecture development for complex connectivity IP/subsystems. \n\nTranslate specifications and system requirements into robust hardware architecture. \n\nDesign high-performance and scalable logic for controllers/subsystems. \n\nWork across connectivity IP / subsystem layers including Transaction, Data Link, and Physical interface integration as applicable to the role. \n\nDevelop and review RTL using SystemVerilog/Verilog. \n\nDevelop robust mechanisms for flow control, ordering, buffering, arbitration, error handling, and reliability. \n\n \n\nDrive performance, latency, area, and power optimization. \n\nCollaborate with verification teams to develop verification strategies and debug complex failures. \n\nWork with SoC integration and physical design teams to ensure successful implementation. \n\nLead technical reviews and mentor senior engineers. \n\nSupport post-silicon debug and root-cause analysis. \n\nRequired Skills \n\nExtensive experience in complex connectivity IPs such as PCIE, UALink, Ethernet, CXL, UCIe. \n\nStrong RTL design experience using SystemVerilog/Verilog. \n\nDeep knowledge of PCIe architecture and protocol. \n\nStrong understanding of high-speed data paths, FIFOs, arbitration, flow control, and error handling. \n\nExperience with simulation, lint, CDC, synthesis, and timing considerations. \n\nStrong debugging and problem-solving skills. \n\nPreferred \n\nExperience of working in switching silicon. \n\nExperience of working on entire cycle from concept to silicon production. \n\n \nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.", "jd_status": "stored"}, {"title": "Senior Principal Physical Design Engineer", "company": "Astera Labs", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-30T02:22:00-04:00", "url": "https://job-boards.greenhouse.io/asteralabs/jobs/4736140005", "is_hardware": true, "platform": "greenhouse", "jd_text": "Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\n\nAstera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.  \n\nBasic qualifications:\n\nStrong academic and technical background in electrical engineering. A Bachelor’s degree in EE / Computer is required, and a Master’s degree is preferred.\n\n≥6 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.\n\nProfessional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. \n\nEntrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!\n\nRequired experience:\n\nHands-on and thorough knowledge of synthesis, place and route, CTS, extraction timing analysis/STA, Physical Verification and other backend tools and methodologies for technologies 16nm or less, preferably 7nm or less.\n\nProven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level.\n\nFull chip or block level ownership from architecture to GDSII, driving multiple complex designs to production.\n\nExperience with Cadence and/or Synopsys physical design tools/flows.\n\nFamiliarity and working knowledge of System Verilog/Verilog.\n\nExperience with DFT tools and techniques.\n\nExperience in working with IP vendors for both RTL and hard-mac blocks.\n\nGood scripting skills in python or Perl\n\nPreferred :\n\nGood knowledge of design for test (DFT), stuck-at and transition scan test insertion.\n\nFamiliarity with DFT test coverage and debug.\n\nFamiliarity with ECO methodologies and tools.\n\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.", "jd_status": "stored"}, {"title": "Physical Verification Engineer (Lead/Staff/Sr Staff) - Custom Silicon Group", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-30T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720951914", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nExperience: 5 to 15 Years\n\nKey ResponsibilitiesDrive Physical Verification sign-off activities including DRC, LVS, Antenna, ERC, PERC, ESD, and related verification checks for advanced technology nodes.\nCollaborate closely with Physical Design, Custom Layout, and Foundry teams to ensure clean sign-off and physical convergence.\nDebug and resolve physical verification violations while driving closure to tape-out.\nSupport methodology development, automation, and flow enhancements for sign-off quality and productivity.\nParticipate in floorplanning, power planning, and PDN reviews to ensure robust physical implementation.\nRequired SkillsStrong experience with Physical Verification sign-off flows and tools.\nGood understanding of PDK concepts, SVRF rule decks, Calibre, and ICV.\nHands-on experience with Innovus, ICC2, Fusion Compiler, or equivalent implementation tools.\nSolid understanding of Physical Design implementation flow, layouts, and backend design methodologies.\nExperience working on advanced technology nodes such as 2nm, 3nm, 5nm, 7nm, or 10nm.\nFamiliarity with Tech LEF, Design Rules, and Foundry PDKs.\nStrong debugging and problem-solving skills in sign-off environments.\nPreferred QualificationsExperience in Floorplanning, Power Planning, and PDN design.\nTeam leadership or people management experience.\nAutomation skills using TCL, Perl, or scripting languages.\nExposure to custom IC design flows and mixed-signal/SOC environments.\nNice to HaveExperience driving physical convergence across multiple blocks or full-chip designs.\nExposure to ESD reliability analysis and advanced PERC methodologies.\nExperience mentoring junior engineers and leading technical initiatives.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "AMS Silicon Validation Engineer, Senior", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-30T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721322570", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field.\n\nExperience: 2 to 4 years\nThe candidate should have good understanding of analog and mixed signal circuits with experience in high-speed links such as DDR PHY and/or Serdes\nExperienced in post silicon bring-up and validation for Mixed Signal PHYs.\nPre-silicon experience in emulation is desirable.\nExperience with high-speed digital circuits, memories and lab. testing is desirable\nExperience with Tx/Rx equalization techniques and circuits like de-emphasis, CTLE, DFE is desirable\nKnowledge of DDR protocols is desirable \nAbility to work in a dynamic environment and interact well with cross-functional teams such as design, boards, ATE etc.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "DDR PHY Senior Lead Digital Design Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-30T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721322573", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\n\nRole Overview\nWe are seeking a motivated and technically strong DDR PHY Digital Design Engineer to join our team working on next-generation memory interface IPs. The candidate will be responsible for the architecture, RTL implementation, verification support, synthesis, low-power design, DFT, and silicon bring-up of high-performance DDR PHY solutions used in leading-edge SoC products.\n \nResponsibilities\nDesign and develop digital components of high-performance DDR PHY for LPDDR/DDR memory interfaces.\nParticipate in micro-architecture definition, RTL coding, integration, and debug of complex digital IPs.\nDrive RTL quality and signoff through lint, clock-domain crossing (CDC), reset-domain crossing (RDC), low-power, and design rule checks.\nCollaborate with the functional verification team to develop verification plans, review coverage closure, and debug design issues.\nDevelop synthesis and timing constraints, analyze timing reports, and deliver high-quality netlists for physical design implementation.\nCreate and maintain UPF-based low-power intent and perform equivalence checking, and low-power signoff.\nImplement and validate Design-for-Test (DFT) features, support scan insertion, ATPG generation, and optimize stuck-at and transition fault coverage.\nWork closely with physical design, STA, DFT, verification, and SoC integration teams to achieve project milestones and quality targets.\nSupport pre-silicon and post-silicon bring-up, characterization, debug, and issue resolution across multiple product programs.\nContribute to methodology improvements, automation, and design flow enhancements to improve engineering productivity and quality.\nRequired Qualifications\nB.Tech/M.Tech in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.\n5+ years of experience in digital design and front-end implementation of complex ASIC/SoC/IP designs.\nStrong understanding of digital design fundamentals, RTL development using Verilog/SystemVerilog, and micro-architecture concepts.\nHands-on experience with front-end design flows, including:Lint\nCDC/RDC\nLow-power verification\nSynthesis\nStatic Timing Analysis (STA)\nDesign-for-Test (DFT)\n\nFamiliarity with industry-standard EDA tools used for RTL design, verification, synthesis, and timing closure.\nStrong debugging and problem-solving skills.\nExcellent teamwork, communication, and collaboration skills with global engineering teams.\nPreferred Qualifications\nExperience in DDR/LPDDR PHY, high-speed interface, or mixed-signal IP development.\nKnowledge of UPF, power-aware design methodologies, and low-power architecture techniques.\nFamiliarity with scan insertion, ATPG, and silicon debug activities.\nExposure to post-silicon bring-up, validation, and characterization.\nExperience working across multi-functional teams, including verification, physical design, DFT, firmware, and system engineering.\nWhat You'll Work On\nLPDDR5/LPDDR6 and future-generation memory PHY solutions.\nHigh-performance, low-power digital architectures for mobile, compute, XR, automotive, and AI platforms.\nState-of-the-art design methodologies spanning RTL design through silicon validation.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Digital EM/IR Engineer (Lead/Staff/ Sr Staff) - Custom Silicon Group", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-30T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720699935", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nSign-off Ownership:Own full-chip and block-level static/dynamic IR drop and signal/power electromigration sign-off. \nOwn die plus interposer analysis, die plus interposer plus pkg analysis.\nShould have expertise in handling vector based IR signoff and vector less signoff in different modes\nDrive root-cause debugging for voltage, EM violations and collaborate with physical design (PD) teams on floorplanning and power grid fixes.\nOwn power estimation and signoff on Primepower and Joules on different use cases\nShould have knowledge of CPM generation on different use cases\nUnderstand Mixed signal IP requirements and derive metrics for signoff\n \n\nFlow Development:Define and maintain robust EMIR methodologies using standard EDA tools like Ansys RedHawk-SC, or Cadence Voltus. \nWork on enhancing flow and methods for faster convergence and covering critical gaps with changing signoff trends.\n\nCross functional: Support chip-package-system (CPS) integration and work alongside silicon package and interposer teams. \nWork closely with PnR on fixes needed for EMIR violations and left shift strategy for correct by construction methods\nWork with DFT teams to understand impact of DFT strategy on EMIR, assess/fix impact on IR from DFT patterns, provide guidelines for toggling activity in DFT modes, provide power estimation to ATE and board testing teams.\nWork proactively with EDA vendors to get resolution on Tool issues, track critical issues impacting project, initiate and track topics of long term and future interests.\nWork with flow teams to integrate new methods and fixes in to the flow that are impacting ongoing projects. Initiate work flows for long term and future interests.\n\nLeadership & Management Responsibilities\nTeam Guidance: Direct daily task allocation, monitor metrics, and manage project schedules to meet tapeout milestones.\nMentorship: Train junior and mid-level engineers in advanced-node power integrity challenges and scripting (TCL, Python).\nCross-Functional Collaboration: Partner with timing (STA), physical design, package/interposer and analog/SerDes integration groups to clear design bottlenecks.\nStakeholder Reporting: Communicate technical risks, execution progress, and mitigation paths to upper management on a regular basis.\nQualifications & Requirements\nExperience: 5+ years of relevant semiconductor industry experience, with proven background in power integrity sign-off.\nTechnical Skills: Advanced expertise in RedHawk_SC, Voltus, PTPX alongside strong scripting proficiency (Python/TCL). Should have deep knowledge in EMIR domain. Should have good knowledge of adjacent domains like STA and inter-operation with those domains.\nEducation: Bachelor’s or Master’s degree in Electrical Engineering, VLSI, or a related electronics discipline. \n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "DDR PHY Senior Lead Design Verification Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-30T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718646772", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nExperienced DDR-PHY Design Verification engineer to work on next generation System-on-chip (SoC) for smartphones, tablets, laptops.\n\nJob responsibilities:\n \n5+ years of experience in Design Verification of complex IPs. Hands-on experience and very good understanding of DDRPHY architecture, DFI protocol and Jedec standards for latest Gens.\nOwnership of DV test bench and other associated collaterals (Checkers, Scoreboards, Assertion, Functional Coverage).\nDevelop test plan and test cases to cover design feature set, follow up with stake holders at different levels of test bench.\nWork closely with Design, Subsystem/SOC, SVE teams on failure debugs, code/functional coverage closure, as well as DSF.\nDebug of regression signatures and identifying bug fixes.\nResponsible for Quality sign-off and required documentation.\nDebug and root cause SS/SOC/post silicon issues in collaboration with Design teams.\nExpertise in IP level /Sub-system level verification.\nUnderstanding of standard bus protocol like AHB, AXI protocols would be a plus.\n \n \nRequired skillset:\n \nExperience in verification and general computational logic design/verification concepts.\nExpertise in Verilog/System Verilog and UVM/OVM.\nFunctional Verification, Coverage, Gate Simulation (GLS), Low Power Verification, Formal Verification \nStrong debugging, Analytical and problem-solving skills.\nExperience in developing Monitors, Scoreboards, Sequencers that utilize System Verilog, and UVM methodologies for complex scenario generation and verification of DUT.\nExperience in Scripting languages like Perl /Tcl would be a plus.\nPost-si bring-up and HW-SW debug experience would be a plus.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "DSP / NPU Sr Engineer Design Verification Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-30T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446717347331", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nJob Summary:          \n·         Position for 12+ years of experience in design verification of complex Qualcomm propriety DSP/NPU IP\n·         DSP team is responsible for delivering high-performance DSP/NPU cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space, AI, Automotive and more.\n·         Qualcomm is one of the largest fabless semiconductor design companies in the world, generating over $35 Billion in annual revenues from chipsets and royalties from intellectual property.\n\n Job Responsibilities: \n·         Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power,  post silicon and back-end teams.\n·         Implement and improve System Verilog/UVM Testbench Architecture.\n·         Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency.\n·         Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals.\n·         Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails and bugs.\n·         Complete all required verification activities at IP level and ensure high quality commercial success of our products.\n·         Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis.\n·         Responsible gate level simulation bring-up, gate level verification with timing simulations.\n·         Responsible for power aware RTL verification and gate level simulation.\n\nSkillset/Experience:          \n·         12+  years experience in processor/ASIC design verification\n·         Solid background and understanding of Digital Design, Processor Architecture , Processor Verification and Power aware verification.\n·         Expertise in System Verilog Testbench Architecture and implementation.\n·         Experience in writing C based and assembly level testcases is preferred.\n·         Exposure to power aware implementation and verification using UPF is a plus.\n·         Experience with advanced verification techniques such as formal and assertions is a plus.\n·         Gate-Level Simulation and Debug — 0-delay, timing annotated  and power aware.\n·         Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence .\n·         Scripting/Automation Skills — Perl, Python, Shell, Make file TCI .\n·         Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts.\n·         Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred.\n·         Experience in verification of Processor subsystems is preferred.\n·         Experience in creating validation suite and building automation.               \n·         Should have excellent inter-personal and communication skills.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Manager - Design Engineering", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-09-30", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Senior-Manager---Design-Engineering_R3953-26", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nMicrochip’s Communications Business Unit (CBU) develops high-performance networking, connectivity, and edge compute semiconductor solutions that power communications infrastructure, data centers, automotive systems, aerospace and defense platforms, and industrial applications. Our global team works across the full product lifecycle to deliver innovative products that enable the world’s most demanding connected systems. \n\nThe CBU Product Development team is engaged through the full device R&D cycle from concept, design and implementation stages. Once a prototype is available, we support embedded software development and system validation lab testing through to mass-market production release. We are an experienced chip team working with the latest semiconductor development tools and methodologies in advanced process technologies to develop state-of-the-art network devices.\n\nWe are seeking a senior design manager in India for a rare opportunity to help build something foundational. We are looking for a recognized hands-on technical leader who can shape architecture, guide complex semiconductor development programs, solve challenging engineering problems, and make critical technical decisions, while being able to attract exceptional talent, mentor engineers, and build a high-performing organization from the ground up. This is a unique opportunity to help establish and scale CBU’s Silicon Design Center in India while defining both the technical direction and engineering culture of the organization.\n\nAs a Senior Manager in the CBU Product Development team you will be responsible for the technical leadership of communication semiconductor devices or subsystems. You will collaborate with Project Management, Marketing and Application Engineers, Chip Architects, Subsystem Leads and Verification Teams to deliver complex designs in a friendly, challenging and professional environment. As an engineering manager, you will have leadership responsibilities that may include direct reports and/or contractors. You will a have the opportunity to enhance and grow CBU’s technical capabilities through mentorship, coaching and recruitment.\n\nResponsibilities may include:\n\nStrategic Leadership and Talent & Team Management:Lead and develop a team of 20+ engineers;\nManage resource allocation, performance reviews, and technical career growth.\n\nTechnical Execution:Drive end-to-end RTL design execution, from concept through to architecture, coding, verification, synthesis, sign-off, and silicon bring-up support;\nServing as a technical authority for digital design, ensuring high standards in quality, performance, power, and area;\nResolving complex, cross-domain design and EDA tool challenges impacting schedule or silicon quality. \n\nMethodology Innovation: Drive the adoption of advanced techniques through different phases of silicon development: from design, verification, to validation and release to production;\nContinuously improve efficiency through automation, scripting, and the integration of AI-driven tools.\n\nCross-Functional Collaboration: Partner closely with Physical Design, Software, Product Engineering, Validation and other teams/vendors to resolve complex integration issues and bottlenecks.\n\nRequirements/Qualifications:\n\nEducation: Degree in EE (Bachelor’s or higher)\nWork experience: 14+ years of experience is preferred\nProven leadership skills with strong coaching and mentoring temperament\nAbility to think both strategically and tactically\nDeep understanding of all phases of silicon development with expertise in RTL design and verification.\nStrong understanding of functional verification flows and environments.\nProven success delivering multiple complex tape-outs in high-performance silicon.\nDeep hands-on experience with Lint, CDC, formal verification, logic synthesis, and static timing analysis along with physical design interactions.\nSolid experience with low-power design methodologies and flows.\nWorking knowledge of DFT, including scan, testability considerations, and DFT sign-off interactions.\nExperience with Synopsys or Cadence tools for synthesis, verification or STA (an asset)\nExperience with 28nm and smaller silicon process technologies (an asset)\nHands-on experience with ASIC EDA tools/environment is an asset.\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Modeling Design, Staff Engineer", "company": "Lattice", "location": "Pune, India", "date_posted": "2026-09-30", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Pune-India/Modeling-Design--Staff-Engineer_R-103324", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nJob Summary:  As a Modeling Design Staff Engineer, you will be responsible for creation and validation of models used for Lattice FPGAs, ensuring their accuracy and performance.  You will work closely with design, architecture and other development teams to ensure the accuracy and reliability of our models.\n\nKey Responsibilities:\n\nDevelop and validate models for analog, digital, and mixed-signal circuits.\nUtilize simulation tools such as Verilog, VHDL, SystemVerilog, or similar, to perform digital circuit analysis.\nProvide technical leadership and mentorship to a team of circuit modeling engineers.\nCollaborate with design engineers to understand circuit requirements and specifications.\nCollaborate with internal customers/consumers of the models to assure their needs are comprehended and objectives are met.\nAnalyze simulation results and provide feedback to improve models and model performance.\nOptimize circuit models for performance, accuracy, and efficiency.\nDocument modeling processes, assumptions, and results for internal and external stakeholders.\nStay updated with the latest advancements in circuit modeling techniques and tools.\n\nQualifications:\nBachelor’s or Master’s degree in Electrical Engineering with 5+ years of experience.\nProven experience in circuit modeling and simulation.\nProficiency in using circuit simulation tools such as SPICE, Verilog, VHDL, System Verilog, or similar.\nUnderstanding of analog, digital, and mixed-signal circuit design principles.\nSkill in modeling with SystemVerilog and higher level modeling with System C.\nExcellent analytical and problem-solving abilities.\nExcellent communication and collaboration skills.\nExperience with data analysis and visualization tools is a plus.\n\n#LI-DNP\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Principal Foundry Engineer", "company": "Lattice", "location": "Austin, TX", "date_posted": "2026-09-30", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Austin-TX/Principal-Foundry-Engineer_R-103272", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nAbout the Role\n\nLattice Semiconductor is seeking a Staff/Principal Foundry Engineer to lead and manage the transfer and qualification of our products on Samsung 28FDS FD-SOI process technology. This role requires strong semiconductor process knowledge, device physics understanding, and the ability to drive cross-functional programs across Lattice internal teams. The ideal candidate operates with a high degree of autonomy, will serve as the primary interface between Lattice's distributed foundry engineering teams (US and Taiwan) and Samsung's Austin fab, ensuring process quality, yield, and reliability standards are met.\n\nKey Responsibilities\n\nFoundry Engagement & Program Management\n\nLead technical engagement with Samsung Austin (primary) and Samsung Korea teams; coordinate with Lattice foundry engineers across US and Taiwan sites\nDrive foundry suppliers to meet company yield, quality, and reliability goals\nDefine and maintain program plans, milestone trackers, and risk registers across transfer and sustaining phases\nProvide clear, concise status reporting to leadership and cross-functional stakeholders\nTravel regularly to Samsung Austin fab\n\nProcess Transfer & Product Qualification\n\nOwn end-to-end process transfer and qualification, including baseline qualification, process corner validation, and PVT characterization\nLead product qualification activities in collaboration with the Reliability team\nDrive lot starts, wafer splits, and process window experiments; perform WAT analysis to validate process baselines\nEvaluate and qualify Samsung-initiated process changes, material substitutions, or equipment updates for product impact\nSupport new product ramp-up activities to volume production\n\nYield Engineering & Sustaining\n\nOwn post-transfer sustaining activities including yield improvement, process window optimization, and SPC monitoring on production silicon\nAnalyze WAT, inline, and final test data to identify process drift, yield loss mechanisms, and reliability risks; drive root cause and corrective action with Samsung process owners\nPerform product process corner and design window studies to optimize process targets\nCollaborate with Design, Product Test, and Failure Analysis teams to debug and root cause systematic yield issues\n\nFailure Analysis & Quality\n\nCoordinate failure analysis efforts across internal teams and Samsung FA resources\nPerform product failure diagnosis for yield debug and failure localization, including bitmap analysis\nSupport customer-facing quality escalations including 8D and CAR responses\n\nData Analysis & Reporting\n\nApply advanced analytics and statistical methodologies to maximize yields, lower costs, and prevent quality excursions\nInterface with cross-functional teams including R&D, Quality and Reliability, Manufacturing Test, Product Engineering, and Operations to deliver high-quality products and meet key metrics\n \nRequired Qualifications\n \nM.S. in Electrical Engineering, Materials Science, or related discipline or above\n10+ years of semiconductor process or foundry engineering experience, prior experience in a fabless semiconductor company managing an external foundry relationship a plus\nHands-on experience with advanced CMOS or FD-SOI process technologies at 28nm node or below, including strong understanding of device physics, fabrication processes, and their interactions with circuit behavior\nStrong knowledge of FD-SOI device physics including back-bias tuning, body effects, leakage, and variability\nExperience with product qualification and reliability testing (HTOL, TDDB, EM); familiarity with AEC-Q100 for automotive applications\nDemonstrated experience with WAT parametric analysis, yield engineering, SPC, and failure diagnosis and analysis coordination; familiarity with technology design rules, DFM, and layout-based yield analysis tools\nUnderstanding of semiconductor product test flow and ability to engage effectively with manufacturing test and product engineering teams\nExperience leading multi-year foundry transfer or qualification programs with cross-functional ownership; ability to manage multiple concurrent programs and priorities\nExcellent written and verbal communication skills; ability to convey technical concepts clearly to both technical and business audiences\n\n \nPreferred Qualifications\n \nDirect experience with Samsung 28FDS FD-SOI process technology\nExperience working with Samsung Foundry engineering or process teams\nPrior Failure Analysis experience\nProficiency in JMP, Python, or equivalent tools for large-scale data analysis\nFamiliarity with Lattice FPGA architecture or programmable logic products\nIn addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! \nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nUnited States of AmericaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.\n\nAs an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.", "jd_status": "stored"}, {"title": "Principal Synthesis, STA  Engineer", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-09-30", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Principal-Physical-Design-Engineer_R256069", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nP5 Synthesis & STA Engineer\n \nAbout the Role\nAs a P5 Synthesis & STA Engineer, you will provide technical leadership for Synthesis, STA, and timing closure of complex high-performance SoCs with large digital and analog interfaces.\nYou will drive full-chip timing analysis and closure for complex, multi-GHz SoC, establish robust top-down closure methodologies, and solve complex QoR challenges spanning RTL, synthesis, constraints, clocking, and physical implementation. The role requires deep hands-on expertise combined with the ability to influence implementation strategy, introduce industry best practices, drive methodology improvements, and mentor engineers into leadership roles.\n \n \nKey Responsibilities\nLead and own Synthesis and STA closure for complex, high-performance, multi-GHz SoCs across IP, subsystem, partition, and full-chip levels.\nDevelop, validate, and review complex timing constraints spanning IP, subsystem, partition, and full-chip hierarchies.\nDrive full-chip timing signoff across multi-mode, multi-corner scenarios and establish a robust top-down timing closure methodology, driving constraints, budgets, interface timing, and convergence from full-chip to subsystem and partition levels.\nDemonstrate strong expertise in AOCV/SOCV methodologies, variation-aware timing analysis, and advanced-node timing signoff.\nDrive top-level clock planning and balancing across partitions and interfaces, working with Physical Design teams to optimize clock topology, implementation, and routing.\nDemonstrate strong understanding of design partitioning and hierarchical implementation, including partition boundaries, interface paths, timing budgeting, feedthrough paths, top-level clocking, and routing considerations.\nRoot-cause complex  and recurring timing convergence  and QoR issues across RTL, synthesis, constraints, DFT, clocking, placement, CTS, routing, extraction, and signoff, and drive solutions to closure.\nDrive timing ECO strategy and execution, using both automated and manual techniques for complex setup, hold, DRC, and full-chip timing closure.\nUnderstand Scan/DFT architectures, operating modes, constraints, and associated timing implications.\nDrive strong automation and scalable analysis methodologies that improve productivity, debug efficiency, timing convergence, and signoff quality.\n \nMust Have Skills\nExperience leading multiple successful advanced-node tapeouts.\nDeep hands-on expertise in Digital Synthesis, STA, and timing closure for complex high-speed SoCs in advanced process technologies, preferably 16nm and below.\nStrong expertise in AOCV/SOCV methodologies is a must\nStrong expertise in developing, reviewing, scaling and debugging complex timing constraints across hierarchical designs.\nProven experience owning IP, subsystem, partition, and full-chip timing convergence and signoff.\nStrong understanding of clock-tree analysis, clock latency/skew, clock uncertainty, clock interactions, and clock balancing.\nDemonstrated knowledge of design partitioning, hierarchical timing closure, top-level clock planning/balancing, interface timing, and routing considerations.\nStrong analytical skills to root-cause complex timing and QoR problems across different stages of design implementation and drive effective solutions.\nStrong expertise in automated and manual timing ECO techniques for setup, hold, DRC, and overall timing closure.\nExperience with leakage and dynamic power optimization as part of synthesis and implementation.\nStrong understanding of the complete RTL-to-GDS flow, including floorplanning, placement, CTS, routing, extraction, physical verification, EM/IR, and signoff.\nStrong automation mindset and demonstrated ability to develop scalable solutions for analysis, debug, convergence, and productivity improvements.\n \n \nPreferred Education and Experience\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering.\n10-15 years of relevant experience.\n\nWhy You'll Love Working Here\nAt Analog Devices, you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on professional growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world.\n\nYour expertise will shape the future of technology, and you’ll be supported by a culture that values continuous advancement and professional growth. Join us and help create the technologies that bridge the physical and digital worlds, making a tangible difference in how people live, work, and connect\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Applications Engineering, Sr Staff Engineer (STA, Primetime)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-30", "url": "https://careers.synopsys.com/job/bengaluru/applications-engineering-sr-staff-engineer-sta-primetime/44408/101344394848", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years deep in the timing closure trenches, and you know that the difference between a chip that tapes out on schedule and one that slips six months often comes down to someone who understands both the tool and the real design problem underneath. You have seen PrimeTime from every angle: competitive evals where you had to prove superiority in two days, tape-out firefights at 2 AM, and those strategic conversations where a VP needs to understand why their timing methodology needs to change.\nYou do not just run the tool. You understand setup and hold violations in the context of process corners, you can debug a crosstalk issue that is hiding in a specific mode, and you know when a timing problem is actually a synthesis problem or an extraction artifact. When a customer's design team is stuck, you can look at their reports, ask three targeted questions, and find the path forward.\nYou are equally comfortable sitting with an engineer walking through TCL debug and presenting to a director explaining why their current flow is leaving performance on the table. You have learned that the best technical win is the one where the customer feels like they discovered it with you, not that you sold them something. At Synopsys, you will work with the teams building the most advanced chips in the world, and what you help them solve actually matters.\nWhat You'll Be Doing\nDrive PrimeTime adoption and deployment at customer sites, from initial competitive benchmarks through production tape-out support across advanced node designs\nLead technical evaluations that demonstrate PrimeTime's advantages over competing STA tools, translating runtime, capacity, and accuracy metrics into clear business value for design teams and management\nProvide hands-on support during critical design phases, including timing closure, ECO iterations, and sign-off, working directly with customer engineers to resolve complex timing, SI, and variation issues\nDevelop and deliver technical training on PrimeTime workflows, covering timing constraints, multi-mode multi-corner analysis, variation modeling, and integration with synthesis and physical design flows\nCollaborate with R&D to communicate customer requirements, reproduce field issues, and influence product roadmap based on real design challenges you see in the field\nBuild and maintain TCL-based automation scripts and methodologies that improve customer productivity and demonstrate best practices for timing analysis workflows\nAct as the technical bridge between customers, sales, marketing, and engineering, translating customer pain points into actionable product feedback and solution strategies\nThe Impact You Will Have\nEnable customers to tape out complex SoCs on schedule by resolving timing bottlenecks that would otherwise cause costly respins or schedule slips\nExpand PrimeTime footprint at strategic accounts by proving technical superiority in head-to-head evaluations, directly contributing to revenue growth and competitive wins\nAccelerate customer productivity by delivering training and methodology improvements that reduce timing closure cycles from weeks to days\nShape future PrimeTime capabilities by channeling real-world design challenges back to R&D, ensuring the product evolves to meet next-generation design requirements\nBuild deep technical credibility with customer design teams and management, becoming the trusted advisor they turn to when timing issues threaten project milestones\nReduce support escalations by developing reusable scripts, documentation, and best practices that empower customers to solve common problems independently\nStrengthen Synopsys's position as the timing sign-off standard by demonstrating value across the full design flow, from RTL to GDS\nWhat You'll Need\nBachelor's degree in Electrical Engineering or equivalent, with 10+ years of hands-on experience in ASIC/SoC design or EDA applications, or Master's degree with 8+ years of experience\nDeep working knowledge of Synopsys PrimeTime, including hands-on experience with timing analysis, constraint development, and sign-off flows\nStrong understanding of timing concepts including setup/hold analysis, clock domain crossing, multi-mode multi-corner scenarios, OCV, AOCV, and signal integrity effects\nProficiency in TCL scripting for automation, analysis, and methodology development in EDA tool environments\nFamiliarity with the broader digital design flow, including synthesis, place and route, extraction, and ECO methodologies, and how STA fits into each phase\nExcellent communication skills with the ability to explain complex technical tradeoffs to both engineers and management, prior customer-facing or field engineering experience is a strong plus\nWillingness to travel to customer sites as needed to support evaluations, training, and critical design milestones\nWho You Are\nYou can walk into a customer war room during a timing crisis, look at their reports and setup, and within an hour identify whether the issue is a constraint problem, a tool setting, or a fundamental design issue\nYou know how to run a competitive benchmark that is both technically rigorous and tells a clear story, you measure what matters and you can explain the results to someone who has never opened PrimeTime\nYou are comfortable saying 'I don't know, but I'll find out' and then actually following through, often by pulling in the right R&D engineer or digging into the code yourself\nYou can write TCL that does not just work but that someone else can read and modify six months later, and you have strong opinions about what makes a timing methodology sustainable versus fragile\nYou have been in enough tape-out cycles to know when to push back on an unrealistic constraint and when to help the team find a creative workaround\nYou build relationships that last beyond the eval period, customers call you because they trust your judgment, not just because you know the tool\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Applications Engineering, Sr Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-30", "url": "https://careers.synopsys.com/job/bengaluru/applications-engineering-sr-staff-engineer/44408/101403651056", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n \nYou Are:\nYou are energized by motion—new problems, shifting priorities, and the kind of fast-paced environment where progress depends on clear thinking and calm execution. You don’t wait for perfect information before you act; you ask sharp questions, form a hypothesis, and move forward while keeping others aligned on what you’re learning. You thrive when the work is ambiguous and the stakes are real, because you enjoy turning complexity into something teams can rally around.\nYou approach challenges with a builder’s mindset. You’re curious, hands-on, and willing to experiment, but you’re equally disciplined about quality and follow-through. When something isn’t working, you don’t look for someone to blame—you look for the root cause, the simplest path to resolution, and the long-term fix that prevents repeat issues. You communicate with intention, adapting your message so engineers, partners, and stakeholders all walk away with the same understanding and next steps.\nYou’re the teammate people trust in the middle of pressure. You create space for collaboration, invite different viewpoints, and make others better by sharing context and giving credit freely. You take ownership naturally: when you see a gap, you close it; when you see an opportunity, you champion it. You’re motivated by impact, not spotlight, and you measure success by the reliability, clarity, and momentum you bring to the work—day after day.\n\nWhat You’ll Be Doing:\nCollaborating with customers to understand their technical challenges and providing comprehensive solutions using Synopsys tools and platforms.\nDriving the adoption and integration of EDA tools in customer design flows, ensuring optimal utilization and performance.\nDeveloping and delivering technical workshops, training sessions, and product demonstrations tailored to customer needs.\nPartnering with R&D and product management teams to influence product direction and resolve complex technical issues.\nAuthoring and maintaining technical documentation, application notes, and best practice guides.\nProviding pre- and post-sales technical support, including troubleshooting, bug tracking, and solution development.\nMentoring and guiding junior engineers, fostering a culture of technical excellence and innovation.\nThe Impact You Will Have:\nAccelerating customer success by ensuring seamless deployment and integration of Synopsys solutions.\nEnhancing product quality and usability through direct feedback and collaboration with R&D teams.\nExpanding Synopsys’ footprint in key accounts by demonstrating technical excellence and building strong customer relationships.\nReducing design cycle times and improving overall productivity for our customers.\nContributing to the growth of Synopsys’ technical community through knowledge sharing and mentoring.\nInfluencing future product innovations by identifying emerging customer needs and market trends.\nWhat You’ll Need:\nStrong expertise in ASIC/FPGA design and verification methodologies.\nHands-on experience with industry-leading EDA tools such as synthesis, simulation, and formal verification platforms.\nProficiency in scripting languages (e.g., Python, Perl, TCL) and automation frameworks.\nSolid understanding of digital design, SoC architectures, and semiconductor manufacturing processes.\nAbility to analyze and resolve complex technical issues quickly and effectively.\nWho You Are:\nInnovative thinker with a proactive approach to problem-solving.\nExcellent communicator, able to convey complex technical concepts to diverse audiences.\nCollaborative team player who values diversity and inclusion.\nCustomer-oriented with a commitment to delivering outstanding service and solutions.\nAdaptable, resilient, and eager to learn new technologies and methodologies.\nThe Team You’ll Be A Part Of:\nYou’ll join an accomplished team of application engineering experts at the forefront of EDA and semiconductor innovation. Our team partners closely with customers, R&D, and product management to deliver world-class solutions and technical support. We foster a collaborative, inclusive culture that encourages continuous learning, knowledge sharing, and professional growth. Together, we drive the adoption of cutting-edge technologies and ensure Synopsys remains the trusted partner for industry leaders worldwide.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "IP Technical Expert Center Specialist", "company": "Nokia", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-09-30", "url": "https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/36218", "is_hardware": true, "platform": "oracle", "jd_text": "As an IP Technical Expert Center Specialist, you will serve as a key technical authority in diagnosing and resolving complex IP network issues. You will collaborate with cross-functional teams to lead deployments, conduct root cause analyses, and enhance product performance. This role involves mentoring team members, ensuring operational excellence, and supporting mission-critical production networks while fostering innovation and implementing industry best practices for Network Infrastructure business.\n\nResponsibilities\nDebugs complex product installations, product problems by applying both established procedures and creative alternatives.\nWrites technical application notes, field notices.\nAssists and advises Tier 1/2/3 network architecture and implementation teams. Performs on-site product adaptations or enhancements to installed product.\nProvides technical and sales support for Test and Evaluations, New Product Introductions (NPI). Maintains awareness of new products and releases through regular updates with R&D, Product Management.\nCoordinates upgrade programs for Tier 1 customers (including generation of MOP).\nProvides emergency support to customers on a global basis 24/7.\nExperience / interest in working in a customer support role and environment is preferred.\nProven aptitude for methodical problem solving. Good communication skills. Ability to work well in a close-knit.\n\nQualifications\nYou have:\nBachelor’s degree in Engineering with 7–15 years of relevant experience.\nProvide technical requirement inputs based on customers’ deployment experiences.\nContribute inputs to the development of software/hardware build-controlled production releases.\nSupport the creation and release of hardware/software documentation and customer notifications.\nMaintain technical and design knowledge for assigned products and technologies, and provide training to lower-tier support teams.\n \n\n \nIt would be nice if you also had:\nFamiliarity with the care process (especially emergency case handling), contributing as needed to the fastest possible problem resolution.\nExperience with access network nodes, integrating theoretical knowledge and principles with organizational practices and precedents.\nAdvanced network and node-level troubleshooting skills for IP routers and networks, along with in-depth technical knowledge.\nSpecialized expertise in IP Routing, MPLS, QoS, L2, OAM, Systems, and related areas deployed in high-availability core networks.\n\nAbout the organization\nSome of our benefits in India:\n\nFlexible and hybrid working arrangements to support work–life balance\n\nHealth and well-being support – medical insurance for you and your family, health check-ups, life and accident insurance, well-being programs, and employee resource groups \n\nA minimum of 90 days of Maternity and Paternity Leave based on eligibility\n\nPersonal Support Service 24/7 – a confidential support channel open to all Nokia employees and their families in challenging situations\n\nCareer growth & mobility – technical career paths, job rotations, international assignments, and relocation support\n\nContinuous learning – technical certifications, mentoring programs, coaching, and digital learning platforms\n\nOpportunities to innovate and contribute through Nokia’s research and development environment\n\nRecognition programs that celebrate outstanding contributions\n\nWorkplace support – ergonomic working support and mobile device programs based on eligibility", "jd_status": "stored"}, {"title": "PMIC Analog Design Manager", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-30", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018069", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n We are looking for an experienced Analog Design Manager to lead a team of talented engineers developing next-generation Power Management ICs for advanced personal electronics applications. This is a techno-managerial role — we are looking for someone who remains deeply engaged in the technical fabric of the work: contributing to architectural decisions, shaping design direction, and staying close to silicon, along with managing people and delivery.\n\nYou will drive technical execution across the full PMIC development cycle — from architecture definition and circuit design through silicon bring-up and customer qualification — while building and growing a world-class analog design team. Collaborate with internal teams including layout, systems, verification and validation as well as directly with customers, translating complex system-level requirements into innovative silicon solutions.\n\nFor strong technical contributors, the door to TI's technical career ladder remains open — though the primary growth trajectory in this role is toward senior engineering management and broader technical leadership across programs and teams.\n\nQualifications\nBasic Requirements:\n\n •    Bachelor's degree in Electrical Engineering or related field (Master's or PhD preferred)\n\n •    10+ years of analog/mixed-signal IC design experience with a strong track record in power management\n\n •    Demonstrated experience leading technical teams and projects in a silicon design environment\n\n •    2+ years of experience directly managing analog design engineers (performance management, hiring, career development) in a semiconductor/IC design environment\n\n •    Deep expertise in power converter topologies: buck, boost, LDO, charge pump\n\n •    Hands-on experience across the full IC design flow: schematic, simulation, layout review, silicon bring-up, and characterization\n\n •    Strong written and verbal communication skills\n\n •    Strong stakeholder management skills, with experience communicating program status, risks, and technical decisions to senior leadership and cross-functional teams\n\nPreferred Skills:\n\n •    Experience designing PMICs for consumer electronics applications (mobile, laptops, wearables)\n\n •    Fully proficient and comfortable with standard Power IC design flows end-to-end (Cadence Virtuoso, Spectre)\n\n •    Worst-case analysis, top-level and Monte Carlo simulation, and post-layout PEX verification\n\n •    Physical layout review: power routing, grounding, thermal management, and die area optimization\n\n •    Background in high-performance, high-efficiency analog design with aggressive power and area targets\n\n •    Familiarity with advanced CMOS process nodes\n\n •    Experience working directly with customers on technical alignment and specification definition\n\n •    Exposure to tools including Simplis, AMS, or equivalent (good to have)\n\n •    Demonstrated ability to drive customer and cross-functional technical discussions with authority and ownership\n\n •    Proven track record of mentoring engineers through complex design challenges\n\n •    Ability to manage and personally execute multiple concurrent design tasks on aggressive schedules with high autonomy\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Analog Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-30", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018358", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\n This is a great opportunity to be part of an established team that's continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electronics, mobile computing and communications.\n\nWho are we and what do we do?\n\nThe advanced circuits and power solution business is known for delivering industry leading custom IC system solutions including display and touch power products, charger power products, camera PMICs, power path devices, sensing devices and high-performance communication interface products. Our products integrate precision signal-chain and highly efficient power components in ultra-small form factors that enable TI’s best-in-class customer to translate their ideas to high value products that revolutionize the personal electronics market. \n\n In this team, you will get to work with, and learn from incredibly talented technical leaders, who have influenced TI technology, productivity and way of working in a creative and impactful way. You will get to directly interact with one of TI’s valued and high-volume customers, by way of intense technical reviews and architecture discussions! \n\n By enabling designs that are highly impactful to TI revenue and working with a critical customer on a versatile set of products, you will find yourself on an accelerated career path. \n\n  \n\nAbout the job If you are looking to join an ingenious, vigorous & ambitious team that consistently delivers groundbreaking technologies into the custom mobile electronics world, here is an opportunity for you!   \n\nAnalog Design Engineer\n\nLocation: Bangalore, India\n\nExperience: 2+ Years\n\nWhat will you be doing in this role?\n\nAnalog Chip/Sub-section/IP architect and design with complete ownership and responsibility from definition to release to manufacturing.\n\nDirect, guide and participate in activities of a research or technical design function responsible for designing, developing, modifying and evaluating electronic parts, components, integrated circuits for a variety of applications.\n\nEvaluate intermediate and final results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives.\n\nCollaborate with Design Verification teams during the pre-PG phase of a project to ensure completion of all technical tasks before PG.\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production.\n\nQualifications\nBasic Requirements (Must-Haves)\n\nBachelor’s & Master’s degree in Electrical Engineering or related field of study\n\n2+ years of analog circuit design.\n\n  Preferred Skills & \"Good to Have\" \n\nActive involvement with a customer. Candidate would be expected to interact and collaborate with a sense of ownership with customers and all product development team members including design, layout, systems, verification, validation, test and program management\n\nIC system partitioning and architectural tradeoff analysis\n\nBlock level topology selection, hand analysis, and IC transistor level implementation\n\nSchematic generation and simulation on modern CAD tools (Cadence tool set)\n\nWorst case identification, top level simulation, Monte Carlo analysis, and simulation data analysis\n\nExpertise in tools e.g. Spectre, Simplis, Matlab and AMS\n\n  System level understanding and analysis; and the ability to translate requirements to an IC spec level\n\nPhysical layout management, signal grounding and routing tradeoffs, die area optimization\n\nPost layout parasitic extraction and simulation, verification of all IC level performance metrics\n\nTop level verification, block level modelling, top level simulation\n\nKnowledge of device physics and process technologies tradeoffs that are applicable to Power IC design\n\nMust budget time, manage schedule and complete complex IC design tasks on time\n\nMust have depth of experience and meticulous approach to assure high quality results\n\nMust account for limitations of system level specifications, testability, debug, characterization, production and yield targets in the IC design phase.\n\nMust work well with colleagues and customers to foster a highly creative, interesting, productive and fun working environment.\n\nOrganizational Skills: Ability to work well with internal cross functional teams. Must successfully and appropriately interface with external customers. Project management, time management, multi-tasking, problem solving and communication (written and oral) are important skills in this role. Must be able to manage assigned tasks with minimal supervision.\n\nTeam and People Skills: Candidate must be team oriented and must be able to work with TI-internal and external groups (systems, test, sales, marketing, customers, etc.) to resolve issues and generate business success. The ability to work well with others and to perform in a team environment is essential.\n\nProjects and Deliverables: The main deliverable is the timely release of meticulously analysed and simulated IC designs or sub-sections of designs for custom designs with tight schedules. These designs should lead to cost-effective, high quality, bug-free products that fully meet our customer’s end-system requirements.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Layout Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-30", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018354", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n Texas Instruments is seeking a Layout Engineer. In this role, you will develop and prepare multi-dimensional layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering. Work may be completed through use of CAD or other computerized equipment. You may also check dimensions, write specifications, and verify completed drawings, artwork or digitized plots. Additional job functions may involve checking design layouts and detailed drawings, referring to offline layout leveling charts for details on duties. A bachelor's degree in engineering is typically required, and in the U.S. this job is restricted to specific job grades.\n\nQualifications\nMinimum requirements:\n\nMinimum education (ie bachelor's degree in electrical and electronics engineering)\n\nMinimum of 2-5 years of experience\n\nRoles and responsibilities:\n\nFrame the layout schedule, effort estimation, risk and mitigation plan of layout activities for all layout engineers in the project\n\nWork closely with designers to understand the architecture and key requirements for the IC\n\nStrike right balance of area, performance and schedule during layout development by collaborating with design, packaging and process teams\n\nWork closely with Process development team to carry out PDK, P-cell and Design rule updates\n\nWork closely with Packaging engineer to develop custom lead-frames for various packages \n\nAnalysis and closure of Electro Migration, Thermal gradients, ESD/LU performance and layout parasitic\n\nRoutinely develop test vehicles for new process & package technology development\n\nMentor and guide junior layout engineers/contract engineers, review their work and provide feedback to meet the quality and schedule norms \n\nResponsible for the final layout which meets the design expectations and layout checklist.\n\nIdentify improvements needed in process/ quality/ cycle time and take up necessary initiatives\n\nKnowledge and skills:\n\nFull chip layout experience from definition through release of IC to production\n\nStrong LVS, DRC, ERC, and antenna debug skills\n\nProficient in analog and mixed-signal layout techniques and verification process including Device Matching, Power Bus design, avoiding Cross-talk, ESD/LU protection techniques\n\nGood understanding about all layout parasitics (R, C, diodes, BJTs)\n\nGood understanding of device physics and semiconductor fabrication process\n\nMust have worked on some of the Technologies like: 40nm, 65nm, 90nm, 130nm, 180nm, BiCMOS\n\nShould be well versed with tools such as Virtuoso XL/Assura /PVS/Voltas\n\nAbility to quickly ramp up on new tools/ process and mentor LEs\n\nExperience in automation/ SKILL coding for reducing cycle time/ quality checks will be an added advantage\n\nRequires excellent teamwork, good communication, strong problem-solving and documentation skills.\n\nStrong time management skills for on-time project delivery\n\nAbility to take initiatives and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Layout Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-30", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018355", "is_hardware": true, "platform": "oracle", "jd_text": "About the job - Analog Layout Engineer.\n\nRoles and responsibilities:\n\nFrame the layout schedule, effort estimation, risk and mitigation plan of layout activities for all layout engineers in the project\n\nWork closely with designers to understand the architecture and key requirements for the IC\n\nStrike right balance of area, performance and schedule during layout development by collaborating with design, packaging and process teams\n\nWork closely with Process development team to carry out PDK, P-cell and Design rule updates\n\nWork closely with Packaging engineer to develop custom lead-frames for various packages \n\nAnalysis and closure of Electro Migration, Thermal gradients, ESD/LU performance and layout parasitic\n\nRoutinely develop test vehicles for new process & package technology development\n\nMentor and guide junior layout engineers/contract engineers, review their work and provide feedback to meet the quality and schedule norms \n\nResponsible for the final layout which meets the design expectations and layout checklist.\n\nIdentify improvements needed in process/ quality/ cycle time and take up necessary initiatives\n\nKnowledge and skills:\n\nFull chip layout experience from definition through release of IC to production\n\nStrong LVS, DRC, ERC, and antenna debug skills\n\nProficient in analog and mixed-signal layout techniques and verification process including Device Matching, Power Bus design, avoiding Cross-talk, ESD/LU protection techniques\n\nGood understanding about all layout parasitics (R, C, diodes, BJTs)\n\nGood understanding of device physics and semiconductor fabrication process\n\nMust have worked on some of the Technologies like: 40nm, 65nm, 90nm, 130nm, 180nm, BiCMOS\n\nShould be well versed with tools such as Virtuoso XL/Assura /PVS/Voltas\n\nAbility to quickly ramp up on new tools/ process and mentor LEs\n\nExperience in automation/ SKILL coding for reducing cycle time/ quality checks will be an added advantage\n\nRequires excellent teamwork, good communication, strong problem-solving and documentation skills.\n\nStrong time management skills for on-time project delivery\n\nAbility to take initiatives and drive for results\n\nQualifications\nMinimum requirements:\n\nMinimum education (ie bachelor's degree in electrical and electronics engineering)\n\nMinimum of 2-5years of experience\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Sr Staff/Principal Application Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-29T14:35:31.953000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000152457341-sr-staff-principal-application-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking a Senior Staff /Principal Applications Engineer with deep expertise in power electronics and power management systems to support Renesas’ India‑focused growth initiatives. This role is hands‑on, customer‑facing, and technically authoritative. \nThe successful candidate will act as the technical backbone between customers, field teams, and internal design groups, owning application architecture, reference designs, competitive analysis, validation methodology, and critical customer debug. This role strongly influences product P&L or roadmap decisions through real system insight. \nYou will be expected to operate autonomously, mentor other applications engineers, and represent Renesas as a trusted technical authority at key customer engagements \nResponsibilities :\nCustomer‑Facing Applications Leadership \nServe as the primary technical interface for key customers in power-related applications (industrial, automotive light EV, inverter/UPS, consumer power, energy storage). \nLead design‑in, bring‑up, and debug activities at customer sites or Renesas labs. \nDiagnose complex system‑level issues across power stage, control loop, sensing, firmware interaction, EMI/thermal behaviour. \nProvide structured technical feedback to product and design teams based on real customer usage. \nReference Designs & Application Enablement \nArchitect and develop reference designs, evaluation platforms, and application demonstrators using Renesas power products (e.g., MOSFETs, DC/DC, PMICs, gate drivers, BMS ICs). \nOwn schematic review, component selection, PCB guidance, and layout best‑practice recommendations. \nGenerate application notes, design guides, and technical collateral that materially improve customer adoption. \nDefine validation plans that reflect real-world corner cases, not just datasheet conditions. \nSystem‑Level Technical Expertise \nUnderstand and analyse full power system behaviour, including:  \nControl loop stability and transient response \nThermal and efficiency trade‑offs \nProtection mechanisms and fault behaviour \nInteraction with MCUs/SoCs and firmware \nPerform and guide system modelling and simulation (SIMPLIS, PLECS, SPICE). \nEvaluate design trade‑offs and clearly articulate why one solution works better than another keeping BOM cost in mind \nLab Ownership & Technical Depth \nHands‑on operation of lab equipment: oscilloscopes, Bode/network analysers, electronic loads, power supplies, thermal setups. \nDevelop automation scripts (Python/C) to accelerate validation and characterization. \nSupport failure analysis and root cause investigation for field issues and RMA trends. \nTechnical Leadership & Mentorship \nAct as a technical mentor for junior and mid‑level applications engineers. \nHelp define best practices, review standards, and debug methodologies across the power applications team. \nInfluence hiring by helping assess deep technical capability (not surface‑level)\n\nRequired skills & Qualifications:\nComfort and ability to collaborate and be effective in an entrepreneurial (fast-paced and ambiguous) environment  \nExcellent interpersonal, communication and presentation skills and comfort in presenting to a wide range of audiences. Capable to communicate issues in a concise and effective way. \nDesire and drive to interact with, as well as ability to build and maintain excellent relationships with internal and external stakeholders.  \nProduct ownership mentality \n12+ years of experience in power management space, ideally including customer facing technical problem solving with semiconductor companies  \nTravel will be required \nBachelor or Masters of Electronics Engineering related discipline  \nAbility to build a strong team and motivate individuals to work out of their comfort zone \nSelf-driven, strongly motivated individual capable to take full ownership of their activities, and to involve other functions in the company or management when needed to bring them to a successful outcome. \nUnderstanding of power management applications and products. \nTechnical proficiency :\nDeep understanding of Power topologies (e.g., buck, boost, buck boost, isolated where relevant), Control loop theory and compensation, Thermal design and power loss modelling (using FEA tools), and EMI/EMC considerations at board and system level \nHands-on experience and ability in lab debugging, probing and characterizing circuit and silicon using a mixture of custom-made and standard equipment such as power supplies, e-load, digital oscilloscopes, spectrum analyzers, etc. \nSIMPLIS or similar ckt simulator  \nProgramming proficiency Python or C for automation and data analysis \nExpertise in board level analog and digital circuit design expertise and PCB schematic design using PCB CAD tools \nProficiency with a full complement of lab equipment including network analysers, oscilloscopes and waveform generators.  Experience with automation of lab testing. \nData analysis using Excel or JMP  \nUnderstanding of AECQ / IATF /ISO26262 (FuSa) (At least basic level) \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "CPU Verification Engineer - Core Enablement", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-29T14:17:00+00:00", "url": "https://global-external-amd.icims.com/jobs/93097/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. SILICON DESIGN ENGINEER 2 THE ROLE: AMD is looking for talented, detail-oriented, and motivated design verification engineers who are interested in functional verification of x86 microprocessor cores. You’ll have the unique opportunity to work on and learn about some of the industry’s cutting edge micro-architectural designs while you create verification models and plans for verifying the architecture of the X86 CPU core. Your contributions will impact products that span the global x86 market from server to desktop and laptop designs. THE PERSON: The ideal candidate will have a strong interest in Computer Architecture, Digital Logic Design and Verification and should strive to continuously learn on the job. Excellent communication, organization, and teamwork skills are paramount, as is the ability to identify and tackle different problems with diligence, whether it is a tool, flow or process issue, or a logic design or verification issue. You should be adaptive, self-motivated, able to strike a balance between collaborative problem-solving and independent solution development. Candidate should have a solid track record of working on complex designs with hands-on experience on architecting and developing test-bench, test-bench components, test-planning and execution of test plan, coverage development and closure. Candidate should have working experience with global teams spread across different geography and time-zones. KEY RESPONSIBILITIES: · Collaborate with architects, design engineers, and other verification engineers to understand new CPU features to be verified. · Build test plan documentation, accounting for interactions with other features, various design sub-units within CPU, SOC and also hardware, firmware, and software use cases if applicable. · Estimate time required to write new feature tests and any required changes to the test environment and tools. · Develop directed and random verification tests. · Understanding the existing test bench setup and look for opportunities to improve it. · Debug test failures to determine the root cause; work with RTL design engineers to resolve design defects and correct any stimulus or testbench issues. · Use scripting and internal AI tools to come up with innovative solutions to day-to-day problems and to improve individual as well as team's productivity. · Develop functional coverage properties as needed. · Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements. · Mentor junior engineers as needed. PREFERRED EXPERENCE: · ASIC design verification experience of 5 to 10 years. · Understanding or technical expertise in functional verification of microprocessor designs. · Experience with Verilog/System Verilog HDL, programming in Perl/Python/Ruby, C/C++, Makefile and logic simulation. · Experience with x86, ARM or any other industry standard microprocessor architecture. · Strong understanding of computer architecture and assembly programming, preferably x86. · A passion for computer architecture and a good understanding of modern out-of-order superscalar processor architecture. · Strong understanding the design and verification life cycle. · Experience in CPU cache/memory subsystem verification is a plus · Simulation and debugging with a Verilog based functional simulator. · General functional verification experience with digital designs. · Working experience in UNIX software environment. · Strong problem-solving and debugging skills in both pre- and post-silicon environments. · Exposure to leadership or mentorship is an asset. · Familiarity with use of AI is a plus. ACADEMIC CREDENTIALS:      Bachelor's or Master’s degree in Electrical/Electronics Engineering, Computer Engineering, Computer Science or similar with a focus on computer architecture #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Staff Engineer Design", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-09-29T12:39:52+00:00", "url": "https://jobs.infineon.com/careers/job/563808971975656", "is_hardware": true, "platform": "eightfold", "jd_text": "Seasoned DSP Hardware Design expert with 7+ years of experience in taking complex digital signal processing solutions from RTL development to silicon. Strong expertise in Verilog RTL design, fixed-point arithmetic, programmable digital filters, high-throughput data paths, and mixed-signal SoCs. Proven capability in implementing and verifying digital filters within closed-loop control systems, with deep understanding of system stability, phase behavior, and numerical accuracy. Experienced in UVM-based verification, AMBA bus integration, timing closure, CDC, and safety-critical development environments. Combines strong DSP fundamentals with hands-on hardware realization expertise, making them an excellent fit for advanced semiconductor and control-system applications.\n\nYour role\nKey responsibilities in your new role\n\nExpert\nVerilog RTL design for arithmetic data paths: multipliers, accumulators,\npipelining, resource sharing and time-multiplexing across parallel channels. \n\nDesigning programmable filter hardware — coefficient tables, compact coefficient encodings, and run-time bandwidth reconfiguration.\nComfortable working alongside UVM-based verification and defining the numerical acceptance criteria (Bit-exact model correlation) Clock domain crossing, reset architecture, and timing closure awareness for high-throughput data paths.\nRegister interface and on-chip bus integration (AMBA AHB/APB).\n\nYour profile\nQualifications and skills to help you succeed \n\nMaster’s\ndegree in Electrical/Electronic Engineering, Communications Engineering,\nMicroelectronics or a related field, with a specialization digital signal\nprocessing, control engineering or communications. \n\nA Bachelor’s degree with equivalent demonstrated DSP implementation experience is also welcome\nMinimum 7 years designing digital signal processing hardware in RTL with at least one product taken through to silicon.\nProven track record implementing digital filters in fixed-point hardware— not only modelling them, but owning the RTL realization, its numerical behavior and its verification.\nExperience where filters sit inside a closed control loop, so that filter bandwidth, group delay and phase behavior directly affect system stability.\nBackgrounds in digital power conversion, motor control, sensor signal chains, audio, or wireless baseband are all relevant.\nExperience in mixed-signal SoCs, working directly with ADC/sensor frontends and understanding how converter behavior shapes downstream processing.\nAutomotive or other safety-critical development to ISO 26262 is an advantage\nDeep,\npractical expertise in fixed-point arithmetic and Q-format design: word-length\nand bit-growth analysis, coefficient quantization, rounding and truncation\nmodes, overflow and saturation strategy. \n\nStrong\ncommand of DSP fundamentals: sampling and aliasing, Z-transform, transfer\nfunctions, pole/zero placement, frequency response, group delay, and stability\nanalysis. \nFamiliarity\nwith requirements-driven development and traceability tooling such as Jama.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nVidhi Thakkar", "jd_status": "stored"}, {"title": "Sr Validation Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-29T06:59:46.629000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000152337439-sr-validation-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Staff Engineer – Hardware Engineering Strategist", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-29T06:51:20.374000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000152336119-staff-engineer-hardware-engineering-strategist", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking a senior engineering professional with strong experience across the hardware product development lifecycle and exposure to a wide range of engineering tools and ecosystems used in the industry. \nThis role will evaluate engineering toolchains, assess new technologies, and drive the adoption of solutions that improve collaboration, traceability, workflow efficiency, and design reuse across engineering teams. The successful candidate will work closely with hardware, software, systems, quality, manufacturing, and IT teams to build a more connected and efficient engineering ecosystem. \nThis is not a product design role. The primary responsibility is to leverage deep hardware development knowledge and industry experience to improve engineering processes, tools, integrations, and overall engineering effectiveness. \nKey Responsibilities \nStrong understanding of the end-to-end product development lifecycle, including Requirements Management, System Architecture, Design, Simulation, Verification, Compliance, Manufacturing, Product Release, and Product Lifecycle Management (PLM). \n\nExtensive knowledge of industry-leading engineering tools and platforms like Altium, A365, Cadence, Siemens Xpedition, Ansys, MATLAB/Simulink, Teamcenter, Windchill, Jira, Git, and related engineering collaboration solutions. \n\nAnalyze engineering workflows to identify process gaps, tool limitations, data silos, manual handoffs, and opportunities to improve productivity, quality, traceability, and engineering efficiency. \n\nCollaborate with hardware, software, systems, manufacturing, quality, and program teams to understand engineering challenges and define ecosystem requirements. \n\nEvaluate, recommend, and drive adoption of engineering tools, technologies, and workspace capabilities that enhance collaboration, integration, and lifecycle visibility. \n\nChampion engineering best practices, design reuse, traceability, standardization, and scalable development methodologies across the organization. \n\nLead initiatives focused on tool integration, workflow automation, digital engineering, and AI-enabled engineering solutions. \n\nSupport the development of engineering workspaces, governance models, data management strategies, and lifecycle processes that enable a connected engineering ecosystem. \n\nBenchmark engineering ecosystems, tools, and industry practices to identify opportunities for modernization and continuous improvement. \n\nContribute to engineering technology roadmaps and future ecosystem strategies through strong lifecycle, tooling, and industry knowledge. \n\nDrive successful solution adoption through stakeholder engagement, training, documentation, user workshops, and engineering advocacy. \n\nBachelor’s or Master’s degree in Electronics Engineering, Electrical Engineering \n\n10+ years of experience in engineering organizations with strong exposure to the complete hardware product development lifecycle. \n\nHands-on experience working with industry-standard engineering tools and platforms such as Altium, Altium 365 (A365), Cadence, Siemens Xpedition, Ansys, MATLAB/Simulink, Teamcenter, Windchill, Jira, Git, and related engineering collaboration solutions. \n\nStrong knowledge of engineering data management, configuration management, change control, traceability, design reuse, and lifecycle governance practices. \n\nUnderstanding of engineering tool integrations, workflow automation, digital thread, digital engineering, and AI-enabled engineering capabilities. \n\nStrong stakeholder management, communication, facilitation, and influencing skills with the ability to drive organizational change and solution adoption. \n\nAbility to lead workshops, training sessions, process improvement initiatives, and cross-functional transformation programs. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Staff/Senior Engineer- Mask Design (Analog Layout)", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-29T06:47:49.597000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000152335037-staff-senior-engineer-mask-design-analog-layout-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Looking for an experienced Analog Layout Design Engineer to join the 2.6B$ Power Business Unit where in the candidate will get to work on a wide range of exciting products such as Controllers, Drivers, DC-DC converters powering the next generation of AI and automotive power needs. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas’s massive Power product portfolio.\n\nEssential Functions:\nExperienced in all aspects of Analog layout design from block level to full chip with a demonstrated history in driving design innovation and best practices.\nShould have the ability to work independently with little supervision to floorplan and layout typical analog circuits such as charge pumps, comparators, amplifiers, bandgaps, linear regulators etc take complete ownership to drive all aspects within the committed schedule.\nCan manage a small group of engineers with a proven history of mentoring new college graduates.\nStrong knowledge of die-level digital, analog, PowerFET, ESD, I/O, and PAD integration, including die-to-bump connectivity and package substrate interactions.\nMust have deep knowledge in floor planning, analog layout matching techniques along with designing for EM and reliability.\nMust be a natural team player and strive towards fostering a highly creative and productive working environment\n\nBachelor’s or master’s degree in electrical engineering.\n5+ years in Analog Layout Design and associated flows for DRC, LVS, Packaging\nAdditional Preferred Qualifications\nSolid understanding of IC Layout design (preferably BCD nodes) and package/substrate design (Flip chip, BGA, wire bond) along with familiarity with advanced IC CAD tools\nSKILL coding and proficiency in any of the scripting languages such as Python, Perl, TCL etc\nExpertise in the required CAD tools (Virtuoso XL / Calibre DRC, LVS & PEX / PVS / EM/ IR/ R3D)\nWork closely in collaboration with colleagues in circuit and layout to minimize need for rework.\nFollow methodology guidelines to ensure easy portability of IP across designs.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "LEC CAD Engineer, Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-29T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446717620210", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Description\nWe are seeking a highly motivated Formal Verification Engineer with 6-8 yeas of experience to join our GCAD Formal team. The ideal candidate will have strong formal verification fundamentals, hands-on experience with formal tools, excellent analytical and scripting skills, and the ability to drive innovative verification methodologies. This role provides the opportunity to collaborate across global architecture, design, and systems teams to influence and strengthen verification sign‑off quality.\nWhat You Will Be Doing\nDrive formal verification of complex design blocks using advanced Formal Apps and robust convergence strategies to achieve exhaustive and high‑confidence sign‑off.\nCollaborate with worldwide architecture, design, and systems teams to achieve verification goals.\nReview and refine formal setups, proofs, constraints, and abstractions with design/DV teams.\nEngage with EDA vendors and evaluate advanced DV methodologies to improve sign‑off quality.\nDevelop automation scripts (Python preferred) to enhance efficiency and scalability of FV flows.\nAnalyze challenging formal problems and propose effective verification strategies.\nLow power formal methodology\nWhat We Need to See\n5+ years of hands-on experience in Formal Verification.\nStrong understanding of formal concepts, proof strategies, and abstraction techniques.\nProficiency with formal tools (Jasper, VC Formal, Questa Formal, etc.).\nWorking knowledge of property-based FV (SVA ) is a plus.\nExcellent scripting skills (Python strongly preferred).\nStrong analytical and problem‑solving abilities.\nClear communication skills and ability to collaborate with global teams.\nA strong willingness to learn, innovate, and deliver high‑quality results.\nLow‑power knowledge is a plus (e.g., power‑aware verification concepts, UPF/CPF, isolation/retention, power/clock gating, power‑aware apps, and basic power‑intent debugging).\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Engineer, SoC Performance", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-29T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721219174", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Systems Engineering\nGeneral Summary:\nJob Overview\nQualcomm's Multimedia System Performance team is responsible for system-level performance validation, analysis, and optimization across compute and mobile SoCs. The Engineer will work on pre-silicon and post-silicon platforms to validate multimedia use cases, analyze system performance metrics, debug bottlenecks, and collaborate with cross-functional teams to ensure performance goals are achieved.\n \nKey Responsibilities\nPerform system-level performance validation and analysis on pre-silicon (RUMI, emulation, simulation) and post-silicon platforms.\nDevelop and execute multimedia and system-level performance workloads, test vectors, and concurrency use cases.\nCollect, analyze, and debug performance metrics including bandwidth, latency, throughput, and QoS indicators.\nInvestigate performance bottlenecks across multimedia IPs, SMMU, cache, NoC, memory controller, DDR, power, and software domains.\nCollaborate with Architecture, Design, DV, Software, Power, and Multimedia teams to drive issue resolution and performance optimization.\nContribute to automation, performance sign-off activities, technical reviews, and project deliverables.\nMinimum Qualifications\nMaster's/Bachelor's degree in Electronics and Communications Engineering, Computer Science, or related field.\n1-2 years of experience in embedded systems, SoC validation, system performance, or a related domain.\nStrong analytical and system-level debugging skills.\nGood programming skills in C and familiarity with Python/Shell scripting.\nUnderstanding of Linux/Android OS fundamentals, scheduling, memory management, and kernel concepts.\nBasic understanding of SoC architecture, memory hierarchy, interconnects (NoC), and performance analysis.\nPreferred Qualifications\nExperience with pre-silicon platforms such as RUMI, emulation, FPGA, or simulation environments.\nExposure to multimedia subsystems including Display, Video, Camera, or Graphics.\nFamiliarity with performance profiling tools, counters, traces, and workload analysis.\nExperience debugging system-level performance issues in mobile or compute SoCs.\nLevel of Responsibility\nWorks under general supervision to execute assigned validation and debugging tasks.\nIndependently analyzes performance issues and collaborates with cross-functional teams to drive resolution.\nContributes to project execution, documentation, and performance sign-off activities.\n \n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RTL Design - Director", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-29T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719429122", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    15+ years of Hardware Engineering or related work experience.\n•    4+ years of experience with circuit/logic design/validation (e.g., digital, analog, RF).\n•    4+ years of experience utilizing schematic capture and circuit stimulation software.\n•    4+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    4+ years in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages expert Hardware knowledge and experience to plan, optimize, verify, and test highly critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Drives the development of design rules and processes for electronic hardware, equipment, and/or integrated circuitry.\n•    Serves as an expert resource for conducting highly complex simulations and analyses of designs as well as for the implementation of designs with the best power, performance, and area.\n•    Collaborates with high-level representatives across functions (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement and drive new requirements and the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the novel manufacturing solutions for leading edge products in highly advanced processes and bring-up product to meet customer expectations and schedules.\n•    Serves as an expert resource for the evaluation of reliability for highly critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Advises multiple teams of engineers in the development of complex hardware designs, evaluating various design features to identify potential flaws or issues.\n•    Writes detailed technical documentation for highly complex Hardware projects; reviews technical documentation for experienced engineers.\n\nLevel of Responsibility:\n•    Provides supervision to direct reports.\n•    Decision-making is critical in nature and highly impacts program, product, or project success.\n•    Requires verbal and written communication skills to convey highly complex and/or detailed information. May require strong negotiation and influence with large groups or high-level constituents.\n•    Works within the prescribed budgetary objectives of the department. \n•    Has a great degree of influence over key organizational decisions.\n•    Tasks often require multiple steps which can be performed in various orders; extensive planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU Design Sr Staff Verification Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-29T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720189489", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nQualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement.\n\nRoles and Responsibilities\n\no   Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling.\no   Work closely with design/verification teams within CPU to develop comprehensive test plan.\no   Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus.\no   Verify power intent through use of methodologies like UPF.\no   Work closely with system architects, software teams and Soc team to validate system use cases.\no   Work closely with emulation team to enable verification on emulators and FPGA platforms.\no   Debug and triage failures in simulation, emulation and/or Silicon.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nBE/BTech degree in CS/EE with 4+ years’ experience.\n\no   Experience in power management verification.\no   Implementation of assembly and C language embedded firmware.\no   Experience in C/C++, scripting languages, Verilog/system Verilog.\no   Strong understanding of power management features in CPUs and CPU based Socs.\no   Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.\n\nPreferred Requirements:\n\no   Good Understanding of CPU architectures and CPU micro-architectures.\no   In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture\no   Experience with advanced verification techniques such as formal and assertions is a plus\no   Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Sr Engineer - HW Board design", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-29T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720932786", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    12+ years of Hardware Engineering or related work experience.\n•    3+ years of experience with circuit/logic design/validation (e.g., digital, analog, RF).\n•    3+ years of experience utilizing schematic capture and circuit stimulation software.\n•    3+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test highly critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Participates in or leads the implementation of advanced design rules and processes for electronic hardware, equipment, and/or integrated circuitry.\n•    Conducts highly complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops novel manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of highly critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Advises and leads engineers in the development of complex hardware designs, evaluating various design features to identify potential flaws or issues.\n•    Writes detailed technical documentation for highly complex Hardware projects; reviews technical documentation for junior engineers.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making is significant in nature and affects work beyond immediate work group.\n•    Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. \n•    Has a moderate amount of influence over key organizational decisions.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SOC RTL Design - Senior Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-29T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721182712", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.\n•    5+ years of ASIC design, verification, validation, integration, or related work experience.\n•    2+ years of experience with architecture and design tools.\n•    2+ years of experience with scripting tools and programming languages.\n•    2+ years of experience with design verification methods.\n•    1+ year of work experience in a role requiring interaction with senior leadership (e.g., Director level and above).\n\nPrincipal Duties & Responsibilities:\n•    Leverages ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.\n•    Creates architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.\n•    Collaborates across teams (e.g., software architecture, hardware architecture) to develop and execute an implementation strategy that meets system requirements and customer needs.\n•    Evaluates all aspects of complex process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.\n•    Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable architecture and design of multiple blocks/SoC or IC Packages.\n•    Writes and reviews detailed technical documentation for EDA/IP/ASIC projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc.  \n•    Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions).\n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU Design Verification - Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-29T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719906908", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nQualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement.\n\nRoles and Responsibilities\n\no   Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling.\no   Work closely with design/verification teams within CPU to develop comprehensive test plan.\no   Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus.\no   Verify power intent through use of methodologies like UPF.\no   Work closely with system architects, software teams and Soc team to validate system use cases.\no   Work closely with emulation team to enable verification on emulators and FPGA platforms.\no   Debug and triage failures in simulation, emulation and/or Silicon.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nMinimum Requirements:\n\no   BE/BTech degree in CS/EE with 3+ years’ experience.\no   Experience in power management verification.\no   Implementation of assembly and C language embedded firmware.\no   Experience in C/C++, scripting languages, Verilog/system Verilog.\no   Strong understanding of power management features in CPUs and CPU based Socs.\no   Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.\n\nPreferred Requirements:\n\no   Good Understanding of CPU architectures and CPU micro-architectures.\no   In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture\no   Experience with advanced verification techniques such as formal and assertions is a plus\no   Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Analog Circuit Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-29", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Analog-Circuit-Design-Engineer_JR0287600", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nRole Overview\nAs an Integrated Voltage Regulator (IVR) Design Engineer, you will be responsible for the architecture, design, and implementation of high-performance power management solutions directly integrated onto advanced processors (CPUs, GPUs, or SoCs). You will work at the intersection of Analog/Mixed-Signal IC design and Power Electronics to improve energy efficiency and performance in next-generation computing systems.\n\nKey Responsibilities\nCircuit Architecture and Design: Develop and refine analog topologies such as Operational Amplifiers (Op-Amps), Bandgap References, Data Converters (ADC/DAC), and Phase-Locked Loops (PLLs).\nDesign and Simulation: Perform transistor-level design using industry-standard tools (like Cadence Virtuoso). Conduct extensive Monte Carlo simulations, corner analysis, and noise analysis to ensure high yield and reliability.\nLayout Oversight: Collaborate closely with layout engineers to guide critical placement and routing, focusing on matching, shielding, and minimizing parasitic capacitance/resistance.\nVerification: Use SPICE-based simulators to verify circuit functionality against rigorous performance specifications (speed, power, gain, etc.).\nPost-Silicon Characterization: Bench-test silicon prototypes in the lab to validate performance against pre-silicon models and debug hardware anomalies\n\nQualifications:\nRequired Technical Skills\nTransistor Fundamentals: Expert knowledge of MOSFET/BJT device physics, small-signal modeling, and aging effects.\nEDA Tool Proficiency: Mastery of Cadence (Spectre/Virtuoso), Mentor Graphics, or Synopsys tool suites.\nSignal Integrity: Deep understanding of thermal noise, jitter, crosstalk, and power supply rejection ratio (PSRR).\nMixed-Signal Flow: Familiarity with Verilog-A or Verilog-AMS for behavioral modeling of analog blocks.\nQualifications\nEducation: BS, MS, or PhD in Electrical Engineering (EE) with a concentration in Analog IC Design.\nExperience: 3 - 7 years of experience in analog design (FinFET or planar CMOS nodes).\nAnalytical Mindset: Strong mathematical background for analyzing feedback systems and stability.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Senior IP Design Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-09-29", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Verification-Engineer--Digital-IP_R-10063871-1", "is_hardware": true, "platform": "workday", "jd_text": "In this role, you will be responsible for developing high-quality, reusable IPs for SoC/subsystem integration and driving designs from concept through silicon. This position offers an opportunity to work on cutting-edge semiconductor technologies and collaborate with global cross-functional teams.\n \n \n \nKey responsibilities\n \nWork with architecture teams and put up the micro-architecture based on the IP requirements\nDevelop RTL using Verilog/SystemVerilog/VHDL based on micro-architectural specifications\nTranslate system-level requirements into high-quality IP designs\nOptimize designs for power, performance, and area\nPerform design checks such as Lint, CDC, synthesis, and STA\nDrive bug fixing and closure\nSupport design reviews and sign-off processes\nCollaborate with verification teams on test plans and coverage closure\n \nRequired skills\nStrong experience in RTL design (Verilog/SystemVerilog/VHDL)\nSolid understanding of SoC/IP design and integration\nHands-on experience with:Lint, CDC, synthesis, timing analysis\nExperience in Low-power design techniques\n \n \nPreferred skills\n \nExperience in full-cycle IP/SoC development\nExposure to formal verification or low-power flows\nExperience with post-silicon validation and bring-up\n\nMore information about NXP in India...\n\n#LI-29f4", "jd_status": "stored"}, {"title": "Senior Engineer, DFT Engineering", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-09-29", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Sr-Physical-Design-Engineer_R264060", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \n\nJob Description:\n\nWe are seeking a skilled and experienced DFT Engineer to join our VLSI design team. The ideal candidate should have a strong background in Design for Testability (DFT) techniques, including LBIST (Logic Built-In Self-Test), ATPG (Automatic Test Pattern Generation), DFT DRC (Design Rule Checking), MBIST (Memory Built-in Sefl-Test), Boundary Scan, JTAG and Analog/Phy DFT.\n\nResponsibilities:\nCollaborate with the design team to ensure efficient and effective testability of complex integrated circuits.\nDesign and implement DFT features such as scan chains, compression, and built-in self-test structures to enhance testability.\nConduct DFT DRC checks in RTL/Netlist database to ensure compliance with DFT guidelines and rules.\nUtilize Siemen’s DFT tool to perform DFT analysis and optimize testability metrics.\nGenerating high quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models using on-chip test compression techniques.\nMBIST Design (including repair) and Verification using Siemen’s EDA tool.\nValidation of DFT structures/patterns in RTL, Netlist with and without SDF.\nWork closely with the verification team to define and implement DFT verification plans.\nWork closely with physical design team for DFT implementation/constraints strategy for synthesis/STA.\nAnalyze and debug test failures and collaborate with the test engineering team to resolve issues.\nProvide guidance and mentorship to junior DFT engineers.\n\nQualifications:\nBachelor's/Master's degree in Electrical/Electronic Engineering, or a related field.\n3-8 years of hands-on experience in DFT methodologies and techniques.\nStrong knowledge of LBIST, ATPG, DFT DRC, Scan compression, Low power DFT Techniques, MBIST, Boundary Scan, Analog DFT, JTAG Architecture, DFT STA Constraint development.\nHand-on experience/expertise in Siemen’s DFT EDA tools for Scan stitching, DRC, ATPG, Coverage improvement, MBIST, Boundary Scan.\nProficiency in scripting languages such as Perl, Tcl, and/or Python for automation.\nSolid understanding of digital design fundamentals, RTL coding, Lint/CDC, Low Power Checks and ASIC design flow.\nExcellent problem-solving skills and ability to work effectively in a team-oriented environment.\nStrong communication and interpersonal skills.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Principal Engineer, Digital Design Engineering", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-09-29", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/SoC-Chip-Lead_R262925", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nAbout the Role:\n\nAs an SoC Chip Lead, you will lead SoC execution from spec to silicon across domains. You will be responsible to drive technical strategy and execution for complex SoCs and digital systems, drive product and technology roadmaps, architecture for mission-critical projects and serve as a technical authority within the organization. This position requires exceptional expertise across multiple domains and the ability to influence business direction while delivering on the product actualization.\n\nKey Responsibilities:\n\nTechnical Strategy & Architecture\nDrive Product Strategy: Define long-term product and technology roadmaps for complex SoCs and systems.\nSelect IP & Nodes: Lead technical IP assessments, vendor selection, and foundry technology node evaluations.\nDefine Architecture: Author and drive top-level SoC definitions alongside business and architecture teams, including fabric interconnects (NoC), memory hierarchies, power management, and micro-architecture.\nSilicon Execution & Sign-off\nOwn the Lifecycle: Lead SoC execution from initial concept through definition, tape-out, and final productization.\nOptimize PPA: Ensure all silicon milestones meet strict Power, Performance, Area, and Cost (PPA) requirements.\nGovern Silicon Sign-off: Drive final sign-off reviews for synthesis, DFT, constraints, timing closure, and physical design tape-out.\nCross-Functional Leadership & Collaboration\nUnify Engineering Domains: Direct and collaborate closely with all core hardware engineering functions, including Design (RTL), Verification (DV), DFT, Physical Design (PD), Power, and Silicon Validation (SiVal).\nBridge Hardware and Software: Partner with software, systems, manufacturing, and program management to guarantee high-quality, first-time-right silicon success.\nManage Stakeholders: Lead executive decision-making, mitigate program risks, and manage communications across business units, product marketing, and customers.\n\nMust Have Skills:\n\nTechnical Strategy: Visionary capability to define and drive technical strategy for digital design\nInnovation Leadership: Exceptional ability to drive innovation in digital design approaches and solutions\nSoC Architecture: Authority in complex SoC architecture design and implementation\nMulti-Domain Expertise: Comprehensive mastery across multiple technical domains\nBusiness Acumen: Strong understanding of business context and ability to align technical strategy with business goals\nIndustry Thought Leadership: Recognized expertise with ability to influence industry direction\n\nPreferred Education and Experience:\n\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent experience\n12+ years of relevant experience in semiconductors design roles\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Senior Staff Hardware Engineer, Signal and Power Integrity", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-29", "url": "https://careers.synopsys.com/job/bengaluru/senior-staff-hardware-engineer-signal-and-power-integrity/44408/101302185232", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nYou have spent years deep in the physics of high-speed signaling, where a trace width or a via placement can mean the difference between a chip that works and one that doesn't. Signal and power integrity is not an afterthought for you, it is the foundation, and you have learned that the best IP designs are the ones where SI/PI constraints shape architecture from day one, not get bolted on at tape-out.\nYou are comfortable running SPICE simulations, setting up 3D EM models, and translating what you find into layout rules that a package designer in another time zone can actually use. When a customer asks whether UCIe will close timing in their 2.5D interposer stack, you do not guess, you model it, validate it, and walk them through the tradeoffs with enough clarity that they trust your guidance.\nYou have worked on enough high-speed interfaces to know that every protocol has its quirks, UCIe, HBM, DDR, PCIe, and you know how to adapt your analysis flows without starting from scratch every time. You script when it saves time, you collaborate when it moves the work forward, and you push back when a design decision will create an SI problem six months down the line. At Synopsys, you will work on UCIe IP that is being designed into the next generation of chiplet-based systems, and the analysis you do will directly influence what ships.\n\nWhat You'll Be Doing\nDrive SI/PI compliance and sign-off for UCIe IP as a core member of the design team, ensuring the IP meets spec across packaging technologies and customer use cases\nRun SI/PI feasibility studies for current and next-generation UCIe IP using SPICE simulation, 3D electromagnetic field solvers, and power-aware co-simulation tools\nBuild and continuously improve SI/PI analysis flows and sign-off methodologies that support both internal design validation and customer adoption\nDefine layout constraints for UCIe interfaces across 2D and 2.5D packaging technologies, translating simulation results into actionable design rules\nDevelop SI/PI application notes, design guidelines, and reference materials that help customers implement UCIe IP successfully in their own systems\nCollaborate with design, verification, and customer engineering teams distributed across global sites to align SI/PI requirements with IP architecture and customer needs\nServe as the SI/PI technical point of contact for customer engagements, answering questions, reviewing designs, and troubleshooting signal integrity issues in real deployments\n\nThe Impact You Will Have\nShape UCIe IP architecture decisions by providing early SI/PI feedback that influences floorplanning, power delivery, and interface design before tape-out\nBuild customer confidence in Synopsys UCIe IP by delivering robust SI/PI analysis, clear documentation, and responsive technical support during evaluations and production ramps\nAccelerate customer time-to-market by creating reusable SI/PI flows, validated models, and design guidelines that reduce the guesswork in high-speed chiplet integration\nEstablish Synopsys as the SI/PI leader in the UCIe ecosystem by contributing to industry best practices and enabling successful deployments at lead customers\nEnable next-generation AI and HPC systems by ensuring that UCIe IP performs reliably at multi-gigabit data rates across diverse packaging and system configurations\nReduce design respins and late-stage failures by catching SI/PI issues early through rigorous simulation and validation during the IP development cycle\nContribute to Synopsys' mission to lead in the Era of Pervasive Intelligence by delivering the high-speed interconnect IP that powers chiplet-based architectures\n\nWhat You'll Need\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related technical field\n8+ years of hands-on experience in signal integrity, power integrity, or high-speed interface design in the semiconductor or systems industry\nStrong working knowledge of transmission line theory, S-parameters, eye diagrams, and time-domain and frequency-domain analysis techniques\nProven experience with SPICE-based circuit simulation tools and 3D electromagnetic field solvers such as HFSS, Ansys SIwave, or similar platforms\nSolid understanding of high-speed serial interfaces such as UCIe, HBM, DDR, PCIe, or Ethernet, including protocol-level awareness and physical layer design considerations\nExperience with scripting in Python or Tcl to automate simulation workflows, post-process results, or build analysis tools is a strong plus\nFamiliarity with both Linux and Windows environments for running simulations, managing files, and collaborating across toolchains\n\nWho You Are\nYou can take a customer's package stackup, run an SI analysis, and come back with specific layout recommendations, not just a pass/fail verdict\nYou are comfortable presenting SI/PI tradeoffs to architects and design leads who may not live in the frequency domain every day, and you can explain why a decision matters without losing the technical thread\nYou stay organized across multiple simulation runs, customer requests, and internal design reviews without dropping details or missing deadlines\nYou do not wait for perfect data to start analyzing, you work with what you have, document your assumptions, and refine as more information comes in\nYou push back when a design constraint does not make sense from an SI/PI perspective, and you do it in a way that moves the conversation forward instead of shutting it down\nYou are curious about new packaging technologies, simulation methods, and interface standards, and you bring that curiosity into your work without needing to be asked\n\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Solutions DFT Engineer, Staff", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-29", "url": "https://careers.synopsys.com/job/bengaluru/solutions-dft-engineer-staff/44408/101338136464", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years deep in the details of digital IC design, and you know that the difference between a chip that works and one that doesn't often comes down to decisions made during DFT planning. You are the engineer who catches those decisions early, who can look at a scan architecture and immediately see where the coverage gaps will show up three months later during silicon bring-up. You have debugged enough ATPG failures and MBIST issues to know that the best solutions start with understanding what the customer is actually trying to build, not just what they think they need.\nYou operate at the intersection of deep technical work and customer collaboration. You can spend the morning implementing a complex test access network for a multi-IP SoC and the afternoon explaining to a customer why their current flow is leaving test coverage on the table, and you are equally comfortable in both modes. You do not wait for perfect specs. You ask the right questions, prototype quickly, and iterate based on what you learn.\nAt Synopsys, you will work with customers designing some of the most complex chips in automotive, AI, and consumer electronics, and what you deliver will directly determine whether their silicon works on the first spin.\n\nWhat You'll Be Doing\nDeliver end-to-end DFT solutions for customer designs, from architecture planning and scan insertion through pattern generation, silicon bring-up, and diagnostics analysis\nImplement and validate test solutions including scan, MBIST, and IEEE 1687 architectures for complex SoCs with multiple IP blocks\nParticipate in customer design reviews to understand their flows, identify gaps, and propose specific improvements that reduce test time or increase coverage\nPrototype and validate new DFT methodologies in collaboration with Solution Architects, proving out viability before customer deployment\nProvide technical support and training to customers, including hands-on problem resolution, methodology workshops, and account-level engagement\nConduct product demonstrations, competitive benchmarking, and evaluations to help win new customers and expand adoption of Synopsys test solutions\nAnalyze silicon test data, diagnose failures, and present findings to both internal teams and customer stakeholders with clear recommendations\n\nThe Impact You Will Have\nEnable first-time silicon success for customers by delivering robust, validated DFT solutions that catch issues before tapeout\nAccelerate time-to-market for automotive and consumer electronics customers by optimizing their test flows and reducing pattern generation cycles\nExpand Synopsys' footprint in next-generation test technologies by proving out new methodologies that become standard practice across accounts\nBuild long-term customer relationships that turn one-time engagements into strategic partnerships, increasing account value and retention\nRaise the technical capability of customer teams through training and knowledge transfer, creating a multiplier effect beyond individual projects\nShape the direction of Synopsys test products by feeding real-world customer challenges and use cases back to R&D teams\nContribute to measurable improvements in test coverage, pattern count reduction, and silicon yield across diverse customer programs\n\nWhat You'll Need\nBachelor's degree with 7+ years or Master's degree with 5+ years in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field\nHands-on experience with RTL coding, DFT insertion, ATPG pattern generation, and silicon bring-up for digital ICs\nDeep knowledge of scan architectures, fault models, test access networks, and IEEE standards including 1149.1, 1500, and 1687\nProven ability to handle scan implementation and validation for large, multi-IP SoCs with complex hierarchies and multiple clock domains\nExperience with MBIST concepts, architecture planning, and integration in automotive or safety-critical design environments is a strong plus\nFamiliarity with industry-standard DFT tools and flows, exposure to Synopsys TetraMAX, DFT Compiler, or MBIST Architect is valuable\nStrong written and verbal communication skills to translate technical concepts for both engineering teams and non-technical stakeholders\n\nWho You Are\nYou can walk into a customer design review, absorb their methodology in real time, and walk out with three specific recommendations they can act on next week\nYou are comfortable working independently on complex technical problems while knowing when to pull in a Solution Architect or R&D engineer for a second opinion\nYou manage multiple customer engagements at once without dropping threads, keeping track of where each project stands and what needs to happen next\nYou prototype quickly and iterate based on feedback, treating customer pushback as useful signal rather than friction\nYou explain tradeoffs clearly, whether you are talking to a junior engineer learning DFT or a VP trying to understand why test time matters for their product schedule\nYou stay current on emerging test standards and methodologies because you are genuinely curious about where the technology is headed, not just what you need to know today\n\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.", "jd_status": "stored"}, {"title": "Layout Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-29", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018346", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\nLayout Engineers develop and prepare multi-dimensional layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by designers. Their work may be completed through use of CAD or other computerized equipment. Layour engineers will checks dimensions, write specifications, and verify the completed drawings, artwork or digitized plots. A bachelor's degree in engineering is typically required.\n\nHiring manager, please answer a few of the following prompts to give applicants a good idea of the role and delete the rest. \n\n A typical day-to-day in this role is… \n\n The team is a great team because… \n\n In this role, you will work most closely with…\n\n Some of the people you'll get to work with include…\n\n The most challenging aspect of this role is…\n\n The best thing about this role is…\n\n An example of a project you would work on in this role is…\n\n During the first 30 days of this role, you will…\n\n Something interesting about this role that wasn't in the job description is…\n\n The key to succeeding in this role is…\n\n The steepest learning curve in this role is…\n\n Our vision for the team is… \n\n Key responsibilities of this role include…\n\n \n\n \n\n \n\n \n\nYou would be great for this role if you've previously… (list experiences or roles here)\n\nQualifications\nMinimum Requirements:\n\nMinimum education (ie bachelor's degree in electrical engineering).\n\nCumulative 3.0/4.0 GPA or higher\n\n \n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "EDA Simulation Automation Engineer", "company": "onsemi", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-09-29", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506618", "is_hardware": true, "platform": "oracle", "jd_text": "Role Summary\n\nWe are looking for a hands-on EDA Simulation Automation Engineer to join our AI-native product development team at onsemi. The role sits at the intersection of power semiconductor module simulation and engineering automation: you bring deep, practical experience running electrical, thermal, and mechanical simulations across industry-standard EDA tools, and you partner with our software and AI agent engineering team to codify that expertise into repeatable, automatable workflows. Today, every design cycle waits on a few subject-matter experts to configure tools, run simulations, and extract KPIs by hand. Your job is to break that bottleneck by defining standardized inputs, outputs, and KPI extraction logic that our platform can orchestrate and scale across engineers, teams, and products. You will also identify where commercial EDA tool licensing or concurrency limits constrain simulation throughput, and research, evaluate, or build custom and open-source alternatives that can be integrated into the platform's automation pipeline.\n\nSuccess Expectations\n\nYou would become the platform's trusted domain authority for simulation configuration, execution, and KPI extraction — defining clear, documented automation contracts for each supported EDA tool, validating that automated and agent-driven simulation runs match expert-derived results, and steadily expanding the set of tools and KPIs the platform can orchestrate without manual SME intervention on every cycle.\n\n#LI-VS1\n\nResponsibilities\nOwn hands-on simulation execution for power module characterization across electrical, thermal, and mechanical domains using tools such as Ansys Discovery, Q3D, HFSS, IcePak, Mechanical, OptiSLang, Cadence Virtuoso, Spectre, Calibre (DRC/LVS/PEX), SIMetrix/SIMPLIS, and PLECS.\n\nDefine and validate KPI extraction logic from raw simulation outputs, including loop inductance, on-resistance (RDS(on)), switching energy, junction temperature (Tj,max), thermal resistance (Rth), and power-cycling lifetime.\n\nDesign standardized, parameterized test-bench definitions and post-processing rules that convert raw tool outputs into compliance-ready KPI values.\n\nDocument tool-specific configuration, input/output file schemas, and scripting hooks (Python, tool APIs, batch/command-line modes) so engineering can automate configuration, dispatch, and result ingestion for each tool.\n\nPartner with software and SDET engineers to build and validate simulation regression pipelines, ensuring automated or agent-driven runs reproduce trusted, manually-derived golden results.\n\nCapture and formalize simulation best practices, known-good configurations, and troubleshooting knowledge that today lives only with individual SMEs, so it can be reused across teams and products.\n\nSupport AI agent tool-calling integrations for EDA tools by defining safe, well-scoped automation boundaries, required parameters, and expected outputs for each tool.\n\nResearch, evaluate, and prototype custom or open-source alternatives to commercial EDA tools where per-seat licensing or concurrency limits throttle agentic, parallelized simulation throughput, and propose where such alternatives can safely substitute or supplement licensed tools.\n\nReview and sign off on automated simulation results and generated KPI/compliance reports against domain expectations before release certification.\n\nCollaborate with model-generation and layout/GDS teams to ensure electrical and thermal models feeding simulations remain accurate and traceable.\n\nProvide simulation domain expertise during project scoping, test-suite definition, and requirements-to-KPI mapping discussions.\n\n#LI-VS1\n\nQualifications\n3 to 5 years of hands-on experience running simulations for power semiconductor or power module design, with direct, practical use of at least two or three of: Ansys Discovery, Q3D, HFSS, IcePak, Mechanical, Cadence Virtuoso, Spectre, Calibre, SIMetrix/SIMPLIS, or PLECS.\n\nSolid understanding of power module electrical, thermal, and mechanical characterization and the KPIs engineers derive from each (parasitics, loop inductance, resistance, thermal resistance, junction temperature, lifetime/reliability metrics).\n\nPractical experience configuring simulation inputs (parameters, test benches, boundary conditions) and interpreting/post-processing raw simulation outputs into engineering KPIs.\n\nScripting ability in Python sufficient to automate tool configuration, batch execution, and output parsing.\n\nWorking knowledge of GDS/layout-based design flows and how layout, parasitic extraction, and model generation feed downstream simulation.\n\nAbility to translate tribal SME knowledge into clear, documented, repeatable procedures that a software or AI agent engineer can implement without deep tool expertise.\n\nComfort researching and evaluating open-source, custom-built, or alternative simulation/extraction methods to work around commercial tool licensing or concurrency bottlenecks.\n\nStrong attention to detail in validating automated results against known-good manual runs, with a rigorous approach to signing off on release-quality simulation data.\n\nGood collaboration and communication skills to work closely with software engineers, SDETs, and AI coding agents on a shared automation roadmap.\n\n#LI-VS1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Staff Design Verification Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-09-29", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506784", "is_hardware": true, "platform": "oracle", "jd_text": "We are seeking an experienced Staff ASIC/SoC Verification Engineer to join our dynamic and fast‑paced engineering team. In this role, you will be responsible for ensuring the functional correctness, robustness, and overall quality of our cutting‑edge semiconductor and SoC designs. If you thrive in a collaborative environment and enjoy solving complex technical challenges, this opportunity is an excellent fit.\n\n#LI-RT1\n\nResponsibilities\nResponsibilities:\nVerification Planning and Execution:Develop and execute comprehensive verification plans.\n \nClose verification with coverage closure, ensuring high-quality results.\nApply standard ASIC verification techniques, including test planning, testbench creation, code and functional coverage, directed and random stimulus generation, and assertions.\n\nTestbench Development:Create and enhance testbenches using SystemVerilog (OVM/UVM) or other standard testbench languages.\nImplement reusable Verification IP (VIP) components.\nCollaborate with third-party VIP providers.\n\nMethodology and Flows:Demonstrate a solid understanding of ASIC design and verification methodologies.\nApply object-oriented programming principles effectively.\nImplement constraint random verification methodology.\n\nTechnical Skills:Proficiency in SystemVerilog (OVM/UVM) and other relevant languages (C/C++, Perl, Tcl, Python, Verilog PLI).\nFamiliarity with industry standards (e.g., I2C/SPI).\nExperience with low-power verification using UPF (Unified Power Format) is a plus.\nKnowledge of formal verification techniques is advantageous.\n\nCollaboration and Communication:Work effectively with internal teams and external customers.\nStrong written and verbal communication skills.\nInitiative, analytical problem-solving abilities, and adaptability within a diverse team environment.\n\nQualifications\nRequired Qualifications\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.\n10 Years of experience in SoC/IP verification,.\nStrong expertise in SystemVerilog, UVM, and advanced verification methodologies.\nHands-on experience with ARM-based SoC architectures, AMBA protocols (AXI/AHB/APB), and system-level interactions.\nProven ability to build reusable, scalable testbench architectures.\nSolid understanding of test planning, coverage-driven verification, and verification metrics.\nExperience with GLS, timing verification, and debug.\nKnowledge of power-aware verification (UPF/CPF).\nStrong scripting and automation skills (Python, Perl, Shell, Make, etc.).\nExposure to AI/ML techniques applied to verification (e.g., intelligent stimulus generation, failure triage, coverage optimization).\nExcellent problem-solving, debugging, and communication skills.\n#LI-RT1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Senior Engineer -Low Power CLP", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-29", "url": "https://careers.arm.com/job/bengaluru/senior-engineer-low-power-clp/33099/101307117584", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Description: In Arm's Solutions Engineering group, our primary focus extends beyond the development of advanced System-on-Chips (SoCs). In the endeavour to deliver a quality silicon we need to ensure all our signoff checks across various domains are diligently performed. Delivering quality silicon leads to quality rewards and every effort and skill is recognized and appreciated at ARM. Our responsibilities also encompass improvising methodologies, influencing EDA tools and build a knowledge base which will help in our product design. Learning and sharing knowledge is part of ARM culture and is very much appreciated and encouraged. If your interested in working with a team of collaborative and smart engineers responsible for validating RTL-to-Gate and Gate-to-GDS implementations, ensuring power intent correctness, and enabling high-quality silicon tapeout\nResponsibilities:\nLow Power structural check\nPerform low-power verification using Cadence Conformal Low Power (CLP) or Synopsys VCLP.\nVerify and validate UPF implementation across RTL, netlist, and physical design stages.\nPerform power-aware equivalence checking and resolve identified issues.\nAnalyze, debug, and resolve CLP structural, rule-based, and power-aware verification failures.\nImplement SoC-level low-power structural checks and debug issues through closure.\nLogical Equivalence Checking (LEC/Formality):\nPerform RTL-to-Synthesis, Synthesis-to-P&R, and ECO logic equivalence verification using Cadence Conformal LEC.\nAnalyze, debug, and resolve non-equivalences and aborts across different stages of the design flow.\nDevelop, automate, and maintain robust LEC flows and signoff methodologies.\nDrive LEC failure resolution and closure, and generate comprehensive signoff reports.\nImplement and debug SoC-level flat LEC runs through signoff.\nMethodology and Automation:\nDevelop TCL, Perl, and Python scripts to automate verification tasks and improve productivity.\nBuild and maintain reusable verification flows and debug utilities to improve efficiency and scalability.\nDrive methodology enhancements for low-power verification signoff and efficient resolution of verification aborts.\nRequired Skills and Experience :\nWe are looking for a candidate with 5+ years of relevant experience in logical signoff and low-power structural verification for sophisticated SoC and IP development programs.\nStrong experience with low-power design and verification, including hands-on knowledge of UPF/CPF and SystemVerilog.\nHands-on experience with low-power verification tools such as Cadence Conformal Low Power (CLP) or Synopsys VCLP.\nExperience with Logic Equivalence Checking (LEC) and power-aware LEC, with strong skills in analyzing and resolving verification failures.\nAbility to effectively debug CLP/VCLP and LEC issues and drive them through closure.\nUnderstanding of synthesis and Place & Route (P&R) flows is an advantage.\nAbility to collaborate across design, verification, and implementation teams to support successful signoff of complex SoC and IP designs.\n#LI-BB1\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Layout Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-29", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018284", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\nLayout Engineers develop and prepare multi-dimensional layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by designers. Their work may be completed through use of CAD or other computerized equipment. Layour engineers will checks dimensions, write specifications, and verify the completed drawings, artwork or digitized plots. A bachelor's degree in engineering is typically required.\n\nHiring manager, please answer a few of the following prompts to give applicants a good idea of the role and delete the rest. \n\n A typical day-to-day in this role is… \n\n The team is a great team because… \n\n In this role, you will work most closely with…\n\n Some of the people you'll get to work with include…\n\n The most challenging aspect of this role is…\n\n The best thing about this role is…\n\n An example of a project you would work on in this role is…\n\n During the first 30 days of this role, you will…\n\n Something interesting about this role that wasn't in the job description is…\n\n The key to succeeding in this role is…\n\n The steepest learning curve in this role is…\n\n Our vision for the team is… \n\n Key responsibilities of this role include…\n\n \n\n \n\n \n\n \n\nYou would be great for this role if you've previously… (list experiences or roles here)\n\nQualifications\nMinimum Requirements:\n\nMinimum education (ie bachelor's degree in electrical engineering).\n\nCumulative 3.0/4.0 GPA or higher\n\n \n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Senior System Integration and Feature Validation Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-09-29", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-System-Integration-and-Feature-Validation-Engineer_JR2025190-1", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA pioneered graphics and is now the global AI leader, delivering breakthrough performance and efficiency across every important industry. As an NVIDIAN, you will tackle problems that lie between architecture, silicon, firmware, software, and production. Your judgment in ambiguous, cross-team feature integration determines whether a program ships on schedule.\n\nNVIDIA’s Silicon Co-Design Group is looking for a flexible hardware engineer to join its System Features and System Integration teams. Our responsibilities cover everything from architecture to bring-up and release. We focus on feature integration, debugging, validation, and productization for all NVIDIA GPU, CPU, Client and SoC products. Small decisions in feature integration significantly affect boot, clocks, DVFS, system controllers, pstates, circuits, and all areas where hardware and software meet. This role is not about checklist compliance or feature sign-off. Instead, it is where multi-team feature failures are either root-caused and resolved or cause program delays. The two most critical challenges in this position are:\n\nWhat you will be doing:\nEnd to End responsibility for the integration and product development of system features across — boot, clocks, DVFS, performance and power system controllers, and certain circuits.\n\nLead debugging and root-cause resolution on the most challenging cross-stack feature issues covering silicon, firmware, driver, and platform — delivering productized fixes and reusable workarounds.\n\nBuild and deploy AI-enabled workflows for feature validation, debug, and triage — with explicit guardrails and measurable impact on cycle time, coverage, or escape rate.\n\nSupport silicon bring-up, feature deployment, and GPU/SoC qualification through feature checks, PVT stress and stability testing, and lab debug.\n\nBuild the tools, scripts, and infrastructure the team relies on — and improve validation and productization processes for greater quality and efficiency.\n\nPartner with globally distributed teams — architecture, ASIC, firmware, driver, software, and multiple bring-up teams.\n\nWhat we need to see:\nBTech / BE or MTech / ME in Electronics, Electrical, or Computer Engineering along with over 5 years of experience in post-silicon bring-up, system integration, or feature design and validation for released GPU, CPU, or SoC products. At least once, you should have diagnosed a vague, cross-team feature failure and delivered a finalized fix.\n\nStrong end-to-end understanding of hardware, firmware, and software interaction — with fundamentals in board and system development, DVFS, control loops, SI/PI, timing, clocking, high-speed I/O, PVT, and thermal — and hands-on silicon, board, and lab-debug muscle memory.\n\nPractical understanding of GPU, CPU, or SoC architectures within at least one of PC, datacenter, or automotive environments — proven experience leading efforts to address unclear issues spanning multiple teams.\n\nProven validation approach using smart AI technology you designed or scaled, not only used — with adoption beyond yourself and measurable impact on debug velocity, coverage, or escape rate. You can detail the limits you set and where smart AI tools may introduce hazards in your workflow.\n\nWays to stand out from the crowd:\nA history of building reusable feature-integration methodology, debug playbooks, or validation frameworks that other programs or teams adopted. These are backed by patents, conference papers, or talks where you were encouraged to present.\n\nPractical subsystem expertise in DVFS, boot / clock / reset, power management controllers, high-speed I/O, or thermal — including failure modes, debug instrumentation, and the compromises encountered during production.\n\nExperience partnering deeply with a counterpart team in another major engineering hub — shared on-call, shared metrics, and shared culture across geographies.\n\nAI work that goes beyond personal-copilot uses agentic workflows, RAG-grounded debug assistants, machine learning-based anomaly detection, or automated triage — deployed at team scope with adoption metrics.\n\nNVIDIA is the world leader in accelerated computing, and our work powers AI, gaming, robotics, autonomous systems, and scientific discovery. We invest in our people with competitive benefits, flexible time off, and continuous learning, and we build a team where everyone can do their best work. Come help us build the features that make NVIDIA silicon the reason customers ship on time!\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Hardware Engineer, Silicon Power & Productization", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-09-29", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Hardware-Engineer--Silicon-Power---Productization_JR2026564", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been redefining computer graphics, PC gaming, and accelerated computing for more than 25 years. Today, we are tapping into the unlimited potential of AI to define the next era of computing. As an NVIDIAN, you will address challenges spanning architecture, silicon, firmware, software, and production — and excellent judgment matters as much as technical depth!\nEvery major NVIDIA silicon product family—from the chips powering AI and datacentre systems to gaming, professional, embedded, and automotive platforms—passes through our productization work on its way to production.\n \nNVIDIA’s Silicon Co-Design Productization team works from pre-silicon strategy and feature development through bring-up, characterization, correlation, and optimization. Our charter spans power & performance modelling, bring up & tuning of power & and thermal controllers; and system-level optimization that ultimately shape how NVIDIA products are configured, binned, specified, and shipped.\n\nWhat you'll be doing:\nDrive silicon power productization from pre-silicon planning through bring-up and production, including test strategy, feature readiness, characterization, and optimization.\nPartner with architecture and design teams to identify improvements, validate features, and help translate them into production-ready solutions.\nCharacterize and tune controller behavior across workloads, operating conditions, silicon variation, and product power and thermal limits.\nBuild power and performance models and characterization methodologies that decide silicon binning, product specifications, productization decisions, and customer guidance.\nUse AI/ML and data-driven methods to analyse characterization & telemetry data, identify anomalies & trends; and accelerate debug across silicon, board, power delivery, firmware, and software.\n\nWhat we need to see:\nBachelors/ Masters in Electronics Engineering, Electrical Engineering, or a related field, or equivalent experience.\n3+ years of proven experience in silicon bring-up, characterization, validation, productization, or a related hardware field.\nUnderstanding of silicon power and performance, including process technology, voltage, frequency, workloads, and operating conditions.\nExperience with system-level hardware debugging and interactions across silicon, board hardware, firmware & software.\nData analysis and problem-solving skills—you can turn measurements into hypotheses and design experiments to test them.\n\nWays to stand out from the crowd:\nExperience with Windows/Linux systems, low-power states, power controllers, silicon power, device physics, or power delivery.\nContributions that improved silicon bring-up, characterization coverage, pre/post-silicon correlation, debug efficiency, or productization methodology.\nExperience with power modelling, silicon binning, productization.\nExperience applying AI/ML to engineering workflows, such as debug assistants, characterization analytics, or automated anomaly and trend detection.\n\nEach new process node and architecture brings power challenges that simulation alone cannot answer. This team works where architecture, design, silicon, systems, firmware, and software meet—with the opportunity to influence both how new silicon is built and how it ultimately ships. If you want to get close to new silicon, use data and AI tools to solve problems across engineering boundaries, and help turn first silicon into products at scale, we'd like to hear from you.\n \nWith competitive salaries, generous benefits package and an outstanding culture, we are broadly recognized as one of the technology world’s most desirable employers. We are an equal-opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, colour, national origin, sex, gender, gender expression, sexual orientation, age, marital status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Formal Verification Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-29", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Formal-Verification-Engineer_JR0286327-1", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nIntel is seeking a Formal Verification Engineer for the Silicon Chassis team. This role focuses on applying formal methods to exhaustively verify our interconnect fabric, protocol bridges, and link-layer logic. You will own end-to-end formal verification, from property specification through proof convergence - across multiple protocol domains. You will work closely with architecture, design, and software teams and are expected to contribute across traditional discipline boundaries. This role requires strong Formal depth, solid protocol knowledge, hands-on coding strength, and growing ability to mentor junior engineers. AI-assisted workflows are part of everyday development here. Consistent execution against schedule and quality goals is expected.\n\nKey Responsibilities\n- Develop and execute comprehensive formal verification test and coverage plans, including the definition of scope, strategy, and techniques.\n- Create abstraction models to enable convergence on designs and apply abstraction techniques to formal verification.\n- Generate and validate formal proofs to implement verification plans and resolve failing tests through corrective measures.\n- Collaborate across architecture, RTL design, and physical design teams to improve the verification of complex architectural and microarchitectural features.\n- Maintain and enhance existing formal verification infrastructure, tools, and methodologies.\n- Simplify and model problems using architecture modeling techniques to verify protocols and architectures.\n- Utilize tools to formally prove design protocols, resolve BDD complexity, and optimize data paths.\n- Document test plans, track verification progress, and drive technical reviews with cross-functional teams.\n\nQualifications:\nMinimum Qualifications\n- BS/MS in Electrical Engineering, Computer Science, or related field, with 5+ years of relevant experience in formal verification.\n- Proficiency in formal verification tools and methodologies, including model checking and equivalence checking.\n- Strong knowledge of System Verilog, Verilog, and logic/microarchitecture fundamentals.\n- Experience with abstraction modeling, simulation techniques, and convergence strategies.\n- Familiarity with Binary Decision Diagrams (BDD) and Data Flow Graphs (DFG).\n\nPreferred Qualifications\n- Proven ability to apply problem-solving skills to resolve complex architectural and verification challenges.\n- Strong collaboration and teamwork skills, with experience working in cross-functional teams.\n- Excellent technical documentation and communication abilities.\n- Passion for driving innovation and advancing the state of verification tools and methodologies.\n\nIf you are excited about the opportunity to work on cutting-edge technology and contribute to shaping the future of computing, we encourage you to apply and join Intel's journey of innovation and excellence.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Chip Power Estimation Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-09-29", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Chip-Power-Estimation-Engineer_JR2026671", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking a passionate, creative, and highly motivated engineer to work on architectural power estimation for the world’s leading GPUs and SOCs. In this position, the responsibility includes development of advanced power models to estimate chip and board power under product driven use cases. You are expected to understand the high-level chip architecture, application use-cases, low power design techniques, process technology aspects which impact dynamic and leakage power, develop the estimation infrastructure, estimate power consumption under various scenarios. You will be working with architecture, design, synthesis, timing, circuit, and post silicon teams to accomplish your tasks.\n \nThis position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n \nWhat you’ll be doing:\nArchitecture, development and correlation of power estimation models/tools for NVIDIA's chips\nHelp architect and develop power models for use-cases, Idle power and IO power.\nChip in to design the tools based on these models and their testing methodology/infrastructures\nCorrelate and Calibrate the power models using measured silicon data\nAnalyze and help decide the chip configuration and process technology options to optimize power/performance for NVIDIA's upcoming chips\nHelp study and contribute to Performance/Watt improvement ideas for NVIDIA's GPUs and SOCs\n \nWhat we need to see:\nB.Tech./M.Tech and 1+ years of experience related to Power / Performance estimation and optimization techniques\nStrong fundamentals in power including transistor-level leakage/dynamic characteristics of VLSI circuits\nFamiliarity with low power design techniques such as multi VT, Clock gating, Power gating, and Dynamic Voltage-Frequency Scaling (DVFS)\nStrong background in power estimation techniques, flows and algorithms\nGood programming skills - Python preferred. Good skills with object-oriented programming and design.\n \nWays to stand out from the crowd:\nExposure to lab setup including power measurement equipment such as scope/DAQ with ability to analyze board level power issues is a plus\nExposure to power analysis EDA tools such as PTPX/EPS\nGood communication skills & desire to work as a great teammate\n \nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.", "jd_status": "stored"}, {"title": "CPU/Cores Post‑Silicon Validation (Security)", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-28T18:09:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92799/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. Cores Post‑Silicon Validation (Security) THE ROLE The AMD Cores Validation team is looking for a highly motivated engineer to drive post-silicon validation of CPU security features across next-generation x86 processor products. The engineer will be responsible for validating architectural and microarchitectural security capabilities, developing security-focused test methodologies, executing validation plans, and driving complex debug activities from first silicon through production readiness. This role provides an opportunity to work closely with Architecture, Design, Firmware, Security, and Product Engineering teams to ensure robust implementation of processor security technologies. KEY RESPONSIBILITIES Develop and execute post-silicon validation plans for CPU security features. Validate architectural security capabilities including: Secure Virtual Machine (SVM) SEV / SEV-ES / SEV-SNP Memory encryption technologies Secure Boot Trusted execution and attestation mechanisms Speculation and side-channel mitigation features Virtualization security extensions Design directed and stress workloads to verify security functionality, robustness, and corner-case behavior. Perform silicon bring-up and feature enablement on pre-production platforms. Debug failures spanning: CPU cores and microarchitecture Microcode (uCode) BIOS/Firmware Security processors and firmware Analyze logs, machine check data, MSRs, traces, and hardware debug information to isolate root causes. Collaborate with Design, Architecture, Security, and Firmware teams to drive issue resolution. Develop automation infrastructure to improve validation efficiency, coverage, and regression execution. Track validation coverage, defect metrics, and readiness criteria for product milestones. REQUIRED QUALIFICATIONS Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, Computer Science, or related field. Strong understanding of computer architecture and x86 processors. Good knowledge of operating systems internals and virtualization technologies. Familiarity with processor security concepts such as: Encryption Authentication Secure boot flows Trust chains Isolation mechanisms Virtualization security Experience with silicon validation, system validation, or hardware validation. Strong debug and root-cause analysis skills. Proficiency in Python, C/C++, or scripting languages for automation. Experience working in Linux and Windows environments. PREFERRED QUALIFICATIONS Prior experience in CPU cores post-silicon validation. Experience validating security IPs or processor security features. Knowledge of SEV, SNP, TSME, SME, Secure Boot, PSP/ASP architectures, or trusted execution technologies. Understanding of cache hierarchy, memory management, coherency protocols, and microarchitectural behavior. Familiarity with microcode, BIOS, firmware, and platform bring-up flows. Exposure to security testing methodologies including penetration, negative, and adversarial validation approaches. Experience with post-silicon debug tools, JTAG, trace, and performance monitoring infrastructure.    ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering or related field #LI-DB2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Principal Engineer- Design Verification ", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-28T09:06:36.342000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000152116473-senior-principal-engineer-design-verification-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Job Summary:\nWe are seeking a highly experienced Verification Lead to drive the verification strategy and execution for next-generation UA Link Switch products within the Memory Interface Division (MID). The candidate will be responsible for leading verification efforts across complex digital subsystems and SoCs, ensuring first-silicon success for high-performance, high-bandwidth interconnect and switching solutions.\nThe ideal candidate will possess deep expertise in modern verification methodologies and extensive experience verifying large-scale, high-speed digital designs involving switching fabrics, SerDes-based interfaces, memory subsystems, and complex SoC architectures.\nKey Responsibilities\nDefine and own the verification strategy, methodology, and execution plan for UA Link Switch products.\nLead verification architecture, testbench development, coverage planning, and verification closure activities.\nBuild and drive scalable UVM/ System Verilog-based verification environments for complex SoC and subsystem designs.\nCollaborate closely with architecture, design, firmware, system validation, and silicon bring-up teams to ensure comprehensive verification coverage.\nDevelop verification plans covering functionality, performance, reliability, error handling, and corner-case scenarios.\nDrive debug and root-cause analysis of design and verification issues.\nDefine and track verification metrics including functional coverage, code coverage, assertions, and regression quality.\nLead verification reviews, sign-off activities, and silicon readiness assessments.\nMentor verification engineers and establish best practices across the organization.\n\nBachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or related field.\n18+ years of experience in ASIC/SoC verification.\nProven leadership experience delivering complex SoC or subsystem verification programs from architecture through tape-out.\nStrong expertise in:System Verilog, UVM, Assertion-Based Verification (SVA), Functional and Code Coverage Methodologies, Simulation and Regression Infrastructure and Verification Closure Techniques.\n\nExperience verifying large-scale digital systems involving:High-speed digital designs, SoCs and subsystem integration, Switching fabrics and interconnect architectures, Memory controllers and memory subsystems and Microcontroller-based systems.\n\nStrong understanding of RTL design concepts and hardware architecture.\nDemonstrated ability to drive cross-functional technical teams and influence architecture and design decisions.\nPreferred Qualifications\nPrior verification experience in one or more of the following:High-speed SerDes-based systems\nSwitching fabrics and packet-based architectures\nMemory interface technologies\nAI/HPC interconnect solutions\nPCIe, CXL, Ethernet, UALink, UCIe, or similar protocols\n\nExperience with formal verification, emulation, and FPGA prototyping.\nFamiliarity with performance verification and system-level validation methodologies.\nExperience debugging silicon issues and supporting post-silicon validation.\nHands-on experience with mixed hardware/firmware verification environments.\nExperience leading geographically distributed verification teams.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Lead Full-chip STA and timing signoff  Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-28T08:48:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92750/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. THE ROLE: We are seeking an experienced Full Chip SoC Timing Lead in ASIC/SoC design implementation and timing closure. The ideal candidate will lead full-chip timing activities from synthesis through place-and-route, signoff, and tapeout for complex SoCs in advanced technology nodes. This role requires deep expertise in STA, timing constraints, MMMC flows, SI/crosstalk analysis, ECO closure, and cross-functional collaboration with RTL, PD, CTS, DFT, power, and signoff teams. THE PERSON: You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: Lead full-chip timing closure for complex SoC/ASIC designs across all modes and corners. Own and drive timing signoff from synthesis to final tapeout. Develop, validate, and maintain timing constraints including SDC for full-chip and block-level integration. Perform and review static timing analysis (STA) for setup, hold, recovery, removal, clock gating, and async paths. Drive MMMC timing methodology and ensure robust timing convergence across PVT corners. Work closely with physical design teams on floorplanning, placement, CTS, routing, and post-route timing optimization. Analyze and resolve timing violations related to datapath, clock path, cross-talk, noise, OCV/AOCV/POCV, derates, and variation effects. Lead timing ECO strategies and execute closure with minimal impact to power, area, and performance. Collaborate with RTL/design teams to identify architectural or logic changes required for timing improvement. Coordinate with IP/block owners for timing budgeting, interface timing closure, and hierarchical timing signoff. Ensure signoff quality using industry-standard tools and methodologies. Drive correlation between implementation timing and signoff timing. Lead tapeout readiness reviews and provide timing risk assessment to program leadership. Mentor junior engineers and define best practices for timing methodology and closure. PREFERRED EXPERIENCE: Bachelor’s or Master’s degree in Electronics / Electrical Engineering / VLSI / Microelectronics / Computer Engineering. 12+ years of hands-on experience in ASIC/SoC timing analysis and timing closure. Strong expertise in full-chip STA and timing signoff for large-scale SoCs. Proven experience in advanced technology nodes (such as 7nm, 5nm, 3nm or similar). Strong knowledge of synthesis, place-and-route, extraction, and signoff flows. Experience with timing budgeting and hierarchical/full-chip integration. Solid understanding of clocking architecture, CDC implications, and timing exception handling. Ability to debug complex timing issues and drive closure under aggressive schedule targets. Strong communication, stakeholder management, and leadership skills. #LI-SR4 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Principal/Sr. Director- SoC/Chip Lead", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-28T07:50:42.834000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000152098819-senior-principal-sr-director-soc-chip-lead", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Own end-to-end technical leadership and execution of complex SoC programs from architecture through silicon production.\nDrive SoC planning, integration strategy, execution schedules, risk management, and tape-out readiness.\nLead cross-functional teams across digital design, verification, physical design, DFT, firmware, validation, packaging, and product engineering.\nDefine chip-level architecture, integration requirements, performance targets, and power/area objectives.\nDrive technical decision-making and trade-off analysis across architecture, implementation, and product requirements.\nOversee subsystem and IP integration, ensuring successful deployment of complex multi-domain SoCs.\nPartner with analog and SerDes teams to integrate high-speed interfaces and mixed-signal subsystems into the overall chip architecture.\nLead design reviews, execution reviews, silicon readiness assessments, and post-silicon debug activities.\nDrive issue resolution across the development lifecycle and ensure successful first-pass silicon execution.\nMentor senior engineers and provide technical leadership across multiple engineering organizations.\n\nBachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or related discipline.\n20+ years of semiconductor industry experience with substantial leadership responsibility.\nProven experience as a Chip Lead, SoC Lead, Technical Program Lead, or equivalent role for large-scale ASIC/SoC products.\nDemonstrated success leading advanced-node SoCs, preferably at 3nm and/or 5nm technology nodes.\nDeep understanding of SoC architecture, integration methodologies, and full-chip development flows.\nStrong experience working across:RTL Design, Design Verification, Physical Design, DFT, Static Timing Analysis, Low-Power Design Methodologies and Silicon Bring-up and Productization.\n\nExperience managing complex schedules, technical dependencies, and cross-functional execution across global teams.\nStrong communication, stakeholder management, and engineering leadership skills.\nPreferred Qualifications: \nPrior experience with:High-performance switching silicon\nNetwork-on-Chip (NoC) architectures\nData movement and interconnect fabrics\nHigh-bandwidth memory-centric systems\nComplex multi-die or chiplet-based architectures\n\nHands-on experience integrating:High-speed SerDes interfaces, Analog front-end (AFE) subsystems, Mixed-signal IPs and Advanced PHY technologies.\n\nExperience with high-bandwidth and low-latency interconnect technologies.\nKnowledge of packaging technologies and signal integrity considerations for high-speed systems.\nExperience in AI, HPC, networking, connectivity, data-center, or memory infrastructure products.\nPrior exposure to UALink, Ethernet switching, switch fabrics, or similar high-performance interconnect technologies is highly desirable.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "SOC Debug tools validation Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-28T06:50:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92730/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. SOC Debug tools validation Engineer: THE ROLE: The right engineer will drive the success of power IP (Intellectual Property) and features in AMD (Advanced Micro Devices) products through leadership & coordination, resolution of technical dependencies, and achievement of schedule commits. This is a high-visibility and widely multi-functional role, spanning pre-silicon architecture to post-silicon implementation & product delivery.   THE PERSON: The person should have hunger for understanding newer technologies and willing to take the untrodden path. The candidate should be able to work independently and also guide the team (as needed). The candidate should be able to communicate (both oral and written) and put across his ideas effectively. KEY RESPONSIBILITIES: Own the multi-functional validation of AMD Silicon Debug Tools products Ability to create Test strategy, Test plan and Test execution Work under minimal supervision Lead Quality assurance tasks and enhance product quality Work across engineering teams and subject areas spanning silicon, firmware, hardware, and software Coordinate debug of issues and drive them to closure Pull together meetings, set up clear agendas and follow up on action items Deliver regular progress updates toward program goals Make tough decisions such as priority calls based on partial or incomplete data   Proactively drive continuous improvement for Debug Tools and performance activities Must be a self-starter, and able to independently drive tasks to completion Work with the stakeholders to gather and understand the testing requirements, define a test plan/strategy and responsible for the execution of the test plans Domain expert who can develop/use test tools, automation scripts and frameworks for product testing and drive process initiatives, understand customer use case and configurations Be a technical mentor and leader for the team and independently drive tasks to closure by possessing strong debugging & troubleshooting skills Design and Develop test cases for new or existing features in a product, extract test cases from bug reports Responsible for the installation and maintenance of the test harness/environment on various platforms Analyze and validate tests results- create reports of bug failures, validate bug fixes, follow up with stakeholders to ensure closure of bug reports, participate in debug and triage activities PREFERRED EXPERIENCE: Product development/validation or systems engineering background with hardware platforms and their software & firmware ecosystems Familiarity with x86 Debug Tools ,DFT (Design for Testability) Good understanding of DFT /JTAG 1149.x / BMC (Baseboard management controller) Experience in any test automation tools Familiarity with Windows and Linux Excellent trouble shooting and debugging techniques with attention to detail Experience with standard automation and scripting (Shell programming/Ruby/Perl/Python) Knowledge on test tools (Coverage tools / Security testing tools / Performance / API testing and stress testing techniques) Experience in maintaining lab infrastructure by Setting up, Configuring and troubleshooting test environment (hardware, software) Sound Knowledge on Computer architecture, micro controller/microprocessor Experienced in configuring virtual machines, assembling systems, creating dual / multi-boot systems etc. Strong analytical and problem-solving skills Excellent verbal and written communication skills. Experience in functional and regression test automation of web, desktop apps and Service APIs Excellent interpersonal, organizational, analytical, planning, and technical leadership skills Excellent verbal communication and written, presentation skills ACADEMIC CREDENTIALS: MS / M Tech / BE/ in Electronics and Communication/Computer Engineering Should have total relevant work experience of minimum 8+ years #LI-Hybrid #LI-RR1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "PD Clocking Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-28T06:24:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92545/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. Role Summary Own and drive clocking and Physical Design (PnR) methodologies for complex SoC/ASIC designs. Responsible for developing, validating, and maintaining implementation flows, clock-tree methodologies, timing correlation, QoR convergence strategies, and automation frameworks used across multiple projects. Key Responsibilities Own end-to-end clocking methodology including CTS architecture, clock latency/skew management, clock QoR reviews, and timing convergence strategies. Develop, certify, and maintain PnR implementation flows across technology nodes and design styles. Drive flow correlation between Tile PnR, Full-Chip Timing (FCT), STA, and signoff environments to ensure predictable closure. Define implementation recipes, optimisation strategies, and best practices for timing, congestion, power, and area closure. Develop automation using Tcl/Python/Shell to improve productivity, debug efficiency, and flow robustness. Partner with CAD, FCFP, Timing, DFT, and Design teams to resolve methodology issues and improve project execution. Enable new technology nodes, validate EDA tool features, and drive methodology enhancements for future projects Required Qualifications Bachelor's/Master's degree in Electrical/Electronics Engineering. Strong understanding of ASIC Physical Design flow including Floorplanning, Placement, CTS, Routing, STA, ECO, IR/EM, and Physical Verification. Expertise in clock-tree synthesis, clock skew/latency optimisation, and timing closure methodologies. Experience with industry-standard tools such as Fusion Compiler, ICC2, Innovus, PrimeTime, Calibre, and RedHawk. Strong scripting skills in Tcl, Python, and Shell. Good debugging, problem-solving, and cross-functional collaboration skills. Preferred Experience Prior experience owning flow development, methodology certification, or automation projects. Experience across advanced technology nodes (5nm/3nm and below) is a plus. #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "CPU/Cores Post Silicon Validation (Functional)", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-28T04:27:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92800/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. CPU/Cores Post Silicon Validation(Functional) THE ROLE: The AMD Cores system validation team is looking for a dynamic, energetic CPU Cores Validation engineer to join our growing team focused on the Zen CPU. Cores Systems Validation Engineer will architect, drive and perform hands-on system level debug to isolate functional failures to a specific IP or domain. Exposure begins at the architecture level, working with pre-silicon teams to maximize pre-silicon coverage, post-silicon bring-up and enablement, and engagement through production and working with customer facing teams for best adoption. You will work in a dynamic environment, directly with the product, tools, motherboards, and BIOS/OS. THE PERSON: As a key contributor to the success of AMD’s Cores roadmap, you will be driving and directing a high performing team towards the delivery of high quality, industry-leading processors to the market. The validation team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. KEY RESPONSIBILITIES: Orchestrate the validation of CPU Cores by participating in the Test plan definition, Content generation, Execution and Debug of critical functional issues. Isolate and triage generic system level failures into a more focused area of the platform or CPU. Drive debug and resolution of Zen CPU validation issues across silicon, firmware/BIOS, and coordinating with memory partners as needed Develop x86 content to exercise new features and reproduce complex bugs in silicon Devise validation strategy from pre-silicon through customer adoption working across architecture, silicon design, firmware, validation, and debug teams Proactively participating in project planning, developing, and maintaining schedules, managing dependencies, and ensuring quality of deliverables at committed milestones. Generates/Maintains regular status representing the Cores Validation team in program meetings providing status to program management PREFERRED EXPERIENCE: Programming/scripting skills (e.g. C/C++, Perl, Ruby, Python) x86 assembly programming Debug techniques and methodologies Extensive experience with board/platform-level debugging, including delivery, sequencing, analysis, and optimization Extensive knowledge of system architecture, technical debug, and validation strategy Strong analytical/problem-solving skills and pronounced attention to details Must be a self-starter, and able to independently drive tasks to completion      ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-DB2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Staff Physical Design Engineer", "company": "Tenstorrent", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-28T03:33:31-04:00", "url": "https://job-boards.greenhouse.io/tenstorrent/jobs/5243509007", "is_hardware": true, "platform": "greenhouse", "jd_text": "Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.\n\nAs part of our Physical Design team, you will work on high-performance designs alongside world-class engineers, covering everything from synthesis to tapeout across various IP blocks.\n\nThis role is hybrid, based out of Bangalore.\n\nWe’re looking for experienced professionals with hands-on expertise in physical design. Your role and offer will align with the experience demonstrated during interviews, which may differ from the level in this posting.\n\n \n\nWho You Are\n\nYou enjoy solving complex timing, power, and layout problems at advanced nodes.\n\nYou’ve worked on multiple chip tapeouts and understand physical design flows end-to-end.\n\nYou’re comfortable using tools like Innovus, Primetime, and RedHawk.\n\nYou like working closely with cross-functional teams to deliver high-quality silicon.\n\nWhat We Need\n\n4-8 yrs of experience,Take ownership of blocks from synthesis to sign-off: floorplanning, PnR, clocking, and optimization.\n\nDefine physical design needs in collaboration with front-end and architecture teams.\n\nCoordinate with foundry partners, IP vendors, and design services during integration.\n\nImprove design quality and drive area, power, and performance improvements through flow tuning and RTL experiments.\n\nWhat You Will Learn\n\nHow high-performance CPU/SOC and AI chips are built at leading-edge technology nodes.\n\nTechniques to push the limits of performance, power, and area in real silicon.\n\nHow front-end, back-end, and validation teams work together to ship a product.\n\nWays to evolve implementation workflows and improve team efficiency.\n\n \n\nTenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.\n\nThis offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.  Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).   These requirements apply to persons located in the U.S. and all countries outside the U.S.  As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.  If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.", "jd_status": "stored"}, {"title": "Peripherals (Ethernet) Validation Engineer - Sr. Lead / Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-28T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446717656625", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nKey Responsibilities:\n\nDevelop, execute and maintain comprehensive validation plans for Ethernet IP and SoC-level features across pre-silicon, emulation and post-silicon environments.\nCollaborate closely with IP architecture, design and systems teams to understand validation requirements and translate them into robust test content.\nLead bring-up, debug and root-cause analysis for complex cross-functional issues spanning hardware, drivers and platform integration.\nEnsure validation coverage is sufficient to provide high confidence in functional correctness, performance, power behavior, and production readiness.\n\nRequired Skills and Experience:\n\nStrong hands-on experience with Ethernet controllers, NIC architectures, PCIe and related high-speed connectivity IPs.\nProficiency in bare-metal and Linux driver development with strong C/C++ programming and debugging skills.\nSolid understanding of embedded systems, SoC architecture, peripheral subsystems and hardware/software interaction.\nExperience validating complex SoC features across functional, performance, power and system-level scenarios.\nExposure to automotive SoC development, automotive Ethernet, safety-aware validation practices or automotive process requirements is preferred.\nHands-on experience with lab and debug tools such as Lauterbach TRACE32, oscilloscopes, protocol analyzers and traffic-generation equipment.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior/Lead Engineer - DSP/NSP Power Analysis & Correlation", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-28T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721257215", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Systems Engineering\nGeneral Summary:\nWe are seeking a highly motivated Senior Engineer (5-6 years experience) to drive pre-si power analysis, optimization, and silicon correlation for next-generation DSP and NSP architectures. The role focuses on evaluating and improving pre-silicon power analysis methodologies, understanding the strengths and limitations of various power estimation tools, and enabling early power optimization through actionable insights.\n \nThe engineer will also work closely with silicon validation teams to characterize performance and power on silicon, compare results against pre-silicon estimates, and help improve correlation accuracy. This role requires a strong understanding of DSP/NSP architectures, workload behavior, packet/data flows, and the relationship between system activity, performance, and power consumption.\n \nKey Responsibilities\n\nEvaluate and compare pre-silicon power analysis and estimation tools across simulation, emulation, and modeling environments.\nAnalyze tool methodologies, identify gaps, and recommend enhancements to improve power estimation accuracy and usability.\nDrive adoption of best-in-class capabilities from various power analysis tools to improve pre-silicon power optimization workflows.\nPerform workload-level and block-level power analysis for DSP/NSP subsystems.\nIdentify power hotspots and optimization opportunities across architecture, RTL, and software layers.\nMeasure and characterize performance and power behavior on silicon platforms.\nCorrelate silicon measurements with pre-silicon estimates and investigate sources of mismatch.\nDevelop methodologies and automation to improve power prediction accuracy and correlation efficiency.\nAnalyze packet flows, data movement, memory traffic, and workload behavior to understand their impact on power and performance.\nCollaborate with architecture, design, software, performance, and silicon validation teams to drive power-efficient solutions.\nGenerate technical reports and present findings to stakeholders and engineering leadership.\n\nRequired Qualifications\n\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.\n5-6 years of experience in power analysis, performance characterization, silicon validation, architecture analysis, or related areas.\nStrong understanding of processor and SoC architecture fundamentals.\nExperience working with pre-silicon environments such as simulation, emulation, performance models, or power models.\nExperience with silicon performance and power characterization.\nUnderstanding of performance-per-watt tradeoffs and power optimization techniques.\nFamiliarity with scripting and automation using Python, Shell, Perl, or similar languages.\nStrong analytical, debugging, and problem-solving skills.\nExcellent communication and cross-functional collaboration abilities.\n \nPreferred Qualifications\n\nExperience with DSP, AI/ML accelerators, vector processors, or heterogeneous compute architectures.\nKnowledge of power modeling, power estimation methodologies, activity-based analysis, and PMU-based profiling.\nUnderstanding of packet/data flow analysis, memory hierarchy, bandwidth utilization, and workload characterization.\nExperience correlating simulation, emulation, or modeling results against silicon measurements.\nExperience working with large-scale performance and power datasets and visualization tools.\n\nDesired Skills\n\nStrong curiosity to explore new tools and methodologies.\nAbility to translate complex power data into actionable optimization recommendations.\nPassion for improving correlation between pre-silicon and post-silicon environments.\nSelf-driven mindset with strong ownership and execution capabilities.\n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience.\n                                                                    OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.\n                                                                    OR\nPhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SOC Verification Principal Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-28T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721283194", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.\n\nUnderstand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.\n\nResponsible to implement and analyze system Verilog assertion and coverage(code, toggle, functional) .\n\nWork alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue.\n\nCollaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nAdhere to quality standards and good test and verification practices.\n\nB.E/B. Tech/M.E/M. Tech in electronics with 12+ year experience in verification domain.\n\nPrior work experience on IP level or Soc level.\n\nPrior work on UFS (Universal Flash Storage),Ethernet and PCIe Protocol is desirable.\n\nGood understanding of processor based Soc level verification  which includes native ,Verilog ,system Verilog and UVM mix environment.\n\nHand on experience with verification tools such as VCS, waveform analyzer and  third party VIP integration (such as Synopsys VIPs).\n\nHands on experience in UVM. C/C++ ,System Verilog verification language.\n\nGood understanding of AXI-AMBA  protocol variants.\n\nCan work with scripting language (shell, Makefile, Perl )\n\nStrong understanding of design concepts and ASIC flow.\n\nGood problem solving , analytical and debugging skill is mus\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Formal Verification CAD Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-28T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721233539", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\n\nJob Description\nJob Description\nWe are seeking a highly motivated Formal Verification Engineer with 2+ years of experience to join our GCAD Formal team. The ideal candidate will have strong formal verification fundamentals, hands-on experience with formal tools, excellent analytical and scripting skills, and the ability to drive innovative verification methodologies. This role provides the opportunity to collaborate across global architecture, design, and systems teams to influence and strengthen verification sign‑off quality.\nWhat You Will Be Doing\nDrive formal verification of complex design blocks using advanced Formal Apps and robust convergence strategies to achieve exhaustive and high‑confidence sign‑off.\nCollaborate with worldwide architecture, design, and systems teams to achieve verification goals.\nReview and refine formal setups, proofs, constraints, and abstractions with design/DV teams.\nEngage with EDA vendors and evaluate advanced DV methodologies to improve sign‑off quality.\nDevelop automation scripts (Python preferred) to enhance efficiency and scalability of FV flows.\nAnalyze challenging formal problems and propose effective verification strategies.\nLow power formal methodology\nWhat We Need to See\n2+ years of hands-on experience in Formal Verification.\nStrong understanding of formal concepts, proof strategies, and abstraction techniques.\nProficiency with formal tools (Jasper, VC Formal, Questa Formal, etc.).\nWorking knowledge of property-based FV (SVA ) is a plus.\nExcellent scripting skills (Python strongly preferred).\nStrong analytical and problem‑solving abilities.\nClear communication skills and ability to collaborate with global teams.\nA strong willingness to learn, innovate, and deliver high‑quality results.\nLow‑power knowledge is a plus (e.g., power‑aware verification concepts, UPF/CPF, isolation/retention, power/clock gating, power‑aware apps, and basic power‑intent debugging).\n \n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "DDR Design Verification Staff Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-28T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721264662", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nJob Overview\nWe are looking to hire a strong DV engineer to work on verification of LPDDR/DDR based IPs and Subsystems in the Infra IP team\nCreate DV infrastructure for verification\nIntegrate VIP's\nCreate and execute test plans, debug failures, write assertions, close code and functional coverage\nEnsure high quality verification\nWorking with all stakeholders to ensure program success\nMinimum Qualifications\nBachelor's degree in Engineering, Electronics, Information Systems, Computer Science, or related field.\n11+ years Hardware Engineering experience or related work experience.\nPreferred Qualifications\nFollowing skill set is required:\nStrong Debug, UVM, System Verilog\nUnderstanding Specs and Standards and developing relevant test plans\nMonitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved\nCandidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening\nPreferred Qualifications 4+ Year of industry experiences in the following areas: -\nThorough understanding of Digital design concepts\nThorough understanding dv methodologies and tools\nGood understanding of DDR/LPDDR families (LP/PC) and generations (DDR2/3/4/5)\nUnderstanding of Bus protocols like AHB/AXI/ACE/ACE-Lite\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "PD Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-28T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721116517", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\n2  yrs experience in Physical Design and timing signoff for high speed cores.\nShould have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology.\nMasters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design.\nExperience in leading block level or chip level Physical Design, STA and PDN activities.\nWork independently in the areas of RTL to GDSII implementation.\nAbility to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc.\nKnowledge of low power flow (power gating, multi-Vt flow, power supply management etc.)\nCircuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.)\nTcl/Perl scripting Willing to handle technical deliveries with a small team of engineers.\nStrong problem-solving skills\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SOC Design Verification Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-28T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721244414", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field.\n\nUnderstand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.\n\nResponsible to implement and analyze system Verilog assertion and coverage(code, toggle, functional) .\n\nWork alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue.\n\nCollaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nAdhere to quality standards and good test and verification practices.\n\nB.E/B. Tech/M.E/M. Tech in electronics with 3+ year experience in verification domain.\n\nPrior work experience on IP level or Soc level.\n\nPrior work on UFS (Universal Flash Storage),Ethernet and PCIe Protocol is desirable.\n\nGood understanding of processor based Soc level verification  which includes native ,Verilog ,system Verilog and UVM mix environment.\n\nHand on experience with verification tools such as VCS, waveform analyzer and  third party VIP integration (such as Synopsys VIPs).\n\nHands on experience in UVM. C/C++ ,System Verilog verification language.\n\nGood understanding of AXI-AMBA  protocol variants.\n\nCan work with scripting language (shell, Makefile, Perl )\n\nStrong understanding of design concepts and ASIC flow.\n\nGood problem solving , analytical and debugging skill is must.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RTL Design (DDR)- Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-28T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721283495", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.\n•    5+ years of ASIC design, verification, validation, integration, or related work experience.\n•    2+ years of experience with architecture and design tools.\n•    2+ years of experience with scripting tools and programming languages.\n•    2+ years of experience with design verification methods.\n•    1+ year of work experience in a role requiring interaction with senior leadership (e.g., Director level and above).\n\nPrincipal Duties & Responsibilities:\n•    Leverages ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.\n•    Creates architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.\n•    Collaborates across teams (e.g., software architecture, hardware architecture) to develop and execute an implementation strategy that meets system requirements and customer needs.\n•    Evaluates all aspects of complex process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.\n•    Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable architecture and design of multiple blocks/SoC or IC Packages.\n•    Writes and reviews detailed technical documentation for EDA/IP/ASIC projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc.  \n•    Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions).\n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NOC Design --Sr Lead/Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-28T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720362616", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    8+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates complex features and functionality into hardware designs in line with proposals or roadmaps for complex products.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the novel manufacturing of solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for complex Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making is significant in nature and affects work beyond immediate work group.\n•    Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. \n•    Has a moderate amount of influence over key organizational decisions.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Principal Engineer - Design", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-09-28", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Principal-Engineer---Design_R2977-26", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nThe Principal Engineer - Design will join Microchip’s rapidly growing Data Center Solutions (DCS) business unit, delivering high-performance silicon solutions used by leading server and storage OEMs and hyperscale data centers. DCS products enable workloads ranging from cloud and big data storage to AI/ML acceleration, shaping the next generation of data center infrastructure.\nThe DCS portfolio includes SAS, PCIe, NVMe, and CXL infrastructure products, Flash Controllers, High-Performance Switches, and advanced memory infrastructure solutions. This role provides a unique opportunity to drive architecture, design excellence, and methodology innovation in complex data center–class ASICs\nKey Responsibilities\n• Lead architecture and micro-architecture definition for complex IPs, subsystems, or full-chip designs.\n• Drive end-to-end RTL design execution, from concept through synthesis, sign-off, and silicon bring-up support.\n• Serve as a technical authority for digital design, ensuring high standards in quality, performance, power, and area (PPA).\n• Resolve complex, cross-domain design and EDA tool challenges impacting schedule or silicon quality.\n• Collaborate closely with verification, physical design, DFT, system, and product teams to ensure robust and predictable\ndelivery.\n• Guide low-power, high-performance design strategies suitable for data center workloads.\n• Influence protocol and platform roadmap decisions, particularly in PCIe, CXL, NVMe, SAS, and related interconnects.\n• Mentor and technically guide engineers, providing architectural reviews and design direction.\n\nRequirements/Qualifications:\n\n• 10+ years of experience in ASIC or SoC digital design.\n• Bachelor degree in Electronics or Electrical Engineering minimum\n• Strong expertise in SystemVerilog RTL design and micro-architecture development.\n• Proven success delivering multiple complex tape-outs in high-performance or data center–class silicon.\n• Deep hands-on experience with Lint, CDC, formal verification, logic synthesis, and static timing analysis.\n• Strong understanding of physical design interactions, including timing, power, and congestion considerations.\n• Solid experience with low-power design methodologies and flows.\n• Mandatory knowledge of DFT, including scan, testability considerations, and DFT sign-off interactions.\n• Proficiency in scripting languages such as Tcl, Perl, and/or Awk.\n• Hands-on experience with high-speed protocols such as PCIe, CXL, NVMe, SAS/SATA, or similar serial interfaces.\n• Experience in AI-driven workflows to accelerate AI development.\n• Hands-on experience with Cadence-based ASIC design environments is an asset\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Staff Physical Design Engineer: CPU Implementation & Flow Automation", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-28", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Staff-Physical-Design-Engineer--CPU-Implementation---Flow-Automation_R-101149", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nThe Role:\nAs a Staff Physical Design Engineer, you will be responsible for developing and perfecting the RTL-to-GDS implementation flow for our high-performance CPU cores. You will take ownership of advanced implementation recipes, driving PPA (Power, Performance, Area) closure on leading-edge N3/N2 process nodes. This role combines deep technical execution with the development of automated, ML-enhanced methodologies to ensure our CPU designs hit aggressive frequency and power targets.\n\nKey Responsibilities\nFlow Development & Execution: Develop, validate, and deploy production-ready RTL-to-GDS recipes using Synopsys Fusion Compiler\n\nPPA Optimization: Drive block-level and hierarchical PPA closure, utilizing advanced techniques in timing-driven placement, CTS, and routing.\n\nML Implementation: Hands-on deployment of ML optimization tools (DSO.ai) to automate design space exploration and achieve optimal PPA results.\n\nTechnical Support: Serve as the first line of defense for flow and tool-related issues, working closely with the methodology team to resolve bottlenecks.\n\nCollaboration: Partner with IP teams (SRAM/Std Cell) to characterize and model PPA impacts on the overall flow.\n\nAutomation: Create and maintain robust Tcl/Python scripts to improve flow efficiency and ensure repeatable, predictable results across design iterations.\n\nRequirements\nExperience: 7+ years of experience in Physical Design/Methodology, with a focus on high-performance digital implementation.\n\nNode Knowledge: Proven experience with FinFET nodes (N5/N3); understanding of N2/GAAFET challenges is a plus.\n\nTool Proficiency: Expert knowledge of the Synopsys digital implementation suite (Fusion Compiler, ICC2, PrimeTime, StarRC).\n\nHierarchical Design: Strong understanding of hierarchical physical design, including floorplanning, pin assignment, and timing budgeting.\n\nAutomation Skills: High proficiency in Tcl and Python for flow customization and data analysis.\n\nProblem Solving: A track record of solving complex timing and congestion issues in high-speed, high-density CPU blocks.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Security Operations Center (SOC) Functional Lead (Individual Contributor)", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2026-09-28", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/Security-Operations-Center--SOC--Functional-Lead--Individual-Contributor-_R2629590", "is_hardware": true, "platform": "workday", "jd_text": "Who We Are\n\nApplied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI and accelerating the commercialization of next-generation semiconductor chips. Join us and push the boundaries of materials science and engineering in a company at the foundation of the electronics industry. The work we do together advances the world’s technology. \n\nWhat We Offer\n\nLocation:\nBangalore,IND\nYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. \n\nAt Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. \n\nRole Summary \n\nThe Security Operations Center (SOC) Functional Lead is a senior individual contributor who provides functional leadership, technical direction, and operational oversight for SOC capabilities. The role focuses on strengthening threat detection, incident response, and continuous improvement across cybersecurity operations. \n\nThis role requires strong expertise in SOC operations, incident response, detection engineering, and security platforms, along with the ability to influence stakeholders, guide analysts, and deliver scalable operational improvements. \n\n \n\nCore Responsibilities \n\nProvide functional leadership and operational coordination for SOC activities \n\nLead high-severity incident response, threat detection, and continuous improvement initiatives \n\nGuide analysts, improve playbooks and detection content, and enhance SOC processes and tooling \n\nPartner with IT, Risk, Compliance, and business stakeholders to strengthen security posture \n\nTrack key operational metrics and support governance, risk, and compliance requirements \n\nKey Requirements \n\nStrong expertise in SOC operations, incident response, SIEM/SOAR, and threat detection \n\nAbility to provide functional leadership, mentor analysts, and lead cross-functional initiatives \n\nStrong communication, stakeholder management, and problem-solving skills \n\nUnderstanding of security frameworks, governance, and compliance requirements \n\nEducation \n\nBachelor’s or Master’s in Cybersecurity, Computer Science, or related field \n\nExperience \n\n10+ years of experience in cybersecurity, including SOC operations, incident response, and detection engineering \n\nExperience in senior individual contributor, technical lead, or functional lead roles \n\nExposure global SOC environment \n\nCertifications (Preferred) \n\nCISSP, CISM, or equivalent \n\nGIAC (GCIA, GCED, GCIH) \n\nMicrosoft SC-200 / AZ-500 or equivalent \n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nAssignee / Regular\nTravel:\nYes, 10% of the Time\nRelocation Eligible:\nYes\n\nApplied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "Principle DFT Engineer", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-09-28", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Principle-DFT-Engineer_2604815", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nAs a part of the Connectivity BU DFT team the suitable candidate will work on all aspects of DFT in products catering to the networking domain: DFT architecture and Testability strategy, Flow, Implementation, Verification and post-Si bring up.\nMarvell's Connectivity Business Unit is the industry-leading provider of high-speed connectivity solutions powering the full range of network infrastructure — from the optics of AI GPU boards to top-of-rack optical fibers and active copper cables in data centers and their fabrics. The BU spans multiple cutting-edge product lines, including Optical Digital Signal Processing (ODSP), Active Electrical Cable (AEC), and Coherent Digital Signal Processing (CDSP), delivering solutions to enterprise, data center, service providers, and cloud customers worldwide.\n\nYou'll work closely and mentor other DFT team members for DFT features Implementation, Integration and Verification in SoC. You will also have close interaction with Logic Design/Physical design/STA/ATE teams as needed.\nWhat You Can Expect\nDefine and drive the DFT architecture and test strategy for complex IPs and SoCs, ensuring robust testability and alignment with product quality, coverage, and manufacturability goals.\nLead the implementation and integration of Scan, ATPG, JTAG, MBIST, and Boundary Scan (BSCAN) solutions, ensuring compliance with IEEE 1149.1/1149.6 standards.\nDevelop and deploy DFT features including test structures, IP-level DFT integration, ATPG fault models, test point insertion, coverage optimization, scan insertion, and MBIST implementation at both block and chip levels.\nOwn and execute hierarchical DFT flows across the design hierarchy, from individual IPs through full-chip integration.\nImplement, validate, and debug DFT/DFX features, ensuring seamless integration with the overall SoC architecture.\nGenerate and validate production test patterns, perform RTL and netlist verification, execute gate-level simulations (zero-delay and SDF-based), and ensure comprehensive test-mode validation.\nDevelop and maintain test timing constraints, including SDC creation, test-mode timing analysis, and support for block- and chip-level STA signoff activities.\nUtilize industry-standard EDA tools for Scan, ATPG, MBIST, and JTAG implementation, verification, and debug.\nCollaborate closely with Design, Synthesis, Physical Design, STA, Validation, and Silicon Bring-up teams to resolve DFT-related issues and ensure successful project execution.\nDrive Post-Silicon bring-up, ATE debug, silicon characterization, and production ramp-up activities, enabling efficient silicon validation and productization.\nOwn DFT deliverables throughout the project lifecycle, ensuring successful execution from architecture definition through tape out, silicon validation, and manufacturing release.\nDemonstrate strong ownership, accountability, and technical leadership to ensure successful tape out and post-silicon ramp-up of the project.\n\nWhat We're Looking For", "jd_status": "stored"}, {"title": "Principal Engineer, Design Verification Engineering", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-09-28", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Principal-Engineer--Design-Verification-Engineering_R265641", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nAnalog Devices is seeking Digital Design Principal Verification Engineer, who will be responsible for design verification of highly integrated solutions and products in a multifunctional team. You will be working on driving real revenue growth on the next generation of Intelligence at the Edge products across multiple products and business units.\nAbout ADI:\nAnalog Devices, Inc. is a leading global high-performance analog technology company dedicated to solving our customers' most complex engineering challenges. We play a critical role at the intersection of the physical and digital world by providing the building blocks to sense, measure, interpret, connect, and power devices and systems. We design, manufacture, test, and market a broad portfolio of solutions, including integrated circuits (ICs), software and subsystems that leverage high-performance analog, mixed-signal and digital signal processing technologies. We embrace a culture of innovation and collaboration to push the state of the art.\n \nAbout the Role\nLead design verification team for SOC or subsystem design pre silicon verification.  The candidate will be responsible for formulating verification strategies, Define verification architecture, Flow, Methodology and leading, driving and completing verification of large integrated products. As a senior team member, it is expected that he/she will lead and influence verification methodologies within both DBU and ADI.   The candidate is also encouraged to participate in cross company technical initiatives as well as patent and publish work where possible.\nResponsibilities\nLead end-to-end SoC verification for complex digital SoCs, driving execution from planning to signoff.\nVerify complex microprocessor-based designs, AI/ML accelerators, and high-speed peripherals using advanced verification methodologies.\nDefine and drive team execution by planning tasks, tracking progress, and providing technical leadership, mentoring, and guidance.\nCollaborate closely with architecture and design teams to define requirements and align on verification deliverables and dependencies.\nDrive pre-silicon readiness by aligning with emulation, FPGA, and software teams to cover post-silicon validation scenarios early.\nDevelop and execute end-to-end system-level use cases for comprehensive functional validation.\nArchitect and implement scalable UVM-based testbenches, DV flows, and methodologies.\nDefine and review test plans; ensure closure of functional and code coverage across block, subsystem, and SoC levels.\nWork cross-functionally with emulation, FPGA, firmware, and system teams to ensure full-system correctness.\nApply formal verification techniques for IP and subsystem-level validation.\nLead NoC/interconnect verification and ensure robust data flow across the SoC.\nPerform performance verification and system-level analysis across real-world use cases.\nDrive innovation in verification strategies to meet aggressive schedules and quality goals.\nDefine overall verification strategy based on product requirements and design specifications, leveraging modern techniques such as formal, emulation, portable stimulus, and virtual platforms.\n \nRequirements\nB.Tech/M.Tech with 12+ years of experience in digital pre-silicon verification, including leadership across IP, subsystem, or SoC-level DV.\nStrong understanding of SoC/Subsystem architectures with hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development, debugging, and methodology implementation.\nProven track record in verification closure using functional and code coverage metrics across block, subsystem, and SoC levels.\nExpertise in NoC, bus, and interconnect verification, along with coverage analysis and optimization.\nExperience in architecting scalable testbench environments and defining robust DV flows and methodologies.\nStrong background in power-aware verification (UPF), including power analysis and optimization.\nHands-on experience with formal verification, including flow definition, connectivity, and functional property checking.\nSolid protocol knowledge and verification experience across high-speed and low-speed interfaces such as I2C, SPI, Ethernet, UART, AXI/AHB, DMA, and SVI3.\nExperience in security and safety verification, ensuring compliance with secure design and functional safety requirements.\nFamiliarity with gate-level simulations with timing annotation (GLS).\nStrong expertise in test planning, constrained-random verification, assertions, and transaction-level modeling.\nGood understanding of processor-based systems (ARM, RISC-V, Tensilica), AI/ML accelerators, and proficiency in C/C++, SystemC, and scripting (Python/TCL/Shell).\nExposure to mixed-signal/analog verification (ADC/DAC/PLL/PHY) is a plus.\nExcellent communication and leadership skills with the ability to collaborate across global teams and drive verification innovation.\nStrong problem-solving mindset with the ability to quickly learn and adopt new technologies\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 25% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Senior Manager, Design Verification Engineering", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-09-28", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Senior-Manager--Design-Verification-Engineering_R265640", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nAnalog Devices is seeking Senior Manager, Design Verification Engineer, who will be responsible for design verification of highly integrated solutions and products in a multifunctional team. You will be working on driving real revenue growth on the next generation of Intelligence at the Edge products across multiple products and business units.\nAbout ADI:\nAnalog Devices, Inc. is a leading global high-performance analog technology company dedicated to solving our customers' most complex engineering challenges. We play a critical role at the intersection of the physical and digital world by providing the building blocks to sense, measure, interpret, connect, and power devices and systems. We design, manufacture, test, and market a broad portfolio of solutions, including integrated circuits (ICs), software and subsystems that leverage high-performance analog, mixed-signal and digital signal processing technologies. We embrace a culture of innovation and collaboration to push the state of the art.\n \nAbout the Role\nLead design verification team for SOC or subsystem design pre silicon verification.  The candidate will be responsible for formulating verification strategies, Define verification architecture, Flow, Methodology and leading, driving and completing verification of large integrated products. As a senior team member, it is expected that he/she will lead and influence verification methodologies within both DBU and ADI.   The candidate is also encouraged to participate in cross company technical initiatives as well as patent and publish work where possible.\nResponsibilities\nLead end-to-end SoC verification for complex digital SoCs, driving execution from planning to signoff.\nVerify complex microprocessor-based designs, AI/ML accelerators, and high-speed peripherals using advanced verification methodologies.\nDefine and drive team execution by planning tasks, tracking progress, and providing technical leadership, mentoring, and guidance.\nCollaborate closely with architecture and design teams to define requirements and align on verification deliverables and dependencies.\nDrive pre-silicon readiness by aligning with emulation, FPGA, and software teams to cover post-silicon validation scenarios early.\nDevelop and execute end-to-end system-level use cases for comprehensive functional validation.\nArchitect and implement scalable UVM-based testbenches, DV flows, and methodologies.\nDefine and review test plans; ensure closure of functional and code coverage across block, subsystem, and SoC levels.\nWork cross-functionally with emulation, FPGA, firmware, and system teams to ensure full-system correctness.\nApply formal verification techniques for IP and subsystem-level validation.\nLead NoC/interconnect verification and ensure robust data flow across the SoC.\nPerform performance verification and system-level analysis across real-world use cases.\nDrive innovation in verification strategies to meet aggressive schedules and quality goals.\nDefine overall verification strategy based on product requirements and design specifications, leveraging modern techniques such as formal, emulation, portable stimulus, and virtual platforms.\n \nRequirements\nB.Tech/M.Tech with 12+ years of experience in digital pre-silicon verification, including leadership across IP, subsystem, or SoC-level DV.\nStrong understanding of SoC/Subsystem architectures with hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development, debugging, and methodology implementation.\nProven track record in verification closure using functional and code coverage metrics across block, subsystem, and SoC levels.\nExpertise in NoC, bus, and interconnect verification, along with coverage analysis and optimization.\nExperience in architecting scalable testbench environments and defining robust DV flows and methodologies.\nStrong background in power-aware verification (UPF), including power analysis and optimization.\nHands-on experience with formal verification, including flow definition, connectivity, and functional property checking.\nSolid protocol knowledge and verification experience across high-speed and low-speed interfaces such as I2C, SPI, Ethernet, UART, AXI/AHB, DMA, and SVI3.\nExperience in security and safety verification, ensuring compliance with secure design and functional safety requirements.\nFamiliarity with gate-level simulations with timing annotation (GLS).\nStrong expertise in test planning, constrained-random verification, assertions, and transaction-level modeling.\nGood understanding of processor-based systems (ARM, RISC-V, Tensilica), AI/ML accelerators, and proficiency in C/C++, SystemC, and scripting (Python/TCL/Shell).\nExposure to mixed-signal/analog verification (ADC/DAC/PLL/PHY) is a plus.\nExcellent communication and leadership skills with the ability to collaborate across global teams and drive verification innovation.\nStrong problem-solving mindset with the ability to quickly learn and adopt new technologies\n \n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Senior System Software Engineer - GPU and SOC", "company": "NVIDIA", "location": "India, Pune", "date_posted": "2026-09-28", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Pune/Senior-System-Software-Engineer---GPU-and-SOC_JR2026373", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is searching for a highly motivated, creative engineer to join the GPU Software team. As a GPU/SOC system software engineer, you will work with a team of very dedicated software and hardware engineers involving a wide variety of technologies. As someone who is hardworking and passionate about their work, you will craft and debug key aspects of our production GPU and SOC kernel drivers and embedded SW, focusing on platform performance, power savings, and robustness. You should demonstrate the ability to excel in an environment with intricate system level interactions.\n\nWhat your role entails:\nDesign, implement and debug changes in the NVIDIA SW stack to take next-gen HW from design / development stage to production, with focus on kernel-mode SW\nYou will follow the devices all the way through the development process to datacenter systems, customer desktops, notebooks, workstations, and gaming console products that are used throughout the world\nBe heavily involved in emulation, bringup, and product hardening required to build our groundbreaking products\nMultiple opportunities to collaborate and communicate effectively with teams from all around the globe\n\nWhat we need to see:\nBS or MS degree in Computer Engineering, Computer Science, or equivalent experience\n5+ years of relevant software development experience\nBackground in solving problems that apply to sophisticated systems deployed at scale\nStrong C/C++ programming skills as well as having shown initiative in pursuing independent coding projects\nFamiliarity with computer system architecture, microprocessor, and microcontroller fundamentals (caches, buses, memory controllers, DMA, etc.)\nStrong Operating systems fundamentals with Kernel experience on Linux or Windows systems\n\nWays to stand out from the crowd:\nBackground and strength with system-level (SW and HW) debugging is invaluable\nWindows Driver Models, with WDDM or MCDM a strong plus.\nFamiliarity with system level security concepts\nExperience with system software concepts", "jd_status": "stored"}, {"title": "Functional Safety Staff Engineer, ASIC Digital Design", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-28", "url": "https://careers.synopsys.com/job/bengaluru/functional-safety-staff-engineer-asic-digital-design/44408/101253319776", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in the space where hardware meets safety, and you know that a chip destined for an automotive system is not just about performance or power, it is about proving that when something goes wrong, the design catches it before it matters. You think in failure modes, diagnostic coverage, and safety mechanisms, not as compliance checkboxes but as engineering decisions that determine whether a product ships or gets recalled.\nYou have read ISO 26262 enough times that you can tell when a Technical Safety Concept is missing a dependency or when an FMEA is too shallow to survive an audit. You are comfortable sitting with architects who are sketching out a new IP block and asking the questions that surface safety gaps early, before RTL is written and before verification plans are locked. You do not wait for someone to hand you a safety requirement, you help shape it based on what the hardware can realistically deliver.\nYou have done the work. You have written safety analyses, reviewed fault injection results, defined safety mechanisms, and worked through assessor feedback without losing your patience or your clarity. At Synopsys, you will work on IP and SoC products where safety is not an afterthought, and where the rigor you bring will directly shape what our automotive customers can build.\nWhat You'll Be Doing\nDrive Functional Safety activities across ASIC IP and SoC development lifecycles, from early architecture through verification and release\nDevelop and review safety requirements, Technical Safety Concepts, and safety work products in compliance with ISO 26262\nConduct safety analyses including FMEA, FMEDA, FTA, and Dependent Failure Analysis to identify and mitigate failure modes\nDefine, implement, and evaluate safety mechanisms at the IP, subsystem, and SoC level to meet diagnostic coverage and fault detection targets\nCollaborate with Architecture, RTL Design, and Verification teams to integrate safety into design and validation workflows\nInterface with customers, cross-functional teams, and external safety assessors to support audits, reviews, and certification activities\nDocument safety analyses, traceability matrices, and compliance evidence for internal reviews and external assessments\nThe Impact You Will Have\nEnable Synopsys IP and SoC products to meet automotive safety standards and support customer certification timelines\nReduce late-stage design rework by identifying safety risks early in the architecture and design phases\nImprove diagnostic coverage and fault detection capabilities across safety-critical semiconductor products\nStrengthen customer confidence by delivering well-documented, auditable safety work products that pass assessor scrutiny\nInfluence hardware safety architectures that will be deployed in next-generation automotive systems\nBuild internal capability by mentoring design and verification engineers on Functional Safety principles and practices\nContribute to a culture where safety is embedded in engineering decisions, not bolted on at the end\nWhat You'll Need\nBachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or a related discipline\n6 to 10 years of experience in Functional Safety engineering, with a focus on automotive semiconductor, IP, or SoC development\nStrong working knowledge of ISO 26262 standards, processes, and compliance requirements across hardware development lifecycles\nProven experience developing and reviewing safety requirements, Technical Safety Concepts, and related safety work products\nHands-on expertise in FMEA, FMEDA, FTA, and Dependent Failure Analysis methodologies\nExperience defining and evaluating safety mechanisms, diagnostic coverage, and fault mitigation strategies at IP or SoC level\nUnderstanding of semiconductor product development and verification flows, and the ability to work independently with cross-functional teams, customers, and assessors. Experience with automotive IPs, networking or communication IPs, or safety-critical products is a strong plus\nWho You Are\nYou can walk into an architecture review and spot a safety gap that others miss, not because you are looking for problems but because you understand how failures propagate\nYou write safety analyses that are clear enough for an assessor to follow and detailed enough to survive a technical challenge from a design lead\nYou do not get stuck when requirements are incomplete or when a design decision has not been finalized, you work with what you have and flag what needs to be resolved\nYou can explain a complex safety mechanism to an RTL engineer in a way that makes sense within their workflow, not as an abstract concept but as something they can implement and verify\nYou are organized enough to track safety work products across multiple IP blocks and disciplined enough to maintain traceability without cutting corners\nYou push back when a proposed design does not meet safety targets, and you do it in a way that moves the conversation forward instead of shutting it down\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior Build and Release Methodology Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-09-28", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Build-and-Release-Methodology-Engineer_JR2013548", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\nWe are looking for a Senior Engineer for our Build and Release Methodology Group catering to our pioneering SOCs. As the SOC development becomes more complex requiring packing of more and more IPs and the need for doing more SOCs increase, we need to have a scalable infrastructure to be able to complete SOC development in fastest as well as most efficient way possible. This requires an SOC Build and IP Release infrastructure that caters to and keeps up with these ever-increasing complexities. In this position, you will work first-hand on architecting and developing this methodology. If you have real passion for methodologies and automation solutions, you will fit in great!\n\nWhat you'll be doing:\nDefine and develop system-level methodologies and tools to build SOCs in an efficient and scalable manner.\n\nArchitect and implement core build flows so as to optimize build and make it simpler and efficient.\n\nImprove build, release, and integration tools and procedures.\n\nIdentify and develop Checks to enforce the best practices for the Build and Release guidelines.\n\nDevelop solutions to enable abstraction and compartmentalization for customer IPs.\n\nIdentify difficulties and inefficiencies in the SOC implementation process and propose ideas to solve them.\n\nSupport IP teams with Build and Release related issues.\n\nWhat we need to see:\nBS or MS in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent experience.\n\n4+ years of industry experience as Build and Release Engineer, Build Automation, IP integration and related areas.\n\nStrong coding skills in Perl, Python, Makefile, Shell script, or other industry-standard scripting languages.\n\nExcellent analytical and problem-solving skills.\n\nExcellent interpersonal skills to work with multi-functional teams and collaborate with team members across sites and cultures to build consensus.\n\nBackground in RTL (Verilog), Verification (UVM, System Verilog) and C/C++ is a plus - Not must.\n\nExperience in synthesis and physical design is a plus - Not must.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "System Software Engineer – SoC Validation", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-28", "url": "https://careers.arm.com/job/bengaluru/system-software-engineer-soc-validation/33099/101248979968", "is_hardware": true, "platform": "talentbrew", "jd_text": "JOB OVERVIEW\nAre you interested in understanding how complex SoCs work and using software to find problems in real silicon?\nWe are looking for a Software Engineer to join our SoC Post-Silicon Validation team. We use Linux and software as powerful tools to exercise, validate, and debug advanced SoCs used in Infrastructure and Data Center systems.\nYou will work at the intersection of hardware and software, where you can see the direct impact of the code you develop. We will give you opportunities to expand your knowledge of SoC architecture, Linux, system software, and silicon validation while working alongside experienced engineers.\nIf you enjoy debugging complex problems and learning how hardware and software work together, we would love to hear from you!\nRESPONSIBILITIES\nYou will use Linux to validate SoC functionality, develop software and automated tests, analyze results, and investigate failures. You will work closely with design, firmware, software, and verification engineers to understand problems and contribute to their resolution.\nWe will encourage you to look beyond individual tests and help us improve our validation tools, automation, coverage, and ways of working. As your experience grows, you will have opportunities to take ownership of increasingly complex areas of SoC validation.\nREQUIRED SKILLS AND EXPERIENCE\nWe are looking for someone with around 2–3 years of experience in Linux, embedded software, firmware, system software, validation, or a related area.\nYou should have experience programming in C/C++, Assembly and using Python or shell scripting, together with an understanding of computer architecture and operating system fundamentals. Experience using Linux for development, testing, or debugging will help you get started quickly.\nMost importantly, we value curiosity, analytical thinking, collaboration, and an interest in understanding how complex systems work.\n“NICE TO HAVE” SKILLS AND EXPERIENCE\nYou may already have exposure to areas such as SoC validation, silicon bring-up, Linux kernel or device drivers, CPU and memory systems, PCIe, interrupts, SoC interconnects.\nYou do not need experience in all these areas. We are interested in what you can bring to the team and what you would like to learn next.\nIN RETURN\nWe will support you as you build expertise across Linux, system software, computer architecture, silicon validation, and hardware/software debugging.\nYou will have opportunities to learn from experienced engineers, work with advanced SoCs, contribute to real product development, and grow your technical skills and career. We offer a collaborative environment where we share knowledge, learn from each other, and solve challenging engineering problems together.\nWe also offer a competitive benefits package designed to support your wellbeing, professional development, and work-life harmony. Specific benefits may vary by location.\nWe want our recruitment process to be accessible to everyone. If you need reasonable accommodations or adjustments during the recruitment process, please let us know, and we will work with you to provide appropriate support.\nInterested in using software to explore what is happening inside a complex SoC? We would like to hear from you!\n\nLI#-KR2\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Principal Engineer, Agentic AI (CAD/EDA)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-28", "url": "https://careers.synopsys.com/job/bengaluru/principal-engineer-agentic-ai-cad-eda/44408/101270640320", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nYou have spent the better part of a decade building CAD infrastructure that has to hold up under real silicon development pressure, not just proof-of-concept demos or similar domains. You know that the difference between a flow that gets adopted and one that gets worked around is usually in the details no one else thought about. Lately, you have been watching the explosion of agentic AI and LLM orchestration, and instead of seeing hype, you see exactly how autonomous agents could transform the way IP gets designed, verified, and managed across its lifecycle.\nYou are someone who can sit with IP designers who need faster turnaround on design and verification and walk out with a multi-agent workflow spec that actually solves their problem. You do not wait for the AI platform team to tell you what is possible. You prototype, you integrate, you prove the concept, and then you scale it. You have strong opinions about what makes infrastructure scalable, and you are not afraid to push back when a proposed solution will not survive the challenges of a scalable production use.\nAt Synopsys, you will work at the center of Silicon Lifecycle Management (SLM) IP development in the AI Center of Excellence team, architecting AI Infrastructure, building Agents from scratch, leveraging when possible and customizing to the team needs. The problems are hard, the scale is real, and what you build will reshape how thousands of engineers work.\n\nWhat You'll Be Doing\nArchitect and define the next generation of AI-powered CAD infrastructure for Silicon IP development, building and integrating autonomous agents into core design and verification workflows\nBuild Agentic frameworks and Agents to improve Engineering productivity of the organization\nDeploy and operationalize Synopsys' global Agentic AI platform directly into the SLM IP development loop, building orchestration layers that connect LLMs, agents, and EDA toolchains across design, verification, synthesis, PnR, and timing\nDesign multi-agent workflows that automate IP design tasks, verification loops, and lifecycle analytics, turning manual bottlenecks into autonomous, scalable processes\nPartner with IP design teams, CAD engineers, and global AI platform teams to align architecture with real engineering needs and deployment constraints\nBuild and maintain the infrastructure layer that connects silicon design phases with AI-driven automation, ensuring performance, reliability, and scalability across the full IP lifecycle\nPrototype, test, and validate new AI-CAD integrations in live development environments, iterating based on feedback from design teams and measurable workflow improvements\nDrive technical strategy and roadmap for AI-augmented CAD systems within SLM, translating emerging AI capabilities into concrete engineering solutions\nProvide technical leadership and mentorship to the team, fostering best practices\n\nThe Impact You Will Have\nEnable IP design and verification teams to move faster by automating repetitive, high-friction tasks through intelligent agent-driven workflows\nReduce time-to-market for SLM IP by building scalable CAD infrastructure that adapts to design complexity without linear increases in manual effort\nSet the technical foundation for how Synopsys integrates agentic AI into silicon development, influencing architecture decisions across the broader EDA organization\nImprove design quality and lifecycle visibility by embedding AI-driven analytics and telemetry into the core IP development flow\nAccelerate adoption of Synopsys' Agentic AI platform by proving its value in one of the most demanding, high-stakes engineering environments in the company\nShape the future of CAD infrastructure at Synopsys, defining patterns and practices that will scale across multiple IP families and product lines\nDirectly influence how thousands of engineers experience their daily workflows, making complex silicon development more efficient, predictable, and autonomous\n\nWhat You'll Need\nBachelor's, Master's, or Ph.D. in Computer Science, VLSI, Electrical Engineering, or a related field\n12+ years of hands-on experience developing and deploying advanced CAD flows and infrastructure in silicon design environments\nProven experience implementing Agentic AI frameworks such as LangGraph, AutoGen, CrewAI, or equivalent platforms, LLM orchestrations, or autonomous software agent systems in production settings\nMastery of Python and C++ for building production-grade infrastructure, plus strong proficiency in EDA scripting languages like Tcl, Perl, and Shell\nTrack record of building agents and orchestration layers that interact with design, verification, synthesis, PnR, and timing flows\nTechnical understanding of silicon design phases, particularly IP development, verification, and lifecycle management workflows, is a plus\nExperience with Silicon Lifecycle Management concepts such as in-chip sensing, telemetry, and analytics is a strong plus\n\nWho You Are\nYou can walk into a room full of IP designers talking about verification bottlenecks and walk out with a clear architecture for an agent-driven solution that actually fits their workflow\nYou prototype fast and iterate based on real feedback, not theoretical requirements, and you know the difference between a demo that impresses and a system that ships\nYou have a point of view on what makes CAD infrastructure scalable and maintainable, and you are comfortable defending that view with technical depth and real-world examples\nYou are comfortable operating in ambiguity, especially when integrating cutting-edge AI technologies into established silicon development environments where stability and correctness are non-negotiable\nYou think in systems, understanding how changes in one part of the CAD flow ripple through design, verification, and downstream lifecycle analytics\nYou do not need perfect documentation or fully baked requirements to get started, you ask the right questions, align stakeholders, and find a path forward\n\nThe Team You'll Be Part Of\nYou will be part of the Silicon Lifecycle Management IP Development team in Bangalore, working at the intersection of advanced IP design and AI-driven automation. This team is responsible for building the infrastructure and workflows that power SLM IP development across Synopsys, and you will be the principal engineer defining how agentic AI gets integrated into that foundation. You will collaborate closely with IP designers, CAD engineers, and Synopsys' global Agentic AI platform teams, bridging technical domains and driving alignment across a distributed, highly technical organization. This is a Principal Individual Contributor role with significant technical leadership responsibilities across multiple globally distributed engineering teams. This role may evolve into leading a small team of AI infrastructure engineers as adoption scales.\n\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\n\n#TPG", "jd_status": "stored"}, {"title": "Formal Verification Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-28", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Formal-Verification-Engineer_JR0287328", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nIntel is seeking a Formal Verification Engineer for the Silicon Chassis team. In this role, you will apply advanced formal methods to rigorously verify interconnect fabrics, protocol bridges, and link-layer logic. You will drive end-to-end formal verification processes, including property specification and proof convergence across multiple protocol domains. Through close collaboration with architecture, design, and software teams, your work will ensure the delivery of high-quality, cutting-edge solutions.\n\nBusiness Group\nThe Central Engineering Group (CEG) focuses on enabling technology innovation across Intel by delivering robust engineering solutions and methodologies. As part of this group, the UIC Validation Transport team plays a critical role in supporting Intel's broader goals of advancing silicon development. By leveraging formal verification techniques, this team ensures the reliability and performance of foundational technologies used in Intel's products worldwide.\n\nKey Responsibilities\n- Develop and execute formal verification test plans, including defining scope, strategies, and methodologies.\n- Create abstraction models to facilitate convergence on complex designs and apply abstraction techniques for formal analysis.\n- Generate and validate proofs to verify designs, troubleshoot failing tests, and implement corrective measures.\n- Collaborate across architecture, RTL design, and physical implementation teams to improve verification accuracy for advanced features.\n- Maintain and enhance formal verification tools, methodologies, and infrastructure for optimized workflows.\n- Simplify and model design verification challenges using architecture-level modeling techniques.\n- Utilize formal verification tools to resolve Binary Decision Diagrams (BDD) complexities and optimize data paths.\n- Document verification plans, track progress, and lead technical reviews with cross-functional teams.\n\nQualifications:\nMinimum Qualifications\n- Bachelor's degree in Electrical Engineering, Computer Science, or a related field, with 4+ years of professional experience in formal verification OR Master's degree in a relevant field, with 3+ years of experience OR PhD with no prior professional experience.\n- Proficiency in formal verification tools and methodologies, including model checking and equivalence checking.\n- Strong knowledge of System Verilog, Verilog, and fundamentals of logic/microarchitecture.\n- Experience with abstraction modeling, simulation techniques, and convergence strategies.\n- Familiarity with Binary Decision Diagrams (BDD) and Data Flow Graphs (DFG).\n\nPreferred Qualifications\n- Proven ability to resolve complex architectural and formal verification challenges.\n- Strong collaboration and teamwork skills, with experience in cross-functional environments.\n- Exceptional technical documentation and communication abilities.\n- Enthusiasm for driving innovation and improving verification tools and methodologies.\n\nJoin us in shaping the future of computing technology with Intel by contributing to groundbreaking advancements in the field of formal verification.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "SysDE I - Multimedia, Silicon and Systems Group", "company": "Amazon", "location": "Bengaluru, Karnataka, IND", "date_posted": "2026-09-28", "url": "https://www.amazon.jobs/en/jobs/10561696/sysde-i-multimedia-silicon-and-systems-group", "is_hardware": true, "platform": "amazon", "jd_text": "Are you passionate about display subsystems and kernel-level graphics frameworks that power millions of consumer devices? Join our team to work at the core of the Linux display stack, driving DRM/KMS framework development, V4L2 display driver integration, and kernel module development to deliver visually rich and high-fidelity experiences on cutting-edge devices.\n\nAs a SysDE I on the Display Module team, you will own the development and integration of display kernel drivers built on the DRM/KMS framework, enabling features such as plane management, CRTC configuration, and atomic modesetting. You will work with V4L2 drivers for display pipeline processing, develop and extend kernel modules for display processing units, and drive HDR/SDR format conversion across the display pipeline, including support for 8-bit, 10-bit, and 12-bit color depth configurations to ensure accurate tone mapping and color fidelity on diverse panel types.\n\nYou will also be responsible for bootsplash enablement, ensuring seamless visual output from early kernel initialization through kernel hand-off to the userspace display stack, delivering a flicker-free and visually consistent boot experience across product platforms.\n\nThis summary shifts the focus from GPU/compositor work to the Display module domain, specifically emphasizing:\n\nDRM/KMS framework — plane management, CRTC, atomic modesetting\nV4L2 driver — display pipeline processing\nKernel module development — DPU driver work\nHDR/SDR conversion — tone mapping across the display pipeline\n8/10/12-bit depth — color fidelity and panel support\nBootsplash — early kernel visual output through kernel hand-off\n\nKey job responsibilities\n• Own the development, integration, and bring-up of display kernel drivers built on the DRM/KMS framework across multiple product platforms, including CRTC configuration, plane management, connector setup, and atomic modesetting to ensure stable and performant display output\n• Develop and maintain V4L2-based display and video pipeline drivers, enabling hardware-accelerated video processing, format conversion, and display output routing through the kernel media subsystem\n• Design, implement, and extend Linux kernel modules for Display Processing Units (DPU), including driver architecture, power management hooks, interrupt handling, and device tree integration\n• Drive HDR/SDR format conversion and tone mapping across the display pipeline, ensuring accurate rendering of HDR10, HLG, and SDR content with proper metadata handling and color space transitions\n• Enable and validate support for 8-bit, 10-bit, and 12-bit color depth configurations across the display pipeline, ensuring correct pixel format negotiation, dithering strategies, and panel compatibility\n• Own bootsplash enablement and optimization, ensuring seamless visual output from early kernel initialization (bootloader framebuffer handoff) through kernel driver probe to userspace display stack handoff, delivering a flicker-free boot experience\n• Debug and root-cause complex display subsystem issues spanning DRM/KMS, V4L2, DPU firmware, panel timing, and color pipeline using kernel traces, DRM debug logs, and hardware diagnostic tools\n• Collaborate with SoC/silicon vendors on display IP bring-up, driver patch integration, and resolving vendor-specific display controller and panel driver defects\n• Develop and maintain automated test suites and CI validation frameworks for display subsystem regression, compliance testing, and color accuracy verification\n• Author and maintain technical documentation including display driver design specs, integration guides, boot sequence diagrams, and troubleshooting runbooks for the display subsystem\n\nA day in the life\nSoC/Silicon Vendor Teams for display IP bring-up, DRM/KMS driver patches, panel driver support, and DPU firmware integration\nVideo Pipeline Teams for V4L2 driver integration, media framework alignment, and end-to-end display output routing\nBSP and Platform Teams for device tree configuration, kernel module integration, and boot sequence validation\nApplication and UI Framework Teams who consume the display output stack and depend on accurate color depth, HDR metadata, and panel timing\nQA and Automation Teams for display compliance testing, color accuracy verification, and regression validation\n\nBasic qualifications\n- Bachelor's degree or above in computer science, computer engineering, or related field\n- Experience in automating, deploying, and supporting infrastructure\n- Experience with Linux/Unix\n- Hands-on experience with DRM/KMS framework including CRTC configuration, plane management, connector setup, and atomic modesetting\n\nPreferred qualifications\n- Experience with CI/CD pipelines build processes\n- Working knowledge of V4L2 driver framework for video and display pipeline integration\n- Understanding of HDR/SDR conversion formats and color space management including HDR10, HLG, and tone mapping concepts\n- Understanding of display color depth configurations across 8-bit, 10-bit, and 12-bit pipelines including pixel format negotiation and dithering\n- Familiarity with bootsplash enablement and early kernel framebuffer initialization through kernel hand-off to userspace display stack\n- Minimum 1 year of experience with Linux kernel display subsystem or embedded display driver development\n\nOur inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "jd_status": "stored"}, {"title": "Senior Development Tools Software Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-28", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Senior-Development-Tools-Software-Engineer_JR0286526", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nIn this role, you'll build software capabilities to automate the build, test, and deployment of Intel's Process Design Kit (PDK). A PDK is a collection of artifacts representing Intel's semiconductor process, used by product designers to model, implement, and verify Intel's mobile, desktop, and server products before manufacturing. You'll be a member of the Design Technology Platform organization, working closely with teams in the United States, Bangalore, and Penang to build world-class DevOps infrastructure that shapes the future of deploying PDKs to silicon product development teams at Intel.\n\nQualifications:\nBachelor's or Master's degree in Computer Science, Computer Engineering, or another closely related field.\n7-12 years of experience with a Bachelor's degree or Master's degree in software development and engineering.\nExcellent Python programming skills.\nExpert-level knowledge of pytest concepts.\nExpert-level experience with GitHub-based Jenkins CI/CD deployment, enablement, and debugging.\nProven knowledge of Agile software engineering practices, IT environments, and DevOps principles and processes.\nExcellent debugging and problem-solving skills.\nExcellent written and verbal communication skills; ability to present complex issues with clarity to drive decisions.\nMust have hands-on experience with AI tools and demonstrated experience building AI agents/tools.\nExposure to VLSI PDK domain is preferred.\nStrong team player with proven ability to collaborate effectively across cross-functional and geographically distributed teams.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Staff/ Sr Staff Engineer, STA ", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-27T16:14:44.227000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000152030269-staff-sr-staff-engineer-sta-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking a seasoned Backend Design Expert specializing in Static Timing Analysis (STA) and Logic Synthesis. You will own the RTL-to-Gate conversion, constraint development, and final timing closure, ensuring our chips deliver maximum performance at the lowest possible power and area.  \nKey Responsibilities \nPhysical-Aware Synthesis and PPA optimization: Own and execute hierarchical synthesis flows to translate SystemVerilog RTL into optimized gate-level netlists. Execute physical-aware and floorplan-driven synthesis flows to minimize post-layout congestion and achieve PPA targets, identify bottlenecks and drive optimizations (e.g., critical path restructuring, datapath optimization). Conduct flat and hierarchical synthesis, ensuring seamless interface timing budgets. Manage formal verification (LEC) to ensure logical equivalence between RTL and netlist. UPF management for multiply power domains. \nTiming Closure & STA: Perform block-level and full-chip STA across multi-mode and multi-corner (MMMC) scenarios using industry-standard tools. Collaborate with PNR team, understand the clock tree and provide timely feedback to optimize the clock tree and achieve best QOR and perform STA signoff checks to closure.  \nConstraint Development: Architect, validate, and manage files, addressing both functional and DFT modes. Develop and manage comprehensive block-level and top-level constraints (SDC / UPF). \nLow-Power Implementation: Implement and verify UPF-based (Unified Power Format) low-power architectures and multi-voltage domains \nProgramming/Scripting: Strong scripting skills in Tcl, Python, or Perl to automate flows and improve design methodologies \n\nExperience of about 8-13 years in synthesis and STA closure. \nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. \nAbility to understand design specifications, can contribute to design planning, partitioning, and setup a feasible seed for convergence PD cycle. \nExtensive experience in STA closure on complex design with ability to understand the clocks structure from both functional and DFT side and provide solutions to complete design closure.  \nWorked on synthesis of high frequency designs and come up PPA solutions to meet the targets. \nGood understanding of EDA tools such as Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC. \nStrong understanding of static timing analysis, power analysis, and signal integrity analysis. \nExcellent problem-solving skills and attention to detail. \nExcellent scripting skills and development of utilities to reduce overall TAT. \nAbility to work effectively in a team environment and communicate clearly with cross-functional teams. \nExperience in mentoring and coaching junior engineers is a plus. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Engineer, Test Engineering - Product Development", "company": "Analog Devices", "location": "India, Bangalore, Nova", "date_posted": "2026-09-27", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-Nova/Senior-Engineer--Test-Engineering---Product-Development_R263262", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nTest Engineering - Product Development\n\nThe ASIC BU PTE Team which's part of the Digital Business Unit in ADI Bangalore is seeking a PTE engineer who’ll play a key role in testing state-of-the-art mixed signal & Digital SoC devices which are complex and industry leading. You'll become an integral member of the development team, participate in developing innovative, high performance, production ready hardware and software test solutions for our ASIC BU product portfolio.\n\nKey responsibilities include:\nDesign of innovative, reliable and efficient Probe and Test solutions on high performance mixed-signal/Digital ATE platforms (primarily ultra-flex and 93K) for multisite parallel testing\nDevelopment of the ATE software solutions as per the specifications\nPlay a role in DFT/BIST definition & development, through direct involvement with the Design Team early in the New Product Development, to reduce FFC and improve testability\nExecution of the Test development phases of the projects including Silicon functionality, Characterization, Yield Analysis, Correlation & Offshore Production release\n\n Qualifications\nThe ideal candidate should have a strong practical knowledge of Analog & Digital Electronics, be self-motivated, capable of accepting responsibility, show initiative and demonstrate strong skills in identifying and solving technical problems.\n\nKey Qualities:\nHave a degree in Electrical/Electronic Engineering\nHave minimum 4-5years’ of hands-on experience in mixed signal or digital test\nHave knowledge of the ATE software development and working knowledge of Teradyne Flex and/or 93K ATE systems\nHave good analytical & statistical skills and knowledge of the Perl/C++ programming\nBe experienced in ATE high-speed digital h/w design & layout, with lead skills in understanding the problems/limitations in hardware development\nBe experienced in releasing multi-site test programs to off-shore production test houses\nBe well versed with the usage of bench equipment such as Oscilloscope, VI meter, Signal generator and analyzers\nBe capable of working with the reliability engineers on the product qual\nBe proactive and work under own supervision\nBe self-motivated, and willing to accept responsibility\nPossess strong interpersonal, teamwork & communication skills\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Staff STA Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-09-27", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506721", "is_hardware": true, "platform": "oracle", "jd_text": "Description     \n\n OnSemi is seeking a Staff STA Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications.\n\n#LI-VS1\n\nResponsibilities\nResponsibilities    \n\nSTA Lead with expertise in timing constraints handling for different fullchip IO protocol (I2C, DDR, USB etc…)\n\n Generating ECO for timing closure for complex multi power domain designs\n\n Good experience in running STA regression with high number of modes/corners efficiently.\n\n Power recovery with STA signoffDebug constraint issues in P&R environment\n\n LEC/Low power checks experience\n\n Solid understanding of Verilog, TCL and Perl/Python/XML programming languages\n\n Strong in problem solving with deep understanding of technical issues.\n\n Candidate should have keen eye to improve existing flow and methods with positive impact on PPA.\n\n#LI-VS1\n\nQualifications\nQualifications\n\nBE in Electrical Engineering or related + 6 years of experience, or M.Tech + 5 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments\n\n Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF\n\n Solid understanding of Verilog, TCL and Perl/Python/XML programming languages\n\n Solid track record of releasing complex ICs to market \n\n Ability to clearly articulate issues, challenges, and concerns to all levels of management \n\n Must have good written and verbal cross-functional communication skills\n\n#LI-VS1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "DFT Principal Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-09-27", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506722", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Principal Physical DFT Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications.\n\n#LI-VS1\n\nResponsibilities\nIn this role, you will focus on the following: \nDFT Lead with expertise various Scan implementation like Stuck-At, MBIST, iJTAG, BSCAN, Transition, bridge faults\nProviding timing constraints for scan modes\nPattern simulation with zero delay and SDF\nCoverage analysis and improvement suggestions to design\nLow power issues fix post DFT implementation\nPost silicon debug\nSolid understanding of Verilog, TCL and Perl/Python/XML programming languages\nStrong in problem solving with deep understanding of technical issues.\nCandidate should have keen eye to improve existing flow and methods with positive impact on PPA.\n#LI-VS1\n\nQualifications\nQualifications\nBS in Electrical Engineering or related + 12 years of experience, or MS + 11 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments\nSolid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF\nSolid understanding of Verilog, TCL and Perl/Python/XML programming languages\nSolid track record of releasing complex ICs to market \nAbility to clearly articulate issues, challenges, and concerns to all levels of management \nMust have good written and verbal cross-functional communication skills\n#LI-VS1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "NPU AI/Processor Synthesis Engineer- Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-26T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720780780", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Overview\nWe are seeking a highly motivated Synthesis Engineer/Lead to join our NPU (Neural Processing Unit) design team. In this role, you will drive RTL-to-GDS synthesis and timing closure for high-performance AI/ML accelerators used in next-generation SoCs. You will work closely with Architecture, RTL Design, STA, DFT, and Physical Design teams to deliver high-quality, power-efficient silicon on advanced technology nodes.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nKey Responsibilities\nOwn RTL-to-gate synthesis and timing closure for NPU IPs and subsystems.\nDevelop and maintain synthesis flows, constraints, and automation for complex hierarchical designs.\nDrive pre-layout and post-layout timing closure across multiple modes and process corners.\nOptimize designs for PPA (Performance, Power, Area) targets using physical-aware synthesis methodologies.\nCreate, validate, and maintain timing constraints (SDC), clock definitions, false paths, and multi-cycle paths.\nCollaborate with RTL, DFT, STA, and Physical Design teams to resolve QoR, timing, power, and convergence issues.\nPerform quality checks including LEC, CDC, lint, and low-power verification.\nAnalyze and improve synthesis QoR through scripting and flow enhancements.\nSupport tapeout activities and drive continuous improvements in synthesis methodologies.\nRequired Qualifications\nBachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or related field.\nStrong understanding of ASIC design flow from RTL to GDS.\nHands-on experience with RTL synthesis, timing closure, and constraint development.\nExpertise in Synopsys Design Compiler/Fusion Compiler or Cadence Genus.\nStrong timing analysis knowledge using PrimeTime.\nExperience with low-power design methodologies and UPF-based flows.\nGood understanding of clocking architecture, timing constraints, and timing signoff.\nProficiency in TCL and scripting languages such as Python or Perl.\nExcellent debugging, problem-solving, and cross-functional collaboration skills.\nPreferred Qualifications\nExperience working on AI/ML accelerators, NPU, DSP, GPU, CPU, or other high-performance compute architectures.\nKnowledge of advanced technology nodes (5nm, 4nm, 3nm and below).\nExperience with physical-aware synthesis and hierarchical design methodologies.\nFamiliarity with LEC, CDC, lint, power analysis, and low-power verification flows.\nProven track record of successful SoC or IP tapeouts.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Engineer - BT/UWB validation and system integration", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-26T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721255550", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nDept Description and Job Duties: The BDC BT VI team are looking for an adaptable, enthusiastic, and reliable individual to form an integral part of our BT/UWB validation and system integration team in Bangalore. The team will work closely with the BT HW (DD, DV, EMU), FW/SW, SOC and Systems teams across Geos. The team plays a pivotal role in testing HW IP and lower layer controller FW on pre-silicon emulation and post-silicon environment, system bring-up & integration for the company’s Connectivity products. Working within our team provides a unique opportunity to work across the engineering disciplines from high level SOC to low-level hardware/firmware. Typical tasks for the successful applicant would include:\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field.\n\n· Interpreting wireless specifications and product requirements\n· Developing test cases in C/python/TCL/.CMM or similar scripting language\n· Collaborate with senior team members to troubleshoot HW/FW/SW issues and find solutions that are documented and shared with internal cross functional teams working on similar products.\n· Analysis and support bug fixes during final stages of program to customers\n· Communication of status/bugs/issues to leads\n· Software and hardware debug of testing issues\n· Working with other team members to plan development, testing and maintenance work\n\n \nMinimum Qualifications:\n               · BTech with 1-6 years or MTech with 1-5 years of relevant experience -Preparable ECE\n \nAttributes required:\n\n ·Proficient in C and python programming skills\n· Technical background in wireless communication systems such as cellular, Bluetooth, UWB, WLAN and IEEE 802.15.4 with validation experience\n· Familiar with Pre-Silicon and Post Silicon SOC Baremetal/FW based validations including power, performance associated and Automate test execution\n· A good understanding of electronic hardware and reading schematics : Possess knowledge of standard lab equipment including Oscilloscope, Spectrum analyzer, logic analyzers, oscilloscope, Bluetooth tester, Protocol analyzers, and RF test equipment\n· A good understanding Microcontrollers & Architectures: like Risc V, Andes, ARM\n· Technical background  in Interfaces: JTAG, J-Link, UART, SPI, I2C, I3C, USB\n· Strong debugging skills at the hardware-software boundary using JTAG, serial consoles, and vendor tools\n· Self-motivated, adaptable team player\n· Comfortable with taking responsibility for their team\nTo be familiar with AI tools/usage \n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NPU/AI Processor Synthesis (Design implementation) - Staff Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-25T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718668666", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Overview\n\nWe are seeking a highly motivated Synthesis Engineer/Lead to join our NPU (Neural Processing Unit) design team. In this role, you will drive RTL-to-GDS synthesis and timing closure for high-performance AI/ML accelerators used in next-generation SoCs. You will work closely with Architecture, RTL Design, STA, DFT, and Physical Design teams to deliver high-quality, power-efficient silicon on advanced technology nodes.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nKey Responsibilities\nOwn RTL-to-gate synthesis and timing closure for NPU IPs and subsystems.\nDevelop and maintain synthesis flows, constraints, and automation for complex hierarchical designs.\nDrive pre-layout and post-layout timing closure across multiple modes and process corners.\nOptimize designs for PPA (Performance, Power, Area) targets using physical-aware synthesis methodologies.\nCreate, validate, and maintain timing constraints (SDC), clock definitions, false paths, and multi-cycle paths.\nCollaborate with RTL, DFT, STA, and Physical Design teams to resolve QoR, timing, power, and convergence issues.\nPerform quality checks including LEC, CDC, lint, and low-power verification.\nAnalyze and improve synthesis QoR through scripting and flow enhancements.\nSupport tapeout activities and drive continuous improvements in synthesis methodologies.\nRequired Qualifications\nBachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or related field.\nStrong understanding of ASIC design flow from RTL to GDS.\nHands-on experience with RTL synthesis, timing closure, and constraint development.\nExpertise in Synopsys Design Compiler/Fusion Compiler or Cadence Genus.\nStrong timing analysis knowledge using PrimeTime.\nExperience with low-power design methodologies and UPF-based flows.\nGood understanding of clocking architecture, timing constraints, and timing signoff.\nProficiency in TCL and scripting languages such as Python or Perl.\nExcellent debugging, problem-solving, and cross-functional collaboration skills.\nPreferred Qualifications\nExperience working on AI/ML accelerators, NPU, DSP, GPU, CPU, or other high-performance compute architectures.\nKnowledge of advanced technology nodes (5nm, 4nm, 3nm and below).\nExperience with physical-aware synthesis and hierarchical design methodologies.\nFamiliarity with LEC, CDC, lint, power analysis, and low-power verification flows.\nProven track record of successful SoC or IP tapeouts.\nExperience\nSenior Engineer: 3-5 years of relevant experience.\nLead Engineer: 5-8 years of relevant experience.\nStaff Engineer: 8-12 years of relevant experience.\nSr Staff Engineer: 12-18 years of relevant experience.\nPrincipal Engineer: 18+ years of relevant experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NPU Synthesis Engineer, Principal", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-25T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720292006", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nJob Overview\nWe are seeking a highly motivated Synthesis Engineer/Lead to join our NPU (Neural Processing Unit) design team. In this role, you will drive RTL-to-GDS synthesis and timing closure for high-performance AI/ML accelerators used in next-generation SoCs. You will work closely with Architecture, RTL Design, STA, DFT, and Physical Design teams to deliver high-quality, power-efficient silicon on advanced technology nodes.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nKey Responsibilities\nOwn RTL-to-gate synthesis and timing closure for NPU IPs and subsystems.\nDevelop and maintain synthesis flows, constraints, and automation for complex hierarchical designs.\nDrive pre-layout and post-layout timing closure across multiple modes and process corners.\nOptimize designs for PPA (Performance, Power, Area) targets using physical-aware synthesis methodologies.\nCreate, validate, and maintain timing constraints (SDC), clock definitions, false paths, and multi-cycle paths.\nCollaborate with RTL, DFT, STA, and Physical Design teams to resolve QoR, timing, power, and convergence issues.\nPerform quality checks including LEC, CDC, lint, and low-power verification.\nAnalyze and improve synthesis QoR through scripting and flow enhancements.\nSupport tapeout activities and drive continuous improvements in synthesis methodologies.\nRequired Qualifications\nBachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or related field.\nStrong understanding of ASIC design flow from RTL to GDS.\nHands-on experience with RTL synthesis, timing closure, and constraint development.\nExpertise in Synopsys Design Compiler/Fusion Compiler or Cadence Genus.\nStrong timing analysis knowledge using PrimeTime.\nExperience with low-power design methodologies and UPF-based flows.\nGood understanding of clocking architecture, timing constraints, and timing signoff.\nProficiency in TCL and scripting languages such as Python or Perl.\nExcellent debugging, problem-solving, and cross-functional collaboration skills.\nPreferred Qualifications\nExperience working on AI/ML accelerators, NPU, DSP, GPU, CPU, or other high-performance compute architectures.\nKnowledge of advanced technology nodes (5nm, 4nm, 3nm and below).\nExperience with physical-aware synthesis and hierarchical design methodologies.\nFamiliarity with LEC, CDC, lint, power analysis, and low-power verification flows.\nProven track record of successful SoC or IP tapeouts.\nExperience\nSenior Engineer: 3-5 years of relevant experience.\nLead Engineer: 5-8 years of relevant experience.\nStaff Engineer: 8-12 years of relevant experience.\nSr Staff Engineer: 12-18 years of relevant experience.\nPrincipal Engineer: 18+ years of relevant experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NPU AI/Processor Synthesis Engineer- Sr Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-25T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720292004", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nJob Overview\n\nWe are seeking a highly motivated Synthesis Engineer/Lead to join our NPU (Neural Processing Unit) design team. In this role, you will drive RTL-to-GDS synthesis and timing closure for high-performance AI/ML accelerators used in next-generation SoCs. You will work closely with Architecture, RTL Design, STA, DFT, and Physical Design teams to deliver high-quality, power-efficient silicon on advanced technology nodes.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nKey Responsibilities\nOwn RTL-to-gate synthesis and timing closure for NPU IPs and subsystems.\nDevelop and maintain synthesis flows, constraints, and automation for complex hierarchical designs.\nDrive pre-layout and post-layout timing closure across multiple modes and process corners.\nOptimize designs for PPA (Performance, Power, Area) targets using physical-aware synthesis methodologies.\nCreate, validate, and maintain timing constraints (SDC), clock definitions, false paths, and multi-cycle paths.\nCollaborate with RTL, DFT, STA, and Physical Design teams to resolve QoR, timing, power, and convergence issues.\nPerform quality checks including LEC, CDC, lint, and low-power verification.\nAnalyze and improve synthesis QoR through scripting and flow enhancements.\nSupport tapeout activities and drive continuous improvements in synthesis methodologies.\nRequired Qualifications\nBachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or related field.\nStrong understanding of ASIC design flow from RTL to GDS.\nHands-on experience with RTL synthesis, timing closure, and constraint development.\nExpertise in Synopsys Design Compiler/Fusion Compiler or Cadence Genus.\nStrong timing analysis knowledge using PrimeTime.\nExperience with low-power design methodologies and UPF-based flows.\nGood understanding of clocking architecture, timing constraints, and timing signoff.\nProficiency in TCL and scripting languages such as Python or Perl.\nExcellent debugging, problem-solving, and cross-functional collaboration skills.\nPreferred Qualifications\nExperience working on AI/ML accelerators, NPU, DSP, GPU, CPU, or other high-performance compute architectures.\nKnowledge of advanced technology nodes (5nm, 4nm, 3nm and below).\nExperience with physical-aware synthesis and hierarchical design methodologies.\nFamiliarity with LEC, CDC, lint, power analysis, and low-power verification flows.\nProven track record of successful SoC or IP tapeouts.\nExperience\nSenior Engineer: 3-5 years of relevant experience.\nLead Engineer: 5-8 years of relevant experience.\nStaff Engineer: 8-12 years of relevant experience.\nSr Staff Engineer: 12-18 years of relevant experience.\nPrincipal Engineer: 18+ years of relevant experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NPU AI/Processor Synthesis Engineer- Sr Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-25T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720780775", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nJob Overview\n\nWe are seeking a highly motivated Synthesis Engineer/Lead to join our NPU (Neural Processing Unit) design team. In this role, you will drive RTL-to-GDS synthesis and timing closure for high-performance AI/ML accelerators used in next-generation SoCs. You will work closely with Architecture, RTL Design, STA, DFT, and Physical Design teams to deliver high-quality, power-efficient silicon on advanced technology nodes.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nKey Responsibilities\nOwn RTL-to-gate synthesis and timing closure for NPU IPs and subsystems.\nDevelop and maintain synthesis flows, constraints, and automation for complex hierarchical designs.\nDrive pre-layout and post-layout timing closure across multiple modes and process corners.\nOptimize designs for PPA (Performance, Power, Area) targets using physical-aware synthesis methodologies.\nCreate, validate, and maintain timing constraints (SDC), clock definitions, false paths, and multi-cycle paths.\nCollaborate with RTL, DFT, STA, and Physical Design teams to resolve QoR, timing, power, and convergence issues.\nPerform quality checks including LEC, CDC, lint, and low-power verification.\nAnalyze and improve synthesis QoR through scripting and flow enhancements.\nSupport tapeout activities and drive continuous improvements in synthesis methodologies.\nRequired Qualifications\nBachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or related field.\nStrong understanding of ASIC design flow from RTL to GDS.\nHands-on experience with RTL synthesis, timing closure, and constraint development.\nExpertise in Synopsys Design Compiler/Fusion Compiler or Cadence Genus.\nStrong timing analysis knowledge using PrimeTime.\nExperience with low-power design methodologies and UPF-based flows.\nGood understanding of clocking architecture, timing constraints, and timing signoff.\nProficiency in TCL and scripting languages such as Python or Perl.\nExcellent debugging, problem-solving, and cross-functional collaboration skills.\nPreferred Qualifications\nExperience working on AI/ML accelerators, NPU, DSP, GPU, CPU, or other high-performance compute architectures.\nKnowledge of advanced technology nodes (5nm, 4nm, 3nm and below).\nExperience with physical-aware synthesis and hierarchical design methodologies.\nFamiliarity with LEC, CDC, lint, power analysis, and low-power verification flows.\nProven track record of successful SoC or IP tapeouts.\nExperience\nSenior Engineer: 3-5 years of relevant experience.\nLead Engineer: 5-8 years of relevant experience.\nStaff Engineer: 8-12 years of relevant experience.\nSr Staff Engineer: 12-18 years of relevant experience.\nPrincipal Engineer: 18+ years of relevant experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Physical Design Sr / Lead / Staff Engineer - Camera", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-25T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721248582", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nGeneral Summary:\nExperience:\n3 - 15 years of experience in Physical Design, including floorplanning, Place & Route (PNR), Clock Tree Synthesis (CTS), and STA signoff checks\nHands-on experience owning end-to-end Physical Design from netlist to GDSII, including HM-level PV, LEC, low-power checks, PDN design, and STA closure\nExperience with voltage islands and low-power design methodologies, flows, and implementation\nStrong focus on achieving optimal PPA (Power, Performance, Area)\nStrong familiarity with industry-standard tools such as Fusion Compiler (FC), Genus, Innovus, , PrimeTime (PT), Tempus, Voltus, and RedHawk\nSolid understanding of the full Physical Design flow from floorplanning to post-route optimization and timing signoff, including IR drop analysis and physical verification\nExperience in implementing complex ECOs for timing convergence across multiple corners using Tweaker, Tempus, and physical ECO flows in PrimeTime\nKnowledge of power optimization techniques and methods to minimize power consumption\nExperience in deep submicron technology nodes (preferred)\nUnderstanding of high-performance and low-power implementation techniques (preferred)\nStrong fundamentals in Physical Design and VLSI concepts\nProficiency in scripting languages such as Perl, Python and TCL\nRoles and Responsibilities\nCollaborate with cross-functional teams (Design, CAD) to address critical physical design challenges in Camera PNR Implementation.\nDevelop innovative techniques within Physical Design and optimization space to meet stringent PPA targets.\nEngage with external CAD tool vendors and internal CAD teams to identify and enhance optimization issues related to Camera designs.\nPartner with all block-level implementation teams to analyze, implement, and improve optimization methods relevant to the designs.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Synthesis Engineer, Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-25T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721248735", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nMinimum Qualificationso 4+ Year of industry experiences in the following areas: Expertise in Synthesis - Synopsys Design Compiler, DCG/DC_NXT/Fusion Compiler and/or Cadence RC/Genus.\no Expertise on with multi-voltage, power aware synthesis, UPF flows in synthesis and low power designs.\no Expertise in formal verification with Cadence LEC/ Synopsys Formality\no Expertise in writing and debugging timing constraints\no Perl and/or TCL scripting, makefile flows.\nAdditional Job DescriptionMasters in Electronics or Electrical Engineeringwork on integration or RTL design is considered plus.Candidates should have excellent analytical and problem-solving skillsTrack record of driving ideas from design through commercialization  \n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RF Bench Characterization Engineer, Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-25T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718808538", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nRF Bench Characterization Engineer\nRole:\nThe BDC Post Silicon Engineering group has an opening for a RF Bench Characterization Engineer. This group develops Test solutions for design verification of highly integrated Receivers/Transmitters/Transceivers and Mixed signal ASICs designed by QCT.  Job responsibilities for this position include New Test methodology implementation, Device Verification and Characterization, Design and debug of Test interface hardware, Test automation, and Data analysis.\nSkills/Experience:\nSolid software skills for writing and debugging Test Automation code. Competency in automation development using at least 1 automation tool (C#, Python, LabVIEW).\nExpertise on developing test automation through remote control of instrument.\nSolid understanding of Electronics engineering fundamentals, Mixed-signal and RF circuit analysis techniques.\nGood knowledge of Mixed-signal and RF measurement techniques such as Harmonics, EVM, IP3, Noise Figure, ACPR, Jitter, Phase noise and Lock time.\nGood ASIC device level post silicon validation skills. System level knowledge is a plus.\nAble to work hands on with Lab equipment like Spectrum analyzer, Signal Generator, Network Analyzer and Digitizer.\nKnowledge of Mixed-signal and RF PCB bring-up and debug. Using CAD software such as Mentor Graphics DA or Cadence Allegro is a plus.\nKnowledge of statistical analysis techniques, quality and reliability testing. Wafer fabrication fundamentals is a plus.\nAble to work independently with initiative through challenges, Technical or otherwise.\nAble to communicate clearly, organize effectively and document work thoroughly while working with local and global teams.\n\nEducation Requirements:\nB.E, M.E or equivalent.\n4 years plus experience.\n\nKey Terms to Find on Resumes:\nRF Post Silicon Validation, C#, Python, LabVIEW, Test Automation, RF, Mixed Signal, Analog, Bench Characterization\n\n \n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SOC Design Verification Assoc Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-25T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721244330", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nQualcomm Overview:\nQualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.\n\nGeneral Summary:\nUnderstand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.\n\nResponsible to implement and analyze system Verilog assertion and coverage(code, toggle, functional) .\n\nWork alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue.\n\nCollaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nAdhere to quality standards and good test and verification practices.\n\nB.E/B. Tech/M.E/M. Tech in electronics with 1+ year experience in verification domain.\n\nPrior work experience on IP level or Soc level.\n\nPrior work on UFS (Universal Flash Storage),Ethernet and PCIe Protocol is desirable.\n\nGood understanding of processor based Soc level verification  which includes native ,Verilog ,system Verilog and UVM mix environment.\n\nHand on experience with verification tools such as VCS, waveform analyzer and  third party VIP integration (such as Synopsys VIPs).\n\nHands on experience in UVM. C/C++ ,System Verilog verification language.\n\nGood understanding of AXI-AMBA  protocol variants.\n\nCan work with scripting language (shell, Makefile, Perl )\n\nStrong understanding of design concepts and ASIC flow.\n\nGood problem solving , analytical and debugging skill is must.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail myhr.support@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Mixed- Signal Systems and Verification Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-09-25", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Mixed--Signal-Systems-and-Verification-Engineer_R55855", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nQualifications • New graduates strongly encouraged to apply! • Experience in developing and verifying real-numbered behavioral models in SystemVerilog • Understanding of SystemVerilog, RNM, UDN/UDT/UDR, wreal, and Verilog-AMS • Basic understanding of AMS blocks like filters, ADC, DAC, VCO, A/DPLL, SerDes, LNA, Mixer, etc • Working experience in low power Architecture • Working experience in Cadence Virtuoso Schematic Composer and ADE • Experience with Analog Assertion Based Verification • Experience in TB development will be a strong plus • Experience in writing scripts in languages such as Perl or Python • Excellent teammate with excellent communication skills • Experience with FPGA prototyping is a plus Responsibilities • You will become part of a hands-on development team that fosters engineering excellence, creativity, and innovation. • As an AMS Verification Engineer, you will be responsible for Developing accurate and simulation-efficient analog behavioral models for analog/RF blocks in SystemVerilog. • Verifying that the behavior models are accurate representations of analog schematics • Integrating the models with RTL • Verifying analog functionalities against design specifications using analog behavioral models: for example, coding test benches, test scenarios, and assertions. • DSP experience a huge plus. Documenting modeling and verification results for formal review We’re doing work that matters. Help us solve what others can’t\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Lead PDN/EMIR Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-09-25", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Lead-PDN-EMIR-Engineer_R-10066221", "is_hardware": true, "platform": "workday", "jd_text": "Required Qualifications\nB.Tech/M.Tech in Electronics, Electrical Engineering, VLSI, or related field.\n8+ years of experience in Physical Design, Power Integrity, or Signoff.\n\nKey Responsibilities\nTechnical Skills:\nOwn full-chip and subsystem-level PDN signoff for complex SoCs.\nDefine PDN signoff criteria across project milestones.\nDrive power integrity closure for functional, DFT, LBIST, capture, and stress modes.\nLead package-aware IR/EM analysis and chip-package co-optimization.\nDefine and review power grid architecture, bump planning, power switch strategy, and decap methodology.\nDrive Vmin, peak EM, dynamic IR, and thermal-aware analysis.\nMethodology & Innovation\nDevelop next-generation PDN signoff methodologies.\nAutomate PDN flows using TCL/Python/Shell.\nImprove runtime, capacity, dashboarding, and regression infrastructure.\nCollaborate with EDA vendors (Ansys/Cadence/Synopsys) for feature enhancements and tool debug.\nEstablish best practices and reusable signoff frameworks across projects.\nCross-Functional Collaboration\nWork closely with Physical Design teams to drive PDN-aware floorplanning, placement, routing, and ECO solutions.\nPartner with DFT teams to optimize pattern power and capture-mode reliability.\nCollaborate with Package and Thermal teams on package RLC optimization and thermal correlation.\nSupport silicon bring-up, debug, and correlation of pre-silicon versus post-silicon measurements.\nProject Execution\nProvide technical risk assessment and mitigation plans.\nDrive closure of critical PDN hotspots with minimal PPA impact.\nPresent signoff status to management and project stakeholders.\nEnsure on-time delivery for tapeout milestones.\nLead reviews for high-risk blocks and top-level integrations.\nPeople Leadership\nMentor engineers and PDN owners across multiple projects.\nDefine training content and technical roadmaps for the team.\nLead technical reviews and establish signoff governance.\nInfluence organizational PDN strategy and future technology direction.\n\n#LI-DNI", "jd_status": "stored"}, {"title": "Lead STA Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-09-25", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Lead-STA-Engineer_R-10066213", "is_hardware": true, "platform": "workday", "jd_text": "Summary: Seeking a highly skilled and experienced Lead STA Engineer to lead and execute static timing analysis for complex semiconductor designs, ensuring timing closure and performance targets are met. This role involves guiding a team, developing methodologies, and collaborating with design and verification teams to deliver high-quality products.\n\nJob Qualification:\nMaster's degree or Bachelor's degree in Electronics/ Electrical Engineering, Computer Engineering, or a related field.\n7+ years of hands-on experience in static timing analysis for complex ASIC/SoC designs.\nExperience of Multi mode timing constraint development, execution, and final timing signoff for advanced technology nodes\nProven experience leading STA efforts for multiple successful tape-outs.\nExpertise in industry-standard STA tools (e.g., Synopsys PrimeTime, Cadence Tempus).\nStrong understanding of digital design fundamentals, clocking architectures, and low-power techniques\n In-depth knowledge of timing constraints (SDC) and their application.\n Proficiency in scripting languages such as Perl, Python, or TCL.\nStrong communication and interpersonal skills, with the ability to collaborate effectively in a global team environment.\nWork closely with Architects,Front End,DFT and the PD team to understand design,clocking,timing ,Requirements and lead the writing constraints and closing timing activities\n\nKey Responsibilities\nConstraint Development: Create, validate, and maintain Synopsys Design Constraints (SDC) for block and full-chip levels, covering false paths, multicycle paths, and test modes.\nTiming Signoff: Perform exhaustive timing analysis across multiple corners and modes (MCMM), adhering to process, voltage, and temperature (PVT) variations.\nViolation Debugging: Debug and resolve setup, hold, transition, and path-based violations (PBA).\nOptimization & ECO: Drive timing closure by generating and evaluating timing Engineering Change Orders (ECOs).\nCross-functional Collaboration: Partner with RTL, physical design, and DFT teams to ensure robust timing integration and refine timing models.\nTool & Flow Automation: Develop and support implementation flows using industry-standard Electronic Design Automation (EDA) tools and improve script-based automation.\nDrive a small team of STA engineers.\nShould be able to do IP level synthesis.\n\nMore information about NXP in India...\n\n#LI-7013", "jd_status": "stored"}, {"title": "Sr Design Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-09-25", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Sr-Design-Engineer_R-10066921", "is_hardware": true, "platform": "workday", "jd_text": "Key Responsibilities\nDesign and develop custom IO circuits including:GPIO\nLVDS\nLVCMOS\nSSTL\nHSTL\nDDR Interfaces\nHigh-speed SerDes support circuits\n\nPerform transistor-level design and simulation using advanced CMOS technology nodes.\nDevelop and optimize:ESD protection circuits\nLevel shifters\nInput buffers\nOutput drivers\nOn-chip termination circuits\n\nConduct pre-layout and post-layout simulations for functionality, timing, power, noise, and reliability.\nPerform signal integrity analysis including:IBIS model generation\nPackage-aware simulations\nCrosstalk and reflection analysis\n\nDrive layout reviews and work closely with physical design teams to ensure design quality and performance targets.\nSupport silicon bring-up, characterization, debugging, and production ramp activities.\nCollaborate with system, package, reliability, and product engineering teams.\nDevelop and maintain design documentation, specifications, and verification reports.\n\nRequired Qualifications\nBachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, or related field.\n2-4 years of experience in Analog/Mixed-Signal or IO Circuit Design.\nStrong understanding of:CMOS device physics\nAnalog circuit design fundamentals\nIO architectures and standards\nESD design methodologies\n\nHands-on experience in custom circuit design using Cadence Virtuoso.\nExpertise in SPICE-based simulators such as Spectre, HSPICE, or FineSim.\nExperience with advanced technology nodes (16nm/7nm/5nm preferred).\nGood knowledge of LVS, DRC, EMIR, and reliability checks.\nFamiliarity with process corners, Monte Carlo analysis, and yield optimization techniques.\n\nPreferred Skills\nExperience with DDR4/DDR5, LPDDR, USB, PCIe, MIPI, or Ethernet interfaces.\nKnowledge of package modeling and SI/PI analysis tools.\nUnderstanding of ESD standards such as HBM, CDM, and IEC.\nExperience in silicon validation and lab characterization.\nScripting skills in Python, Perl, Tcl, or SKILL.\nFamiliarity with IBIS and IBIS-AMI model generation.\n\nDesired Competencies\nStrong analytical and debugging skills.\nExcellent communication and cross-functional collaboration.\nAbility to lead technical discussions and mentor junior engineers.\nProven track record of delivering silicon successfully from specification to production.\nSelf-driven with strong problem-solving abilities.\n\nNice to Have\nExperience in automotive, AI/ML, networking, mobile, or data center SoCs.\nExposure to functional safety and reliability requirements.\nPrior ownership of complete IO IP development cycle.\nThis role is ideal for an engineer who has hands-on experience in IO circuit design, ESD, signal integrity, and silicon validation, and is looking to contribute to next-generation semiconductor products.\n\nMore information about NXP in India...\n\n#LI-7013", "jd_status": "stored"}, {"title": "Staff Digital Verification Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-25", "url": "https://careers.synopsys.com/job/bengaluru/staff-digital-verification-engineer/44408/101119414208", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years building verification environments that have to catch the bugs no one else saw coming, the corner cases that only show up when three protocols collide and a timing edge goes the wrong way. You know that a test plan is only as good as the bugs it finds, and you have learned to think like the design, like the system integrator, and like the customer all at once.\nYou are the engineer who sees a coverage hole at 95% and knows exactly which scenario is missing. Writing assertions is not a checkbox exercise for you, it is how you encode your understanding of what should never happen. You have debugged enough waveforms to know when something smells wrong three layers deeper than the symptom.\nLeading a verification effort means more than running regressions. You set the strategy, you review the test plans your team writes, and you make the call on what gets verified to what depth. You work directly with RTL designers and architects, not to rubber-stamp their work but to push back when the intent is unclear or the interface is going to be painful to verify.\nAt Synopsys, you will work on DesignWare IP that ships into real products. The verification environments you build will be used across product generations, and the bugs you catch will never make it to silicon.\nWhat You'll Be Doing\nBuild and evolve SystemVerilog/UVM verification environments for DesignWare synthesizable IP cores, ensuring they scale across multiple product generations and configurations\nDefine comprehensive test plans that cover corner cases, protocol compliance, and system-level interactions for serial interface protocols and memory controllers, including DDR and LPDDR where applicable\nWrite and debug complex testbenches, checkers, and assertions that catch real bugs in critical PHY blocks and interface logic\nDevelop software requirements for the PHY that scale across various configurations and use cases\nOwn verification closure for multiple critical blocks within DDR PHYs, including functional coverage, code coverage, and formal signoff\nCollaborate directly with RTL designers, digital architects, and circuit teams to align verification scope with design intent and surface issues early in the design cycle\nManage regression infrastructure and work with the infra team to optimize verification cycles, debug failures, and keep the environment reliable\n\nThe Impact You Will Have\nYour verification environments will catch critical bugs before tapeout, directly affecting the quality and time-to-market of DesignWare IP used across the semiconductor industry\nThe test plans you define and review will set the verification standard for the team, ensuring consistent coverage and reducing escapes\nYour coverage-driven approach will surface gaps that others miss, leading to more robust IP and fewer silicon respins\nThe assertions and checkers you write will become reusable verification IP, accelerating future projects and raising the quality bar\nYour collaboration with RTL and architecture teams will shape design decisions early, making designs easier to verify and more reliable in the field\nThe regression strategies you implement will directly improve team productivity and reduce verification cycle time\nYour ownership of critical PHY blocks will ensure that high-stakes features meet functional and performance requirements on schedule\n\nWhat You'll Need\nBachelor's or Master's in Electrical Engineering or Electronics and Communication Engineering with 4+ years of hands-on verification experience\nProven track record leading verification teams through IP project delivery, including planning, execution, and signoff\nStrong experience developing SystemVerilog/UVM testbenches from scratch and evolving them as designs grow in complexity\nDeep expertise writing test plans, implementing checkers, and building assertions that catch real bugs, not just toggle coverage\nProficiency extracting and interpreting functional coverage and code coverage metrics, and using those insights to drive verification closure\nExperience verifying serial interface protocols and working through IP design and verification processes, knowledge of DDR or LPDDR protocols is a strong plus\nDemonstrated ability to own end-to-end verification deliverables, including metric closure and formal review signoff, experience with AI-assisted verification tools is a plus\n\nWho You Are\nYou can walk into a coverage review, spot the gap in the test plan, and articulate exactly what scenario is missing and why it matters\nYou write assertions that encode real design intent, not just the obvious cases, and you know the difference between a checker that catches bugs and one that just makes noise\nYou are comfortable leading technical discussions with RTL designers and architects, pushing back when verification scope is unclear or the interface is going to create downstream pain\nYou manage multiple verification efforts in parallel without losing track of what is at risk, what is on schedule, and what needs attention today\nYou debug with purpose, you do not just stare at waveforms hoping for insight, you form hypotheses, test them, and move systematically toward root cause\nYou treat verification infrastructure as a product, you care about regression efficiency, debug turnaround time, and whether your environment is actually usable by the rest of the team\n\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "R&D Engineering, Sr Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-25", "url": "https://careers.synopsys.com/job/bengaluru/r-and-d-engineering-sr-engineer/44408/101119414080", "is_hardware": true, "platform": "talentbrew", "jd_text": "Alternate Job TitlesStandard Cell Library Characterization Engineer\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent enough time in library characterization to know that a Liberty model is only as good as the corner cases you tested and the correlations you actually validated. You understand that when a designer's STA run fails because of a timing model mismatch, it is not just a data issue, it is hours of someone's schedule gone, and you take that seriously.\nYou are comfortable moving between SPICE simulations, Liberty file generation, and debugging why a CCS noise model behaves differently than expected across PVT corners. When a correlation gap shows up between characterization and static timing analysis, you do not just log it, you dig in, reproduce it, and figure out what assumption broke down.\nYou know the difference between running a characterization flow and owning it. Running it means you execute scripts. Owning it means you catch the issue before QA does, you spot the pattern in regression failures, and you know when a model needs another pass even if it technically meets spec.\nAt Synopsys, you will work on standard cell libraries that power advanced node designs across the semiconductor industry. The libraries you characterize will be used in real tapeouts, and the quality bar is not negotiable.\nWhat You'll Be Doing\nCharacterize and model standard cell libraries for advanced technology nodes, generating Liberty files including NLDM, NLPM, CCS timing, CCS noise, ECSM, LVF, AOCV, POCV, spatial OCV, aging, and EM models\nHandle characterization across a wide range of cell types: combinational, sequential, clock gating, synchronizers, retention, level shifters, power gating, always-on, filler, and decap cells\nDebug and resolve correlation issues between characterization results, static timing analysis, and SPICE simulations, working across tool flows to identify root causes\nExecute QA checks, regression analysis, and release validation to ensure library deliverables meet quality and accuracy standards before they ship\nDrive methodology improvements and automation initiatives that make characterization flows faster, more reliable, and easier to maintain across multiple projects\nCoordinate project execution timelines, manage deliverables, and communicate status across cross-functional teams including design, verification, and product engineering\nSupport library releases by validating models against design rule checks, performing sanity testing, and ensuring documentation is complete and accurate\nThe Impact You Will Have\nEnable accurate timing closure for advanced node designs by delivering high-quality Liberty models that designers and STA tools depend on\nReduce correlation gaps between characterization and silicon behavior, improving predictability and reducing costly respins for customers\nAccelerate library development cycles by building automation and improving characterization flows that scale across multiple technology nodes\nIncrease library quality and reliability through rigorous QA, regression testing, and validation processes that catch issues before release\nSupport successful tapeouts by ensuring standard cell libraries meet performance, power, and area targets across all operating conditions\nContribute to methodology evolution by identifying gaps, proposing solutions, and implementing improvements that benefit the entire characterization team\nHelp Synopsys maintain its leadership in library IP by delivering models that meet the precision and robustness requirements of cutting-edge semiconductor designs\nWhat You'll Need\nBachelor's or Master's degree in Electronics, VLSI, Microelectronics, or a related technical field\n2+ years of hands-on experience in standard cell library characterization and Liberty modeling\nStrong understanding of Liberty file formats including NLDM, CCS, ECSM, and advanced modeling constructs like AOCV, POCV, and aging models\nExperience characterizing multiple cell types: combinational, sequential, clock gating, level shifters, retention, or power management cells\nSolid grasp of SPICE simulation, timing analysis concepts, and correlation methodologies between characterization tools and STA flows\nProficiency in scripting languages like Python, Tcl, or Perl for automation, data analysis, and flow development\nExperience with industry-standard characterization tools and STA platforms is a strong plus\nWho You Are\nYou can look at a Liberty file and spot when a timing arc does not make sense or a capacitance value looks off, and you know how to trace it back to the characterization setup\nWhen a correlation issue appears, you do not wait for someone else to debug it, you pull the SPICE deck, compare waveforms, and figure out where the model diverged\nYou are organized enough to manage multiple library releases in parallel without losing track of which models are validated, which are in QA, and which need another pass\nYou can explain a complex characterization issue to a design engineer or a project lead in a way that makes sense without dumbing it down or losing the technical detail\nYou push back when a release timeline does not leave enough room for proper validation, because you know that shipping a bad model costs more than delaying a release by a few days\nYou treat automation as part of the job, not extra credit, and you are always looking for repetitive tasks that should be scripted instead of done manually\nThe Team You'll Be Part Of\nYou will join the Library Characterization team at Synopsys, a group responsible for characterization, validation, QA, release management, and methodology support for advanced standard cell libraries across multiple technology nodes. Your recruiter will share more about the team structure, current projects, and how the team collaborates with design, product engineering, and customer-facing groups during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Design Verification Manager", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-25", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018232", "is_hardware": true, "platform": "oracle", "jd_text": "The RADAR product line is a rapidly expanding business within TI, investing to address the fast-growing segment in Industrial & automotive markets. This product line will enable a scalable portfolio using DSP and ARM multi-cores to support high-end applications in ADAS, body & Chassis and in Industrial space. Radar systems process digital information from sources like digital cameras, lasers, radar and other sensors to perform tasks such as lane departure warning or parking assistance. The processed information can be displayed on screens or announced via acoustical warning signals. The system has multifaceted features such as High precision ADC, extremely accurate chirp, wide range visibility and Faster scene processing abilities. As a Verification Engineer, you will play a pivotal role in ensuring the quality and reliability of our advanced RADAR products. You will be responsible for the verification of IP, Subsystem (SS), and System-on-Chip (SoC) designs, contributing to the development of robust verification methodologies, strategies and team.\n\nResponsibilities: \n\nComplete ownership of IP/subsystem/SOC DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis. This includes:\n\nBuild, Mentor and scale high preforming verification team across IP, Subsystem and SoC level\n\nLead verification activities for overall verification strategy, methodology, infrastructure and execution plans across multiple SoC programs.\n\nVerification strategy definition along with Verification plan to meet 100% spec to regression traceability along with signoff metrics. \n\nIP/SS/SOC verification covering functional and Firmware scenarios in RTL/PARTL, GLS/PAGLS modes. \n\nDV Environment ownership: TB development/enhancements including checkers and coverage monitor definitions along with DV flow updates as per the project needs \n\nActive collaboration with cross functional teams -Architecture, RTL, PD, DFT, Systems, Analog, FW and application teams -to enable the Verification goals for IP/Subsystem/SOC starting from spec definition till post silicon verification closure activities\n\nFinal SoC DV signoff based on Regressions, coverage metrics, DV to spec traceability using C and/or SV-UVM adhering to ISO26262 guidelines \n\nActive involvement in the customer reviews and certifications (ISO26262/ISO21434).\n\nQualifications\nQualifications:\n\n• 8+ years of DV experience in IP/SS/SOC/Post silicon DV with a Bachelor or Master’s degree in EE/ECE/CS or related specializations\n\n \n\nSkills: \n\nStrong people management skills along with experience in leading DV projects \n\nFirst pass success silicon success enablement by working closely with team members as well as various cross functional teams\n\nExperience in one or more of the following areas: C-based SoC design verification (DV), firmware verification exposure, scripting knowledge (Perl/Python/AI/ML based DV), DV flow ownership for functional/firmware verification, deep understanding of UVM/SystemVerilog, Specman, GLS/PAGLS/CPF/UPF based verification, post-silicon verification, etc.\n\nThorough knowledge of standard protocols, such as AXI, AHB, APB, CAN, Ethernet, I2C, SPI, UART, and high-speed interfaces like CSI and Ethernet.\n\nWork experience in a C-based environment with complex ARM/DSP multi-processor systems, including power-aware simulations, is a significant plus.\n\nStrong understanding of digital design fundamentals, computer organization and architectures, and bus protocols.\n\nExcellent Analytical, debugging skills with Verilog/VHDL designs.\n\nGood problem-solving skills.\n\nExperience with Cadence tools (Xcelium/vManager/Formal JG applications/safety simulator) or similar tools/DV flows.\n\nProficiency in AMS, CDC digital verification, formal verification, and post-silicon verification, along with familiarity with functional safety and cybersecurity processes, would be advantageous.\n\nEffective communication skills to interact seamlessly with all stakeholders.\n\nMust be highly focused and committed to achieving project goals.\n\nAbility to quickly ramp up on new systems and processes while maintaining the time management skills necessary for on-time delivery.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Design Verification Engr", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-25", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018238", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\nIn your first year with TI, you will participate in the Career Accelerator Program (CAP), which provides professional and technical training and resources to accelerate your ramp into TI and set you up for long-term career success. Within this program, we also offer function-specific technical training and on-the-job learning opportunities that will encourage you to solve problems through a variety of hands-on, meaningful experiences from your very first day on the job.\n\nAs a Design Verification Engineer in the business, you will be responsible for:\n\nDeveloping detailed verification plans while working closely with the design and system team to ensure first pass silicon success\n\nDeveloping test benches, tests and simulations at RTL and GLS\n\nRunning coverage regressions to meet the defined coverage goals\n\nTracking and communicating verification status, issues, and concerns\n\nWork with regression tools and develop scripts to submit cases for regression analysis\n\nContribute to continuous improvements for quality and efficiency on DV strategy, tools, methods and flows\n\nAs part of your job, you will also get exposure to other roles such as: Digital Design& Analog Design through formal learning, projects and on-the-job development experiences that will help you broaden your knowledge and accelerate your growth and success at TI.\n\nPut your talent to work with us as a Design Verification Engineer !\n\nQualifications\nMinimum requirements\n\nBachelors degree in Electrical Engineering, Electrical and Computer Engineering, Computer Engineering or related field\n\nCumulative 3.0/4.0 GPA or higher\n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Principal Analog Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-09-25", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506742", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Principal Analog design Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including LED drivers, SiC/MOS/IGBT/motor/GAN drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following\n\nLead and design analog IP blocks from definition to IP delivery individually as well as an IP lead\n\nEvaluate intermediate and results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to layout engg for your IP block and monitors the progress\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nCollaborate with overseas design and systems teams on technical aspects, IP development, sharing of know-how \n\nOwn technical outcomes of design, verification, implementation, and execution of power management ICs with complexities that can span from simple regulators to complex mixed-signal designs and control loops \n\nUnderstand project goals, execute to schedule with given resources, track execution schedule to plan, monitor progress, \n\n#LI-RG1\n\nResponsibilities\nLead and design analog IP blocks from definition to IP delivery individually as well as an IP lead\nEvaluate intermediate and results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\nWork with and provide guidance to layout engg for your IP block and monitors the progress\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\nCollaborate with overseas design and systems teams on technical aspects, IP development, sharing of know-how \nOwn technical outcomes of design, verification, implementation, and execution of power management ICs with complexities that can span from simple regulators to complex mixed-signal designs and control loops \nUnderstand project goals, execute to schedule with given resources, track execution schedule to plan, monitor progress.\n#LI-RG1\n\nQualifications\nSolid track record of designing multiple complex IPs with Si learnings\nUnderstand and execute IP design, simulations methods, boundary conditions, stress and reliability simulations, PVT/PMC/SOA simulations.\nExtensive knowledge of engineering processes, principles, and methodologies \nStrong CMOS circuit design fundamentals, circuit architectures.\nAbility to clearly articulate issues, challenges, and concerns to all levels of management \nGood understanding of various building blocks like charge pump, LDOs, gate drivers, comparators, linear regulators, gm-stage and relevant Analog building blocks \nUnderstanding of LED drivers, SiC/GAN devices and drivers is a strong plus\nStrong Analog IC design skills, debug of complex silicon problems using simulations and/or bench testing \nFamiliarity with advanced Bipolar, CMOS, and High Voltage BCD technology, Process, Device Physics, Semiconductor Manufacturing processes, and their impact on Analog performance \nunderstanding of power transistor Design, Layout, and Robustness \nProficiency in leading-edge design and verification tools such as Simplis or MATLAB for architectural simulations, Cadence Spectre for schematic capture, simulation, layout, and tape-out \nStrong verbal and written communication skills \nAbility to quickly ramp on new systems and processes \nDemonstrated strong interpersonal, analytical and problem-solving skills \nAbility to work in teams and collaborate effectively with people in different functions\nAbility to take the initiative and drive for results\n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Senior Principal Analog Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-09-25", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506744", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Senior Principal Analog design Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including LED drivers, SiC/MOS/IGBT/motor/GAN drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following\n\nMentor junior Analog IC design engineers  \n\nLead multiple analog IPs with IP ownership and responsibility from definition, IP execution to release to manufacturing\n\nAble to resolve complex analog problem and propose and implement the solution\n\nProvide design guidance as needed, developing schedules and monitoring progress throughout the project\n\nEvaluate intermediate and results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout\n\nCollaborate with Design Verification teams during the pre-tapeout phase of a project to ensure completion of all technical tasks before tapeout\n\nWork with systems engineers, application engineers and marketing assisting in the definition of the product to meet customer needs as well as contributing to roadmap formulation and new concept creation\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nProvide technical leadership in driving architecture design and circuit design based on high-level specifications \n\nOwn technical outcomes of design, verification, implementation, and execution of power management ICs with complexities that can span from simple regulators to complex mixed-signal designs and control loops \n\nUnderstand project goals, create a realistic schedule and resource plan, track execution schedule to plan, monitor progress, and provide full clarity to the team on the goals and objectives.\n\n#LI-RG1\n\nResponsibilities\nMentor junior Analog IC design engineers  \n\nLead multiple analog IPs with IP ownership and responsibility from definition, IP execution to release to manufacturing\n\nAble to resolve complex analog problem and propose and implement the solution\n\nProvide design guidance as needed, developing schedules and monitoring progress throughout the project\n\nEvaluate intermediate and results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout\n\nCollaborate with Design Verification teams during the pre-tapeout phase of a project to ensure completion of all technical tasks before tapeout\n\nWork with systems engineers, application engineers and marketing assisting in the definition of the product to meet customer needs as well as contributing to roadmap formulation and new concept creation\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nProvide technical leadership in driving architecture design and circuit design based on high-level specifications \n\nOwn technical outcomes of design, verification, implementation, and execution of power management ICs with complexities that can span from simple regulators to complex mixed-signal designs and control loops \n\nUnderstand project goals, create a realistic schedule and resource plan, track execution schedule to plan, monitor progress, and provide full clarity to the team on the goals and objectives \n\n#LI-RG1\n\nQualifications\nSolid track record of delivering multiple complex IPs with Si learnings\n\nExtensive knowledge of engineering processes, principles, and methodologies \n\nGoal and outcome-focused with the ability to handle multiple projects within the team \n\nAbility to provide technical mentorship\n\nExperience in simplifying complex problems into smaller problems and solving them as a team \n\nGood understanding of various drivers like SiC/GAN/LED, smartFET / Efuses and relevant Analog building blocks \n\nStrong Analog IC design skills, debug of complex silicon problems using simulations and/or bench testing \n\nFamiliarity with advanced Bipolar, CMOS, and High Voltage BCD technology, Process, Device Physics, Semiconductor Manufacturing processes, and their impact on Analog performance \n\nunderstanding of power transistor Design, Layout, and Robustness \n\nProficiency in leading-edge design and verification tools such as Simplis or MATLAB for architectural simulations, Cadence Spectre for schematic capture, simulation, layout, and tape-out \n\nStrong verbal and written communication skills \n\nAbility to quickly ramp on new systems and processes \n\nDemonstrated strong interpersonal, analytical and problem-solving skills \n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results \n\n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Associate Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-25", "url": "https://careers.arm.com/job/bengaluru/associate-engineer/33099/101118903488", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview:\n\nThe implementation team in Arm's Solution Engineering drives the standards and methodology behind producing best in class Arm cores and systems on silicon. The group works on ensuring that our IPs can meet the requirements of the Arm partner base, on brand new deep sub-micron processes, whilst driving advanced implementation methodologies using the latest EDA tools. In addition, this group is responsible for specification, design and fabrication of Arm based SoCs used for demonstrating the capabilities of Arm intellectual property, resulting in the testing and analysis of real silicon.\n\nThis is an exciting role, employing the latest design techniques to meet demanding product specifications on the newest technology nodes. The role also involves interaction and working with customers, EDA vendors and other Arm engineering groups around the world.\n\nResponsibilities:\n\nSynthesis, Physical design and implementation of Arm cores, systems and SoCs\n\nAnalyze design timing, area and power to help improve the quality of Arm IP.\n\nDevelop and deploy new methodologies to improve implementation efficiency and results.\n\nSupport and develop detailed implementation analysis and data-mining methodologies.\n\nWork with implementation and physical IP RTL design teams to drive analysis and optimization of our IP.\n\nRequired Skills and Experience :\n\nBachelors or Master’s degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields.\n\n2+ years of proven experience in ASIC system-on-chip implementation flow from RTL to GDS.\n\nExperience in Timing Constraints development, Synthesis, Timing Closure\n\nPossess a high level of dedicated, initiative and problem-solving skills.\n\nExperience of tape outs of multi-million gate designs on latest technologies\n\nAbility to develop and work with timing constraints for build and signoff\n\nThe ability to effectively work alone as well as in a team\n\n“Nice To Have” Skills and Experience :\n\nExperience with a wide range of programming, scripting & data presentation languages Eg. Tcl, Shell, Perl, Python.\n\nExperience with low power design techniques (power gating, voltage/frequency scaling).\n\nExperience with Verilog RTL design\n\nUnderstanding of DFT modes and their implications on Physical Design\n\n \n#LI-BB1\n\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Analog/Mixed-Signal Layout Engineer - SERDES", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-24T14:02:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92875/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. THE ROLE: As a member of SERDES Group, you will help develop layout designs. As a member of the team, you will work closely with the architecture, IP design, Physical Design teams to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Implementation Layout of blocks and macros Own and deliver the high-quality macros with help of team Mentor and groom the juniors in the team Work with contractor team and the planned work done as per aligned schedule Enable release flows as required PREFERRED EXPERIENCE: 8+ yrs of hands-on experience in layout design Experience with Cadence virtuoso, Caliber and other verification tools as required for layout development Preferrable experience in high speed SERDES blocks ACADEMIC CREDENTIALS: Bachelors or Masters degree in Electrical Engineering or equivalent #LI-PK2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Staff / Senior Staff Engineer, Analog Design (Power & Analog ICs)", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-24T09:09:27.979000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000151567059-staff-senior-staff-engineer-analog-design-power-analog-ics-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking a Senior Staff Analog Design Engineer with deep expertise in power management, analog, and mixed-signal IC development. This is a senior individual-contributor role requiring ownership of complex analog IP, subsystem architecture, converter design, and silicon execution from concept through production. \nThe successful candidate will lead the design of key analog and power-management functions including switching converters, LDOs, charge pumps, references, sensors, protection circuits, data converters, and signal-conditioning blocks used across Renesas power and analog products. The role requires strong technical judgment, architecture ownership, cross-functional collaboration, and the ability to drive first-silicon success. \nYou will be expected to operate independently, resolve ambiguous technical challenges, establish design methodology, mentor engineers, and influence product architecture and execution through deep technical expertise. \nResponsibilities:  \nAnalog Architecture & Circuit Design \nDefine and own the architecture of complex analog and power-management IP used in PMICs, converters, battery-management products, and mixed-signal devices. \nDesign and own blocks such as positive and negative charge pumps, buck converters, source-sink LDOs, ultra-low-power oscillators, temperature sensors, current-sense circuits, SAR ADCs, voltage and current references, op-amps, comparators, analog buffers, level shifters, and protection circuits. \nTranslate product and top-level chip requirements into detailed block specifications, architecture decisions, circuit implementations, and verification plans. \nPerform block-level error budgeting and system-level trade-off analysis across performance, area, power, cost, robustness, and manufacturability. \nConverter & Control Loop Design \nIndependently architect and design complete switching converters including buck, boost, and buck-boost converters, as well as LDOs and point-of-load devices. \nDemonstrate deep understanding of analog feedback loops, control-loop stability, compensation implementation, and trade-offs across compensation strategies. \nEvaluate control architectures such as constant-frequency, constant-on-time, constant-off-time, voltage-mode, and current-mode control, and select the appropriate approach for product requirements. \nEnsure robust converter performance across process, voltage, temperature, load, line, startup, shutdown, and fault conditions. \nVerification, Silicon & Production Support \nDrive analog verification and simulation strategy across schematic, extracted, pre-layout, and post-layout environments. \nOptimize simulation setups based on speed, convergence, accuracy, and parasitic conditions, and resolve simulator, model, and tool-related challenges. \nOwn or support silicon validation, characterization, debug, qualification, production readiness, and root-cause analysis for silicon issues. \nCollaborate with product engineering, test engineering, applications, reliability, and manufacturing teams across the complete product lifecycle. \nPhysical Design, Reliability & Sign-off \nCollaborate closely with layout engineers from floor planning through chip-top completion, extraction, verification, and tape-out. \nGuide layout trade-offs related to matching, noise, parasitics, isolation, current density, electromigration, IR drop, thermal behavior, and high-current operation. \nDemonstrate strong understanding of ESD, latch-up, I/O-ring protection, and other IC-level reliability requirements. \nReview physical implementation and extracted performance to ensure the design meets electrical, yield, reliability, and manufacturability targets. \nTechnical Leadership & Methodology \nDrive analog design methodology, checklists, design reviews, reusable IP practices, and quality standards from concept through silicon success. \nLead technical reviews and provide clear architecture, design, verification, risk, and sign-off assessments to project leadership. \nMentor junior and mid-level engineers through architecture reviews, circuit design, simulation strategy, layout collaboration, and silicon debug. \nInfluence product architecture and technical roadmap decisions through demonstrated technical depth, while operating as a senior individual contributor rather than a formal people manager. \n\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related discipline. \n\n12+ years of relevant experience in analog, mixed-signal, or power-management IC design. \n\nDemonstrated ownership of complex analog IP, converter subsystems, or complete smaller ICs from architecture through silicon and production. \n\nDeep hands-on expertise in PMICs, switching regulators, LDOs, charge pumps, and complex analog IP development. \n\nStrong understanding of analog feedback loops, control-loop compensation, stability analysis, and converter-architecture trade-offs. \n\nExperience with references, op-amps, comparators, buffers, level shifters, oscillators, sensors, current sensing, ADCs, and protection circuitry. \n\nExperience with industry-standard schematic design, simulation, extraction, and post-layout verification flows and tools. \n\nStrong understanding of analog layout effects, parasitics, matching, noise, reliability, ESD, latch-up, and IC-level robustness. \n\nExperience taking products through design, verification, tape-out, silicon validation, debug, qualification support, and production release. \n\nProven ability to establish design methodology, lead technical reviews, mentor engineers, and influence cross-functional decisions without requiring formal people-management authority. \n\nStrong communication and collaboration skills across global, multisite, and multicultural teams. \n\nSelf-driven, results-oriented, and able to deliver high-quality designs under tight schedules with limited supervision. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior STA Design Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-24T07:26:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92734/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. SENIOR STA SILICON DESIGN ENGINEER KEY RESPONSIBILITIES: Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Ensuring constraints quality (SDC) using industry tools like Fishtail , GCA Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts) Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip. Ensuring Subsystem/full chip level Interface timing closure along DRV closure Generating timing ECO using tools DMSA/Tweaker. PREFERRED EXPERIENCE: 4-5 years of experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. Experience with analyzing the timing reports and identifying both the design and constraints related issues. Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc. Experience in timing closure of high frequency blocks & subsystems (> Ghz range ) Good Understanding of DFT modes requirements for timing signoff Good understanding of SDC constraints, OCV,AOCV,POCV analysis. Strong TCL/scripting knowledge is mandatory.   ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Principal Engineer/Senior Staff Engineer- CPU Software & Hardware Co-Design Engineer (ML Systems)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-24T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720477787", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Software Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Software Engineer, you will design, develop, create, modify, and validate embedded and cloud edge software, applications, and/or specialized utility programs that launch cutting-edge, world class products that meet and exceed customer needs. Qualcomm Software Engineers collaborate with systems, hardware, architecture, test engineers, and other teams to design system-level software solutions and obtain information on performance requirements and interfaces.\n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 8+ years of Software Engineering or related work experience.\n                                                                    OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 7+ years of Software Engineering or related work experience.\n                                                                    OR\nPhD in Engineering, Information Systems, Computer Science, or related field and 6+ years of Software Engineering or related work experience.\n\n•    4+ years of work experience with Programming Language such as C, C++, Java, Python, etc.\n\nDetailed JD:\n==========\n\nJob Description: CPU Software & Hardware Co-Design Engineer (ML Systems)\nLocation: Bangalore (or relevant)\nLevels: Engineer / Senior Engineer / Staff / Principal Engineer\n\nRole Overview\nWe are building a high-impact team at the intersection of CPU architecture, machine learning workloads, and system-level performance optimization. This role focuses on CPU software–hardware co-design for next-generation QMX architectures, including workload characterization, simulation, kernel optimization, and driving architectural insights for future CPU designs. The ideal candidate will work across the full stack—from ML models to low-level kernels to architectural feedback—enabling efficient execution of ML workloads on CPU platforms.\n\nKey Responsibilities\n1. ML Workload Identification & Characterization\nIdentify and prioritize critical ML use cases and models for CPU-centric execution (LLMs, vision, speech, recommender systems, etc.)\nAnalyze workload characteristics including:Compute intensity\nMemory bandwidth and cache behavior\nParallelism and dataflow patterns\n\n2. Simulation & Trace Generation\nGenerate detailed execution traces for ML workloads using QEMU or equivalent simulators\nDevelop tooling to:Capture instruction-level execution behavior\nExtract performance counters and bottlenecks\n\nEnable accurate modeling of workload behavior for architectural exploration\n\n3. Bottleneck Analysis & Performance Optimization\nIdentify system bottlenecks across:CPU pipelines\nMemory hierarchy\nInstruction utilization\n\nOptimize critical hotspots through:Kernel-level tuning\nAlgorithmic improvements\nData layout and memory optimizations\n\nDrive measurable improvements in workload performance\n\n4. Software–Hardware Co-Design\nCollaborate with CPU architecture and design teams to:Provide data-driven insights from real workloads\nIdentify inefficiencies and propose architectural enhancements\n\nInfluence next-generation CPU features in:Compute units\nVector/SIMD extensions (e.g., QMX)\nMemory subsystems\n\n5. ML Kernel & Library Development (QMX Focus)\nDesign and implement highly optimized ML kernels and libraries for QMX architecture\nDevelop kernels for:GEMM, convolution, attention, activation functions, etc.\n\nEnable integration with:Open-source ML frameworks (e.g., PyTorch, ONNX, XNNPACK, MLAS)\n\nApply advanced optimizations:SIMD/vectorization\nCache-aware execution\nParallel execution strategies\n\n6. Benchmarking & Performance Engineering\nOptimize CPU-centric ML benchmarks such as:Geekbench AI\nInternal benchmarking suites\n\nEstablish performance baselines and track improvements across hardware generations\nPerform competitive analysis and performance positioning\n\nRequired Qualifications\nStrong background in:Computer Architecture / Systems Programming\nMachine Learning fundamentals\n\nProficiency in:C/C++ (mandatory)\n\nExperience with:Performance profiling, benchmarking, and optimization\n\nPreferred Qualifications\nExperience with:QEMU or equivalent simulators\nML kernel development (GEMM, convolution, attention)\n\nKnowledge of:CPU architecture (pipelines, caching, SIMD/vector extensions such as NEON, SVE, QMX)\n\nFamiliarity with:ML frameworks and inference stacks\n\nExperience with low-level optimization:Intrinsics, assembly, memory and cache tuning\n\nWhy Join This Team\nWork on next-generation CPU architectures (QMX)\nDirectly influence hardware design through real workload insights\nSolve end-to-end ML performance challenges (model → kernel → silicon)\nCollaborate with top architecture, systems, and AI teams\nHigh-impact role with visibility across product and research roadmaps\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "PostSi Debug Validation Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-24T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721035541", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nWe are Hiring Post-Silicon Validation Engineers! We are seeking highly motivated engineers to join the Post-Silicon Customer Engineering & Debug team for Oryon Custom CPU-based products across flagship mobile, compute, automotive, and Data center platforms. This role sits at the intersection of silicon, software, and customer engagement, driving root-cause analysis and resolution of complex customer-reported issues.\n\nAre you passionate about CPU architecture and solving some of the toughest silicon challenges? We’re growing the Oryon CPU Customer Engineering Post-Silicon team and are looking for engineer who thrive on deep technical debugging and validation.\n\nWhat you’ll work on:\n* Own end-to-end debug and resolution of customer issues involving CPU crashes, hangs, watchdog resets, performance issues, power abnormalities, boot failures, and silicon marginalities\n* Root-causing complex functional and microarchitectural issues using silicon traces, scan dumps, ETM/PTM, and debug infrastructure\n* Cross-functional collaboration with CPU Architecture, RTL, Design Verification, Physical Design, DFT, Firmware, and SoC teams to drive issues to closure\n* Troubleshoot complex hardware, firmware, and electrical issues (like signal integrity, boot failures, or interface bugs) * Enabling world-class quality for next-generation flagship mobile processors\n\nWe’re looking for engineers with 7-10 years of relevant experience in:\n✔ CPU microarchitecture and ARM architecture fundamentals\n✔ Post-silicon validation, debug, or silicon bring-up\n✔ Understanding of SoC architecture, interconnects, memory subsystems, and multi-core CPU systems\n✔ Pipeline, cache, memory subsystem, coherency, and exception/debug flows\n✔ Assembly, C/C++, Python, and automation\n✔ Strong analytical thinking and systematic root-cause debugging\n\nLocation - Bengaluru, India\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Engineer, ASIC IP STA", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-24T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/44634677", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nASIC IP STA Engineer (6-10 Years) | DDR PHY / ONFI PHY / IO Expander\nLocation: Bengaluru, India\nExperience: 6-10 Years\nEnducational Qualification : BE/B-Tech/M-Tech (EEE, ECE, Micron Electronics, VLSI)\n\nKey Requirements\nMember of the AMS IP Physical Design team, responsible for post-layout STA signoff and timing closure of high-speed interface IPs, with close collaboration across IP Design, SoC Synthesis, and SoC Physical Design teams throughout IP development and SoC integration.\n6-10 years of experience in Static Timing Analysis (STA) with a proven track record of 4+ successful tapeouts.\nStrong hands-on expertise with Cadence Tempus (preferred).\nIn-depth experience in MMMC timing analysis and closure across functional, scan, MBIST, and other DFT modes.\nExperience working on high-speed Memory Interface IPs such as DDR PHY, ONFI PHY, IO Expander (IOE), or similar high-performance interface designs.\nStrong understanding of timing constraints development, validation, and debug, including clocks, generated clocks, timing exceptions, and mode-specific constraints.\nExperience in Liberty (.lib) and ETM timing model generation, validation, correlation, and quality assessment.\nAbility to deliver early timing models (.lib/ETM) and ensure high-quality timing collateral to enable smooth and predictable SoC integration.\nHands-on experience with SDF generation, validation, and Gate-Level Simulation (GLS) support for verification teams.\nSolid understanding of setup/hold analysis, recovery/removal checks, pulse-width verification, OCV/AOCV/POCV methodologies, and SI-aware timing signoff.\nExperience with the Cadence digital implementation and signoff flow, including Genus, Innovus, and Tempus.\nProficiency in TCL and/or Python for timing analysis, methodology development, and flow automation.\nExposure to AI/ML-enabled EDA methodologies, leveraging AI-assisted workflows for timing analysis, timing closure, constraint validation, root-cause analysis, and productivity improvement.\nStrong analytical, debugging, communication, and stakeholder management skills, with the ability to drive timing closure across cross-functional teams.\n\nPreferred Qualifications\nExperience with advanced-node, high-frequency designs including LPDDR/DDR, ONFI, IO Expander, or similar memory and interface IPs.\nExposure to AMS/Digital-on-Top IP development flows and timing signoff challenges associated with mixed-signal integrations.\nFamiliarity with AI-powered EDA solutions, Agentic AI workflows for design automation and productivity enhancement.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Staff Engineer, ASIC STA", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-24T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/44624805", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nWhat Makes This Opportunity Unique\n\nAt Micron, we're not just offering a job; we're presenting a chance to be part of a team that develops the future of memory and storage solutions. As a Staff Engineer, ASIC STA in our Bengaluru office, you will have the opportunity to work with powerful technology and contribute to highly innovative projects. Your work will help us deliver flawless results and uphold our world-class standards!\n\nJob Responsibilities\n\nProficient at Synthesis, Static Timing Analysis (STA), and Logic Equivalence Checking (LEC)\nAbility to understand and integrate new mixed signal complex IPs\nExpertise in developing constraints and timing models\nManage synthesis to timing closure, ensuring all checks for silicon success\nExperience with hierarchical designs involving high-frequency clocks\nProficient with scripting, automation, and EDA tools\nProficiency with AI and AI-enabled workflows\nSolid understanding of low power builds involving multiple power domains\nIdentify and meet requirements for critical paths of multi-GHz builds\nCollaborate effectively in multi-functional and globally dispersed teams\n\nRequirements\n\nM.S./M.Tech, BS/BE in Electronics or related field\nMinimum of 6+ years of relevant experience\nProven ability to successfully implement complex builds\nAmbitious and determined to compete at a global level\n\nJoin us at Micron and play a pivotal role in our projects that transform information into intelligence. Your expertise will directly contribute to our mission of encouraging the world to learn, communicate, and advance faster than ever. We are committed to encouraging an inclusive and collaborative environment where your skills can truly shine. This is your chance to be part of a team that is setting the standards in memory and storage solutions!\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Staff Engineer - Post-Si Validation", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-24T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721139131", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n\nResponsibilities\nYou will be part of Qualcomm Snapdragon SoC - Silicon Validation team, particularly in the bring up of SVE convex infra, IST framework for the enablement of VI content in production.\n\nUnderstand the IP architecture,  work with IP validation teams and Systems validation Lead/system content engineer to understand the validation requirements, develop/port/enhance the validation software content and bring up.\n\nOwn SoC frequent regression and execute end-to-end regression suite by considering SoC design corner cases wrt power and performance.\n\nExecuting SOC validation releases on bench in lab and supporting the SLT teams in Debug and enabling different features in the framework.\n\nUse silicon debug hooks to measure power/performance/coverage and other KPI metrics\n\nWork with a relevant team member for regular reporting of issues and failure of debugs.\n\n    \nMandatory Skills:\n\n- Basics of processor architecture, Multicore/Multiprocessor with SMP/MTE/heterogenous cores.\n- C language expertise for low level programming, Assembly language for any processor, C-assembly interworking\n- Operating systems/RTOS/Linux kernel internals, scheduling policies, locking mechanism, MMU/paging etc\n- Exposure to working on emulation/pre-si environment is added advantage\n- Using JTAG based debuggers, compilers/linkers\n- Should have good exposure to software development life cycle\n \nDesired Skills:\n\n- Exposure to SoC architecture paradigms – interconnects, power management,\n- Software development for silicon enablement, silicon validation\n- Bring-up of hardware-software solution on FPGA/emulation platforms and on fresh SOC designs\n- Software for power/performance KPIs\n- Good knowledge of ARM Cortex-A7/A8) / x86 / PowerPC CPU and memory system architecture\n- Weakly ordered memory model/pipelining of memory systems/memory barriers\n- Software development towards higher performance of multi-threaded applications using lower power\n- Top level of ASIC design methodology is an added skill\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RTL Design (Power) - Audio", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-24T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720202709", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    3+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n\nPrincipal Duties and Responsibilities:\n•    Applies Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Assists in the assessment of complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Engineer - DFT", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-24T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720669037", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    5+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Staff Engineer", "company": "Samsung", "location": "SSIR, Angkor West, Bangalore, India", "date_posted": "2026-09-24", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/SSIR-Angkor-West-Bangalore-India/Senior-Staff-Engineer_R120924", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.\nRole and Responsibilities\n\nPosition: Design Verification Engineer\n \nRoles and Responsibilities\n \nIndependent Verification Ownership of IP DV. Collaborating with various cross functional teams at multiple geo locations as part of execution. Expected to work hands on to close all aspects of verification activities including Testplan creation, building testbenches based on standard DV methodology, developing DV Infrastructure (Coverage/Regression/Simulation Scripts)\nDomain: AXI, PCIe, UCIe protocol experience is highly preferred\n \nSkills:\n \nMust have experience in developing test benches for IP/Subsystems/SoC.\nIn depth knowledge and hands on experience in the execution of verification of SoC/Sub System/IP DV.\nPrevious experience of independently driving IP DV projects from ability to lead a team by providing technical guidance, as well as be part of execution by debugging and SoC architecture understanding capabilities.\nStrong hands on experience with common verification tools and methodology including UVM/ System Verilog/CDV/MDV, DV signoffs.\nMust have a strong domain expertise in one or more following areas - AXI/PCIe/UCIe.\nExperience in Hybrid testbenches (SV, SystemC, Python) and SystemC based reference model test vectors/stimulus based verification is desirable.\n \nExperience – 7 to 10 Years of experience\n \nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nSkills and Qualifications\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n \n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "ASIC Digital Design, Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-24", "url": "https://careers.synopsys.com/job/bengaluru/asic-digital-design-staff-engineer/44408/101087862672", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nYou have built verification environments that catch bugs before they become customer issues. Whether you have been doing this for three years or closer to ten, you have learned that verification is not about running tests; it is about thinking through what could go wrong and building the infrastructure to prove it won't. You understand that a well-written testbench is half the battle, and the remaining is knowing which corner cases matter, and which ones are just noise.\nYou are comfortable working in System Verilog and UVM, writing test cases that exercise real scenarios, not just the ones in the specification. You have debugged enough simulations to recognize patterns in waveforms, and you know when to dig deeper versus when to loop in the design team. Protocols like MIPI UFS/UniPro, DDR, PCIe, Ethernet or USB are not just acronyms to you; you have worked with at least one of them closely enough to understand how transactions flow and where things typically break.\nWorking on a verification team means asking questions when the test plan does not make sense, writing assertions that catch issues, and tracking coverage in a way that tells you what you have validated and what you have not. At Synopsys, you will work on IP cores that go into AI systems, automotive platforms, and data centers. The verification work you do will determine whether that IP works when it ships.\n\nWhat You'll Be Doing\nBuild and maintain UVM-based testbench for RTL IP cores, including agents, drivers, monitors, scoreboards, and coverage collectors\nWrite System Verilog test cases and constrained random stimulus to verify functional correctness across different operating modes and protocol scenarios\nDevelop and execute verification plans based on design specifications, identifying test scenarios, corner cases, and coverage goals\nDebug RTL and testbench issues by analyzing simulation logs, waveforms, and coverage reports to isolate root causes and verify fixes\nImplement assertion-based checks and functional coverage models to track verification progress and ensure thorough validation\nCollaborate with design engineers to understand IP functionality, clarify requirements, and provide feedback on design-for-verification considerations\nRun regressions, analyze results, and work toward coverage closure, documenting verification status and outstanding issues\n\nThe Impact You Will Have\nEnsure Synopsys IP cores are thoroughly validated before they reach customers building AI accelerators, automotive systems, and cloud infrastructure\nReduce post-silicon bugs and customer escalations by catching design issues early through systematic verification and coverage analysis\nContribute to faster IP release cycles by building reusable verification components and efficient test strategies\nHelp maintain high-quality standards across Synopsys IP products, directly impacting customer success and product reliability\nSupport the development of verification best practices and methodologies within the Bangalore team\nEnable design teams to iterate faster by providing clear, actionable feedback on functional correctness and edge case behavior\nBuild verification infrastructure that can scale across multiple IP variants and protocol configurations\n\nWhat You'll Need\n4-8 years of hands-on experience in ASIC or RTL verification for IP cores or digital designs\nUnderstanding of verification planning, test case development, and coverage-driven verification concepts\nWorking knowledge of UVM or similar verification methodologies, with experience building testbench components and writing test cases\nSolid System Verilog skills, including understanding of constrained random verification, coverage, and assertions\nFamiliarity with at least one industry-standard protocol such as MIPI UFS/UniPro, DDR, PCIe, Ethernet, USB or similar\nExperience debugging RTL simulations using waveform viewers and analyzing coverage reports to guide verification progress\nExperience with Perforce or similar revision control environment\nBasic scripting ability in Python, Perl, TCL, or shell scripting to support automation and regression management\nAbility to use AI tools like Cursor and GitHub Copilot for analysis, development, debugs and maximizing productivity.\nHave good communication skills, will be a team player, and will have good problem-solving skills.\n\nWho You Are\nYou can look at a design spec and start listing the test scenarios that need to be covered without waiting for someone to hand you a complete test plan\nYou are methodical about debugging, when a test fails, you do not guess, you trace through the waveform and log until you understand exactly what happened\nYou ask questions when requirements are unclear or when a design decision seems like it will be hard to verify, and you do it early enough to matter\nYou are comfortable working with design engineers who may be in different locations, coordinating on bug fixes, clarifications, and verification scope\nYou track your own coverage and verification progress, knowing what has been tested, what has not, and what the gaps mean for overall quality\nYou are motivated by the moment when your testbench catches a real bug, the kind that would have caused problems downstream if it had slipped through\n\nThe Team You'll Be Part Of\nYou will join the IPG and SSG Group at the Bangalore Design Center, working alongside verification and design engineers who develop IP cores for a range of applications including AI, automotive, and cloud infrastructure. The team collaborates across Synopsys' global sites, and you will have the opportunity to work on IP that goes into high-performance systems used by customers worldwide.\n\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Sr Staff High-Speed I/O Design Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-24", "url": "https://careers.synopsys.com/job/bengaluru/sr-staff-high-speed-i-o-design-engineer/44408/101087862640", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nYou have spent years designing analog circuits that move data at speeds where physics stops being forgiving and starts being the problem. You know that a high-speed link is not just about transistors, it is about package inductance, substrate coupling, jitter budgets, and the thirty other things that conspire to close an eye diagram at 32 Gbps. You have debugged enough silicon to know that the difference between a working PHY and a failing one often comes down to a decision you made six months earlier during floor planning or bias distribution.\nYou are comfortable moving between Spectre simulations, behavioral models in Python or MATLAB, and actual scope measurements in the lab. When a digital engineer asks why the receiver is not locking, you can explain it in terms they understand without losing the analog nuance. You do not need a perfect spec to get started. You work with what you have, build models to explore the tradeoffs, and align with signal integrity and packaging teams early because you have learned that waiting until tapeout is too late.\nAt Synopsys, you will design the analog PHY circuits that power UCIe die-to-die interfaces, the kind of IP that gets integrated into chiplets across the industry. The work is hard, the constraints are real, and what you build will ship.\n\nWhat You'll Be Doing\nDefine analog PHY architectures for UCIe and high-speed die-to-die interfaces, translating system requirements into circuit-level specifications for transmitters, receivers, equalization, clocking, and calibration blocks\nDesign transistor-level analog and mixed-signal circuits including TX drivers, RX front-ends, continuous-time linear equalizers, decision feedback equalizers, delay-locked loops, bias generators, and termination circuits using Cadence Virtuoso, Spectre, Synopsys Custom Compiler, or HSPICE\nBuild behavioral models for link performance analysis, jitter budgeting, BER estimation, and system-level trade-off exploration in collaboration with digital and signal integrity teams\nVerify designs across PVT corners, Monte Carlo mismatch, aging, reliability, and post-layout parasitic extraction, ensuring margin and performance targets are met before tapeout\nAnalyze package, interposer, substrate, and channel effects including insertion loss, return loss, crosstalk, common-mode voltage, and eye closure, working closely with signal integrity and packaging engineers\nSupport floor planning, layout reviews, parasitic back-annotation, and design sign-off, ensuring circuits meet area, power, and performance targets\nLead silicon bring-up, lab characterization, compliance testing, and simulation-to-silicon correlation, debugging issues and driving root cause analysis with cross-functional teams\n\nThe Impact You Will Have\nEnable Synopsys to deliver UCIe PHY IP that powers the next generation of chiplet-based systems across AI, HPC, and data center applications\nReduce time-to-market for customers by delivering analog circuits that meet first-pass silicon targets for BER, jitter, power, and eye performance\nImprove design quality and predictability by building accurate behavioral models and verification methodologies that catch issues before tapeout\nStrengthen collaboration between analog, digital, layout, signal integrity, and validation teams through clear communication and early alignment on critical design decisions\nAccelerate silicon debug cycles by correlating lab measurements to simulation, identifying root causes faster, and feeding learnings back into the design process\nMentor junior engineers on analog design techniques, high-speed I/O fundamentals, and best practices for verification and silicon bring-up\nContribute to technical reviews, design documentation, and IP release processes that ensure long-term maintainability and reuse across product lines\n\nWhat You'll Need\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or equivalent practical experience\n8 to 15 years of hands-on experience in analog or mixed-signal IC design, with a focus on high-speed interfaces\nProven track record designing circuits for UCIe, die-to-die interconnects, SerDes, PCIe, Ethernet, CXL, USB, or similar high-speed I/O standards\nDeep expertise in analog circuit design including transmitters, receivers, equalization, DLLs, bias circuits, and high-speed drivers, with strong understanding of jitter, phase noise, linearity, signal integrity, and power trade-offs\nStrong proficiency with transistor-level design and simulation using Cadence Virtuoso/Spectre, Synopsys Custom Compiler/HSPICE, or equivalent tools\nExperience with schematic design, behavioral modeling, layout interaction, parasitic extraction, post-layout verification, and design sign-off in advanced semiconductor process nodes\nHands-on experience with silicon bring-up, lab measurements using high-speed oscilloscopes and BERTs, debugging, and simulation-to-silicon correlation; familiarity with compliance testing and industry standards is a plus\n\nWho You Are\nYou can look at an eye diagram and know whether the problem is ISI, jitter, noise, or something in the package, and you know which knobs to turn to fix it\nYou do not wait for the layout to come back to think about parasitics; you work with layout engineers during floor planning to minimize coupling, manage current return paths, and keep sensitive nodes clean\nYou can explain a complex analog trade-off, like why increasing bias current does not always improve bandwidth, to a digital engineer or a project lead in two sentences without losing the nuance\nYou are organized enough to manage multiple circuit blocks in parallel, track verification coverage across corners, and keep stakeholders aligned on schedule and risk\nYou push back when a spec is unrealistic or a timeline does not account for the iteration cycles that analog design actually requires\nYou have spent enough time in the lab to know that the scope does not lie, and you use that experience to build better models and make better decisions during design\n\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\n\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Test Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-24", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010838", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n This is a unique opportunity to be part of a team that drives testing of highly integrated multi-rail power management devices going into markets with significant growth potential. The ideal candidate would have a background that includes probe and final test development of complex mixed signal circuits.\n\nResponsibilities include:\n\nWork with design team to understand design specifications\n\nGenerate test plan, create test and char program, design ATE hardware interface boards\n\nDebug characterizing silicon on ATE, correlate results with bench data\n\nAnalyze silicon results, supporting failure analysis tasks\n\nPerform statistical analysis of yield fallout, debug and fix yield issues; optimize test time\n\nWork with production team to release products to volume production\n\nTest strategy definition and implementation for new DCDC converter products\n\nATE (Automatic Test Equipment) test hardware and software\n\nSilicon qualification& characterization including qual hardware development\n\nComprehensive device debugging, design validation and failure analysis\n\nDrive for robust and cost effective test solutions while being accountable for product quality\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in Electrical Engineering\n\nXX years of relevant experience\n\nATE experience on Teradyne Eagle or equivalent analog ATE (iFlex, LTX, VLCT), although Eagle experience is preferred and is a differentiator\n\nCharacterization test program and hardware development experience, Production test program and hardware development experience\n\nStrong technical knowledge of electronic devices and circuits, and Analog test techniques\n\nData analysis skills using Spotfire, dataPower or equivalent tool based on STDF\n\nExperienced with various lab equipment such as scopes, power supplies, sourcemeters, loads etc.\n\nExperience with product engineering activities such as yield improvement and test time reduction\n\nStrong understanding of the IC product development process, from concept to volume production\n\nPreferred qualifications:\n\nMixed signal test techniques and experience with developing mixed-signal tests on TI roadmap testers\n\nExperienced with test program and hardware offload to TI offshore manufacturing sites\n\nProficiency in programming/scripting in C++, Python, C#\n\nLabview, Teststand experience\n\nRevision control tools experience : Subversion, Git\n\nDemonstrated strong analytical and problem solving skills\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nStrong time management skills that enable on-time project delivery\n\nDemonstrated ability to build strong, influential relationships\n\nAbility to work effectively in a fast-paced and rapidly changing environment\n\nAbility to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Digital Design Lead Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-24", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25011114", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n In this position, you will be working on high-speed mixed-signal communication circuits using state-of-the art process technology, as well as be involved in the design of high performance digital circuits interfacing to leading edge analog circuitry as part of an overall system.\n\n Your responsibilities will include RTL coding, simulation, synthesis, timing closure, verification, evaluation, debugging of high-speed communication chips both at the circuit level and behavioral level.\n\n As a design engineer, you will prepare test methods and specifications, assist in preparation of application information, data sheets and demo boards. You will develop solutions to complex problems through assessment of various techniques and approaches. You will plan and organize work to ensure timely completion of many independent tasks with general instructions on routine tasks and with detailed instructions on new assignments.\n\n This position involves routine communication with a highly talented team of analog and digital design engineers to solve problems and present information as well as active participation in work groups, providing ideas and collaborative teamwork.\n\nQualifications\nMinimum requirements:\n\n5+ years of relevant experience\n\nA thorough understanding of digital logic design\n\nFamiliarity with the Verilog language and simulators\n\nA good understanding of analog functionality and exposure to analog IC design methods\n\nAbility to solve problems using a systematic approach\n\nPreferred qualifications:\n\nExperience with System Verilog\n\nDemonstrated strong analytical and problem solving skills\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nStrong time management skills that enable on-time project delivery\n\nDemonstrated ability to build strong, influential relationships\n\nAbility to work effectively in a fast-paced and rapidly changing environment\n\nAbility to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Digital Design Lead Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-24", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25011160", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n In this position, you will be working on high-speed mixed-signal communication circuits using state-of-the art process technology, as well as be involved in the design of high performance digital circuits interfacing to leading edge analog circuitry as part of an overall system.\n\n Your responsibilities will include RTL coding, simulation, synthesis, timing closure, verification, evaluation, debugging of high-speed communication chips both at the circuit level and behavioral level.\n\n As a design engineer, you will prepare test methods and specifications, assist in preparation of application information, data sheets and demo boards. You will develop solutions to complex problems through assessment of various techniques and approaches. You will plan and organize work to ensure timely completion of many independent tasks with general instructions on routine tasks and with detailed instructions on new assignments.\n\n This position involves routine communication with a highly talented team of analog and digital design engineers to solve problems and present information as well as active participation in work groups, providing ideas and collaborative teamwork.\n\nQualifications\nMinimum requirements:\n\n5+ years of relevant experience\n\nA thorough understanding of digital logic design\n\nFamiliarity with the Verilog language and simulators\n\nA good understanding of analog functionality and exposure to analog IC design methods\n\nAbility to solve problems using a systematic approach\n\nPreferred qualifications:\n\nExperience with System Verilog\n\nDemonstrated strong analytical and problem solving skills\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nStrong time management skills that enable on-time project delivery\n\nDemonstrated ability to build strong, influential relationships\n\nAbility to work effectively in a fast-paced and rapidly changing environment\n\nAbility to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Design Verification Lead", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-24", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25011177", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n  \n\nAbout the Team:\n\nThe High-speed Data development team is focused on building state-of-the-art signal conditioning transceivers for Automotive, Industrial, Enterprise and Personal Electronics markets ranging from Ethernet PHY(s), FPD-Link Serdes & USB re-timers. The data rates range from 100Mbps to 40Gbps posing design challenges in high-speed circuit design and digital signal processing to enable data transfer with high fidelity in challenging industrial and automotive environments. These devices need to be competitive in power & area and are being designed in the 65nm and 28nm process nodes.\n\n \n\nThe FPD product group charter is to develop High-speed SerDes transceivers for Automotive targeting ADAS (Advanced driver-assistance systems) and In-Vehicle-Infotainment applications. These require high-reliability communication links that support auto-driving, and high-resolution graphic applications. The high-speed SerDes designs require significant signal conditioning in Analog with Digital assist to calibrate / adapt the system in challenging electrical environments in the vehicle. The signal chain includes high bandwidth blocks (multi-Ghz) and signal processing data path designs that support multi-Gsps throughput involving clock recovery, channel adaptation, echo cancellation and forward error correction (FEC) to enable highly reliable links. Designed in 28nm CMOS process, the target for these designs is low power and low cost with best-in-industry performance.\n\nQualifications\nMinimum Requirements\n\nB.E/B.Tech or higher\n\nDigital design and modeling knowledge.\n\nStrong Debug skills\n\n5 years of experience\n\nPreferred qualification:\n\nDesign knowledge\n\n Soft Skills:\n\nPassion, Self-drive, Hard work, Willingness to learn\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Analog Design Engg - II", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-09-24", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506716", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Analog design Engineer, level II, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including LED drivers, SiC/MOS/IGBT/motor/GAN drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following\n\nDesign and develop an analog IP block from definition to IP delivery\n\nDesign and simulation at the block/IP level during execution phase, present the block results to review team in timely manner.\n\nWork with and provide guidance to layout engg and monitors the progress of IP block layout\n\nWork with validation, product engineering and test engineering teams to enable them to measure Si performance\n\nOwn technical outcomes of design, verification, implementation, and execution of power management IPs with complexities that can span from simple regulators to complex mixed-signal designs and control loops \n\nAble to plan and execute the work in timely manner aligning with full chip schedule. \n\n#L1-LK1\n\nQualifications\nBS in Electrical Engineering or related + 4 years of experience, or MS + 2 years of experience\n\nQualification\n\nSolid track record of delivering block/IP level design \n\nUnderstand and execute IP design, simulations methods, boundary conditions, stress and reliability simulations, PVT/PMC/SOA simulations.\n\nGood communication skills to make detailed technical presentations  \n\nGood understanding of various building blocks like LDOs, gate drivers, comparators, linear regulators, gm-stages, charge pumps etc \n\nExperience in SiC/GAN/LED/Motor, Efuse and smart Switches etc is plus\n\nStrong Analog IC design skills, debug of complex silicon problems using simulations and/or bench testing \n\nUnderstanding of power transistor Design, Layout, and Robustness \n\nExperience in system tools such as Simplis or MATLAB for architectural simulations, Cadence Spectre for schematic capture, simulation \n\nStrong verbal and written communication skills \n\nAbility to quickly ramp on new systems and processes \n\nDemonstrated strong interpersonal, analytical and problem-solving skills \n\nAbility to work in teams \n\n#L1-LK1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Analog Layout Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-09-24", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506717", "is_hardware": true, "platform": "oracle", "jd_text": "Onsemi is seeking a Senior Analog Layout Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and e-fuses for consumer, industrial and automotive applications. In this role, you will focus on the following\n\n  Produce high quality layout for complex AMS IP blocks (voltage regulators, bandgap, current sense-amp, amplifier, high voltage switches, drivers etc)\n\nWork on layouts of block/module level for integrated circuits from schematics. Verify using design rules provided by technology and design engineering.\n\nWork on layout floor planning of schematic block/module level, power routing, latch-up, ESD layout and area optimization using best layout techniques considering mismatch and process variations.\n\nAble to perform DRC, LVS, LVL, LEF generation, ERC, Antenna, Density and EM checks.\n\nWorking with team members/design engineers for innovative, optimal solutions\n\nUsing production quality workflow and documentation procedures\n\n#LI-LK1\n\nQualifications\nMinimum Requirements\nBS in Electrical Engineering or related 2  years of experience, \nQualification\nExperience in delivering high quality analog layout IPs\nGood understanding of layout fundamentals and best practices\nProficiency in interpretation of CALIBRE DRC, ERC, LVS, reports\nProgramming knowledge in SKILL, Perl, and/or Python is a bonus\nExperience with CADENCE or MENTOR GRAPHICS layout tools\nSolid understanding of semiconductor manufacturing process and DFM techniques\nProficient at debugging/fixing LVS/DRC errors\nMust be familiar with Cadence Design Environment (CDE) and Unix OS\nMust have strong communication skills and be a team player\n#LI-LK1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Analog Staff Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-09-24", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506719", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Staff Analog design Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including LED drivers, SiC/MOS/IGBT/motor/GAN drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following\n\nDesign and develop an analog IP block from definition to IP delivery\n\nDesign and simulation at the block/IP level during execution phase, present the block results to review team in timely manner.\n\nWork with and provide guidance to layout engg and monitors the progress of IP block layout\n\nWork with validation, product engineering and test engineering teams to enable them to measure Si performance\n\nOwn technical outcomes of design, verification, implementation, and execution of power management IPs with complexities that can span from simple regulators to complex mixed-signal designs and control loops \n\nAble to plan and execute the work in timely manner aligning with full chip schedule. \n\n#L1-LK1\n\nResponsibilities\nDesign and develop an analog IP block from definition to IP delivery\n\nDesign and simulation at the block/IP level during execution phase, present the block results to review team in timely manner.\n\nWork with and provide guidance to layout engg and monitors the progress of IP block layout\n\nWork with validation, product engineering and test engineering teams to enable them to measure Si performance\n\nOwn technical outcomes of design, verification, implementation, and execution of power management IPs with complexities that can span from simple regulators to complex mixed-signal designs and control loops \n\nAble to plan and execute the work in timely manner aligning with full chip schedule. \n\n#L1-LK1\n\nQualifications\nMinimum Requirements\n\nBS in Electrical Engineering or related +8 years of experience, or MS + 7 years of experience\n\nQualification\n\nSolid track record of delivering block/IP level design \n\nUnderstand and execute IP design, simulations methods, boundary conditions, stress and reliability simulations, PVT/PMC/SOA simulations.\n\nGood communication skills to make detailed technical presentations  \n\nGood understanding of various building blocks like LDOs, gate drivers, comparators, linear regulators, gm-stages, charge pumps etc \n\nExperience in SiC/GAN/LED/Motor, Efuse and smart Switches etc is plus\n\nStrong Analog IC design skills, debug of complex silicon problems using simulations and/or bench testing \n\nUnderstanding of power transistor Design, Layout, and Robustness \n\nExperience in system tools such as Simplis or MATLAB for architectural simulations, Cadence Spectre for schematic capture, simulation \n\nStrong verbal and written communication skills \n\nAbility to quickly ramp on new systems and processes \n\nDemonstrated strong interpersonal, analytical and problem-solving skills \n\nAbility to work in teams \n\n#L1-LK1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Principal Analog Design Engg", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-09-24", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506720", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Principal Analog design Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including LED drivers, SiC/MOS/IGBT/motor/GAN drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following\n\n \n\nLead and design analog IP blocks from definition to IP delivery individually as well as an IP lead\n\nEvaluate intermediate results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to layout engg for your IP block and monitors the progress\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nCollaborate with overseas design and systems teams on technical aspects, IP development, sharing of know-how \n\nOwn technical outcomes of design, verification, implementation, and execution of power management ICs with complexities that can span from simple regulators to complex mixed-signal designs and control loops \n\nUnderstand project goals, execute to schedule with given resources, track execution schedule to plan, monitor progress.\n\n#L1-LK1\n\nResponsibilities\nLead and design analog IP blocks from definition to IP delivery individually as well as an IP lead\n\nEvaluate intermediate results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to layout engg for your IP block and monitors the progress\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nCollaborate with overseas design and systems teams on technical aspects, IP development, sharing of know-how \n\nOwn technical outcomes of design, verification, implementation, and execution of power management ICs with complexities that can span from simple regulators to complex mixed-signal designs and control loops \n\nUnderstand project goals, execute to schedule with given resources, track execution schedule to plan, monitor progress.\n\n#L1-LK1\n\nQualifications\nMinimum Requirements\n\nBS in Electrical Engineering or related + 12 years of experience, or MS + 10 years of experience\n\n \n\nQualification\n\nSolid track record of designing multiple complex IPs with Si learnings\n\nUnderstand and execute IP design, simulations methods, boundary conditions, stress and reliability simulations, PVT/PMC/SOA simulations.\n\nExtensive knowledge of engineering processes, principles, and methodologies \n\nStrong CMOS circuit design fundamentals, circuit architectures. \n\nAbility to clearly articulate issues, challenges, and concerns to all levels of management \n\nGood understanding of various building blocks like charge pump, LDOs, gate drivers, comparators, linear regulators, gm-stage and relevant Analog building blocks \n\nUnderstanding of LED drivers, SiC/GAN devices and drivers is a strong plus\n\nStrong Analog IC design skills, debug of complex silicon problems using simulations and/or bench testing \n\nFamiliarity with advanced Bipolar, CMOS, and High Voltage BCD technology, Process, Device Physics, Semiconductor Manufacturing processes, and their impact on Analog performance \n\nunderstanding of power transistor Design, Layout, and Robustness \n\nProficiency in leading-edge design and verification tools such as Simplis or MATLAB for architectural simulations, Cadence Spectre for schematic capture, simulation, layout, and tape-out \n\nStrong verbal and written communication skills \n\nAbility to quickly ramp on new systems and processes \n\nDemonstrated strong interpersonal, analytical and problem-solving skills \n\nAbility to work in teams and collaborate effectively with people in different functions \n\nAbility to take the initiative and drive for results \n\n \n\n#L1-LK1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Sr Analog Design Engg.", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-09-24", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506715", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Sr Analog design Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following\n\nDesign and develop an analog IP block from definition to IP delivery\n\nDesign and simulation at the block/IP level during execution phase, present the block results to review team in timely manner.\n\nWork with and provide guidance to physical designers and monitors the progress of IP block layout\n\nWork with validation, product engineering and test engineering teams to enable them to measure Si performance\n\nOwn technical outcomes of design, verification, implementation, and execution of power management IPs with complexities that can span from simple regulators to complex mixed-signal designs and control loops \n\nAble to plan and execute the work in timely manner aligning with full chip schedule. \n\n#L1-LK1\n\nResponsibilities\nonsemi is seeking a Sr Analog design Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following\n\nDesign and develop an analog IP block from definition to IP delivery\n\nDesign and simulation at the block/IP level during execution phase, present the block results to review team in timely manner.\n\nWork with and provide guidance to physical designers and monitors the progress of IP block layout\n\nWork with validation, product engineering and test engineering teams to enable them to measure Si performance\n\nOwn technical outcomes of design, verification, implementation, and execution of power management IPs with complexities that can span from simple regulators to complex mixed-signal designs and control loops \n\nAble to plan and execute the work in timely manner aligning with full chip schedule. \n\n#L1-LK1\n\nQualifications\nSolid track record of delivering block/IP level design \n\nSound knowledge in CMOS analog design, CMOS fundamentals and related simulation tools \n\nGood communication skills to make detailed technical presentations  \n\nGood understanding of various Power Converters such as Buck, Boost, LDOs, gate drivers, comparators, linear regulators gm-stage and relevant Analog building blocks \n\nExperience in power converters like DC/DC, AC/DC, gate drivers, PMICs etc is plus\n\nStrong Analog IC design skills, debug of complex silicon problems using simulations and/or bench testing \n\nUnderstanding of large power transistor (LDMOS) Design, Layout, and Robustness \n\nExperience in system tools such as Simplis or MATLAB for architectural simulations, Cadence Spectre for schematic capture, simulation, layout, and tape-out \n\nStrong verbal and written communication skills \n\nAbility to quickly ramp on new systems and processes \n\nDemonstrated strong interpersonal, analytical and problem-solving skills \n\nAbility to work in teams \n\n#L1-LK1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Senior Implementation Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-24", "url": "https://careers.arm.com/job/bengaluru/senior-implementation-engineer/33099/100792411840", "is_hardware": true, "platform": "talentbrew", "jd_text": "We are seeking a highly experienced ASIC Physical Design Engineer with 12+ years of hands-on expertise in full-chip and hierarchical SoC physical design.  \n\nThis role requires deep technical expertise in advanced technology nodes, strong problem-solving capability, and leadership in driving chip closure from netlist to GDSII. \n\nJob Overview: \n\nResponsibilities: \n\nLead chip-level hierarchical floor planning and block-level integration. \n\nDrive partitioning strategy, partition push-down, and hierarchical design implementation. \n\nOwn pin planning, IO planning, bump planning, and bump routing for complex SoCs. \n\nDefine and execute power planning (ring/mesh/grid architecture, multi-domain handling). \n\nPerform and manage full-chip CTS and clock architecture optimization. \n\nLead chip integration activities across multiple blocks and subsystems. \n\nExecute and sign off physical verification (DRC, LVS, ERC, ESD, antenna, etc.). \n\nHandle ESD planning and implementation at chip level. \n\nDrive full-chip closure including congestion, IR/EM, timing, and noise analysis. \n\nCollaborate closely with RTL, synthesis, STA, package, and backend teams. \n\nSupport tape-out activities and resolve last-mile issues. \n\nMentor junior engineers and provide technical guidance on chip-level challenges. \n\nRequired Skills and Experience : \n\nEducation: \n\nBachelor’s or Master’s degree in Electrical Engineering, Electronics, Microelectronics, or related field! \n\nMandatory Experience: \n\nChip-level hierarchical floor planning \n\nPartitioning & partition push-down \n\nPin planning & IO planning \n\nBump planning & bump routing \n\nESD planning \n\nFull-chip integration \n\nPhysical verification (DRC/LVS/ERC/Antenna), IR DROP, SI-Noise Signoff. \n\nFull-chip CTS \n\nPower planning (multi-voltage domains, UPF awareness) \n\nHands-on experience with leading EDA tools (e.g., Innovus, ICC2, Fusion Compiler, Tempus, PrimeTime, Calibre, etc.) \n\nExperience in advanced nodes (5nm/3nm/2nm or similar preferred) \n\n“Nice To Have” Skills and Experience : \n\nExperience leading full-chip tape-outs. \n\nKnowledge of packaging interactions and bump/IO co-design. \n\nAbility to script and automate workflows using Python, TCL, or SKILL. \n\nFamiliar with Cadence/Synopsys/Mentor tools\n\n \n#LI-BB1\n\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Design Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-24", "url": "https://careers.arm.com/job/bengaluru/senior-design-engineer/33099/101070683088", "is_hardware": true, "platform": "talentbrew", "jd_text": "We are looking for a motivated and innovative Senior Design Engineer to develop innovative IPs and technologies for next-generation SoCs. If you enjoy solving complex design challenges, collaborating across teams, and influencing future architectures, this role is for you.\nResponsibilities:\nDevelop high-quality IP and technology components for advanced SoCs.\nWorking with Architects to refine and translate architecture specifications and translate them into detailed design specs.\nOwn micro-architecture, RTL coding, bug fixing, and design quality checks.\nCollaborate with verification teams on test plan reviews and debug activities.\nImprove and evolve design methodologies, flows, and guidelines.\nMentor and support junior team members to ensure successful project execution.\nRequired Skills and Experience:\nBachelor’s/Master’s degree in CS, EE, or CE\nSkilled in design for IPs/Sub systems with 5+ years of experience\nSynthesis & timing analysis\nPower management and low-power design techniques\nClock & power domain implementations\nDigital hardware design and Verilog HDL.\nStatic checks (Lint, CDC, RDC, Power checks)\nExperience writing design & micro-architecture specifications.\nHands-on RTL development expertise.\nProficiency with scripting (Perl, Python, etc.).\n“Nice To Have” Skills and Experience:\nExperience with ARM-based designs or ARM System Architectures.\nExposure to:\nAdvanced synthesis checks\nFunctional verification, X-propagation, GLS etc\nDFT and physical implementation flows\n10x Mindset at Arm\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Read more about how we bring the 10x mindset to life on the Arm blog.\n \n#LI-SC2\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Engineer, SoC PnP Architect", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-24", "url": "https://careers.arm.com/job/bengaluru/engineer-soc-pnp-architect/33099/101070672112", "is_hardware": true, "platform": "talentbrew", "jd_text": "Roles and Responsibilities:\nRun benchmarks and performance experiments in Linux and bare-metal environments. Collect and interpret metrics such as latency, bandwidth, throughput, and utilization.\nInvestigate performance bottlenecks using traces, counters, simulation results, and workload measurements, with guidance from senior engineers.\nDevelop and maintain C/C++ and Python scripts for workload characterization\nCompare measured performance against architectural expectations and help identify the causes of gaps.\nExperience Required:\nExperience in SoC Performance Analysis within the semiconductor industry\nStrong background in computer architecture and microarchitecture, including pipelines, cache hierarchy, memory systems, and system-level performance interactions.\nProficiency in C/C++ and Python for developing performance analysis tools, automation frameworks, profiling infrastructure, and data visualization.\nexperience working in both Linux and bare-metal environments, including:\nExcellent communication and cross-functional collaboration skills, with the ability to clearly present complex performance findings and influence architectural decisions\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Staff Analog Layout Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-24", "url": "https://careers.synopsys.com/job/bengaluru/senior-staff-analog-layout-engineer/44408/101087862656", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nYou have spent the better part of a decade building analog layouts that do not just pass verification, they perform in real silicon under real conditions. High-speed differential pairs, micro bump planning, die-to-die interconnects, these are not abstract concepts to you, they are problems you have solved repeatedly and refined over time. You know that a transmitter layout that looks clean in Virtuoso can still fail at the package if you did not think three steps ahead about return paths, skew, and substrate coupling.\nYou do not treat floor planning as a one-time exercise. You iterate with circuit designers, package engineers, and digital integration teams because you have learned that the best layouts emerge from collaboration, not isolation. When an EM/IR check flags a violation two days before tape out, you do not panic, you debug, you fix, and you close it.\nYou have worked on chiplet architectures, 2.5D integration, or advanced packaging, and you understand that UCIe is not just another interface, it is a shift in how we think about die boundaries, signal integrity, and physical partitioning. At Synopsys, you will work on IP that defines how chiplets talk to each other, and the layouts you create will ship in products that matter.\n\nWhat You'll Be Doing\nDesign and deliver full-custom analog layouts for UCIe PHY blocks including transmitters, receivers, drivers, equalizers, DLLs, bias circuits, calibration engines, and regulators\nExecute PHYTOP-level floor planning, bump planning, micro bump architecture, and channel routing with package co-design considerations for 2.5D/3D integration\nImplement high-speed differential routing with precise length matching, skew control, shielding, symmetry, and signal integrity optimization across die and package boundaries\nDrive physical verification closure including DRC, LVS, ERC, antenna checks, density rules, LPE extraction, EM/IR analysis, and reliability signoff\nCollaborate with ASIC physical design teams to integrate analog layouts into top-level flows, generate LEFs, support place-and-route, and resolve integration issues\nDevelop layout methodologies, automation scripts, and reusable design flows that improve efficiency and consistency across the team\nLead technical reviews, mentor layout engineers, resolve complex cross-domain issues, and drive tape out execution with global circuit design, package, and reliability teams\n\nThe Impact You Will Have\nYour layouts will enable UCIe die-to-die interfaces that ship in chiplet-based products across the semiconductor industry\nThe floor plans and bump architectures you create will define how analog PHYs integrate with digital logic, package substrates, and interposers in advanced 2.5D/3D systems\nYour signal integrity work will directly affect whether high-speed channels meet performance targets in real silicon, not just simulation\nThe verification methodologies and automation you build will accelerate tape out cycles and reduce respins for future PHY designs\nYour collaboration with package and digital teams will resolve integration challenges that would otherwise delay or compromise product quality\nThe engineers you mentor will carry forward the layout practices and problem-solving approaches you establish\nYour contributions will help Synopsys deliver industry-leading UCIe IP that powers the next generation of chiplet ecosystems\n\nWhat You'll Need\nDiploma or Bachelor's degree in Electrical Engineering, Electronics Engineering, or related technical field\n8 to 15 years of hands-on experience in analog or mixed-signal custom IC layout design\nProven track record designing layouts for UCIe PHY, high-speed SerDes, or die-to-die interface IP with successful tape outs\nDeep expertise in micro bump planning, bump map architecture, package-aware floor planning, and die/package co-design for 2.5D/3D integration including interposers, RDL, and TSVs\nStrong command of high-speed differential routing techniques including length matching, skew control, shielding, symmetry, and signal integrity-driven layout practices\nDemonstrated experience closing DRC, LVS, ERC, EM/IR, antenna, density, and reliability checks through tape out on advanced process nodes\nExperience integrating analog layouts with ASIC physical design flows, LEF generation, and top-level verification is a strong plus\n\nWho You Are\nYou can walk into a floor planning meeting with incomplete specs, ask the right questions about power distribution and signal flow, and walk out with a layout strategy that works\nWhen a package engineer tells you the micro bump pitch changed, you do not just update the layout, you think through the implications for channel routing, return paths, and crosstalk\nYou have debugged an LVS mismatch at 2 a.m. before tape out and found it was a subtle device matching issue that three other people missed\nYou can explain to a circuit designer why their ideal placement will not work given EM constraints, and propose an alternative that meets both performance and reliability requirements\nYou keep track of five parallel layout blocks, their verification status, and their integration dependencies without losing sight of the tape out timeline\nYou document your work clearly enough that an engineer in a different time zone can pick up your layout, understand the intent, and continue without a handoff call\n\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "PTE Engineer, Consumer Audio", "company": "Analog Devices", "location": "India, Bangalore, Nova", "date_posted": "2026-09-24", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-Nova/PTE-Engineer--Consumer-Audio_R266064", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nSenior Test Engineer - Test & Product Development\nJob Description\nADI’s Hearable Audio Solutions Business Unit is looking for a Senior engineer in test product development at our Bangalore location. The candidate will become an integral part of the Product & Test Engineering (PTE) activities for the development of mixed signal audio edge processors and battery management power products. The candidate will also be part of pre & post-silicon phase of the silicon development from DFT to silicon bring up / characterization to high volume production. The ideal candidate will be technically strong and will have demonstrated experience in testing both Digital and Analog/Mixed-Signal (AMS) Products, working with cross functional teams like Design, Bench Eval, PD, etc., with ability to collaborate with ADI global teams and off-shore subcons. \nJob Responsibilities:\nDesign of innovative, reliable, and efficient Probe and Test solutions with highly parallel multi-site test capability using mixed signal/Digital ATE platforms (primarily ultra-flex or NI or 93K)\nDevelopment of the ATE software solutions as per the specifications.\nPlay a role in DFT/BIST definition & development, through direct involvement with the Design Team early in the New Product Development, to reduce FFC and improve testability.\nExecution of the Test development phases of the projects including Silicon functionality, Characterization, Yield Analysis, Correlation & Offshore Production release.\n\nQualifications:\nHave a degree in Electrical/Electronic Engineering\nHave 5-7years’ of hands-on experience in mixed signal or digital test.\nHave knowledge of the ATE software development and working knowledge of Teradyne Flex, NI and/or 93K ATE systems.\nHave good analytical & statistical skills and knowledge of the Perl/C++ programming.\nBe experienced in ATE highly parallel multi-site test digital h/w design & layout, with lead skills in understanding the problems/limitations in hardware development.\nBe experienced in releasing multi-site test programs to offshore production test houses.\nBe well versed with the usage of bench equipment such as Oscilloscope, VI-meter, Signal generator and analyzers.\nBe capable of working with the reliability engineers on the product qual\nBe proactive and work under own supervision.\nBe self-motivated, and willing to accept responsibility.\nPossess strong interpersonal, teamwork & communication skills.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Principal Test Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-23T16:04:23.368000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000151425519-principal-test-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "IFI (India for India) organization is seeking a Principal Test Engineer to define and deliver robust, cost-effective production test solutions for new semiconductor products from concept through mass production and sustaining support. In this lead role, the principal test engineer owns the test strategy, ATE test development, test hardware, test validation, qualification and production release, test-cost optimization and industrial activities.\nKey Responsibilities\nDefine the production test strategy and manufacturing test flow for assigned products including tester selection\nOwn the test planning\nProvide testability input to DFT, DFM and design reviews before tapeout\nDefine detailed test plan covering ATE implementation\nLead test hardware requirements and development, including loadboards, probe cards, sockets, interface hardware and related fixtures.\nDevelop and review ATE test programs, test methods, production patterns and supporting software.\nLead first-silicon ATE bring-up, test program debug and sample generation.\nExecute ATE characterization across process, voltage and temperature conditions in alignment with the product characterization plan.\nSupport qualification and customer sample generation by developing dedicated test programs\nIdentify test coverage gaps and potential escapes, then implement containment and permanent corrective actions\nRelease qualified test software and hardware into production and support OSAT manufacturing start-up.\nReview and sign off test deliverables\nDrive production ramp readiness reviews and close test-related release risks.\nReduce test time through method optimization, improved sequencing, multisite efficiency and instrumentation utilization.\nSupport customer-return and RMA investigations by reproducing failures and assessing production test coverage.\nTechnical Leadership\nProvide technical direction, sign off reviews\nLead technical decisions and risk resolution across Design, Product Engineering, Operations, suppliers and OSAT teams including DFX topics\nFully independent and recognized as subject-matter-expert\nInfluence cross-functional teams without direct authority and communicate clearly to the stakeholders.\n\nBachelor's or Master's degree in Electronics Engineering, Electrical Engineering or a related discipline.\nAt least 15 years of relevant semiconductor test engineering experience spanning NPI, characterization, qualification, production release and sustaining support.\nStrong knowledge of semiconductor production test methodologies and practical experience developing ATE test solutions.\nExperience with Teradyne J750HD, Advantest V93000 or equivalent ATE platforms.\nExperience developing production test solutions for SoC, MCU products\nExperience with test hardware development, including loadboards, probe cards, sockets and handler/prober interfaces.\nStrong programming skills\nExperience driving manufacturing release at OSATs\nExperience with data-analysis and yield-management tools such as JMP, PDF Exensio, Python or equivalent platforms.\nStrong analytical, technical leadership, planning, communication and problem-solving skills.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Principal Product Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-23T16:02:22.119000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000151424354-principal-product-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "IFI organization is seeking a Principal Product Engineer to provide end-to-end ownership from engineering material planning through qualification, characterization, product release and volume-production support. In this role, the principal product engineer acts as the lead within the project and owns the characterization, qualification plan, production release, and industrial activities.\nKey Responsibilities\nOwn the assigned product lifecycle from concept and first silicon through qualification, production release, sustaining and end of life. \nDrive first-silicon bring-up and debug with Design, Test, Applications teams. \nPlan and coordinate voltage, temperature and process characterization, including production limit setting and guard-banding. \nCreate and maintain product BOMs and product lifecycle data in PLM systems such as Agile. \nWork with planning, manufacturing, subcontractors and operations teams to remove material-flow obstacles and recover schedule gaps. \nOwn qualification planning and execution in accordance with applicable JEDEC and AEC requirements. \nPrepare product-release documentation, datasheet compliance evidence and automotive compliance reports as applicable. \nMonitor production data and use statistical analysis to identify and correct yield, quality and test-time deficiencies. Drive yield improvement\nOptimize PAT, SYL, SBL, SPC and disposition limits to protect outgoing quality\nSupport fab transfer and BOM change activities\nSupport customer-return and RMA investigations by reproducing failures and assessing production test coverage.\nTechnical Leadership\nProvide technical direction, sign off reviews\nLead technical decisions and risk resolution across Design, Product Engineering, Operations, suppliers and OSAT teams including DFX topics\nFully independent and recognized as subject-matter-expert\nInfluence cross-functional teams without direct authority and communicate clearly to the stakeholders.\n\nBachelor’s degree in electronic engineering or industrial engineering \nAt least 15 years of relevant semiconductor experience spanning product engineering, NPI, manufacturing, test \nPractical understanding of semiconductor wafer fabrication, assembly, test, qualification and production-release flows. \nExperience managing engineering wafer starts, prototype builds, customer samples, inventory and product BOMs. \nWorking knowledge of SoC and mixed-signal device testing, common circuit building blocks, device behaviour and semiconductor test methodology. \nFamiliarity with ATE platforms such as Teradyne J750 or Advantest V93000, and with laboratory equipment such as oscilloscopes, power supplies and digital multimeters. \nFamiliarity with JEDEC/AEC qualification standards, qualification hardware/software and semiconductor failure analysis. \nExperience with PLM and yield-management tools such as Agile, PDF Exensio or JMP. \nExperience working with external foundries, OSATs, subcontractors and globally distributed product teams. \nExperience with failure analysis methods \nExperience using data and statistical methods to manage yield, quality, cycle time and operational priorities. \nStrong analytical, planning, coordination and problem-solving skills, with attention to detail and the ability to work under schedule pressure. \nClear written and verbal communication skills and the ability to influence cross-functional teams without direct authority. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Lead Verification Engineer - PCIE/CXL", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-23T10:28:00+00:00", "url": "https://global-external-amd.icims.com/jobs/86823/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. MTS SILICON DESIGN ENGINEER    THE ROLE: As an IP verification engineer in the AECG Group, you will help bring to life cutting-edge FPGA, ASICs for variety of target customers. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, PD teams, and product engineers to achieve first pass silicon success. THE PERSON: You have a passion for modern, complex IP architectures, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBLITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified for PCIe CXL based IP's Develop test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Code IP or SS level UVM based testbenches, verification components - monitors, scoreboard, checkers Build the directed and random verification tests Run regressions, debug test failures towards ensuring high design functional, performance and implementation quality  PREFERRED EXPERIENCE: 8-10 Years of Experience in ASIC Verification Experience with PCIe or CXL or ethernet protocols is a must Proficient in IP level ASIC verification Expert in Verilog, System Verilog, Object Oriented programming Expertise in developing UVM based verification frameworks and testbenches Scripting and automation of verification processes and flows Exposure to leadership or mentorship is an asset Experience working in a team environment through the ASIC / FPGA Project lifecycle from Planning to Tape Out Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Comfortable in python / Perl and editing / maintaining scripts Strong communication skills and the ability to work independently as well as in a cross-site team environment Good Computer Architecture, systems knowledge is a plus Exposure to generative AI or simulation tools for test, testbench, assertion, test plan generation or performance optimization is a plus ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-NS1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "ASIC Top Level Verification-HW Emulation", "company": "Ericsson", "location": "Bangalore,Karnataka,India", "date_posted": "2026-09-23T09:40:08+00:00", "url": "https://jobs.ericsson.com/careers/job/563121775484433", "is_hardware": true, "platform": "eightfold", "jd_text": "About this opportunity\n\nJoin our new ASIC top level verification team.\nWe specialize in the top-level verification of cutting-edge ASICs that power complex high-performance systems. Our designs are either monolithic ASICs or integrated multi-chip-modules holding several hundreds of processor cores, DSPs as well as ARM cores, tailored hardware accelerator IPs and many high-speed interfaces, including Ethernet, CPRI, and PCIe.\nAs an ASIC Top-Level Verification Engineer, you'll be part of a team tackling some of the most challenging verification tasks in the industry, ensuring that our ASICs meet our high standards for performance, functionality, and security.\nYou will play an important role in the team developing environments and/or tests run in SystemC/TLM simulation, RTL environments, hardware emulation, and eventually on Silicon.\n\nWhat you will do\n\nWe are looking for people with focus in various areas in ASIC TLV. Exactly what you will do depends on your experience and the needs in the different projects, but typically includes\nSoC level testcase development with possibilities to specialize in special areas related to traffic on external interfaces and/or ASIC internal functionality involving DSPs, MCUs, CPU cores, ARM infrastructure, switches, security, SerDes, DDR and other types of external memory and much more.\nPreparing and setting up designs to run in Hardware Emulators, and update and maintain existing emulator platforms.\nParticipate in defining/documenting verification strategies for the parts of the ASIC assigned to you as a verifier.\nAs input you have documents and information from interaction with various type of stakeholders.\nParticipate in specification and development of software driven tests written in C.\nDebug RTL designs with help of EDA simulation tools and SW debuggers.\nBut also debug failing test cases using the SystemC/TLM platform or using the hardware emulator, depending on the situation\nBeside RTL simulations you will debug failing test cases running on any of our other run-platforms, SystemC/TLM simulation, Hardware emulation and on Silicon mounted on boards in the lab. In case you lack experience of some platform you are expected to develop skills for such tasks.\nContribute to keeping tests clean in the CI regression running on our four platforms.\n.\n\nYou will bring\n\nGeneral skills you must possess:\nSolid C programming skills targeting ASICs or other type of embedded software programming.\nSolid skills in RTL debugging issues in simulations of SystemVerilog or VHDL designs.\nDesired knowledge and experience in:\nUsing SW debuggers, waveforms windows etc. for HW/SW co-debugging of C-code running in the ASIC. Experience of multi core designs is a plus.\nGLS\nCoresight and other JTAG TAP related features\nCompiling designs for HW emulation\nFormal connectivity verification\nHigh speed interfaces like Ethernet, PCIe, CPRI\nARM CPUs/cores, SMMU\nAMBA interconnect, preferably using Cadence STG or IWB\nSoft Skills\nOpen, inclusive mindset, embracing diversity in culture, nationality, gender, etc.\nCollaborative approach, with a focus on team productivity and mutual growth.\nStrong drive for innovation, with a proactive interest in refining verification methodologies.\nClear communication skills for effective teamwork and coordination across diverse teams.\n\n.\n\n“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”", "jd_status": "stored"}, {"title": "FPGA prototyping/FPGA design Engineer (Lead/Staff)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-23T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719574650", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nExperience: 5+ years of relavant experience is a must.\n\nPrincipal Duties and Responsibilities:\n•    Applies Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Assists in the assessment of complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SoC STA/Timing Engineer (Senior Staff/Principal)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-23T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720933067", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nJob Description:\n12 to 20 years of relavant experience is a must\nSTA Setup & Signoff: Perform STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs for SoC & SubSystem\nTiming Analysis & Debug: Validate and debug timing across multiple PVT conditions using tools like PrimeTime and Tempus.\nFlow Optimization: Run STA flows and correlate Spice to STA results.\nMethodology Development: Evaluate timing methodologies/tools across technology nodes and automate STA/PD flows using TCL/Perl/Python.\nCross-Functional Collaboration: Work closely with design, DFT, synthesis, technology, CAD and physical implementation teams.\nLow-Power Techniques: Knowledge of clock gating, power gating, and multi-voltage designs.\nECO Timing Flow: Handle timing ECOs (DMSA, tweaker, PrimeClosure) and logical equivalence checks (RTL to Netlist). \nRequired Skills\nStrong expertise in STA fundamentals, AOCV/POCV concepts, CTS, and timing constraints.\nHands-on experience with STA tools: PrimeTime, Tempus.\nFamiliarity with ASIC back-end flows: ICC2, Innovus.\nKnowledge of signal integrity, cross-talk noise, and parasitic extraction.\nScripting proficiency: TCL, Perl, Python.\nMentoring junior engineers in different areas of timing flows and methodologies\nUnderstanding of Spice simulations: Hspice, FineSim, Monte Carlo analysis. \nPreferred Experience\nDriving timing convergence at chip-level and hard-macro level.\nExposure to RTL-to-GDSII flows.\nGood technical writing and communication skills for cross-team collaboration\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "PMIC Systems and Validation Engineer, Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-23T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721205111", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nPMIC Systems & Validation Engineer\nTeam & Product Overview:\nQualcomm's Power Management Systems, Validation & Integration team (PMIC-SVI) leads the industry in the system architecture and post-silicon validation of high-performance feature-rich Power Management Integrated Circuits (PMICs), that are embedded in our Chipsets - for smartphones, tablets, laptops, wearables and a variety of cutting-edge consumer electronics. This team gets to work on state-of-art technology to enable products with world’s leading brands.\nA typical Qualcomm PMIC is a highly advanced IC that has a multitude of IPs viz. switching DC-DC converters, linear regulators, clock oscillators, battery charger, fuel gauge, LED drivers, and ADCs. Additionally, there is an embedded mini-processor running critical firmware (FW) to support power sequencing, interrupt servicing, crash handling and various device reset scenarios. It is also responsible for maintaining various stability & performance related configurations that are part of SoC software driver initializations. Furthermore, it provides an intelligent-framework for sequencing of time-critical-operations, which otherwise can't be guaranteed by any OS / higher-level software. Often, Qualcomm chipset solutions contain multiple PMICs working together in sync – which together constitute a ‘PMIC-System’.\n\nJob Responsibilities\nThis job involves a mix of Architecture, HW Systems, Functional Validation, Chipset integration & customer issue debug support. We are looking for Systems & Validation engineers with preferably 8 years of experience in analog/power electronics. Depending on your experience level and area of technical expertise you will own and participate in systems definition, HW/SW debugging and validation of PMIC solutions by partnering with various engineering teams like Analog/Digital Design, Software and Customer Engineering in a fast-paced environment.\nSystems involves coming up with a Top-Level specification (involving HW/FW/SW level partitioning of feature-design, HW Register interfaces, memory sizing, protocol selection, multi-PMIC connectivity grid, debug framework support, etc) to satisfy all chipset level requirements.\n\nValidation involves coming up with a comprehensive functional validation plan (that covers both manual and scripted automated test cases), executing them within stipulated time-period, analyzing results at HW-level (via signal measurements), debugging issues & creating reports.\n\nEngineers will be responsible to perform risk assessment of development and validation plans; and interact with PMIC Product Management, Design & Characterization teams; other SoC HW/SW Architecture, Development & Validation teams; and finally Customer-Engagement teams across worldwide sites.\n\nEducation Requirements\nA Bachelor's degree in Electronics related Engineering is a must.\nMaster’s degree is preferred esp. with specialization in VLSI / Microelectronics, Power Management, etc.\n\nMinimum Qualifications\nWe are looking for applicants with 8+ years of job-experience – relevant to various HW/S aspects of any electronic product development. They should be well-versed with knowledge of entire ASIC Flow (from concept-stage to commercial-product support).\n\nPreferred Qualifications\nApplicants should be aware of fundamentals of PMIC, Power Management, Microcontroller architecture, basic-firmware & HW-SW interaction.\n\nApplicants should also have strong hands-on lab-experience in Post-Si Validation. (HW-level Bench measurement and/or SW-level logs-based verification).\n\nPreferred Skills:\n· Hands-on ability & comfort in using various lab instruments like oscilloscopes, power supplies, JTAG debuggers etc.\n· Good understanding of PMIC, Power Electronics , digital & embedded electronics concepts\n· Good Hardware Debug Skills related to DC -DC (SMPS, LDO) converters preferred.\n· Good programming skills in at least one of the following: C#, F#, Python, Perl, LabVIEW or any other scripting language (used in VLSI/Embedded Domain) + understanding of few OOPS concepts.\n· Familiarity with HW schematics and ability to trace inter connections on a PCB. Good analytical & communication (verbal/written) skills.\n· Ability to seek information pro-actively, understand priorities and juggle multiple tasks in a highly paced environment.\n· Experience in automating test-cases via SW-control for HW-systems Ability to come up with a High-Level Strategy for any objective and being able to break it into Mid-level flows & Low-level tasks – for efficient execution.\n· Prior experience in leading & executing white-box validation efforts of a HW-module or sub-module, is a big plus.\n· Exposure to Assembly-language programming (for microcontroller) is good-to-have. Exposure to tools like JIRA and GIT are a plus.\n\nKeywords PMIC, Power Systems, System Architecture, switch mode power supply, SMPS, DC-DC, LDO, ADC, functional Validation, test automation, Voltage Regulators, Battery Chargers, Battery Management/Gauging\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SoC Program Management Director", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-23T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721219991", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Services Group, Engineering Services Group > Program Management\nGeneral Summary:\nDevelops, defines, and executes plans of record, including: schedules, budgets, resources, deliverables, and risks. Monitors and drives the program from initiation through delivery, interfacing with internal and external stakeholders across functions on technical matters, as needed. Monitors budget/spending, on-time delivery, and achievement of program milestones. Represents the program and drives alignment across stakeholders. \n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Computer Science, or related field.\n•    5+ years of Program Management or related work experience.\n\n​Job Overview:\nWe are looking for technically strong System on Chip(SOC) Program Manager to own and manage the enablement, execution and delivery of System on Chip(SOC)\n  \nDetailed JD & Responsibilities:\nProgram Manager expected to drive the requirements, scoping, planning and execution of highly complex SoC across the portfolio. This involves working and supporting multiple functional teams including Design, DV, DFT, Physical design and System emulation. \nTrack the program milestones & Key KPI’s (Power, Performance, Cost) \nSupport program development activities as required for NPI development – Starting from concept review to TO(Tapeout) and further towards commercialization\nDrive SOC execution reviews and track milestones using program indicators. Participate in cross functional reviews including technology, IP and Process and update to executive management   \nKey custodian for Risk, Schedule, NRE, quality and compliance to process\nUpdate Project dashboards on weekly basis, review and drive closure of checklists, work with cores/IP team on schedule & NRE tracking.\nHelps to promote program vision and objectives within own team and ensures program objectives are met or exceeded.\nCollaborates with key stakeholders and program sponsors to develop goals, set the prioritization of deliverables, and discuss necessary priorities and stakeholder needs\n\nMinimum Qualifications:\nBachelor's degree in Engineering, Computer Science, or related field.\n7+ years Program Management or related work experience\n\nPreferred Qualifications & Expertise: \n20 + years experience in the semiconductor industry with minimum 7 years in Project/Program Management\nGood experience in Microsoft Tools like Excel, Power point, Word\nMust have strong interpersonal skills and be able to effectively communicate at all levels\nSound knowledge and understanding of Semiconductor Chip design cycle, Development and Process from design to customer deployment\nExposure to one or more of the technology fields will be preferrable - IOT, Wireless/Mobile or Automotive\nExposure and ability to work and adapt in new technologies like AI driven reports, dashboards creation.\nTrack record of proven leadership/management experience\nProcess definition & implementation\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "PMIC Systems and Validation Engineer, Senior", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-23T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721205109", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob DescriptionAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nAdditional Job Description\nPMIC Systems & Validation EngineerTeam & Product Overview:Qualcomm's Power Management Systems, Validation & Integration team (PMIC-SVI) leads the industry in the system architecture and post-silicon validation of high-performance feature-rich Power Management Integrated Circuits (PMICs), that are embedded in our Chipsets - for smartphones, tablets, laptops, wearables and a variety of cutting-edge consumer electronics. This team gets to work on state-of-art technology to enable products with world’s leading brands.A typical Qualcomm PMIC is a highly advanced IC that has a multitude of IPs viz. switching DC-DC converters, linear regulators, clock oscillators, battery charger, fuel gauge, LED drivers, and ADCs. Additionally, there is an embedded mini-processor running critical firmware (FW) to support power sequencing, interrupt servicing, crash handling and various device reset scenarios. It is also responsible for maintaining various stability & performance related configurations that are part of SoC software driver initializations. Furthermore, it provides an intelligent-framework for sequencing of time-critical-operations, which otherwise can't be guaranteed by any OS / higher-level software. Often, Qualcomm chipset solutions contain multiple PMICs working together in sync – which together constitute a ‘PMIC-System’.Job ResponsibilitiesThis job involves a mix of Architecture, HW Systems, Functional Validation, Chipset integration & customer issue debug support. We are looking for Systems & Validation engineers with preferably\n3 - 5 years of experience in analog/power electronics. Depending on your experience level and area of technical expertise you will own and participate in systems definition, HW/SW debugging and validation of PMIC solutions by partnering with various engineering teams like Analog/Digital Design, Software and Customer Engineering in a fast-paced environment.Systems involves coming up with a Top-Level specification (involving HW/FW/SW level partitioning of feature-design, HW Register interfaces, memory sizing, protocol selection, multi-PMIC connectivity grid, debug framework support, etc) to satisfy all chipset level requirements.Validation involves coming up with a comprehensive functional validation plan (that covers both manual and scripted automated test cases), executing them within stipulated time-period, analyzing results at HW-level (via signal measurements), debugging issues & creating reports.Engineers will be responsible to perform risk assessment of development and validation plans; and interact with PMIC Product Management, Design & Characterization teams; other SoC HW/SW Architecture, Development & Validation teams; and finally Customer-Engagement teams across worldwide sites.Education RequirementsA Bachelor's degree in Electronics related Engineering is a must.Master’s degree is preferred esp. with specialization in VLSI / Microelectronics, Power Management, etc.Minimum QualificationsWe are looking for applicants with\n3 - 5 years of job-experience – relevant to various HW/S aspects of any electronic product development. They should be well-versed with knowledge of entire ASIC Flow (from concept-stage to commercial-product support).Preferred QualificationsApplicants should be aware of fundamentals of PMIC, Power Management, Microcontroller architecture, basic-firmware & HW-SW interaction.Applicants should also have strong hands-on lab-experience in Post-Si Validation. (HW-level Bench measurement and/or SW-level logs-based verification).Preferred Skills:· Hands-on ability & comfort in using various lab instruments like oscilloscopes, power supplies, JTAG debuggers etc.· Good understanding of PMIC, Power Electronics , digital & embedded electronics concepts· Good Hardware Debug Skills related to DC -DC (SMPS, LDO) converters preferred.· Good programming skills in at least one of the following: C#, F#, Python, Perl, LabVIEW or any other scripting language (used in VLSI/Embedded Domain) + understanding of few OOPS concepts.· Familiarity with HW schematics and ability to trace inter connections on a PCB. Good analytical & communication (verbal/written) skills.· Ability to seek information pro-actively, understand priorities and juggle multiple tasks in a highly paced environment.· Experience in automating test-cases via SW-control for HW-systems Ability to come up with a High-Level Strategy for any objective and being able to break it into Mid-level flows & Low-level tasks – for efficient execution.· Prior experience in leading & executing white-box validation efforts of a HW-module or sub-module, is a big plus.· Exposure to Assembly-language programming (for microcontroller) is good-to-have. Exposure to tools like JIRA and GIT are a plus.Keywords PMIC, Power Systems, System Architecture, switch mode power supply, SMPS, DC-DC, LDO, ADC, functional Validation, test automation, Voltage Regulators, Battery Chargers, Battery Management/Gauging\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "PMIC Systems Validation Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-23T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721205110", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob DescriptionAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nAdditional Job Description\nPMIC Systems & Validation EngineerTeam & Product Overview:Qualcomm's Power Management Systems, Validation & Integration team (PMIC-SVI) leads the industry in the system architecture and post-silicon validation of high-performance feature-rich Power Management Integrated Circuits (PMICs), that are embedded in our Chipsets - for smartphones, tablets, laptops, wearables and a variety of cutting-edge consumer electronics. This team gets to work on state-of-art technology to enable products with world’s leading brands.A typical Qualcomm PMIC is a highly advanced IC that has a multitude of IPs viz. switching DC-DC converters, linear regulators, clock oscillators, battery charger, fuel gauge, LED drivers, and ADCs. Additionally, there is an embedded mini-processor running critical firmware (FW) to support power sequencing, interrupt servicing, crash handling and various device reset scenarios. It is also responsible for maintaining various stability & performance related configurations that are part of SoC software driver initializations. Furthermore, it provides an intelligent-framework for sequencing of time-critical-operations, which otherwise can't be guaranteed by any OS / higher-level software. Often, Qualcomm chipset solutions contain multiple PMICs working together in sync – which together constitute a ‘PMIC-System’.Job ResponsibilitiesThis job involves a mix of Architecture, HW Systems, Functional Validation, Chipset integration & customer issue debug support. We are looking for Systems & Validation engineers with preferably\n1 -2 years of experience in analog/power electronics. Depending on your experience level and area of technical expertise you will own and participate in systems definition, HW/SW debugging and validation of PMIC solutions by partnering with various engineering teams like Analog/Digital Design, Software and Customer Engineering in a fast-paced environment.Systems involves coming up with a Top-Level specification (involving HW/FW/SW level partitioning of feature-design, HW Register interfaces, memory sizing, protocol selection, multi-PMIC connectivity grid, debug framework support, etc) to satisfy all chipset level requirements.Validation involves coming up with a comprehensive functional validation plan (that covers both manual and scripted automated test cases), executing them within stipulated time-period, analyzing results at HW-level (via signal measurements), debugging issues & creating reports.Engineers will be responsible to perform risk assessment of development and validation plans; and interact with PMIC Product Management, Design & Characterization teams; other SoC HW/SW Architecture, Development & Validation teams; and finally Customer-Engagement teams across worldwide sites.Education RequirementsA Bachelor's degree in Electronics related Engineering is a must.Master’s degree is preferred esp. with specialization in VLSI / Microelectronics, Power Management, etc.Minimum QualificationsWe are looking for applicants with 1-2 years of job-experience – relevant to various HW/S aspects of any electronic product development. They should be well-versed with knowledge of entire ASIC Flow (from concept-stage to commercial-product support).Preferred QualificationsApplicants should be aware of fundamentals of PMIC, Power Management, Microcontroller architecture, basic-firmware & HW-SW interaction.Applicants should also have strong hands-on lab-experience in Post-Si Validation. (HW-level Bench measurement and/or SW-level logs-based verification).Preferred Skills:· Hands-on ability & comfort in using various lab instruments like oscilloscopes, power supplies, JTAG debuggers etc.· Good understanding of PMIC, Power Electronics , digital & embedded electronics concepts· Good Hardware Debug Skills related to DC -DC (SMPS, LDO) converters preferred.· Good programming skills in at least one of the following: C#, F#, Python, Perl, LabVIEW or any other scripting language (used in VLSI/Embedded Domain) + understanding of few OOPS concepts.· Familiarity with HW schematics and ability to trace inter connections on a PCB. Good analytical & communication (verbal/written) skills.· Ability to seek information pro-actively, understand priorities and juggle multiple tasks in a highly paced environment.· Experience in automating test-cases via SW-control for HW-systems Ability to come up with a High-Level Strategy for any objective and being able to break it into Mid-level flows & Low-level tasks – for efficient execution.· Prior experience in leading & executing white-box validation efforts of a HW-module or sub-module, is a big plus.· Exposure to Assembly-language programming (for microcontroller) is good-to-have. Exposure to tools like JIRA and GIT are a plus.Keywords PMIC, Power Systems, System Architecture, switch mode power supply, SMPS, DC-DC, LDO, ADC, functional Validation, test automation, Voltage Regulators, Battery Chargers, Battery Management/Gauging\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Engineer II - Verification Engineer", "company": "Microchip", "location": "India - Hyderabad", "date_posted": "2026-09-23", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Hyderabad/Senior-Engineer-II---Verification-Engineer_R3568-26", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nAbout the Role\nWe are seeking an experienced C-Based FPGA Pre-Silicon Verification Engineer to drive verification activities for next-generation FPGA platform. In this role, you will develop and execute verification strategies for FPGA verification. You will work closely with RTL designers, architects, firmware teams, and validation engineers to ensure robust functional coverage and early bug detection across complex FPGA designs.\nThe role involves developing C/C++ based test frameworks, firmware-driven verification environments, simulation based verification flows, and hardware/software co-verification methodologies. You will contribute to pre-silicon verification using SystemVerilog/UVM environments while leveraging embedded software, BFMs, and protocol stacks to validate real-world use cases.\nYou will independently manage complex verification tasks, debug RTL and firmware interactions, analyze failures, and drive verification closure. The ideal candidate will have strong expertise in FPGA/SoC architectures, embedded software development, and pre-silicon verification methodologies.\nThis role also includes mentoring engineers, defining best practices, and contributing to innovation and continuous improvement in verification methodologies and automation flows.\n\nRequirements/Qualifications:\n\nQualifications\nBachelor’s or Master’s degree in Electrical Engineering or a related field.\nRequired Skills and Experience\n8+ years of experience in FPGA/ASIC functional verification with strong focus on C-based or embedded software-driven pre-silicon verification..\nExperience with RISC-V, ARM-based SoCs, or embedded CPU verification\n Hands-on experience developing C/C++ testcases and verification frameworks for FPGA/SoC verification\nStrong understanding of FPGA architectures, SoC subsystems, memory architectures, interrupts, DMA, boot flows, and embedded processors\nStrong scripting skills in Python, Shell, Perl, and TCL.\nExperience with coverage-driven and assertion-based verification methodologies.\nExperience developing constrained-random and directed simulation testcases using System Verilog/UVM; knowledge of C-based testcase development is a plus.\nSolid understanding of IC chip design, development flows, and verification methodologies.\nProven ability to develop verification plans, build robust UVM testbenches, define functional coverage models, execute regressions, analyze coverage gaps, and drive closure against verification goals.\nStrong analytical, debugging, and problem-solving skills.\nExcellent written and verbal communication skills in English\n\nTravel Time:\n\nNo Travel\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Senior Staff IP Design Engineer", "company": "Lattice", "location": "Penang, Malaysia", "date_posted": "2026-09-23", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Penang-Malaysia/Senior-Staff-SW-Dev-Eng_R-102550", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\n\nA successful candidate will join a team designing and developing Lattice FPGA software tools at Penang. The candidate will contribute to research, design and development of FPGA Foundation IP and IP Catalog tooling. The candidate is expected to work closely with cross-functional teams to plan and execute Lattice FPGA software release cycle including requirement analysis, feature scoping, development, testing and validation. The candidate also will be responsible for maintaining existing software product tools and develop improvement plan to increase the test coverage to achieve high product quality.\n\nKey Responsibilities\nDesign and implement Digital Signal Processor (DSP) DSP-centric foundation IP blocks, including multipliers, accumulators, FIR/IIR filter primitives, and arithmetic units targeted for integration into FPGA fabric\nDevelop RTL (VHDL/Verilog/SystemVerilog) for DSP hard macros and programmable DSP slices\nPerform functional simulation and timing analysis to ensure correctness and performance targets are met\nEngage with software and tools teams to ensure DSP IP is correctly modeled in simulation libraries and synthesis flows\n\nRequired Qualifications\nBachelor's or Master's degree in Electronics/Electrical Engineering, Computer Engineering, or a related discipline\n10 or more years of experience in IP design or ASIC/FPGA engineering\nStrong proficiency in RTL design using Verilog, VHDL, or SystemVerilog\nWorking experience in DSP theory and algorithms: filtering, FFT, fixed-point arithmetic, sample-rate conversion\n\nPreferred Qualifications\nExperience with functional verification methodologies (SystemVerilog Assertions, formal verification)\nFamiliarity with synthesis and static timing analysis tools (Synopsys Design Compiler, PrimeTime, Radiant, Quartus or equivalent)\nWorking knowledge of FPGA architectures and programmable DSP slice design\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nMalaysiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Lead Verification Engineer", "company": "Cadence", "location": "NOIDA", "date_posted": "2026-09-23", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/NOIDA/Lead-Verification-Engineer_R56198-1", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nCadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.\nThe Cadence Advantage\nThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.\nCadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.\nThe unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success\nMultiple avenues of learning and development available for employees to explore as per their specific requirement and interests\nYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.\nJob Summary:\nWe are looking for a candidate with excellent communication skills and ability to ramp up on new technologies quickly and independently. This position requires the technical expertise in Emulation domain. This an excellent opportunity to work in a supportive and friendly work environment, where we are vested in each other’s success, and are passionate about technology and innovation.\nPosition Description:\nProduct validation engineer to work on key Palladium technologies including UPF. Position is based in Noida/Bangalore.\nRole involves verification of various upcoming features in Palladium.\nWork also involves managing current set of regressions.\nParticipate in technical discussions, including Functional Specification reviews, Testplan reviews etc\nReview and guide team members on technical deliverables from the team\nPerson will be fully responsible and accountable for quality of releases and features for Palladium emulation technology.\nMentor juniors in the team\nContribute towards the improvement of existing emulation validation/verification flows  \nPosition Requirements:\nThe person should be an Electrical, Electronics or Computer Science Engineer with very good understanding of HDLs (Verilog and/ or VHDL).\nPrior experience in Emulation/UPF will be big plus. He/ she should have a good working knowledge of EDA tools (Cadence/ Others) specially Palladium with focus towards debugging design/ verification problems.\nExperience in process automation with scripting.\nExperience with SystemVerilog, C++, UVM.\nExperience with Functional Verification of complex digital systems, e.g. SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog.\nB. Tech/BE/ M. Tech / ME with 3+ years of relevant experience\nBehavioral skills required:\nMust possess strong written, verbal and presentation skills.\nGood communication and interpersonal skills, demonstrate teamwork and collaboration skills.\nAbility to establish a close working relationship with both customer peers and management.\nExplore what’s possible to get the job done, including creative use of unconventional solutions\nWork effectively across functions and geographies\nPush to raise the bar while always operating with integrity\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Architect - System Performance Verification and Analysis", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-09-23", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Architect---System-Performance-Verification-and-Analysis_JR2025636", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.\n\nNVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world. As part of this team, you would be working on projects that will help make our next generation visual computing, automotive, GPU, HPC  systems better. You will get to work on high performance CPU and Memory sub-systems, Next-Gen GPUs , NOC based Interconnect Fabric etc. Make the choice to join us today. Our work spans the full pre-silicon and post-silicon lifecycle: performance models, RTL simulation, emulation platforms, and silicon bringup. We catch bugs early, influence architecture and design decisions, and help ensure that the final product delivers the performance that our customers depend on. If you are passionate about building the hardware that underpins the future of AI and computing, this is where you belong.\n\nWhat You'll Be Doing:\nPartner with System Architecture, Usecase Modeling, Unit Architecture/PV, and Design/Verification teams to define comprehensive performance test plans that reflect real product usecases.\n\nDrive full-chip SoC performance verification across all real engines and subsystems, running realistic concurrent workloads that represent how the product will be used by customers in the field.\n\nExecute performance test plans across the full verification stack: cycle-accurate performance models, RTL simulation, emulation platforms, and silicon, identifying bottlenecks and regressions at each stage.\n\nDebug performance failures through waveform analysis, signal-level queries, trace analysis, and system-level profiling to root-cause issues in the memory subsystem, fabric, or individual engines.\n\nInfluence architecture and microarchitecture decisions by surfacing performance data and trade-off analysis to the design and architecture teams early in the product development cycle.\n\nDevelop and maintain performance workloads, test suites, and infrastructure — including testbench components, performance simulators, analysis scripts, and automated regression flows.\n\nLeverage AI-assisted tools and automation to accelerate repetitive analysis tasks, improve coverage, and free up engineering time for higher-level problem solving. This includes using LLM-based assistants for querying results and specs, AI-driven triage of regressions, and intelligent tooling that improves over time.\n\nDrive methodology improvements to reduce verification turnaround time, improve coverage of representative workloads, and enable earlier performance insight in the product development cycle.\n\nWhat We Need to See:\nB.E./B.Tech or M.S./M.Tech (or equivalent experience) in Electrical Engineering, Computer Science, or a related field.\n\n3+ years of relevant experience in SoC or system-level architecture, performance verification, or hardware validation.\n\nStrong understanding of SoC architecture including GPU and CPU pipelines, memory subsystem design (caches, DRAM controllers, coherency), Network-on-Chip (NoC)/fabric architecture, and high-speed IO interfaces.\n\nHands-on experience with RTL simulation and debug, including waveform-based debug and signal-level querying to isolate performance failures.\n\nSolid programming skills in Python and C/C++; scripting proficiency in Bash/Python for automation and analysis. Exposure to Verilog/SystemVerilog or SystemC/TLM is a strong plus.\n\nStrong debugging, data analysis, and statistical analysis skills — ability to synthesize large volumes of performance data into actionable insights.\n\nExperience with or exposure to pre-silicon performance analysis methodologies, including performance models, cycle-approximate simulators, or emulation platforms.\n\nExcellent communication skills and the ability to work effectively in a large, globally distributed engineering organization.\n\nWays to Stand Out from the Crowd:\nDeep experience with RTL-level performance debug — particularly the ability to formulate precise signal queries and interpret waveforms to root-cause complex system-level interactions.\n\nBackground in system-level performance analysis for GPU, AI accelerators, or high-bandwidth memory subsystems, with knowledge of bottleneck identification across multiple concurrent engines.\n\nDemonstrated use of AI and LLM-based tools (e.g., NVIDIA NIM/NeMo, OpenAI APIs, LangChain, or similar agentic frameworks) to measurably improve your own engineering productivity — whether for automated analysis, natural-language querying of data, intelligent triage, or workflow automation.\n\nExperience building or deploying ML/AI-assisted tooling in an engineering or EDA context (e.g., regression analysis, anomaly detection, test generation, coverage closure).\n\nExpertise in data analysis and visualization — ability to build dashboards and tooling that surface performance trends clearly to both engineering and architecture stakeholders.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "High Speed IO Validation Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-09-23", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/High-Speed-IO-Validation-Engineer_JR2025319", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is widely considered to be one of the world’s most desirable employers in the technology field. We have some of the most forward-thinking and hardworking people in the world working for us. The NVIDIA Silicon Co-Design Group is seeking a versatile engineer to join our High Speed SERDES IO electrical validation team. Your bench is where silicon meets the signal — where every link train, jitter sweep, eye diagram, and protocol corner gets exercised before the part ships. You drive characterization and debug for IO interconnects across silicon, board, firmware, and driver — designing tests that anticipate rack-scale deployment so marginality surfaces at die-and-board scale, never in a rack. Your decisions show up in link margin, BER, power per lane, and the go/no-go calls that gate samples and production.\n\nThis role focuses on industry-leading high-speed interconnects such as PCIe, USB3, Ethernet, and UFS. You will perform bring-up and electrical validation with a strong emphasis on quality, stability, and efficiency. Additionally, you will leverage AI-assisted workflows, automation, and advanced analytics to enhance validation quality, accelerate root cause analysis, and improve engineering efficiency. This position offers the opportunity to make a significant impact in a dynamic, technology-driven environment influencing product lines that span artificial intelligence, consumer graphics, self-driving cars, and more.\n \nWhat You’ll Be Doing:\n\nExecute electrical validation for PCIe, Ethernet, USB3, and UFS interfaces for NVIDIA GPUs, CPUs, and SOCs, ensuring adherence to signal integrity standards.\n\nEngage with cross-functional engineering teams to facilitate the design and development process, leveraging your knowledge of firmware/driver interactions and circuit design.\n\nAnalyze complex HSIO bugs by applying strong debugging techniques and collaborating with various teams for rapid resolution.\n\nDiagnose issues and validate high-speed interfaces using modern lab equipment, including DSOs and BERT, with expert-level proficiency.\n\nDevelop and apply test/debug programs using scripting languages (such as Perl and Python) to perform stress and failure analysis on high-speed interfaces.\n\nInnovate methodologies that leverage AI-assisted workflows and data-driven analytics to enhance debugging efficiency and improve validation quality.\n\nWhat We Need to See:\n\nBS or MS in Electronics Engineering (or equivalent experience) with at least 3 years of relevant experience.\n\nDeep high-speed/SERDES electrical validation and tuning experience, with strong SI and PI fundamentals — S-parameters, eye diagrams, channel margin, crosstalk, return loss, PDN noise, jitter decomposition — and validation experience across silicon and platform boundaries (CoWoS/interposer/substrate, board), translating rack-environment effects into silicon/board characterization.\n\nExpert-level proficiency in electrical validation of PCIe (or similar) protocols, hands-on with lab equipment (DSOs, BERT, protocol analyzers), and scripting skills (Perl, Python) for developing test/debug programs.\n\nProven experience in building AI solutions specifically in the context of electrical and silicon validation, including designing and implementing AI-assisted workflows and automation frameworks to enhance engineering productivity and validation quality.\n\nIf you are energized by challenging problems, real ownership, deep work, and AI-enabled engineering at scale, we’d love to talk to you.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Digital Design, Senior Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-23", "url": "https://careers.synopsys.com/job/bengaluru/digital-design-senior-engineer/44408/101087862608", "is_hardware": true, "platform": "talentbrew", "jd_text": "ASIC Digital Design Engineer, Senior\nWe Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence—from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to help transform the future through continuous technological innovation.\n \nYou Are:\nYou are a Senior ASIC Digital Design Engineer who delivers high-quality RTL for complex PCIe IP. You take a spec or micro-architecture, implement it cleanly, debug it thoroughly, and stand behind the block you own.\nYou have proven digital design experience on SoC or IP, ideally high-speed interfaces. You understand clocks, resets, state machines, pipelines, and synthesizable coding practice. PCIe experience is a strong plus; equivalent protocol or data-path experience is welcome.\nYou work closely with Staff and Principal engineers for your assigned subsystem features. You contribute in reviews, write maintainable RTL, and help verification reproduce and close issues.\n \nWhat You'll Be Doing:\nImplement and own RTL for PCIe blocks and features from micro-architecture and design specs.\nDebug design issues in simulation and, as needed, in formal, emulation, or silicon bring-up support.\nContribute to micro-architecture discussions for your blocks; document design intent and corner cases.\nFollow and help enforce RTL coding standards, lint/CDC hygiene, and review comments to closure.\nWork with verification to define coverage intent, root-cause failures, and deliver fixes on schedule.\nSupport synthesis, timing, and low-power feedback from physical design for your blocks.\nDevelop toward broader subsystem ownership with mentoring from Staff and Principal engineers.\nThe Impact You Will Have:\nDeliver quality, maintainable RTL for silicon-proven PCIe IP.\nImprove execution speed and quality on assigned features\nBe part of Synopsys PCIe controller team delivering high-speed interface IP to leading customers.\nWhat You'll Need:\nBSEE with 5+ years of relevant experience, or MSEE with 3+ years (or equivalent).\nHands-on ASIC RTL design in SystemVerilog on production designs.\nExperience with at least one of: PCIe, CXL, AMBA/AXI, DDR, Ethernet, or other high-speed / on-chip interconnect data paths.\nWorking knowledge of clocking, resets, FSMs, pipelines, and synthesizable design practice.\nFamiliarity with simulation debug; lint, CDC, or synthesis exposure is a plus.\nScripting (Python, TCL, Perl) and AI-assisted design tools are a plus.\nWho You Are:\nA strong RTL engineer with quality mindeset who finishes what they own.\nResponsive in reviews and debug.\nCurious about protocol and micro-architecture", "jd_status": "stored"}, {"title": "Embedded Software Engineer - Security", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-23", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25017848", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n  Software at TI usually refers to embedded software (such as device firmware, device peripheral drivers, software frameworks, algorithms, etc.) and the related software development tools (compilers, simulators, demo software, IDEs, etc.)\n\nSoftware engineers are critical to our “whole-product” offerings. We rely on them to ensure our products are easy to use and customers can get our products up and running quickly. To do that, they partner closely with our product development and demand creation teams on pre-silicon software design and requirements as well as software validation and test activities. They also have an eye for backwards and cross-compatibility and reuse to ensure we are as efficient as possible.\n\nIn addition, software engineers might work directly with customers on any issues that arise and deliver on-going support along with regular software releases, which includes quality assurance and release management activities.\n\nAs a Software Engineer, some of your responsibilities may include:\n\nRequirements definition, design, development, test, integration, and support of embedded software (e.g. operating system software, device drivers, software frameworks, algorithmic libraries etc.) and software development tools (compilers, simulators, IDEs, etc.)\n\nFollowing established software development methodology and practices defined for the business\n\nDeveloping and applying machine learning algorithms to edge applications, which may include using AI coding assistant to develop embedded software\n\nSupporting pre-silicon design and requirements as well as software validation activities\n\nImpacting hardware architecture requirements from a software usage, compatibility, performance, and reuse potential perspectives\n\nUsing the most up to date coding languages, conducting server analysis and reporting infrastructure\n\nCreating and maintaining customer collateral for software products and deliverables\n\nWorking closely with TI teams (silicon, hardware, software teams) and customers as part of the normal software life-cycle\n\nQuality assurance and configuration/release management\n\nASM (Application Specific MCU) SW group has a strong and robust software development team focused on solving some of the most challenging technical problems in automotive and industrial. We believe that hardware and software advancements go hand in hand, and to give our customers seamless, integrated solutions, we need to drive cutting-edge innovations in both. If software is your passion, TI is the right place for you. Our SW strategy rests open source and community focused SW development which allows you to connects you with 1000s of like-minded engineers whose passion is to innovate and share!\n\nWe are seeking an Embedded Security Software Architect to define the software security architecture for our next-generation microcontrollers (MCUs) targeting automotive and industrial markets. In this role, you will bridge the gap between hardware and software, converting silicon capabilities into robust, scalable security software solutions. You will collaborate closely with silicon systems engineers designing custom security IP, work directly with the ROM team to secure the earliest stages of device boot, and serve as a technical mentor to junior security software engineers on the team.\n\nQualifications\nKey Responsibilities \n\nSecurity Software Architecture: Architect, define, and document end-to-end security software solutions for MCU platforms, covering secure boot, secure firmware updates (FOTA), runtime security, and secure execution environments. \n\nCrypto & Key Infrastructure: Define software frameworks for cryptographic key management and manufacturing-time provisioning configurations. \n\nHSM Service Integration: Design the software interfaces and middleware to fully utilize the gamut of boot-time and runtime hardware security services offered by the HSM, including secure storage isolation, hardware-accelerated cryptographic primitives, and secure debug. \n\nCross-Functional Collaboration: Partner with hardware systems engineers to co-define and integrate security hardware IPs (HSM, SHE, Crypto Accelerators). \n\nSilicon Boot Optimization: Work closely with the ROM design and development teams to ensure a flawless, immutable hardware Root of Trust (RoT) and secure first-stage bootloaders. \n\nTechnical Leadership & Mentorship: Act as a key technical guide for the security software engineering team, providing architectural oversight, code reviews, and mentoring junior engineers, without direct supervisory duties. \n\nDomain Standards & Compliance: Drive compliance strategies for rigorous automotive and industrial standards, including ISO 26262 (Functional Safety), ISO/SAE 21434 (Automotive Cybersecurity), and IEC 62443 (Industrial Automation). [1] \n\nQualifications & Requirements \n\nEducation: Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, Computer Science, or equivalent. \n\nExperience: 5-10 years of experience in embedded software development (C/Assembly), with a minimum of 5 years dedicated strictly to embedded software security architecture. \n\nIndustry Domain Knowledge: Proven experience delivering security software for automotive or industrial functional safety/security environments. \n\nHardware/Software Co-Design: Deep technical understanding of microcontroller architectures (e.g., ARM Cortex-M/R, RISC-V), TrustZone, MPUs, and Hardware Security Modules (HSM). \n\nFull-Spectrum HSM Competency: Proven experience implementing both boot-time (e.g., hardware-enforced secure boot, image verification, key injection verification) and runtime (e.g., cryptographic offloading, secure communication stacks like SecOC/TLS, life-cycle state management, runtime tampering/exception handling) services. \n\nCommunication & Mentorship: Exceptional leadership skills with a proven track record of mentoring junior engineers and translating complex silicon hardware concepts into actionable software requirements. \n\nDesired Extras: Hands-on experience with Rust programming for embedded systems, working familiarity with operating systems/RTOS environments such as Linux, Zephyr, FreeRTOS, or ThreadX is a plus.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "RF Device Modeling Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-23", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25017823", "is_hardware": true, "platform": "oracle", "jd_text": "About TI\n\n  Texas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world’s brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000+ customers transform the future today. We’re committed to building a better future – from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. Put your talent to work with us – change the world, love your job!\n\nAbout the Job\n\nJoin TI's elite SPICE Modeling Group and drive cutting-edge semiconductor innovation. You'll extract and optimize compact (SPICE) models for next-generation devices while collaborating with world-class engineers across analog, digital, and mixed-signal design and process technology teams.\n\nLocation: Bangalore, India\n\nWhat You'll Do: \n\nExtract compact models for advanced semiconductor devices (HBT/BJT, RF CMOS, RF Passives, GaN)\n\nPartner with designers and technologists to deploy modeling solutions for breakthrough RF circuit topologies and drive design-technology co-optimization \n\nDevelop innovative model formulations for emerging device technologies\n\nAutomate modeling infrastructure to accelerate technology development\n\nDevelop AI/ML-enhanced models and parameter extraction methodologies\n\nValidate models through comprehensive measurement and analysis\n\nThe person performing this role must be capable to plan effectively, drive schedules, meet critical deadlines on multiple tasks in parallel, lead technical discussions in their area of expertise, and work effectively across organizational boundaries. They must be able to clearly communicate project status and actions. Additionally, they must be able to interface with multiple organizations and work well on a diverse team to accomplish goals.\n\nWhy This Role Matters: \n\nYour modeling expertise will directly impact TI's next-generation products, from automotive to industrial to embedded applications. You will work at the intersection of process, device physics, and circuit design, solving complex challenges and delivering cutting edge solutions.\n\nReady to model the future? Apply today.\n\nQualifications\nMinimum requirements:\n\nPh.D./Masters in Electrical Engineering or related field\n\n5+ years in compact (SPICE) RF modeling for HBT/BJT and CMOS\n\nPreferred qualifications: \n\nExpert-level experience with RF characterization, modeling, and circuit-level validation for s-parameters, noise figure, linearity, IMP3/IP3, and harmonic distortion\n\nStrong understanding of RF test-structures, layouts, and calibration/de-embedding techniques\n\nExperience with models (BSIM, MEXTRAM, HICUM, MVSG-GAN, ASM) and parameter extraction tools (ICCAP, BSIMPROPLUS, MBP, etc.)\n\nDeep understanding of semiconductor physics and circuit analysis\n\nProficiency in EDA tools (Cadence), SPICE simulators (Spectre) and Verilog-A\n\nProgramming skills in MATLAB/Python\n\nStrong data analysis skills with AI/ML expertise and TCAD experience are highly valued\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Applications Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-23", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018020", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\n Our business has very high growth in TI and is in a segment where the market is fast growing. We're searching for applications engineer who have the passion and excitement to grow, innovative, take an active role in product definition, execute the characterization until ramp, and provide post ramp application support to customers.\n\n This role is responsible for application support for DC/DC switching regulators, buck converters. Key responsibilities include:\n\nAnswer customer questions and supporting design-in activities for released products. This includes:\n\nForum and email questions from customers\n\nSchematic and Layout Review of customer application\n\nDebug of customer problems by re-creating issues in our evaluation boards and/or customer boards\n\nOn-site support for customer board as required\n\nDesign EVM and internal evaluation boards to support correlation and evaluation activities of new products\n\nCreate user guides, test procedures and proper release of EVM boards for customer consumption\n\nParticipate in datasheet review to ensure completeness of datasheet being developed by the Systems Engineer\n\nPerform Bench Characterization for switching regulator devices, including bench automation, hardware design \n\nParticipate in new silicon testing from an application perspective to ensure robustness of the product (i.e. destructive testing)\n\nWork with systems engineer to provide support to early design in activities for new products\n\nCreate custom reference designs targeting relevant applications to be used as customer implementation ideas\n\nWrite application notes that explain different use cases, implementation and/or flexibility of our products\n\nQualifications\nMinimum requirements\n\nBachelor's degree in Electrical Engineering, ECE, or related field\n\n2-5 years of relevant experience in power electronics, preferably DC/DC converters\n\nExperience in applications support of analog products like switching regulators\n\nSolid hardware debugging skills\n\nStrong technical background, with the ability to produce high quality technical documentation\n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "PMIC Analog Design Lead", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-23", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018070", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n  \n\nIn this role you will be choosing switching converter architectures for Buck, Boost, Buck-Boost, Inverting Buck-boost and SIMO converters, innovating to meet the best efficiency, transient-performance and IQ at high operational frequencies, to enable our customers to get the best battery life for hand-held electronic devices. Suitable candidates with proven experience in leading switching converter designs, track -record in pushing performance boundaries by way of innovation, an in-depth silicon debug experience should apply. Following are the key activities:\n\n •    Design and deliver high-performance analog power converter circuits — buck, boost, SIMOs, LDOs, and Charge Pumps — meeting aggressive targets for power density, efficiency, and transient performance\n\n •    Define PMIC system architecture and translate complex customer requirements into silicon specifications, driving alignment across design, systems, and applications teams\n\n •    Own technical execution across the full IC design flow: schematic capture, simulation, layout review, post-layout verification, silicon bring-up, and characterization\n\n •    Serve as primary technical owner for one or more converter blocks within multi-block PMIC products\n\n •    Lead cross-functional design reviews and ensure design quality, robustness, and reliability meet program and customer standards\n\n •    Collaborate with internal systems and architecture teams to resolve integration challenges and drive technical closure\n\n •    Mentor and support junior engineers on design methodology, tools, and best practices\n\nQualifications\nMinimum requirements:\n\n•    Bachelor's degree in Electrical Engineering or related field (Master's or PhD preferred)\n\n •    7+ years of analog/mixed-signal IC design experience with deep expertise in power management\n\n •    Strong hands-on experience designing at least one of Buck, boost, SIMO converter in silicon. \n\n •    Expert hands-on experience of LDOs, Charge Pumps, Boot Strap, Switch Cap circuits.\n\n •    Expert command of converter control architectures: Adaptive on Time, Constant on/off Time, peak/valley/average current mode control, control systems and compensations.\n\n •    Hands-on transistor-level design of integrated power FETs, gate drivers, oscillators, bandgap/bias circuits, error amplifiers, and frequency compensation networks\n\n •    High-efficiency design techniques: adaptive dead-time, DVS, multi-phase current balancing, light-load optimization, and IDDQ minimization at high switching frequencies\n\n •    Experience with multi-rail PMIC SoC integration: power sequencing, UVLO, OCP, OTP, and digital interfaces (I2C, SPI, MIPI I3C)\n\n •    Fully proficient and deeply comfortable with standard Power IC design flows end-to-end (Cadence Virtuoso, Spectre)\n\n •    Worst-case corner analysis, top-level and Monte Carlo simulation, and post-layout PEX sign-off\n\n •    Physical layout review: power routing, grounding, signal integrity, thermal management, and die area optimization\n\n •    Working knowledge of Simplis and AMS co-simulation flows required; hands-on expertise is a strong plus\n\n •    Strong knowledge of BCD and/or advanced CMOS process trade-offs for high-performance Power IC design\n\n •    Full-cycle IC design experience: schematic, simulation, layout collaboration, post-layout verification, silicon validation, and characterization\n\n •    Ability to work independently and drive technical decisions with confidence, and multi-task\n\n •    Strong written and verbal communication skills\n\n  \n\nPreferred qualifications:\n\n•    Experience of designing PMICs for consumer electronics (mobile, laptops, wearables)\n\n •    Experience in customer-facing technical alignment and specification negotiation\n\n •    Prior experience as a technical lead or design owner on a multi-block PMIC products for consumer electronics (mobile, laptops, wearables)\n\n •    Demonstrated ability to drive customer and cross-functional technical discussions with authority and ownership\n\n •    Proven track record of mentoring engineers through complex design challenges\n\n •    Ability to manage and personally execute multiple concurrent design tasks on aggressive schedules with high autonomy\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "PMIC Analog Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-23", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018071", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n  \n\nWe are looking for a highly skilled and passionate Analog Designer, with PMIC experience preferred, to partner with senior technical leads to execute PMIC programs, otaking primary ownership of assigned blocks/sub-systems while receiving architectural guidance on system-level decisions. This is a deeply technical, hands-on role — you will be doing circuit design, participating in layout reviews, PEX simulations, analysis leading to architecture decisions, and collaborating with cross-functional experts to deliver successful IPs and Products. Following are the key responsibilities:\n\n •    Design and deliver high-performance analog circuits and blocks needed for power converter circuits — buck, boost, LDO, and charge pump — meeting aggressive targets for power performance, efficiency, and transients.\n\n •    Contribute towards PMIC system architecture development and execute block-level designs against challenging performance, power, and area specifications.\n\n •    Own technical execution across the full IC design flow: schematic capture, simulation, layout review, post-layout verification, silicon bring-up, and characterization\n\n •    Serve as primary technical owner for one or more complex blocks, sub-system and converters (with some guidance & support) within multi-block PMIC products\n\n •    Ensure design quality, robustness, and reliability through in-depth technical reviews \n\n •    Collaborate with internal systems and architecture teams to resolve integration challenges and drive technical closure\n\n •    Mentor and support junior engineers on design methodology, tools, and best practices\n\nQualifications\nMinimum requirements:\n\n•    Bachelor's degree in Electrical Engineering or related field (Master's or PhD preferred)\n\n •    4+ years of analog/mixed-signal IC design experience with strong analog fundamentals and design understanding for standard blocks including BGRs, V2Is, Amplifiers, Comparators, Level shifters, Oscillators\n\n •    Experience with high-voltage circuit designs and high speed level shifters \n\n •    Familiarity with SOA (Safe Operating Area) & Reliability, Aging sims\n\n •    Strong understanding of mismatch effects and device noise, with experience in auto-zeroing, chopping, and statistical analysis\n\n •    Good understanding of Control Systems fundamentals, compensation, large signal analysis etc.\n\n •    Fully proficient and deeply comfortable with standard Power IC design flows end-to-end (Cadence Virtuoso, Spectre)\n\n •    Worst-case corner analysis, top-level and Monte Carlo simulation, and post-layout PEX sign-off\n\n •    Strong knowledge of BCD and/or advanced CMOS process trade-offs for high-performance Power IC design\n\n •    Ability to work independently and drive design related technical decisions with confidence and provide predictable development schedule for blocks & sub-systems based on the specifications, with high quality.\n\n •    Should be able to independently explore multiple options and come up with optimum architectures of blocks for given specs and execute with high quality while adhering to the schedules.\n\n •    Strong written and verbal communication skills\n\n  \n\nPreferred qualifications:\n\n•    Experience in designing blocks for PMICs in consumer electronics (mobile, laptops, wearables)\n\n •    Understanding of one or more converter control architectures: Adaptive/Constant On/Off Time, peak/valley/average current mode control\n\n •    Hands-on transistor-level design of integrated power FETs, gate drivers, oscillators, bandgap/bias circuits, error amplifiers, and frequency compensation networks\n\n •    High-efficiency design techniques with focus on performance while minimizing power and area.\n\n •    Working familiarity with multi-rail PMIC SoC integration: power sequencing, UVLO, OCP, OTP, and digital interfaces (I2C, SPI, MIPI I3C)\n\n •    Experience in customer-facing technical alignment and specification negotiation\n\n •    Physical layout understanding and key aspects including power routing, grounding, signal integrity, thermal management, and die area optimization\n\n •    Exposure to Simplis, AMS, or equivalent simulation tools (good to have)\n\n •    Experience of full / partial design ownership of Switching Converters, LDOs\n\n •    Full-cycle IC design experience: schematic, simulation, layout collaboration, post-layout verification, silicon validation, and characterization\n\n •    Ability to independently manage and execute multiple design tasks in parallel on aggressive schedules\n\n •    Mentoring Junior members and New College Graduates in the team\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Senior Test Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-23", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018091", "is_hardware": true, "platform": "oracle", "jd_text": "Who are we and what do we do?\n\nThe Advanced Circuits and Power Solutions business is known for delivering industry-leading custom IC system solutions, including display and touch power products, charger power products, camera PMICs, power path devices, sensing devices, and high-performance communication interface products. Our products integrate precision signal chains and highly efficient power components into ultra-small form factors, enabling TI’s best-in-class customers to translate their ideas into high-value products that revolutionize the personal electronics market.\n\nIn this team, you will work with and learn from incredibly talented technical leaders who have influenced TI’s technology, productivity, and way of working in creative and impactful ways. You will directly interact with one of TI’s most valued, high-volume customers through intense technical reviews and architecture discussions!\n\nBy enabling designs that are highly impactful to TI revenue and working with a critical customer on a versatile set of products, you will find yourself on an accelerated career path.\n\nAbout the job\n\nIf you are looking to join an ingenious, vigorous & ambitious team that consistently delivers groundbreaking technologies into the custom mobile electronics world, here is an opportunity for you!\n\nWhat will you be doing in this role?\n\nStrategic Leadership & Industry Authority\n\nTechnology Roadmap & Vision: Own the strategic direction of ATE ecosystem in TI while collaborating with AT sites, establishing TI's test methodologies , quality benchmarks and technical judgments that form the foundation for TI's next generation of products.\n\nIndustry & Customer Influence: Serve as TI's technical authority in high-stakes customer engagements and partner discussions, taking complex decisions and communicating with authority and clarity.\n\nDesign Governance & Quality Authority: Act as the quality authority for the data analytics, driving yield improvements and setting the quality standards that projects across TI measure themselves against.\n\nCross-Functional Orchestration: Orchestrate deep collaboration with AT Vendors, TI's IT and data infrastructure, and IP teams to eliminate flow bottlenecks, align execution priorities, and raise the implementation bar across all TI projects.\n\nChange the world. Love your job.\n\n Are you looking to grow your career in production testing at one of the leading semiconductor companies in the world? At Texas Instruments (TI) a Production Test Engineer ensures manufactured components and assembled products meet company standards and objectives. You'll develop and implement testing and evaluation methods and create test plans based on production specifications and requirements. You'll use your talent to perform testing and compiling and analyzing data for review and identification of manufacturing and production issues.\n\nResponsibilities include:\n\nUtilize analog circuit analysis and Automated Test Equipment debug knowledge to troubleshoot test, quality, and device performance issues\n\nDriving decisions on test strategy: optimizing trade-offs between test cost, coverage / performance and quality\n\nDevelop test processes, fixtures and software for automated test equipment for optimized production use\n\nEstablish and influence next-generation test solutions that help achieve the lowest obtainable costs on future products\n\nFacilitate and support new multi-factory manufacturing test and assembly flows\n\nAnalyze test solution robustness through correlated performance and sameness verification techniques\n\nPerform yield analysis and work with fabs for yield improvements where applicable\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in electrical engineering, electrical & computer engineering, mathematics, physics or a related field of study\n\n12+ years' work related experience\n\nATE expertise. Experience with ETS88, ETS800, Advantest V93K / EXAscale and Handlers is highly desirable\n\nExpertise in Data Analytics and Yield analysis\n\nProbe card hardware and circuit design experience\n\nSoftware development experience\n\nExcellent debugging skills and strong VLSI fundamentals\n\nPreferred qualifications:\n\nKnowledge of production data analysis for both Engineering and Mass Production\n\nStrong verbal and written communication skills\n\nDemonstrated strong analytical, critical thinking, and problem solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbility to work effectively in an interrupt-driven, fast-paced and rapidly changing environment\n\nDemonstrated ability to build strong, influential relationships\n\nProblem solving skills, including meticulous attention to details\n\nAbility to communicate effectively across functional boundaries and with upper management\n\nAbility to work in stressful situations and arrive at creative and effective solutions\n\nAbility to think strategically\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Senior Analog Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-23", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018100", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\n This is a great opportunity to be part of an established team that's continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electronics, mobile computing and communications.\n\nWho are we and what do we do?\n\nThe Advanced Circuits and Power Solutions business is known for delivering industry-leading custom IC system solutions, including display and touch power products, charger power products, camera PMICs, power path devices, sensing devices, and high-performance communication interface products. Our products integrate precision signal chains and highly efficient power components into ultra-small form factors, enabling TI’s best-in-class customers to translate their ideas into high-value products that revolutionize the personal electronics market.\n\nIn this team, you will work with and learn from incredibly talented technical leaders who have influenced TI’s technology, productivity, and way of working in creative and impactful ways. You will directly interact with one of TI’s most valued, high-volume customers through intense technical reviews and architecture discussions!\n\nBy enabling designs that are highly impactful to TI revenue and working with a critical customer on a versatile set of products, you will find yourself on an accelerated career path.\n\nAbout the job\n\nIf you are looking to join an ingenious, vigorous & ambitious team that consistently delivers groundbreaking technologies into the custom mobile electronics world, here is an opportunity for you!\n\nIn this role, responsibilities may include:\n\nParticipate in the review and sign-off of designs developed within the team as well as other products developed across TI.\n\nRepresent TI's technical leadership in front of leading customers.\n\nDrive TI's technology roadmap while collaborating with Process, Packaging, EDA, and other stakeholders within and outside TI.\n\nDefine and drive industry-leading best practices within TI.\n\nAct as an Analog Chip/Sub-section/IP architect and designer, with complete ownership and responsibility from definition to release and manufacturing.\n\nDirect, guide, and participate in research or technical design functions responsible for designing, developing, modifying, and evaluating electronic parts, components, and integrated circuits for a variety of applications.\n\nProvide design guidance to team members as needed, developing schedules and monitoring progress throughout the project.\n\nEvaluate intermediate and final results of projects during the design phase and silicon evaluation to ensure the accomplishment of technical objectives.\n\nWork with and provide guidance to physical designers, and monitor the progress of IC layout.\n\nCollaborate with Design Verification teams during the pre-PG phase of a project to ensure completion of all technical tasks before PG.\n\nWork with systems engineers and application engineers, assisting in the definition of products to meet customer needs.\n\nCollaborate with validation, product engineering, and test engineering teams to enable a successful transfer to production.\n\nInterface and lead discussions with customers and/or TI field sales/field applications teams to understand customer designs and problems, and to provide support as required.\n\nActively participate in hiring, developing, and evaluating personnel to ensure efficient operation of the organization and the growth of individuals into leaders.\n\nQualifications\nMinimum requirements:\n\nMasters OR Bachelor's degree in Electrical Engineering\n\n12 years of relevant experience\n\nOrganizational Skills: Ability to work well with internal cross functional teams. Must successfully and appropriately interface with external customers. Project management, time management, multi-tasking, problem solving and communication (written and oral) are important skills in this role. Must be able to manage assigned tasks with minimal supervision.\n\nTeam and People Skills: Candidate must be team oriented and must be able to work with TI-internal and external groups (systems, test, sales, marketing, customers, etc.) to resolve issues and generate business success. The ability to work well with others and to perform in a team environment is essential.\n\nProjects and Deliverables: The main deliverable is the timely release of meticulously analysed and simulated IC designs or sub-sections of designs for custom designs with tight schedules. These designs should lead to cost-effective, high quality, bug-free products that fully meet our customer’s end-system requirements.\n\nPreferred qualifications:\n\nCustomer Interaction: Active involvement with customers, with a demonstrated sense of ownership when collaborating with customers and all product development team members (including design, layout, systems, verification, validation, test, and program management).\n\nArchitectural Expertise: Proficiency in IC system partitioning, architectural tradeoff analysis, block-level topology selection, hand analysis, and IC transistor-level implementation.\n\nCAD & Simulation: Expert-level schematic generation and simulation using modern CAD tools (Cadence toolset), including Spectre, Simplis, Matlab, and AMS.\n\nAdvanced Analysis: Expertise in worst-case identification, top-level simulation, Monte Carlo analysis, and simulation data analysis.\n\nSystem Integration: Strong system-level understanding and analysis, with the ability to translate requirements into IC-level specifications.\n\nPhysical Design: Experience in physical layout management, including signal grounding, routing tradeoffs, die area optimization, post-layout parasitic extraction, and simulation to verify all IC-level performance metrics.\n\nVerification: Proficiency in top-level verification, block-level modeling, and top-level simulation.\n\nDevice Physics: Knowledge of device physics and process technology tradeoffs applicable to Power IC design.\n\nProject Execution: Proven ability to budget time, manage schedules, and complete complex IC design tasks on time with a meticulous approach to ensure high-quality results.\n\nDesign for Manufacturing (DFM): Ability to account for system-level specification limitations, testability, debug, characterization, production, and yield targets during the IC design phase.\n\nInterpersonal & Leadership:\n\nAbility to foster a highly creative, interesting, productive, and fun working environment for colleagues and customers.\n\nAbility to establish strong relationships with key stakeholders, both internally and externally.\n\nStrong verbal and written communication, interpersonal, analytical, and problem-solving skills.\n\nAbility to take initiative, drive for results, and quickly ramp up on new systems and processes.\n\nStrong time management skills to ensure on-time project delivery and effective collaboration across different functions\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Test Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-23", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018161", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n This is a unique opportunity to be part of a team that drives testing of low cost microcontroller devices going into markets with significant growth potential. The ideal candidate would have a background that includes probe and final test development.\n\nResponsibilities include:\n\nWork with design team to understand design specifications\n\nGenerate test plan, create test and char program, design ATE hardware interface boards\n\nDebug characterizing silicon on ATE, correlate results with bench data\n\nAnalyze silicon results, supporting failure analysis tasks\n\nPerform statistical analysis of yield fallout, debug and fix yield issues; optimize test time\n\nWork with production team to release products to volume production\n\nTest strategy definition and implementation for new DCDC converter products\n\nATE (Automatic Test Equipment) test hardware and software\n\nSilicon qualification& characterization including qual hardware development\n\nComprehensive device debugging, design validation and failure analysis\n\nDrive for robust and cost effective test solutions while being accountable for product quality\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in Electrical Engineering\n\n3 to 5 years of relevant experience\n\nATE experience on Teradyne J750 or Advantest V93K or Eagle platform. Having J750 experience is a differentiator\n\nCharacterization test program and hardware development experience, Production test program and hardware development experience\n\nProgram release to Manufacturing sites, Post release activities like Yield improvement, Test time reduction, Coverage analysis.\n\nGood technical knowledge of electronic devices and circuits, Analog test techniques, SCAN & PBIST\n\nData analysis skills using Spotfire, dataPower or equivalent tool based on STDF, Guardband analysis & Limit setting\n\nExperienced with various lab equipment such as scopes, power supplies, sourcemeters, loads etc.\n\nExperience with product engineering activities such as yield improvement and test time reduction\n\nStrong understanding of the IC product development process, from concept to volume production\n\nPreferred qualifications:\n\nMixed signal test techniques and experience with developing mixed-signal tests on TI roadmap testers\n\nExperienced with test program and hardware offload to TI offshore manufacturing sites\n\nProficiency in programming/scripting in C++, Python, C#\n\nRevision control tools experience : Subversion, Git\n\nDemonstrated strong analytical and problem solving skills\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nStrong time management skills that enable on-time project delivery\n\nDemonstrated ability to build strong, influential relationships\n\nAbility to work effectively in a fast-paced and rapidly changing environment\n\nAbility to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Principal Verification Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-09-23", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506067", "is_hardware": true, "platform": "oracle", "jd_text": "Job Description – ASIC/SoC Verification Engineer\n\nWe are seeking an experienced Principal ASIC/SoC Verification Engineer to join our dynamic and fast‑paced engineering team. In this role, you will be responsible for ensuring the functional correctness, robustness, and overall quality of our cutting‑edge semiconductor and SoC designs. If you thrive in a collaborative environment and enjoy solving complex technical challenges, this opportunity is an excellent fit.\n\n   #LI-VS1\n\nResponsibilities\nResponsibilities\n1. Verification Planning and Execution\nDevelop and execute comprehensive SoC/IP‑level verification plans aligned with design specifications and project goals.\nDrive verification closure through functional, code, and assertion coverage, ensuring high‑quality deliverables.\nApply industry‑standard ASIC/SoC verification techniques including test planning, testbench creation, constrained‑random and directed stimulus, assertions, and coverage‑driven verification.\nPerform SoC integration verification, validating interactions across subsystems, interfaces, and power/performance domains.\n2. Testbench & Environment Development\nArchitect, develop, and enhance SystemVerilog UVM/OVM‑based testbenches for IP and SoC‑level verification.\nBuild and integrate reusable Verification IP (VIP) and scalable verification components.\nCollaborate with internal teams and third‑party VIP providers to ensure seamless integration and compliance.\nDevelop checkers, scoreboards, monitors, and coverage models to support robust verification.\n3. Methodology, Flows & Best Practices\nDemonstrate strong understanding of ASIC/SoC design and verification methodologies, including constraint‑random verification and object‑oriented programming principles.\nContribute to verification methodology improvements, automation, and flow optimization.\nEnsure adherence to best practices in UVM architecture, reuse, and maintainability.\n4. Advanced Verification Skills\nPerform Gate‑Level Simulation (GLS) including SDF annotation, timing verification, and debug of post‑synthesis/post‑layout issues.\nExecute power‑aware verification using UPF/CPF, validating power modes, isolation, retention, and sequencing.\nDebug complex SoC‑level issues involving multiple clock domains, resets, and power states.\nApply formal verification techniques where appropriate to complement simulation‑based verification.\n5. Technical Skills\nStrong proficiency in SystemVerilog (UVM/OVM) and scripting languages such as Python, Perl, Tcl, C/C++, and Verilog PLI.\nFamiliarity with standard protocols and interfaces (e.g., I2C, SPI, UART, AXI/AHB/APB).\nExperience with simulation, debug, and coverage tools from major EDA vendors (Synopsys, Cadence, Siemens).\nKnowledge of CI/regression automation, version control, and workflow tools is a plus.\n6. Collaboration & Communication\nWork effectively with design, architecture, DV, validation, and firmware teams to drive verification to completion.\nCommunicate technical concepts clearly through documentation, reviews, and cross‑functional discussions.\nDemonstrate initiative, strong analytical problem‑solving skills, and adaptability in a diverse team environment.\n#LI-VS1\n\nQualifications\nRequired Qualifications\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.\n10 Years of experience in SoC/IP verification,.\nStrong expertise in SystemVerilog, UVM, and advanced verification methodologies.\nHands-on experience with ARM-based SoC architectures, AMBA protocols (AXI/AHB/APB), and system-level interactions.\nProven ability to build reusable, scalable testbench architectures.\nSolid understanding of test planning, coverage-driven verification, and verification metrics.\nExperience with GLS, timing verification, and debug.\nKnowledge of power-aware verification (UPF/CPF).\nStrong scripting and automation skills (Python, Perl, Shell, Make, etc.).\nExposure to AI/ML techniques applied to verification (e.g., intelligent stimulus generation, failure triage, coverage optimization).\nExcellent problem-solving, debugging, and communication skills.\n#LI-VS1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Senior Principal Engineer, DFT", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-23", "url": "https://careers.arm.com/job/bengaluru/senior-principal-engineer-dft/33099/101043784080", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview:\nArm's Central Engineering DFT Architecture and Methodology team defines the future of Design-for-Test across Arm's CPUs, GPUs, System IP, AI accelerators and next-generation SoCs. The team develops DFT architectures, methodologies and implementation flows that enable high-quality, scalable test solutions across soft IP, hard macros, test chips and complex multi-die SoCs.\nWorking at the forefront of semiconductor innovation, you will collaborate with product teams, system architects, design engineers and EDA vendors to shape DFT technologies several years ahead of production. This is a highly technical architecture role with significant influence across Arm and the broader semiconductor ecosystem. \nResponsibilities:\nAs a Senior Principal DFT Architect/Engineer, you will:\nDefine DFT architecture for next-generation Arm IPs and SoCs, including emerging AI and hyperscale computing products.\nDevelop and drive scalable DFT methodologies and implementation flows used across multiple Arm engineering organizations.\nEvaluate emerging DFT technologies and lead technical investigations to solve future product challenges.\nCollaborate with architecture, implementation, verification and physical design teams to define robust DFT solutions.\nWork closely with EDA vendors to influence product roadmaps, evaluate new capabilities and drive adoption of new technologies.\nProduce architecture specifications, methodology documentation and deployment guidance.\nProvide technical leadership and mentorship across project teams.\nSupport strategic engagements with customers, ASIC partners and industry standards bodies where appropriate.\nContribute to technical publications, patents and industry conferences.\nRequired Skills and Experience :\nPrincipal or Senior Principal level engineer with extensive experience in Design-for-Test architecture and implementation.\nStrong understanding of modern SoC DFT methodologies including:Scan architecture and scan compression\nATPG and fault simulation\nAt-speed testing\nMemory BIST\nLogic BIST\nJTAG / IEEE 1149.1\nIJTAG / IEEE 1687\nDFT verification and debug\n\nExperience developing reusable DFT methodologies or automation rather than project-specific solutions.\nExperience evaluating and deploying Siemens Tessent, Synopsys and/or Cadence DFT solutions.\nStrong scripting skills (Perl, Tcl and/or Python) together with Linux/Unix expertise.\nExcellent problem-solving and analytical skills.\nStrong communication skills with the ability to influence technical direction across multiple engineering teams.\nDegree (or equivalent) in Electronic Engineering, Computer Engineering or related discipline.\n“Nice To Have” Skills and Experience :\nExperience defining DFT architecture for large-scale SoCs.\nExperience with heterogeneous compute systems, AI accelerators or hyperscale computing products.\nKnowledge of IEEE 1500, IEEE 1838 and advanced IJTAG methodologies.\nExperience with Streaming Scan Network (SSN) and chiplet/3DIC architectures.\nFamiliarity with silicon bring-up and production test.\nExperience working directly with EDA vendors on new technology development.\nKnowledge of synthesis, STA and physical implementation considerations for DFT.\nExperience with formal verification and simulation methodologies.\nRecord of patents, conference publications or contributions to industry standards.\n \n\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Engineer- Multi-Physics Sign-off (Timing, PDN & Thermal)", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-23", "url": "https://careers.arm.com/job/bengaluru/engineer-multi-physics-sign-off-timing-pdn-and-thermal/33099/101024460816", "is_hardware": true, "platform": "talentbrew", "jd_text": "We are seeking a CAD & Methodology Engineer to develop, enable, and support 3DIC and 2.5D physical design and signoff methodologies for advanced multi-die systems. This role focuses on building robust, scalable, and production-ready flows spanning timing, power, IR/EM, ESD, thermal, CFD/FEM, and multiphysics analysis, in close collaboration with physical design, package, PI, reliability, and EDA vendor teams.\nThe ideal candidate brings hands-on understanding of advanced-node implementation and signoff, combined with strong scripting, flow ownership, and cross-team collaboration skills.\n \nResponsibilities:\nThis is a hand-on role for delivering tool-flow-methodology and automation.\n3DIC / 2.5D CAD Flow Development\nDevelop, maintain, and qualify CAD flows for 3DIC and 2.5D designs, including chiplets, interposers, and advanced packaging technologies\nEnable end-to-end implementation and signoff methodologies covering floor planning through tapeout\nSupport die-to-die connectivity, bump/TSV-aware flows, and cross-die constraint management\nWork with design and packaging teams to integrate package-aware and system-aware considerations into PD flows\nTiming, Power, and Reliability Methodology\nDevelop and support STA methodologies for multi-die designs, including cross-die timing, constraints, and closure strategies\nEnable power analysis, IR drop, and EM signoff flows for 2.5D and 3DIC systems\nDefine guidelines for ESD verification in advanced packaging contexts\nAssist with tool qualification, correlation, and signoff criteria definition\nThermal, CFD, and Multiphysics Methodology\nDevelop and support thermal analysis methodologies for 3DIC and 2.5D designs\nEnable CFD/FEM-based thermal analysis to model conduction, convection, and airflow effects from die to package to system\nSupport coupled electro-thermal and Multiphysics flows, integrating power, thermal, and reliability analysis\nPartner with design and package teams to incorporate thermal considerations early in the design flow\nAutomation, Infrastructure, and Enablement\nBuild and maintain automation, scripts, and checks to improve flow robustness, runtime, and usability\nDevelop documentation, examples, and training materials for design teams\nDebug flow issues and provide CAD support during active design cycles\nDrive continuous improvement based on user feedback and silicon takeaways\nTeamwork and Vendor Engagement\nWork closely with physical design, package, PI, reliability, and silicon teams\nCollaborate with EDA vendors to evaluate new tools, features, and roadmap items\nSupport tool upgrades, regressions, and flow migrations across projects\nRequired Skills and Experience :\nVLSI Knowledge MUST\nMinimum 5+ years of System Level experience \nStrong hands-on experience with 3DIC and/or 2.5D designs\nFamiliarity with chiplet-based designs, system-in-package designs and tradeoffs involved\n“Nice To Have” Skills and Experience :\nExperience with TSVs, micro-bumps, interposers, and advanced packaging technologies\nFamiliarity with industry-standard EDA tools for 3DIC implementation and signoff\nCadence Integrity 3D-IC\nSynopsys 3DIC Compiler\nCadence Celsius Thermal Solver\nAnsys Icepak\nAnsys RHSC-ET\n \n#LI-BB1\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Engineer - CAD SW", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-23", "url": "https://careers.arm.com/job/bengaluru/engineer-cad-sw/33099/101024460784", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview:\nArm is leading the vision to unlock a broad ecosystem of silicon required for AI, Data centers, mobile, compute and IoT. As a member of Solution engineering team you will be delivering optimized design flow, methodology, and full CAD solution for industry leading compute subsystem and SoCs. We are seeking outstanding expertise in algorithms and automation specifically tailored for meticulous optimization of power, performance, area, signoff and silicon quality. The role brings opportunity to collaborate with foundry, EDA and ecosystem partners in 3nm/2nm technodes and multi-die.\nThe Software Engineer is responsible for designing, developing, testing, deploying, and maintaining reliable and scalable software solutions. The role involves working with cross-functional teams to translate requirements into high-quality software while following engineering best practices.\nResponsibilities:\nDesign, develop, test, and maintain software applications and tools.\nWrite clean, maintainable, efficient, and well-documented code.\nDevelop automation to improve engineering productivity and reduce manual processes.\nDebug complex software, system, and performance issues.\nParticipate in code reviews and contribute to coding standards and best practices.\nDesign and maintain APIs, databases, command-line tools, and supporting infrastructure as required.\nBuild automated unit, integration, and regression tests.\nUse Git and established CI/CD workflows for software development and delivery.\nMonitor software reliability and improve performance, scalability, and robustness.\nCollaborate with engineers, architects, product teams, and other stakeholders.\nEvaluate new technologies and improve existing software architecture and development processes.\nCreate and maintain technical documentation.\nRequired Skills and Experience :\nStrong programming skills in one or more languages such as Python, TCL, C/C++.\nGood understanding of data structures, algorithms, object-oriented programming, and software design principles.\nExperience with Linux/Unix, Git, debugging, scripting, and automation.\nUnderstanding of databases such as PostgreSQL, MySQL, or SQLite.\nFamiliarity with REST APIs, distributed systems, CI/CD, containers.\nKnowledge of software testing methodologies and development lifecycle practices.\n“Nice To Have” Skills and Experience :\nWorking knowledge of agentic workflow models from OpenAI and Claude. Experience with RTL synthesis tools, process technology design rules, STA, and power estimation and analysis methodologies. Prior experience in SoC design, CAD engineering, or related areas, with a focus on physical design and signoff, is highly desirable.\n \n#LI-BB1\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Engineer- CAD SW", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-23", "url": "https://careers.arm.com/job/bengaluru/senior-engineer-cad-sw/33099/101024454880", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview:\nArm is leading the vision to unlock a broad ecosystem of silicon required for AI, Data centers, mobile, compute and IoT. As a member of Solution engineering team you will be delivering optimized design flow, methodology, and full CAD solution for industry leading compute subsystem and SoCs. We are seeking outstanding expertise in algorithms and automation specifically tailored for meticulous optimization of power, performance, area, signoff and silicon quality. The role brings opportunity to collaborate with foundry, EDA and ecosystem partners in 3nm/2nm technodes and multi-die.\nThe Software Engineer is responsible for designing, developing, testing, deploying, and maintaining reliable and scalable software solutions. The role involves working with cross-functional teams to translate requirements into high-quality software while following engineering best practices.\nResponsibilities:\nDesign, develop, test, and maintain software applications and tools.\nWrite clean, maintainable, efficient, and well-documented code.\nDevelop automation to improve engineering productivity and reduce manual processes.\nDebug complex software, system, and performance issues.\nParticipate in code reviews and contribute to coding standards and best practices.\nDesign and maintain APIs, databases, command-line tools, and supporting infrastructure as required.\nBuild automated unit, integration, and regression tests.\nUse Git and established CI/CD workflows for software development and delivery.\nMonitor software reliability and improve performance, scalability, and robustness.\nCollaborate with engineers, architects, product teams, and other stakeholders.\nEvaluate new technologies and improve existing software architecture and development processes.\nCreate and maintain technical documentation.\nRequired Skills and Experience :\nStrong programming skills in one or more languages such as Python, TCL, C/C++.\nGood understanding of data structures, algorithms, object-oriented programming, and software design principles.\nExperience with Linux/Unix, Git, debugging, scripting, and automation.\nUnderstanding of databases such as PostgreSQL, MySQL, or SQLite.\nFamiliarity with REST APIs, distributed systems, CI/CD, containers.\nKnowledge of software testing methodologies and development lifecycle practices.\n“Nice To Have” Skills and Experience :\nWorking knowledge of agentic workflow models from OpenAI and Claude. Experience with RTL synthesis tools, process technology design rules, STA, and power estimation and analysis methodologies. Prior experience in SoC design, CAD engineering, or related areas, with a focus on physical design and signoff, is highly desirable.\n#LI-BB1\n \nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Engineer- Tech PNR methodology", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-23", "url": "https://careers.arm.com/job/bengaluru/engineer-tech-pnr-methodology/33099/101024454672", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview:\nArm is leading the vision to unlock a broad ecosystem of silicon required for AI, Data centers, mobile, compute and IoT. As a member of Solution engineering, you will be joining a team enabling the latest semiconductor process nodes. This role requires study of advanced node processes, to enable teams to deliver a flow that achieves the best performance at the lowest power and area cost on advanced CPU designs.\nThe suitable candidate has a strong understanding of EDA vendor tool and design flows and technology files as well as process design rule manuals, with experience developing, and optimizing design flows on advanced process nodes.\n \nResponsibilities:\nDrive EDA technology enablement from early technology development through production readiness\nDevelop, and desply design methodologies, flows, scripts, and automation supporting advanced node processes.\nDevelop strategy and roll-out for EDA tools roadmap and features.\nThe suitable candidate will be able to analyze the requirements, define and develop CAD solution including external EDA tools integration.\nCollaborate with EDA vendors to debug tool issues, evaluate new capabilities, and influence tool and methodology improvements.\nAbility to lead a product implementation, working closely with internal design teams, foundry and partners.\nRequired Skills and Experience :\nStrong experience and deep understanding of Floorplan, PDN, Timing, Power, and Physical design.\nOutstanding expertise in EDA tool-flows, PPA analysis and designing solutions\nExperience with architecting and developing VLSI CAD Software and automation.\nStrong coding proficiency in languages Python, C, Tcl. Proficiency with version control systems like git, distributed processing, and disk management.\nAbility to work with evolving problem statements and solutions. Excellent interpersonal skills, communication, team spirit and effective collaboration with multi-functional teams.\n \n“Nice To Have” Skills and Experience :\nExperience with multi-die SoC design flows. Experience with Data analytics, dashboards and metrics desired.\n #LI-BB1\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Staff ATE Test Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-23", "url": "https://careers.arm.com/job/bengaluru/staff-ate-test-engineer/33099/101022865808", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview: \n \nThis is a great opportunity to join Arm's  Solutions Test Team working with emerging process technologies and the latest offerings across Cloud, Infra, IoT, Auto segments! The test team works closely with IP, SoC Design, Product and Systems teams throughout the company, to represent test engineering and drive test capability development within Arm. You will play a key role in preparing Arm and our partners for how to address production, Characterization challenges in areas like 2.5D/3DIC and sub-3nm nodes. The role requires execution oriented engineering focus across areas such as: Test Strategy, ATE SW/HW planning/execution,  bring-up/characterization/production, and test data capture/correctness/reporting!\nResponsibilities:\nDrive test strategy development for upcoming projects\nDevelop/implement ATE production/characterization plan\nOwns ATE test program development, including:\nTest method source code for test types (ATPG/Scan, MBIST, HSIO, Sensors, Functional, etc)\nTest flow development, including implementation of binning strategy\nTest program revision control framework (ie SVN, git, etc)\nPattern conversion flow\nGuide ATE test HW development (in collaboration with vendors), including wafer probe card, loadboard/socket, and thermal control interface\nRequired Skills and Experience:\nDemonstrated knowledge of ATE (Advantest EXAScale-SMT8) test program development, including areas of test method/flow development, test bring-up, characterization, debug, and production\nKnowledge in areas of DFT (Scan, MBIST, PHY BIST, etc), fabrication process, product qualification.\nExperience in end-to-end project execution, from architecture to production release\nStrong project ownership and ability to lead external vendors and drive multi-functional teams\n10+ years of demonstrated experience in semiconductor product development, including bring-up, characterization, and production\nDegree or equivalent experience with experience in Electronic Engineering or Computer Engineering\n“Nice To Have” Experience:\nUnix, C++, Python, SmarTest, SmartRDI\nData analysis techniques and tools, such as excel, Tableau, JMP, YieldExplorer, etc\nExperience with:\nIEEE 1149, 1500, 1687, 1838\nStreaming Scan Network (SSN), scan diagnostics, failure analysis techniques\nSTIL pattern conversion techiques/tools\nKnowledge of active thermal management\nPersonal Skills:\nAbility to work both collaboratively on a team and independently\nInnovative mentality\nResults-driven mindset and excellent time management skills with an ability to multi-task\nAn upbeat approach to working on exciting projects on the forefront of technology\nCommunicate effectively across teams and sites in different geographies and time zones\nGood analytical and debug skills with a “figure it out” mentality\n10x Mindset at Arm\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Read more about how we bring the 10x mindset to life on the Arm blog.\n\n #LI-SC2 \nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Applications Engineer (Functional Verification)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-23", "url": "https://careers.synopsys.com/job/bengaluru/senior-applications-engineer-functional-verification/44408/101040901232", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nYou have spent enough time in digital design or verification to know that the real work starts when something breaks in a way the documentation never mentioned. Debugging is not just a skill for you, it is how you think. You follow the signal, trace the logic, and figure out what actually happened versus what should have happened, and you can explain the difference to someone who was not there when it broke.\nWorking with customers does not intimidate you. You have learned that the best support is not about having every answer immediately, it is about asking the right questions, reproducing the issue, and staying with it until it makes sense. You know your way around Verilog or VHDL well enough to read someone else's RTL and spot where the problem might be hiding.\nYou are comfortable working across time zones with engineers in different locations, and you understand that being remote does not mean working in a vacuum. At Synopsys, you will be part of a global team supporting EDA tools that matter, and the work you do will directly affect how customers deploy and trust the products we build.\n\nWhat You’ll Be Doing:\nDrive customer deployments of VCS/Verdi simulation/debug technology, working closely with product teams and R&D to ensure successful adoption and integration.  \nDiagnose and troubleshoot complex technical issues in verification flows, utilizing good product knowledge and analytical skills.\n Collaborate with global domain experts to gather requirements and contribute to the development of a robust product roadmap.\n Drive competitive engagements by demonstrating Synopsys VCS/Verdi advantages and supporting customers in benchmarking scenarios.\n Interface directly with customers, product validation, and R&D teams to propose solutions and suggest improvements in implementation and validation processes.\nDevelop and optimize scripts (Perl, TCL, Shell, Make,Python) to enhance productivity and workflow automation.\n \nThe Impact You Will Have:\nEnable customers to accelerate their verification cycles and achieve first-pass silicon success through expert support and deployment of VCS simulation technology.  \nDrive innovation in verification methodologies by integrating advanced features and AI-driven productivity tools.  \nEnhance Synopsys’ product offerings by providing actionable feedback from customer engagements and competitive benchmarking.  \nFacilitate seamless collaboration across global teams, ensuring consistent delivery of high-quality solutions.  \nSupport the continuous improvement of VCS/Verdi and related technologies through proactive problem-solving and technical expertise.\nContribute to the growth of Synopsys’ leadership in EDA by empowering customers to leverage the full capabilities of verification platforms.\n \nWhat You’ll Need:\nBachelor’s degree in Electronics with 4+ years or Master’s degree in Electronics with 2+ years of experience.  \nProficiency in verification technologies, including simulation, UVM, SVA, and LRM.  \nStrong expertise in HDL languages (Verilog, VHDL, SystemVerilog) and digital design fundamentals.  \nProven experience in debugging simulation mismatches and verification flows.  \nAdvanced scripting skills (Perl, TCL, Make, Shell, Python) and working knowledge of UNIX environments.  \nExposure to Synopsys EDA tools such as SpyGlass, VC SpyGlass, Verdi is a plus.\nExposure to GenAI technologies is a plus\n \n \nWho You Are:\nExcellent written and oral communication skills, comfortable interfacing with global teams and customers.  \nCollaborative team player with a proactive and innovative mindset.  \nDetail-oriented and organized, able to manage multiple tasks and priorities.  \nMotivated self-starter with strong problem-solving abilities.  \nAdaptable and open to travel, eager to learn and grow in a fast-paced environment.\n\nThe Team You'll Be Part Of\nYou will be working as part of the Colombo-based team supporting Synopsys EDA tools for customers globally. The team collaborates closely with remote engineering and support teams across different continents, and your role will involve both reactive support and proactive engagement to improve product deployment and customer satisfaction.\n\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "ASIC Digital Design, Sr Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-23", "url": "https://careers.synopsys.com/job/bengaluru/asic-digital-design-sr-engineer/44408/101023239552", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years moving between RTL and bare metal firmware, and you know that the hardest problems show up where those two worlds meet. SerDes IP does not forgive sloppy handoffs or assumptions that worked on the last project, and you have learned to design with that reality baked in from day one. You understand that silicon bring-up is where theory meets the bench, and you are the kind of engineer who stays calm when the prototype does not behave like the simulation said it would.\nYou do not wait for perfect specs. You ask the right questions, align with mixed-signal teams, and find a path through ambiguity without creating more downstream. When a junior engineer gets stuck on a timing closure issue or a register map conflict, you can walk them through it without taking over, because you have been there and you remember what actually helped.\nYou care about documentation and process, not because someone told you to, but because you have seen what happens when firmware gets handed off without it. At Synopsys, you will work on SerDes products that ship into real customer SoCs, and the decisions you make during development will matter long after tapeout.\nWhat You'll Be Doing\nDesign, develop, and validate bare metal firmware for NRZ and PAM-based SerDes IP targeting high-speed data recovery and serialization circuits\nWork directly with mixed-signal design and verification teams to integrate firmware with analog and digital subsystems from spec through silicon bring-up\nExecute silicon bring-up on prototype test chips, diagnosing and resolving functional and performance issues between RTL behavior and actual hardware\nMentor junior firmware and digital design engineers on structured development flows, RTL debugging, and bring-up best practices\nDrive firmware development using structured processes including documentation, version control, and verification handoffs\nCollaborate with customer support and design groups to resolve integration issues and support SerDes IP deployment into customer SoCs\nLeverage AI tools like Cursor to accelerate development, debugging, and code quality without sacrificing rigor\nThe Impact You Will Have\nYour firmware will enable SerDes IP that powers high-speed interfaces in AI, automotive, and 5G applications shipping to customers globally\nThe bring-up work you lead will directly determine whether prototype test chips meet performance targets and move to production on schedule\nYour mentorship will shape how junior engineers approach firmware design, RTL integration, and silicon debugging across the team\nThe structured processes you help establish will reduce handoff friction between design, verification, and customer support teams\nYour ability to navigate ambiguity will keep projects moving even when specs evolve or silicon behaves unexpectedly\nThe documentation and design decisions you make will carry forward into next-generation SerDes products and customer deployments\nYour work will help Synopsys maintain its position as the broadest silicon IP provider in the industry\nWhat You'll Need\nBachelor's or Master's in Electrical Engineering or equivalent practical experience\n5+ years of hands-on experience in bare metal firmware development and silicon bring-up\nStrong digital design skills with deep understanding of RTL, synthesis, and timing closure\nDemonstrated ability to mentor engineers and provide technical leadership on complex projects\nExperience executing firmware projects from specification through silicon validation using structured development and verification processes\nAbility to work across design groups and customer support teams with clear, effective communication\nKnowledge of SerDes, Ethernet, or PCIe standards is a strong plus\nProficiency with AI tools like Cursor for accelerating development workflows is a plus\nWho You Are\nYou can explain a register map conflict to a mixed-signal designer in two sentences without losing the technical nuance\nWhen a prototype does not match simulation, you methodically isolate the issue rather than guessing or escalating prematurely\nYou balance design quality with deadlines, knowing when to push back and when to ship with documented trade-offs\nYou treat documentation as part of the deliverable, not an afterthought, because you have inherited undocumented firmware before\nYou are comfortable diving into unfamiliar territory, whether that is a new SerDes standard or a silicon bug that does not match any known pattern\nYou stay current with tooling and methods, including AI-assisted development, and apply them where they genuinely improve outcomes\n\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior RTL Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-23", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Senior-RTL-Design-Engineer_JR0285094", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nWe are seeking a Senior RTL Design Engineer with 7+ years of experience to drive the logic design and integration of our next-generation, high-speed Mixed-Signal IP. In this role, you will bridge the gap between digital architecture and analog mixed-signal (AMS) circuits, taking ownership of critical digital blocks that control, calibrate, and interface with high-speed SerDes components.\nYou will collaborate closely with analog designers, verification engineers, and architectural teams to deliver robust, power-efficient, and highly optimized silicon IPs compliant with the latest specifications.\nKey Responsibilities\nRTL Development: Own the micro-architecture and RTL design (using System Verilog/Verilog) for digital control blocks within the PHY, including PCS (Physical Coding Sublayer), calibration engines, power management states (L0s, L1, L2), and clock/reset distribution.\nMixed-Signal Interface and Integration: Define, design, and verify the digital-analog interface boundary. Implement complex calibration algorithms for analog components (e.g., RX equalization, TX driver impedance, PLL/DLL tracking loops).\nIP Compliance: Ensure the digital logic seamlessly integrates with the Data Link layer via standard interfaces (such as PIPE 5.x/6.x) and strictly adheres to protocol constraints.\nFront-End Implementation: Drive design closure activities including Linting, Clock Domain Crossing (CDC) analysis, Formal Verification (LEC), and Static Timing Analysis (STA) constraints generation.\nCollaboration and Debug: Work hand-in-hand with Analog Mixed-Signal (AMS) simulation teams and Design Verification (DV) teams to debug complex co-simulation failures and maximize functional coverage.\nSilicon Power-On Support: Support post-silicon validation, bring-up, and debug teams to root-cause silicon misbehavior and optimize firmware/hardware calibration parameters.\n\nQualifications:\nRequired Technical Skills and Qualifications -\nExperience: Minimum 7+ years of dedicated experience in ASIC/IP RTL design.\nProtocol and Domain Expertise: Strong working knowledge of high-speed SerDes architectures. Deep understanding of the PIPE interface standard.\nMixed-Signal Familiarity: Proven experience dealing with digital/analog boundaries, including handling asynchronous signals, handshaking protocols, and managing distinct analog/digital power domains.\nDesign Automation: Proficiency with industry-standard front-end design tools (e.g., Synopsys SpyGlass for Lint/CDC, Cadence JasperGold for formal verification, or similar).\nLow Power and Timing: Solid understanding of multi-clock designs, low-power design techniques (UPF, clock gating), and synthesis/STA fundamentals.\nEducation: Bachelor's or Master's degree in Electrical Engineering, Electronics and Communication, or a related discipline.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "DFT Pattern", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-22T13:34:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92570/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. MTS Pattern THE ROLE: · As a member of the S3 SoC Pattern Team, the successful candidate will own/lead the Pattern verification activities on complex SOC. These SOCs are among the biggest in the market with billions of transistors, consisting of AMD's high performance X86 cores, graphics, data fabric and many IPs such as USB, PCIE · Strong self-driving ability, should have excellent communication skills (both written and oral) · Strong problem-solving skills PREFERRED EXPERIENCE: · Candidate is responsible for verifying and delivering patterns to Product Engineering team for silicon validation. · Candidate is responsible for taking the test sequence from IP and porting it to SOC, running and verifying it at SOC, debug any fails/issues seen and deliver the passing patterns to Product Engineering · Must have good knowledge on the verification flows and tools such as VCS, Verdi · Must have hands in experience with AMBA, HSIO, IEEE 1149.1, IEEE 1678, IEEE 1500 protocols · Excellent hands-on debug skills and problem-solving attitude. · Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC · Experience of working on Functional Verification, SoC Verification, Emulation · Good in programming, System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language · Must have good communication skills and the ability to work in a team environment. · Preferably having experience in architecture such as x86 or ARM domain based SOCs · Experience with CReST, PCIE, DDR is desired but not essential. · This position requires minimum of 10 to 15 years of experience   ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-RR1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Synthesis CAD Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-22T09:08:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92683/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. MTS SILICON DESIGN ENGINEER    THE ROLE: • Play a critical role in shaping the next generation of AMD products, including CPUs, GPUs, and adaptive compute engines. • Interface with large, globally distributed design teams to support complex and collaborative development efforts. • Drive automation of Synthesis, Place and Route, Logic Eqv, Functional ECO methodologies targeting advanced technology nodes. • Own the development and support of next-generation synthesis flows, ensuring scalability and efficiency across projects. • Collaborate closely with EDA vendors to identify innovative solutions, resolve tool/methodology issues, and enhance flow capabilities. • Contribute to the evolution of AMD’s design infrastructure by improving automation, performance, and methodology robustness. KEY RESPONSIBILITIES: - Responsible for developing and automating Synthesize, PnR and Functional ECO, for various designs at advanced technology nodes. - Script out utilities to automate different components of the implementation flow. - Support design teams across global sites on various issues related to Front-End Synthesis flow targets. - CAD flow and methodology development on advanced process nodes are preferred. Tool Expertise Required: - Hands on experience in Front-End Synthesis, Logical Eqv and Conformal ECO flows. - Hands on experience in industry standard tools such as Innovus, Genus, DC, Fusion Compiler, FM,VCLP, ICC2, Conformal. - Hands on experience in any of PnR, STA, Formal Verification or RTL coding domains is a plus. - CAD and automation mindset ACADEMIC CREDENTIALS: - Masters degree in Electronics Engineering - 5-9 years of experience in CAD flow and methodology development on advanced nodes. - Proficiency in one or more scripting languages namely Python, Tcl, Perl, sed/awk - Strong problem-solving skills and analytical thinking - Team player, good work ethic, and excellent communication skills. Job Location : Bangalore #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Staff Product Engineer - Power / Analog", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-22T08:23:01.345000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000150963379-senior-staff-product-engineer-power-analog", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "The role\nThis is a product engineering role with technical program ownership. You are the single point of accountability for power/analog products from concept through first silicon, characterization, qualification, production release and sustaining — working across design, package, test, operations, foundry and OSAT teams to get it there.\nIt is not a yield-analysis role. Yield and outgoing quality are yours, but so are testability and trim strategy before tape-out, package and thermal selection, the NPI schedule, and the cross-functional risk register. If it stands between silicon and shipping product, you own it.\nKey responsibilities\nNPI and design-phase readiness\nRepresent product, test and package requirements in design reviews — test access to analog nodes, trim and OTP strategy, diagnostic and self-test coverage, and the multi-variant bond-out plan where one die serves several products.\nOwn package and thermal selection and the package development and qualification plan with the package team and OSAT — power dissipation, junction-to-ambient and junction-to-case targets, exposed-pad and board-level reliability considerations.\nOwn the NPI schedule, milestone gates and cross-functional risk register from concept through production release.\nOwn product cost — die size and yield entitlement, test time, package, and the unit-cost roadmap across the product life.\nQualification and release\nOwn qualification planning and execution in accordance with applicable JEDEC and AEC-Q100 requirements, including the stress set appropriate to power devices — HTOL, power/temperature cycling, and package-level reliability.\nPrepare product-release documentation, datasheet parameter tables and compliance evidence, including PPAP evidence where applicable.\nSupport the functional-safety work products — ensuring production screens and characterization data substantiate the FMEDA and safety manual claims.\nProduction and sustaining\nMonitor production data and apply statistical analysis to identify and correct yield, quality and test-time deficiencies; drive yield improvement.\nOptimise PAT, SYL, SBL, SPC and disposition limits to protect outgoing quality.\nWork with planning, manufacturing, subcontractors and operations to remove material-flow obstacles and recover schedule gaps.\nCreate and maintain product BOMs and lifecycle data in PLM systems such as Agile; support fab transfer, process change and BOM change activities.\nSupport customer-return and RMA investigations by reproducing failures and assessing production test coverage — including electrical overstress and field-stress modes typical of power devices.\nOwn the product through end of life, including last-time-buy and discontinuation planning.\nTechnical leadership\nProvide technical direction and sign off reviews across design, product engineering, operations, suppliers and OSAT teams, including DFX topics.\nAct as the escalation point for product-level technical decisions and drive risk resolution to closure.\nInfluence cross-functional teams without direct authority and communicate clearly to stakeholders at every level.\nMentor product and test engineers and raise the standard of product engineering practice across programs.\n\nBachelor's degree in electronics, electrical, materials or physics engineering. Advanced degree welcome.\n10+ years of semiconductor experience spanning product engineering, NPI, manufacturing and test — or 8+ with an advanced degree. Concept-to-mass-production ownership of at least one product is essential.\nPower or analog product experience — High-voltage or high-current devices; drivers, regulators, power management or similar. This is the core requirement.\nStrong grasp of analog and power device behaviour — driver stages, regulators, references and protection circuits — and how they move over process, voltage and temperature.\nPractical understanding of wafer fabrication, assembly, test, qualification and production-release flows.\nExperience managing engineering wafer starts, prototype builds, customer samples, inventory and product BOMs..\nFamiliarity with JEDEC and AEC-Q100 qualification standards, qualification hardware and software, and failure analysis methods.\nExperience working with external foundries, OSATs and globally distributed teams.\nFluency with data and statistical methods for managing yield, quality, cycle time and operational priorities.\nClear written and verbal communication, strong planning and coordination skills, and the ability to work under schedule pressure.\nPreferred\nAutomotive power/analog experience — AEC-Q100 Grade 1 or 0, tri-temp production test, IATF 16949 and PPAP environments.\nISO 26262 exposure — production screens and characterization traced to FMEDA claims, safety-related release evidence.\nExperience with a multi-variant die — bond-out or package derivatives sharing one base silicon.\nThermal modelling and SOA analysis experience for power devices.\nPLM and yield-management tooling — Agile, PDF Exensio, JMP or equivalent.\nExperience with a product from first silicon through a fab or OSAT transfer.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "DFT - MBIST", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-22T07:31:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92564/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. MTS DFT Design Engineer THE ROLE: · As a member of the S3 SoC DFx Team, the successful candidate will own/lead the DFT Design and Integration of cutting edge DFT structures including SCAN, ATPG, MBIST, BSCAN. · Position includes DFT design development, data analysis and silicon debug of DFT in leading process technologies. · Strong self-driving ability, should have excellent communication skills (both written and oral) · Strong problem-solving skills KEY RESPONSIBILITIES: · Working closely with the DFT Architecture and the various IP Design teams to align on the DFT requirements and successfully implementing the DFT design · Design and develop correct by construction DFT design and support DFT verification · Working closely with the RTL designers, Verification Engineers, and PD team to find creative ways to accelerate the identification of functional defects. PREFERRED EXPERIENCE: · Experience and an understanding of ASIC DFT, synthesis, simulation and verification flow · Experience is End-to-End DFT flow development/creation. · Expert in Perl, Python, TCL, and ability to create complex flows/scripts. · Strong EDA tools experience (Tessent, Design Compiler, Spyglass,) · Experience in DFT architecture for complex chips · Experience in RTL development using Verilog/System Verilog having worked on RTL for IP and SoC integration · Proficient in doing basic unit-level verification using simulations. · Experience with RTL quality check tools/methodologies such as Spyglass, CDC, Lint is required. · Must have experience with integration of various IPs into complex SOCs. · Exposure to Static timing analysis & Timing closure is required. · Scan/ATPG patterns & test flows development, debug, test, and characterization · Excellent hands-on debug skills and scripting skills are critical. · Must have good communication skills and the ability to work in a worldwide team environment. · Knowledge & experience of low power concepts, clock gating, power gating is a plus · Experience with post-silicon bring up is a plus ACADEMIC CREDENTIALS: · B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering · 7+ years’ experience in DFT Design #LI-RR1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Staff Hardware Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-22T07:25:39.410000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000150947134-staff-hardware-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Introduction\nAre you a passionate Power electronics designer with a talent for defining and supervising power electronics prototypes and reference designs?\n\nAre you looking forward to working on cutting-edge solutions in the field of power electronics for Infrastructure and Datacenter applications?\n\nIf so, we want you on our expanding Power System and Solution Marketing Team!\nWe are seeking a highly motivated, talented and experienced Hardware designer to play a pivotal role in the development of our next-generation power electronics systems, from concept to reference design and physical prototyping.\nThe ideal candidate has track-record of successfully leading the definition, development, validation and integration for power solutions (1 – 100s kW) which seamlessly combine several power converters (AC-DC, DC-AC, DC-DC), multiple MCUs/MPUs (ARM Cortex-A/M, Renesas proprietary core) and numerous sensors.\nIn this exciting role, you will be responsible for the entire proof-of-concept lifecycle, from defining the architecture and selecting suitable parts, to supervising the integration of both hardware and software.\nDeep knowledge in Power Management, Infrastructure Power Delivery Network and Server/Datacenter power architectures will make you successful in this role.\nExceptional communication skills will help you interacting with customers, but also working with both System and Chip Design Teams Engineers to ensure in our worldwide, customer-oriented, expanding team.\nThis position allows for a hybrid work schedule with a mix of work spent between the office and working from home.\nRole Responsibilities\nIn this role, you will be responsible for:\nDefine complex power electronics system architectures (1 - 250 kW) which meet electrical performances, reliability, and cost requirements focusing on Infrastructure and Servers/Datacenter\nPerform trade-off studies and select optimal solution in regards of system size (i.e., power density), cost and performances.\nDevelop detailed system specifications and ensure adherence to all regulatory requirements.\nSelect the best Renesas Power Products among released and sampled ICs to meet system requirements and resolve customers’ technical issues.\nBreak-down large and complex power electronic systems into modular and scalable sub-systems to meet Efficiency and Power Density requirements of modern Communications and Datacenter infrastructures\nModelling and simulation of complex power electronics systems in MATLAB Simulink (preferred system-simulation tool).\nLead the development of Proof-of-Concept Boards from schematic implementation to system validation stages.\nEffectively manage project timelines, engineering resources and budget.\nMonitor market trends and contribute to both Solutions and IC design roadmap for Datacenter and Infrastructure Power Supply Systems, Power Products (Voltage Regulators, Power Supply Controllers, Gate-Drivers, Discrete Power Switches).\nCollaborate with cross-functional teams, e.g. Business Development Team, Sales Team, Power Product design, both Hardware and Software development team, external vendors, to ensure seamless system definition, integration and promotion.\n\nMSEE is required, PhD is a plus, with 12+ years of relevant experience in Power Systems (1 - 250 kW) design and development.\nProven track record of successfully leading the development of complex power electronics system design and physical prototype validation.\nSolid knowledge of electrical engineering fundamentals, strong analytical and problem-solving skills.\nProficient with conducting feasibility studies to compare electrical performances, Bill of Materials (BOM), and cost of various power converter designs or system solutions.\nIn-depth knowledge of power conversion topologies (AC-DC, Inverter, Isolated DC-DC converters, LDO, Switching Mode Power Supply like Buck, Boost and Buck-Boost DC-DC converters), magnetics, control theory, and discrete power devices (SiC MOSFET, IGBT, GaN).\nHands on experience in schematic design for high power applications (1-250 kW), including PCB layout techniques to minimize EMI/EMC\nProficient with Power electronics simulation tools (e.g. MATLAB Simulink, SIMetrix/Simplis, SPICE, etc.).\nExcellent communication skills and demonstrated ability to work cross-functionally with a wide range of worldwide groups including FAEs, Sales, Power ICs design teams, Hardware and Software engineers, Product Marketing Manager, etc.\nExperience in Power Supply Architecture for Communication Infrastructure, Datacenter, Traditional and AI Servers applications is a strong plus.\nExperience in designing and developing power electronics systems utilizing Wide-bandgap (WBG) devices (e.g., GaN, SiC) is a strong plus.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "DFT Timing Lead", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-22T07:06:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92565/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. SMTS/MTS Silicon Design Engineer The Role: · As a key member of the S3 SoC DFT Team, the successful candidate will play a significant role in ensuring the quality of next generation AMD SoCs through structural DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques. Key Responsibilities: · Develop full chip DFT Synthesis and DFT STA constraints. · STA constraint development of DFT modes (ScanShift, Atspeed, MBIST) · Set up DFT timing constraints, defining the overall SOC Test STA methodology. · Working with the Design team to clean-up all the DFT related constraint issues · Closely work with physical design team to generate and validate timing constraints · Developing, improving and maintaining automation scripts as necessary Preferred Experience: · Experience in DFT architecture for complex chips · Exposure to Static timing analysis & Timing closure is required. · Proven experience in DFT constraints handling, Block and Top-level test mode Static timing analysis (STA). · Experience in SOC timing closure in DFT modes and sign-off · Experience with RTL quality check tools/methodologies such as Spyglass, CDC, Lint is required. · Excellent hands-on debug skills and scripting skills are critical. Qualification: · B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering with 8 to 15 years of DFT Experience #LI-RR1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "DFT - ATPG", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-22T07:02:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92573/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. MTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning PREFERRED EXPERIENCE: Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.) Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-RR1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Sr DFT ATPG Lead", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-22T06:51:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92572/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. SMTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning PREFERRED EXPERIENCE: Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.) Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-RR1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Silicon Design Architect", "company": "Astera Labs", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-22T05:46:03-04:00", "url": "https://job-boards.greenhouse.io/asteralabs/jobs/4735007005", "is_hardware": true, "platform": "greenhouse", "jd_text": "Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\n\nSilicon Digital Architect - IP / Subsystem\n\n \n\nExperience- 20+ years\n\nJob Summary\n\nWe are looking for an experienced IP/Subsystem Architect to define the architecture and technical direction of complex semiconductor IPs and subsystems. The candidate will own architecture definition from requirements through implementation, working closely with SoC, RTL, verification, physical design, firmware, and system teams.\n\nKey Responsibilities\n\nDefine architecture for complex IP blocks and SoC subsystems based on product and system requirements.\n\nTranslate system requirements into architecture, specifications, interfaces, and performance targets.\n\nDefine microarchitecture, data paths, control paths, interfaces, clocking, reset, power, and error-handling mechanisms.\n\nEvaluate architectural trade-offs across performance, power, area, latency, bandwidth, scalability, and complexity.\n\nDefine interfaces and protocols such as PCIe, UALink, AXI, APB, CHI, or other high-speed/interconnect protocols.\n\nDevelop architecture specifications, block diagrams, interface specifications, and technical documentation.\n\nWork closely with RTL, verification, physical design, DFT, firmware, and system architecture teams.\n\nIdentify architectural risks and drive resolution of complex technical issues.\n\nReview RTL and verification strategies to ensure implementation aligns with architectural intent.\n\nProvide technical leadership and mentorship to senior/principal engineers.\n\nDrive architecture reviews and communicate technical decisions to engineering leadership.\n\nRequired Skills\n\nStrong background in IP architecture and microarchitecture\n\nBackground in ASIC/SoC architecture and microarchitecture is a big plus.\n\nStrong understanding of digital design, computer architecture, memory systems, interconnects, and SoC design.\n\nExperience with high-speed interfaces and/or coherent interconnects.\n\nStrong understanding of performance modeling, bandwidth, latency, and system-level trade-offs.\n\nExcellent technical communication and problem-solving skills.\n\nPreferred\n\nExperience with PCIe, UALink, CXL, Ethernet, CCIX, CHI, or similar technologies.\n\nExperience with AI/accelerator, networking, compute, or high-performance SoC architectures.\n\nExperience taking IP/subsystems from architecture through silicon production.\n\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.", "jd_status": "stored"}, {"title": "Staff Engineer - SoC Power Architecture", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-22T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721200769", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Systems Engineering\nGeneral Summary:\nSeeking an experienced SoC Power Architect to drive power-efficient architectures for next-generation SoCs. The role focuses on optimizing & exploring new features to optimize dynamic power , Vmin reduction, leakage power , use case energy footprint across SOC infra ,  CLK tree power, power modelling including lab characterization of SOC infra energy impacts & residency profiles of use-cases, data analysis\n\nKey Responsibilities\nExploring new SoC-level power architecture & optimization features, architecture dependencies with different IP blocks. Driving cross-functional technical evaluations of new features across multiple stakeholders\n\nEnergy & latency sensitivity study of dynamic power reduction techniques DVFS, clock gating, power gating, Micro/Macro power collapse periods\n\nAnalyze and optimize Vmin margins, power-performance tradeoffs, and silicon robustness.\n\nSOC infrastructure power optimization techniques by studying infra utilization based on use-case profiles ,\n\nIsland use-cases flows,  constraints in micro & macro -idle power optimization techniques,  \n\nDrive leakage reduction and low-power design techniques across advanced process nodes.\n\nEvaluate efficient techniques to manage voltage droops, overshoots, thermal & electrical limits \n\nHandson experience in developing MATLAB models to quantify PPA KPI of power architecture features  \n\nSPICE simulations to backup SOC/System level architecture features heling optimize Voltage droops, overshoots dynamic load-line management \n\nRequired Qualifications\nBachelor's/Master's degree in Electrical/Electronics Engineering or related field.\n\n8+ years of experience in SoC Power Architecture, Energy Management & Low-Power Design.\n\nStrong expertise in:\nDynamic Power Optimization\n\nVmin Analysis and Margining\n\nLeakage Power Reduction\n\nLow-Power Design Techniques\n\nPDN/Power Integrity Analysis\n\nDVFS, Clock Gating, Power Gating\n\nHands-on experience with:\nMATLAB Modeling,  SPICE Simulations, Lab power/perf data crunching \n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.\n                                                                    OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience.\n                                                                    OR\nPhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CAD/EDA Methodology Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-22T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720318849", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Description\n- Develop, maintain, and enhance automation tools and infrastructure supporting ASIC Front-End design flows.\n- Analyze existing design workflows and propose solutions to improve efficiency, scalability, and usability.\n- Implement software-based solutions using Python, Perl, C++, or similar programming languages.\n- Debug, troubleshoot, and resolve issues in CAD tools, scripts, and automation frameworks.\n- Collaborate with design and CAD teams to understand requirements and deliver effective automation solutions.\n- Support internal customers by enabling adoption of existing and newly developed tools.\n- Contribute to documentation, tool validation, and continuous improvement of engineering methodologies.\n- Explore and evaluate AI/ML-based approaches to enhance EDA tools and front-end design productivity.\n \nEducational Qualification Requirement\n- Must hold a B.E/B.Tech or M.E/M.Tech degree in Electronics/VLSI stream.\n \nRequired Skills\n- 0-1 year of experience in CAD/EDA automation, software development, or RTL design.\n- Strong programming skills in Python (preferred), Perl, C++, or similar languages.\n- Good understanding of software development fundamentals, debugging, and problem-solving techniques.\n- Ability to analyze requirements and design practical software solutions.\n- Experience working in Linux/Unix environments and scripting is a plus.\n- Strong analytical, communication, and collaboration skills.\n- Basic understanding of ASIC Front-End design flow and RTL concepts is desirable.\n- Exposure to AI/ML concepts and their application in engineering workflows is a plus.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU Design Verification - Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-22T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719906887", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n\nQualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement.\nRoles and Responsibilities\no  Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling.\no  Work closely with design/verification teams within CPU to develop comprehensive test plan.\no  Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus.\no  Verify power intent through use of methodologies like UPF.\no  Work closely with system architects, software teams and Soc team to validate system use cases.\no  Work closely with emulation team to enable verification on emulators and FPGA platforms.\no  Debug and triage failures in simulation, emulation and/or Silicon.\nBE/BTech degree in CS/EE with 4+ years’ experience.\no  Experience in power management verification.\no  Implementation of assembly and C language embedded firmware.\no  Experience in C/C++, scripting languages, Verilog/system Verilog.\no  Strong understanding of power management features in CPUs and CPU based Socs.\no  Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.\nPreferred Requirements:\no  Good Understanding of CPU architectures and CPU micro-architectures.\no  In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture\no  Experience with advanced verification techniques such as formal and assertions is a plus\no  Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU Design Verification Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-22T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720377869", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nQualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement.\n\nRoles and Responsibilities\n\no   Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling.\no   Work closely with design/verification teams within CPU to develop comprehensive test plan.\no   Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus.\no   Verify power intent through use of methodologies like UPF.\no   Work closely with system architects, software teams and Soc team to validate system use cases.\no   Work closely with emulation team to enable verification on emulators and FPGA platforms.\no   Debug and triage failures in simulation, emulation and/or Silicon.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nBE/BTech degree in CS/EE with 4+ years’ experience.\n\no   Experience in power management verification.\no   Implementation of assembly and C language embedded firmware.\no   Experience in C/C++, scripting languages, Verilog/system Verilog.\no   Strong understanding of power management features in CPUs and CPU based Socs.\no   Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.\n\nPreferred Requirements:\n\no   Good Understanding of CPU architectures and CPU micro-architectures.\no   In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture\no   Experience with advanced verification techniques such as formal and assertions is a plus\no   Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "LPASS Design Verification Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-22T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718854044", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nQualcomm LPASS HW team in Bangalore is part of a worldwide team responsible for developing and delivering Audio solutions which are setting the benchmark in mobile computing industry. The role of LPASS DV Engineer will involve a deep understanding of the HW architecture while getting an opportunity to work with the latest DV tools and technologies.\nIndividual responsibility will include\nDV ownership of one or more features in the Low power audio subsystem(LPASS) core\n\nDeveloping a robust testbench, optimized for the specific feature/DUT\n\nExplore innovative DV methodologies (formal, simulation and emulation based) to continuously push the quality and efficiency of test benches and process improvements.\n\nEnsure a bug free silicon for Tape Out which eventually leads to a superb user experience of Snapdragon based computing devices\n\nFor better understanding of some of our products, please refer to the links below\nhttps://www.qualcomm.com/products/smartphones\nQualcomm Aqstic | Qualcomm\n\nMinimum Qualifications\nMinimum 1 - 2  years of VLSI industry experience\n\nStrong debugging and analytical skills\n\nStrong knowledge of HDLs like Verilog, System Verilog\n\nProficiency in developing SV/UVM based test benches\n\nProficient in debugging RTL/TB issues using Verdi or similar tools\n\nProficient with scripting languages such as Perl and(or) Python\n\nPreferred Qualifications *\nKnowledge of UPF, low power  architecture\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Implementation Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-22T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720250363", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nLooking for a highly talented and a technically strong leader with an eye for quality to lead a high performing and talented team of engineers in the implementation domain for Display Sub-System.\nAble to handle multiple project execution that are time critical and complex\nAble to communicate effectively with all stakeholders across the organization\nAble to collaborate with cross functional teams for upholding the best practices and enabling smooth execution\nFocus on improving execution efficiency and improve on the optimizations in area, power and performance.\nAble to grow the team in terms of technical depth and size as we do more and more projects\nAble to innovate and bring fresh ideas\nBachelor’s or master’s degree in engineering with 9-13+ Years of experience.\nShould have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.\nExperience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.\nExperience in all aspects of timing closure for multi-clock domain designs.\nShould be familiar with MCMM synthesis and optimization.\nShould have good understanding of low-power design implementation using UPF.\nExperience with scripting language such as Perl/ Python, TCL.\nExperience with different power optimization flows or technique such as clock gating.\nShould be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation\nShould be able to handle ECOs and formal verification and maintain high quality matrix\nResponsibilities include:\nSynthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation.\nDevelopment of signoff quality constraints and the development of power intent constraints.\nMay also include running RTL Lint, CLP, MEMBIST, DFT DRC etc.\nTCL script development in addition to running/analyzing/debugging designs.\nHands on with Synopsys DCG/Genus/Fusion Compiler.\nHands on with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains.\nHands on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development\nExperience with either RTL development or Physical Design is also a plus\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Lead Layout Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-22T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721144709", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Services Group, Engineering Services Group > Layout Engineer\nGeneral Summary:\nDevelops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues.\n\nMinimum Qualifications:\n•    Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 3+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.\n                                                                    OR\nAssociate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 5+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.\n                                                                    OR\nHigh School diploma or equivalent and 7+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.\n\n•    3+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap).\n\n*Completed advanced degrees in a relevant field may be substituted for up to two years (Master’s = one year, Doctorate = two years) of the general custom layout design work experience in a relevant domain (e.g., analog, mixed signal, RF, digital design).\n\n5+ years of expertise in high speed / Analog / Mixed signal layouts in lower nodes with Bachelor's in Electrical or Electronics Engineering or equivalent. Owning and delivering top‑level physical layout for complex analog, digital, or mixed‑signal designs across technology nodes.\nProficient in meeting layout performance, reliability, manufacturability, and quality requirements, adhering to foundry DRC/LVS and internal design guidelines. Proficient in Cadence Virtuoso layout XL / GXL / EXL and Calibre physical verification flow and expertise in debugging skills.\nAbility to work & communicate effectively with global engineering teams. Effectively multitask and lead parallel projects, coordinating execution and priorities by well collaborating with the team members.\nCapable of leveraging automation and having scripting expertise to eliminate repetitive manual tasks, improving efficiency and reducing total turnaround time. Act as a technical point of contact for layout‑related discussions with design, verification, CAD, and technology teams.\nIdentify risks early and proactively develop mitigation plans to ensure on‑time delivery of layout milestones.\nMentor junior layout engineers by reviewing work, sharing best practices, and promoting design quality and efficiency\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Infra Design Verification Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-22T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720401871", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nAdditional Job Description\nKey Responsibilities:\nDevelop and maintain UVM-based verification environments for high-speed interconnect protocols (PCIe, CXL, AXI).\nCreate and execute verification plans for high-speed interconnect protocols including PCIe, CXL, AXI, and CHI.\nPerform block-level and top-level verification, including functional coverage, assertion-based verification, and regression testing.\nCollaborate with RTL designers, architects, and validation teams to ensure design correctness and coverage closure.\nWork closely with design and architecture teams to understand specifications and derive verification strategies.\nUse third-party VIPs (e.g., Synopsys, Mentor) for protocol compliance and simulation.\nImplement and enhance scoreboards, agents, monitors, and sequences.\nIntegrate and validate SMMU and Coresight components in Subsystem environments.\nDrive verification closure through coverage convergence and assertion-based verification.\nContribute to performance, power, and cost optimization considerations during verification.\nMentor junior engineers and contribute to verification methodology improvements.\nDebug failures at RTL and gate-level simulations.\nRequired Skills:\nStrong proficiency in System Verilog, UVM, and verification methodologies.\nDeep understanding of PCIe Gen3/Gen4/Gen5/Gen6, CXL 1.1/2.0/3.0, AXI/CHI protocols, and SMMU/Coresight architecture.\nFamiliarity with Synopsys/Mentor VIPs for PCIe/CXL and AMBA protocols.\nExpertise in assertion-based verification (SVA) and coverage-driven testing.\nProficiency in Perl/Python/Tcl scripting for automation.\nKnowledge of power-aware verification (UPF), formal verification, and performance/power optimization.\nExperience with coverage-driven verification and random constraint-based testing.\nExperience with scripting languages like Python, Perl, or Tcl.\nPreferred Qualifications:\nBachelor’s/Master’s/Ph.D. in Electrical, Electronics, or Computer Engineering.\n3+ years of ASIC/Subsystem/SoC verification experience.\nExperience with PCIe, USB, Ethernet, or other peripheral protocols is a plus.\nExposure to post-silicon validation and lab bring-up is desirable.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NOC DV Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-22T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721094632", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nRole Summary\nSeeking a highly skilled and self-driven Design Verification Engineer to lead verification of complex AI, Networking, Datacenter, HPC, and Interconnect IPs/Sub-systems. The candidate should demonstrate strong ownership, technical depth, and the ability to independently drive verification from architecture understanding through signoff-quality closure.\nKey Responsibilities & Skills\nExpert in SystemVerilog (SV) and UVM, with hands-on experience in building reusable verification environments, UVCs/agents, sequences, scoreboards, checkers, assertions, and coverage infrastructure.\nStrong expertise in verification planning, constrained-random verification, SVA, functional coverage closure, regression management, and signoff methodologies.\nProven ability to independently own and execute IP/Sub-System DV from specification review to verification closure.\nStrong debugging skills across RTL, protocol, architecture, performance, and testbench issues, with demonstrated root-cause analysis capability.\nExperience in verifying NoC, coherent/non-coherent interconnects, memory/cache subsystems, AI accelerators, or complex data movement fabrics.\nDeep protocol verification expertise in one or more of: PCIe (Gen4/5/6)\nUSB (USB3.x/USB4)\nEthernet (10G/25G/100G/400G+)\nCXL\nOther high-speed serial/networking protocols\n\nExperience with AI Scale-Up / Scale-Out Interconnects such as UAL, UMAC, eSUN, or equivalent accelerator cluster fabrics.\nStrong understanding of AMBA protocols (AXI, AHB, ACE, CHI) and coherency architectures.\nKnowledge of performance verification, QoS validation, congestion analysis, scalability testing, and system-level qualification.\nProficiency in Python, Shell, Perl, or Tcl for regression automation, infrastructure development, and productivity enhancement.\nFamiliarity with industry-standard simulators, debug tools, coverage tools, CI/CD workflows, emulation, and verification automation frameworks.\nStrong collaboration, communication, technical leadership, and execution skills with the ability to thrive in a fast-paced environment.\nPreferred Experience\nVerification experience in SoC, AI/ML Accelerators, Networking, Datacenter, Multi-Die, or HPC platforms.\nExposure to SystemC/TLM modeling, performance modeling, emulation/prototyping, and post-silicon correlation.\nTrack record of delivering first-pass verification closure for complex IPs and subsystems.\nQualifications\nB.Tech/M.Tech in Electronics, Electrical Engineering, Computer Science, VLSI, or related disciplines from reputed Tier-1 institutions (IITs, NITs, IIITs, BITS, or equivalent).\nRelevant industry experience aligned with the position level, demonstrating strong expertise in Design Verification, SV/UVM methodologies, protocol verification, and architecture-driven validation.\nProven history of technical ownership and successful delivery of complex IP, Sub-System, or SoC verification programs.\nIdeal Candidate\nA hands-on verification expert with deep protocol knowledge, strong debugging capability, and the ability to independently architect, execute, and close verification of next-generation AI and high-performance silicon designs.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Silicon Validation Engineer", "company": "Lattice", "location": "San Jose, CA", "date_posted": "2026-09-22", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/San-Jose-CA/Silicon-Validation-Engineer-5_R-100658", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\n\nJob Description:\nWhat Will You Get to Do?\n\nDo you have a passion for invention and self-challenge? This position gives you an opportunity to learn and participate in one of the most cutting-edge projects that Lattice’s Silicon Engineering team has embarked upon to date.\nWe are validating building blocks in FPGA on board level to ensure functionality and performance aspect of Design intent. FPGA consists of various IPs as a building block such as SERDES(PMA/PCS), Memory DDR(DDR4, LPDDR4, DDR5 etc), DPHY, PLL, DSP, Fabric, I/O etc. \n\nAs a Silicon Design Validation engineer, you will have an opportunity to learn and train yourself on how to validate one/or many of the building blocks within the FPGA. And also, you will be able to acquire knowledge on process/methodology required for validating certain IPs from planning to completion. While you are working on those, you will be exposed to cutting edge equipment and advanced boards as well as Various SW/tools/scripts. \n\nWhat you’re going to be exposed to and learn\n:\n\nThe ideal candidate is highly motivated in developing a career in Silicon Design Validation engineering.  You will get significant exposure and training in the following areas:\nChance to learn FPGA and it’s build block such as SERDES(PMA/PCS), Memory DDR(DDR4, LPDDR4, DDR5 etc), DPHY, PLL, DSP, MIPI, Fabric, I/O etc but not limited.\nValidate and characterize various IPs from silicon arrival to release to production.\nDevelop validation and characterization plans for certain IP, bench hardware and software.\nDevelop test logic RTL to achieve intended validation/characterization test.\nDrive new silicon product bring-up, validation, debug to asses IP functionality/performance. Characterizing data sheet parameters. Analyzing the measured data with statistical view. Data sheet preparation etc.\nServe as the central resource with design, verification, manufacturing, test, quality and marketing/apps as the product(s) move Silicon arrival to product release.\nSupporting customer issues as required to resolve issues found after product release\n\nYou Have…\n\n8+ years of experience\nElectrical Engineering degree with a strong desire to pursue an engineering career in Silicon Design Validation\nCapability to lead small group of teams as tech lead.\nExpertise in High Speed Serdes Interface characterization and protocol compliance testing such as PCIe/Ethernet/SDI/CoaXpress/JESD204, MIPI D-PHY, MIPI CSI/DSI-2, USB and DisplayPort/HDMI etc.\nExpertise in high speed board design and signal integrity evaluation/debug.\nExpertise in Verilog/VHDL and design implementation using FPGA development tools.\nExpertise in test automation development using programming languages such as Python, Perl.\nKnowledge of statistical analysis concepts and use of analysis tools such as JMP, R.\nProficiency with bench equipment for device characterization such as BERT, VNA, Oscilloscopes, Protocol Exerciser/Analyzers.\nExposure on FPGA(emulation/prototyping etc)\nStrong written and verbal communication skills to work with cross-functional team\nSelf-motivated and proactive with critical thinking.\nGood problem solving and debugging skills.\n\n#LI-DNP\n\nPay & Benefits\n\nConsistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. \n\nFor candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.  The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.\n\nBase Pay Range\n220800\nIn addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! \n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in the United States.\n\nLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.\n \nAs an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.", "jd_status": "stored"}, {"title": "Silicon Validation Engineer", "company": "Lattice", "location": "San Jose, CA", "date_posted": "2026-09-22", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/San-Jose-CA/Silicon-Validation-Engineer-3_R-100748-1", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\n\nJob Description:\nWhat Will You Get to Do?\n\nDo you have a passion for invention and self-challenge? This position gives you an opportunity to learn and participate in one of the most cutting-edge projects that Lattice’s Silicon Engineering team has embarked upon to date.\nWe are validating building blocks in FPGA on board level to ensure functionality and performance aspect of Design intent. FPGA consists of various IPs as a building block such as SERDES(PMA/PCS), Memory DDR(DDR4, LPDDR4, DDR5 etc), DPHY, PLL, DSP, Fabric, I/O etc.  As a Silicon Design Validation engineer, you will have an opportunity to learn and train yourself on how to validate one/or many of the building blocks within the FPGA. And also, you will be able to acquire knowledge on process/methodology required for validating certain IPs from planning to completion. While you are working on those, you will be exposed to cutting edge equipment and advanced boards as well as Various SW/tools/scripts. \n\nWhat you’re going to be exposed to and learn:\n\nThe ideal candidate is highly motivated in developing a career in Silicon Design Validation engineering.  You will get significant exposure and training in the following areas:\n\nChance to learn FPGA and it’s build block such as SERDES(PMA/PCS), Memory DDR(DDR4, LPDDR4, DDR5 etc), DPHY, PLL, DSP, MIPI, Fabric, I/O etc but not limited.\nValidate and characterize various IPs from silicon arrival to release to production.\nDevelop validation and characterization plans for certain IP, bench hardware and software.\nDevelop test logic RTL to achieve intended validation/characterization test.\nDrive new silicon product bring-up, validation, debug to asses IP functionality/performance. Characterizing data sheet parameters. Analyzing the measured data with statistical view.  Data sheet preparation etc.\nServe as the central resource with design, verification, manufacturing, test, quality and marketing/apps as the product(s) move Silicon arrival to product release.\nSupporting customer issues as required to resolve issues found after product release\n\nYou Have…\n\n2+ years of experience\nElectrical Engineering degree with a strong desire to pursue an engineering career in Silicon Design Validation\nExpertise in High Speed Serdes Interface characterization and protocol compliance testing such as PCIe/Ethernet/SDI/CoaXpress/JESD204, MIPI D-PHY, MIPI CSI/DSI-2, USB and DisplayPort/HDMI etc.\nExpertise in high speed board design and signal integrity evaluation/debug.\nExpertise in Verilog/VHDL and design implementation using FPGA development tools.\nExpertise in test automation development using programming languages such as Python, Perl.\nKnowledge of statistical analysis concepts and use of analysis tools such as JMP, R.\nProficiency with bench equipment for device characterization such as BERT, VNA, Oscilloscopes, Protocol Exerciser/Analyzers.\nExposure on FPGA(emulation/prototyping etc)\nStrong written and verbal communication skills to work with cross-functional team\nSelf-motivated and proactive with critical thinking.\nGood problem solving and debugging skills.\n\n#LI-DNP\n\nPay & Benefits\n\nConsistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. \n\nFor candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.  The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.\n\nBase Pay Range\n170400\nIn addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! \n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in the United States.\n\nLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.\n \nAs an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.", "jd_status": "stored"}, {"title": "Senior Analog IC Design Engineer", "company": "Lattice", "location": "Taipei, Taiwan", "date_posted": "2026-09-22", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Taipei-Taiwan/Senior-Analog-IC-Design-Engineer_R-100774", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\n\nThe Senior Analog IC Design Engineer is responsible for the design and development of analog, mixed-signal IC circuit blocks from initial specification and architecture to final, post-silicon verification to ensure specifications are met.\n\nResponsibilities include:\nAnalog, mixed-signal circuit design and simulation.\n\nWork with mask designers to deliver physical design.\n\nIntegration of analog/mixed-signal blocks into large, complex, digital chips.\n\nDefine bench-level test plans for post-silicon characterization.\n\nPost-silicon measurements, characterization, and debug.\n\nLead/mentor junior engineers.\n\nQualifications:\nBS, MS, and/or PhD in Electrical Engineering or related fields.\n\nMultiple years of experience working in analog/mixed-signal circuit design (BSEE, 10+ years, MS 8+ years, PhD 5+ years).\n\nProven design experience in most of the following analog, mixed-signal circuits: SerDes receivers/transmitters, low-jitter PLLs, oscillators, phase interpolators, ADC/DAC, high speed clock distribution, bandgap/bias, and voltage regulators.\n\nIn-depth knowledge of transistor mismatch, linearity, stability, low-power and low-noise techniques.\n\nExperience designing circuits in advanced FinFET technologies.\n\nProficient in AMS design flows, tools, and methodologies like Cadence schematic capture, Virtuoso, Spectre, layout, and analog behavioral modeling.\n\nDetailed oriented, with excellent problem-solving skills, communication skills, and the ability to work collaboratively in a fast-paced, team environment.\n\n#LI-DNP\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nTaiwanLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Analog Design Engineer", "company": "Lattice", "location": "Taipei, Taiwan", "date_posted": "2026-09-22", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Taipei-Taiwan/Analog-Design-Engineer-4_R-100804", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nThe Analog IC Design Engineer is responsible for the design and development of analog, mixed-signal IC circuit blocks from initial specification and architecture to final, post-silicon verification to ensure specifications are met.\n\nResponsibilities include:\nAnalog, mixed-signal circuit design and simulation.\n\nWork with mask designers to deliver physical design.\n\nIntegration of analog/mixed-signal blocks into large, complex, digital chips.\n\nDefine bench-level test plans for post-silicon characterization.\n\nPost-silicon measurements, characterization, and debug.\n\nLead/mentor junior engineers.\n\nQualifications:\nBS, MS, and/or PhD in Electrical Engineering or related fields.\n\nMultiple years of experience working in analog/mixed-signal circuit design (BSEE, 5+ years, MS 3+ years, PhD 2+ years).\n\nProven design experience in most of the following analog, mixed-signal circuits: SerDes receivers/transmitters, low-jitter PLLs, oscillators, phase interpolators, ADC/DAC, high speed clock distribution, bandgap/bias, and voltage regulators.\n\nIn-depth knowledge of transistor mismatch, linearity, stability, low-power and low-noise techniques.\n\nExperience designing circuits in advanced FinFET technologies.\n\nProficient in AMS design flows, tools, and methodologies like Cadence schematic capture, Virtuoso, Spectre, layout, and analog behavioral modeling.\n\nDetailed oriented, with excellent problem-solving skills, communication skills, and the ability to work collaboratively in a fast-paced, team environment.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nTaiwanLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Sr Principal Software Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-09-22", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Sr-Principal-Software-Engineer_R53100", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nPosition: Sr. Principal Software Engineer\nGrade: T5\nExperience: 12- 16 Years\nLocation: Bangalore/Noida\n\nJob Responsibilities:\nR&D support of application and product engineers for customer problems and requests. This consists of problem analysis, debugging and fixing, or the development of new features and enhancements to improve synthesis results with respect to timing, area and power.\nThis job will suit applicants looking to continue their software engineering career in an intellectually stimulating and challenging problem domain.  There is a significant research element to the work that Cadence does that is truly innovative; we don’t know what the answers are when we start out!\nMentoring and support will be provided to the successful candidate to both enable contribution to the large EDA problem domain and to develop their programming skills into professional software engineering skills.\nJob Qualifications:\nBE/BTech/ME/MTech- Computer Science or others\nRequired Skills\nThe candidate should have hands-on experience in RTL Coding. The candidate should be able to\nwrite, update, and optimize register-transfer level code using System Design Guide standards in VHDL or Verilog.\nrun functional simulations (using Xcelium), static timing analysis, and design-for-test checks to find bugs.\nvalidate, test, and investigate performance/accuracy issues in the simulator.\n \nKnowledge of Design-For-Test (DFT) and/or Memory-Built-In-Self-Test (MBIST) is a plus.\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Lead digital verification engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-09-22", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Lead-digital-verification-engineer_R-10065589", "is_hardware": true, "platform": "workday", "jd_text": "Summary:\nWe are seeking a Lead Digital Verification Engineer to join NXP’s NVM IP design group in Bangalore, India. This role involves leading and managing verification activities for a diverse NVM IP portfolio of L-NVM, RRAM and MRAM, developing and maintaining verification flow and environment, and collaborating with NXP product design teams to deliver high-quality, scalable NVM IP solutions across multiple business verticals.\n\nJob Responsibility:  \n·       Responsible for the pre-silicon verification of non-volatile memory controller modules.\n·       Responsible for defining digital verification strategy and plan for IP modules.\n·       Interface to Digital design teams to understand functionality and application of the IP subsystem, SoC system.\n·       Responsible for executing verification plan according to the product specification and verification requirements defined.\n·       Responsible for developing, debugging and running System Verilog UVM based verification environment for RTL/netlist simulation.\n·       Define and develop test cases in an appropriate verification framework. Create stimulus and assertions, run simulation, debug test cases on the design models (RTL, power aware RTL, gate level), run regression, collect and analyze code/functional coverage.\n\n Job Qualification: \n·       Bachelor’s degree or above in Microelectronics, Electronics, Electrical Engineering, Computer Science or relevant disciplines, with 8+ years of experience.\n·       Understanding of SoC architecture and functionality\n·       Understanding of directed and constrained random verification methodology\n·       Good knowledge in UVM, Verilog, System Verilog, Shell\n·       Good software programming skills\n·       Good knowledge in Scripting like Perl, TCL or Python is a plus\n·       Understanding of AI-Powered developer assistance tools\n·       Good communication skills to interact with teams across the globe and work independently\n\nMore information about NXP in India...\n\n#LI-29f4", "jd_status": "stored"}, {"title": "Principal Engineer, Design Verification Engineering", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-09-22", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Principal-Engineer--Design-Verification-Engineering_R265647", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nAnalog Devices is seeking Digital Design Principal Verification Engineer, who will be responsible for design verification of highly integrated solutions and products in a multifunctional team. You will be working on driving real revenue growth on the next generation of Intelligence at the Edge products across multiple products and business units.\nAbout ADI:\nAnalog Devices, Inc. is a leading global high-performance analog technology company dedicated to solving our customers' most complex engineering challenges. We play a critical role at the intersection of the physical and digital world by providing the building blocks to sense, measure, interpret, connect, and power devices and systems. We design, manufacture, test, and market a broad portfolio of solutions, including integrated circuits (ICs), software and subsystems that leverage high-performance analog, mixed-signal and digital signal processing technologies. We embrace a culture of innovation and collaboration to push the state of the art.\n \nAbout the Role\nLead design verification team for SOC or subsystem design pre silicon verification.  The candidate will be responsible for formulating verification strategies, Define verification architecture, Flow, Methodology and leading, driving and completing verification of large integrated products. As a senior team member, it is expected that he/she will lead and influence verification methodologies within both DBU and ADI.   The candidate is also encouraged to participate in cross company technical initiatives as well as patent and publish work where possible.\nResponsibilities\nLead end-to-end SoC verification for complex digital SoCs, driving execution from planning to signoff.\nVerify complex microprocessor-based designs, AI/ML accelerators, and high-speed peripherals using advanced verification methodologies.\nDefine and drive team execution by planning tasks, tracking progress, and providing technical leadership, mentoring, and guidance.\nCollaborate closely with architecture and design teams to define requirements and align on verification deliverables and dependencies.\nDrive pre-silicon readiness by aligning with emulation, FPGA, and software teams to cover post-silicon validation scenarios early.\nDevelop and execute end-to-end system-level use cases for comprehensive functional validation.\nArchitect and implement scalable UVM-based testbenches, DV flows, and methodologies.\nDefine and review test plans; ensure closure of functional and code coverage across block, subsystem, and SoC levels.\nWork cross-functionally with emulation, FPGA, firmware, and system teams to ensure full-system correctness.\nApply formal verification techniques for IP and subsystem-level validation.\nLead NoC/interconnect verification and ensure robust data flow across the SoC.\nPerform performance verification and system-level analysis across real-world use cases.\nDrive innovation in verification strategies to meet aggressive schedules and quality goals.\nDefine overall verification strategy based on product requirements and design specifications, leveraging modern techniques such as formal, emulation, portable stimulus, and virtual platforms.\n \nRequirements\nB.Tech/M.Tech with 12+ years of experience in digital pre-silicon verification, including leadership across IP, subsystem, or SoC-level DV.\nStrong understanding of SoC/Subsystem architectures with hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development, debugging, and methodology implementation.\nProven track record in verification closure using functional and code coverage metrics across block, subsystem, and SoC levels.\nExpertise in NoC, bus, and interconnect verification, along with coverage analysis and optimization.\nExperience in architecting scalable testbench environments and defining robust DV flows and methodologies.\nStrong background in power-aware verification (UPF), including power analysis and optimization.\nHands-on experience with formal verification, including flow definition, connectivity, and functional property checking.\nSolid protocol knowledge and verification experience across high-speed and low-speed interfaces such as I2C, SPI, Ethernet, UART, AXI/AHB, DMA, and SVI3.\nExperience in security and safety verification, ensuring compliance with secure design and functional safety requirements.\nFamiliarity with gate-level simulations with timing annotation (GLS).\nStrong expertise in test planning, constrained-random verification, assertions, and transaction-level modeling.\nGood understanding of processor-based systems (ARM, RISC-V, Tensilica), AI/ML accelerators, and proficiency in C/C++, SystemC, and scripting (Python/TCL/Shell).\nExposure to mixed-signal/analog verification (ADC/DAC/PLL/PHY) is a plus.\nExcellent communication and leadership skills with the ability to collaborate across global teams and drive verification innovation.\nStrong problem-solving mindset with the ability to quickly learn and adopt new technologies\n \n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Staff Engineer, Design Verification Engineering", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-09-22", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Staff-Engineer--Design-Verification-Engineering_R265643", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nPosition Requirements:\nMinimum BTech/BE degree in Electrical/Electronics/Computer science\n8+  years of solid  digital logic design experience in hands-on and/or technical leadership.\nStrong technical orientation to lead the activities -architecting and Design of key digital blocks in SoC Designs.\nMust have worked with cross-functional product development teams and the designs must be realized in Silicon (ASIC tapeouts, *not* FPGA)\nHands-on experience in the development of optimal micro-architecture by analyzing power, performance, and area tradeoffs\nExperience with Lint, CDC, formal equivalence, ECO flows and scripting\nStrong  Knowledge in Processor/SoC architecture.\nGood verbal and written communication skills to logically drive the  discussions effectively with teams spread geographically\nExperience in  technically mentoring junior engineers\nExperience with participating in Post Silicon issue debug is a definite plus\nKnowledge of DSP fundamentals will be an added advantage.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "ASIC Verification Engineer, Staff Level", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-22", "url": "https://careers.synopsys.com/job/bengaluru/asic-verification-engineer-staff-level/44408/100992953920", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nYou have spent years in verification trenches where the difference between a clean signoff and a late-stage respin comes down to the testbench you built three months ago. You know that coverage numbers mean nothing if the corner cases are still hiding, and you are the engineer who finds them before tapeout. You think in layers: block-level behavior, subsystem integration, protocol compliance, and the edge cases that only show up when three things go wrong at once.\nWorking in UVM is second nature to you. You do not just write tests, you build environments that catch real bugs and make the next verification cycle faster. Debugging is not a chore for you, it is a puzzle you actually enjoy solving, whether that means tracing through waveforms at 2am or writing a Python script to parse regression logs and surface the pattern everyone else missed.\nYou have worked on real IP, the kind that ships in millions of devices, and you understand what it takes to get from 'mostly works' to 'ready for customer integration.' At Synopsys, you will verify DesignWare IP that powers everything from mobile processors to data center silicon, and the quality bar you hold will matter.\n\nWhat You'll Be Doing\nVerify IP blocks and subsystems across DesignWare product lines, developing and executing verification plans, test scenarios, checkers, assertions, and functional coverage models for your assigned areas\nBuild and enhance UVM-based verification environments that support block-level and subsystem-level testing, regression automation, and coverage closure\nDebug complex functional failures across IP domains like Ethernet, USB, PCI Express, or other industry-standard protocols, identifying root causes and driving resolution with design and architecture teams\nAnalyze regression results, track coverage metrics, and identify gaps or risks that could affect signoff quality or schedule\nWrite scripts and automation utilities in Python or similar languages to improve debug efficiency, regression analysis, test development, and coverage closure\nCollaborate with cross-functional teams including design, firmware, quality, and architecture to clarify requirements, resolve technical issues, and align on verification strategy\nApply AI-assisted techniques where appropriate to accelerate debug workflows, optimize regression cycles, or improve test generation and coverage analysis\n\nThe Impact You Will Have\nDeliver high-quality, customer-ready DesignWare IP by catching critical bugs early and ensuring thorough verification coverage across your assigned blocks and subsystems\nReduce time-to-signoff by building reusable verification infrastructure, improving regression efficiency, and identifying risks before they become schedule blockers\nStrengthen the quality and reliability of Synopsys IP that powers next-generation AI, mobile, automotive, and data center silicon products used by customers worldwide\nEnable faster debug and root cause analysis across the team by developing automation tools, sharing technical knowledge, and improving verification workflows\nSupport predictable project execution by maintaining clear verification plans, tracking progress against coverage and quality goals, and communicating risks early\nContribute to Synopsys leadership in the era of pervasive intelligence by helping verify the IP building blocks that enable advanced AI and compute architectures\nImprove team execution and engineering practices through dependable collaboration, peer reviews, documentation, and knowledge sharing\n\nWhat You'll Need\nBachelor's or Master's in Electrical, Electronics, or Computer Engineering with 5+ years of hands-on IP or SoC verification experience (or MS with 3+ years)\nStrong proficiency in SystemVerilog and UVM, VMM, or OVM methodologies, with real project experience developing verification environments, test plans, checkers, assertions, and functional coverage\nHands-on experience with industry-standard simulators such as VCS and associated debug tools, including waveform analysis and regression infrastructure\nDemonstrated ability to debug complex functional failures, analyze regression results, track issues to closure, and support verification signoff activities\nExperience writing scripts or automation utilities in Python, Perl, or shell to improve verification productivity, debug efficiency, or regression analysis\nPractical understanding of verification planning, coverage analysis, quality criteria, and what it takes to reach signoff on real IP or SoC projects\nExperience with DesignWare IP or similar synthesizable IP verification projects is a strong plus, as is familiarity with protocols such as Ethernet, USB, or PCI Express\nExposure to AI-assisted methods for debug, regression optimization, test generation, or coverage closure is desirable\n\nWho You Are\nYou can look at a failing regression and know within 15 minutes whether it is a testbench issue, a design bug, or a corner case no one thought to cover\nYou write verification code that other engineers can actually understand and reuse six months later without needing to ask you how it works\nYou push back when a verification plan is too vague or a signoff criterion does not match the actual risk, and you do it in a way that moves the conversation forward\nYou are comfortable working across time zones and teams, clarifying requirements with architects in one meeting and debugging with design engineers in the next\nYou do not wait for perfect documentation or complete specs, you ask the right questions, fill in the gaps, and keep moving without creating downstream confusion\nYou share what you learn, whether that is a debug technique, a coverage trick, or a script that saves the team three hours a week\n\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\n\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Sr Staff ASIC Verification Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-22", "url": "https://careers.synopsys.com/job/bengaluru/sr-staff-asic-verification-engineer/44408/100992953904", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years verifying complex IP and you know the difference between a verification plan that looks complete on paper and one that actually catches the corner case that would have escaped to silicon. Ownership is not a buzzword for you, it is how you work. When you take on an IP or subsystem, you see the entire arc from architecture through signoff, and you know which risks matter in week two versus week twenty.\nYou do not wait for someone to tell you the methodology is broken. You see it, you fix it, and you bring the rest of the team along. Leading without a title comes naturally because people trust your judgment and your ability to translate a messy verification problem into a plan that actually closes coverage. You have debugged enough failing tests to know when to dig deeper and when to step back and rethink the approach.\nMentorship matters to you, not as a checkbox but because you remember the engineer who showed you how to think about verification strategy, and you want to be that person for someone else. At Synopsys, you will work on DesignWare IP that powers the next generation of silicon, and the verification quality you drive will be the difference between a product that ships and one that does not.\nWhat You'll Be Doing\nOwn verification for a major IP block, subsystem, or cross-IP methodology from architecture definition through final signoff and customer delivery\nDefine verification strategy, planning, architecture, and signoff criteria for complex IP projects including Ethernet, USB, and similar industry-standard protocols\nLead technical execution across verification teams by setting objectives, tracking milestones, managing risk, and driving coverage and quality closure\nApply AI-assisted verification techniques to intelligent debug, regression analytics, test generation, and coverage closure to measurably reduce cycle time and improve defect detection\nBuild and drive reusable verification infrastructure, UVM environments, and methodology improvements that scale across multiple IP domains and projects\nMentor verification engineers on test planning, debug strategies, coverage analysis, and verification best practices while fostering technical growth across the team\nCollaborate with design, architecture, firmware, and quality teams to align verification deliverables with project goals and ensure high-quality IP releases\nThe Impact You Will Have\nDeliver thoroughly verified, customer-ready DesignWare IP that reduces integration risk and increases confidence for silicon teams building next-generation products\nDrive measurable improvements in verification efficiency including faster coverage closure, shorter regression cycles, reduced debug time, and fewer escaped defects\nAdvance verification methodologies and reusable infrastructure that improve execution quality and delivery predictability across IP projects\nStrengthen the technical capability of the verification organization by mentoring engineers and establishing best practices that scale\nReduce project risk by identifying verification gaps early, optimizing processes, and ensuring robust signoff criteria are met before release\nEnable Synopsys to maintain leadership in IP quality and reliability during the era of pervasive intelligence and AI-powered silicon design\nContribute to the success of customers who depend on Synopsys IP to power critical functions in their chips, from data centers to automotive to mobile devices\n\nWhat You'll Need\nBS or BE in Electrical or Electronics Engineering with 8+ years of IP or SoC verification experience, or MS with 6+ years\nDemonstrated ownership of verification for complex IP blocks, subsystems, or cross-project methodologies with a track record of delivering measurable quality and coverage results\nProven ability to lead verification teams and projects through technical influence, expertise, and collaboration rather than formal management authority\nDeep hands-on expertise in UVM, VMM, or OVM methodologies applied to real verification environments at unit and system levels\nStrong proficiency in SystemVerilog, industry-standard simulators like VCS, and associated debug tools used in complex IP verification workflows\nPractical experience applying AI-assisted methods to debug, regression optimization, test generation, or verification closure activities\nExperience with DesignWare IP or similar synthesizable IP verification, and familiarity with protocols such as Ethernet, USB, or PCI Express is a strong plus\n\nWho You Are\nYou lead through expertise and influence, not authority, and engineers follow your technical direction because they trust your judgment and your ability to solve hard problems\nYou own complex verification areas end to end, from defining strategy and architecture through executing the plan, managing risks, and driving signoff without needing constant oversight\nYou can explain a verification bottleneck, a coverage gap, or a project risk to a design lead or program manager in two sentences without losing the technical nuance that matters\nYou combine strategic thinking with attention to detail, knowing when to zoom out to assess methodology and when to dive into a waveform to find the root cause\nYou mentor engineers by sharing not just what to do but how to think about verification problems, coverage strategies, and trade-offs in a way that builds their capability over time\nYou adapt quickly in evolving project environments, shifting priorities, and ambiguous requirements, and you help the team stay focused on what actually moves the needle toward delivery\n\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Principal Field Applications Engineer – Memory Characterization", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-22", "url": "https://careers.synopsys.com/job/bengaluru/principal-field-applications-engineer-memory-characterization/44408/100975183568", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nWe are seeking an experienced and highly motivated Principal Applications Engineer to support deployment and adoption of advanced memory characterization solutions at leading semiconductor companies worldwide.\nThis role combines deep technical expertise in memory design, characterization, circuit simulation, and library generation with strong customer engagement and technical leadership skills. The successful candidate will serve as a trusted advisor to customers, helping them develop, validate, and optimize memory characterization methodologies while working closely with R&D, Product Management, and worldwide field teams.\nThe ideal candidate will have extensive experience with memory design and characterization flows and hands-on knowledge of industry-standard characterization tools such as LiberateMX, PrimeLib, SiliconSmart, or similar solutions. Experience with memory circuit simulation and signoff technologies including HSPICE, PrimeSim XA, CustomSim, Spectre, NanoTime, and PrimeTime is highly desirable.\n\nWhat You'll Be Doing\nCustomer Engagement & Technical Leadership\nServe as the primary technical interface for strategic semiconductor customers deploying memory characterization solutions.\nLead customer evaluations, proof-of-concepts, benchmarks, and production deployments.\nWork directly with customer memory design, characterization, CAD, methodology, and library teams to understand requirements and drive successful adoption.\nProvide technical leadership during customer escalations and resolve complex issues involving memory design, SPICE simulation, characterization, library generation, and signoff validation.\nDeliver technical presentations, methodology reviews, workshops, and training sessions.\nServe as a trusted technical advisor helping customers improve characterization quality, runtime, scalability, and deployment readiness.\nDrive competitive displacement opportunities involving migration from alternative solutions such as LiberateMX and other characterization environments.\nCoordinate cross-functional efforts involving Applications Engineering, Product Management, R&D, and customer engineering teams.\nTravel as needed to support key customer engagements, deployments, and strategic initiatives.\n\nTechnical Responsibilities\nSupport characterization of SRAMs, register files, ROMs, embedded memories, custom memory macros, and memory compilers.\nDevelop and optimize memory characterization methodologies across advanced process technologies.\nDebug and resolve characterization, modeling, simulation, convergence, and library quality issues.\nDrive validation and correlation activities for timing, power, leakage, and variation-aware models.\nAssist customers in deploying scalable production characterization flows.\nCollaborate with R&D to reproduce customer issues and influence future product enhancements.\nDevelop best practices, reference methodologies, and technical collateral for customer adoption.\n\nThe Impact You Will Have\nEnable leading semiconductor companies to deploy production-ready memory characterization flows that reduce tapeout risk and improve library quality\nAccelerate customer adoption of advanced memory modeling techniques including variation-aware characterization, CCS timing, CCS noise, and statistical analysis\nResolve critical customer escalations that directly impact tapeout schedules and product success at strategic accounts\nInfluence the direction of Synopsys memory characterization and simulation products based on real-world customer requirements and deployment feedback\nBuild long-term technical relationships with memory design and CAD teams at top-tier semiconductor companies worldwide\nExpand Synopsys footprint in memory characterization by winning competitive evaluations and driving migrations from alternative toolsets\nContribute to the development of industry best practices and reference flows that raise the bar for memory characterization quality and efficiency\n\nWhat You'll Need\nCharacterization Tool ExpertiseExperience with one or more of the following:\nPrimeLib , \nSiliconsmart, \nLiberateMX, \nSolido\nCustom or in-house memory characterization environments\n\nSimulation & Signoff Expertise\nExperience with:\nHSPICE\nPrimeSim XA\nCustomSim\nSpectre\nNanoTime\nPrimeTime\nFineSim or equivalent simulation technologies\n\nAdvanced Modeling & Library Views\nKnowledge of:\nNLDM\nCCS Timing\nCCS Noise\nLVF\nVariation-aware characterization methodologies\nStatistical timing and power analysis\n\nAdditional Experience\nAdvanced node characterization and validation\nMemory compiler qualification and deployment\nHigh-capacity simulation methodologies\nMachine learning or automation techniques applied to characterization flows\nCustomer-facing applications engineering experience within EDA or semiconductor industries\n\nWho You Are\nDeep expertise in memory design and characterization.\nStrong hands-on experience with characterization tools such as PrimeLib, LiberateMX, SiliconSmart, or equivalent solutions.\nExpertise with simulation technologies including HSPICE, PrimeSim XA, CustomSim, Spectre and NanoTime.\nStrong understanding of signoff methodologies and downstream consumption flows.\nProven customer engagement experience supporting strategic semiconductor accounts.\nThe ability to communicate effectively with engineers, technical managers, architects, and executive stakeholders.\nA passion for solving difficult customer problems and turning customer requirements into product improvements.\nExperience with scripting in python, tcl and AI experience preferred\n\nThe Team You'll Be Part Of\nYou will be part of the Customer Application Services organization supporting memory characterization solutions globally. You will collaborate closely with field applications engineers, R&D teams working on PrimeLib and simulation technologies, Product Management, and customer-facing teams across regions. Your work will directly support strategic semiconductor customers deploying memory IP and characterization flows for advanced process nodes.\n\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior Design Verification Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-22", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25016996", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n Texas Instruments is seeking Design Verification Engineer. In this role you will confirm the accuracy of designs for analog and mixed signal electronic parts, components, or integrated circuitry for analog and mixed signal electronic equipment and other hardware systems before pattern generation/mask development. The role will require working independently from the product development team who designed the devices to confirm adherence to known design rules, procedures, and best practices. You will be required to undertake complete ownership of IP/Full chip DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis.\n\n This includes:\n\n Active involvement with architecture team during the spec definition phase\n\n Verification strategy definition along with Verification plan to meet 100% spec to regression traceability along with signoff metrics\n\n ip/Full chip verification covering functional and firmware scenarios in RTL and GLS.\n\n DV Environment ownership: TB development/enhancements including checkers and coverage monitor definitions along with DV flow updates as per the project needs. Develop and maintain comprehensive verification environments using UVM\n\n Active collaboration with cross functional teams - Architecture, RTL, PD, DFT, Systems, Analog, FW and Application teams to ensure comprehensive verification of specific IP/Subsystem/SOC starting from spec definition till post silicon verification closure activities\n\nQualifications\nMinimum requirements\n\nMinimum of 5+ years of experience in Digital Design Verification.  with a Bachelor or master’s degree in EE/ECE/CS or related specializations\n\n   -Excellent debugging skills with SystemVerilog/VHDL/VAMS designs, with understanding of testbench creation for full chip solutions.\n\n Must have good understanding of analog concepts to create behavioral models for Analog IPs in System Verilog, needed for signal chain verification.\n\n   - Experience in Motor control for BLDC/BSM motor driver devices including commutation, sensor less control and feedback systems are an added advantage.\n\nWell versed with setting up nad debugging, Gate level simulations/Formal verification methodologies.\n\nGood knowhow of cadence tools for Design verification activities is an advantage.\n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Software Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-22", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25017908", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n The DLP Products Organization has openings for Embedded Software Engineer.  In this role, you'll design and develop real-time SW to control our family of DLP Controllers. You'll write code that tells the Controller how to operate in revolutionary new ways. You will work closely with other functions like systems, applications engineering, marketing to collaborate and solve business problems. If you are passionate about embedded systems & software, this is the place to be as you get to work on a complete system that has electronics, optics and mechanics that has its applications across Industrial, Automotive and Display end equipment.\n\nIn addition, software engineers might work directly with customers on any issues that arise and deliver on-going support along with regular software releases, which includes quality assurance and release management activities.\n\nAs a Software Engineer, some of your responsibilities may include:\n\nRequirements definition, design, development, test, integration, and support of embedded software (e.g. operating system software, device drivers, software frameworks, algorithmic libraries etc.) and software development tools (compilers, simulators, IDEs, etc.)\n\nFollowing established software development methodology and practices defined for the business\n\nDeveloping and applying machine learning algorithms to edge applications, which may include using AI coding assistant to develop embedded software\n\nSupporting pre-silicon design and requirements as well as software validation activities\n\nImpacting hardware architecture requirements from a software usage, compatibility, performance, and reuse potential perspectives\n\nCreating and maintaining customer collateral for software products and deliverables\n\nWorking closely with TI teams (silicon, hardware, software teams) and customers as part of the normal software life-cycle\n\nQuality assurance and configuration/release management\n\nQualifications\nMinimum qualifications:\n\n •    2+ years industry experience in software development on embedded devices.\n\n •    Bachelor’s/master’s degree in EE / ECE / CSE\n\n •    Proficient in C/C++ with experience in development and deployment of applications on embedded platforms\n\n •    Adequate knowledge of hardware, read schematics and use lab equipment like scopes, logic analyzers and so on \n\n •    Good SW debugging skills. Able to identify software/hardware issues with minimal iterations\n\n •    Ability to multi-task, work independently, and take initiative to seek clarification and guidance when required \n\n •    Ability to work in teams and collaborate effectively with people in different functions including controller design, software, applications, and field teams.\n\n •    Demonstrated good analytical and problem-solving skills, and a knack for automation of repeated tasks. \n\n •    Ability to take initiative and drive for results, persistence to overcome barriers\n\nAdditional Preferred Qualifications:\n\n The ideal candidate also has one or more of the following qualifications:\n\n •    Experience in embedded RTOS platforms\n\n •    Experience of scripting using Python\n\n •    Well versed with software development tools like Git, static code analyzer tools.\n\n •    Quality conscious and able to develop and deploy unit, system and regression tests and automation test scripts.\n\n •    Experience in using Lab equipment like Oscilloscope, Logic Analyzers, Video generators\n\n •    Experience working on Image processing and other algorithms\n\n •    Experience in using AI in day-to-day SW development to improve productivity\n\n •    Experience in developing, implementing, and verifying products involving Functional Safety (ISO26262), HARA\n\n •    Experience in Automotive ASPICE SW Development, MISRA C, Dynamic Analysis, DFMEA\n\nKey responsibilities:\n\n •    Design and develop Embedded Software for DLP Controllers and associated peripherals including industrial and automotive products that may involve safety and security considerations. \n\n •    Work hand in hand with Controller, FPGA, Algorithms, tools, and applications team to define needs, influence system decisions and design the product to meet the needs. \n\n •    Follow processes defined to meet the project goals and improve on them. \n\n •    Collaborate with our Worldwide DLP team to enable the program objectives are met as per plan\n\n •    Act like an owner to everything you work on and demonstrate commitment and best outcome. \n\n •    Creates design documentation and associated application and user guides\n\n •    Ensure code coverage and adhere to code quality guidelines.\n\n •    Maintenance and support change requests on the existing SW platforms\n\n •    Debug and support co-work with Customers and Applications team as needed\n\n •    Come up with unit and system level test plans and procedures and develop test scripts\n\n •    Analyze test results to ensure correct functionality, determine root causes of failures and recommends corrective action.\n\n •    Ensure lead and the manager is updated on the program progress, anticipated risks and other dependencies as required on a timely manner.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "STA Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-22", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018127", "is_hardware": true, "platform": "oracle", "jd_text": "About ASM Auto:\n\nASM (Application specific Microcontroller) business powers automotive and industrial MCU across multiple applications. ASM is now working on next generation Automotive MCU platform for all kind of vehicle applications e.g. Traction motor control, Charging, Lighting and Heating control, IC Engine management etc. This platform will churn out multiple differentiated products for Zonal networking in Software defined Vehicles (SDV) and superior real time control for EV Cars. Great opportunity to be part of this grounds up platform development across process nodes, IPs and SoCs.\n\nhttps://www.ti.com/applications/automotive/overview.html\n\n \n\nWhat will you be doing in this role as a STA Engineer?\n\nAs an STA engineer in the team, you will be part of the STA team responsible for analysis and timing closure of the automotive MCU Cores.\n\nQualifications\nWhat do we expect from you? \n\nBachelor or Master’s degree in Electrical engineering.\n\n3+ years’ experience in STA roles\n\nExperience with constraints development of block level designs and at the chip level too\n\nGood understanding of concepts like:\n\nMargins, OCV, timing corners\n\nGroup and Path based analysis\n\nFunctional and Test Mode constraints merging \n\nIO STA: Deriving constraints from chip/protocol interface specs and analysis\n\nILM/ timing models for blocks\n\nCrosstalk analysis\n\nHands on working experience with one or more of the below areas:\n\nExperience with planning, setting up and managing the STA runs for design (preferably at the chip level)\n\nExperience with analysis of reports, deriving fixes and working with the PD team to drive the timing ECOs\n\nWorking with DFT team to understand the DFT architecture and help derive the test mode constraints\n\nGood working knowledge of timing signoff tools like Primetime or Tempus\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Senior Digital Design Verification Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-22", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018088", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n  Texas Instruments is seeking Design Verification Engineer. In this role you will confirm the accuracy of designs for analog and mixed signal electronic parts, components, or integrated circuitry for analog and mixed signal electronic equipment and other hardware systems before pattern generation/mask development. The role will require working independently from the product development team who designed the devices to confirm adherence to known design rules, procedures, and best practices. Additional job functions include analyzing equipment to establish operating data and conducting experimental tests and evaluating results to confirm the device meets all requirements in the specifications. You may also run software simulations, selecting components and equipment based on analysis of specifications and reliability. As a Design Verification Engineer you may also review vendor capability to support product development. Requires a BS degree or equivalent experience in the design of equipment, components or circuitry.\nWho are we and what do we do?\nThe advanced circuits and power solution business is known for delivering industry leading custom IC system solutions including display and touch power products, charger power products, camera PMICs, power path devices, sensing devices and high-performance communication interface products. Our products integrate precision signal-chain and highly efficient power components in ultra-small form factors that enable TI’s best-in-class customer to translate their ideas to high value products that revolutionize the personal electronics market. \n\n  In this team, you will get to work with, and learn from incredibly talented technical leaders, who have influenced TI technology, productivity and way of working in a creative and impactful way. You will get to directly interact with one of TI’s valued and high-volume customers, by way of intense technical reviews and architecture discussions! \n\n  By enabling designs that are highly impactful to TI revenue and working with a critical customer on a versatile set of products, you will find yourself on an accelerated career path. \n\n   \nAbout the job\nIf you are looking to join an ingenious, vigorous & ambitious team that consistently delivers groundbreaking technologies into the custom mobile electronics world, here is an opportunity for you!\n\n \n\nWhat will you be doing in this role?\n\nVerification Strategy: Drive verification strategy by creating detailed test plans, test cases, and checkers, and developing comprehensive chip-top testbenches.\n\nUVM Architecture: Develop UVM environments from the ground up, including agents, drivers, monitors, and scoreboards.\n\nFull-Cycle Execution: Execute RTL and Gate-Level Simulations (GLS). Run regressions and track functional/code coverage (Block, Expression, Toggle, FSM) to ensure 100% closure. Implement SVAs and coverage models for protocols such as I2C, ASI, SPI, and UART.\n\nTechnical Debugging: Resolve complex design and testbench issues using advanced debugging and problem-solving techniques.\n\nPost-Silicon Support: Collaborate with Product and Application Engineering to support ATE functional pattern generation and silicon characterization.\n\nCross-Functional Collaboration: Partner with Architecture, Design, and Firmware teams to ensure successful product execution.\n\nQualifications\nMinimum requirements:\n\nMinimum education Master's or Bachelor's degree in electrical engineering\n\nMinimum of 5 years of experience\n\nCore Competencies: Expertise in SystemVerilog (SV) and UVM methodologies.\n\nTools: Proficiency in Cadence environments (e.g., Xcelium, vManager, JasperGold).\n\nCommunication: Strong interpersonal skills for collaborating with global cross-functional teams and stakeholders.\n\nFormal Verification (FV): Experience with Formal Property Verification (FPV), connectivity checks, and unreachability (UNR) analysis for top-level sign-off.\n\nCDC/RDC: Proficiency in writing and debugging Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) assertions.\n\nLow Power Verification: Experience with UPF (Unified Power Format) and power-aware simulations.\n\nPreferred Qualifications:\n\nAutomation: Proven ability to automate verification flows and repetitive tasks using Python, Perl, or Shell scripting.\n\nMethodology Innovation: Ability to drive improved verification methodologies, collaborate with EDA vendors, and implement AI-driven verification techniques.\n\nMixed-Signal: Familiarity with AMS (Analog Mixed-Signal) verification environments is a plus.\n\nTechnical Leadership: Proactive approach to driving results, managing time effectively, and rapidly mastering new systems and processes.\n\nCollaboration: Strong analytical, interpersonal, and communication skills, with a proven ability to build relationships with global stakeholders and cross-functional teams.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Senior Digital Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-22", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018089", "is_hardware": true, "platform": "oracle", "jd_text": "Who are we and what do we do?\n\nThe advanced circuits and power solution business is known for delivering industry leading custom IC system solutions including display and touch power products, charger power products, camera PMICs, power path devices, sensing devices and high-performance communication interface products. Our products integrate precision signal-chain and highly efficient power components in ultra-small form factors that enable TI’s best-in-class customer to translate their ideas to high value products that revolutionize the personal electronics market. \n\n  In this team, you will get to work with, and learn from incredibly talented technical leaders, who have influenced TI technology, productivity and way of working in a creative and impactful way. You will get to directly interact with one of TI’s valued and high-volume customers, by way of intense technical reviews and architecture discussions! \n\n  By enabling designs that are highly impactful to TI revenue and working with a critical customer on a versatile set of products, you will find yourself on an accelerated career path. \n\n   \n\nAbout the job\n\nIf you are looking to join an ingenious, vigorous & ambitious team that consistently delivers groundbreaking technologies into the custom mobile electronics world, here is an opportunity for you!\nChange the world. Love your job.\nYou will play a pivotal role in delivering the industry-leading custom IC systems that power the next generation of electronics. By integrating precision signal chains and highly efficient power components into ultra-small form factors, you will help our most valued customers revolutionize the personal electronics market. In this role, you will work alongside world-class technical leaders and engage directly with key customers through intense architecture reviews. By solving high-impact design challenges, you will drive significant revenue and accelerate your professional growth while building technology that changes how the world connects and powers its devices.\n\n  \n\nWhat will you be doing in this role?\n\nDigital Design Execution: Drive all aspects of the digital design flow (RTL, DFT, Synthesis, STA, and PnR) for complex, highly integrated mixed-signal products.\n\nStrategic Planning: Define design development strategies to achieve on-time delivery while meeting aggressive performance, power, and area (PPA) targets.\n\nArchitecture & Micro-architecture: Lead the definition of top-level architectures and develop detailed micro-architecture for various digital sub-modules.\n\nPre-Silicon Verification: Partner with AMS and DMS verification teams to ensure thorough functional coverage; collaborate with PD and DV teams to debug and optimize designs.\n\nPost-Silicon Support: Support silicon validation, test program development, and application-level debugging to ensure successful product rollout.\n\nTechnical Leadership: Mentor team members, manage daily design challenges, and engage in high-level technical discussions with customers and stakeholders.\n\nCross-Functional Collaboration: Work closely with System, Analog, Physical Design, and Test teams to ensure seamless, integrated product development.\n\nQualifications\nMinimum requirements:\n\n5 years of relevant experience\n\nA thorough understanding of digital logic design\n\nFamiliarity with the Verilog language and simulators\n\nA good understanding of analog functionality and exposure to analog IC design methods\n\nAbility to solve problems using a systematic approach\n\nPreferred qualifications:\n\nExperience with System Verilog\n\nDemonstrated strong analytical and problem solving skills\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nStrong time management skills that enable on-time project delivery\n\nDemonstrated ability to build strong, influential relationships\n\nAbility to work effectively in a fast-paced and rapidly changing environment\n\nAbility to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Senior Silicon Validation Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-22", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018077", "is_hardware": true, "platform": "oracle", "jd_text": "About TI \n\n Texas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world’s brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We’re committed to building a better future – from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. Put your talent to work with us – change the world, love your job! \n\nWho are we and what do we do?\n\nThe advanced circuits and power solution business is known for delivering industry leading custom IC system solutions including display and touch power products, charger power products, camera PMICs, power path devices, sensing devices and high-performance communication interface products. Our products integrate precision signal-chain and highly efficient power components in ultra-small form factors that enable TI’s best-in-class customer to translate their ideas to high value products that revolutionize the personal electronics market. \n\n In this team, you will get to work with, and learn from incredibly talented technical leaders, who have influenced TI technology, productivity and way of working in a creative and impactful way. You will get to directly interact with one of TI’s valued and high-volume customers, by way of intense technical reviews and architecture discussions! \n\n By enabling designs that are highly impactful to TI revenue and working with a critical customer on a versatile set of products, you will find yourself on an accelerated career path. \n\n  \n\nAbout the job \n\nIf you are looking to join an ingenious, vigorous & ambitious team that consistently delivers groundbreaking technologies into the custom mobile electronics world, here is an opportunity for you!   \n\nSenior Silicon Validation Engineer\n\nLocation: Bangalore, India\n\nWhat will you be doing in this role?\n\nDevelop validation board, schematics and layout, matching it with customer use-case & applications. The validation boards include - modularization of the Val board for generic flow, solving mixed-signal challenges, scalability of HW for many setups and most importantly closeness to the customer EVMs. \n\nBuild, design, and document the full validation plan. The validation plan needs a detailed understanding of not only the device but also the system environment.\n\nDefine the Validation Strategy in terms of Hardware, Software and Instrumentation\n\nBuilding Validation test cases and implementing them on different scripting languages. (i.e. Python, Test stand, lab view etc)\n\nDefine, build the automation strategies and implement them through methodology, circuit, script and hardware innovations.   \n\nBring the device on the bench; Perform system level and parametric test on the bench with a strong break-the-part mentality.\n\nClose collaboration with system and design teams to understand the device issues and bugs and find the SW-level workaround for the fix.\n\nDebug device and setup-related issues and drive the issue to closure independently.\n\nPerform correlation study between ATE and bench board char results. \n\nEngaging on customer issues and fixes with application engineers, to help them understand the device better, help to fix the issues and provide modifications if any tweaks are needed. This is done in collaboration with Application engineers.\n\nQualifications\nBasic Requirements (Must-Haves)\n\nBachelor’s degree in Electrical Engineering or related field of study\n\n3+ years of silicon validation experience for mixed signal devices.\n\n \n\nPreferred Skills & \"Good to Have\" (Innovation & Automation)\n\nDemonstrates hardware debugging skills, schematic and PCB layout design.\n\nExcellent time management; Strong written and verbal communication skills\n\nExperience in simulating and designing inverters and/or DCDC converters\n\nExpertise in tools e.g. Simplis, Matlab, Altium, PSPICE. \n\nProficient in different scripting languages. (i.e. Python, Test stand, lab view etc)\n\nSchematic generation and layout performed in Altium\n\nPhysical layout management, signal grounding and routing tradeoffs, optimization\n\nMust budget time, manage schedule and complete complex design tasks on time\n\nMust have depth of experience and meticulous approach to ensure high-quality results\n\nMust account for limitations of system-level specifications, testability, and debug\n\nMust work well with colleagues and customers to foster a highly creative, interesting, productive, and fun working environment.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Senior Analog Mixed Signal DV Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-22", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018078", "is_hardware": true, "platform": "oracle", "jd_text": "About TI \n\n  Texas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world’s brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We’re committed to building a better future – from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. Put your talent to work with us – change the world, love your job! \n\nWho are we and what do we do?\n\nThe advanced circuits and power solution business is known for delivering industry leading custom IC system solutions including display and touch power products, charger power products, camera PMICs, power path devices, sensing devices and high-performance communication interface products. Our products integrate precision signal-chain and highly efficient power components in ultra-small form factors that enable TI’s best-in-class customer to translate their ideas to high value products that revolutionize the personal electronics market. \n\n  In this team, you will get to work with, and learn from incredibly talented technical leaders, who have influenced TI technology, productivity and way of working in a creative and impactful way. You will get to directly interact with one of TI’s valued and high-volume customers, by way of intense technical reviews and architecture discussions! \n\n  By enabling designs that are highly impactful to TI revenue and working with a critical customer on a versatile set of products, you will find yourself on an accelerated career path. \n\n   \n\nAbout the job \n\nIf you are looking to join an ingenious, vigorous & ambitious team that consistently delivers groundbreaking technologies into the custom mobile electronics world, here is an opportunity for you!   \n\nSenior Analog Mixed-Signal (AMS) Verification Engineer\n\nLocation: Bangalore, India\n\nExperience: 3–10 Years\nWhat will you be doing in this role?\n\nVerification Strategy: Develop detailed coverage-driven Verification Plans by collaborating closely with System, Application, and Design teams.\n\nModelling & Simulation: Create high-fidelity analog behavioural models using Verilog-A, Verilog-AMS, Wreal (RNM) or EENet to enable efficient top-level simulation.\n\nEnvironment Development: Build and enhance mixed signal testbenches using a combination of schematic, models, and RTL.\n\nCheckers & Assertions: Implement real-time analog checkers and post-processing checker strategies to ensure functional correctness.\n\nFull-Cycle Verification: Execute RTL and Gate Level Simulations (GLS), running regressions and tracking functional coverage goals until tape-out.\n\nCollaboration: Work with Digital DV, Analog Designers, and Post-Silicon Validation teams to debug complex issues and ensure successful product delivery.\n\nQualifications\nBasic Requirements (Must-Haves)\n\nEducation: Bachelor’s or Master’s degree in Electrical Engineering (EE) or Electronics and Communication Engineering (ECE) \n\nExperience: Minimum 3 years of hands-on experience in Analog Mixed-Signal (AMS) design verification.  \n\nModelling Skills: Proficiency in analog behavioural modelling using Verilog-AMS, Verilog-A, or Wreal.  \n\nVerification Flow: Direct experience with mixed-signal verification involving a combination of schematic, behavioural models, and RTL.  \n\nTool: Strong command of Cadence Virtuoso/AMS Designer toolsets and debug environments or other standard mixed-signal simulation tools\n\nCommunication: Clear ability to present technical analysis and conclusions to internal stakeholders and business leaders.  \n\nPreferred Skills & \"Good to Have\" (Innovation & Automation)\n\nAdvanced DV: Knowledge of SystemVerilog (SV) and UVM, as the top-level environments are built on these frameworks.  \n\nAutomation: Proficiency in scripting (Python, Perl, or Shell) to automate simulation flows and data analysis. Exposure and interest in building AI-driven verification methodologies. \n\nDomain Expertise: Experience in signal processing, PMICs, or high-speed communication interfaces.  \n\nSilicon Interaction: Experience in silicon debug and working alongside silicon validation teams. \n\nStandard protocols exposure: Verification experience with I2C, SPI, UART, ASI etc.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Lead Analog Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-22", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018079", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\n This is a great opportunity to be part of an established team that's continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electronics, mobile computing and communications.\n\nWho are we and what do we do?\n\nThe advanced circuits and power solution business is known for delivering industry leading custom IC system solutions including display and touch power products, charger power products, camera PMICs, power path devices, sensing devices and high-performance communication interface products. Our products integrate precision signal-chain and highly efficient power components in ultra-small form factors that enable TI’s best-in-class customer to translate their ideas to high value products that revolutionize the personal electronics market. \n\n In this team, you will get to work with, and learn from incredibly talented technical leaders, who have influenced TI technology, productivity and way of working in a creative and impactful way. You will get to directly interact with one of TI’s valued and high-volume customers, by way of intense technical reviews and architecture discussions! \n\n By enabling designs that are highly impactful to TI revenue and working with a critical customer on a versatile set of products, you will find yourself on an accelerated career path. \n\n  \n\nAbout the job If you are looking to join an ingenious, vigorous & ambitious team that consistently delivers groundbreaking technologies into the custom mobile electronics world, here is an opportunity for you!   Senior Analog Design Engineer\n\nLocation: Bangalore, India\n\nExperience: 5+ Years\n\nWhat will you be doing in this role?\n\nAnalog Chip/Sub-section/IP architect and design with complete ownership and responsibility from definition to release to manufacturing.\n\nDirect, guide and participate in activities of a research or technical design function responsible for designing, developing, modifying and evaluating electronic parts, components, integrated circuits for a variety of applications.\n\nProviding design guidance to team members as needed, developing schedules and monitoring progress throughout the project.\n\nEvaluate intermediate and final results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives.\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout.\n\nCollaborate with Design Verification teams during the pre-PG phase of a project to ensure completion of all technical tasks before PG.\n\nWork with systems engineers, application engineers and assisting in the definition of the product to meet customer needs.\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production.\n\nInterface and lead discussions with the customer and/or TI field sales/field applications teams to understand customer designs, problems and support as required.\n\nActively participate in hiring, developing and evaluating personnel to ensure efficient operation of the organization and growth of the individuals into leader.\n\nQualifications\nBasic Requirements (Must-Haves)\n\nBachelor’s & Master’s degree in Electrical Engineering or related field of study\n\n5+ years of analog circuit design.\n\n  Preferred Skills & \"Good to Have\" \n\nActive involvement with a customer. Candidate would be expected to interact and collaborate with a sense of ownership with customers and all product development team members including design, layout, systems, verification, validation, test and program management\n\nIC system partitioning and architectural tradeoff analysis\n\nBlock level topology selection, hand analysis, and IC transistor level implementation\n\nSchematic generation and simulation on modern CAD tools (Cadence tool set)\n\nWorst case identification, top level simulation, Monte Carlo analysis, and simulation data analysis\n\nExpertise in tools e.g. Spectre, Simplis, Matlab and AMS\n\n  System level understanding and analysis; and the ability to translate requirements to an IC spec level\n\nPhysical layout management, signal grounding and routing tradeoffs, die area optimization\n\nPost layout parasitic extraction and simulation, verification of all IC level performance metrics\n\nTop level verification, block level modelling, top level simulation\n\nKnowledge of device physics and process technologies tradeoffs that are applicable to Power IC design\n\nMust budget time, manage schedule and complete complex IC design tasks on time\n\nMust have depth of experience and meticulous approach to assure high quality results\n\nMust account for limitations of system level specifications, testability, debug, characterization, production and yield targets in the IC design phase.\n\nMust work well with colleagues and customers to foster a highly creative, interesting, productive and fun working environment.\n\nOrganizational Skills: Ability to work well with internal cross functional teams. Must successfully and appropriately interface with external customers. Project management, time management, multi-tasking, problem solving and communication (written and oral) are important skills in this role. Must be able to manage assigned tasks with minimal supervision.\n\nTeam and People Skills: Candidate must be team oriented and must be able to work with TI-internal and external groups (systems, test, sales, marketing, customers, etc.) to resolve issues and generate business success. The ability to work well with others and to perform in a team environment is essential.\n\nProjects and Deliverables: The main deliverable is the timely release of meticulously analysed and simulated IC designs or sub-sections of designs for custom designs with tight schedules. These designs should lead to cost-effective, high quality, bug-free products that fully meet our customer’s end-system requirements.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Test Manager", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-22", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018093", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n  Are you looking to grow your career in production testing at one of the leading semiconductor companies in the world? At Texas Instruments (TI) a Production Test Engineer ensures manufactured components and assembled products meet company standards and objectives. You'll develop and implement testing and evaluation methods and create test plans based on production specifications and requirements. You'll use your talent to perform testing and compiling and analyzing data for review and identification of manufacturing and production issues.\nWho are we and what do we do?\nThe advanced circuits and power solution business is known for delivering industry leading custom IC system solutions including display and touch power products, charger power products, camera PMICs, power path devices, sensing devices and high-performance communication interface products. Our products integrate precision signal-chain and highly efficient power components in ultra-small form factors that enable TI’s best-in-class customer to translate their ideas to high value products that revolutionize the personal electronics market. \n\nIn this team, you will get to work with, and learn from incredibly talented technical leaders, who have influenced TI technology, productivity and way of working in a creative and impactful way. You will get to directly interact with one of TI’s valued and high-volume customers, by way of intense technical reviews and architecture discussions! \n\nBy enabling designs that are highly impactful to TI revenue and working with a critical customer on a versatile set of products, you will find yourself on an accelerated career path. \n\nResponsibilities include:\n\nUtilize analog circuit analysis and Automated Test Equipment debug knowledge to troubleshoot test, quality, and device performance issues\n\nDevelop test processes, fixtures and software for automated test equipment for optimized production use\n\nEstablish and influence next-generation test solutions that help achieve the lowest obtainable costs on future products\n\nFacilitate and support new multi-factory manufacturing test and assembly flows\n\nAnalyze test solution robustness through correlated performance and sameness verification techniques\n\nPerform yield analysis and work with fabs for yield improvements where applicable\n\nLead Silicon Test & Validation development activities with product ownership and responsibility from definition to release to manufacturing.\n\nDirect, guide and participate in activities of a research or technical function responsible for silicon char, production testing, qualification, developing, modifying and evaluating electronic parts, components, integrated circuits for a variety of applications.\n\nMake assignments for team members, providing technical guidance as needed, developing schedules and monitoring progress throughout the project.\n\nEvaluate intermediate and final results of projects during the development phase and during silicon evaluation, to ensure accomplishment of technical objectives.\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in electrical engineering, electrical & computer engineering, mathematics, physics or a related field of study\n\nXX years' work related experience\n\nExperience with USP and Testware, Eagle 364/500, LTX Fusion, Catalyst, Agilent 407x, Ultraflex\n\nATE expertise\n\nProbe card hardware and circuit design experience\n\nSoftware development experience\n\nPreferred qualifications:\n\nExperience with ATE plaforms including:ETS364, ETS500, LTX Fusion HFI, LTX Fusion HT, Teradyne Catalyst, Teradyne UltraFlex, Agilent 4062 and 4071\n\nExperience with Agilent customer framework features and scripting\n\nKnowledge of Mbayse analysis for both TP and MP\n\nKnowledge of EDGE probe release system and probe build documentation\n\nStrong verbal and written communication skills\n\nDemonstrated strong analytical, critical thinking, and problem solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbility to work effectively in an interrupt-driven, fast-paced and rapidly changing environment\n\nDemonstrated ability to build strong, influential relationships\n\nProblem solving skills, including meticulous attention to details\n\nAbility to communicate effectively across functional boundaries and with upper management\n\nAbility to work in stressful situations and arrive at creative and effective solutions\n\nAbility to think strategically\n\nOrganizational Skills: Ability to work well with internal cross functional teams. Must successfully and appropriately interface with external customers. Project management, time management, multi-tasking, problem solving and communication (written and oral) are important skills in this role. Must be able to manage assigned tasks with minimal supervision.\n\nTeam and People Skills: Candidate must be team oriented and must be able to work with TI-internal and external groups (systems, test, sales, marketing, customers, etc.) to resolve issues and generate business success. The ability to work well with others and to perform in a team environment is essential.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Senior Test Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-22", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018094", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n Are you looking to grow your career in production testing at one of the leading semiconductor companies in the world? At Texas Instruments (TI) a Production Test Engineer ensures manufactured components and assembled products meet company standards and objectives. You'll develop and implement testing and evaluation methods and create test plans based on production specifications and requirements. You'll use your talent to perform testing and compiling and analyzing data for review and identification of manufacturing and production issues.\n\nResponsibilities include:\n\nUtilize analog circuit analysis and Automated Test Equipment debug knowledge to troubleshoot test, quality, and device performance issues\n\nDevelop test processes, fixtures and software for automated test equipment for optimized production use\n\nEstablish and influence next-generation test solutions that help achieve the lowest obtainable costs on future products\n\nFacilitate and support new multi-factory manufacturing test and assembly flows\n\nAnalyze test solution robustness through correlated performance and sameness verification techniques\n\nPerform yield analysis and work with fabs for yield improvements where applicable\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in electrical engineering, electrical & computer engineering, mathematics, physics or a related field of study\n\nXX years' work related experience\n\nExperience with USP and Testware, Eagle 364/500, LTX Fusion, Catalyst, Agilent 407x, Ultraflex\n\nATE expertise\n\nProbe card hardware and circuit design experience\n\nSoftware development experience\n\nPreferred qualifications:\n\nExperience with ATE plaforms including:ETS364, ETS500, LTX Fusion HFI, LTX Fusion HT, Teradyne Catalyst, Teradyne UltraFlex, Agilent 4062 and 4071\n\nExperience with Agilent customer framework features and scripting\n\nKnowledge of Mbayse analysis for both TP and MP\n\nKnowledge of EDGE probe release system and probe build documentation\n\nStrong verbal and written communication skills\n\nDemonstrated strong analytical, critical thinking, and problem solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbility to work effectively in an interrupt-driven, fast-paced and rapidly changing environment\n\nDemonstrated ability to build strong, influential relationships\n\nProblem solving skills, including meticulous attention to details\n\nAbility to communicate effectively across functional boundaries and with upper management\n\nAbility to work in stressful situations and arrive at creative and effective solutions\n\nAbility to think strategically\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Senior Analog Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-22", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018080", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \nTexas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\nThis is a great opportunity to be part of an established team that's continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electronics, mobile computing and communications.\nWho are we and what do we do?\nThe Advanced Circuits and Power Solutions business is known for delivering industry-leading custom IC system solutions, including display and touch power products, charger power products, camera PMICs, power path devices, sensing devices, and high-performance communication interface products. Our products integrate precision signal chains and highly efficient power components into ultra-small form factors, enabling TI’s best-in-class customers to translate their ideas into high-value products that revolutionize the personal electronics market.\nIn this team, you will work with and learn from incredibly talented technical leaders who have influenced TI’s technology, productivity, and way of working in creative and impactful ways. You will directly interact with one of TI’s most valued, high-volume customers through intense technical reviews and architecture discussions!\nBy enabling designs that are highly impactful to TI revenue and working with a critical customer on a versatile set of products, you will find yourself on an accelerated career path.\nAbout the job\nIf you are looking to join an ingenious, vigorous & ambitious team that consistently delivers groundbreaking technologies into the custom mobile electronics world, here is an opportunity for you!\n\nIn this role, responsibilities may include:\nParticipate in the review and sign-off of designs developed within the team as well as other products developed across TI.\nRepresent TI's technical leadership in front of leading customers.\nDrive TI's technology roadmap while collaborating with Process, Packaging, EDA, and other stakeholders within and outside TI.\nDefine and drive industry-leading best practices within TI.\nAct as an Analog Chip/Sub-section/IP architect and designer, with complete ownership and responsibility from definition to release and manufacturing.\nDirect, guide, and participate in research or technical design functions responsible for designing, developing, modifying, and evaluating electronic parts, components, and integrated circuits for a variety of applications.\nProvide design guidance to team members as needed, developing schedules and monitoring progress throughout the project.\nEvaluate intermediate and final results of projects during the design phase and silicon evaluation to ensure the accomplishment of technical objectives.\nWork with and provide guidance to physical designers, and monitor the progress of IC layout.\nCollaborate with Design Verification teams during the pre-PG phase of a project to ensure completion of all technical tasks before PG.\nWork with systems engineers and application engineers, assisting in the definition of products to meet customer needs.\nCollaborate with validation, product engineering, and test engineering teams to enable a successful transfer to production.\nInterface and lead discussions with customers and/or TI field sales/field applications teams to understand customer designs and problems, and to provide support as required.\nActively participate in hiring, developing, and evaluating personnel to ensure efficient operation of the organization and the growth of individuals into leaders.\n\nQualifications\nMinimum requirements:\n\nMasters OR Bachelor's degree in Electrical Engineering\n\n12 years of relevant experience\n\nOrganizational Skills: Ability to work well with internal cross functional teams. Must successfully and appropriately interface with external customers. Project management, time management, multi-tasking, problem solving and communication (written and oral) are important skills in this role. Must be able to manage assigned tasks with minimal supervision.\n\nTeam and People Skills: Candidate must be team oriented and must be able to work with TI-internal and external groups (systems, test, sales, marketing, customers, etc.) to resolve issues and generate business success. The ability to work well with others and to perform in a team environment is essential.\n\nProjects and Deliverables: The main deliverable is the timely release of meticulously analysed and simulated IC designs or sub-sections of designs for custom designs with tight schedules. These designs should lead to cost-effective, high quality, bug-free products that fully meet our customer’s end-system requirements.\n\nPreferred qualifications:\n\nCustomer Interaction: Active involvement with customers, with a demonstrated sense of ownership when collaborating with customers and all product development team members (including design, layout, systems, verification, validation, test, and program management).\n\nArchitectural Expertise: Proficiency in IC system partitioning, architectural tradeoff analysis, block-level topology selection, hand analysis, and IC transistor-level implementation.\n\nCAD & Simulation: Expert-level schematic generation and simulation using modern CAD tools (Cadence toolset), including Spectre, Simplis, Matlab, and AMS.\n\nAdvanced Analysis: Expertise in worst-case identification, top-level simulation, Monte Carlo analysis, and simulation data analysis.\n\nSystem Integration: Strong system-level understanding and analysis, with the ability to translate requirements into IC-level specifications.\n\nPhysical Design: Experience in physical layout management, including signal grounding, routing tradeoffs, die area optimization, post-layout parasitic extraction, and simulation to verify all IC-level performance metrics.\n\nVerification: Proficiency in top-level verification, block-level modeling, and top-level simulation.\n\nDevice Physics: Knowledge of device physics and process technology tradeoffs applicable to Power IC design.\n\nProject Execution: Proven ability to budget time, manage schedules, and complete complex IC design tasks on time with a meticulous approach to ensure high-quality results.\n\nDesign for Manufacturing (DFM): Ability to account for system-level specification limitations, testability, debug, characterization, production, and yield targets during the IC design phase.\n\nInterpersonal & Leadership:\n\nAbility to foster a highly creative, interesting, productive, and fun working environment for colleagues and customers.\n\nAbility to establish strong relationships with key stakeholders, both internally and externally.\n\nStrong verbal and written communication, interpersonal, analytical, and problem-solving skills.\n\nAbility to take initiative, drive for results, and quickly ramp up on new systems and processes.\n\nStrong time management skills to ensure on-time project delivery and effective collaboration across different functions\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Senior Mixed Signal DV Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-22", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018083", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n Texas Instruments is seeking Design Verification Engineer. In this role you will confirm the accuracy of designs for analog and mixed signal electronic parts, components, or integrated circuitry for analog and mixed signal electronic equipment and other hardware systems before pattern generation/mask development. The role will require working independently from the product development team who designed the devices to confirm adherence to known design rules, procedures, and best practices. Additional job functions include analyzing equipment to establish operating data and conducting experimental tests and evaluating results to confirm the device meets all requirements in the specifications. You may also run software simulations, selecting components and equipment based on analysis of specifications and reliability. As a Design Verification Engineer you may also review vendor capability to support product development. Requires a BS degree or equivalent experience in the design of equipment, components or circuitry.\n\nWho are we and what do we do?\n\nThe Advanced Circuits and Power Solutions business is known for delivering industry-leading custom IC system solutions, including display and touch power products, charger power products, camera PMICs, power path devices, sensing devices, and high-performance communication interface products. Our products integrate precision signal chains and highly efficient power components into ultra-small form factors, enabling TI’s best-in-class customers to translate their ideas into high-value products that revolutionize the personal electronics market.\n\nIn this team, you will work with and learn from incredibly talented technical leaders who have influenced TI’s technology, productivity, and way of working in creative and impactful ways. You will directly interact with one of TI’s most valued, high-volume customers through intense technical reviews and architecture discussions!\n\nBy enabling designs that are highly impactful to TI revenue and working with a critical customer on a versatile set of products, you will find yourself on an accelerated career path.\n\nAbout the job\n\nIf you are looking to join an ingenious, vigorous & ambitious team that consistently delivers groundbreaking technologies into the custom mobile electronics world, here is an opportunity for you!\n\nWhat will you be doing in this role?\n\nStrategic & Technical Leadership\n\nStrategic Leadership: Drive TI's technology roadmap by collaborating with Process, Packaging, EDA, and other key stakeholders both within and outside the company.\n\nIndustry Influence: Define and implement industry-leading best practices within TI and represent the company's technical leadership in front of key customers.\n\nDesign Governance: Participate in the critical review and sign-off of designs developed within the team as well as cross-product designs across TI.\n\nCross-Functional Collaboration: Partner closely with Architecture, Design, and Firmware teams to ensure successful product execution.\n\nVerification Strategy & Architecture\n\nVerification Strategy: Drive the verification strategy by creating detailed test plans, defining test cases, checkers, and coverage metrics. Develop comprehensive, coverage-driven verification plans in close collaboration with System, Application, and Design teams.\n\nUVM Architecture: Lead the ground-up development of UVM-based verification environments, including the implementation of agents, drivers, monitors, and scoreboards.\n\nMixed-Signal Methodology: Build and enhance mixed-signal testbenches using a combination of schematics, behavioral models, and RTL.\n\nMixed-Signal & Modeling Expertise\n\nModeling & Simulation: Create high-fidelity analog behavioral models using Verilog-A, Verilog-AMS, Wreal (RNM), or EENet to enable efficient top-level simulation.\n\nAnalog Checkers & Assertions: Implement real-time analog checkers and post-processing checker strategies to ensure functional correctness across domains.\n\nProtocol Expertise: Verify standard communication protocols such as I2C, ASI, SPI, and UART.\n\nExecution, Debug, & Support\n\nFull-Cycle Execution: Execute RTL and Gate-Level Simulations (GLS), manage regressions, and track functional and code coverage (Block, Expression, Toggle, FSM) to ensure 100% closure through tape-out.\n\nTechnical Debugging: Utilize advanced debugging and problem-solving skills to resolve complex design and testbench issues.\n\nPost-Silicon Support: Collaborate with Product and Application Engineering teams to support ATE functional pattern generation and silicon characterization.\n\nQualifications\nMinimum requirements:\n\nMinimum education Master's or Bachelor's degree in electrical engineering\n\nMinimum of 12 years of experience\n\nBasic Requirements (Must-Haves)\n\nCore Competencies: Strong expertise in SystemVerilog (SV) and UVM methodologies.\n\nMixed-Signal Modeling: Proficiency in analog behavioral modeling using Verilog-AMS, Verilog-A, or Wreal (RNM).\n\nMixed-Signal Verification: Direct experience with mixed-signal verification flows involving a combination of schematics, behavioral models, and RTL.\n\nTooling:\n\nProficiency with Cadence simulation tools (e.g., Xcelium, vManager, JasperGold).\n\nStrong command of Cadence Virtuoso, AMS Designer, or equivalent industry-standard mixed-signal simulation and debug environments.\n\nFormal Verification (FV): Hands-on experience with Formal Property Verification (FPV), connectivity checks, and Unreachability (UNR) analysis for top-level sign-off.\n\nClock & Reset Domains: Deep understanding of Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) assertions, including the ability to write and debug them.\n\nLow Power Verification: Practical experience with UPF (Unified Power Format) for low-power verification and power-aware simulations.\n\nCommunication: Excellent interpersonal skills with the ability to present complex technical analysis and conclusions clearly to global cross-functional experts and business leaders.  \n\nPreferred Skills (Innovation & Automation)\n\nAutomation & Scripting: Proven ability to automate verification flows and data analysis using Python, Perl, or Shell scripting.\n\nMethodology Innovation: Ability to drive advanced verification methodologies and collaborate with EDA vendors to enhance tool capabilities.\n\nEmerging Technologies: Experience or strong interest in implementing AI/ML-driven verification methodologies to improve coverage and efficiency.\n\nAdvanced DV Frameworks: Deep familiarity with complex SystemVerilog and UVM-based top-level environments.\n\nDomain Expertise: Experience with signal processing, PMICs (Power Management ICs), or high-speed communication interfaces.\n\nProtocol Proficiency: Hands-on verification experience with standard protocols such as I2C, SPI, UART, or ASI.\n\nPost-Silicon Integration: Experience in silicon debug and collaborating closely with silicon validation teams.\n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Senior Digital PD Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-22", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018085", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n  In this position, you will be working on high-speed mixed-signal communication circuits using state-of-the art process technology, as well as be involved in the design of high performance digital circuits interfacing to leading edge analog circuitry as part of an overall system.\n\n  Your responsibilities will include RTL coding, simulation, synthesis, timing closure, verification, evaluation, debugging of high-speed communication chips both at the circuit level and behavioral level.\n\n  As a design engineer, you will prepare test methods and specifications, assist in preparation of application information, data sheets and demo boards. You will develop solutions to complex problems through assessment of various techniques and approaches. You will plan and organize work to ensure timely completion of many independent tasks with general instructions on routine tasks and with detailed instructions on new assignments.\n\n  This position involves routine communication with a highly talented team of analog and digital design engineers to solve problems and present information as well as active participation in work groups, providing ideas and collaborative teamwork.\n\nWho are we and what do we do?\n\nThe Advanced Circuits and Power Solutions business is known for delivering industry-leading custom IC system solutions, including display and touch power products, charger power products, camera PMICs, power path devices, sensing devices, and high-performance communication interface products. Our products integrate precision signal chains and highly efficient power components into ultra-small form factors, enabling TI’s best-in-class customers to translate their ideas into high-value products that revolutionize the personal electronics market.\n\nIn this team, you will work with and learn from incredibly talented technical leaders who have influenced TI’s technology, productivity, and way of working in creative and impactful ways. You will directly interact with one of TI’s most valued, high-volume customers through intense technical reviews and architecture discussions!\n\nBy enabling designs that are highly impactful to TI revenue and working with a critical customer on a versatile set of products, you will find yourself on an accelerated career path.\n\nAbout the job\n\nIf you are looking to join an ingenious, vigorous & ambitious team that consistently delivers groundbreaking technologies into the custom mobile electronics world, here is an opportunity for you!\n\nWhat will you be doing in this role?\n\nStrategic Leadership & Industry Authority\n\nTechnology Roadmap & Vision: Own the strategic direction of physical design at TI, establishing the methodologies, quality benchmarks, and technical judgments that form the foundation for TI's next generation of products.\n\nIndustry & Customer Influence: Serve as TI's technical authority in high-stakes customer engagements and partner discussions, communicating complex physical design decisions with authority and clarity.\n\nDesign Governance & Quality Authority: Act as the global quality authority for the digital backend, owning the sign-off for the complete flow from RTL to GDSII and setting the quality standards that projects across TI measure themselves against.\n\nCross-Functional Orchestration: Orchestrate deep collaboration with EDA, Library, Memory, and IP teams to eliminate flow bottlenecks, align execution priorities, and raise the implementation bar across all TI projects.\n\n  \n\nArchitectural Influence & Methodology Innovation\n\nUpstream Design Shaping: Embed \"design-for-implementation\" thinking into early-stage architecture and front-end decisions to mitigate costly backend constraints before they arise.\n\nMethodology & Flow Engineering: Define and establish TI-wide physical design methodologies and flows, ensuring they are robust, scalable, and optimized for the latest process nodes.\n\nEDA & Node Qualification: Evaluate and qualify new EDA tools and process nodes, driving adoption decisions through data-driven recommendations and rigorous benchmarking.\n\nMentorship: Elevate the physical design community at TI by mentoring engineers, standardizing implementation practices, and building lasting institutional knowledge.\n\n  \n\nTechnical Execution & Optimization\n\nEnd-to-End Flow Ownership: Independently drive the entire Physical Design lifecycle, including floorplanning, placement, CTS, routing, and full-chip implementation.\n\nTiming & Reliability Closure: Lead rigorous Static Timing Analysis (STA) and ensure total closure for EM (Electromigration), IR drop, and Physical Verification (DRC/LVS).\n\nPPA Optimization: Drive aggressive techniques to optimize Power, Performance, and Area (PPA) to ensure TI’s silicon remains industry-leading and highly competitive.\n\nClock & Reset Integrity: Analyze and influence clock, reset, and DFT architectures to ensure they are fully optimized for physical implementation and reliability.\n\nQualifications\nWhat do we expect from you? (Minimum Qualifications)\n\n12+ years of hands-on experience in Physical Design / Digital Backend implementation\n\nBachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or VLSI Design\n\nProven expertise in RTL-to-GDSII flows using industry-standard EDA tools (Synopsys and/or Cadence toolchain)\n\nDemonstrated ability to own and deliver complex designs independently from specification through signoff\n\nDeep knowledge of timing closure, power integrity, signal integrity, and physical verification (DRC/LVS/ERC)\n\nStrong understanding of process node design rules and implementation constraints\n\nExperience working with or alongside Library, Memory, and IP teams in a product development context\n\nStrong written and verbal communication skills, with experience presenting technical content to internal stakeholders or external customers\n\n \n\nPreferred Skills/ Experience\n\n12–18 years of progressive experience in physical design with increasing ownership and scope\n\nHands-on experience with mixed-signal designs — including analog-digital co-design, guard-ring strategies, substrate coupling mitigation, and mixed-signal floor planning\n\nPrior experience in a Subject Matter Expert, methodology lead, or technical architect capacity — having defined implementation standards that others adopted and built upon\n\nFamiliarity with in-house or customized EDA flow development and scripting (Tcl, Python, Perl)\n\nExperience with customer-facing roles — design reviews, technology presentations, or pre-silicon collaboration with external customers\n\nKnowledge of DFT integration within the physical design flow (scan insertion, BIST, boundary scan)\n\nExposure to power management architectures and low-power implementation techniques (multi-Vt, power gating, voltage islands)\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Digital Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-22", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25018087", "is_hardware": true, "platform": "oracle", "jd_text": "About ASM Auto:\n\nWe are seeking talented and motivated individuals to join our team in developing cutting-edge solutions with Application-Specific Microcontrollers (MCUs) for the rapidly evolving automotive industry. Our MCUs power a wide range of critical vehicle functions, including traction control, onboard charging (OBC) and DC-DC converters, advanced lighting systems, body control modules, engine management, and braking systems. Additionally, we are at the forefront of innovation with zonal microcontrollers designed to enable software-defined vehicles, paving the way for greater functionality, scalability, and efficiency. Our products shape the future of automotive technology and create impactful solutions for modern mobility challenges.\n\nhttps://www.ti.com/applications/automotive/overview.html\n\nRole: Senior Design Engineer (RTL)\n\nWe are looking for an experienced Senior RTL Design Engineer to join our team in developing cutting-edge automotive microcontroller solutions. The ideal candidate will have deep understanding of RTL design and SoC integration, particularly in the context of ARM-based architectures, and a proven ability to collaborate across multiple engineering disciplines to deliver high-quality solutions for complex systems.\n\n \n\nKey Responsibilities:\n\n•Define and develop microarchitecture for various subsystems, including CPU subsystems, low-power subsystems, and Reset & Clock Management modules.\n\n•Own SoC integration for automotive MCUs, ensuring efficient, scalable designs.\n\n•Collaborate with IP teams, Systems, and Architecture teams to derive requirements, co-develop microarchitecture, and align on design goals for IPs, subsystems, and SoC.\n\n•Work closely with cross-functional teams such as Design Verification (DV), Design for Testability (DFT), Emulation, and Physical Implementation to ensure quality deliverables.\n\n•Participate in debug sessions, design reviews, and ensure design robustness and compliance with industry standards.\n\nQualifications\nQualifications and Skills Required:\n\n•Education: Bachelor’s or Master’s degree in Electrical Engineering (EE), Electronics & Communication Engineering (ECE), Computer Science (CS), or a related specialization.\n\n•Experience: 2-5 years of hands-on experience in RTL development for IPs and SoCs.\n\nTechnical Expertise:\n\n•Experience in SoC integration with ARM processors and ARM bus architectures.\n\n•Good understanding of SoC reset and clocking architectures.\n\n•Experience with standard interfaces like SPI/QSPI, I2C, Debug/Trace, CAN, and others.\n\n•Expertise in industry-standard front-end (FE) tools and flows, including Lint, CDC, LEC, and power estimation tools such as Jasper Gold, Conformal, Joules, etc.\n\n•Knowledge of DFT concepts and ability to design for testability.\n\n•Good understanding of constraints, timing analysis, and optimization techniques.\n\n•Proficiency in system verilog and verilog.\n\n•Experience with industry-standard simulators (e.g., Incisive) and formal verification tools.\n\nSoft Skills:\n\n•Exceptional problem-solving and debugging skills.\n\n•Strong written and verbal communication skills for effective collaboration and reporting.\n\n•Ability to work in a team-oriented environment and guide junior engineers when needed.\n\n \n\nPreferred Qualifications:\n\n•Experience in automotive-grade SoC designs and compliance with ISO 26262 (Functional Safety) standards.\n\n•Familiarity with power management techniques and low-power design principles.\n\n•Knowledge of scripting languages such as Python, Perl, or TCL for automation.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "IC Verification Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-09-22", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/IC-Verification-Engineer_R027135-6", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nJob duties include:\n·       Build Test plans with all features for Block/Core/SoC and Write Functional Coverage for the features, participate in Reviews\n·       Write scalable and re-usable test benches, using the framework of the verification methodology\n·       Develop Pseudo-random tests to verify and get to full Functional Coverage\n·       Debug Regression failures, analyze Functional coverage gaps and improve tests to cover the gaps\n·       Document verification strategy including Test plans, Testbench, Random tests, etc.\n \nRequirements:\n·       Bachelor’s degree in electrical engineering or related degree with 5+ years relevant experience or master’s degree in electrical engineering or related degree with 3+ years relevant experience\n·       Must have working knowledge of System Verilog and Verification methodologies like UVM/VMM\n·       Should have good command of Object-Oriented Programming principles.\n·       Have experience writing Functional Coverage, pseudo random tests\n·       Knowledge of PCI Express protocol is a plus\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Systems and Hardware Enabling Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-22", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Systems-and-Hardware-Enabling-Engineer_JR0287240", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact :\nAs a Systems and Hardware Enabling Engineer, you will play a key role in driving the successful integration and deployment of cutting-edge Intel products and technologies. You will design, validate, and optimize solutions that meet quality and performance standards while ensuring they are ready for market. Your technical expertise and collaboration will directly contribute to delivering innovative products that empower customers and shape the future of technology.\n\nBusiness group :\nAt Intel Corporation, we are passionate about creating world-changing technology that enriches the lives of every person on earth. The Systems and Hardware Enabling team focuses on enabling and supporting solutions that leverage Intel's latest hardware and software innovations, ensuring seamless integration for our customers and partners. This group plays a vital role in advancing Intel's leadership position in technology development and driving excellence in product deployment.\n\nKey Responsibilities :\n-Provide technical support for solutions incorporating Intel products and technologies to ensure readiness for the market.\n- Drive solution design and enable industry partners for platform solution readiness.\n- Develop and implement product design, validation tools, and testing strategies to optimize quality and performance.\n- Collaborate with internal and external silicon, hardware, and software stakeholders to achieve design and production wins.\n- Evaluate, design, and develop new software and hardware fixtures for deployment and validation needs.\n- Create technical documentation, including product specifications, hardware design guides, and application notes.\n- Partner with relevant stakeholders to ensure smooth product ramp and effective integration of customer requirements.\n- Deliver product training and technical support to resolve development, testing, and production challenges rapidly.\n\nQualifications:\nRequired Qualifications:\n\n• Education: B.E./B.Tech in Electronics/Electrical/Computer Engineering or related (M.E./M.Tech preferred).\n• Experience: 3+ years in customer engineering/product applications/hardware systems in semiconductor/client platforms.\n• Technical: Strong client architecture/IO knowledge; schematic review and board-level design; lab proficiency (scopes, analyzers); bring-up/debug on x86/ARM; Python/C++ for automation.\n• Communication: Clear technical collateral; strong executive presentation and stakeholder management.\n\nPreferred Qualifications:\n•\tM.E./M.Tech/MS in EE/CE.\n•\tExperience with HSIO Interfaces\n•\tSI/PI simulation/review experience; pre-/post-silicon validation collaboration.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Senior DD Engineer", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-09-22", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Senior-DFT-Engineer_R261532", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nSenior DFT Engineer Responsibilities\nDFT architecture definitionUnderstand SoC architecture and test requirements.\nWork very closely with the lead Product/Test engineering throughout the DFT definition phase to determine efficient ways to optimize test cost and achieve high test coverage.\nDrive and optimize DFT architecture for high performance and efficiency:SCAN – scan partition, compression, at-speed, IR and low power\nMBIST for memories\nJTAG boundary scan insertion\n\nHandle responsibilities pertaining to both block and top-level activities in Hierarchical Scan.\n\nImplementationDevelop / Upgrade SCAN & MBIST Insertion flows\nDevelop appropriate timing constraints for SCAN/MBIST modes and debug timing violations\nATPG flow implementation catering to various fault models, test pattern generation\nSCAN , MBIST & BSCAN Pattern Simulation\nSolutions to test analog macros\n\nPost-Silicon bring-up/supportWork with Evaluation/Test Engineering team to bring-up patterns on ATE\nWork on failure analysis as required\nWork with the Operation team on test cost and yield improvement\n\nImprove DFT methodology to be in sync with latest best practices and technology in the industry\nWork closely with physical design team throughout the development cycle.\nShould be able to guide newly inducted team members on their bring-up on flow, methodology and execution methods in all aspects of DFT.\nRequirements\n4-8 years of industry experience in DFT domain.\nMust have experience in bringing atleast one or two products to successful production from architecture phase, scan implementation and simulations.\nMust have hands-on experience working on post-silicon activities.\nHaving working experience with tessent DFT (SCAN, Mbist, Lbist, OCC, EDT, SSN, Boundary Scan) will be preferred.\nExceptional interpersonal and communication skills are critical for working, influencing and collaborating with product development groups and CAD tool teams spread across the globe.\nScripting skills in Perl/Python/TCL and a good command over HDLs.\nCandidates with exposure to deep submicron effects and low power implementation using UPF/CPF will be at an advantage. Candidates with experience using Cadence digital implementation tools (Genus, Tempus) would be preferred.\nPrior experience of timing closure/physical design will be an added plus.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "FPGA Verification Engineer", "company": "Nokia", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-09-22", "url": "https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/39498", "is_hardware": true, "platform": "oracle", "jd_text": "In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise\n\n Join Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.\n\nInfinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group. \n\nAs an FPGA Verification engineer, you will be responsible for designing verification plans, developing environment/testbench, creating test scenarios for running simulations, coverage analysis and lab support during board bring up to ensure first time right quality of Infinera product. Candidate should be capable of handling projects independently and have a strong will to drive for solutions.\n\nResponsibilities\nDevelop and execute verification plans for high-complexity DWDM systems used in LH/ULH optical network applications.\nDesign and implement simulation environments and testbenches to validate FPGA functionality and performance.\nCreate and run functional and directed/random test scenarios to ensure comprehensive design coverage.\nPerform detailed coverage analysis and implement strategies to achieve full functional and code coverage.\nCollaborate closely with cross-functional R&D teams across multiple global locations throughout the product lifecycle.\nProvide lab support during board bring-up and assist in root cause analysis to ensure first-time-right product quality.\nIndependently manage verification projects with a proactive and solution-driven approach to meet quality and timeline goals.\n\nQualifications\nMust have 12 – 16 years of experience in developing System Verilog UVM based test environments, developing and implementing test plans – at block, sub-chip and chip levels.\nMust have strong HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform-based debugging tools.\nExposure to UVM (or similar) verification methodologies is required.\nFamiliarity with HDLs such as Verilog and scripting languages such as perl is highly desired. Working knowledge of RTL design is preferred.\nShould be conversant with technologies like the Ethernet, PCIe, I2C, SPI etc. Knowledge of telecom protocol is preferred.\nStructured and thorough with analytical and troubleshooting skills.\nGood written and oral communication skills are required.\nFlexible, innovative, self-driven and willing to take initiatives.\nHighly motivated team player with exceptional leadership capability.\n\nAbout the organization\nSome of our benefits in India:\n\nFlexible and hybrid working arrangements to support work–life balance\n\nHealth and well-being support – medical insurance for you and your family, health check-ups, life and accident insurance, well-being programs, and employee resource groups \n\nA minimum of 90 days of Maternity and Paternity Leave based on eligibility\n\nPersonal Support Service 24/7 – a confidential support channel open to all Nokia employees and their families in challenging situations\n\nCareer growth & mobility – technical career paths, job rotations, international assignments, and relocation support\n\nContinuous learning – technical certifications, mentoring programs, coaching, and digital learning platforms\n\nOpportunities to innovate and contribute through Nokia’s research and development environment\n\nRecognition programs that celebrate outstanding contributions\n\nWorkplace support – ergonomic working support and mobile device programs based on eligibility", "jd_status": "stored"}, {"title": "Sr Director, Design Verification Engineering", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-09-22", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Sr-Director--Design-Verification-Engineering_R266117", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nSr Director, Design Verification Engineering\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 25% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Experienced Engineer - ASIC Verification", "company": "Ericsson", "location": "Bangalore,Karnataka,India", "date_posted": "2026-09-21T11:51:03+00:00", "url": "https://jobs.ericsson.com/careers/job/563121772208422", "is_hardware": true, "platform": "eightfold", "jd_text": "Grow With Us\n\nAbout this opportunity\n \nWe are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport – to enable communication service providers to surpass the expectations of their end-customers.  At our state-of-the-art design centers, we don't just follow industry trends—we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, you'll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. \n\nAs part of our global R&D organization, you'll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. \n\nCreative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. You'll have the opportunity to explore advanced verification technologies alongside skilled experts.\nGlobal Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. \nWork-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. \nProfessional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere.\nAn international work environment with opportunities for professional growth and development. \nA collaborative and inclusive culture that values diversity and innovation.\n\nWhat you will do\n\nTake part in the verification of designs, whether at the block or subsystem level.\nParticipate in defining and implementing UVM-based test environments.\nSupport the creation of Verification Strategies and contribute to the development and execution of Verification Plans.\nDevelop, run, and debug test cases to ensure design quality.\nContribute to the improvement and optimization of verification methodologies.\nGenerate documentation throughout the verification lifecycle.\nCollaborate closely with other verifiers, designers, and architects.\nBuild competence in the technical domain.\nEngage in cross-team collaboration to ensure successful project delivery.\n\nThe skills you bring\n\nRequired Qualifications: \nBachelor’s degree in electrical or computer engineering.\n5+ years industry experience in ASIC IP verification using SystemVerilog and UVM.  \nExperience in / with:developing creating directed/randomized test cases.\nimplementing scoreboards, checkers, bus functional models within UVM environments.\nAMBA-based designs such as AXI and CHI.\nSystemVerilog Assertions.\n\nAdditional Requirements:\n\nExperience with Cadence or Synopsys verification suites.\nTeam-oriented, prioritizing team success within the team, across teams, and across sites over individual results.   Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment.\nHigh attention to detail and commitment to quality.\nStrong focus on meeting project deadlines and deliverables.\nProficient in English, with strong communication skills. \n\nPreferred Skills:\n\nUnderstanding of radio access systems and their components.\nExperience in low-power design verification.\nWorking knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira).\nExperience in formal verification\nExperience in verification in one or more of the following hardware domains:ARM-based real-time embedded microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces.\nImplementation of hardware-based digital signal processing systems (filters, adaptation, etc.) \n\n.\n\n“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”\n\nWhy join Ericsson?\nAt Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.\n \nWhat happens once you apply?\nClick Here to find all you need to know about what our typical hiring process looks like.\nEncouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.\nPrimary country and city: India (IN) ||\nReq ID: 772965", "jd_status": "stored"}, {"title": "Senior Engineer - ASIC Design", "company": "Ericsson", "location": "Bangalore,Karnataka,India", "date_posted": "2026-09-21T11:49:53+00:00", "url": "https://jobs.ericsson.com/careers/job/563121766780763", "is_hardware": true, "platform": "eightfold", "jd_text": "Grow With Us:\n\nAbout this opportunity:\n \nWe are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport – to enable communication service providers to surpass the expectations of their end-customers.  At our state-of-the-art design centers, we don't just follow industry trends—we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, you'll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. \n \nAs part of our global R&D organization, you'll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. \n \nCreative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. You'll have the opportunity to explore advanced design technologies alongside skilled experts. \nGlobal Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. \nWork-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. \nProfessional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere.\nAn international work environment with opportunities for professional growth and development. \nA collaborative and inclusive culture that values diversity and innovation.\n\nWhat you will do:\n\nDevelop ASIC IP blocks and subsystems, contributing to the advancement of 5G and 6G communication technology. \nTake full ownership of a design, whether at the block or subsystem level. \nGenerate comprehensive documentation throughout the design lifecycle. \nPerform digital design and conduct all RTL sign-off checks. \nContinuously enhance and optimize design methodologies and processes. \nCollaborate with IP Architects to break down requirements and create detailed IP architecture and design specifications. \nWork closely with verification engineers to review and refine verification plans. \nBuild competence in the technical domain. \nEngage in cross-team collaboration to ensure successful project delivery\n\nYou will bring\n\nRequired Qualifications:\nBachelor’s degree in electrical or computer engineering.\n10+ years industry experience in ASIC IP Design\nStrong Experience in/with:\nUnderstanding of ASIC technology, design environments, and methodologies.\nIP development from concept (High-level Spec) to Micro-architecture, RTL creation and sign-off with SystemVerilog\nRTL static sign-off tools such as SpyGlass\nUnderstanding of Synthesis and Timing concepts.\nScripting languages like TCL, Python, or similar.\nAMBA-based IP development using AXI and CHI.\nSystemVerilog Assertions\n\nAdditional Requirements:\n\nExperience with Cadence and Synopsys front-end and middle-end design suites.\nTeam-oriented, prioritizing team success within the team, across teams, and across sites over individual results.   Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment.\nHigh attention to detail and commitment to quality.\nStrong focus on meeting project deadlines and deliverables.\nProficient in English, with strong communication skills.\n \nPreferred Skills:\nUnderstanding of radio access systems and their components. Modelling in MATLAB is a plus.\nExpertise in low-power design, including specifying power intent using UPF or similar standards.\nWorking knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira).\nExperience in designing IPs for one or more of the following hardware domains:\nARM-based embedded microcontroller systems including their control and interface peripherals (Ethernet, USB, CPRI)\nWireless infrastructure specific protocols and interfaces and protocols.\nImplementation of hardware-based digital signal processing systems (filters, adaptation, knowledge of CFR, DPD, Digital up-conversion and down-conversion chains etc)\n\n.\n\n“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”\n\nWhy join Ericsson?\nAt Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.\n \nWhat happens once you apply?\nClick Here to find all you need to know about what our typical hiring process looks like.\nEncouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.\nPrimary country and city: India (IN) ||\nReq ID: 771286", "jd_status": "stored"}, {"title": "DFT Engineer", "company": "Astera Labs", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-21T02:18:41-04:00", "url": "https://job-boards.greenhouse.io/asteralabs/jobs/4723233005", "is_hardware": true, "platform": "greenhouse", "jd_text": "Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\n\n \n\nAstera Labs is hiring a Tech Lead Design Engineer to help architect and deliver the connectivity silicon powering the world's largest AI clusters. You'll own design execution on complex blocks across our purpose-built products, working at the cutting edge of PCIe, CXL, Ethernet, and emerging rack-scale interconnect technologies.\n\nThis is a high-impact technical role at a hyper-growth company. You'll partner closely with architecture, verification, DFT, and physical design teams to take features from spec to silicon, while contributing to the design methodology that scales with our roadmap. If you want to ship silicon that defines AI infrastructure, this is the team.\n\nKey Responsibilities\n\nRTL Design & Implementation\n\nOwn RTL design for assigned blocks from microarchitecture through synthesis sign-off\n\nDevelop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA\n\nDrive design reviews, lint, CDC, and timing closure activities to silicon-ready quality\n\nCross-Functional Execution\n\nPartner with architecture to translate specifications into implementation-ready microarchitecture\n\nCollaborate with verification on testplans, coverage closure, and bug triage\n\nWork with DFT and physical design teams on scan, BIST, floorplanning, and timing closure\n\nTechnical Leadership & Quality\n\nMentor junior engineers and contribute to design methodology, scripts, and best practices\n\nDebug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments\n\nDrive structured, data-driven design decisions in support of aggressive tapeout schedules\n\nBasic Qualifications\n\nBachelor's degree in Electrical Engineering, Computer Engineering, or related field\n\n5+ years of digital design experience, including at least one full chip from spec to tapeout\n\nStrong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows\n\nHands-on experience with timing closure, CDC, lint, and low-power design techniques\n\nSolid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration\n\nPreferred Qualifications\n\nMS or PhD in Electrical Engineering or Computer Engineering\n\nExperience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs\n\nFamiliarity with formal verification, emulation, or assertion-based methodologies\n\nBackground in advanced process nodes (7nm, 5nm, or below)\n\nStrong debug skills across pre-silicon and post-silicon environments\n\nSalary range is $133,200 to $185,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\n\n \nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.", "jd_status": "stored"}, {"title": "GPU Physical Design Engineer (Senior/Lead)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-21T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720934717", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Overview\nQualcomm's GPU team is seeking experienced Physical Design Engineers to drive implementation and physical signoff of next-generation high-performance GPU designs. The role involves close collaboration with RTL, STA, DFT, Power, and SoC teams to achieve aggressive PPA targets and successful tapeouts.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nMinimum Qualifications\nBachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution\n\n3+ years of experience in Physical Design/Implementation\n\nMinimum Requirements:\nPhysical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization.\n\nShould have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions.\n\nStrong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts\n\nWell versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes\n\nGood understanding of clocking architecture.\n\nShould be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc.\n\nWell versed with Tcl/Perl Scripting\n\nExperience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers.\n\nStrong problem-solving skills and good communication skills.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "GPU STA/Timing Engineer (Senior Lead/Staff)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-21T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720953651", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Overview\nQualcomm's GPU team is looking for experienced STA Engineers to drive timing signoff and closure for next-generation high-performance GPU designs. The role involves close collaboration with Architecture, RTL, Physical Design, DFT, and SoC teams to deliver best-in-class silicon products.\n\nResponsibilities\nOwn block-level and full-chip STA signoff for GPU designs.\n\nDevelop and validate timing constraints (SDC).\n\nPerform MCMM/MMMC timing analysis, timing closure, and ECO implementation.\n\nDrive setup/hold, noise, SI, and low-power timing closure.\n\nCollaborate with cross-functional teams to resolve timing issues.\n\nEnhance STA methodologies, signoff flows, and automation.\n\nMentor junior engineers and provide technical leadership.\n\nRequired Qualifications\nBS/MS in Electrical/Electronics Engineering or related field.\n\n6-10 years of experience in ASIC/SoC STA and timing signoff.\n\nStrong expertise in STA, MCMM/MMMC, SDC, timing closure, ECOs, SOCV/AOCV, and SI analysis.\n\nHands-on experience with Synopsys PrimeTime.\n\nStrong understanding of Physical Design concepts and implementation flows.\n\nProficiency in Tcl/Python scripting.\n\nPreferred Skills\nExperience with GPU, CPU, AI/ML, or high-performance SoC designs.\n\nExperience in advanced technology nodes (5nm and below).\n\nExposure to Fusion Compiler, ICC2, StarRC, Tempus, or Innovus.\n\nProven technical leadership and mentoring experience.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SOC Design Verification Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-21T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721139150", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\n\nUnderstand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.\n\nResponsible to implement and analyze system Verilog assertion and coverage(code, toggle, functional) .\n\nWork alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue.\n\nCollaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nAdhere to quality standards and good test and verification practices.\n\nB.E/B. Tech/M.E/M. Tech in electronics with 5+ year experience in verification domain.\n\nPrior work experience on IP level or Soc level.\n\nPrior work on UFS (Universal Flash Storage),Ethernet and PCIe Protocol is desirable.\n\nGood understanding of processor based Soc level verification  which includes native ,Verilog ,system Verilog and UVM mix environment.\n\nHand on experience with verification tools such as VCS, waveform analyzer and  third party VIP integration (such as Synopsys VIPs).\n\nHands on experience in UVM. C/C++ ,System Verilog verification language.\n\nGood understanding of AXI-AMBA  protocol variants.\n\nCan work with scripting language (shell, Makefile, Perl )\n\nStrong understanding of design concepts and ASIC flow.\n\nGood problem solving , analytical and debugging skill is must.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SoC Physical Design Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-21T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720745164", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nJob Description :\nBachelor's degree in Electrical Engineering with 8 to 15 years of experience in physical design.\n\nExperience managing complex Subsystem and Small team.\n\nExperience in synthesis, PnR, sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations.\n\nJob Requirement:\nExperience with demanding PPA requirement of complex sub-systeM/SOC, place and route, IP integration. \n\nExperience in low power design Implementation including UPF, multi-voltage domains, power gating. \n\nExperience with ASIC design flows and methodology of Physical design. \n\nUnderstanding of circuit design, device physics and deep sub-micron technology. Should have worked on multiple TO in advance technology nodes. \n\nPerson should also have good understanding of automation to drive the efforts to improve the PPA\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SoC STA Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-21T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720750897", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nKey Responsibilities :\nPerform block/full Modem STA and timing closure across MMMC scenarios.\nDrive setup/hold closure, ECO implementation, and timing signoff.\nAnalyze timing at each Netlist to GDS stage\nCollaborate with RTL, PD, and DFT teams to resolve timing issues.\nAnalyze noise, crosstalk, OCV/AOCV impacts and optimize critical paths.\nValidate timing constraints (SDC).\nAutomate timing flows using Tcl/Perl/Python scripts. \n\nRequired Skills :\nStrong hands-on experience in STA, Timing Closure, MMMC, SDC, ECO.\nExpertise in Synopsys PrimeTime/PTPX and Cadence Tempus\nGood understanding of Digital Design, Synthesis, Physical Design, CTS, and Routing.\nScripting skills in Tcl/Perl/Python.\nExperience with advanced technology nodes is preferred. \nHaving Physical Design experience and candidate looking for PD and STA combined ownership can apply\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NPU AI Processor Synthesis Engineer-Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-21T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720292005", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    5+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior SoC Physical Design Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-21T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721116212", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nJob Description:\nBachelor's degree in Electrical or Electronics Engineering with 2 - 4 years of experience in physical design.\n\nExperience in synthesis, PnR, sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations.\n\nJob Requirement:\nExperience with demanding PPA requirement of complex sub-syste/SOC, place and route, IP integration.\n\nExperience in low power design Implementation including UPF, multi-voltage domains, power gating.\n\nExperience with ASIC design flows and methodology of Physical design. Understanding of circuit design, device physics and deep sub-micron technology.\n\nShould have worked on multiple TO in advance technology nodes.\n\nPerson should also have good understanding of automation to drive the efforts to improve the PPA\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NSP STA/Timing Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-21T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720515866", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nResponsibilities:\nSTA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.\n\nTiming analysis, validation and debug across multiple PVT conditions using PT/Tempus.\n\nRun Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.\n\nEvaluate multiple timing methodologies/tools on different designs and technology nodes.\n\nWork on automation scripts within STA/PD tools for methodology development.\n\nGood Technical writing and Communication skills, should be willing to work in cross-collaborative environment\n\nExperience in design automation using TCL/Perl/Python.\n\nFamiliar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus\n\nFamiliar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo.\n\nEducation : B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI.\nPreferred Qualification/Skills\n7 - 14 years of experience in STA/Timing\n\nStrong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling\n\nHands-on experience with STA tools - Prime-time, Tempus\n\nHave experience in driving timing convergence at Chip-level and Hard-Macro level\n\nIn-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,\n\nKnowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)\n\nKnowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation.\n\nProficient is scripting languages – TCL, Perl, Awk\n\nBasic knowledge of device physics\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SoC FV/CLP  Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-21T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720933111", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nRequired Skills and Experience :\nWe are looking for a candidate with 5+ years of relevant experience in logical signoff and low-power structural verification for sophisticated SoC and IP development programs.\nStrong experience with low-power design and verification, including hands-on knowledge of UPF/CPF and SystemVerilog.\nHands-on experience with low-power verification tools such as Cadence Conformal Low Power (CLP) or Synopsys VCLP.\nExperience with Logic Equivalence Checking (LEC) and power-aware LEC, with strong skills in analyzing and resolving verification failures.\nAbility to effectively debug CLP/VCLP and LEC issues and drive them through closure.\nUnderstanding of synthesis and Place & Route (P&R) flows is an advantage.\nAbility to collaborate across design, verification, and implementation teams to support successful signoff of complex SoC and IP designs.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SoC Design Verification Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-21", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/SoC-Design-Verification-Engineer_JR0286727", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nIntel is looking for candidates on Contract role.\nStrong knowledge and experience in Pre-Si Verification and Emulation content execution.\nPreference for skills in Core Verification, DFD - Debug fabrics, Power management, Security, SoC verification, DDR verification, PCIE/CXL verification.\nReset, Clock, fuse flows.\nGood exposure to System Verilog, UVM\nExperience with Low power/UPF/ Regression / Coverage verification techniques.\nDemonstrate excellent Self-motivation, communication, strong problem solving and teamwork skills.\n\nQualifications:\nB.E/B.Tech/M.E/M.Tech in Electrical/Electronics/Communication Engineering with 2+ years of experience.\n\n          \n\nJob Type:\nIntel Contract Employee\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Analog Layout Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-09-21", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Analog-Layout-Engineer_R027080", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nAnalog layout designer providing onsite support for advanced nodes, working with global layout and design team.\n- Candidate should work independently on block level and IP level Analog layout design, coordinating with the circuit designer & the layout team\n- Candidate should have minimum 8+ years of hands-on experience in Analog or RF layout.\n- Should have worked on floorplan and layout for analog modules like SerDes, ADC/DAC, PLL, etc.\n- Should have worked on and top-level integration\n- Should have a good understanding of analog layout concepts for deep sub-micron processes and knowledge of fabrication process, preference will be given to FinFet experience candidates.\n- Should have a good understanding of ESD, latch-up, EM, and strong skills debugging DRC, LVS, and antenna errors.\n- Job Complexity: Works on complex issues where analysis of situations or data requires an in-depth evaluation of variable factors.  Exercises judgment in selecting methods, techniques and evaluation criteria for obtaining results. Networks with key contacts outside own area of expertise.\n - Supervision:  Determines methods and procedures on new assignments and may coordinate activities of other personnel (Team Lead).\n- Experience with Cadence tools and TSMC processes are preferred\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Staff Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-09-21", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Staff-Engineer_R027147-5", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nBroadcom Central Engineering team is looking for a Multi Skilled RTL, Verification engineer with DFT expertise. The Successful candidate will work in one or more domains of RTL, Verification, DFT for Complex Memory, IO subsystems, Hierarchical Blocks including BIST. It is a great opportunity and challenging role for the people who want to gain in-depth knowledge on end to end chip development flow with deeper expertise on RTL, Synth and Memory BIST \nResponsibilities\nRTL development and Verification for Digital subsystems, Memory Subsystems including BIST.\n\nMemory Digital Subsystems with Tessent/Embedded MBIST\n\nMBIST, ATPG, RSQ Verification and sign-off.\n\nFormal verification, Cross Clock Domain checks, Power/Timing sign off\n\nVerify complex Digital subsystems through OVM, UVM methodology, creating the Verification Suit Independently.\n\nRequirements\nHands on Experience with RTL, Synthesis,\n\nHands on experience in defining ICC/Synthesis constraints that meets timing closure needs\n\nFamiliarity with DFT flows includes MBIST, ATPG, RSQ and Verification methodologies and best practices for the DFT signoff.\n\nFamiliarity with Spyglass, LEC, CDC, and Synthesis tools DC Ultra, Fusion Compiler.\n\nFamiliarity with GLS, simulation, UVM, OVM methodologies is a big plus\n\nProficiency with Verilog NC, Verilog XL tools\n\nStrong fundamentals in digital design and Coding/Verifying  complex RTL subsystems\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "VC Formal Staff Application Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-21", "url": "https://careers.synopsys.com/job/bengaluru/vc-formal-staff-application-engineer/44408/100930292928", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in the trenches of formal verification, and you know the difference between a proof that closes and one that explodes the state space at 2am. You understand that formal is not magic, it is a precise tool that works brilliantly when applied to the right problem with the right setup, and you have developed the instinct to know which is which.\nYou are comfortable walking into a customer's verification environment, looking at their design blocks and assertion strategy, and quickly seeing where formal will shine and where it will struggle. Diagnosing why a formal run is slow or why convergence stalled does not frustrate you, it engages you. You think in terms of abstraction, state space, and proof complexity, and you can refactor a formal testbench so the tool can actually finish.\nAt Synopsys, you will work directly with customers deploying VC Formal across complex SoC and IP designs, and what you recommend will directly shape how they verify their next chip.\nWhat You'll Be Doing\nLead technical deployment of VC Formal at customer sites, assessing their verification environments and recommending formal methodologies that fit their design challenges\nAnalyze customer design blocks to identify the right candidates for formal property checking, sequential equivalence, connectivity checking, and formal coverage analysis\nDiagnose root causes of tool performance issues and design complexity bottlenecks, then optimize formal testbench modeling to achieve proof closure\nDevelop and deliver technical training on VC Formal features, product updates, and formal verification best practices\nWork with Synopsys R&D teams to communicate customer priorities and technical requirements that influence product roadmap\nApply formal verification across data path logic, math function proofs, sequential equivalence checking, and formal coverage closure\nThe Impact You Will Have\nEnable customers to catch critical design bugs earlier, reducing costly respins and time to tapeout\nDrive measurable improvements in formal tool performance and proof convergence through optimized modeling\nInfluence the VC Formal product roadmap by translating customer pain points into actionable R&D priorities\nExpand formal verification adoption by demonstrating clear ROI and building internal customer champions\nBuild reusable formal methodologies that scale across multiple customer engagements and design domains\nWhat You'll Need\n4 to 8 years of hands-on experience applying formal verification in semiconductor design or verification roles\nDeep expertise in formal property checking, including writing assertions, constraints, and assumptions for complex digital designs\nProven experience with sequential equivalence checking, formal coverage analysis, and connectivity checking methodologies\nStrong understanding of formal verification theory, including state space exploration, abstraction techniques, and proof convergence strategies\nExperience diagnosing and resolving formal tool performance issues and testbench modeling optimization\nAbility to assess customer verification environments and recommend tailored formal solutions\nWho You Are\nYou can walk into a customer meeting, listen to their verification pain points, and sketch out a formal methodology that makes immediate sense\nYou treat failed proofs as puzzles to solve, methodically working through abstraction and constraints until they close\nYou can explain why an assertion is vacuous or a constraint is overconstrained without making someone feel like they did it wrong\nYou are comfortable saying 'formal is not the right fit here' when simulation would be faster, because credibility matters more than a tool sale\nYou can manage multiple customer engagements simultaneously without dropping threads or missing commitments\nThe Team You'll Be Part Of\nApplication engineers (AEs) drive and deploy SNPS technologies at the customers and support successful usage of the products at the customers that leads to renewals and new business.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Principal Application Engineer, VC Formal", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-21", "url": "https://careers.synopsys.com/job/bengaluru/principal-application-engineer-vc-formal/44408/100930292880", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent a decade or more in verification and you know that formal is not a checkbox, it is the difference between finding a corner case bug in week two or in production six months later. You walk into a customer site, look at their design blocks and test benches, and see the problem underneath the symptoms. You ask questions that get to root cause, not surface noise.\nYou have debugged enough performance bottlenecks to know when the issue is the tool, the model, or the design itself, and you can explain the tradeoff in terms the design team will understand. You are comfortable presenting to senior engineers and equally comfortable rolling up your sleeves to optimize a formal test bench that is choking on state space explosion.\nAt Synopsys, you will work directly with customers building the most complex chips in the industry, and what you recommend will shape how they verify their designs.\nWhat You'll Be Doing\nLead technical deployment of VC Formal solutions at customer sites, assessing verification environments and recommending formal methodologies tailored to their design challenges\nAnalyze customer design blocks to identify the right targets for formal property checking, sequential equivalence checking, formal coverage analysis, and connectivity checking\nDiagnose root causes of tool performance issues, including state space explosion and convergence problems, then optimize formal test benches to achieve proof closure\nDevelop and deliver technical training to customer teams on new VC Formal features, product updates, and formal verification best practices\nWork directly with Synopsys R&D and product engineering teams to communicate customer priorities and technical requirements that influence product roadmap\nSupport customers in applying formal verification to complex logic including data path verification, math functions, and sequential equivalence across design revisions\nThe Impact You Will Have\nEnable customers to find critical bugs earlier in the design cycle, reducing costly respins and time-to-market delays\nDrive adoption of formal verification methodologies that improve verification coverage and confidence across complex SoC and IP designs\nShape the VC Formal product roadmap by translating real-world customer challenges into actionable engineering requirements\nAccelerate customer productivity by delivering training and methodologies that make formal verification accessible to teams with varying levels of expertise\nBuild long-term technical relationships with leading semiconductor companies, becoming a trusted advisor on verification strategy\nReduce tool performance bottlenecks and proof times through expert modeling and optimization, directly improving customer ROI\nWhat You'll Need\n10 to 15 years of hands-on experience in digital design verification, with deep expertise in formal verification methodologies\nStrong application knowledge of formal property checking, sequential equivalence checking, formal coverage analysis, and connectivity checking\nProven experience diagnosing and resolving formal tool performance issues, including convergence problems and proof optimization\nSolid understanding of RTL design, SystemVerilog, and verification test bench development\nExperience working directly with customers in a technical consulting, application engineering, or field engineering role\nExperience with VC Formal or equivalent formal verification tools is a strong plus\nWho You Are\nYou can walk into a customer meeting, listen to a verification challenge, and sketch out a formal methodology that makes immediate sense to the team\nYou know when to push back on a customer request that will not solve the real problem, and you can explain why in terms they respect\nYou are comfortable moving between deep technical debugging, writing formal properties, and presenting results to engineering leadership\nYou treat every customer deployment like a learning opportunity, not just for them but for the product team back at Synopsys\nYou are organized enough to manage multiple customer engagements at once and technical enough to go deep when a proof is failing\nThe Team You'll Be Part Of\nApplication engineers (AEs) drive and deploy SNPS technologies at the customers and support successful usage of the products at the customers that leads to renewals and new business.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior Engineer- STA", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-21", "url": "https://careers.arm.com/job/bengaluru/senior-engineer-sta/33099/100929942032", "is_hardware": true, "platform": "talentbrew", "jd_text": "Responsibilities:\nSupport timing constraints development and validation for functional and test modes\nPerform timing analysis and closure at block/subsystem level\nAnalyze setup and hold timing violations and work with Physical Design and Design teams for closure\nSupport timing ECO generation, implementation, and validation\nGenerate and review timing reports across different modes and corners\nSupport timing signoff activities and debug timing/constraint issues\nRequired Skills and Experience:\nGood understanding of STA fundamentals, including setup/hold, clocking, timing exceptions, and timing constraints\nHands-on experience with STA tools such as PrimeTime or Tempus\nBasic understanding of Physical Design flow, including placement, CTS, routing, and timing closure\nUnderstanding of timing ECO techniques such as cell sizing, buffering, and Vt swaps\nExposure to multi-mode multi-corner (MMMC) timing analysis\nKnowledge of advanced technology nodes is preferred\nGood scripting skills in TCL, Perl, or Python\nGood data analysis and debugging skills\nAbility to collaborate with Physical Design, RTL/Design, DFT, and Constraint teams\n2–4 years of experience in Physical Implementation, STA, or Timing Signoff\nGood communication and problem-solving skills\n \n \n#LI-BB1\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Digital Design Member of Technical Staff (MTS)", "company": "onsemi", "location": "Cork, IE", "date_posted": "2026-09-21", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506445", "is_hardware": true, "platform": "oracle", "jd_text": "About onsemi \n\nonsemi is driving innovation in power, sensing, and automotive semiconductor solutions to enable a more sustainable future. Our Treo™ platform underpins next-generation intelligent power systems for automotive and industrial markets, emphasizing safety, reliability, and scalability. \n\nRole Overview \n\nWe are seeking a senior Digital Design Member of Technical Staff (MTS) to lead and deliver digital controller IP for power, clock, and error management subsystems within the onsemi Treo™ platform. This role is a hands-on technical leadership position, focused on architecting, designing, integrating, and evolving complex digital IP that tightly interfaces with analog and mixed-signal blocks in automotive-grade SoCs. \n\nThe successful candidate will bring deep experience in automotive functional safety, digital-analog co-design, and system-level integration, while also serving as a technical mentor and thought leader within the Cork design organization. \n\n \n\nKey Responsibilities \n\nArchitect, design, and implement digital system controllers for:  \n\nPower management \n\nClock management \n\nError detection, reporting, and mitigation subsystems \n\nDevelop robust digital IP that controls and interacts closely with analog and mixed-signal blocks. \n\nOwn IP delivery from architecture through RTL, verification, integration, and silicon bring-up support. \n\nDrive and support digital-on-top product integration flows, including:  \n\nIP integration into SoC environments \n\nClocking, reset, power domain, and safety integration \n\nEnsure designs meet automotive functional safety requirements (e.g., ISO 26262 concepts such as ASIL, fault coverage, diagnostic mechanisms). \n\nCollaborate cross-functionally with:  \n\nAnalog design \n\nVerification \n\nPhysical design \n\nSystems, safety, and product engineering teams \n\nDefine and evolve IP roadmaps aligned with:  \n\nPlatform strategy \n\nProduct requirements \n\nLong-term business objectives \n\nMentor and technically guide junior and mid-level engineers, promoting best practices in design, documentation, and review culture. \n\nContribute to continuous improvement of:  \n\nDesign methodologies \n\nVerification strategies \n\nAutomation and productivity tools \n\nStay technically curious and engaged with emerging AI/ML applications in digital design, including their potential impact on RTL development, verification, and productivity. \n\n \n\nRequired Qualifications \n\n15+ years of hands-on digital design experience, primarily in ASIC or SoC development. \n\nProven experience delivering automotive IP with functional safety requirements. \n\nStrong background designing digital controllers for analog blocks (e.g., power regulators, PLLs, sensors, clocking systems). \n\nDeep understanding of system-level digital integration, including:  \n\nPower and clock domain management \n\nReset strategies \n\nError handling and safety mechanisms \n\nSolid experience with RTL design (SystemVerilog). \n\nWorking knowledge of constrained-random verification methodologies, including SystemVerilog and UVM. \n\nDemonstrated ability to work effectively as a senior individual contributor, owning complex technical problems end to end. \n\nStrong communication skills and a demonstrated willingness to mentor junior engineers. \n\n \n\nPreferred / Plus Qualifications \n\nExperience with automotive safety standards such as ISO 26262 (concept, system, or IP-level application). \n\nWorking knowledge of JIRA for task tracking and JAMA for requirements management. \n\nExposure to safety diagnostics, fault injection, or safety verification techniques. \n\nExperience contributing to platform-level IP strategies or multi-generation roadmap planning. \n\nFamiliarity with low-power design techniques and power-aware verification. \n\n \n\nWhat We Offer \n\nOpportunity to work on industry-leading automotive and power semiconductor platforms. \n\nA senior, high-impact technical role with architectural ownership. \n\nA collaborative engineering culture with strong ties between digital, analog, and system teams. \n\nCompetitive compensation and benefits. \n\nCareer growth within a global semiconductor leader, while being based in Cork’s vibrant technology ecosystem.\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "SOC Design Engineer", "company": "Lattice", "location": "Shanghai, China", "date_posted": "2026-09-21", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Shanghai-China/SOC-Design-Engineer_R-101130-1", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nAccountabilities: \n \nIdentify the domain specific requests for certain solution/application, define and develop the IP accordingly;\n\nIntegrate all IPs into SOC and verify the implementation flow;\n\nSOC level functional verification and performance evaluation based on SOC;\n\nBoard level setup/bootup;\n\nCo-work with software engineer for co-verificantion and system debug;\n\n针对具体的解决方案或者应用，评估并找出特定需求，并以此定义和开发IP；\n\n集成IP并构建合适的SOC，并验证整个实现流程；\n\nSOC级别的功能验证及性能评估；\n\n建立板级开发环境并初步启动SOC；\n\n和软件工程师合作完成软硬联合验证及系统级调试。\n\n \n\nRequired Skills\n\nMaster's degree or above, majored in ME/EE/CS etc, and experience in FPGA related design is a plus.\n\nFamiliar the concept of Embedded System (SoC) design or digital/FPGA design.\n\nFamiliar with verilog/SystemVerilog\n\nFamiliar with simulation tools like Ncsim, Modelsim/Questasim\n\nFamiliar with system bus (AXI, AHB, Wishbone etc ).\n\nExperiences in one or more of the following area will be a plus:\n\na. RISC architecture and micro-architecture (RISCV , ARM);\nb. Peripheral and legacy IP (PCIE, SPI, I2C, UART etc);\nc. Embedded  programming with C language;\nd. FPGA design flow;\nMust possess independent problem solving skills\n\nStrong written and verbal communication skills and the ability to work with multiple groups\n\nMust be a sense of responsibility and work actively\n\n研究生及以上学历，电子、通信、计算机、自动化等相关专业\n\n熟悉嵌入式系统/SOC，或数字/FPGA设计\n\n熟悉Verilog/SystemVerilog\n\n熟悉仿真工具，如Ncsim，Questasim\n\n熟悉系统总线，包括AXI，AHB，wishbone等\n\n对以下项目有所掌握的优先：\n\na. RISC体系结构和微架构（RISCV，ARM）\nb. 常用外设或IP，如PCIE, SPI，I2C，UART等\nc. 基于C的嵌入式软件编程\nd. FPGA开发流程\n独立解决问题的能力\n\n英文书写和口语能能力，能跨部门协作\n\n有强烈的责任心\n\n#LI-DNP\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nChinaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Analog Circuit Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-21", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Analog-Circuit-Design-Engineer_JR0283055-1", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nDesigns, develops, and builds analog circuits in advanced process nodes for analog and mixedsignal IPs. Designs floorplans, performs circuit design, extracts chip parameters, and simulates analog behavior models. Creates test plans to verify design according to circuit and block microarchitecture specifications and evaluates test results. Verifies functionality to optimize circuit for power, performance, area, timing, and yield goals. Collaborates cross functionally to report design progress and collects, tracks, and resolves any performance and circuit design issues. Optimizes performance, power, area, and reduces leakage of circuits. Works with architecture and layout team to design circuit for best functionality, robustness, and electrical capabilities.\n\nQualifications:\nYou must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research and relevant previous job and/or internship experience. This is an entry level position and will be compensated accordingly.\n\nMinimum Qualifications:\n\nMust have a master's degree or a PhD with experience in Electrical Engineering or any STEM related degree with analog and mixed-signal circuit design experience.1 years of school experience or knowledge in one or more of the following: Tools for schematic entry, IC layout, and SPICE simulation. Designing mixed signal circuits including DACs, RX, TX, PLLs, Filters, bias circuits, regulators, and other analog circuits.\n\nPreferred Qualifications:\n\nKnowledge of Verilog A for analog behavioral modeling, TCL, Perl, C, python or other scripting languages. Industry standard design conventions and rules in analog circuit design awareness of techniques to reduce design risk.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "ASIC Verification Engineer - Clocks", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-09-21", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/ASIC-Verification-Engineer---Clocks_JR2015795", "is_hardware": true, "platform": "workday", "jd_text": "The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification. The NVIDIA Clocks Team is committed to deliver high-quality clocking and reset logic to various units in SOC automotive and datacenter ASICs. The complexity of the clocks and resets design has increased many folds. This requires sophisticated verification to deliver a bug free clocks design to power our product lines ranging from Data Centers, Consumer graphics to Self-driving cars and the growing field of artificial intelligence. Modern clocking verification solutions need to be innovative, ensure quality in covering the complex design specifications and balance the constraints on infrastructure, re-usability, testing speed and multi-platform support.\n\nWhat you'll be doing:\nOwn validation of Clocking structures in Tegra automotive and datacenter products from start to finish, including test plan development, automation, validation flows development, coverage metrics, test execution, bug identification/fix and productization.\n\nTackle Sophisticated problems and develop a scalable solution that works across platform.\n\nHands on industry-standard tools and state of the art verification methodologies. This includes coding in System Verilog, UVM, C++, Perl, Python and NVIDIA custom compilers and tools.\n\nPartnering closely with our clocks architecture and design team to validate our clocks design.  \n\nCoordinate with internal and external teams across time zones.\n\nWhat we need to see:\nBS or MS in EE/ECE or equivalent experience.\n\n3+ years of relevant industry work experience.\n\nGood understanding of Logic Design and Architecture.\n\nExpertise in industry-standard verification flows like SV constraint random verification, UVM, Formal Verification, Coverage metrics, profiling tools, X prop, etc.\n\nExposure on block level and system-level verification.\n\nStrong coding skills in System Verilog, scripting languages (Perl/python) and C++.\n\nAbility to collaborate and work with multiple groups.\n\nPrior experience in implementing Test plans for pre-silicon platforms.\n\nUnderstanding of DFT/IST is optional.\n\nWe have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our world-class engineering teams are growing fast. If you are creative, curious, and motivated with real passion for technology, we want to hear from you!\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Staff ASIC Design Engineer", "company": "Nokia", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-09-21", "url": "https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/36568", "is_hardware": true, "platform": "oracle", "jd_text": "In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise\n Join Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.\nInfinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group. \n\nLed RTL development through coding, checks, synthesis, and supported verification for successful integration.\n\nResponsibilities\nJob Responsibilities:\nWork with the architecture team to comprehend requirements and create/interpret a microarchitecture document\nPropose solutions and  get them reviewed with senior architects.\nBe responsible for implementing the architecture by taking it through definition and implementation phase.\nDo RTL coding and RTL checks including lint, CDC checks, synthesis\nWork with verification team to debug and qualify the implementation.\n\nQualifications\nWhat we Seek:\nCandidate must have a bachelor's degree or higher in CS or EE with very good academics. Master's degree preferred\n6+  years of experience and hands-on experience in delivery of a major function/ASIC\nAbility to communicate using diagrams and written documents.\nAbility and desire to learn and work in a team.\nKnowledge in Ethernet/networking protocols is preferred\n\nAbout the organization\nSome of our benefits in India:\n\nFlexible and hybrid working arrangements to support work–life balance\n\nHealth and well-being support – medical insurance for you and your family, health check-ups, life and accident insurance, well-being programs, and employee resource groups \n\nA minimum of 90 days of Maternity and Paternity Leave based on eligibility\n\nPersonal Support Service 24/7 – a confidential support channel open to all Nokia employees and their families in challenging situations\n\nCareer growth & mobility – technical career paths, job rotations, international assignments, and relocation support\n\nContinuous learning – technical certifications, mentoring programs, coaching, and digital learning platforms\n\nOpportunities to innovate and contribute through Nokia’s research and development environment\n\nRecognition programs that celebrate outstanding contributions\n\nWorkplace support – ergonomic working support and mobile device programs based on eligibility", "jd_status": "stored"}, {"title": "Senior Engineer II - Verification Engineer", "company": "Microchip", "location": "India - Hyderabad", "date_posted": "2026-09-21", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Hyderabad/IO-Mixed-Signal-Design-Engineer_R1696-25-4", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nDefine and develop verification environments\nWrite verification plans, and documentation\nGenerate test bench and automatic regression plans\nBe responsible for verification architecture, simulations, verifications, and debugging of circuit and logic designs\nComplete block-level verification and chip level verification\nBring a self-motivated and enthusiastic approach that will achieve any new requirements and overcome all challenges\nAble to work mostly independently and handle complex SoC Verification platform. Able to debug the RTL for design intent and Interface with cross-functional teams and collaboration in all verification related activities\n\nRequirements/Qualifications:\n\nMinimum of 5 years related proven silicon design or verification work experience\nHands on project experience with leading edge verification methodologies like OVM/UVM\nOne of the Protocol knowledge areas AXI/AHB/DDR/PCIe is must\nHands on project experience in coverage/assertion driven verification\nKnowledge of IC chip design, development flow, process, and methodology\nKnowledge of CMOS logic design, circuit design, and circuit analysis\nProficient in HDL languages System Verilog, Verilog and VHDL\nGood knowledge of UNIX shell scripting, Perl and TCL scripting.\nGood knowledge and understanding of CMOS device operation and characteristics\nProven experience in writing verification plans and test bench development, simulation, and debugging\nProficient with UNIX environment, and CAE/CAD tools such as schematic capture, simulation, design verification\nMust be able to learn new technology\nGood analytical and problem-solving skills\nExcellent written and verbal communication in English.\nExperience dealing with and communicating at different levels of the organization\n\nTravel Time:\n\nNo Travel\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Post-Silicon Product Engineer, Silicon Systems Group", "company": "Amazon", "location": "Bengaluru, Karnataka, IND", "date_posted": "2026-09-21", "url": "https://www.amazon.jobs/en/jobs/10554928/post-silicon-product-engineer-silicon-systems-group", "is_hardware": true, "platform": "amazon", "jd_text": "Come join Amazon Devices and work within Amazon Lab126, where top engineers, researchers, and scientists invent, design, and build Amazon's new consumer electronics devices and services. Amazon Lab126 has produced the best-selling Kindle devices, the ground breaking Fire tablets and Fire TV, and the revolutionary Echo.\n\nWe are seeking a seasoned Senior Post-Silicon Product Engineer to lead and execute critical post-silicon validation, characterization, and production ramp activities for our advanced semiconductor products. This role demands a deep understanding of the semiconductor product lifecycle, from initial silicon bring-up to high-volume manufacturing, ensuring product performance, quality, and reliability meet the highest standards.\n\nOur final product is a complete consumer electronics system, not just the silicon. As a Post-Silicon Product Engineer, you'll go beyond traditional product engineering boundaries to address system-level challenges—offering rich opportunities to understand and influence system architecture and end-user performance.\n\nKey job responsibilities\nPost-Silicon Validation & Characterization:\n   • Lead the bring-up and characterization of new silicon, ensuring functionality and performance meet design specifications.\n   • Develop and execute detailed validation plans, including defining test methodologies, coverage metrics, and corner conditions.\n   • Define and validate silicon and ATE-level test coverage, ensuring comprehensive validation aligned with customer application scenarios.\n\nData Analysis & Yield Improvement:\n   • Analyze data from WAT, wafer sort, ATE, and system-level tests to identify trends, anomalies, and systematic issues.\n   • Implement automation pipelines for data analysis across the test flow to improve traceability, root-cause identification, and feedback into design and test.\n   • Develop and implement strategies that align test environments and methodologies with defined yield, quality, and performance objectives.\n• Apply advanced data analytics—including regression, correlation, and predictive modelling—to optimize test efficiency and drive yield improvements.\n\nTest Development & Optimization:\n   • Collaborate with design and test engineering teams to develop and optimize test programs for wafer and package-level testing.\n   • Partner with ATE engineers to debug test failures, refine test coverage, and identify limitations in test hardware/software infrastructure.\n   • Lead test time reduction and cost optimization initiatives while maintaining required test coverage and quality standards.\n\nCross-Functional Collaboration:\n   • Collaborate with Design, SoC, DFT, Reliability, Quality, and Manufacturing teams to resolve silicon issues and support successful product ramp.\n   • Lead structured failure analysis and root cause investigations to address quality, reliability, and customer-return issues.\n   • Coordinate with cross-functional leaders to ensure alignment on key product KPIs such as yield, DPPM, quality escapes, and production readiness.\n\nDocumentation & Reporting:\n   • Generate comprehensive engineering reports detailing validation results, failure analyses, and recommended actions.\n   • Maintain accurate records of test methodologies, data analyses, and process changes.\n\nBasic qualifications\n- Bachelor's degree in Electrical Engineering or a related field\n- Experience communicating technical details verbally and in writing\n- Minimum 8 years of experience in post-silicon validation, product engineering, or semiconductor development roles.\n- Strong understanding of semiconductor testing methodologies, including ATE, wafer sort, and SLT.\n- Hands-on experience with silicon bring-up, validation, characterization, and debug.\n- Proficiency in data analysis tools such as JMP, Python, and SQL.\n- Familiarity with statistical methods such as SPC, CPK, DOE, and other yield improvement methodologies.\n- Strong problem-solving skills, including root cause analysis across silicon, package, and system levels.\n- Experience working in high-volume manufacturing environments, supporting NPI (New Product Introduction) to mass production transition.\n\nPreferred qualifications\n- Master's degree in Electrical or Communications Engineering or a related field\n- Experience with reliability testing standards (e.g., HTOL, HAST, TC) and failure analysis methodologies.\n- Knowledge of wafer fabrication and packaging processes.\n- Familiarity with defining test coverage for critical IP blocks and validating against customer use cases.\n- Experience using AWS cloud tools — including Lambda functions, SageMaker, and QuickSight — for data analysis and automation.\n- Exposure to system-level validation, including correlation between silicon behavior and system-level performance.\n- Experience collaborating with SoC Design, DFT, Debug Leads, Reliability, and Quality teams.\n- Strong understanding of customer RMA handling and product sustenance strategies. Experience with end-to-end product ownership from early silicon evaluation through to high-volume production.\n\nOur inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "jd_status": "stored"}, {"title": "Packaging Associate, IN Packaging", "company": "Amazon", "location": "Bengaluru, Karnataka, IND", "date_posted": "2026-09-21", "url": "https://www.amazon.jobs/en/jobs/10554326/packaging-associate-in-packaging", "is_hardware": true, "platform": "amazon", "jd_text": "Overview:\nAt Amazon, we strive to be Earth’s most customer-centric company where people can find and discover anything they want to buy online. We hire the world’s brightest minds, offering them an environment in which they can relentlessly improve the experience for customers. Innovation and creativity are built into the DNA of the company and are encouraged at all levels of employment. Every day we solve complex technical and business problems with ingenuity and simplicity. We’re making history and the good news is we’ve only just begun.\n\nKey roles and responsibilities will include:\n1. Perform visual testing against attributes for PWP/any other workstream in Imaging team.\n2. Responsible for achieving the metric goals for imaging team.\n3. Identify and manage small-scale process improvement opportunities by performing root cause analysis.\n\nSkills:\n•\tExcellent analytical and statistical skills\n•\tProblem solving through data driven approach\n•\t0-1 year experience and process understanding of AMZ\n•\tExcellent written & verbal communication skills including writing skills in Word, Power point, and Excel\n•\tBachelor’s degree or higher.\n•\tAbility to relocate to Bangalore as per the requirement.\nJob Location- Bangalore, Karnataka\n\nKey job responsibilities\n1. Perform visual testing against attributes for PWP/any other work stream in Imaging team.\n2. Responsible for achieving the metric goals for imaging team.\n3. Identify and manage small-scale process improvement opportunities by performing root cause analysis.\n\nBasic qualifications\n- Bachelor's degree\n\nPreferred qualifications\n- Experience in logistics\n\nOur inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "jd_status": "stored"}, {"title": "Packaging Associate, IN Packaging", "company": "Amazon", "location": "Bengaluru, Karnataka, IND", "date_posted": "2026-09-21", "url": "https://www.amazon.jobs/en/jobs/10554327/packaging-associate-in-packaging", "is_hardware": true, "platform": "amazon", "jd_text": "Overview:\nAt Amazon, we strive to be Earth’s most customer-centric company where people can find and discover anything they want to buy online. We hire the world’s brightest minds, offering them an environment in which they can relentlessly improve the experience for customers. Innovation and creativity are built into the DNA of the company and are encouraged at all levels of employment. Every day we solve complex technical and business problems with ingenuity and simplicity. We’re making history and the good news is we’ve only just begun.\n\nKey roles and responsibilities will include:\n1. Perform visual testing against attributes for PWP/any other workstream in Imaging team.\n2. Responsible for achieving the metric goals for imaging team.\n3. Identify and manage small-scale process improvement opportunities by performing root cause analysis.\n\nSkills:\n•\tExcellent analytical and statistical skills\n•\tProblem solving through data driven approach\n•\t0-1 year experience and process understanding of AMZ\n•\tExcellent written & verbal communication skills including writing skills in Word, Power point, and Excel\n•\tBachelor’s degree or higher.\n•\tAbility to relocate to Bangalore as per the requirement.\nJob Location- Bangalore, Karnataka\n\nKey job responsibilities\n1. Perform visual testing against attributes for PWP/any other workstream in Imaging team.\n2. Responsible for achieving the metric goals for imaging team.\n3. Identify and manage small-scale process improvement opportunities by performing root cause analysis.\n\nBasic qualifications\n- Bachelor's degree\n\nPreferred qualifications\n- Experience in Logistics and supply chain management\n\nOur inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "jd_status": "stored"}, {"title": "RTL Design Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-18T09:17:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92324/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. RTL DESIGN ENGINEER    THE ROLE: The focus of this role is to microarchitect , design and deliver data fabric IP RTL . These include new and existing features and components for AMD’s data fabric IP , working in close coordination with verification to ensure design quality.     THE PERSON:  You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.   KEY RESPONSIBILITIES:  Digital design implementation and micro-architecture of components of the Infinity Data Fabric Micro-architecture and RTL coding in Verilog/SystemVerilog of Data fabric components and its features as the fabric scales for server, data centre application systems. Design of Power Management flows and architecture for the fabric Collaborate with architectss to understand the new features to be implemente Knowledge of cache coherency and/or fabric /NOC design is a plus Leaf level cache designing Collaborating with verification and integration teams to resolve inter IP integration issues Design flow quality checks - Lint, CDC, RDC and others Timing closure - timing constraints, synthesis, logic-depth reduction Design area optimizations Low power design techniques, UPF included PREFERRED EXPERIENCE:  7+ years of working experience in ASIC design Proficiency in Verilog/SystemVerilog RTL Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification. Active knowledge of ASIC design quality flows ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR5 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "SoC Physical Design Engineer (Senior/Lead)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-18T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720933107", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nExperience: 3-6 Years\nLocation: Bangalore\nJob Responsibilities\nOwn end-to-end physical design implementation from Netlist to GDSII for complex SoC/IP blocks.\n\nDrive Floorplanning, Power Planning (PDN), Placement, CTS, Routing, STA, and Timing Closure.\n\nPerform physical verification including DRC, LVS, and signoff checks.\n\nCollaborate with RTL, STA, DFT, Verification, and CAD teams to achieve design and tapeout goals.\n\nDebug and resolve timing, congestion, IR drop, and physical design challenges.\n\nSupport successful chip tapeouts on advanced technology nodes.\n\nRequired Skills\n3-6 years of hands-on experience in SoC/ASIC Physical Design.\n\nStrong expertise in Floorplanning, PDN, Placement, CTS, Routing, and Timing Closure.\n\nExperience with industry-standard EDA tools such as Innovus, ICC2/Fusion Compiler, PrimeTime, and Calibre.\n\nGood understanding of physical verification, power integrity, and signoff methodologies.\n\nExperience working on advanced nodes (16nm and below preferred).\n\nStrong debugging, problem-solving, and communication skills.\n\nPreferred\nExperience in high-performance CPU, GPU, AI, Mobile, Networking, or Multimedia SoCs.\n\nCandidates from leading semiconductor product companies are strongly preferred.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Design Implementation Engineer, Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-18T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721066501", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Description\n\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nAdditional Job Description\n\nRole Summary: Technical leader driving synthesis strategy, QoR convergence, and execution for large GPU/SoC hierarchies.\nKey Responsibilities: Own synthesis closure for major hierarchies, define QoR strategy, resolve high‑complexity issues, act as synthesis focal point across functions, lead flow/automation initiatives, mentor senior engineers.\nQualifications: BS/MS EE, 6–8 yrs deep synthesis experience, tapeout ownership, strong methodology leadership.\nLeveling Alignment: Program‑level ownership, solves highly complex multi‑dimensional problems, drives cross‑functional technical decisions.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "System HW Applications Engineer, Sr / Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-18T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720514229", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Description\nAs a member of Qualcomm Customer engineering team, the individual will be responsible for successful integration of Qualcomm solution into customer end products in Mobile, Compute, 5G Broadband, Automotive, IoT and consumer electronics markets.\nGathers, integrates, and interprets information across cross functional teams from a variety of sources in order to troubleshoot issues and find solutions.\nApplies deep and broad knowledge to anticipate and identify gaps/risks in processes, efforts, technical aspects of HW/System aspects etc., and closes the gaps with wide range of eco-system partners within Qualcomm and enable customer product commercialization\nIndividual will be responsible and acts as a tech lead on projects and owns the outcome of the project for supporting Qualcomm's growing portfolio of platforms/applications. Job involves working closely with internal partners in definition of product (as appropriate), collaborate with HW/SW/validation/test and product teams on customized use cases of customer applications, support customers on HW design signoffs, system/SoC debug, deliverables etc and effectively managing cross functional team of engineers.\nIndividual will be responsible to create chipset documentation, assist customers in technical responses to customer queries and troubleshooting of customer designs from overall system and SoC point of view. Candidate should have minimum 8+ Years of relevant experience.\nPast expertise and experience in interacting with multiple teams in HW, SW, domain skills in Digital/High Speed/SoC, Power Management, Silicon validation, Customer engagement, ability to adapt dynamic changes to meet tight deadlines/commitments and deliver customer requirements, Strong written and oral communication skills is highly desirable.\nTravelling to customer sites across geographical locations in Asia/NA etc on need basis\n\nAdditional Job Description\nPreferred Qualifications\nEmbedded systems HW/SW design preferably ARM based, board bring up, Silicon bench tests/ Characterization, measurements AC/DC parameters, SOC interface parametric measurements, basic SW integrated functional tests, Silicon validation, HW PCB design, High speed peripheral expertise, Signal Integrity and Power Integrity, System level architecture\nProgramming languages: ‘C’ and scripting languages PERL/PYTHON preferred. Good trouble-shooting skills with analysis and debug ability at PCB, HW IP, SW and SoC level. Expertise in High Speed Digital interfaces such as: Memory Bus I/F (UFS, eMMC, LPDDRx), USB, MIPI CSI/DSI, PCIe, SERDES etc and Power management areas like LDO, SMPS, Clock, Crystal etc. Hands on experience in working with Oscilloscopes, Logic Analyzers. Basic knowledge of ARM processors, Multi core architecture, experience in working with JTAG emulators. Knowledge of Multi-core system/inter-chip system design is a plus.\nExperience in technical leadership and people management, guiding cross-functional engineering teams. Proven track record in leading projects to successful completion while supporting team growth and development.\nKeywords\nEmbedded systems, Silicon Characterization, LPDDR4x, LPDDR5, LPDDR, NAND, UFS, eMMC, SERDES, PCIe, MIPI, USB, UART, SPI, I2C, Logic Analyzer, PADS, Allegro, ARM processor, JTAG, LDO, SMPS, Clock, Crystal, Board bring up\nEducational Requirements\nRequired: Bachelor's, Electronics and/or Electrical Engineering Preferred: Master's, Electronics and/or Electrical Engineering\n\n3 - 8 years relevant experience\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NOC Design Verification Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-18T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720429933", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nLooking for an experience Verification Architect/ Engineer, who will be responsible for verification of next generation Infrastructure IPs (DDRSS, Memory Controllers etc.) which goes into System-on-chip (SoC) for smartphones, tablets and other product categories. In this position you will be expected to plan and implement IP/Cluster/Formal verification flows for the Infra IPs. Also expected to coordinate with different Design and SOC teams throughout the IP development cycle.  \n\nJob responsibilities include \nOwnership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage) \nDevelop test plan and test cases to cover design feature set, follow up with stakeholders on code coverage, functional coverage closure at different levels of test bench \nWork closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure \nDebug of regression signatures and identifying bug fixes \nResponsible for Quality sign off and required documentation \nDeveloping/Deploying scripts/tools for validation (Certitude, VC Formal, VPlan) \nDebug and root cause post silicon issues in collaboration with Design, SW and test teams \nWork with SoC level performance modeling team on latency, bandwidth analysis next-generation experiences and drives digital transformation to help create a smarter, connected future for all.\n\nRequired skillset include \nStrong debugging, Analytical and problem-solving skills \nExpertise on UVM based verification  \nKnowledgeable about ARM bus protocols, Virtual Memory concepts, SoC system architecture \nExperience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved \nCommunication and collaboration skills to work with a large world-wide design organization \n\nDesired skillset includes \nExperience in designs optimized for low power - Dynamic clock gating, Logic/ Memory power collapse  \nExperience in verifying designs meeting Automotive Safety Integrity Levels (ASIL) \nProficiency in Scripting languages (Python or Perl) for Automation initiatives, C/C++/SystemC for performance models \nPost-si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage \nQualification : \nBachelor/Master’s Degree in Electronics & Communication / Micro Electronics \n3 Years of Experience in IP verification or related\nExperience with UVM and ARM Bus protocols. \n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NPU Physical Design Engineer (Lead/Staff/Sr Staff)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-18T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719660336", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nGeneral Summary\nPNR implementation for Qualcomm Hexagon NPU\n\nGood hands-on  experience on Floorplanning, PNR and STA flows\n\nGood knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc\n\nGood understanding on signoff domains– LEC/CLP/PDN knowledge, etc\n\nGood knowledge on Unix/Linux – Perl/TCL fundamentals/scripting\n\nPrincipal Duties and responsibilities:\nComplete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes.\n\nSignoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc)\n\nQuick learner with good analytical and problem solving skills\n\nQualifications:\n8- 12 years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Memory Designer", "company": "Lattice", "location": "Penang, Malaysia", "date_posted": "2026-09-18", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Penang-Malaysia/Senior-Memory-Designer_R-100058-1", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nWe are seeking an experienced Memory Designer to join our team. The ideal candidate will have over 10 years of experience in designing and implementing high-performance, low-power memory circuits as well as low-power configuration memory and architectures. This role involves working on cutting-edge technology and contributing to the development of innovative memory\nsolutions.\n\nKey Responsibilities:\nDesign and Development: Lead the design and development of custom circuits for high-speed and low-power SRAM and low-power configuration RAM (CRAM)\n\nArchitecture and Implementation: Develop memory architectures and implement them in advanced semiconductor technologies, including FinFET and nanometer CMOS\n\nSimulation and Verification: Perform schematic capture, simulation, and margin verification of major memory blocks\n\nLayout Planning: Oversee layout planning and ensure tight pitch-matched memory layout designs\n\nCollaboration: Work closely with architecture and design teams to define memory PPA (Performance, Power, Area) and yield targets\n\nFull Design Flow: Manage the full embedded memory design flow, including architecture, circuit design, physical implementation, compiler usage, characterization, timing, and model generation\n\nInnovation: Bring innovative and revolutionary ideas to life in our products, influencing various parts of our FPGA designs\n\nQualifications:\nEducation: Bachelor’s degree in electrical engineering, or a related field. A Master’s or PhD is preferred\n\nExperience: Over 10 years of experience in memory design, verification, validation, and integration\n\nTechnical Skills:\nStrong knowledge of custom memory design, high speed, low power as well as custom memory design for configuration of FPGA\n\nExpertise in high-performance and low-power design techniques\n\nFamiliarity with variation-aware design in advanced semiconductor technologies\n\nSoft Skills: Excellent problem-solving skills, strong communication abilities, and the ability to work collaboratively in a team environment\n\nPreferred Qualifications:\nExperience with large density memory cell design for high yield\n\nKnowledge of semiconductor device fundamentals\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nMalaysiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Staff Engineer – DFT Engineering", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-09-18", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Staff-Engineer---DFT-Engineering_R265854-1", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nJob Description:\n \nWe are seeking a skilled and experienced DFT Engineer to join our VLSI design team. The ideal candidate should have a strong background in Design for Testability (DFT) techniques, including LBIST (Logic Built-In Self-Test), ATPG (Automatic Test Pattern Generation), DFT DRC (Design Rule Checking), MBIST (Memory Built-in Sefl-Test), Boundary Scan, JTAG and Analog/Phy DFT.\n \nResponsibilities:\n \nCollaborate with the Design/Arch/PTE/PD team to ensure efficient and effective testability of complex integrated circuits.\nDesign and implement DFT features such as scan chains, compression, and built-in self-test structures to enhance testability.\nConduct DFT DRC checks in RTL/Netlist database to ensure compliance with DFT guidelines and rules.\nUtilize Siemen’s DFT tool to perform DFT analysis and optimize testability metrics.\nGenerating high quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models using on-chip test compression techniques.\nMBIST Design (including repair) and Verification using Siemen’s EDA tool.\nValidation of DFT structures/patterns in RTL, Netlist with and without SDF.\nWork closely with the verification team to define and implement DFT verification plans.\nWork closely with physical design team for DFT implementation/constraints strategy for synthesis/STA.\nAnalyze and debug test failures and collaborate with the test engineering team to resolve issues.\nProvide guidance and mentorship to junior DFT engineers.\n \nQualifications:\n \nBachelor's/Master's degree in Electrical/Electronic Engineering, or a related field.\n7-10 years of hands-on experience in DFT methodologies and techniques.\nStrong knowledge of LBIST, ATPG, DFT DRC, Scan compression, Low power DFT Techniques, MBIST, Boundary Scan, Analog DFT, JTAG Architecture, DFT STA Constraint development.\nHand-on experience/expertise in Cadence/Siemen’s DFT EDA tools for Scan stitching, DRC, ATPG, Coverage improvement, MBIST, Boundary Scan.\nProficiency in scripting languages such as Perl, Tcl, and/or Python for automation.\nSolid understanding of digital design fundamentals, RTL coding, Lint/CDC, Low Power Checks and ASIC design flow.\nExcellent problem-solving skills and ability to work effectively in a team-oriented environment.\nStrong communication and interpersonal skills.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Applications Engineering, Sr Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-18", "url": "https://careers.synopsys.com/job/bengaluru/applications-engineering-sr-engineer/44408/100768195920", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent the last few years deep in FPGA design and implementation, and you have learned that the real work begins when a customer's design does not compile the way they expected or when partitioning across multiple FPGAs creates timing issues no one saw coming. You are the engineer who stays on the call until the problem is solved, not because you have to, but because leaving something half-fixed bothers you.\nYou are comfortable reading Verilog or SystemVerilog that someone else wrote, understanding what they were trying to do, and figuring out why the synthesis tool is choking on it. You know your way around FPGA architecture well enough to explain why a design that worked fine in simulation is failing in hardware, and you can do it in a way that does not make the customer feel like they missed something obvious.\nWorking with customers energizes you. You like the variety of problems, the pressure of real deadlines, and the satisfaction of helping someone get unstuck. You do not need everything documented perfectly to move forward. You ask the right questions, dig into log files, reproduce issues locally, and escalate to R&D when needed with enough context that they can actually help.\nAt Synopsys, you will work with some of the most complex emulation and prototyping workflows in the industry, supporting global customers who depend on Zebu and Protocompiler to verify chips that power everything from automotive systems to data centers.\nWhat You'll Be Doing\nProvide technical support to global customers using Synopsys Zebu Emulation and Protocompiler Prototyping software, troubleshooting issues across partitioning, synthesis, place and route, and hardware debug\nWork directly with customers to migrate their designs to new software releases, ensuring compatibility and resolving any regressions or performance issues that surface\nDeploy new software features on live customer designs, helping them adopt capabilities like advanced partitioning algorithms, new debug modes, or updated FPGA target support\nDeliver technical training sessions to customers, ranging from basic tool usage to advanced workflows for multi-FPGA partitioning and hardware-software co-verification\nCollaborate with Synopsys HAV R&D teams to report customer issues, provide reproducible test cases, and advocate for product improvements based on real-world usage patterns\nSupport pre-sales evaluations by running customer designs through the Synopsys emulation and prototyping flow, demonstrating performance and identifying potential adoption blockers\nTravel occasionally to customer sites for onsite support, training, or critical issue resolution\nThe Impact You Will Have\nEnable customers to bring up complex SoC designs on emulation and prototyping platforms faster, reducing their verification cycle time by weeks or months\nImprove product quality by surfacing real customer pain points to R&D with enough technical detail that fixes can be prioritized and implemented effectively\nBuild customer confidence in Synopsys HAV solutions through responsive, expert-level support that helps them solve problems they could not solve on their own\nExpand adoption of new software features by showing customers how to use them on their actual designs, not just in demos\nReduce escalations and support load over time by delivering training that helps customers become more self-sufficient with the toolchain\nStrengthen customer relationships by being the engineer they trust to pick up the phone when something is broken and production timelines are at risk\nContribute to the technical knowledge base and internal best practices that make the entire support organization more effective\nWhat You'll Need\nBachelors in Electronics Engineering with 2-3 years of experience, or Master's in Electronics Engineering with 1-2 years, specifically in emulation or prototyping environments\nHands-on experience with logic design and implementation using FPGAs, including synthesis, place and route, and timing closure\nStrong working knowledge of Verilog, System Verilog, or VHDL, including the ability to read, debug, and modify RTL written by others\nPractical experience with FPGA architecture and back-end implementation flows, including understanding of resource utilization, clock domain crossing, and design partitioning\nExposure to Xilinx or Altera synthesis tools is a plus, as is familiarity with Synopsys Prototyping or Emulation hardware and software\nExperience with interface protocols like PCIe, AXI, UART, or I2C is a plus, particularly in the context of hardware-software integration\nScripting experience in Python, Tcl, or shell is desirable for automating workflows and analyzing log files\nWho You Are\nYou can take a vague customer complaint like 'the compile is failing' and turn it into a specific, reproducible issue with enough detail that R&D can act on it\nYou stay calm when a customer is frustrated or under pressure, and you focus on solving the problem rather than defending the tool\nYou are comfortable working across time zones and managing multiple customer issues in parallel without losing track of who needs what by when\nYou do not mind digging through synthesis logs, waveform dumps, or FPGA utilization reports to find the root cause of a problem\nYou can explain a complex technical tradeoff, like why a design needs to be repartitioned or why certain optimizations are not possible, in a way that makes sense to someone who is not an FPGA expert\nYou are open to occasional travel for customer support, training, or onsite troubleshooting when remote support is not enough\nThe Team You'll Be Part Of\nYou will join Synopsys Technical Sales Group (TSG) as part of the Hardware Assisted Verification (HAV) team, working alongside expert-level field engineers who support customers globally on Zebu Emulation and Protocompiler Prototyping solutions. The team works closely with R&D and directly with customers at all stages of the emulation and prototyping cycle, from pre-sales evaluation through post-deployment support. You will collaborate with engineers across geographies and gain exposure to Synopsys HAV hardware platforms as part of your technical development.", "jd_status": "stored"}, {"title": "Applications Engineering, Sr Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-18", "url": "https://careers.synopsys.com/job/bengaluru/applications-engineering-sr-engineer/44408/100768195904", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent the last few years deep in FPGA design and implementation, and you have learned that the real work begins when a customer's design does not compile the way they expected or when partitioning across multiple FPGAs creates timing issues no one saw coming. You are the engineer who stays on the call until the problem is solved, not because you have to, but because leaving something half-fixed bothers you.\nYou are comfortable reading Verilog or SystemVerilog that someone else wrote, understanding what they were trying to do, and figuring out why the synthesis tool is choking on it. You know your way around FPGA architecture well enough to explain why a design that worked fine in simulation is failing in hardware, and you can do it in a way that does not make the customer feel like they missed something obvious.\nWorking with customers energizes you. You like the variety of problems, the pressure of real deadlines, and the satisfaction of helping someone get unstuck. You do not need everything documented perfectly to move forward. You ask the right questions, dig into log files, reproduce issues locally, and escalate to R&D when needed with enough context that they can actually help.\nAt Synopsys, you will work with some of the most complex emulation and prototyping workflows in the industry, supporting global customers who depend on Zebu and Protocompiler to verify chips that power everything from automotive systems to data centers.\nWhat You'll Be Doing\nProvide technical support to global customers using Synopsys Zebu Emulation and Protocompiler Prototyping software, troubleshooting issues across partitioning, synthesis, place and route, and hardware debug\nWork directly with customers to migrate their designs to new software releases, ensuring compatibility and resolving any regressions or performance issues that surface\nDeploy new software features on live customer designs, helping them adopt capabilities like advanced partitioning algorithms, new debug modes, or updated FPGA target support\nDeliver technical training sessions to customers, ranging from basic tool usage to advanced workflows for multi-FPGA partitioning and hardware-software co-verification\nCollaborate with Synopsys HAV R&D teams to report customer issues, provide reproducible test cases, and advocate for product improvements based on real-world usage patterns\nSupport pre-sales evaluations by running customer designs through the Synopsys emulation and prototyping flow, demonstrating performance and identifying potential adoption blockers\nTravel occasionally to customer sites for onsite support, training, or critical issue resolution\nThe Impact You Will Have\nEnable customers to bring up complex SoC designs on emulation and prototyping platforms faster, reducing their verification cycle time by weeks or months\nImprove product quality by surfacing real customer pain points to R&D with enough technical detail that fixes can be prioritized and implemented effectively\nBuild customer confidence in Synopsys HAV solutions through responsive, expert-level support that helps them solve problems they could not solve on their own\nExpand adoption of new software features by showing customers how to use them on their actual designs, not just in demos\nReduce escalations and support load over time by delivering training that helps customers become more self-sufficient with the toolchain\nStrengthen customer relationships by being the engineer they trust to pick up the phone when something is broken and production timelines are at risk\nContribute to the technical knowledge base and internal best practices that make the entire support organization more effective\nWhat You'll Need\nBachelors in Electronics Engineering with 2-3 years of experience, or Master's in Electronics Engineering with 1-2 years, specifically in emulation or prototyping environments\nHands-on experience with logic design and implementation using FPGAs, including synthesis, place and route, and timing closure\nStrong working knowledge of Verilog, System Verilog, or VHDL, including the ability to read, debug, and modify RTL written by others\nPractical experience with FPGA architecture and back-end implementation flows, including understanding of resource utilization, clock domain crossing, and design partitioning\nExposure to Xilinx or Altera synthesis tools is a plus, as is familiarity with Synopsys Prototyping or Emulation hardware and software\nExperience with interface protocols like PCIe, AXI, UART, or I2C is a plus, particularly in the context of hardware-software integration\nScripting experience in Python, Tcl, or shell is desirable for automating workflows and analyzing log files\nWho You Are\nYou can take a vague customer complaint like 'the compile is failing' and turn it into a specific, reproducible issue with enough detail that R&D can act on it\nYou stay calm when a customer is frustrated or under pressure, and you focus on solving the problem rather than defending the tool\nYou are comfortable working across time zones and managing multiple customer issues in parallel without losing track of who needs what by when\nYou do not mind digging through synthesis logs, waveform dumps, or FPGA utilization reports to find the root cause of a problem\nYou can explain a complex technical tradeoff, like why a design needs to be repartitioned or why certain optimizations are not possible, in a way that makes sense to someone who is not an FPGA expert\nYou are open to occasional travel for customer support, training, or onsite troubleshooting when remote support is not enough\nThe Team You'll Be Part Of\nYou will join Synopsys Technical Sales Group (TSG) as part of the Hardware Assisted Verification (HAV) team, working alongside expert-level field engineers who support customers globally on Zebu Emulation and Protocompiler Prototyping solutions. The team works closely with R&D and directly with customers at all stages of the emulation and prototyping cycle, from pre-sales evaluation through post-deployment support. You will collaborate with engineers across geographies and gain exposure to Synopsys HAV hardware platforms as part of your technical development.", "jd_status": "stored"}, {"title": "ASIC Digital Design , Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-18", "url": "https://careers.synopsys.com/job/bengaluru/asic-digital-design-staff-engineer/44408/100796259312", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years building digital logic that has to actually work in silicon, not just pass simulation, actually work, at 600MHz+ clock speeds with real area budgets and power constraints that matter. You know that the difference between an IP core that ships and one that gets redesigned is usually a micro-architecture decision made during spec review, and you are the kind of engineer who catches that decision before it becomes a six-month debug cycle.\nYou are comfortable moving between protocol specs like PCIe Gen5 or Ethernet 400G and the actual RTL that implements them, translating pages of standards documents into data paths that close timing and control logic that handles every corner case. You do not need a perfect specification to get started. You ask the right questions, sketch out the architecture, and find a way through ambiguity without creating technical debt downstream.\nYou like hard problems. Reed Solomon FEC engines, MAC SEC pipelines, CDC domains that cross multiple clock regions, these are not obstacles, they are the work. You have debugged synthesis mismatches at 2am, you have rewritten a critical path to shave 200ps, and you have mentored someone through their first timing closure. At Synopsys, you will work on DesignWare IP cores that power everything from automotive SoCs to enterprise data centers. The team is global, the RTL is real, and what you build will ship in millions of devices.\nWhat You'll Be Doing\nArchitect and implement RTL designs for DesignWare IP cores targeting commercial, enterprise, and automotive applications, translating protocol specifications into detailed micro-architectures and design documentation\nOwn hands-on RTL coding in synthesizable Verilog/SystemVerilog for medium to high complexity features, including data path logic like Reed Solomon FEC, BCH codes, CRC engines, and MAC SEC implementations\nDrive synthesis, static timing analysis, CDC analysis, lint checking, and P&R-aware synthesis using tools like Fusion Compiler, ensuring designs meet area, latency, and throughput targets at 600MHz+\nCollaborate with global engineering teams and engage directly with customers to refine specifications, resolve design ambiguities, and align on feature requirements\nLead technical reviews, debug complex RTL issues across simulation and synthesis, and develop test strategies that ensure design quality and coverage\nMentor and technically lead a team of RTL designers, providing guidance on coding practices, design trade-offs, timing closure techniques, and process improvements\nManage design flows using version control systems like Perforce and automate repetitive tasks with Perl or Shell scripting to improve team efficiency\nThe Impact You Will Have\nEnable Synopsys to deliver industry-leading IP cores for Ethernet, DDR, PCIe, USB, and other high-speed protocols that power next-generation chips across automotive, enterprise, and consumer markets\nAccelerate time-to-market for customers by delivering robust, synthesizable IP that integrates cleanly and closes timing on the first pass, reducing their integration risk and schedule pressure\nElevate the technical capabilities of your team through hands-on mentorship and leadership, building a culture where designers learn advanced techniques in timing closure, CDC handling, and protocol implementation\nDrive measurable improvements in design quality and efficiency by optimizing RTL architectures, automating flows, and establishing best practices that scale across the DesignWare IP portfolio\nInfluence product roadmaps and feature priorities by working directly with customers and translating their real-world requirements into architectural decisions that shape future IP releases\nContribute to the successful execution of complex, multi-site projects that set new performance and quality standards in the EDA and semiconductor IP industry\nHelp Synopsys maintain its leadership position in IP design by delivering cores that meet the most demanding specifications for area, power, and performance in advanced process nodes\nWhat You'll Need\nBachelor's or Master's degree in Electrical Engineering, Electronics, VLSI, or a related technical field\n4+ years of hands-on industry experience in ASIC RTL design, with a track record of delivering completed IP cores or complex digital subsystems to production\nDeep expertise in data path and control path design, including practical experience with Reed Solomon FEC, BCH codes, CRC architectures, MAC SEC engines, or similar error correction and security logic\nStrong proficiency in synthesizable Verilog/SystemVerilog coding, simulation, and design flows including lint, CDC analysis, synthesis, and static timing analysis\nExperience with high-speed design targeting 600MHz+ clock frequencies, P&R-aware synthesis techniques, and timing closure in advanced process nodes\nFamiliarity with industry-standard protocols such as Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, or AMBA (AHB, AXI), and the ability to read and implement from protocol specifications\nExperience with version control systems like Perforce and scripting languages such as Perl or Shell for design automation and flow management; prior experience as a technical lead or mentor is a strong plus\nWho You Are\nYou can sit in a spec review with a customer, hear a vague requirement about latency tolerance, and walk out with a clear architecture sketch that addresses the real constraint without overbuilding\nYou are the engineer who catches the CDC violation in code review before it gets to simulation, and you explain why it matters in a way that helps the junior designer learn, not just fix\nYou are comfortable leading a technical discussion with a distributed team across Bangalore, Sunnyvale, and Taipei, keeping everyone aligned on the critical path without losing the details that matter\nYou debug with discipline, you do not guess, you form hypotheses, you instrument the design, you trace signals, and you document what you find so the next person does not hit the same issue\nYou have a point of view on design trade-offs, area versus latency, pipeline depth versus clock frequency, and you can articulate those trade-offs to an architect or a verification lead in two sentences without losing the nuance\nYou stay current with industry trends, new protocols, emerging standards, and EDA tool capabilities, and you bring that knowledge back to your team to improve how you all work\nThe Team You'll Be Part Of\nYou will join the R&D Solutions Group at the Bangalore Design Center, as part of the DesignWare IP Design team. This team architects, develops, and delivers cutting-edge IP cores that enable Synopsys' global customers to achieve their design goals. The group is diverse, collaborative, and deeply technical, working across time zones with teams in North America, Europe, and Asia. The environment values creativity, knowledge sharing, and continuous growth, and the work directly impacts products that ship in everything from automotive SoCs to data center infrastructure.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Principal Post-Silicon Validation Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-09-18", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505715", "is_hardware": true, "platform": "oracle", "jd_text": "We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.\n\nEmployer Description\n\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\n#LI-RG1\n\nResponsibilities\nJob Summary\nWe are seeking a Principal Post-Silicon Validation Engineer to lead silicon bring-up, characterization, validation, and debug of mixed-signal image sensor products. The ideal candidate will provide technical leadership, define validation strategies, drive complex debug activities, and influence product quality from development through production.\nResponsibilities\nLead post-silicon bring-up, validation, characterization, and debug of mixed-signal and image sensor products.\nDefine validation strategies, test plans, and coverage methodologies.\nArchitect and enhance validation platforms, automation frameworks, and debug infrastructure.\nDrive root cause analysis and resolution of complex silicon, hardware, firmware, and system-level issues.\nCollaborate with Design, Verification, Firmware, Product Engineering, Reliability, and Manufacturing teams to ensure product quality and successful execution.\nAnalyze validation data and provide technical recommendations to improve product performance, reliability, and yield.\nDrive innovation, automation, and continuous improvement in validation methodologies and processes.\nMentor engineers and provide technical leadership across validation programs.\nSupport product qualification, customer escalations, and strategic debug activities.\n#LI-RG1\n\nQualifications\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.\n10+ years of experience in post-silicon validation, characterization, or bench validation of analog, digital, and mixed-signal semiconductor products.\nStrong expertise in silicon bring-up, debug methodologies, failure analysis, and root cause investigation.\nHands-on experience with lab equipment including oscilloscopes, logic analyzers, signal generators, spectrum analyzers, and power measurement instruments.\nProficiency in Python scripting for automation, test development, and data analysis.\nStrong understanding of interfaces and protocols such as I2C, SPI, UART, GPIO, MIPI CSI-2, and USB.\nProven experience defining validation strategies and leading complex validation efforts across multiple product programs.\nExperience with image sensor validation, characterization, debug, and image quality analysis is preferred.\nExposure to pre-silicon verification, FPGA prototyping, or emulation is a plus.\nExperience with statistical characterization, PVT analysis, and production test correlation is desirable.\nStrong communication, technical leadership, mentoring, and cross-functional collaboration skills.\nDemonstrated ability to drive innovation, influence technical direction, and establish validation best practices\n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Senior Engineer- memory compiler flow development", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-18", "url": "https://careers.arm.com/job/bengaluru/senior-engineer-memory-compiler-flow-development/33099/100795904976", "is_hardware": true, "platform": "talentbrew", "jd_text": "At Arm, we push the boundaries of technology to deliver world-class solutions that build the future of digital innovation. Our Physical IP Division is at the forefront of developing sophisticated, high-performance IPs used by SoC designers globally. Join our Design Enablement team, part of Solutions Engineering - Implementation organization, and be part of an ambitious team working on groundbreaking process nodes!\nJob Overview:\nWe are seeking an exceptionally skilled Senior Software Engineer with a passion for EDA software development. This role focuses on building tools for generating physical views of embedded memories using a compiler approach. Collaborate closely with Physical IP design teams, SoC design teams, and EDA vendors to evaluate methodologies, define new requirements, and develop flawless views for industry-standard EDA flows.\nResponsibilities:\nDevelop, improve, and support tools/flows for memory compiler development, focusing on Physical views like GDSII, LEF, NDM, CDL, etc.\nMaintain and improve testing of internal tools and generated views using internal and external EDA tools/flows.\nAutomate tool development, validation, and release workflows using scripting and software engineering techniques, including the effective use of LLMs and AI-assisted development tools.\nNecessary Skills and Experience:\nProven experience in C/C++, Java, Python, and shell programming with the ability to add significant new functionality, analyze, and fix complex defects.\nExpertise in software engineering guidelines, including Git/Gerrit or similar version control systems, test methodologies, continuous integration (CI), and test automation.\nFamiliarity with digital circuit design fundamentals.\nAbility to rapidly grasp new technologies and approaches, work autonomously, and assume responsibility for new and challenging technical problems.\nExperience leveraging AI/LLM-driven techniques for software development and automating engineering workflows.\nBachelor’s or Master’s degree or equivalent experience in Electronics, Electrical, Computer Engineering, or related fields, with 5+ years of relevant industry experience.\n“Preferred” Skills and Experience:\nExperience with circuit & layout design, and formats like CDL, GDSII, LEF, Cadence DB.\nExperience with memory compilers, tiling, netlist stitching, etc.\nKnowledge of EDA flows: Cadence DB, SKILL, place and route, LVS and DRC, extraction, etc.\nComfortable operating in a dynamic engineering setting, handling shifting priorities, and sustaining a cooperative and optimistic attitude when tackling complex technical issues.\nExperience collaborating with teams distributed across multiple geographical locations and time zones.\n \n#LI-BB1\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Staff / Principal engineer -Multi-Die Advanced Tech PPA  Methodology  Automation", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-18", "url": "https://careers.arm.com/job/bengaluru/staff-principal-engineer-multi-die-advanced-tech-ppa-methodology-automation/33099/100792380384", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview:\nArm is at the forefront of advanced silicon and multi-die system design. As part of the Solutions Engineering team, you will drive sub-2nm technology PPA enablement for high-performance and low-power products.\nIn this role, you will work closely with architecture, RTL, IP, physical design, DTCO, foundry, EDA, and package/board teams to optimize technology-node entitlement across performance, power, area, utilization, routability, reliability, and design convergence. The role focuses on translating advanced-node technology capabilities into practical implementation methodologies, automation, and production-ready flows.\nYou will help define and deliver end-to-end Technology - PA solutions for future Arm products, including advanced-node SoCs, ultra-low voltage designs, and multi-die systems.\nResponsibilities\nDrive technology PPA enablement for sub-2nm and future process nodes, with focus on performance, power, area, utilization, routability, and PPA convergence.\nDevelop scalable methodologies and automation to evaluate and optimize technology-node tradeoffs across libraries, memories, routing resources, power delivery, clocking, design rules, and implementation constraints.\nDrive cross-functional analysis of technology PPA limiters, including congestion, IR/EM, thermal, timing, leakage, dynamic power, area efficiency, and physical verification closure.\nDeliver multi-die and 2.5D/3D implementation enablement where technology-node, package, power, and thermal tradeoffs impact product PPA.\nHand-on execution and delivery demonstrating achieving goals.\nBuild AI-assisted automation and analytics to accelerate PPA exploration, recipe optimization, debug, and design closure.\nPartner with IP, DTCO, foundry, EDA, architecture, design, and physical implementation teams to identify technology entitlement gaps and drive improvements.\nSupport production execution by converting technology learnings into repeatable flows, checks, dashboards, and sign-off readiness criteria.\nRequired Skills and Experience\nStrong expertise in advanced-node SoC physical implementation, technology PPA optimization, and implementation methodology development.\nStrong understanding of technology-node tradeoffs, including libraries, memories, routing resources, utilization, power delivery, clocking, congestion, timing, leakage, dynamic power, and physical verification constraints.\nSolid programming and scripting skills, including Python, C, EDA tools, version control systems such as Git, and distributed processing/debug environments.\nHands-on experience with low-power design methodologies, UPF-based design, chip finishing, and physical verification flows in advanced process technologies.\nExcellent problem-solving, communication, and collaboration skills, with the ability to work effectively across globally distributed teams.\nProven ability to lead technical initiatives and collaborate with internal engineering teams, foundries, EDA providers, and ecosystem partners.\nNice to Have\nDeep understanding of advanced clocking structures, power delivery optimization, and physical verification convergence techniques.\nFamiliarity with AI-assisted design automation and methodology optimization flows.\n \n#LI-BB1\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Applications Engineering, Sr Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-18", "url": "https://careers.synopsys.com/job/bengaluru/applications-engineering-sr-engineer/44408/100768195888", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent the last few years deep in FPGA design and implementation, and you have learned that the real work begins when a customer's design does not compile the way they expected or when partitioning across multiple FPGAs creates timing issues no one saw coming. You are the engineer who stays on the call until the problem is solved, not because you have to, but because leaving something half-fixed bothers you.\nYou are comfortable reading Verilog or SystemVerilog that someone else wrote, understanding what they were trying to do, and figuring out why the synthesis tool is choking on it. You know your way around FPGA architecture well enough to explain why a design that worked fine in simulation is failing in hardware, and you can do it in a way that does not make the customer feel like they missed something obvious.\nWorking with customers energizes you. You like the variety of problems, the pressure of real deadlines, and the satisfaction of helping someone get unstuck. You do not need everything documented perfectly to move forward. You ask the right questions, dig into log files, reproduce issues locally, and escalate to R&D when needed with enough context that they can actually help.\nAt Synopsys, you will work with some of the most complex emulation and prototyping workflows in the industry, supporting global customers who depend on Zebu and Protocompiler to verify chips that power everything from automotive systems to data centers.\nWhat You'll Be Doing\nProvide technical support to global customers using Synopsys Zebu Emulation and Protocompiler Prototyping software, troubleshooting issues across partitioning, synthesis, place and route, and hardware debug\nWork directly with customers to migrate their designs to new software releases, ensuring compatibility and resolving any regressions or performance issues that surface\nDeploy new software features on live customer designs, helping them adopt capabilities like advanced partitioning algorithms, new debug modes, or updated FPGA target support\nDeliver technical training sessions to customers, ranging from basic tool usage to advanced workflows for multi-FPGA partitioning and hardware-software co-verification\nCollaborate with Synopsys HAV R&D teams to report customer issues, provide reproducible test cases, and advocate for product improvements based on real-world usage patterns\nSupport pre-sales evaluations by running customer designs through the Synopsys emulation and prototyping flow, demonstrating performance and identifying potential adoption blockers\nTravel occasionally to customer sites for onsite support, training, or critical issue resolution\nThe Impact You Will Have\nEnable customers to bring up complex SoC designs on emulation and prototyping platforms faster, reducing their verification cycle time by weeks or months\nImprove product quality by surfacing real customer pain points to R&D with enough technical detail that fixes can be prioritized and implemented effectively\nBuild customer confidence in Synopsys HAV solutions through responsive, expert-level support that helps them solve problems they could not solve on their own\nExpand adoption of new software features by showing customers how to use them on their actual designs, not just in demos\nReduce escalations and support load over time by delivering training that helps customers become more self-sufficient with the toolchain\nStrengthen customer relationships by being the engineer they trust to pick up the phone when something is broken and production timelines are at risk\nContribute to the technical knowledge base and internal best practices that make the entire support organization more effective\nWhat You'll Need\nBachelors in Electronics Engineering with 2-3 years of experience, or Master's in Electronics Engineering with 1-2 years, specifically in emulation or prototyping environments\nHands-on experience with logic design and implementation using FPGAs, including synthesis, place and route, and timing closure\nStrong working knowledge of Verilog, System Verilog, or VHDL, including the ability to read, debug, and modify RTL written by others\nPractical experience with FPGA architecture and back-end implementation flows, including understanding of resource utilization, clock domain crossing, and design partitioning\nExposure to Xilinx or Altera synthesis tools is a plus, as is familiarity with Synopsys Prototyping or Emulation hardware and software\nExperience with interface protocols like PCIe, AXI, UART, or I2C is a plus, particularly in the context of hardware-software integration\nScripting experience in Python, Tcl, or shell is desirable for automating workflows and analyzing log files\nWho You Are\nYou can take a vague customer complaint like 'the compile is failing' and turn it into a specific, reproducible issue with enough detail that R&D can act on it\nYou stay calm when a customer is frustrated or under pressure, and you focus on solving the problem rather than defending the tool\nYou are comfortable working across time zones and managing multiple customer issues in parallel without losing track of who needs what by when\nYou do not mind digging through synthesis logs, waveform dumps, or FPGA utilization reports to find the root cause of a problem\nYou can explain a complex technical tradeoff, like why a design needs to be repartitioned or why certain optimizations are not possible, in a way that makes sense to someone who is not an FPGA expert\nYou are open to occasional travel for customer support, training, or onsite troubleshooting when remote support is not enough\nThe Team You'll Be Part Of\nYou will join Synopsys Technical Sales Group (TSG) as part of the Hardware Assisted Verification (HAV) team, working alongside expert-level field engineers who support customers globally on Zebu Emulation and Protocompiler Prototyping solutions. The team works closely with R&D and directly with customers at all stages of the emulation and prototyping cycle, from pre-sales evaluation through post-deployment support. You will collaborate with engineers across geographies and gain exposure to Synopsys HAV hardware platforms as part of your technical development.", "jd_status": "stored"}, {"title": "Hardware Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-18", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Hardware-Engineer_JR0286975", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.\n\nJob Responsibilities:\nSupport hardware design of an optical transceiver and evaluation boards meeting product specifications, including schematic capture, circuit simulation, PCB design guidance, DFM review and design verification testing\nExpertise in designing 100G/lane and 200G/lane module PCBA, own the schematic and layout execution, experience with designing PDN for high-speed DSP, RFICs, manage PI and SI requirements\nExperience with 100Gbps+ DSP, Driver, TIA, uControllers, DACs, ADCs, Voltage regulators, etc\nKey contributor to Product Requirements, Owns PCBA design from concept phase to full final design and EVT/DVT phase of the product.\nUnderstand electrical and optical requirements and specifications of optical transceiver MSA. Like 800G DR8/2xFR4, 1.6T DR8/2xFR4, 800G LPO, 1.6T LRO etc.\nMaintain documentation of a hardware design specification, Pass design check list prior to tape out, BOM specifications and work with NPI team to build PCBA. Lead design reviews and present design summary to management, highlight risks with mitigation plans.\nInterface and work collaboratively with mechanical engineers, optical engineers, Photonics engineer, firmware engineers, process engineers and test engineers.\nDesign and coordinate with PI/SI engineers to simulate high-speed interfaces, RF traces, dc and ac PI analysis, etc. 100Gbps, 200Gbps NRZ and PAM4 signaling\nInteract with program manager, buyer/planner and suppliers to make sure designed parts are available in a timely manner for build.\nTroubleshooting and performance optimization of the sub-system/transceiver module board.\n\nQualifications:\nYou must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.\n\nRequired Skills:\n\nBachelor’s degree with 6+ years of experience or Masters degree 4+ years of experience or PHD with 2+ in Electrical Engineering or similar STEM field.\n\n3+ years of experience in the following:\nHW/circuit design, Schematic design and Layout floor planning\nExperienced in Cadence tools for schematic and layout\nHigh density and high-speed multiple-layer board design.\nVoltage regulator, uController, DAC/ADCs component selection, design and layout optimization to meet product requirements\nPCB and product bring up, laboratory optical and electrical measurement skills.\nHigh speed Tline design and layout guidelines (25-50G NRZ, 100Gbps PAM4 and above)\nUnderstand principles of micro-controller and communication protocols such as SPI, I2C, MDIO, CMIS management interface for optical modules.\n\nPreferred Skills:\nExperience working with high volume PCB/substrate fab houses. Selecting PCB stackup that meets product requirement.\nExperience with electronics CAD tools and modeling. Experience in PI and SI simulations is a plus.\nKnowledge of transceiver/test board electrical design principles, including module architecture, high speed signal integrity, crosstalk, power integrity, noise, soft start, ESD, FW, testing, etc.\n Experienced in layout and able to direct layout engineer with clear design priority\nExperience working with AWG, DCAM, VNA/LCA to characterize high speed performance.\nStrong communication and presentation skills.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Principal Logic Design Engineer - UALink IP/Subsystem", "company": "Astera Labs", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-17T08:31:23-04:00", "url": "https://job-boards.greenhouse.io/asteralabs/jobs/4735009005", "is_hardware": true, "platform": "greenhouse", "jd_text": "Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\n\nPrincipal Logic Design Engineer – UALink IP/Subsystem\n\nExperience\n\n10–15 years\n\nJob Summary\n\nWe are looking for a Principal Logic Design Engineer with strong expertise in high-performance interconnect and SoC/IP design to lead RTL and microarchitecture development for UALink-based IP/subsystems.\n\nKey Responsibilities\n\nLead architecture and RTL development for UALink IP/subsystems.\n\nTranslate protocol and system requirements into scalable hardware architecture.\n\nDesign high-bandwidth, low-latency data paths and control logic.\n\nDevelop robust mechanisms for flow control, ordering, buffering, arbitration, error handling, and reliability.\n\nDefine interfaces between UALink and other SoC/interconnect components.\n\nDevelop and review SystemVerilog RTL.\n\nDrive design optimization for performance, power, area, and latency.\n\nWork closely with verification, physical design, SoC integration, and firmware teams.\n\nReview design specifications and contribute to architectural decisions.\n\nDebug complex simulation and integration issues.\n\nProvide technical leadership and mentorship.\n\nRequired Skills\n\nStrong experience in RTL and microarchitecture development.\n\nExperience with high-speed interconnects and/or coherent fabrics.\n\nStrong understanding of computer architecture, networking/interconnect concepts, and data movement.\n\nProficiency in SystemVerilog/Verilog.\n\nStrong understanding of CDC, reset architecture, performance, and hardware design methodology.\n\nPreferred\n\nDirect UALink experience.\n\nExperience with PCIe, CXL, CCIX, CHI, Ethernet, or similar protocols.\n\nExperience in AI/accelerator or high-performance compute systems.\n\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.", "jd_status": "stored"}, {"title": "Lead Logic Design Engineer", "company": "Astera Labs", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-17T08:29:22-04:00", "url": "https://job-boards.greenhouse.io/asteralabs/jobs/4729059005", "is_hardware": true, "platform": "greenhouse", "jd_text": "Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\n\nLead Logic Design Engineer \n\nExperience\n\n6-10 years\n\nJob Summary\n\nWe are seeking a Lead Logic Design Engineer with deep expertise in micro-architecture and RTL design to lead the development of complex IPs/subsystems. The candidate will provide technical ownership across architecture, microarchitecture, RTL implementation, integration, and silicon bring-up.\n\nKey Responsibilities\n\nLead RTL/microarchitecture development for complex connectivity IP/subsystems.\n\nTranslate specifications and system requirements into robust hardware architecture.\n\nDesign high-performance and scalable logic for controllers/subsystems.\n\nWork across connectivity IP / subsystem layers including Transaction, Data Link, and Physical interface integration as applicable to the role.\n\nDevelop and review RTL using SystemVerilog/Verilog.\n\nDevelop robust mechanisms for flow control, ordering, buffering, arbitration, error handling, and reliability.\n\nDrive performance, latency, area, and power optimization.\n\nCollaborate with verification teams to develop verification strategies and debug complex failures.\n\nWork with SoC integration and physical design teams to ensure successful implementation.\n\nLead technical reviews and mentor senior engineers.\n\nSupport post-silicon debug and root-cause analysis.\n\nRequired Skills\n\nExtensive experience in complex connectivity IPs such as PCIE, UALink, Ethernet, CXL, UCIe.\n\nStrong RTL design experience using SystemVerilog/Verilog.\n\nDeep knowledge of PCIe architecture and protocol.\n\nStrong understanding of high-speed data paths, FIFOs, arbitration, flow control, and error handling.\n\nExperience with simulation, lint, CDC, synthesis, and timing considerations.\n\nStrong debugging and problem-solving skills.\n\nPreferred\n\nExperience of working in switching silicon.\n\nExperience of working on entire cycle from concept to silicon production.\n\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.", "jd_status": "stored"}, {"title": "IP Core Senior Engineer -GSD", "company": "Ericsson", "location": "Pune,Maharashtra,India", "date_posted": "2026-09-17T07:23:04+00:00", "url": "https://jobs.ericsson.com/careers/job/563121776709268", "is_hardware": true, "platform": "eightfold", "jd_text": "Join our Team\n\nAbout this opportunity:\nThe Network Engineer performs design, optimization and audit of a network to meet the customer requirements. The role is focused on executing design, audit and optimization services, where the network engineer is responsible for part of the solution and part of the service process. The Network Engineer is responsible to upkeep time, performance and quality according to Ericsson requirements and Customer contract.\nWhat you will do:\nAbility to Analyze, Discuss and Define Network Requirements and Review Network Solutions.\nCustomer facing role\nInteract with internal and external stakeholders for delivery execution\nExcellent communication skills\nPrepare IP Documents ( HLD/LLD as per Requirement).\nAbility to lead integration services for Telcom IP Networks.\nPerform MPBN Network Audit ( i.e. Security, Configuration & Hardware).\nTroubleshoots network problems and implements corrective action\nAnalysis of Different KPIs & Recommendation of Network Best Practices.\nDeliver technical assistance to the team.\nOptimization of MBPN and ISP networks.\nThe skills you bring:\nHands on experience in Configuration of Cisco, Huawei, Juniper, Arbor, Checkpoint, FortiGate and ZTE Network/Security Devices.\nHands on experience in Troubleshooting – Network related issues.\nExperience in Telecom Technologies (2G, 3G, 4G &  5G).\nExperience in Multi-Vendor Migration of Services.\nShould have sound knowledge in routing and VPN technology (OSPF, ISIS,BGP MPLS, SR & L3/L2 VPN, EVPN) and QOS along with Traffic Engineering\nShould have sound knowledge in Firewall, DDoS, DNS, DPI & load balancer.\nStrong understanding of ISP network technologies, including CDNs, IX, and network optimization techniques.\nSkillset\nPlanning, Design & Optimization of IP/MPLS Network.\nExcellent knowledge in Routing Protocols and MPLS Transport.\nIn-depth understanding and hands-on expertise in Layer 2 networking technologies.\nKnowledge of Managed Service telecom operations practice.\nExcellent verbal and written communication skills.\nAutomation Skills.\nProfessional /Expert IP Certification. (CCIE, JNCIE)\nProficient in DNS, CDN mechanisms, and the structure of ISP networks.\nExcellent skills in Microsoft applications like excel, Power Point, Word etc.\n\n“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”   \nWhy join Ericsson?At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.\n \nWhat happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.\n \nPrimary country and city: India (IN) || Noida\nReq ID: 787480", "jd_status": "stored"}, {"title": "Senior Engineer - Frontend CAD", "company": "Ericsson", "location": "Bangalore,Karnataka,India", "date_posted": "2026-09-17T06:53:53+00:00", "url": "https://jobs.ericsson.com/careers/job/563121776851988", "is_hardware": true, "platform": "eightfold", "jd_text": "Join our Team\n\nAbout this opportunity:\nAre you a hands-on engineer and ready to shape the future of silicon verification methodology and tools on a global scale? \nJoin our Design Verification Methodology team — a newly established global group defining methodologies and EDA workflows across our R&D sites in Bangalore, Austin, Stockholm, and Lund. \nWe are part of the Ericsson Silicon engineering unit, developing state-of-the-art ASICs and FPGAs at advanced technology nodes for Ericsson’s 5G and 6G product portfolio. Our environment offers deep technical challenges, opportunities for growth, and a wealth of expertise to learn from. Last year we started a new Silicon R&D center in Bangalore, ready to join? \n\nYou will do:\n\nIn this high-visibility role, you will shape the next generation of Front-End CAD (FECAD) methodologies, DV flows, and infrastructure for ASIC IP and SoC development.\nMajor part of your work is to work with DV activities of our proprietary tools development. \nYour impact will be central in optimizing methodologies and EDA workflows, driving efficiency and innovation across our global silicon engineering community.\nWe are particularly interested in individuals with exposure to or interest in applying AI/ML techniques to silicon design and verification — a significant plus as we invest in AI-driven design automation.\nIf you thrive on solving technical challenges, spotting opportunities for improvement, and driving continuous innovation, we’d love to have you on our team. \n\nYou will bring:\n\nDeep expertise in Testbench Architecture using SystemVerilog and UVM at IP, ASIC, and/or SoC level.\nPrevious hands-on experience in scripting (Python, Perl, bash, csh, etc.).\nStrong knowledge of layered UVM environments, reusable testbench components, and block/subsystem/SoC-level verification strategies.\nSolid understanding of directed and constrained-random verification, SVA, functional and code coverage closure.\nProficiency with front-end EDA tools: Verilog simulators, RTL/verification linters, CDC checkers, and formal verification.\nExperience with CI methodologies and tools (e.g., Jenkins).\nStrong grasp of modern silicon design methodologies and verification best practices.\nExperience collaborating across geographically distributed teams.\nExcellent communication skills and a strong sense of ownership in solving complex infrastructure challenges.\nExposure to AI/ML applications in design and verification flows (e.g., testbench optimization, anomaly detection, coverage prediction) is a significant advantage. \n\nResponsibilities:\n\nLead the development, verification, deployment, and support of complex front-end DV tools / flows.\nIdentify and solve flow, methodology, and tool inefficiencies across IP/ASIC/SoC environments; productize solutions to improve silicon quality and verification productivity.\nDrive innovation in design and verification processes, including AI-based enhancements.\nCollaborate closely with design, verification, test, and manufacturing teams to align on methodology, quality, and timelines.\nTroubleshoot technical challenges and implement scalable, long-term solutions.\nFoster a collaborative, forward-looking culture within the verification community. \n\n \n\nEducation & Experience \n\nBS/MS in Electrical Engineering, Computer Science, or related field.\n10+ years of relevant experience in ASIC design verification. \n\n*\n\n“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”\n\nWhy join Ericsson?At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.\n \nWhat happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.\n \nPrimary country and city: India (IN) || Bangalore\nReq ID: 788102", "jd_status": "stored"}, {"title": "PMIC Design Engineer, Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-17T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720567475", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nGeneral Summary:\n\nQualcomm PMIC team is a global organization responsible for delivering power and cost efficient solutions to mobile, compute, AR/VR, Auto and IOT products. Selected candidate will be part a new PMIC analog design team in Qualcomm Bangalore and be part of Qualcomm’s global PMIC design community. \nJob function includes but not limited to\nOversees definition, design, verification, and documentation of mixed signal circuits and/or products in the field of Power Management.\n\nExecutes the design and verification strategies of PMICs, for own specific assigned part of a block with supervision from technical lead.\n\nRuns functionality checks on a single block to ensure it meets specifications provided by team lead with minimal guidance.\n\nSeeks essential knowledge of industry trends, competitor products, and advances in the Power Management field from publicly available information\n\nIs actively involved in all aspects of the design from system definition/specification to circuit design and simulation, post silicon debug.\n\nCommunicate information that may be somewhat complex to others through written documents and orally in meetings.  Will require basic skills of negotiation, influence, diplomacy, and tact.\n\nHeavy involvement in overseeing layout and silicon evaluation is also expected.\n\nRequires expertise in one or more of the following engineering disciplines: power electronics (switch mode and linear), control theory, high accuracy data converters and analog front ends, high bandwidth linear amplifiers, very low power references, electro-migration and transistor reliability, behavioral modeling and UVI techniques.\n\nUses design tools such as Cadence ADE, MathWorks MATLAB, Verilog/VerilogAMS, System Verilog and others.\n\nActively participates in next generation initiatives and innovation.\n\n8+ years relevant experience\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "PMIC Design Engineer, Sr Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-17T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720567459", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nGeneral Summary:\n\nQualcomm PMIC team is a global organization responsible for delivering power and cost efficient solutions to mobile, compute, AR/VR, Auto and IOT products. Selected candidate will be part a new PMIC analog design team in Qualcomm Bangalore and be part of Qualcomm’s global PMIC design community. \nJob function includes but not limited to\nOversees definition, design, verification, and documentation of mixed signal circuits and/or products in the field of Power Management.\n\nExecutes the design and verification strategies of PMICs, for own specific assigned part of a block with supervision from technical lead.\n\nRuns functionality checks on a single block to ensure it meets specifications provided by team lead with minimal guidance.\n\nSeeks essential knowledge of industry trends, competitor products, and advances in the Power Management field from publicly available information\n\nIs actively involved in all aspects of the design from system definition/specification to circuit design and simulation, post silicon debug.\n\nCommunicate information that may be somewhat complex to others through written documents and orally in meetings.  Will require basic skills of negotiation, influence, diplomacy, and tact.\n\nHeavy involvement in overseeing layout and silicon evaluation is also expected.\n\nRequires expertise in one or more of the following engineering disciplines: power electronics (switch mode and linear), control theory, high accuracy data converters and analog front ends, high bandwidth linear amplifiers, very low power references, electro-migration and transistor reliability, behavioral modeling and UVI techniques.\n\nUses design tools such as Cadence ADE, MathWorks MATLAB, Verilog/VerilogAMS, System Verilog and others.\n\nActively participates in next generation initiatives and innovation.\n\n13+ years relevant experience\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Synthesis Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-17T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721049856", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Description:  \nShould have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.\n\nExperience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.\n\nExperience in all aspects of timing closure for multi-clock domain designs.\n\nShould be familiar with MCMM synthesis and optimization.\n\nShould have good understanding of low-power design implementation using UPF.\n\nExperience with scripting language such as Perl/ Python, TCL.\n\nExperience with different power optimization flows or technique such as clock gating.\n\nShould be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation\n\nShould be able to handle ECOs and formal verification and maintain high quality matrix\n\n2+ yrs experience\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RISCV CPU Design Verification Staff Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-17T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721086999", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nAdditional Job Description\n\nQualcomm is hiring strong DV engineers to verify high performance and low power RISC V based CPUs in Bangalore.\nRoles and Responsibilities\no  Develop and execute verification plans for units and features of a CPU design\no  Use simulation and formal verification methodologies to execute test plans, develop testbench components like checkers, assertions, stimulus generators.\no  Work closely with system architects, design team, software teams and Soc team to validate system use cases.\no  Work closely with emulation team to enable verification on emulators and FPGA platforms.\no  Debug and triage failures in simulation, emulation and/or Silicon.\nBE/BTech degree in CS/EE with 8+ years’ experience.\no Implementation of assembly and C language tests for verifying CPU architecture.\no  Experience in C/C++, scripting languages, HDLS like Verilog/System Verilog\no  Good Understanding of CPU architectures and CPU micro-architectures. Industry experience with CPU architecture (eg: x86, ARM, MIPS, RISCV, POWER) will be a plus\no  Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.\nPreferred Requirements:\no  Strong understanding of power management features in CPUs and CPU based Socs.\no  In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture\no  Experience with advanced verification techniques such as formal and assertions is a plus\no  Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RISCV CPU Design Verification Staff Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-17T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721098205", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nQualcomm is hiring strong DV engineers to verify high performance and low power RISC V based CPUs in Bangalore.\nRoles and Responsibilities\no  Develop and execute verification plans for units and features of a CPU design\no  Use simulation and formal verification methodologies to execute test plans, develop testbench components like checkers, assertions, stimulus generators.\no  Work closely with system architects, design team, software teams and Soc team to validate system use cases.\no  Work closely with emulation team to enable verification on emulators and FPGA platforms.\no  Debug and triage failures in simulation, emulation and/or Silicon.\nBE/BTech degree in CS/EE with 8+ years’ experience.\no Implementation of assembly and C language tests for verifying CPU architecture.\no  Experience in C/C++, scripting languages, HDLS like Verilog/System Verilog\no  Good Understanding of CPU architectures and CPU micro-architectures. Industry experience with CPU architecture (eg: x86, ARM, MIPS, RISCV, POWER) will be a plus\no  Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.\nPreferred Requirements:\no  Strong understanding of power management features in CPUs and CPU based Socs.\no  In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture\no  Experience with advanced verification techniques such as formal and assertions is a plus\no  Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Synthesis Engineer, Sr Lead", "company": "Qualcomm", "location": "Hyderabad, Telangāna, India", "date_posted": "2026-09-17T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720326923", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nJob Description:  \nShould have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.\n\nExperience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.\n\nExperience in all aspects of timing closure for multi-clock domain designs.\n\nShould be familiar with MCMM synthesis and optimization.\n\nShould have good understanding of low-power design implementation using UPF.\n\nExperience with scripting language such as Perl/ Python, TCL.\n\nExperience with different power optimization flows or technique such as clock gating.\n\nShould be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation\n\nShould be able to handle ECOs and formal verification and maintain high quality matrix\n\n5+ yrs experience\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Sr. Staff Engineer – Power Lead, Systems Architecture", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-17T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721135853", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Systems Engineering\nGeneral Summary:\nWe are seeking a Sr. Staff Power Lead – Systems Architecture to lead system-level power architecture, analysis, modeling, projection, optimization, and issue closure for complex SoCs and platforms. This is a systems architecture role, not a narrowly scoped circuit-power or physical-design position.\nThe successful candidate will define and assess system power states, power islands, operating points, workload scenarios, data movement, shared-resource policies, and power-performance-thermal trade-offs. The role will establish traceability from product use cases and architecture assumptions through pre-silicon estimates, design evidence, post-silicon measurements, correlation, and next-generation improvements. \n\nKey Responsibilities\nLead system power architecture for target SoCs and platforms from concept development through architecture freeze, design convergence, pre-silicon readiness, post-silicon characterization, and learning closure.\nTranslate product requirements, use cases, workload behavior, concurrency, duty cycles, thermal constraints, and performance KPIs into system-level power requirements and architecture decisions.\nDefine and analyze system power states, power islands, retention strategies, clock- and power-gating behavior, wake/sleep flows, operating points, DVFS policies, and cross-IP power-management interactions.\nEstablish top-down system power budgets and projections and work with IP teams to decompose targets, assumptions, modes, activity profiles, and optimization requirements.\nDevelop or guide workload-driven analytical, simulation, empirical, or hybrid models for power and performance projection.\nEvaluate architectural options across power, performance, thermal behavior, area, latency, responsiveness, complexity, risk, and user-experience objectives.\nPerform workload, use-case, concurrency, utilization, traffic, and data-movement analysis to identify system-level optimization opportunities.\nDrive cross-IP power optimization involving compute, memory, interconnect, multimedia, connectivity, peripherals, system infrastructure, firmware, and software policies.\nTrack gaps between targets and projections; lead technical investigations, root-cause analysis, mitigation planning, risk assessment, and issue closure.\nIntegrate IP-level models and implementation evidence into coherent system projections while making assumptions, model fidelity, uncertainty, and confidence ranges explicit.\nDefine architecture validation and measurement requirements so that pre-silicon hypotheses can be verified on emulation, prototypes, boards, and production silicon.\nCorrelate pre-silicon models and estimates with post-silicon rail, workload, telemetry, and performance measurements; explain material variances and feed calibrated models and architecture actions into subsequent products.\nPartner with SoC architecture, performance/modeling, IP architecture, RTL design, DV, physical design, firmware, software, thermal, validation, lab, and silicon teams.\nCommunicate system power status, trade-offs, risks, recommendations, and closure plans to technical and program stakeholders.\nDevelop reusable power-architecture methods, workload definitions, model standards, projection practices, dashboards, and review criteria.\n\nMinimum/Basic Qualifications\nBachelor’s degree in Engineering, Electrical/Electronics Engineering, Computer Engineering, Computer Science, Information Systems, or a related field and 10+ years of Systems Engineering, SoC Architecture, Power Architecture, Performance/Power Analysis, or related experience; or\nMaster’s degree in a related field and 8+ years of relevant experience; or\nPhD in a related field and 5+ years of relevant experience.\nApproximately 10+ years of relevant industry experience is preferred.\nStrong understanding of SoC and computer architecture, including compute subsystems, memory hierarchy, interconnects, system infrastructure, I/O, clock/reset, and HW/SW interaction.\nExperience in system power architecture, workload-based power analysis, power-performance analysis, system modeling, projection, optimization, or post-silicon power characterization.\nAbility to reason about dynamic and leakage power, operating modes, utilization, duty cycle, voltage/frequency operating points, concurrency, and thermal or sustained-performance effects.\nDemonstrated ability to lead cross-functional technical investigations and convert analysis into architecture or optimization decisions.\nStrong analytical, problem-solving, technical-communication, and stakeholder-leadership skills.\n\nPreferred Qualifications and Domain Expertise\nExperience defining SoC or subsystem power states, islands, low-power modes, sleep/idle behavior, wake-up paths, retention, power gating, clock gating, or DVFS.\nExperience with representative CPU, GPU, DSP, NPU/AI, memory, interconnect, multimedia, connectivity, peripheral, or full-platform workloads.\nHands-on experience with power/performance modeling, sensitivity analysis, projection, workload characterization, trace analysis, scripting, or large-data analysis.\nExperience correlating architecture models and pre-silicon estimates with post-silicon measurements and driving variance root cause and model calibration.\nFamiliarity with rail-level power measurements, silicon telemetry, performance counters, profiling, lab measurement methods, board bring-up, or system debugging.\nWorking knowledge of RTL/gate-level power inputs, activity factors, leakage/dynamic splits, corners, implementation data, or power-estimation tools.\nAwareness of UPF/CPF, power-domain crossings, isolation, level shifting, retention, structural low-power verification, synthesis, timing, or physical-design power considerations.\nUnderstanding of PMICs, regulators, power rails, PDN/power-grid considerations, thermal management, and their relationship to SoC operating policy.\nFamiliarity with Linux/Android, firmware, device drivers, system traces, power-management software, or Python/shell-based automation.\nPrior SoC architecture, subsystem architecture, IP microarchitecture, design, validation, or silicon-debug experience.\nDemonstrated technical leadership across distributed teams, including the ability to align stakeholders and influence decisions without direct authority.\n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Systems Engineering or related work experience.\n                                                                    OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Systems Engineering or related work experience.\n                                                                    OR\nPhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RISCV CPU Design Verification Principal Manager/ Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-17T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721098222", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n\nQualcomm is hiring strong DV engineers to verify high performance and low power RISC V based CPUs in Bangalore.\nRoles and Responsibilities\no  Develop and execute verification plans for units and features of a CPU design\no  Use simulation and formal verification methodologies to execute test plans, develop testbench components like checkers, assertions, stimulus generators.\no  Work closely with system architects, design team, software teams and Soc team to validate system use cases.\no  Work closely with emulation team to enable verification on emulators and FPGA platforms.\no  Debug and triage failures in simulation, emulation and/or Silicon.\nBE/BTech degree in CS/EE with 4+ years’ experience.\no Implementation of assembly and C language tests for verifying CPU architecture.\no  Experience in C/C++, scripting languages, HDLS like Verilog/System Verilog\no  Good Understanding of CPU architectures and CPU micro-architectures. Industry experience with CPU architecture (eg: x86, ARM, MIPS, RISCV, POWER) will be a plus\no  Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.\nPreferred Requirements:\no  Strong understanding of power management features in CPUs and CPU based Socs.\no  In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture\no  Experience with advanced verification techniques such as formal and assertions is a plus\no  Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "PMIC Design Engineer, Senior", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-17T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720567442", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nGeneral Summary:\n\nQualcomm PMIC team is a global organization responsible for delivering power and cost efficient solutions to mobile, compute, AR/VR, Auto and IOT products. Selected candidate will be part a new PMIC analog design team in Qualcomm Bangalore and be part of Qualcomm’s global PMIC design community. \nJob function includes but not limited to\nOversees definition, design, verification, and documentation of mixed signal circuits and/or products in the field of Power Management.\n\nExecutes the design and verification strategies of PMICs, for own specific assigned part of a block with supervision from technical lead.\n\nRuns functionality checks on a single block to ensure it meets specifications provided by team lead with minimal guidance.\n\nSeeks essential knowledge of industry trends, competitor products, and advances in the Power Management field from publicly available information\n\nIs actively involved in all aspects of the design from system definition/specification to circuit design and simulation, post silicon debug.\n\nCommunicate information that may be somewhat complex to others through written documents and orally in meetings.  Will require basic skills of negotiation, influence, diplomacy, and tact.\n\nHeavy involvement in overseeing layout and silicon evaluation is also expected.\n\nRequires expertise in one or more of the following engineering disciplines: power electronics (switch mode and linear), control theory, high accuracy data converters and analog front ends, high bandwidth linear amplifiers, very low power references, electro-migration and transistor reliability, behavioral modeling and UVI techniques.\n\nUses design tools such as Cadence ADE, MathWorks MATLAB, Verilog/VerilogAMS, System Verilog and others.\n\nActively participates in next generation initiatives and innovation.\n\n3+ yrears relevant experience\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU Power Modeling & Characterization Engineer (Staff/Senior Staff)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-17T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718595031", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nLooking for a CPU Power Modeling Engineer to work on high‑performance, low‑power CPU clusters (CPUSS / NCC) across pre‑silicon and post‑silicon phases.\nThe role focuses on DPM/EMON‑based power modeling, event‑to‑energy correlation, and power‑performance tradeoff analysis .\n\nKey Responsibilities\nDevelop CPU power models based on architectural micro‑events, PMU/EMON counters, and DPM frameworks\n\nBuild unconstrained vs HW‑limited CPU power models, incorporating Limiters, DVFS, temperature and throttling behavior.\n\nModel dynamic power, leakage, and rail‑specific behavior.\n\nDPM Weight Characterization\nDrive DPM weight characterization using simulation, emulation, and silicon data across representative workloads.\n\nCorrelate CPU event counts vs measured silicon power, debug gaps. \n\nEnhance DPM coverage by adding new CPU events and diags . \n\nRequired Skills\nMinimum 8 years of relevent experience is must\n\nStrong understanding of CPU micro‑architecture.\n\nHands‑on experience with DPM / EMON / PMU‑based power modeling. \n\nExperience with pre‑silicon and post‑silicon power correlation. \n\nProficiency in Python/Perl and data analysis.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "XR Systems Technology Architect", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-17T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446717818253", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Systems Engineering\nGeneral Summary:\nQualcomm is a key enabler for the XR eco-system with a dominant market share. We build custom SoCs and technologies that are at the heart of existing and emerging XR products. Qualcomm XR Systems organization is responsible for architecture definition of Qualcomm’s next generation XR SoCs. Our portfolio of SoC offerings serve a broad range of XR products covering Mixed Reality, Augmented Reality and AI Glass product families. The span of technologies that go into these products and SoCs include high resolution immersive displays, perception features that are bulit on computer vision and deep learning technology, highly efficient DSP processors, dedicated deep learning accelerators, graphics engines supporting high resolution and high frame rate rendering and reprojection, multimedia processing engines (audio, video, imaging,..), CPUs and SoC infrastructure that ensures efficient and secure processing, as well as very low power architecture features such as power islands and power rail isolation, sleep modes etc.\n\nWe are scaling up our operations!! We are looking for engineers with background in diverse areas including architecture and micro architecture definition, design and verification of IPs and SoCs. People who have experience in areas such as SoC architecture, networks on chip, virtual memory, on-chip and off-chip memory subsystems, security architecture, CPUs, etc, also development of IPs such as camera, video, GPU, DSPs, deep learning accelerators and neural signal processors (NSP), peripherals and interfaces such as PICe, SPI etc. Also, people with strong background on pre silicon and post silicon power estimation and optimization, performance estimation, power architecture design will be highly encouraged. We have openings at senior as well as junior job levels.\n\nWe are keenly interested in you if you are someone who has gained expertise in your specific domain which could be one or more of the areas mentioned above and are excited to take the next step in your career to become architects of the SoCs that will shape the future generations of XR products!! Apart from a rewarding career and growth prospects, the organization offers a unique opportunity to learn from a diverse set of experts working collaboratively under the same roof, towards a common goal.\n\nJob Overview\nQualcomm's XR Systems team is seeking system architects who will work on defining the next generation SoC architectures, enabling the future of Augmented Reality / Virtual Reality / Mixed Reality applications. Responsibilities of successful candidates may span one or more of the following areas:\nWorking with lead XR OEMs and QC’s customer-facing teams to understand end to end use cases\n\nResearching the product family roadmap to align internal IP and SoC architecture roadmap\n\nCollaborating with colleagues in the architecture team and across technology, IP and SoC teams with diverse expertise\n\nExploring architectures for power efficient and performant mapping of use cases on future SoCs and coming up with architecture proposals\n\nDefining and optimizing use case data flows\n\nUse case power modeling, estimation and optimization\n\nWorking with SoC design, and validation teams to ensure that the use case power and performance KPIs are met.\n\nMinimum Qualifications\nBachelor’s degree in Electrical Engineering, Information Systems, Computer Science, or related field, and project experience in architecture/micro-architecture\n\nExperience (2 to 15 years) in areas covering at least one of the following: IP and SOC design, DV, micro architecture, architecture, camera, video, GPU, DSP, NSP, CPU, security, NOCs and DRAM controller subsystems, power architecture and power and performance estimation and optimization.\n\nExcellent problem solving and communication skills\n\nPreferred Qualifications\nMaster’s and/or PhD degree in Electrical Engineering, Information Systems, Computer Science\n\nExperience with Mixed & Augmented reality system design, constraints, and trade-offs\n\nDeep understanding of system architecture aspects such as NOCs, DRAM controller performance issues, power domains and sleep modes of memories, IPs and cores.\n\nProven experience in conducting architectural trade-offs, power/performance analysis and/or SW-HW trade-offs\n\nExperience with system level modeling (performance and/or power)\n\nProficiency in scripting languages such as python, perl, shell etc.\n\nKeywords\nCamera, GPU, CPU, SOC, SoC architecture, NOC, DDR subsystem, LPDDR IP, caches, security, virtual memory, development, RTL design, Computer vision, Artificial Intelligence, ML, DSP, AR, VR, MR, XR\n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.\n                                                                    OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience.\n                                                                    OR\nPhD in Engineering, Information Systems, Computer Science, or related field.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "System HW Applications Engineer, Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-17T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721034719", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Description\nAs a member of Qualcomm Customer engineering team, the individual will be responsible for successful integration of Qualcomm solution into customer end products in Mobile, Compute, 5G Broadband, Automotive, IoT and consumer electronics markets.Gathers, integrates, and interprets information across cross functional teams from a variety of sources in order to troubleshoot issues and find solutions.Applies deep and broad knowledge to anticipate and identify gaps/risks in processes, efforts, technical aspects of HW/System aspects etc., and closes the gaps with wide range of eco-system partners within Qualcomm and enable customer product commercializationIndividual will be responsible and acts as a tech lead on projects and owns the outcome of the project for supporting Qualcomm's growing portfolio of platforms/applications. Job involves working closely with internal partners in definition of product (as appropriate), collaborate with HW/SW/validation/test and product teams on customized use cases of customer applications, support customers on HW design signoffs, system/SoC debug, deliverables etc and effectively managing cross functional team of engineers.Individual will be responsible to create chipset documentation, assist customers in technical responses to customer queries and troubleshooting of customer designs from overall system and SoC point of view. Candidate should have minimum 8+ Years of relevant experience.Past expertise and experience in interacting with multiple teams in HW, SW, domain skills in Digital/High Speed/SoC, Power Management, Silicon validation, Customer engagement, ability to adapt dynamic changes to meet tight deadlines/commitments and deliver customer requirements, Strong written and oral communication skills is highly desirable.Travelling to customer sites across geographical locations in Asia/NA etc on need basis\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nPreferred Qualifications\nEmbedded systems HW/SW design preferably ARM based, board bring up, Silicon bench tests/ Characterization, measurements AC/DC parameters, SOC interface parametric measurements, basic SW integrated functional tests, Silicon validation, HW PCB design, High speed peripheral expertise, Signal Integrity and Power Integrity, System level architectureProgramming languages: ‘C’ and scripting languages PERL/PYTHON preferred. Good trouble-shooting skills with analysis and debug ability at PCB, HW IP, SW and SoC level. Expertise in High Speed Digital interfaces such as: Memory Bus I/F (UFS, eMMC, LPDDRx), USB, MIPI CSI/DSI, PCIe, SERDES etc and Power management areas like LDO, SMPS, Clock, Crystal etc. Hands on experience in working with Oscilloscopes, Logic Analyzers. Basic knowledge of ARM processors, Multi core architecture, experience in working with JTAG emulators. Knowledge of Multi-core system/inter-chip system design is a plus.Experience in technical leadership and people management, guiding cross-functional engineering teams. Proven track record in leading projects to successful completion while supporting team growth and development.\nKeywords\nEmbedded systems, Silicon Characterization, LPDDR4x, LPDDR5, LPDDR, NAND, UFS, eMMC, SERDES, PCIe, MIPI, USB, UART, SPI, I2C, Logic Analyzer, PADS, Allegro, ARM processor, JTAG, LDO, SMPS, Clock, Crystal, Board bring up\nEducational Requirements\nRequired: Bachelor's, Electronics and/or Electrical Engineering Preferred: Master's, Electronics and/or Electrical Engineering\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SOC Design - Senior Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-17T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720693268", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    2+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates complex features and functionality into hardware designs in line with proposals or roadmaps for complex products.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the novel manufacturing of solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for complex Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making is significant in nature and affects work beyond immediate work group.\n•    Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. \n•    Has a moderate amount of influence over key organizational decisions.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Infra Formal Verification Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-17T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721114863", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\n\nQualcomm Infra and Periph team in India is part of a worldwide team responsible for developing and delivering Infra and Periph solutions which are setting the benchmark in Mobile/Compute/Automotive industry. The role of Infra and Periph Formal verification Engineer will involve Verification of the Infra and Peripheral RTL using industry standard Formal Verification tools and technologies based on latest model/equivalence checking algorithms\nThe role also requires close collaboration with worldwide design, systems and EDA/CAD teams. Hence, we are looking for candidates with strong communication skill – both written and verbal. For better understanding of some of our products, please refer to the links below\nhttps://www.qualcomm.com/products/smartphones\nMinimum Qualifications\nMinimum 4-12 years of VLSI industry experience\nStrong analytical skills to solve complex problems.\nSpecialization in formal verification with tools like Jasper Gold or VC-Formal\nKnowledge of cutting-edge formal verification methodologies and techniques.\nAble to implement abstraction techniques for effective verification.\nHands-on experience with Verilog / System Verilog HDLs, temporal logic assertions, and able to understand complex RTL quickly.\nProficient with scripting languages such as Perl, TCL and(or) Python\nEducation:\nBachelors - Computer Science, Bachelors - Electronics and Communications Engineering, Bachelors - Information Systems\nWork Experiences:\nCertifications:\nSkills:\nSystem Verilog Assertions, Formal Verification, System Verilog\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-17T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720513982", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    3+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n\nPrincipal Duties and Responsibilities:\n•    Applies Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Assists in the assessment of complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Sr Lead Engineer - HW Board Design", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-17T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720932783", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    8+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates complex features and functionality into hardware designs in line with proposals or roadmaps for complex products.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the novel manufacturing of solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for complex Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making is significant in nature and affects work beyond immediate work group.\n•    Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. \n•    Has a moderate amount of influence over key organizational decisions.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Sr Lead Engineer - DFT", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-17T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721073482", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.\n•    5+ years of ASIC design, verification, validation, integration, or related work experience.\n•    2+ years of experience with architecture and design tools.\n•    2+ years of experience with scripting tools and programming languages.\n•    2+ years of experience with design verification methods.\n•    1+ year of work experience in a role requiring interaction with senior leadership (e.g., Director level and above).\n\nPrincipal Duties & Responsibilities:\n•    Leverages ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.\n•    Creates architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.\n•    Collaborates across teams (e.g., software architecture, hardware architecture) to develop and execute an implementation strategy that meets system requirements and customer needs.\n•    Evaluates all aspects of complex process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.\n•    Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable architecture and design of multiple blocks/SoC or IC Packages.\n•    Writes and reviews detailed technical documentation for EDA/IP/ASIC projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc.  \n•    Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions).\n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Technical Staff Engineer - Design", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-09-17", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Technical-Staff-Engineer---Design_R3412-26-4", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nThe successful candidate will join the rapidly growing Data Center Solutions (DCS) business unit at Microchip.  DCS has a broad portfolio of products widely deployed by the industry’s cutting-edge server/storage OEMs and hyperscale datacenters.  Customers deploy DCS solutions into applications ranging from Big Data capacity storage to artificial intelligence and machine learning that are helping to shape the next digital age.  Our product portfolio includes SAS/PCIe/NVMe/CXL products that connect, manage, and secure the world’s information, including Flash Controllers, High Performance Switches, RAID Controllers and Memory Controllers.  Join a team where you can expand your skill set and drive key elements of the industry’s technology leadership.\n\nAn opening exists for Tech Staff Design Engineer with an interest in developing the next generation of storage and memory controller SoC products.  This will involve taking a design from initial concept through to production. Throughout you will work beside experienced engineers and be exposed to Microchip’s Best-In-Class engineering practices. Working side-by-side with some of the brightest minds and most innovative people in the industry, you won't just fill a position, you will be given an opportunity to work on a team where your contributions matter. Microchip fosters continuous learning in a challenging and rewarding environment.  If this sounds like the kind of environment you'd like to participate in, we'd like to hear from you!\n\nAs a Staff Design Engineer, your job will entail the following:\nOwn design planning and construction of pad rings, bump patterns, ensuring alignment with package and system-level constraints.\n\nDevelop, implement, and maintain IO connectivity, pad ring definitions, and bump pattern designs throughout the design cycle.\n\nGenerate and validate physical design handoff deliverables including pad ring DEF files, Verilog netlists, bump maps, and associated implementation data for downstream teams.\n\nEnsure IO and pad ring designs comply with design standards, package constraints, and implementation best practices.\n\nCollaborate with Architecture, Product Design, Internal IP Packaging, Implementation, Product Engineering, Technology Development, and Foundry teams to align on IO/package requirements and resolve technical issues.\n\nSupport Verification, Emulation, ASIC validation, and silicon debug efforts by analyzing IO-related issues and driving design improvements.\n\nRequirements/Qualifications:\n\nB.S degree in electrical engineering with 12+ years related experience.\n\nHands-on experience with pad ring planning, IO cell placement, and bump map/pattern definition for advanced SoC designs.\n\nKnowledge of IO library cells, IO standards, and PHY-level IO interfaces (SerDes, DDR, PCIe, CXL).\n\nExperience with IO planning and implementation EDA tools (e.g., Orbit IO, ISP or equivalent); specific tool experience is valuable but not mandatory.\n\nExperience generating and validating IO connectivity deliverables (pad ring DEF, IO netlist, bump assignment) for physical design hand-off).\n\nUnderstanding of Foundation and Hard IP related views including RTL, lef and liberty\n\nWorking proficiency in flow automation and scripting using tcl and/or python\n\nExcellent analytical, communication (written and verbal), and documentation skills.\n\nPreferred qualifications:\nM.S degree in electrical engineering\n\nBasic understanding of DFT methodologies mainly JTAG/Boundary Scan (IEEE 1149.1) architecture and TAP controller operation for including post-silicon bring-up and debug flows for SoC IO validation\n\nExposure to RTL compilation and Synthesis flow including understanding of Verilog/System Verilog is desirable\n\nWorking knowledge of Industry standard Project management, versioning and tracking tools e.g. SVN, JIRA.\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "CPU Pre-Silicon Verification Lead", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-17", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/CPU-Pre-Silicon-Verification-Lead_JR0287106", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nRole and Responsibilities\nYou will be part of Intel Core Design Team driving Intel's latest CPU's in the World's leading process technologies. Develops pre-Silicon functional verification tests to verify system to meet design requirements. Creates test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. Analyzes and uses results to modify test bench and tests.\n\nWe're looking for a highly motivated, Pre-Silicon Verification Lead/Manager who is responsible to ensure:\n• CPU Core Group is looking for Pre-Silicon Verification Lead/Manager who leads and guides a team to ensure:\no Driving Strategic Tool/Flow/Methodologies/Quality Initiatives for 1st Pass Silicon from definition to Implementation and Deployment in Projects to reduce overall Cycle Time of Validation Project Cycle for PRQ Quality.\no Development of Complex Pre-Silicon Verification environments for simulation, development of Verification Components and coverage plans. Rigorously driving to improve Validation Plans to ensure Right First Time Success of our Products. Work directly with hardware architects, logic designers to influence overall SoC and system design. Has demonstrated past track record of technical leadership and has managerial experience.\n• Plans, provides resources and drive activities in engineering function to meet schedules, standards, and cost.\n• Cultivates and reinforces appropriate group values, norms and behaviors. Identifies and analyzes problems, plans, tasks, and solutions.\n• Provides guidance on employee development, performance, and productivity issues.\n• Plans and schedules daily tasks, uses judgement on a variety of problems requiring deviation from standard practices.\n• Technically guides test plan development, verification methodology, tracks deliverables to ensure timely execution with high quality and networks with peers locally and across sites for beating commitments\n\nQualifications:\nCandidate must possess a master's degree in Electronics or Computer Engineering with at least 15 or more years of experience in related field or a Bachelor's Degree with at least 10 years of experience in Pre-Silicon Verification Environment.\n\nPreferred Qualifications:\n• Experience with RTL design, Verilog and Simulation/Emulation, debug tools such as Verdi, System Verilog based verification techniques\n• Familiarity with CPU architecture/Processor Verification - Must\n• Experience in Perl/Python and Linux OS\n• Experience in development of integrated software and/or hardware environment - advantage\n• Experience in working with SVTB UVM or Specman (e) - advantage\n• Team player, passionate, energetic, motivated, and drive global activates.\n• Candidate should demonstrate excellent Self-motivation, communication, strong problem solving and teamwork skills.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Memory Layout Manager", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-17", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Memory-Layout-Manager_JR0287176", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nWe are seeking a skilled and motivated Layout Design Engineering Manager to lead a team of layout engineers in delivering best in class SRAM,RF,ROM,CAM Memory compiler designs across the Intel's bleeding FinFETs,GAA technologies. In this role, you will champion technical execution by overseeing compiler friendly and optimized floorplanning, high-density,performance based placement and routing template, and rigorous physical sign-off processes including DRC, LVS, Yield, DFM, Density, parasitic extraction, Noise Reliability i.e. EM, IR. You will provide technical guidance, set clear goals, and foster cross-functional collaboration with circuit design, Tilers, and foundry teams to meticulously optimize memory area, performance, power, and yield. Beyond daily execution, you will spearhead layout methodology innovations, establish advanced automation flows using SKILL, Python, or Tcl, and cultivate a culture of technical excellence by mentoring senior and staff-level engineers. The role requires a strong vision for leveraging AI and ML technologies (such as reinforcement learning for routing or predictive analytics for DRC debugging) to make execution significantly more efficient, robust, and high-quality.\n\nBusiness group\nThe Intel Foundry group plays a pivotal role in enabling innovative semiconductor manufacturing solutions that power Intel's products and those of our partners worldwide. As part of the BA Memories organization, this position supports the development of advanced memory technologies and methodologies, empowering Intel's mission to shape the future of technology and create world-changing advancements.\n\nKey Responsibilities\n- Lead and mentor a team of layout design engineers to developed world class memory compiler designs on FinFets/GAA technologies, ensuring alignment with organizational goals and timelines.\n- Oversee the design, development, modification, analysis, and verification of memory compiler layout designs.\n- Provide technical guidance for analog, digital, memory, and standard cell layout methodologies, compilers, tools, and flows.\n- Enable teams to execute effectively by setting clear objectives, maintaining accountability and facilitating productive workflows through AI-driven EDA tools and generative machine learning models into the design lifecycle to automate repetitive layout tasks, accelerate routing, and optimize cell placement.\n- Drive team results by inspiring and developing team members, modeling Intel values, and fostering a supportive and collaborative environment.\n- Manage resources effectively to optimize project execution and meet performance targets.\n\nQualifications:\nMinimum Qualifications\n- Candidates must possess a Bachelor's or Master's degree in Electronics, Electrical, or VLSI Engineering paired with 15+ years of deep technical experience in memory compiler layout design and management.\n- You must have a proven track record of successful tape-outs on cutting-edge foundry geometries (such as 3nm, 2nm, or below) using industry-standard EDA environments like Cadence Virtuoso, Siemens Calibre, and Synopsys IC Validator along with expert-level proficiency in driving layout methodologies and flows for analog, digital, memory, and standard cells.\n- Demonstrated ability to lead teams and manage complex projects effectively.\n- Demonstration of strong emotional intelligence, exceptional interpersonal communication, and an ability to lead, scaling high-performing engineering teams in a fast-paced semiconductor environment.\n\nPreferred Qualifications\n- Strong communication and interpersonal skills with the ability to collaborate across teams and disciplines.\n- Experience in strategic decision-making and performance management for technical teams.\n- A track record of fostering innovation and driving a culture of excellence.\n- Passion for developing team members and maintaining a productive and inclusive work environment.\n\nJoin us in shaping the future of technology and take your leadership and technical expertise to the next level by driving meaningful innovation at Intel.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Electrical Engineer", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2026-09-17", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/Electrical-Engineer_R2628530", "is_hardware": true, "platform": "workday", "jd_text": "Who We Are\n\nApplied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI and accelerating the commercialization of next-generation semiconductor chips. Join us and push the boundaries of materials science and engineering in a company at the foundation of the electronics industry. The work we do together advances the world’s technology.\n\nWhat We Offer\n\nLocation:\nBangalore,IND\nYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. \n\nAt Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. \n \n \nAs an Electrical Engineer, you are responsible for designing, modifying, and troubleshooting electrical or electronic engineering assemblies, layouts, schematics, and drawings to advance the equipment that supports our technology. Using your technical experience and critical thinking skills, you will perform engineering analysis, generate test reports, develop innovative solutions, and create documentation for product releases. You will also coordinate the procurement and assembly of components, identify sources of critical parts, and resolve technical issues to ensure peak performance. \n \nRole Responsibilities: \nDesign or modify electrical or electronic engineering assemblies, layouts, schematics, drawings, or specifications of difficult scope \n\nIdentify and troubleshoot a variety of complex electrical problems with limited supervision \n\nDefine, coordinate, perform and generate engineering test reports with limited supervision \n\nPerform engineering analysis of difficult scope with limited supervision \n\nTechnically lead or execute engineering projects, including the development of key suppliers \n\nImplement concepts for a variety of complex product issues and electrical solutions of difficult scope \n\nGenerate electrical product specifications; specify and review engineering documentation \n\nServe as a resource for junior colleagues; lead project teams, as needed\n\nClearly communicate difficult or sensitive information; build consensus \n\nMinimum Qualifications: \nBachelor’s degree\n\n4-7 years of experience in a related field\n\nPreferred Qualifications: \nStrong knowledge of industry best practices, key business drivers, competition in the marketplace, and how your area of expertise integrates with others  \n\nDemonstrated leadership skills to lead small projects as needed  \n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nAssignee / Regular\nTravel:\nYes, 10% of the Time\nRelocation Eligible:\nNo\n\nApplied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "Senior principal DFT engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-09-17", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Senior-principal-DFT-engineer_R-10065783", "is_hardware": true, "platform": "workday", "jd_text": "Generic Job Description (not Job Level specific): The Digital Design Engineer / Architect is responsible for defining and realizing Digital functions on IPs, Subsystem or IC level based on required specifications. The individual is responsible for design, verification and evaluation of those. The individual is accountable for designing according to specifications, quality and reliability needs. Participation in problem solving for Digital and system domain of the device. Author of the design-specific documentation for internal and external use.\n\nMore information about NXP in India...\n\n#LI-9415", "jd_status": "stored"}, {"title": "Senior Circuit Silicon Correlation DFT Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-09-17", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Circuit-Silicon-Correlation-DFT-Engineer_JR2012806", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work , to amplify human imagination and intelligence. Make the choice to join us today.\n\nWhat will you be doing:\nParticipate in ground breaking Processor design and debug in deep submicron technologies.\n\nWork in a multi functional team passionate about Silicon characterization and correlation to pre-Silicon Performance and Power models.\n\nResponsible for generating ATPG patterns for Silicon speed path debug.\n\nRTL and gate level verification for ATPG, non-ATPG patterns.\n\n Correlating diagnosis result to map to real design failures. Root cause the same feed learnings to  pre-silicon design sign off parameters.\n\nRAM correlation by studying RAM circuit failure mechanisms and understanding their limits on silicon\n\nBring in more circuit understanding into the RAM testing methods across RAM types, chips and processes and improve correlation in the long run\n\nDevelop new methodologies using DFT infrastructure to analyze components of mis-correlation in logic and in/around RAM.\n\nWhat we need to see:\nBSEE required/MS preferred in Electrical or Electronics Engineering with 8+ years experience; Prior leadership experience a certain plus.\n\nGood understanding of Design-for-test(DFT) and logic design is required.\n\nMust possess a solid understanding of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation.\n\nMust have some experience in bringing up RTL/gate level simulation, writing testcase and debugging it.  \n\nBasics of circuits and RAM functionality/architecture will be helpful.\n\nExperience in VLSI simulation tools like VCS etc\n\nExperience with pattern generation using tools such as tessent.\n\nProficiency in scripting language, such as, Python, Perl, Tcl, Make and automation methods/algorithms would be good.\n\nPrior experience in STA and basic understanding of circuit concepts will help in the role.\n\nPost-Silicon data gathering experience is a plus.\n\nNVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. If you're creative, autonomous and love a challenge, we want to hear from you.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Applications Engineering, Sr Engineer - PrimeTime", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-17", "url": "https://careers.synopsys.com/job/bengaluru/applications-engineering-sr-engineer-primetime/44408/100768195984", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nYou treat ambiguity as an invitation to bring clarity, not as a reason to slow down. Stepping into complex, high-stakes moments with a steady presence comes naturally to you. You listen carefully for what's unsaid, ask the questions that unlock momentum, and align people around the real problem, not just the loudest symptom. Tight timelines and high expectations energize you because you know how to prioritize what matters, communicate tradeoffs early, and keep progress visible without creating noise.\nPartnership over posturing defines how you approach customers and internal teams. The back-and-forth of discovery energizes you, and you naturally translate between technical, business, and everything in between so decisions get made with confidence. You don't just deliver answers. You build trust by being transparent, direct, and constructive, especially when the message is hard. When something breaks, curiosity and methodical thinking guide you as you trace causes with patience while keeping the bigger picture in view.\nConstantly looking for leverage is part of who you are. Patterns reveal themselves to you, one-off fixes become repeatable playbooks, and you leave behind cleaner processes than you found. Precision balanced with pragmatism helps you know when to go deep and when to move forward with a well-framed assumption. Above all, you bring a collaborative intensity that is calm, driven, and generous, helping the team move faster together while keeping quality and integrity non-negotiable.\n\nWhat You'll Be Doing\nSupport Synopsys PrimeTime Static Timing Analysis tool across pre-sale evaluations, post-sale deployments, and ongoing customer engagements\nDrive product adoption by running competitive benchmarks, leading customer evaluations, and articulating technical advantages to design teams and engineering management\nDeliver customer training sessions, technical presentations, and hands-on workshops that maximize user proficiency and satisfaction with PrimeTime\nProvide tape-out support by troubleshooting complex timing issues, resolving signal integrity problems, and ensuring successful project completion under deadline pressure\nCollaborate with R&D, product marketing, and sales teams to relay customer feedback, influence product enhancements, and shape roadmap priorities\nDevelop and maintain technical documentation, best practices guides, and knowledge base resources that scale your expertise across the customer base\nParticipate in advanced customer collaboration initiatives that drive innovation, uncover new use cases, and strengthen long-term partnerships\n\nThe Impact You Will Have\nAccelerate customer project timelines by enabling efficient use of PrimeTime and optimizing design flows that remove timing closure bottlenecks\nEnhance customer satisfaction and loyalty through expert support, proactive problem-solving, and training that builds internal capability\nStrengthen Synopsys' leadership in static timing analysis and semiconductor design solutions by delivering measurable wins in competitive engagements\nFacilitate feedback loops between customers and internal teams that drive continuous innovation in product features, usability, and performance\nEmpower customers to achieve superior chip performance, power efficiency, and cost optimization that directly affect their product success\nContribute to successful tape-outs and high-impact design wins for industry-leading clients building next-generation silicon\nBuild reusable methodologies and documentation that multiply your impact across the global customer base and internal teams\n\nWhat You'll Need\nDeep hands-on expertise in Synopsys PrimeTime STA tool, including advanced features, timing analysis methodologies, and real-world application across multiple design nodes\nStrong understanding of timing corners, process variations, signal integrity issues, and how they affect timing closure in modern semiconductor designs\nFamiliarity with synthesis, physical design, extraction, and ECO methodologies, and how they integrate with static timing analysis workflows\nProficiency in TCL scripting for automation, tool customization, and workflow optimization\nExcellent verbal and written communication skills with experience in customer-facing roles, experience delivering technical training or presentations is a plus\nBSEE or equivalent with 3+ years of relevant experience, or MSEE or equivalent with 4 years of experience in applications engineering, design, or verification roles\n\nWho You Are\nYou collaborate naturally, valuing diverse perspectives and fostering environments where different technical viewpoints strengthen the outcome\nProactive problem-solving defines your approach. You work independently, manage multiple priorities without losing threads, and know when to escalate or pull in help\nAdaptable and resilient, you thrive when priorities shift, timelines compress, or technical challenges require creative thinking under pressure\nDetail-oriented with a commitment to delivering high-quality results, you catch the edge cases and corner conditions that others miss\nYou can explain a complex timing closure tradeoff to a customer VP in two sentences without losing the nuance, and then turn around and debug a TCL script with an engineer\nYou notice when a customer question signals a deeper workflow issue, and you address both the immediate ask and the underlying gap\n\nThe Team You'll Be Part Of\nYou'll join a talented applications engineering team that supports the industry-leading Static Timing Analysis tool, PrimeTime. The team's core purpose is to drive increased product usage, ensure customer success, and collaborate closely with R&D, marketing, and sales to foster innovation. Together, you will enable customers to build next-generation silicon chips faster and more efficiently, playing a vital role in Synopsys' global leadership in chip design and verification.\n\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior Engineer- Modelling", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-17", "url": "https://careers.arm.com/job/bengaluru/senior-engineer-modelling/33099/100747323856", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Description\nArm’s Physical IP Division develops Physical IP that is extensively used by SoC designers around the world to build sophisticated, high-performance chips on groundbreaking process nodes.\nWe are seeking a highly skilled and technically proficient engineer with experience in ASIC front-end design methodologies across IP and SoC design domains, to join the Design Enablement team within Solutions Engineering - Implementation organization. The role will focus on developing and deploying models for various types of Physical IP, including standard cells, embedded memories, and custom blocks.\nResponsibilities:\nWork alongside IP design teams to grasp the functionality and implementation of Physical IP. Coordinate with EDA vendors and SoC design teams to set modeling requirements and specifications.\nDevelop models according to specifications, validate them in relevant EDA flows, and deploy and support the models for production use.\nDevelop robust validation methodologies to ensure model correctness, quality, and compatibility with downstream design flows.\nAutomate model development, validation, and release workflows using scripting and software engineering techniques, including the effective use of LLMs and AI-assisted development tools.\nContinuously improve model quality, performance, development efficiency, and turnaround time.\nInvestigate modeling and flow issues and work together with internal groups and EDA vendors to identify and apply solutions.\nVital Skills and Experience:\nSolid grasp of ASIC/SoC build flows, particularly simulation, synthesis, Design-for-Test (DFT), ATPG, and logic equivalence checking using industry-standard EDA tools.\nExperience with Verilog and SystemVerilog modeling and verification.\nGood understanding of digital circuit fundamentals, logic composition, and gate-level netlist.\nStrong automation and scripting skills using languages such as Python, Tcl, shell scripting, or Perl.\nStrong analytical and debugging skills, with the ability to investigate complex interactions between models and EDA tools.\nAbility to quickly learn new technologies and methodologies, work independently, and take ownership of new and sophisticated technical issues.\nCapacity to engage successfully with engineering groups spread across different locations and EDA vendors.\nBachelor’s or Master’s degree or equivalent experience in Electronics, Electrical, Computer Engineering, or a related field, with 5+ years of relevant proven experience.\n'Preferred' Skills and Experience:\nExperience with Memory BIST, ATPG, and low-power design methodologies.\nExperience using artificial intelligence techniques for model development and for automating and optimizing engineering workflows.\nExperience with software engineering guidelines, including Git/Gerrit or similar version control systems, test methodologies, continuous integration (CI), and test automation.\nComfortable working in a fast-paced engineering environment, handling changing priorities, and maintaining a collaborative and positive approach when addressing challenging technical problems.\nExperience collaborating with engineering teams distributed across multiple geographical locations and time zones.\n \nIn Return:\nAt Arm, we offer a vibrant, collaborative environment where you will work with colleagues who demonstrate creativity and a strong drive for problem-solving. We are committed to encouraging a diverse and inclusive workspace where everyone feels valued and can contribute to their fullest potential. You will have the opportunity to work on innovative technologies and make a significant impact on the future of semiconductor innovation. Join us and be part of a team that is determined to push the boundaries of what’s possible!\n \n#LI-BB1\nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Lead Performance Modeling Engineer – GPU SoC", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-16T09:09:00+00:00", "url": "https://global-external-amd.icims.com/jobs/90966/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. Lead Performance Modeling Engineer – GPU SoC   The Role: Architect, Analyze and optimize high-performance SoCs for Cloud computing, and machine learning acceleration. Propose solutions to enhance performance and optimize power. Explore, analyze and optimize next-generation data center systems. The Person: Do you seek the most sophisticated challenges in the computing industry? As a passionate system performance architect on our design engineering team, you will propose and implement solutions to our next generation GPU SoC and data center system application performance issues. Key Responsibilities: Serve as a Performance Architect in AMD's electronics design engineering team. Participate in microarchitecture exploration, performance modeling, and analysis for next-generation GPU and data center systems. Intimately understand design architecture and propose solutions to enhance performance Responsible for micro-benchmarking, workload characterization, competitive analysis, bottleneck identification, and optimization. Develop tools and methodology for performance analysis of workloads. Communicate, propose, and implement solutions to processor and system performance issues. Preferred Experience: Experience with GPU, CPU or computer system microarchitecture Experience with the development and usage of computer system performance models Experience with computer workload analysis Strong programming skills, including experience with C++ and Python (or similar) Academic Credentials: Bachelors, Masters, or PhD degree in Electrical Engineer, Computer Engineering, Computer Science or a closely related field Masters or PhD with emphasis on Computer Architecture performance studies preferred #LI-PK1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Leadership Role - DFT", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-16T06:28:00+00:00", "url": "https://global-external-amd.icims.com/jobs/88778/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. Leadership Role - DFT THE ROLE: As a Principal Member of Technical Staff (PMTS) in the IODC SoC DFT organization, you will lead end-to-end ATPG strategy, implementation, and pattern validation for complex, multi-million gate SoCs powering next-generation SOCs. You will be responsible for driving all ATPG execution activities from DFT architecture definition through pre-silicon verification, production test enablement, silicon bring-up, and manufacturing ramp. This role requires close collaboration with RTL, DFT RTL, DFT Verification, Physical Design, Product Engineering Operations (PEO), ATE, and Silicon Validation teams to ensure high-quality test content, optimal coverage, tester readiness, and successful silicon deployment. The ideal candidate combines deep technical expertise in ATPG, scan methodologies, and pattern validation with proven experience delivering production-quality test solutions for large-scale SoCs. THE PERSON: You are a highly motivated technical leader with extensive experience in SoC DFT and ATPG execution. You thrive in a fast-paced environment, enjoy solving complex debug challenges, and possess a strong track record of driving cross-functional execution from design conception through manufacturing. You are comfortable working across multiple organizations, influencing technical direction, mentoring engineers, and serving as the key technical expert for ATPG signoff and silicon test readiness. IMPACT This role serves as the technical owner for ATPG execution across critical SoC programs and directly influences product quality, manufacturing yield, test cost, and time-to-market. The successful candidate will play a key role in enabling first-silicon success and scaling robust DFT methodologies across future AMD SoC generations. KEY RESPONSIBILITIES: Own end-to-end ATPG execution for large-scale SoCs from architecture phase through silicon production. Define and drive ATPG methodologies, test strategies, coverage closure plans, and pattern signoff criteria. Generate and validate scan, transition fault, cell-aware, bridge, chain diagnosis, and compression-based ATPG patterns. Drive pattern quality improvements, tester efficiency optimization, and test cost reduction initiatives. Partner closely with DFT RTL, DFT Verification, RTL, Physical Design, and Timing teams to ensure robust DFT implementation and testability. Collaborate with PEO and ATE teams to enable tester bring-up, pattern correlation, tester debug, and manufacturing deployment. Lead pattern validation activities across simulation, emulation, ATE, and platform environments. Drive root-cause analysis and resolution of ATPG, tester, silicon, and yield-related issues. Ensure high-quality pattern delivery meeting schedule, coverage, power, and manufacturing requirements. Support silicon bring-up, diagnosis, yield learning, and production ramp activities. Develop automation flows and AI-enabled solutions to improve ATPG productivity and debug turnaround time. Mentor junior engineers and drive ATPG best practices across the organization. PREFERRED EXPERIENCE: 16+ years of experience in SoC DFT with strong expertise in ATPG and manufacturing test. Proven ownership of ATPG execution for multiple successful high-volume SoC products. Extensive experience with multi-million gate SoCs and hierarchical ATPG methodologies. Deep understanding of Scan, EDT/Compression, LBIST, MBIST, Boundary Scan, and DFT architecture. Strong experience with pattern validation, tester correlation, and post-silicon debug. Hands-on experience working with Product Engineering, Test Engineering, and ATE teams. Experience debugging silicon failures and supporting yield improvement initiatives. Strong scripting and automation skills using Python, Perl, Tcl, Shell, or similar languages. Demonstrated ability to lead technical initiatives across geographically distributed teams. PREFERRED TECHNICAL SKILLS ATPG tools such as Tessent, Modus, TestMAX, TetraMAX, or equivalent. Scan architecture, compression techniques, and diagnosis methodologies. STIL, WGL, tester pattern formats, and pattern conversion flows. Power-aware ATPG and test coverage optimization. Pattern validation on simulation, emulation, ATE, and platform environments. Silicon diagnosis, yield analysis, and failure characterization. DFT timing, physical-aware ATPG, and implementation debug. Strong knowledge of semiconductor manufacturing test flows and production test deployment. ACADEMIC CREDENTIALS: Bachelor’s or Master’s degree in related discipline preferred #LI-SR5 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Design Verification Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-16T06:02:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92115/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. THE ROLE: The Infinity Fabric transport layer verification team is looking for an experienced pre-silicon verification engineer to help verify our configurable switches and die-to-die interconnect. Infinity Fabric is part of every new AMD product being developed across Client, Server, Graphics, and Semi-Custom markets. Our growing team needs additional senior engineering experience to help us enhance our configurable testbench and to mentor junior engineers.   THE PERSON:  The preferred candidate will have proven experience verifying complex design blocks at the IP or SoC level using System Verilog/UVM or related technologies. He or she should be comfortable creating and executing on test plans in collaboration with design and verification colleagues in a metric-focused environment.   KEY RESPONSIBILITIES:  Develop and enhance System Verilog / UVM-based testbenches to verify new features for client, server, graphics, and semi-custom interconnects. Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture. Understand TestBench Architecture and develop expertise in TestBench Verification Components. Mentor junior engineers. PREFERRED EXPERIENCE:  Proficient in IP level ASIC verification Architected and developed complex verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar. Exposure to RTL design, software development, formal verification, or other related domains. Experience in UVM TestBench Development for complex designs preferred. Industry experience is preferred. ACADEMIC CREDENTIALS:  Bachelor’s or master’s degree in Electronics or Electrical or Computer engineering #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Staff Engineer, Layout Design (Power & Analog ICs)", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-16T04:50:44.120000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000149772959-senior-staff-engineer-layout-design-power-analog-ics-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking a Senior Staff Layout Design Engineer with deep expertise in analog and mixed-signal layout for power and analog IC products. This is a senior individual-contributor role requiring strong technical ownership, independent judgment, and the ability to lead layout execution for complex blocks and full-chip designs. \nThe successful candidate will translate circuit requirements into robust, manufacturable layouts for products such as PMICs, linear and switching regulators, gate drivers, battery-management ICs, and other power and analog devices. The role requires close collaboration with analog designers, CAD, process, package, reliability, and verification teams. \nYou will be expected to own challenging layout problems, establish best practices, improve methodology and automation, mentor engineers, and drive projects from floor planning through physical verification and tape-out readiness. \nResponsibilities\nLayout Architecture & Execution \nOwn floor planning and physical implementation for complex analog, power, and mixed-signal blocks, and contribute to full-chip layout planning. \nCollaborate with circuit designers to capture electrical, matching, isolation, current-density, thermal, reliability, and area requirements. \nApply advanced layout techniques for device matching, parasitic reduction, noise isolation, high-current routing, electromigration robustness, thermal behavior, and yield optimization. \nDrive routing, integration, and sign-off readiness for block-level and chip-level layouts. \nPhysical Verification & Sign-off \nOwn and review DRC, LVS, ERC, PEX, antenna, density, latch-up, and reliability verification as required by the process and product. \nAnalyse extracted parasitics with designers and support post-layout simulation closure. \nIdentify physical-design risks early and drive corrective actions with design, CAD, PDK, process, and package teams. \nEnsure layout databases, review records, and release documentation meet tape-out quality standards. \nMethodology, Automation & IP Reuse \nDevelop and deploy automation using SKILL, TCL, Python, Perl, or similar languages to improve quality and turnaround time. \nDrive layout methodology improvements, reusable templates, checklists, and portability of IP across products and process technologies. \nWork with corporate engineering and CAD teams to resolve tool, PDK, extraction, and process-flow issues. \nEvaluate new layout tools and techniques and lead practical adoption within the team. \nTechnical Leadership & Mentorship \nLead layout reviews and provide clear estimates, progress updates, risk assessments, and recovery plans. \nMentor junior and mid-level layout engineers and raise the technical standard of the broader team. \nInfluence project planning, task allocation, technical decisions, and hiring through demonstrated technical depth. \nOperate independently on ambiguous and complex assignments, escalating issues with clear options and recommendations. \n\nBachelor or Masters degree in Electrical Engineering, Electronics Engineering, or a related discipline. \n10+ years of relevant experience in analog, power, or mixed-signal IC layout and associated development flows. \nDemonstrated ownership of complex block-level layout and meaningful contribution to full-chip integration and tape-out. \nDeep understanding of matching, parasitic control, noise isolation, guard rings, latch-up prevention, high-current routing, electromigration, IR drop, thermal effects, and reliability-aware layout. \nHands-on expertise with Cadence Virtuoso and physical verification tools such as Calibre, PVS, or equivalent. Experience with extraction and reliability tools is expected. \nExperience working with deep-submicron CMOS and preferably BCD or high-voltage process technologies. \nAbility to automate layout or verification tasks using SKILL, TCL, Python, Perl, or similar scripting languages. \nProven ability to lead technical reviews, mentor engineers, and drive layout methodology improvements. \nStrong cross-functional communication skills in a multisite and multicultural environment. \nResults-oriented, self-driven, and able to deliver high-quality work under tight schedules with limited supervision. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Staff Engineer, Design Verification (Power & Analog ICs)", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-16T04:33:08.070000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000149771959-senior-staff-engineer-design-verification-power-analog-ics-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking a Senior Staff Design Verification Engineer to lead verification of the digital content embedded within power, analog, and mixed-signal IC products. This is a senior individual-contributor role requiring ownership of verification architecture, methodology, execution, and sign-off at block and full-chip level. \nThe successful candidate will build scalable verification environments from specifications, develop verification plans and coverage strategies, and verify control, protection, diagnostics, communication, trimming, test, and safety-related digital functions that interact closely with analog circuitry. \nYou will be expected to work autonomously, resolve ambiguous specification issues, establish verification flows from scratch where required, mentor engineers, and provide clear evidence that the design meets functional and product requirements before tape-out. \nResponsibilities  \nVerification Strategy & Ownership \nOwn block-level and full-chip digital verification strategy for power, analog, and mixed-signal IC products. \nDevelop verification plans from product and design specifications, including feature extraction, test intent, coverage goals, assumptions, and sign-off criteria. \nDecompose complex functions into reusable verification components and scalable environments. \nIdentify specification gaps and drive closure with architecture, analog design, digital design, applications, and test teams. \nEnvironment Development & Execution \nDesign and develop SystemVerilog/UVM-based testbenches, agents, scoreboards, reference models, assertions, sequences, and coverage models. \nSet up verification flows from scratch where needed and own regression execution, triage, debug, and closure. \nApply simulation, assertion-based verification, formal verification, and FPGA or emulation techniques where they provide practical value. \nVerify digital behavior across reset, clock, power-state, fault, trim, communication, test-mode, and analog-interaction scenarios. \nMixed-Signal, DFT & Post-layout Support \nCollaborate with analog and digital teams to define appropriate models and verify analog-digital interactions at the required abstraction level. \nSupport DFT verification, scan and ATPG-related checks, production-test vector development, and test-mode verification. \nSupport gate-level simulation, timing-aware verification, and post-layout verification where required. \nContribute to silicon bring-up, device evaluation, root-cause analysis, and documented workarounds for device errata. \nTechnical Leadership & Methodology \nDrive reusable verification methodology, automation, metrics, documentation, and review standards across projects. \nMentor and train verification engineers through reviews, debug support, and technical guidance. \nProvide concise status, coverage, risk, and sign-off assessments to project and technical leadership. \nInfluence architecture and design choices by identifying verification complexity, observability gaps, and product risks early. \n\nBachelor or Masters degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline. \n10+ years of experience in digital verification, including substantial hands-on experience with SystemVerilog and UVM. \nProven ownership of block-level and full-chip verification environments and sign-off for complex semiconductor products. \nStrong knowledge of functional verification, assertion-based verification, formal verification, regression frameworks, coverage closure, and debug methodologies. \nExperience verifying digital logic embedded in PMICs, power-management, automotive, audio, or other mixed-signal integrated circuits. \nGood understanding of RTL, microarchitecture, clocks, resets, low-power states, register interfaces, and common serial interfaces such as SPI, I2C, or UART. \nWorking knowledge of synthesis, STA, DFT, scan insertion, ATPG, and gate-level verification to collaborate effectively across the development flow. \nExperience with scripting or automation using Python, TCL, Perl, shell, or similar languages. \nProven ability to mentor engineers, establish verification methodology, and lead technical reviews without requiring formal people-management authority. \nSelf-driven, results-oriented, and able to deliver under tight schedules in a multisite and multicultural environment. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Engineer - DFT", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-16T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446717553950", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nJob Description\nMinimum of 3+ years experience in the area of ASIC/DFT\n-In depth knowledge of DFT concepts\n-In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis\n-Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations\n-Expertise in scripting languages such as perl, shell, etc.\n-Experience in simulating test vectors\n-Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (Tessent, TK, TetraMax)\n-Working experience in Genus, Synopsys TetraMax/DFTMax and Cadence Encounter Test is a plus\n-Ability to work in an international team, dynamic environment\n-Ability to learn and adapt to new tools and methodologies.\n-Ability to do multi-tasking & work on several high priority designs in parallel.\n-Excellent problem solving skills\n-Excellent communication and team work skills and good English is require\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Wireless R&D IP Verification Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-16T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718771669", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nAdditional Job Description\n\nLocation: Bangalore\nKey Responsibilities\nContribute to flagship Wireless IP development covering WAN, WLAN, GNSS, and Bluetooth technologies.\n\nOwn end-to-end IP-level verification, including:\nDesign analysis and verification planning.\n\nDeveloping test benches and writing test cases using SystemVerilog/UVM.\n\nWriting assertions, running simulations, and achieving coverage goals.\n\nExplore and implement advanced DV methodologies (formal, simulation) to improve efficiency and quality.\n\nDebug RTL and testbench issues using industry-standard tools.\n\nCollaborate with design, architecture, and cross-functional teams to meet project milestones.\n\nMaintain and enhance verification environments for scalability and reuse.\n\nSkills & Experience\nStrong expertise in SystemVerilog/UVM and coverage-driven verification methodologies.\n\nProven experience building and maintaining medium-to-complex SV/UVM environments.\n\nProficiency in writing efficient constraint-random tests and achieving coverage closure.\n\nStrong debugging skills using tools like Verdi or similar.\n\nExposure to wireless IPs (Wi-Fi, Modem PHY, DSP blocks) is a plus.\n\nFamiliarity with formal/static verification techniques.\n\nPower-aware verification and Gate-Level Simulation (GLS) experience is highly desirable.\n\nScripting skills (Python, Perl) for automation.\n\nQualifications\nEducation: Bachelor’s or Master’s or PhD in Electrical/Electronics/Computer Science from a reputed institution.\n\nExperience:  2- 12 years\n\nSoft Skills\nGood communication and interpersonal skills.\n\nFlexibility to work with global teams.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "DDR Design Verification Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-16T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720421102", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\nMinimum Qualifications:\n• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\nOR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\nOR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. We are looking to hire a strong DV engineer to work on verification of DDR Subsystem in the Infra IP team\nCreate DV infrastructure for verification\nIntegrate VIP's\nCreate and execute test plans, debug failures, write assertions, close code and functional coverage\nEnsure high quality verification\nWorking with all stakeholders to ensure program success\nMinimum Qualifications\nBachelor's degree in Engineering, Electronics, Information Systems, Computer Science, or related field.\n5+ years Hardware Engineering experience or related work experience.\nPreferred Qualifications\nFollowing skill set is required:\nStrong Debug, UVM, System Verilog\nUnderstanding Specs and Standards and developing relevant test plans\nMonitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved\nCandidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening\nPreferred Qualifications 5+ Year of industry experiences in the following areas: -\nThorough understanding of Digital design concepts\nThorough understanding dv methodologies and tools\nGood understanding of LPDDR4/LPDDR5 protocols\nUnderstanding of Bus protocols like AHB/AXI/ACE/ACE-Lite\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-16T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720351013", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    3+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n\nPrincipal Duties and Responsibilities:\n•    Applies Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Assists in the assessment of complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Tech Staff, Signal Integrity Engineer", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-09-16", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Tech-Staff--Signal-Integrity-Engineer_R2899-26-1", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nThe Mixed Signal Development Group is responsible for delivering analog and Mixed-Signal IP to divisions within Microchip. We work with leading edge CMOS processes to produce analog integrated circuits for wireline applications.  From T1/E1 to 224Gb/s SERDES, we enable technology that allows Microchip’s products to interface to the outside world.\n\nAs a member of the Mixed-Signal Development Group, the candidate will be supervised by a team leader/manager and be engaged in the package designs of highly complex and cutting-edge data center and optical communication processors.\n\nResponsibilities:\nOversee all aspects of Signal and Power integrity for device package designs.\nCollaborate with PCB, Mixed Signal, Product development and package designers to understand SI requirements for devices and package designs.\nWork with package designers to create packaging that meets electrical design specifications.\nHelp develop and evolve SI flows and processes\nSupport internal and external customers with signal integrity simulations of complex channels and power systems\nProduce signal integrity models for usage by internal and external customers.\nAnalysis and design of PCB and Package power systems\nModel future, yet to be designed, systems for the purposes of feasibility\nReview PCB and Package designs\n\nRequirements/Qualifications:\n\nBachelor degree in Electronics Engineering minimum.\n12 years or more experience in signal integrity design or equivalent\nExperience and knowledge of field solvers, such as HFSS, CST MWS, SIWave.\nExperience and knowledge of circuit simulators like ADS, Spectre, Hspice.\nSolid understanding of electromagnetic and transmission line theory, general I/O design, signal integrity, differential and single ended interface technology\nExperienced and knowledgeable of Printed Circuit Board (PCB) layout or electrical package design techniques\nFamiliarity and fundamental understanding of lab measurement equipment.  Oscilloscopes, TDR, Vector Network Analyzer, etc.\nUnderstanding of IBIS and IBIS-AMI\nExperience with MATLAB is an asset.\nScripting languages such as PERL, Python, and SKILL are an asset\nInnovative and creative thinker\nExperience with Cadence Design Environment an asset\nStrong written and oral communication skills\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "GPU Design Verification Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-16", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/GPU-Design-Verification-Engineer_JR0287113", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nPerforms functional verification of graphics logic components, including 3D graphics, media, and display, to ensure design will meet specification requirements.\nDefines and develops scalable and reusable IP verification plans, test benches, and architecture for verification environment to ensure coverage to confirm to graphics microarchitecture specifications.\nExecutes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs.\nReplicates, root causes, and debugs issues in the presilicon environment.\nFinds and implements corrective measures to resolve failing tests. Collaborates with GPU architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals.\nDocuments test plans and drives technical reviews of plans and proofs with design and architecture teams.\nMaintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification.\n\nQualifications:\nBachelor / Masters degree in Electronics or Computer Engineering with 6+ years experience in silicon design development.\nWell versed with Verilog / System Verilog / UVM.\nExperience in Pre-silicon verification, Testplan, testbench, Coverage/Assertion writing and closure.\nExposure to CPU or GPU Architecture (Computer Architecture Knowledge)Debug Experience with industry standard frontend design and verification flows, tools and methodology Programming / scripting languages like Python, Perl, or Shell scripting automation methods.\nGood verbal/written communication skills.\nEffective team player with continuous learning mindset.\nBe willing to balance multiple tasks. Prior experience in IP development teams would be an added advantage.\nExperience in IP coverage and functional verification.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Analog Circuit Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-16", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Analog-Circuit-Design-Engineer_JR0287107", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nIntel is looking for an experienced Analog Designer to join the IO Design Team in Bengaluru. In this role, you will be responsible for leading the design and development of advanced analog and mixed-signal circuits that enable high-speed chip-to-chip, package-to-package, and system-level connectivity for Intel's next-generation products.\nThe ideal candidate will have a strong background in transistor-level circuit design, high-speed IO architectures, and silicon debug. This position requires technical leadership, cross-functional collaboration, and ownership of critical IP blocks from concept through silicon validation.\nKey Responsibilities-\n• Lead the design, analysis, and optimization of analog and mixed-signal circuits for high-speed IO interfaces.\n• Develop and drive architecture and circuit implementation for:\n• High-speed TX and RX circuits\n• Serializer/Deserializer (SerDes) building blocks\n• PLLs, DLLs, CDRs, and clocking circuits\n• Equalization and signal conditioning circuits\n• Bandgap references, bias generation, and LDOs\n• ESD protection and IO pad circuitry\n• Perform detailed transistor-level design, simulation, and verification across multiple PVT corners.\n• Drive design closure for performance metrics including bandwidth, jitter, noise, power, area, yield, and reliability.\n• Collaborate closely with physical design teams on layout reviews and post-lay out optimization.\n• Support silicon bring-up, characterization, root-cause analysis, and correlation between simulation and silicon measurements.\n• Work with architecture, digital design, signal integrity, package, product engineering, and validation teams to ensure successful product execution.\n• Mentor junior engineers and contribute to team-wide design methodologies and best practices.\n• Drive technical reviews and provide leadership in solving complex design challenges.\n\nQualifications:\nBachelor's or master's degree in electrical engineering, Electronics Engineering, VLSI, Microelectronics, or a related discipline.\n• 5 to 9 years of industry experience in analog/mixed-signal IC design.\n• Strong expertise in CMOS analog circuit design fundamentals.\n• Proven experience designing high-speed analog circuits in advanced technology nodes.\n• Hands-on experience with one or more of the following: SerDes architectures, High-speed IO interfaces, PLL/DLL/CDR circuits, TX/RX analog front-end circuits, Clock distribution networks, Reference and bias circuits, LDOs and power management circuits.\n• Deep understanding of circuit noise, mismatch, jitter, stability, and reliability considerations.\n• Strong experience with Cadence Virtuoso, Spectre, and industry-standard analog verification flows.\n• Expertise in: Corner analysis, Monte Carlo simulations, Statistical design methodologies, post-layout verification and extraction analysis, Strong debugging and analytical problem-solving skills.\n• Experience with industry-standard high-speed interfaces such as: PCI Express (PCIe), DDR Memory Interfaces, USB, Ethernet, MIPI, DP, eDP, HDMI, UCIe.\n• Experience in advanced process technologies such as FinFET and Gate-All- Around (GAA) nodes.\n• Knowledge of signal integrity, channel modelling, and equalization techniques.\n• Experience in silicon validation and lab characterization.\n• Familiarity with reliability signoff, ESD verification, and EM/IR analysis.\n• Scripting experience using Python, Perl, TCL, or SKILL for design automation and productivity enhancement.\n\nKey Competencies\n• Technical leadership in analog and mixed-signal design.\n• Strong communication and stakeholder management skills.\n• Ability to work effectively in global, cross-functional environments.\n• Structured problem-solving and decision-making capabilities.\n• Passion for innovation and continuous improvement.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Lead Product Engineer", "company": "Cadence", "location": "BANGALORE 05", "date_posted": "2026-09-16", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE-05/Lead-Product-Engineer_R55309", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob responsibilities:\n\nPerform Product Engineering work for Genus Synthesis Solution (Genus), a logic synthesis software used for synthesizing a design described in a high-level language into logic gates, to achieve best-in-class Power, Performance & Area (PPA) for latest digital ASICs\n\nUnderstand the internal flow within the Genus for newly developed features and verify the correctness and perform experiments to determine an optimal solution\n\nSolve new and challenging problems in physical aware synthesis space with the goal to bridge the gap between logic synthesis and place and route\n\nSupport the field engineers in Cadence Design Systems, Inc. and its customers in using Genus. In addition, interface between R&D and customer as the first line of support for the R&D and the customers\n\nProvide support to verify the interoperability of Genus with other digital logic software tools within Cadence Design Systems, Inc. to provide seamless flows\n\nUnderstand the future requirements of the software by interfacing with the internal and external customers of Genus and document the Product Requirement Specifications (PRS) for newly developed features using the standard documentation software\n\nPreferred Qualifications:\n\nExperience in design and EDA with an emphasis on Cadence tools of Synthesis, Physical Design & timing closure at 20nm or below nodes\n\nPrior Designer, Product Engineering or Application Engineering experience in digital implementation, especially synthesis\n\nUnderstand industry challenges in digital implementation & sign off domain with exposure to 28nm & below foundry process nodes\n\nIndustry experience with EDA tools in the IC digital implementation flow, preferably on Genus and Innovus\n\nExperience in Logic Design and Synthesis, Formal Verification, Low Power design, Physical Design and Timing Closure for block level and top level designs\n\nAutomation skills using Perl, Tcl and shell scripting essential\n\nKnowledge of HDL – Verilog or System Verilog is preferred\n\nMust have logic design and timing closure skills\n\nStrong analysis skills required to debug complex timing closure, logical and physical design problems. Ability to perform root-cause analysis to suggest solutions to customers and provide feedback to R&D\n\nQualifications\nBE/BTech/ME/MS/MTech or equivalent\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Lead Product Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-09-16", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Product-Engineer_R55308", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob responsibilities:\n\nPerform Product Engineering work for Genus Synthesis Solution (Genus), a logic synthesis software used for synthesizing a design described in a high-level language into logic gates, to achieve best-in-class Power, Performance & Area (PPA) for latest digital ASICs\n\nUnderstand the internal flow within the Genus for newly developed features and verify the correctness and perform experiments to determine an optimal solution\n\nSolve new and challenging problems in physical aware synthesis space with the goal to bridge the gap between logic synthesis and place and route\n\nSupport the field engineers in Cadence Design Systems, Inc. and its customers in using Genus. In addition, interface between R&D and customer as the first line of support for the R&D and the customers\n\nProvide support to verify the interoperability of Genus with other digital logic software tools within Cadence Design Systems, Inc. to provide seamless flows\n\nUnderstand the future requirements of the software by interfacing with the internal and external customers of Genus and document the Product Requirement Specifications (PRS) for newly developed features using the standard documentation software\n\nPreferred Qualifications:\n\nExperience in design and EDA with an emphasis on Cadence tools of Synthesis, Physical Design & timing closure at 20nm or below nodes\n\nPrior Designer, Product Engineering or Application Engineering experience in digital implementation, especially synthesis\n\nUnderstand industry challenges in digital implementation & sign off domain with exposure to 28nm & below foundry process nodes\n\nIndustry experience with EDA tools in the IC digital implementation flow, preferably on Genus and Innovus\n\nExperience in Logic Design and Synthesis, Formal Verification, Low Power design, Physical Design and Timing Closure for block level and top level designs\n\nAutomation skills using Perl, Tcl and shell scripting essential\n\nKnowledge of HDL – Verilog or System Verilog is preferred\n\nMust have logic design and timing closure skills\n\nStrong analysis skills required to debug complex timing closure, logical and physical design problems. Ability to perform root-cause analysis to suggest solutions to customers and provide feedback to R&D\n\nQualifications\nBE/BTech/ME/MS/MTech or equivalent\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Lead Product Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-09-16", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Product-Engineer_R56123-1", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nPosition: Lead Product Engineer\nGrade: T3\nExperience: 4-7 Yrs\nLocation: Noida\nPosition Description:\nThis Job involves product engineer role for Synthesis flows including LEC and CLP.\n- Needs to work on synthesis engagement – address issue related to synthesis, LEC and CLP .\n- Should work as individual contributor and be a team player and need to co-ordinate with cross geographic teams to address the issues .\nPosition Requirements:\nEducation qualification requirement :\nB.E/B.Tech/M.Tech in Electrical, Electronics or Computer Science Engineer from reputed institute with good academic credential.\nExperience requirement :\n- Good understanding of HDLs (Verilog, SystemVerilog and/ or VHDL) is MUST\n-  RTL design and synthesis concepts is required.\n- Understanding of low-power concepts and leakage and dynamic power optimization concepts \n- Experience in Synthesis , LEC , CLP and PnR(not mandatory)\n-  Strong analytical and problem solving skills required\n- Experience in process automation with PERL or Tcl scripting is required.\n- He/ she should have a good working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design problems using these tools\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Staff Engineer, Signal and Power Integrity", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-16", "url": "https://careers.synopsys.com/job/bengaluru/staff-engineer-signal-and-power-integrity/44408/100721402208", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\n \nYou Are:\nYou are a passionate engineer with a solid foundation in electrical and electronic engineering, specializing in electromagnetics and high-frequency domains. With 4–7 years of industry experience, you thrive in customer-facing roles and enjoy solving real-world engineering problems. Your deep technical expertise in simulation tools, especially Ansys HFSS, SIwave, or Q3D Extractor, is matched by your ability to communicate complex concepts in an accessible way. You excel in environments that require innovative thinking, logical problem-solving, and a collaborative approach. Your strong organizational and time management skills enable you to efficiently manage multiple projects and deadlines, maintaining a sense of urgency and professionalism. You are energized by opportunities to learn and grow, both technically and professionally, and you seek to stay ahead of industry trends. As someone who values teamwork and cross-functional collaboration, you are comfortable interacting with diverse stakeholders, from customers to product development teams. You are driven by a desire to make a tangible impact, whether through technical pre-sales support, consulting, or training. Your customer service aptitude ensures you always keep the client’s needs at the forefront, and your business acumen enables you to contribute to account management and strategic growth. Fluent in English, you are ready to travel as needed and embrace challenges that stretch your abilities.\n \nWhat You’ll Be Doing:\nLead and assist in coordinating technical activities throughout the sales opportunity lifecycle, including technical discovery, product presentations, demonstrations, and evaluations.\nProvide best-in-class solutions involving PCB/Package/Advance Packaging/system interactions for signal and power integrity flow collaborating across regions and functions.\nParticipate in external and internal events to enhance SI/PI simulation solutions and contribute to professional growth and marketing efforts.\nAct as a product expert for Ansys products, engaging with customers to understand their design needs and workflows, highlighting Ansys’ value proposition.\nWork closely with product development teams to translate customer requirements into innovative product features and test new releases on industrial problems.\nDeliver consulting services and conduct introductory or intermediate training classes to empower customers and colleagues.\n \nThe Impact You Will Have:\nDrive customer success by integrating advanced simulation tools into their engineering workflows, enabling efficient and accurate design outcomes.\nEnhance Synopsys’ reputation for technical excellence and customer-centric innovation through tailored solution delivery.\nAccelerate the adoption of high-frequency simulation technologies, supporting the development of next-generation products in automotive, communications, and IoT industries.\nFoster lasting customer relationships by providing exceptional technical support and consulting, ensuring satisfaction and loyalty.\nInfluence product development by capturing and translating customer feedback into actionable improvements and new features.\nContribute to industry advancements by sharing expertise at events, expanding Synopsys’ thought leadership and market presence.\n \nWhat You’ll Need:\nMS/PhD in Electrical/Electronic Engineering or equivalent, with specialization in electromagnetics.\n4–7 years of experience in the high-frequency domain, using simulation tools for real-world applications.\nExpertise with Ansys HFSS, SIwave, Q3D Extractor, or comparable industry simulation software.\nFamilier with SI, PI, RF and Microwave concepts. Basic-intermediate level of understanding of signal and power integrity. \nAbility to research, debug, and resolve software-related issues efficiently.\n \nAdded Advantage\nExperience building automation workflows for RF/Signal/Power Integrity/EMC simulation flows.\nKnowledge of commercial packages such as ADS, MATLAB, Python, and CST.\nMeasurement & Lab Skills, Analysis and Problem-Solving skills, Hardware / System Knowledge.\n \nWho You Are:\nLogical problem-solver with strong interpersonal and communication skills.\nHighly organized and adept at time management, possessing a sense of urgency.\nProfessional, business-oriented, and driven to succeed in fast-paced environments.\nCustomer-focused and committed to delivering outstanding service and support.\nCollaborative team player who thrives in multi-disciplinary, cross-functional settings.\nAdaptable, eager to learn, and ready to travel up to 25% of the time.\n \nThe Team You’ll Be A Part Of:\nYou will join the Electronics High Frequency team within the Ansys Customer Excellence group. This team is comprised of experts in RF, signal integrity, and simulation technologies, working collaboratively across disciplines and regions to deliver innovative solutions. The team is dedicated to advancing engineering capabilities, supporting customer success, and driving business growth through technical leadership and continuous learning.\n \nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "ASIC Verification- Senior Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-16", "url": "https://careers.synopsys.com/job/bengaluru/asic-verification-senior-staff-engineer/44408/100721402128", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Title:\n* ASIC Verification- Senior Staff Engineer\n \nWe Are:\n \n At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\n \nYou Are:\n \n You are an accomplished verification engineer with a passion for excellence and a track record of delivering robust, high-quality IP solutions. You thrive in a fast-paced, dynamic environment and are excited by the opportunity to work on next-generation connectivity protocols that power commercial, enterprise, and automotive applications. With a solid foundation in Electrical/Electronics Engineering (BSEE with 8+ years or MSEE with 6+ years of relevant experience), you bring deep expertise in System Verilog and industry-standard verification methodologies such as UVM/OVM/VMM. Your hands-on experience developing HVL-based test environments and extracting meaningful verification metrics sets you apart as a technical leader.\n \n You are a collaborative team player who values knowledge sharing and actively contributes to a culture of continuous improvement. Your familiarity with protocols like MIPI-I3C, UFS, AMBA, Ethernet, DDR, PCIe, and USB allows you to quickly ramp up on new projects and deliver results. You bring a strong analytical mindset, exceptional debugging skills, and a drive to meet and exceed quality metrics. Experienced with scripting languages like Perl, TCL, and Python, you automate processes for efficiency and scalability. Your strong communication skills, initiative, and global perspective enable you to work effectively with cross-functional and multi-site teams. Above all, you are a lifelong learner who embraces challenges, adapts to new technologies, and is committed to shaping the future of silicon design.\n \nWhat You’ll Be Doing:\n * Specify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies.\n* Develop and execute comprehensive test plans, ensuring coverage of unit-level and system-level requirements.\n * Design, code, and debug testbenches, test cases, and functional coverage models to validate complex IP functionalities.\n* Perform functional coverage analysis and manage regression testing to achieve and maintain required quality metrics.\n* Collaborate closely with RTL designers and global verification teams to resolve issues and drive verification closure.\n* Leverage scripting (Perl, TCL, Python) to automate verification flows, streamline processes, and enhance productivity.\n * Contribute to the development and refinement of verification methodologies, including VIP development and formal verification approaches.\n \nThe Impact You Will Have:\n* Ensure the delivery of high-quality, robust IP cores that power critical applications in commercial, enterprise, and automotive markets.\n * Drive innovation in verification methodologies, setting new standards for efficiency and coverage.\n* Enhance time-to-market by identifying and resolving design and verification issues early in the development cycle.\n* Strengthen Synopsys’ reputation as a leader in silicon IP and verification through technical excellence and customer focus.\n* Mentor and support junior engineers, fostering a culture of learning and continuous improvement.\n * Contribute to the success of global, multi-site R&D teams by providing expertise and driving cross-functional collaboration.\n \nWhat You’ll Need:\n* BSEE with 8 years or MSEE with 6+ years of relevant experience in ASIC or IP verification.\n* Expertise in developing HVL (System Verilog)-based verification environments and testbenches.\n * Strong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools.\n* Proficiency in verification methodologies such as UVM, OVM, or VMM; exposure to formal verification is highly desirable.\n * Solid understanding of protocols such as MIPI-I3C/UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB.\n* Familiarity with scripting languages (Perl, TCL, Python) and HDLs (Verilog); experience with VIP development is a plus.\n * Demonstrated ability to work with functional coverage-driven methodologies and quality metric goals.\n \nWho You Are:\n * Analytical thinker with strong problem-solving and debugging skills.\n* Excellent verbal and written communication abilities.\n * Team player who thrives in collaborative, multi-site environments.\n * Proactive, self-motivated, and able to take initiative on challenging projects.\n * Detail-oriented, quality-focused, and driven by a desire to excel.\n* Adaptable and eager to continuously learn and apply new technologies.\n \nThe Team You’ll Be A Part Of:\n \n You will join the Solutions Group’s DesignWare IP Verification R&D team, a highly skilled and diverse group of engineers dedicated to delivering world-class IP cores for next-generation connectivity. The team operates in a collaborative, multi-site environment, leveraging global expertise to solve complex verification challenges. Together, you will drive innovation, share knowledge, and uphold Synopsys’ reputation for technical leadership and excellence.\n \nRewards and Benefits:\n \nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process....Less", "jd_status": "stored"}, {"title": "Sr. Principal Engineer, Emulation & IP Verification", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-16", "url": "https://careers.synopsys.com/job/bengaluru/sr-principal-engineer-emulation-and-ip-verification/44408/100703928064", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nYou have spent 15 years learning that emulation is not just about running tests faster, it is about finding the bugs that matter before they cost millions in silicon respins. The difference between a verification plan that looks complete and one that actually catches corner cases is something you can spot in the first ten minutes of a review. You know PCIe, DDR, and Ethernet at the protocol level, not just the spec level, because you have debugged enough real failures to understand where theory and implementation diverge.\nWorking with Zebu is second nature to you. You have built emulation environments that bridge the gap between what the platform can do and what your design team actually needs. When someone says 'the emulation IP does not support that feature,' you do not stop there. You figure out the workaround, propose the enhancement, or find another path entirely.\nYou operate comfortably across geographies and functions. Design teams, verification teams, IP teams, they all speak slightly different languages, and you translate between them without losing the technical thread. Matrixed organizations do not slow you down because you know how to build consensus without waiting for perfect alignment. At Synopsys, you will define how we validate the next generation of high-speed interfaces, and the IP you help verify will ship in products that power everything from data centers to autonomous systems.\n\nWhat You'll Be Doing\nClose the gap between Zebu emulation IP capabilities and what Design IP teams need to verify PCIe, DDR, and Ethernet controllers and PHYs across functional and performance domains\nDefine technical requirements for emulation IP, working directly with IP development teams to ensure correct implementation, deployment, and integration into verification flows\nTrack and report emulation IP quality metrics, identifying trends, gaps, and improvement opportunities that directly impact product schedules and silicon success\nStay ahead of evolving PCIe, DDR, and Ethernet standards, translating specification updates, ECNs, and errata into actionable requirements for both emulation and design teams\nReview and validate test plans for emulation IP and design IP, ensuring coverage is complete, traceable, and aligned with real-world use cases and customer requirements\nDrive cross-functional alignment on verification methodology, standardizing workflows and best practices across global teams to improve efficiency and reduce rework\nMentor engineers on emulation strategy, IP verification techniques, and how to think critically about coverage and quality in pre-silicon environments\n\nThe Impact You Will Have\nAccelerate time to market for high-speed interface IP by catching critical bugs in emulation before they reach silicon\nInfluence the roadmap and feature set of Synopsys emulation IP, shaping tools that thousands of engineers across the company depend on\nElevate verification quality across multiple product lines by defining and evangelizing best practices that become the standard\nReduce costly silicon respins by ensuring emulation environments accurately model real-world system behavior and corner cases\nBuild bridges between geographically distributed teams, turning fragmented verification efforts into cohesive, repeatable strategies\nPosition Synopsys as the industry leader in pre-silicon validation by driving adoption of cutting-edge emulation techniques\nEnable the next generation of AI, automotive, and data center products by ensuring the IP that powers them is verified to the highest standard\n\nWhat You'll Need\n15+ years of hands-on experience in emulation, IP verification, or ASIC digital design\nDeep expertise in PCIe and DDR protocols, including verification strategies, corner cases, and standards compliance\nExtensive experience with Zebu or similar emulation platforms, particularly for IP-level verification and system-level integration\nProven track record leading or contributing to IP product development with a focus on emulation-based verification\nStrong ability to work across global, matrixed teams and drive alignment between emulation IP and design IP organizations\nExcellent communication skills, you can explain a complex tradeoff to a design lead in two sentences without losing the nuance\nExperience interpreting and applying industry standards updates, ECNs, and errata in real verification contexts is a strong plus\n\nWho You Are\nYou can walk into a test plan review, spot the missing corner case that everyone else missed, and explain why it matters in two sentences\nWhen something does not work in emulation, you do not wait for someone else to fix it. You dig in, reproduce it, and come back with a proposal\nYou are comfortable saying 'this verification strategy will not catch that class of bugs' in a room full of senior engineers, and you can back it up with data\nAmbiguity does not slow you down. You ask the right questions, make reasonable assumptions, document them, and keep moving\nYou have mentored engineers before and you know the difference between giving someone the answer and helping them learn how to find it\nYou treat verification like a product. You think about the user experience, the failure modes, and what happens six months from now when someone else has to maintain what you built\n\nThe Team You'll Be Part Of\nYou will join a dynamic, high-performing engineering team focused on IP development, emulation, and verification at the forefront of semiconductor innovation. Our team is collaborative, cross-functional, and globally distributed, working together to solve complex challenges and deliver industry-leading solutions. You will have the opportunity to collaborate with experts across multiple domains, drive impactful initiatives, and shape the future of digital design and verification at Synopsys.\n\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Implementation Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-16", "url": "https://careers.arm.com/job/bengaluru/implementation-engineer/33099/100703565216", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview: \n\nThe implementation team in Arm's Solution Engineering drives the standards and methodology behind producing best in class Arm cores and systems on silicon. The group works on ensuring that our IPs can meet the requirements of the Arm partner base, on brand new deep sub-micron processes, whilst driving advanced implementation methodologies using the latest EDA tools. In addition, this group is responsible for specification, design and fabrication of Arm based SoCs used for demonstrating the capabilities of Arm intellectual property, resulting in the testing and analysis of real silicon. \n\nThis is an exciting role, employing the latest design techniques to meet demanding product specifications on the newest technology nodes. The role also involves interaction and working with customers, EDA vendors and other Arm engineering groups around the world. \n\nResponsibilities: \n\nSynthesis, Physical design and implementation of Arm cores, systems and SoCs \n\nAnalyze design timing, area and power to help improve the quality of Arm IP. \n\nDevelop and deploy new methodologies to improve implementation efficiency and results. \n\nSupport and develop detailed implementation analysis and data-mining methodologies. \n\nWork with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. \n\nRequired Skills and Experience : \n\nBachelors or Master’s degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields. \n\n2+ years of proven experience in ASIC system-on-chip implementation flow from RTL to GDS. \n\nExperience in Timing Constraints development, Synthesis, Timing Closure \n\nPossess a high level of dedicated, initiative and problem-solving skills. \n\nExperience of tape outs of multi-million gate designs on latest technologies \n\nAbility to develop and work with timing constraints for build and signoff \n\nThe ability to effectively work alone as well as in a team \n\n“Nice To Have” Skills and Experience : \n\nExperience with a wide range of programming, scripting & data presentation languages Eg. Tcl, Shell, Perl, Python. \n\nExperience with low power design techniques (power gating, voltage/frequency scaling). \n\nExperience with Verilog RTL design \n\nUnderstanding of DFT modes and their implications on Physical Design \n\n #LI-BB1\n\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Layout Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-16", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25017173", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n Texas Instruments is seeking a Layout Engineer. In this role, you will develop and prepare multi-dimensional layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering. Work may be completed through use of CAD or other computerized equipment. You may also check dimensions, write specifications, and verify completed drawings, artwork or digitized plots. Additional job functions may involve checking design layouts and detailed drawings, referring to offline layout leveling charts for details on duties. A bachelor's degree in engineering is typically required, and in the U.S. this job is restricted to specific job grades.\n\nQualifications\nMinimum requirements:\n\nMinimum education (ie bachelor's degree in electrical engineering)\n\nMinimum of 5 years of experience\n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Senior Lead Verification Engineer, Digital IP", "company": "NXP", "location": "Bangalore", "date_posted": "2026-09-16", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Senior-Lead-Verification-Engineer--Digital-IP_R-10066812", "is_hardware": true, "platform": "workday", "jd_text": "Role Summary:\nWe are part of MCU/MPU Engineering, a central design organization within NXP, developing products for multiple business lines in Automotive, Internet of Things (IoT), Networking, and Radio Frequency products, with expertise in hardware engineering, including architecture, IP, and full SoC Design. \n\nMME's Digital IP team produces design solutions covering the very wide range of SoCs required by the business lines. The team is challenged to produce industry-leading solutions covering very cost-sensitive, low-power devices to highly integrated, high-performance, multi-cohort devices compliant with the latest automotive and industrial safety and security standards.\nJob Responsibility:\nResponsible for the pre-silicon verification of IP modules or, IP subsystems\n\nResponsible for defining and writing IP verification plans based on requirements documents (industry standards, product requirements, IP architecture and IP implementation specifications)\n\nInterface to HW, FW, and SW design teams, as well as to architecture and system engineering teams, to understand functionality and application of the IP or subsystem.\n\nResponsible for executing verification plan according to the product specification and verification requirements defined by product architects.\n\nResponsible for architecting, developing, debugging and running UVM based verification environment for RTL simulation.\n\nDefine and develop test cases in an appropriate verification framework. Create stimulus and assertions, run simulation, debug test cases on the design models (RTL, power aware RTL, gate level, FPGA, Emulation platform), run regression, collect and analyze code/functional coverage.\n\nJob Qualification:\nDegree in Electrical Engineering or Computer Science, with 7+ years of experience on IP/Sub-System Verification\n\nProven experience in testbench design and development using UVM methodology for IP/Subsystem and SOC.\n\nAdvanced knowledge of Verilog, System Verilog, C/C++, Shell.\n\nHigh proficiency in Metric Driven Verification concepts, functional and code coverage.\n\nHigh proficiency in directed and constrained random methodologies.\n\nGood knowledge of formal verification methodologies and assertions.\n\nExperience with debugging of designs pre- and post-silicon, in simulation and on the bench.\n\nExcellent written and verbal communication skill. \n\nGood knowledge in scripting like Perl, TCL or Python is a plus\n\nMore information about NXP in India...\n\n#LI-7013", "jd_status": "stored"}, {"title": "Applications Engineering, Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-16", "url": "https://careers.synopsys.com/job/bengaluru/applications-engineering-staff-engineer/44408/100721402224", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years deep in the realities of chip design, where a power integrity issue at 3nm can cost months and millions, and you have learned that the gap between a tool that works in theory and one that closes timing on a real SoC is everything. You think in terms of deployment, not demos. You know what it takes to get an EDA solution from product spec to production use at a top semiconductor company, and you care about making that path shorter and cleaner every time.\nYou are comfortable sitting with a customer architect who is three weeks from tapeout, diagnosing a signal integrity failure, and walking out with a plan that actually works. You do not wait for perfect documentation. You dig into the design, ask the right questions, and move. You have worked across ASIC physical design, power or signal integrity closure, or custom circuit simulation, and you understand how those worlds connect when you are trying to ship silicon that actually functions.\nAt Synopsys, you will work with the Ansys EDA portfolio, deploy it at companies building the most advanced chips in the world, and help shape what the tools become next.\nWhat You'll Be Doing\nDeploy Synopsys Ansys EDA products at top semiconductor companies working on leading-edge SoCs and 3DICs at 7nm, 5nm, and 3nm nodes\nWork directly with global customers, IP providers, and foundries to understand design challenges around power integrity, signal integrity, reliability (EM, ESD, thermal), advanced timing, jitter, and packaging\nCollaborate with software developers, architects, and product specialists to translate customer challenges into EDA product specifications and drive product development\nUse the Ansys Seascape platform to solve big-data design challenges across chip, package, and system levels\nProvide expert technical guidance and consultation to customers globally, helping them close power, signal, and reliability issues on real designs\nDiagnose complex design failures, reproduce issues, and work with engineering teams to deliver solutions that hold up in production\nTravel occasionally to customer sites for deployment support, technical reviews, and design problem-solving\nThe Impact You Will Have\nEnable the world's leading semiconductor companies to tape out chips at 7nm, 5nm, and 3nm by solving power, signal, and reliability challenges they cannot close without your expertise\nShape the next generation of Synopsys Ansys EDA tools by feeding real customer pain points directly into product development\nReduce time to closure for customers facing critical design bottlenecks, turning weeks of debug into days with the right deployment and guidance\nBuild long-term technical relationships with architects and design teams at top-tier semiconductor companies, becoming their trusted resource for advanced node challenges\nDrive adoption of the Seascape platform across the industry, proving out its value on real, complex designs\nInfluence foundry and IP provider roadmaps by surfacing design trends and tool gaps you see across multiple customer engagements\nMentor application engineers and expand the team's collective expertise in power integrity, signal integrity, and reliability at scale\nWhat You'll Need\nBachelor's degree in Electrical Engineering, Electronics, Computer Engineering, or related field, and 5+ years of related experience, or Master's degree with 3+ years of experience\nHands-on experience in ASIC physical design, power integrity/signal integrity/reliability closure, or custom circuit design and simulation\nStrong problem-solving skills with the ability to diagnose and resolve complex technical issues in real customer design environments\nSolid programming skills in scripting languages like Python, Tcl, or Perl for automation and workflow development\nExcellent verbal and written communication skills, with the ability to explain technical tradeoffs clearly to customers and internal teams\nWillingness to travel occasionally to customer sites for deployment and technical support\nExperience with EDA tools for power analysis, signal integrity, or reliability verification is a strong plus\nWho You Are\nYou can walk into a customer meeting with incomplete information, ask three sharp questions, and leave with a clear picture of what is actually broken and what needs to happen next\nYou are comfortable context-switching between a product development discussion in the morning and a customer debug session in the afternoon without losing the thread of either\nYou push back when a product spec is too vague or a deployment plan does not account for how customers actually work, and you do it in a way that moves the conversation forward\nYou do not need to be the loudest person in the room, but when you speak, people listen because you have done the work and you know what you are talking about\nYou are organized enough to manage multiple customer engagements, product feedback loops, and internal projects at once without dropping details that matter\nYou genuinely enjoy learning new technology and figuring out how to make it work in messy, real-world conditions\nThe Team You'll Be Part Of\nYou will be part of the Applications Engineering team deploying Synopsys Ansys EDA products globally. The team works closely with software developers, architects, product specialists, and customers at top semiconductor companies to drive product development and deployment on leading-edge SoCs and 3DICs. Your recruiter will share more about the team structure, regional focus, and current customer engagements during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "SDC, Synthesis and STA Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-15T14:00:00+00:00", "url": "https://global-external-amd.icims.com/jobs/91697/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. SDC, Synthesis and STA Engineer   THE ROLE: The focus of this role is to plan and execute the front end implementation of IPs and its closure. This involves ownership of SDC development, SDC generation, verification, promotion/demotion and equivalence checking. The role might also epxand to (if needed) synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure. Co-ordinate with design team and PNR teams. Guide team members on technical issues.   KEY RESPONSIBILITIES:  Main responsibility is to own constratins, SDC developement for IPs, SS and SoCs. Including SDC generation, verification, promotion, demotion and equivalence using third party or self built tools. Additonal responsibilities for front end implementation of IPs might include synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure Prior experience with Lint, CDC and RTL & Netlist based static checks is a plus Collaborate with designer and PNR teams to achieve closure. Understand duration required, plan and execute as per schedule. Complete quality delivery for synthesis and timing closure. Debug and resolve technical issues   PREFERRED EXPERIENCE:  Existing SDC, constraints development with or without using fisthail, excellicon or TCM. Experienced in synthesis, LEC, CLP and timing closure Preferred top level or SOC level experience Have handled blocks with complex designs, high frequency clocks and complex clocking complete understanding of timing constraints, low power aspects and concepts of DFT Have debug experience to solve issues. Interst in AI, Scripting and automation   ACADEMIC CREDENTIALS:  Bachelors with 8 years of experience or Masters degree with 6 years of experience in Electrical Engineering #LI-AB1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior/Staff/Sr Staff Engineer, Product Definer (IC Architect)", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-15T11:22:36.665000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000149576039-senior-staff-sr-staff-engineer-product-definer-ic-architect-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking a talented and motivated person to join as a manager of system and application team to own and define next generation products and support customer for India for India business division with focus on power products. \nA successful candidate will have strong desire and ability to work in a technically challenging and entrepreneurial environment. To succeed, candidate will need to combine deep technical understanding of power management, Renesas products and customer systems. You will engage in product definition as well as customer support activities. Your ability to work across functional groups through formal communication and direct interaction is critical to success. The position requires significant technical experience in power management as well as understanding of firmware-enabled and embedded system (attach to SoC) products. The candidate will work closely with management, sales and engineers based in India while coordinating efforts with a global team. \nResponsibilities :\nIdentify market opportunities and collaborate with Marketing team, Business Division management, and Sales to exploit these opportunities \n\nSupport marketing/Sales/FAEs to facilitate the design-in of our products as well as providing technical assistance to address customer technical questions such as customer circuit design review, debug, troubleshooting and field return analysis. \n\nUse knowledge gained to support marketing business plan including TAM/ SAM / SOM) activities by providing analysis demonstrating technical merit of Renesas solutions vs competing solutions. \n\nProvide deep technical support and training to advance Renesas’s commercial success. Requires ability to translate complex ideas or implementations to a level suitable for less experienced audiences such as customers or field sales staff. \n\nWork with the broader marketing team and design team to develop customer collateral that raises the company's profile \n\nUnderstand market and customer requirements and define product requirements and improve product roadmaps \n\nDefine product family roadmap \n\n·Produce technically detailed Product Requirements and / or design specifications documents. \n\nWork with design engineering when conflicts arise between requirements, capabilities and business expectations. \n\nInterpret device level system use cases and requirements and translate to product specifications while ensuring specifications meet customer needs by working with customers and internal teams \n\nCompare of design trade-offs and IP choices to achieve competitive product specifications \n\nParticipate in FPGA based design prototyping to verify key features and functions will meet expectations. Work with design and other staff to find solutions when targets are not met. \n\nGuide staff in creation of Applications Validation Plans by using experience to ensure corner cases are covered \n\nPerform physical silicon device evaluation at board level based on defined evaluation plans, including understanding the silicon behavior and functionality in detail. \n\nDrive system modelling requirement \n\nSupport hiring and managing the necessary team as per business need over time \n\n \n\nComfort and ability to collaborate and be effective in an entrepreneurial (fast-paced and ambiguous) environment \n\nExcellent interpersonal, communication and presentation skills and comfort in presenting to a wide range of audiences. Capable to communicate issues in a concise and effective way. \n\nDesire and drive to interact with, as well as ability to build and maintain excellent relationships with internal and external stakeholders. \n\n Product ownership mentality \n\n5 to 14 years of experience in power management space, ideally including product definition, with semiconductor companies \n\nTravel will be required \n\nBachelor or Masters of Electronics Engineering or related discipline \n\nAbility to build a strong team and motivate individuals to work out of their comfort zone \n\nSelf-driven, strongly motivated individual capable to take full ownership of their activities, and to involve other functions in the company or management when needed to bring them to a successful outcome. \n\nUnderstanding of power management applications and products. \n\nTechnical proficiency: \nHands-on experience and ability in lab debugging, probing and characterizing circuit and silicon using a mixture of custom-made and standard equipment such as power supplies, e-load, digital oscilloscopes, spectrum analyzers, etc. \n\nBoard level analog and digital circuit design expertise and PCB schematic design \n\nSIMPLIS or similar ckt simulator \n\nUnderstanding of control loop theory and its application in power converters \n\nExperience using FEA tools for various thermal, electrical and magnetic investigations \n\nProgramming proficiency in C and Python \n\nPCB CAD tools for both schematic and layout. \n\nProficiency with a full complement of lab equipment including network analysers, oscilloscopes and waveform generators. Experience with automation of lab testing. \n\nData analysis using Excel or JMP \n\nUnderstanding of AECQ / IATF /ISO26262 (FuSa) (At least basic level) \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior/Staff/ Sr Staff Engineer, Digital Design", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-15T11:16:35.573000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000149574968-senior-staff-sr-staff-engineer-digital-design", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.\nWe are seeking a highly motivated and innovative Senior/Staff/Sr Staff IC Design Engineer (RTL Design) with strong experience in SoC development flows. In this role, you will play a pivotal part in the design and development of advanced integrated circuits that power Renesas MCU products. You will lead complex RTL design efforts, own key IP/subsystem deliverables, mentor junior engineers, and help evolve design methodologies and best practices.\nKey Responsibilities\nLead RTL design and development of complex IPs and subsystems within MCU SoCs, ensuring compliance with performance, power, and area (PPA) targets\nDrive micro-architecture definition and high-level digital design for assigned blocks\nSupport SoC integration, delivering high-quality subsystem views and documentation to Back-end and Design Verification teams\nOwn design quality checks, including lint, CDC, and RDC, and actively support functional verification of assigned blocks\nCollaborate closely with system architects, verification engineers, physical design teams, and software teams to define specifications and ensure seamless end-to-end integration\nProvide technical guidance and mentorship to junior engineers, raising overall team capability and design quality\nContribute to continuous improvement of RTL design methodologies, coding guidelines, and design processes\n\nRequired Qualifications\nBachelor’s degree in Electronics & Communication Engineering, Electrical Engineering, Computer Engineering, or related technical field\nMinimum of 4 to 8 years of hands-on experience in digital IC/ASIC design, with a strong track record of delivering high-quality silicon\nStrong expertise in RTL design using Verilog/VHDL\nSolid understanding of digital design principles, timing analysis, clocking, resets, and verification methodologies\nExperience using industry-standard EDA tools for synthesis, simulation, and static timing analysis\nStrong problem-solving skills with the ability to own blocks end-to-end\nPreferred Qualifications\nExperience owning complex IPs or subsystem designs in large SoCs\nStrong background in micro-architecture design and high-level digital design\nHands-on experience with RTL quality tools such as Spyglass (Lint, CDC, RDC)\nExperience with low-power design techniques and methodologies\nFamiliarity with SoC-level design and integration\nUnderstanding of synthesis flows and timing constraints\nScripting experience in Shell, Perl, Python or use of AI for design is a strong plus.\nWhy Renesas\nAt Renesas India, you will work on industry-leading MCU platforms, collaborate with global teams, and influence next-generation semiconductor products. This role offers deep technical ownership, growth into architectural leadership, and the opportunity to shape how we design and deliver high-quality silicon.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Staff Analog Mixed Signal Design", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-09-15T10:18:41+00:00", "url": "https://jobs.infineon.com/careers/job/563808971615690", "is_hardware": true, "platform": "eightfold", "jd_text": "Lead a variety of Analog and Mixed signal IC projects in GaN BL.\n\nYour Role\n\nKey responsibilities in your new role\n\nLead end-to-end development of analog and mixed-signal ICs, from architecture definition through silicon validation and production release.\nArchitect and design high-performance analog building blocks for Power Management IC (PMIC) applications.\nDrive key technical decisions, design reviews, risk assessments, and project execution activities.\nCollaborate closely with system architects, digital design teams, layout engineers, validation engineers, and product engineering groups.\nDefine and implement robust design methodologies, verification plans, and silicon debug strategies to ensure first-pass success.\nLead silicon characterization activities, root-cause analysis, and issue resolution during production ramp-up.\nInterface with customers, applications engineers, and stakeholders to translate system-level requirements into optimized IC solutions.\nMentor and provide technical guidance to junior and senior design engineers.\nFoster a culture of engineering excellence, innovation, accountability, and continuous improvement.\nLead multiple analog and mixed-signal IC development projects within the GaN Business Line.\n\nYour Profile\n\nQualifications and skills to help you succeed\n\nBachelor’s or master’s degree in electrical engineering, Electronics Engineering, Microelectronics, or a related field.\n8+ years of hands-on experience in Analog and Mixed-Signal IC Design.\nStrong analog design fundamentals and deep understanding of semiconductor device physics.\nProven experience in the design and development of:Voltage Regulators\nPower Management ICs (PMICs)\nGate Drivers\nCurrent Sensing Circuits\nProtection Circuits\n\nExperience leading complex IC development programs from concept to production.\nStrong problem-solving, debugging, and silicon bring-up skills.\nAbility to work effectively in cross-functional and geographically distributed teams.\n\nContact:\n\n    Malthesh.Katari@infineon.com\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\nThis means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.\nPlease let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.\nClick here for more information about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Senior Staff/Principal Engineer, Digital Design (Power & Analog ICs)", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-15T07:49:55.914000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000149524299-senior-staff-principal-engineer-digital-design-power-analog-ics-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking a Senior Staff Digital Design Engineer to architect and implement the digital content within power, analog, and mixed-signal IC products. This is a senior individual-contributor role requiring ownership from requirements and microarchitecture through RTL, synthesis, timing closure, DFT support, and silicon bring-up. \nThe successful candidate will design control, sequencing, protection, diagnostics, trimming, communication, test, and safety-related logic that works closely with analog circuitry. The emphasis is not on large processor SoCs. It is on high-quality digital design embedded inside power and analog ICs. \nYou will be expected to resolve ambiguous requirements, make sound area-power-performance trade-offs, develop reusable design practices, mentor engineers, and collaborate across analog design, verification, physical design, test, applications, and product teams. \nResponsibilities :\nDigital Architecture & RTL Design \nTranslate product and circuit requirements into robust digital microarchitecture and detailed block specifications. \n\nDesign optimized RTL for control, sequencing, protection, diagnostics, trimming, communication, test, and low-power functions within power and analog ICs. \n\nOwn block-level integration and contribute to chip-level digital architecture, interfaces, clocking, reset, power-state, and register-map decisions. \n\nMake and document trade-offs across functionality, area, power, testability, timing, reuse, and implementation risk. \n\nImplementation, Timing & DFT \nDevelop synthesizable Verilog/SystemVerilog RTL, synthesis scripts, timing constraints, and implementation collateral. \n\nOwn or guide synthesis, lint, CDC/RDC, low-power checks, static timing analysis, and handoff to physical design. \n\nSupport DFT architecture and implementation, including scan insertion, ATPG enablement, test modes, and production-test requirements. \n\nWork with place-and-route teams on timing closure, congestion, power, and post-layout issues. \n\nVerification & Silicon Support \nCollaborate with verification engineers on verification planning, assertions, coverage, debug, and specification closure. \n\nDevelop directed tests, reference checks, or test vectors where useful to accelerate design validation and production-test development. \n\nSupport gate-level and post-layout verification, silicon bring-up, device evaluation, failure analysis, and root-cause investigation. \n\nDevelop and document practical workarounds where device errata or silicon limitations require them. \n\nTechnical Leadership & Reuse \nDrive reusable RTL, design methodology, coding standards, review practices, and automation across projects. \n\nMentor junior and mid-level digital engineers and lead architecture, RTL, and implementation reviews. \n\nIdentify technical and schedule risks early and communicate clear options and recommendations to project leadership. \n\nCollaborate effectively with analog, applications, test, layout, CAD, and product teams across global locations. \n\nBachelor or Masters degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline. \n\n10+ years of relevant experience in digital design, RTL development, and implementation for semiconductor products. \n\nDeep hands-on experience in logic design, microarchitecture, Verilog/SystemVerilog RTL coding, synthesis, and static timing analysis. \n\nExperience designing digital control logic embedded in PMICs, power-management, automotive, audio, or other mixed-signal integrated circuits. \n\nStrong understanding of clocks, resets, low-power states, finite-state machines, register interfaces, fault handling, and hardware-software interaction. \n\nHands-on experience developing block-level and top-level timing constraints for STA and physical-design sign-off. \n\nWorking knowledge of DFT, scan insertion, ATPG, test modes, CDC/RDC analysis, lint, and gate-level verification. \n\nExperience with scripting and automation using TCL, Python, Perl, shell, or similar languages. \n\nProven ability to own complex design blocks, influence chip-level decisions, mentor engineers, and lead technical reviews. \n\nSelf-driven, results-oriented, and able to deliver high-quality designs under tight schedules in a multisite and multicultural environment. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "PE- CPU Software & Hardware Co-Design Engineer (ML Systems)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-15T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720477804", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Software Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Software Engineer, you will design, develop, create, modify, and validate embedded and cloud edge software, applications, and/or specialized utility programs that launch cutting-edge, world class products that meet and exceed customer needs. Qualcomm Software Engineers collaborate with systems, hardware, architecture, test engineers, and other teams to design system-level software solutions and obtain information on performance requirements and interfaces.\n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 8+ years of Software Engineering or related work experience.\n                                                                    OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 7+ years of Software Engineering or related work experience.\n                                                                    OR\nPhD in Engineering, Information Systems, Computer Science, or related field and 6+ years of Software Engineering or related work experience.\n\n•    4+ years of work experience with Programming Language such as C, C++, Java, Python, etc.\n\nDetailed JD:\n==========\n\nJob Description: CPU Software & Hardware Co-Design Engineer (ML Systems)\nLocation: Bangalore (or relevant)\nLevels: Engineer / Senior Engineer / Staff / Principal Engineer\n\nRole Overview\nWe are building a high-impact team at the intersection of CPU architecture, machine learning workloads, and system-level performance optimization. This role focuses on CPU software–hardware co-design for next-generation QMX architectures, including workload characterization, simulation, kernel optimization, and driving architectural insights for future CPU designs. The ideal candidate will work across the full stack—from ML models to low-level kernels to architectural feedback—enabling efficient execution of ML workloads on CPU platforms.\n\nKey Responsibilities\n1. ML Workload Identification & Characterization\nIdentify and prioritize critical ML use cases and models for CPU-centric execution (LLMs, vision, speech, recommender systems, etc.)\nAnalyze workload characteristics including:Compute intensity\nMemory bandwidth and cache behavior\nParallelism and dataflow patterns\n\n2. Simulation & Trace Generation\nGenerate detailed execution traces for ML workloads using QEMU or equivalent simulators\nDevelop tooling to:Capture instruction-level execution behavior\nExtract performance counters and bottlenecks\n\nEnable accurate modeling of workload behavior for architectural exploration\n\n3. Bottleneck Analysis & Performance Optimization\nIdentify system bottlenecks across:CPU pipelines\nMemory hierarchy\nInstruction utilization\n\nOptimize critical hotspots through:Kernel-level tuning\nAlgorithmic improvements\nData layout and memory optimizations\n\nDrive measurable improvements in workload performance\n\n4. Software–Hardware Co-Design\nCollaborate with CPU architecture and design teams to:Provide data-driven insights from real workloads\nIdentify inefficiencies and propose architectural enhancements\n\nInfluence next-generation CPU features in:Compute units\nVector/SIMD extensions (e.g., QMX)\nMemory subsystems\n\n5. ML Kernel & Library Development (QMX Focus)\nDesign and implement highly optimized ML kernels and libraries for QMX architecture\nDevelop kernels for:GEMM, convolution, attention, activation functions, etc.\n\nEnable integration with:Open-source ML frameworks (e.g., PyTorch, ONNX, XNNPACK, MLAS)\n\nApply advanced optimizations:SIMD/vectorization\nCache-aware execution\nParallel execution strategies\n\n6. Benchmarking & Performance Engineering\nOptimize CPU-centric ML benchmarks such as:Geekbench AI\nInternal benchmarking suites\n\nEstablish performance baselines and track improvements across hardware generations\nPerform competitive analysis and performance positioning\n\nRequired Qualifications\nStrong background in:Computer Architecture / Systems Programming\nMachine Learning fundamentals\n\nProficiency in:C/C++ (mandatory)\n\nExperience with:Performance profiling, benchmarking, and optimization\n\nPreferred Qualifications\nExperience with:QEMU or equivalent simulators\nML kernel development (GEMM, convolution, attention)\n\nKnowledge of:CPU architecture (pipelines, caching, SIMD/vector extensions such as NEON, SVE, QMX)\n\nFamiliarity with:ML frameworks and inference stacks\n\nExperience with low-level optimization:Intrinsics, assembly, memory and cache tuning\n\nWhy Join This Team\nWork on next-generation CPU architectures (QMX)\nDirectly influence hardware design through real workload insights\nSolve end-to-end ML performance challenges (model → kernel → silicon)\nCollaborate with top architecture, systems, and AI teams\nHigh-impact role with visibility across product and research roadmaps\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Principal Engineer - Analog Design", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-15T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/43472038", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nWhat’s Encouraged Daily:\nContribute to the development of new HBM products by assisting with the overall design, and layout.\n•    Interpret product specifications and design circuits to meet the required functionality.\n•    Design, implementation, and improvement of Complex Analog Mixed Circuits such as CMOS Amplifiers, Comparators, Bandgap references, V2I converters, LDOs, charge pumps, Oscillators, DLL, IO circuits (DDR/LPDDR), Delays, Process and temperature sensors in advanced semiconductor process nodes for advanced High Bandwidth Memory (HBM) products\n•    Integration of modules with Power delivery network and propose design solution for optimum performance\n•    Deep understanding of Array and its peripheral circuits.\n•    Driving innovation into the future Memory generations within a dynamic work environment\n•    Validate & optimize design for reliability (Device stress, Aging effect)\n•    EM/IR simulation, optimize layout to achieve best circuit performance\n•    Custom digital circuit design & validation\n•    Parasitic modeling and assisting in design validation, reticle experiments and required tape-out revisions\n•    Overseeing and managing the layout process including floor-planning, placement, and routing\n•    Performing verification processes with modeling and simulation using industry standard simulators\n•    Contributing to cross group communication to work towards standardization and group success\n•    Working with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product\n•    Proactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality\n•    Participate in new circuit conception and design as needed\n•    Perform circuit simulations using standard industry simulators such as FINESIM, HSPICE, and VERILOG\n•    Responsible for reliability and degradation verification.\n•    Assist in design validation, reticle experiments, and required tape-out revisions\n•    Contributes expert technical knowledge to advance innovative technical solutions\n•    Provides advice and counsel to senior management on significant technical issues\nOversee the layout process\n•    Help floor-planning process, including placement and routing optimization\n•    Optimize design rules for cost, performance, and functionality\n•    Import layout parasitic information into the circuit simulation environment\nMaintain Technical Expertise and Provide Training\n•    Contribute to cross-group communication to work towards standardization and group success\n•    Aid in design documentation and communicating best-known practices to the entire department\n•    Participate in continuing education and competitor analysis\n•    Proactively solicit feedback from Standards, CAD, modeling, and verification groups to ensure the design quality\n•    Drive innovation into the future Memory generations within a dynamic work environment\nAI Usage\nAlso, strong AI proficiency, a solid understanding of agentic AI models, and effective use of tools such as Claude are expected to significantly improve engineering efficiency, enhance PPA (Power, Performance, Area) optimization, and accelerate overall delivery timelines.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Synthesis Engineer, Principal", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-15T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721049857", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Description\n\nJob Description:  \nShould have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.\n\nExperience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.\n\nExperience in all aspects of timing closure for multi-clock domain designs.\n\nShould be familiar with MCMM synthesis and optimization.\n\nShould have good understanding of low-power design implementation using UPF.\n\nExperience with scripting language such as Perl/ Python, TCL.\n\nExperience with different power optimization flows or technique such as clock gating.\n\nShould be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation\n\nShould be able to handle ECOs and formal verification and maintain high quality matrix\n\n15+ yrs experience\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU Core Validation Engineer (Senior Lead)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-15T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718595354", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nJob Overview:\n\nAs a “CPU Core Validation Engineer” you would be part of CPU Validation team in CPU org working on validation of CPU core pipeline arch and micro arch features.\n\nRoles and Responsibilities:       \nDevelop detailed test plan considering the IP arch and uarch features. \n\nWork with CPU design and verification teams to develop CPU bring up and functional validation test plans for the IP owned.  \n\nDevelop validation methodology and test contents to exercise on emulators during pre-Si phase and on Silicon.\n\nWork with SOC bring up teams, software teams to plan CPU core features bringup and end to end validation. \n\nTriage and debug failures on Silicon.  \n\nDevelop test contents and testing strategies to assist validation of CPU on silicon.  \n\nWork with CPU verification teams to reproduce silicon fails on emulators and FPGAs. \n\nWork with design team to suggest, architect new debug features to improve future CPU bringup’s.\n\nMinimum Requirements: \nBA/BS degree in CS/EE with 12+ years’ experience.  \n\n6+ Experience in Silicon Validation and bring up. \n\nImplementation of assembly, C/C++ language embedded firmware \n\nExperience with software tool chain including assemblers, C compilers, Makefiles, and source code control tools.\n\nPreferred Requirements: \nGood understanding of micro-processor architecture, in domains such as: Cache Coherence, Memory ordering and Consistency, Prefetching, Branch Prediction, Renaming, Speculative execution, and Address Translation/Memory Management.\n\nKnowledge of Random Instruction Sequencing (RIS) and testing a given design, at the Block/Unit-level and Subsystem/Chip-level for proving correctness.\n\nExperience in writing Test plans and Assembly code.\n\nAbility to develop and work independently on a block/unit of the design.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Engineer II - Backend Implementation", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-09-15", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Senior-Engineer-II---Backend-Implementation_R3785-26-3", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nCompany Description\nMicrochip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products.\nJob Description\nMicrochip AES Design team looking for an experienced and motivated Backend Implementation Engineer to perform STA for larger SOCs. As a member of Implementation team, you will be responsible for timing constraints (SDC) generation, timing closure and Low Power checks for multiple blocks and top level. The candidate should have strong experience with STA tools like Tempus/Primetime. The candidate should have in depth knowledge of timing constraints.\n\nLocation: Bangalore, India\n\nRequirements/Qualifications:\n\nJob Responsibilities:\nThe employee is responsible for implementation activities of multiple large & complex blocks & sub-system implementation from 16nm to 3nm and below technology nodes. The employee is expected to take ownership of Full Chip/Subsystem complex design & flow challenges, which would include:\nPerform STA timing closure for multi-million hierarchical complex designs.\nLead and drive team members to complete Implementation activities.\nComplete timing closure for blocks & top level in advanced nodes.\nDevelop constraints/SDC and perform pre & post-layout timing closure.\nPerform CLP and LEC for both full chip and block level.\nExperience on UPF/CPF would be an added advantage.\nOptimize design performance through timing closure and power optimization.\nDevelop and maintain design constraints and timing models.\nAnalyze and debug timing issues.\nInserting DFT logic for both block and top level.\nAnalyze Physical timing challenges and provide guidance for placement & CTS.\nOccasional travel needed.\nUse metric-driven techniques to help ensure first-pass working silicon.\nCommunicate regularly with the implementation and project team to resolve issues, and communicate status to Project Management.\n\nJob Qualifications:\nThis position requires at least B.E/B.Tech/M.Tech in Electronics with 7+ years of STA experience in a fast-paced environment with following experience.\nExpertise in Implementation activities: STA.\nStatic Timing/Crosstalk Analysis and timing closure\nMust have understanding of DFT insertion.\nExpertise with Synthesis & STA Tools (Genus, Fusion Compiler, Primetime or Tempus).\nExperience on Conformal LEC and CLP will be added advantage.\nStrong programming knowledge in Perl, TCL, and/or Shell and Python Scripting\nExcellent oral and written communications skills to work with teams across the globe\nStrong understanding of timing closure and power optimization techniques\nMust have good understanding of Verilog.\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Silicon Integration Design Engineer - Timing Model", "company": "Lattice", "location": "Penang, Malaysia", "date_posted": "2026-09-15", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Penang-Malaysia/Silicon-Integration-Design-Engineer---Timing-Model_R-100610-1", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nDetailed Description\nCollaborate with IP designers and modelling team to ensure timing model requirements align with FPGA tool specifications.\nUnderstand IP functionality to define timing arcs and constraints per spec and deliver to software team.\nPerform quality checks on timing models to confirm all timing arcs meet software requirements.\nAddress issues such as missing timing arcs and missing clock information.\nGenerate timing reference models based on IP requirements\nCompare timing models: Current proprietary format vs. Liberty format (.lib).\nHandle custom design simulations, use SPICE simulations and additional data to construct proprietary Timing models.\nGenerate full chip timing model to bridge between IP timing models, using SPICE simulations or STA reports.\nFPGA power model know-how and knowledge will be added advantage.\nExperience with PrimeTime/Liberate will be added advantage.\n\nAdditional Job Description\n10 yrs experience of hardware integration design\nFPGA timing model know-how and knowledge will be added advantage.\nSuccessfully went through whole development from start to Tape Out of at least 2 products.\nProficient in schematic generation using Cadence Virtuoso tool and spice simulation of it.\nWorking knowledge of System Verilog, synthesis, and static timing analysis\nSpecialist in floor-planning, power estimate, timing and back-end methodologies\nExperience with Linux scripting and Python\nExperience and knowledge of PnR is a plus\nStrong written and oral communication skills\nThe ability to stay up-to-date with the latest advancements in technology & design\nAbility to leverage AI tools to accelerate content creation, use AI to analyze large datasets and identify patterns.\nDetailed Description\nCollaborate with IP designers and modelling team to ensure timing model requirements align with FPGA tool specifications.\nUnderstand IP functionality to define timing arcs and constraints per spec and deliver to software team.\nPerform quality checks on timing models to confirm all timing arcs meet software requirements.\nAddress issues such as missing timing arcs and missing clock information.\nGenerate timing reference models based on IP requirements\nCompare timing models: Current proprietary format vs. Liberty format (.lib).\nHandle custom design simulations, use SPICE simulations and additional data to construct proprietary Timing models.\nGenerate full chip timing model to bridge between IP timing models, using SPICE simulations or STA reports.\nFPGA power model know-how and knowledge will be added advantage.\nExperience with PrimeTime/Liberate will be added advantage.\n\nAdditional Job Description\n10 yrs experience of hardware integration design\nFPGA timing model know-how and knowledge will be added advantage.\nSuccessfully went through whole development from start to Tape Out of at least 2 products.\nProficient in schematic generation using Cadence Virtuoso tool and spice simulation of it.\nWorking knowledge of System Verilog, synthesis, and static timing analysis\nSpecialist in floor-planning, power estimate, timing and back-end methodologies\nExperience with Linux scripting and Python\nExperience and knowledge of PnR is a plus\nStrong written and oral communication skills\nThe ability to stay up-to-date with the latest advancements in technology & design\nAbility to leverage AI tools to accelerate content creation, use AI to analyze large datasets and identify patterns.\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nMalaysiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Senior Memory Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-09-15", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Senior-Memory-Design-Engineer_R027065", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nJD for Senior Design Engineer\n1) Contribute/Lead towards Design and Development of Single/Multiport SRAM, Register file compilers in 28nm/16FF/7FF/5FF Technologies\n2) Circuit design/simulation of key components such as bitcell, WL decoder, SAMP, Column decoder and control logic.\n3) Development of critical path and characterization flow to perform detailed margin and characterization simulations.\n4) Statistical Analysis of Bit-Cell and Sense Amplifier and Self Time Blocks for Compiler Target yield Sign-Off\n5) Design Tuning, Margin Analysis and Sign-Off for Complete Compiler to meet Yield and Performance targets.\n6) Logic simulations and detailed timing analysis of key paths in high speed memory design.\n7) Signal-Integrity (EM) and Power-Integrity (IR drop) analysis and design. \nSkill Sets/Prerequisites \n1) Expertise of high speed/low power CMOS circuit design, clocking scheme, Static and dynamic logic circuits\n2) Experience in Designing and driving one or many Memory Compilers Specifications to final release \n3) Deep expertise in Understanding and Developing Split rail, Power gating Architecture and circuit design\n4) Hands on Experience on Silicon Debug/Diagnose the failures. Deep expertise on Silicon Failures, Analysis and fixing.\n5 Complete hands on experience in using Cadence/Mentor schematic/layout editor tools\n6) Complete hands on experience with Circuit simulation, MC analysis and waveform viewer tools such as HSPICE, HSIM, XA, FinSim, XARA, nWave, waveform viewer etc\n7) Experience in Skill/Perl/Python Scripting is a strong plus \n8) Experience in Understanding the layout design issues in sub nanometer regime is a must. \n9. Expertise in Understanding Memory DFT is a Plus.\n10. Masters Degree with 4+ Years or Bachelors Degree with 5+ years\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Senior Memory Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-09-15", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Senior-Memory-Design-Engineer_R027062", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nJD for Senior Design Engineer\n1) Contribute/Lead towards Design and Development of Single/Multiport SRAM, Register file compilers in 28nm/16FF/7FF/5FF Technologies\n2) Circuit design/simulation of key components such as bitcell, WL decoder, SAMP, Column decoder and control logic.\n3) Development of critical path and characterization flow to perform detailed margin and characterization simulations.\n4) Statistical Analysis of Bit-Cell and Sense Amplifier and Self Time Blocks for Compiler Target yield Sign-Off\n5) Design Tuning, Margin Analysis and Sign-Off for Complete Compiler to meet Yield and Performance targets.\n6) Logic simulations and detailed timing analysis of key paths in high speed memory design.\n7) Signal-Integrity (EM) and Power-Integrity (IR drop) analysis and design. \nSkill Sets/Prerequisites \n1) Expertise of high speed/low power CMOS circuit design, clocking scheme, Static and dynamic logic circuits\n2) Experience in Designing and driving one or many Memory Compilers Specifications to final release \n3) Deep expertise in Understanding and Developing Split rail, Power gating Architecture and circuit design\n4) Hands on Experience on Silicon Debug/Diagnose the failures. Deep expertise on Silicon Failures, Analysis and fixing.\n5 Complete hands on experience in using Cadence/Mentor schematic/layout editor tools\n6) Complete hands on experience with Circuit simulation, MC analysis and waveform viewer tools such as HSPICE, HSIM, XA, FinSim, XARA, nWave, waveform viewer etc\n7) Experience in Skill/Perl/Python Scripting is a strong plus \n8) Experience in Understanding the layout design issues in sub nanometer regime is a must. \n9. Expertise in Understanding Memory DFT is a Plus.\n10. Masters Degree with 4+ Years or Bachelors Degree with 5+ years\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Memory Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-09-15", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Memory-Design-Engineer_R027064", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nJD for Memory Design Engineer\n1) Contribute/Lead towards Design and Development of Single/Multiport SRAM, Register file compilers in 28nm/16FF/7FF/5FF Technologies\n2) Circuit design/simulation of key components such as bitcell, WL decoder, SAMP, Column decoder and control logic.\n3) Development of critical path and characterization flow to perform detailed margin and characterization simulations.\n4) Statistical Analysis of Bit-Cell and Sense Amplifier and Self Time Blocks for Compiler Target yield Sign-Off\n5) Design Tuning, Margin Analysis and Sign-Off for Complete Compiler to meet Yield and Performance targets.\n6) Logic simulations and detailed timing analysis of key paths in high speed memory design.\n7) Signal-Integrity (EM) and Power-Integrity (IR drop) analysis and design. \nSkill Sets/Prerequisites \n1) Expertise of high speed/low power CMOS circuit design, clocking scheme, Static and dynamic logic circuits\n2) Experience in Designing and driving one or many Memory Compilers Specifications to final release \n3) Deep expertise in Understanding and Developing Split rail, Power gating Architecture and circuit design\n4) Hands on Experience on Silicon Debug/Diagnose the failures. Deep expertise on Silicon Failures, Analysis and fixing.\n5 Complete hands on experience in using Cadence/Mentor schematic/layout editor tools\n6) Complete hands on experience with Circuit simulation, MC analysis and waveform viewer tools such as HSPICE, HSIM, XA, FinSim, XARA, nWave, waveform viewer etc\n7) Experience in Skill/Perl/Python Scripting is a strong plus \n8) Experience in Understanding the layout design issues in sub nanometer regime is a must. \n9. Expertise in Understanding Memory DFT is a Plus.\n10. Masters Degree with 2+ Years or Bachelors Degree with 3+ years\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Lead Design Engineer ( Synthesis/LEC/CLP )", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-09-15", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Design-Engineer---Synthesis-LEC-CLP--_R56395", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nCadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.\nThe Cadence Advantage\nThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.\nCadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.\nThe unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success.\nMultiple avenues of learning and development available for employees to explore as per their specific requirement and interests.\nYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.\n\nExperience: 5–8 Years\nBE/BTech/ME/MS/MTech in Electrical/Electronic or equivalent\nLocation: Bangalore/Ahmedabad/Pune\nAbout the Role\nWe are looking for a Lead Design Engineer to provide hands-on execution across Synthesis, LEC, CLP, and UPF/power-intent flows for advanced ASIC/SoC designs. This role is execution-focused with growing ownership: debugging synthesis and LEC issues independently, contributing to CLP sign-off, and writing constraints and ECO scripts, while working closely with the Team on complex escalations.\nKey Responsibilities\nRun and debug LEC sign off on design blocks; investigate and resolve NEQs and constraint mismatches\nWork on Genus synthesis runs to improve QoR, debug SDC/constraint issues. \nSupport CLP flows\nWrite and maintain ECO scripts and timing/power constraints for design blocks\nIndependently triage and document issues, escalating complex or systemic issues as needed.\nCollaborate with PD, DFT, and RTL teams to resolve cross-functional issues affecting synthesis/LEC/CLP closure\nPrepare clear status updates and technical summaries for internal tracking\nRequired Skills\n5–8 years of hands-on experience in ASIC synthesis, LEC, and/or low-power verification flows\nWorking knowledge of Cadence Genus and Conformal (LEC and/or CLP)\nFamiliarity with UPF/CPF-based power intent (IEEE 1801)\nScripting proficiency in Tcl, Perl, or Python; comfortable in Unix/Linux based environments.\nSolid understanding of digital design fundamentals, STA basics, and low-power architecture concepts\nStrong communication skills and ability to work independently on assigned blocks\n\nRegards\nK Madhu Prasad\nkmadhup@cadence.com\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Timing & Power Analysis CAD Engineer", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-09-15", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Timing---Power-Analysis-CAD-Engineer_2603008", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nAs a key CAD member of Marvell Central Engineering, you will play a leading role on developing next-generation automated design flow and its add-on tools. You will have the opportunity to use your extensive design and CAD knowledge to participate in defining the whole organization's design infrastructure, methodology and workflows.\nWhat You Can Expect\nDevelop, maintain, and enhance PrimeTime-STA & PrimePower-based power signoff flows within Marvell's M1DP CAD platform.\nSolid understanding of STA flows including dealing with hierarchical designs\nUnderstanding of using Hyperscale & Context models for Hierarchical STA analysis\nSolid understanding of power estimation flows (average and time-based)\nEnable and support In-Design Timing & Power flows for timing/power-aware optimization during physical implementation.\nCollaborate with Physical Design and Front-End teams to set up FSDB/activity files, UPF/CLP power intent, and SAIF/vector annotation for accurate power computation.\nDevelop and maintain glitch analysis and optimization flows, including configuration of glitch-aware datapath optimization settings is a plus\nGenerate, validate, and deliver power analysis reports (dynamic, leakage, glitch) to design teams across multiple ASIC projects by building power dashboard\nExperience with PrimePower RTL 2.0 adoption for early-stage power estimation, enabling designers to identify and resolve power issues before gate-level analysis is plus\nInterface with EDA vendors to evaluate new tool features, report bugs, and drive tool improvements.\nDevelop automation scripts (Tcl, Python) to streamline timing & power flow execution, debug, and reporting.\nSupport tapeout activities by ensuring power & timing signoff closure across blocks and full-chip designs.\nContribute to knowledge sharing, documentation, and training for timing & power CAD flows across global teams.\n\nWhat We're Looking For\nB.E./B.Tech or M.E./M.Tech in Electrical Engineering, Electronics Engineering, Computer Science, or a related field.\n\n6 to 10 years of hands-on experience in CAD flow development or power analysis in the semiconductor industry (level-dependent).\n\nProven experience with Synopsys PrimeTime & PrimePower (gate-level and/or RTL-level power analysis).\n\nSolid understanding of timing concepts\n\nUnderstanding of advanced node timing effects and variation formats (LVF, POCV & AOCV etc)\n\nExperience in correlating  timing QoR between P&R and signoff timing engine\n\nSolid understanding of power analysis concepts: dynamic power, leakage, glitch power, clock gating efficiency (CGE).\n\nExperience with FSDB/VCD/SAIF activity file generation and annotation flows.\n\nFamiliarity with UPF/CPF power intent and multi-voltage design methodologies.\n\nProficiency in Tcl scripting for CAD flow development and automation.\n\nWorking knowledge of Physical Design flows (P&R) and their interaction with power & timing signoff.\n\nStrong analytical and problem-solving skills; ability to debug complex power analysis issues.\n\nGood verbal and written communication skills in English; ability to collaborate with global teams.\n\nThis role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.\nAdditional Compensation and Benefit Elements\nWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\n\nInterview Integrity \nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\n\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\n\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n\n#LI-MN1", "jd_status": "stored"}, {"title": "Senior Software Engineer", "company": "Analog Devices", "location": "India, Bangalore, Nova", "date_posted": "2026-09-15", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-Nova/Senior-Software-Engineer_R266040", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nResponsibilities & Scope\nDefine, Develop, prototype, and productize automotive in‑car infotainment audio algorithms across the cabin audio signal chain, including (but not limited to) algorithms like Acoustic Echo Cancellation (AEC), Acoustic & voice cancellation, Road Noise Cancellation (RNC), Personalized Sound Zones (PSZ), In‑Car Communication (ICC), Voice activity detection, trigger word recognition, etc.\nApply AI/ML methods where beneficial (e.g., model‑assisted estimation, adaptive scene classification, learning‑based enhancement, Data set creation for training) to improve robustness and user experience (role requirement).\nOwn algorithm lifecycle activities: requirements interpretation, algorithm design, simulation, development, validation, and tuning, translating concepts into robust, production‑ready implementations\nExecute embedded implementation and optimization of algorithms on target ADI DSP platforms and relevant SoC platforms (ARM‑based and similar), ensuring real‑time performance and memory efficiency\nIntegrate audio algorithms into automotive embedded software stacks and frameworks, ensuring functionality, performance, and reliability on target platforms and reference systems\nContribute to system‑level integration and verification of real‑time automotive products, including debugging complex multi‑domain issues spanning algorithm, firmware, and platform layers\nCollaborate with cross‑functional stakeholders (systems, firmware/platform, QA, product, customer teams) to refine feature requirements, validate behavior in real vehicles, and support customer integration needs\nUse agentic and AI‑enabled productivity tools across the engineering lifecycle (e.g., AI‑assisted coding, test generation, documentation acceleration, and automated analysis) to improve quality, throughput, and traceability (role requirement).\nDocument engineering work products (design notes, configuration/guidelines, verification evidence) in alignment with structured development expectations (like ASPICE) typically used in automotive software programs\nDemonstrate strong ownership: ability to work independently, address change requests, and iterate quickly via rapid prototyping to validate hypotheses\nAbility to create solutions and add value to customer audio system problems through patentable IPs and innovative methods\n\nQualifications — Academic Background, Experience, Skillset & Soft Skills\nEducation / Academic RecordBachelor’s or Master’s degree in Electrical/Electronics & Communication, Computer Science, Signal Processing, Embedded Systems, or equivalent with 8-10 years of experience in audio signal processing and AI enabled algorithm developments on embedded platforms\nStrong fundamentals in signal processing and algorithmic thinking; exposure to MATLAB-based modeling/simulation is valuable\n\nCore Technical Skills (Must Have)Strong programming skills in Embedded C/C++ with a disciplined approach to real‑time and performance‑critical development\nGood exposure to AI/ML methods and tools to automotive noise cancellation and audio applications\nSolid embedded systems fundamentals including RTOS concepts, concurrency, timing, and debugging\nDemonstrated ability to develop and integrate software on ADI DSPs and ARM‑based SoC/ASSP platforms interfacing with ADI parts and automotive reference systems\nExperience in algorithm-to-embedded translation: floating/fixed‑point considerations (as applicable), latency budgeting, memory/performance profiling, and platform‑aware optimization (role requirement).\n\nAudio / Automotive Domain Skills (Strongly Preferred)Background in automotive audio infotainment software projects and/or cabin audio use cases\nHands‑on familiarity with one or more: AEC/voice enhancement, RNC/ANC-style adaptation, beamforming/sound zones, in‑car communication, and related cabin audio processing\n\nAI / Tooling Skills (Expected for This Role)Practical exposure to applying AI/ML techniques in signal processing / audio enhancement contexts (e.g., feature extraction, classification, learning‑based estimators) (role requirement).\nComfort using AI-enabled and agentic engineering tools to accelerate coding, testing, debugging, and documentation while maintaining engineering rigor and traceability (role requirement).\n\nProfessional & Soft SkillsStrong problem-solving and critical thinking skills; able to break down ambiguous problems and converge on pragmatic solutions\nEffective communication and collaboration skills with cross‑functional teams and customer-facing stakeholders when needed\nSelf-starter mindset with strong ownership, ability to handle multiple tasks in parallel, and a learning-oriented attitude\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Analog Design, Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-15", "url": "https://careers.synopsys.com/job/bengaluru/analog-design-staff-engineer/44408/100672041328", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in the trenches of high-speed interface design, where a 50-ohm trace matters and a poorly modeled via can sink a product launch. You know that signal integrity is not just about making the eye diagram look clean, it is about understanding what breaks at 56 Gbps and why the power delivery network you signed off on three months ago is now causing headaches in the lab. You think in transmission lines, S-parameters, and frequency domain responses, not because you memorized the textbook but because you have debugged enough real silicon to know where theory meets reality.\nYou are comfortable sitting with a layout team reviewing a PCB stackup, then jumping into a SPICE deck to model crosstalk on a DDR5 interface, then explaining to a customer why their return path is the problem. You do not wait for someone to hand you a perfect model. You build it, verify it, and iterate until it matches what you see on the scope.\nResearch excites you, especially when it is tied to what is coming next. MRDIMM, LPDDR6, HBM4, UCIe. You want to be ahead of the curve, not chasing it. At Synopsys, you will work on the interfaces that power the next generation of AI and compute, and the work you do will show up in customer tape-outs across the industry.\nWhat You'll Be Doing\nReview and analyze die, package, and PCB physical layouts for signal integrity and power integrity performance on high-speed interfaces\nModel, simulate, and verify DDR, HBM, UCIe, PCIe, and Ethernet interfaces using SPICE and 3D field solvers to ensure compliance with specifications\nDrive improvements to SI/PI methodology flows, identifying bottlenecks and building automation to increase accuracy and turnaround time\nCollaborate with IP development, customer engagement, and CAD teams on cross-functional projects tied to next-generation interface rollouts\nIndependently lead SI/PI research and development activities for emerging standards including MRDIMM, LPDDR6, HBM4, and UCIe\nDebug and resolve signal integrity and power integrity issues in customer SoC, package, and board designs across different application domains\nScript and automate simulation workflows using Python and TCL to streamline repetitive tasks and improve team productivity\nThe Impact You Will Have\nEnable SI/PI sign-off for customer designs across automotive, data center, mobile, and AI applications, directly affecting tape-out schedules and product success\nImprove the speed and accuracy of SI/PI methodology flows used by teams globally, reducing simulation turnaround time and increasing confidence in results\nProvide technical guidance to customers on next-generation memory and interconnect IP, helping them navigate design tradeoffs before they commit to silicon\nDrive early research into emerging standards so Synopsys can deliver IP and tools ahead of industry adoption curves\nBuild cross-team collaboration between Bengaluru, North America, and APAC engineering groups, ensuring knowledge transfer and consistent methodology\nContribute to Synopsys' leadership in high-speed interface IP by solving hard problems that competitors have not figured out yet\nSupport the development of AI-driven SoCs by ensuring the memory and interconnect layers can actually deliver the bandwidth the architecture promises\nWhat You'll Need\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field\n5+ years of hands-on experience in signal integrity, power integrity, or high-speed interface design\nStrong working knowledge of transmission line theory, time-domain and frequency-domain analysis, and S-parameter modeling\nProficiency with SPICE simulation tools and experience using 3D electromagnetic field solvers for layout extraction and analysis\nPractical understanding of DDR, HBM, UCIe, PCIe, or Ethernet interface architectures and their SI/PI challenges\nSolid verbal and written communication skills in English, you will work with global teams and customer-facing engineers regularly\nExperience with Python and TCL scripting for simulation automation and data post-processing is a strong plus\nWho You Are\nYou can look at a layout and immediately spot the return path discontinuity or the stub that is going to cause reflections at 10 GHz\nYou are comfortable explaining a complex SI tradeoff to a customer architect in two sentences without losing the technical nuance\nYou do not treat simulation as a black box, if the results do not make sense, you dig into the model until you understand why\nYou are organized enough to juggle multiple customer engagements and internal projects without dropping threads or missing deadlines\nYou push back when a design decision does not make sense from an SI/PI perspective, and you do it with data, not opinion\nYou are curious about what is coming next in the industry and you actively read specs, papers, and early drafts of emerging standards\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "ASIC Verification- Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-15", "url": "https://careers.synopsys.com/job/bengaluru/asic-verification-staff-engineer/44408/100672041264", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Title:\n* ASIC Verification- Staff Engineer\n \nWe Are:\n \n At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\n \nYou Are:\n \n You are an accomplished verification engineer with a passion for excellence and a track record of delivering robust, high-quality IP solutions. You thrive in a fast-paced, dynamic environment and are excited by the opportunity to work on next-generation connectivity protocols that power commercial, enterprise, and automotive applications. With a solid foundation in Electrical/Electronics Engineering (BSEE with 5+ years or MSEE with 3+ years of relevant experience), you bring deep expertise in System Verilog and industry-standard verification methodologies such as UVM/OVM/VMM. Your hands-on experience developing HVL-based test environments and extracting meaningful verification metrics sets you apart as a technical leader.\n \n You are a collaborative team player who values knowledge sharing and actively contributes to a culture of continuous improvement. Your familiarity with protocols like MIPI-I3C, UFS, AMBA, Ethernet, DDR, PCIe, and USB allows you to quickly ramp up on new projects and deliver results. You bring a strong analytical mindset, exceptional debugging skills, and a drive to meet and exceed quality metrics. Experienced with scripting languages like Perl, TCL, and Python, you automate processes for efficiency and scalability. Your strong communication skills, initiative, and global perspective enable you to work effectively with cross-functional and multi-site teams. Above all, you are a lifelong learner who embraces challenges, adapts to new technologies, and is committed to shaping the future of silicon design.\n \nWhat You’ll Be Doing:\n * Specify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies.\n* Develop and execute comprehensive test plans, ensuring coverage of unit-level and system-level requirements.\n * Design, code, and debug testbenches, test cases, and functional coverage models to validate complex IP functionalities.\n* Perform functional coverage analysis and manage regression testing to achieve and maintain required quality metrics.\n* Collaborate closely with RTL designers and global verification teams to resolve issues and drive verification closure.\n* Leverage scripting (Perl, TCL, Python) to automate verification flows, streamline processes, and enhance productivity.\n * Contribute to the development and refinement of verification methodologies, including VIP development and formal verification approaches.\n \nThe Impact You Will Have:\n* Ensure the delivery of high-quality, robust IP cores that power critical applications in commercial, enterprise, and automotive markets.\n * Drive innovation in verification methodologies, setting new standards for efficiency and coverage.\n* Enhance time-to-market by identifying and resolving design and verification issues early in the development cycle.\n* Strengthen Synopsys’ reputation as a leader in silicon IP and verification through technical excellence and customer focus.\n* Mentor and support junior engineers, fostering a culture of learning and continuous improvement.\n * Contribute to the success of global, multi-site R&D teams by providing expertise and driving cross-functional collaboration.\n \nWhat You’ll Need:\n* BSEE with 5+ years or MSEE with 3+ years of relevant experience in ASIC or IP verification.\n* Expertise in developing HVL (System Verilog)-based verification environments and testbenches.\n * Strong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools.\n* Proficiency in verification methodologies such as UVM, OVM, or VMM; exposure to formal verification is highly desirable.\n * Solid understanding of protocols such as MIPI-I3C/UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB.\n* Familiarity with scripting languages (Perl, TCL, Python) and HDLs (Verilog); experience with VIP development is a plus.\n * Demonstrated ability to work with functional coverage-driven methodologies and quality metric goals.\n \nWho You Are:\n * Analytical thinker with strong problem-solving and debugging skills.\n* Excellent verbal and written communication abilities.\n * Team player who thrives in collaborative, multi-site environments.\n * Proactive, self-motivated, and able to take initiative on challenging projects.\n * Detail-oriented, quality-focused, and driven by a desire to excel.\n* Adaptable and eager to continuously learn and apply new technologies.\n \nThe Team You’ll Be A Part Of:\n \n You will join the Solutions Group’s DesignWare IP Verification R&D team, a highly skilled and diverse group of engineers dedicated to delivering world-class IP cores for next-generation connectivity. The team operates in a collaborative, multi-site environment, leveraging global expertise to solve complex verification challenges. Together, you will drive innovation, share knowledge, and uphold Synopsys’ reputation for technical leadership and excellence.\n \nRewards and Benefits:\n \nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process....Less", "jd_status": "stored"}, {"title": "Automotive Functional Safety Staff Engineer - Digital DesignWare IP", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-15", "url": "https://careers.synopsys.com/job/bengaluru/automotive-functional-safety-staff-engineer-digital-designware-ip/44408/100672041248", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Title\nAutomotive Functional Safety Staff Engineer - Digital DesignWare IP\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in the automotive safety world and you know that a well-written safety case is not just paperwork, it is the difference between a chip that ships and one that sits in legal review for six months. You understand ISO 26262 not as a checklist but as a framework for making defensible engineering decisions under uncertainty.\nYou are comfortable translating a vague customer requirement into a Technical Safety Concept that actually works, and you can explain to a hardware team why their design choice affects ASIL classification without making it feel like a lecture. You do not wait for complete specs to start safety planning. You work with what you have, ask the right questions, and build a safety argument that holds up under scrutiny. At Synopsys, you will work on automotive IP that powers the next generation of vehicles, and the safety work you do will matter.\nWhat You'll Be Doing\nDevelop and maintain ISO 26262 work products including Technical Safety Concept, FMEDA, FTA, DFMEA, DFA, Safety Plan, and Safety Case for Digital DesignWare IP\nCollaborate with IP development teams and automotive customers to align functional safety deliverables with project timelines and ASIL requirements\nEvaluate customer quality, functional safety, and reliability requirements, translating them into actionable engineering guidance\nDesign and implement automation scripts to streamline safety analysis workflows, including FMEDA and fault injection reporting\nLead quality and functional safety reviews, generating detailed reports with findings and recommendations for design improvements\nThe Impact You Will Have\nEnsure Synopsys Automotive IP meets ISO 26262 compliance and achieves ASIL B, C, and D certification for safety-critical automotive applications\nAccelerate customer time to market by delivering complete, audit-ready safety documentation that reduces integration risk\nDrive measurable improvements in safety process efficiency through automation, reducing manual analysis time across IP families\nSupport development of differentiated automotive IP solutions that meet stringent safety demands of ADAS, autonomous driving, and electrification platforms\nElevate Synopsys' reputation as a trusted partner in automotive safety, strengthening customer confidence and market share\nWhat You'll Need\nBachelor's degree in Electrical Engineering with 8+ years of relevant experience, or Master's degree with 5+ years\nFormal training and hands-on expertise in ISO 26262 functional safety standards, including direct experience developing safety work products for ASIL B, C, or D applications\nDemonstrated experience with semiconductor development flows and digital design at the IP or SoC level\nProficiency in English for technical writing and cross-functional collaboration with global teams\nProven track record qualifying embedded hardware or hardware/software systems to ISO 26262 ASIL levels, including ASIL D\nExperience with ISO 26262 Part 5, hardware description languages like Verilog or VHDL, AEC Q100, or scripting languages such as Python is a plus\nWho You Are\nYou can take a 200-page customer safety requirement document and pull out the three things that actually affect your IP architecture, then explain them to a design lead in a 10-minute conversation\nOrganized and detail-oriented, you manage multiple safety deliverables across product lines without losing track of dependencies or deadlines\nYou push back constructively when a safety plan is missing critical information or a design decision creates an unmitigated safety risk\nComfortable working across time zones, you build trust with customers and colleagues through clear communication and follow-through\nThe Team You'll Be Part Of\nYou will join a high-performing, globally distributed IP team that is at the forefront of automotive safety and reliability innovation. The team collaborates closely with product development, quality assurance, and customer engineering groups to deliver world-class automotive IP solutions. Together, you will champion functional safety standards, drive continuous improvement, and support customers in deploying safe, reliable automotive products.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Constraints Verification Applications Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-15", "url": "https://careers.synopsys.com/job/bengaluru/constraints-verification-applications-engineer/44408/100654734768", "is_hardware": true, "platform": "talentbrew", "jd_text": "Alternate Job Titles\nConstraints Verification Applications Engineer\nSDC Flow Application Engineer\nASIC Constraints AE\nTiming Constraints Applications Engineer\nDesign Constraints Methodology Engineer\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years living in the space between design intent and what actually gets constrained, and you know that bad SDC is the silent killer of chip schedules. You have seen projects stall because constraints were incomplete, over-constrained, or just plain wrong, and you have learned that getting the constraint flow right early is what separates a clean tapeout from months of painful debug.\nYou are comfortable sitting with a design team, looking at their RTL, their clock architecture, and their constraint files, and spotting the gaps before they become timing closure nightmares. You do not just write SDC, you understand the methodology behind constraint generation, verification, and management across the entire flow from RTL to signoff. You know when a multi-mode, multi-corner setup is incomplete, and you can explain why it matters without making it sound like a lecture.\nWorking across R&D, field teams, and customer sites does not intimidate you. You have learned that the best constraint flows come from understanding what the design is actually trying to do, not just mechanically translating specs into SDC. At Synopsys, you will work with semiconductor companies solving real constraint challenges on chips that will ship, and the methodologies you help build will become part of how they verify timing and functional correctness.\nWhat You'll Be Doing\nPartner directly with semiconductor companies across the region to solve end-to-end constraint flow challenges including SDC generation, verification, management, and signoff\nDeploy and optimize Synopsys constraint tools like Fishtail/TCM, SpyGlass-Constraints, and PrimeTime across customer design flows, working at both RTL and netlist levels\nDebug constraint issues, analyze MCP (multi-cycle path), false path, and generated clock reports, and trace problems through RTL, synthesis, and timing signoff\nCollaborate with Synopsys R&D and product validation teams to develop methodologies that address customer-specific constraint problems and feed real-world requirements back into product roadmaps\nBuild and maintain automation scripts in TCL, Perl, and Unix shell to streamline constraint generation, verification, and management workflows\nCoordinate with technical account managers and worldwide account teams to shape customer strategies, drive tool adoption, and support successful project completion\nGather, refine, and track flow requirements based on customer feedback, engineering judgment, and emerging tool capabilities, including support for multi-modal analysis and equivalence checks\nThe Impact You Will Have\nEnable semiconductor companies to achieve timing closure faster by solving constraint flow bottlenecks that would otherwise stall projects for weeks or months\nInfluence the direction of Synopsys constraint verification tools by bringing real customer pain points and use cases directly to R&D teams\nBuild repeatable, scalable constraint methodologies that become the foundation for how customers manage SDC across multiple projects and product lines\nAccelerate customer adoption of Synopsys solutions, directly contributing to business growth and long-term account relationships in the region\nReduce customer design respins by catching constraint errors earlier in the flow, saving significant schedule time and engineering cost\nEstablish yourself as a trusted technical advisor to design teams, the person they call when constraint verification gets hard\nShape how the next generation of complex, multi-modal chips are constrained and verified, ensuring functional correctness and timing signoff quality\nWhat You'll Need\nBE/BTech/ME/MTech in Electronics Engineering, Computer Science, or Microelectronics with 5+ years of hands-on industry experience in ASIC design or verification\nEnd-to-end experience with SDC and constraint flows including constraint generation, verification, management, and signoff\nDeep working knowledge of constraint methodologies including multi-cycle paths, false paths, generated clocks, multi-modal analysis, and equivalence checks at RTL and netlist levels\nProven experience with Synopsys constraint tools such as Fishtail/TCM, SpyGlass-Constraints, PrimeTime, or equivalent industry-standard constraint verification and signoff tools\nStrong command of VHDL, Verilog, and SystemVerilog RTL, and solid understanding of ASIC design flows from RTL to tapeout\nExposure to timing closure, static timing analysis (STA), and constraint report analysis and debugging\nAdvanced scripting skills in TCL, Unix shell, Perl, or Python for automation, flow development, and debugging\nWho You Are\nYou can walk into a customer meeting, quickly assess where their constraint flow is breaking down, and propose a concrete next step without needing three follow-up calls\nExplaining why a set of constraints is incomplete or incorrect to a design manager or an R&D engineer feels natural to you, and you adjust your explanation depending on who is in the room\nYou are organized enough to manage multiple customer engagements at once, each with different tools, flows, and timelines, without dropping threads\nWorking across time zones, teams, and functions does not slow you down, you know how to pull the right people in at the right time and keep things moving\nYou push back when a customer request does not make technical sense, but you do it in a way that builds trust rather than friction\nDebugging a stubborn constraint issue for hours, even days, does not frustrate you, it is the part of the job you actually enjoy\nThe Team You'll Be Part Of\nYou will be part of the Application Engineering team supporting Synopsys' constraint verification and management solutions across semiconductor customers in the Bengaluru region. You will work closely with R&D, product validation, technical account managers, and global AE teams to drive methodologies, solve customer problems, and enable successful project outcomes. This is a customer-facing role with deep technical collaboration across the organization.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Low Power Verification Applications Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-15", "url": "https://careers.synopsys.com/job/bengaluru/low-power-verification-applications-engineer/44408/100654734720", "is_hardware": true, "platform": "talentbrew", "jd_text": "Alternate Job Titles\nLow Power Verification Applications Engineer\nPower Analysis Application Engineer\nASIC Low Power AE\nSemiconductor Power Verification Engineer\nRTL Power Optimization Applications Engineer\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years deep in the low power trenches of ASIC design, and you know that power is not just another checkbox in the verification plan. It is the thing that determines whether a chip ships on time, meets its thermal budget, or gets another spin. You have debugged power reports at 2 a.m., traced glitches through netlists, and explained to a design lead why their clock gating strategy is leaking watts they cannot afford.\nYou are comfortable sitting with a customer's design team, looking at their UPF, their power intent, and their simulation results, and finding the gap between what they think is happening and what is actually burning power. You do not just run tools, you understand the methodology behind them. You know when to use RTL-level estimation versus gate-level signoff, and you can articulate the tradeoffs without making it a lecture.\nWorking across R&D, field teams, and customer sites does not intimidate you. You have learned that the best solutions come from listening first, then building the right flow for the problem at hand. At Synopsys, you will work with semiconductor companies solving real power problems on chips that will ship, and the methodologies you help build will become part of how they design.\nWhat You'll Be Doing\nPartner directly with semiconductor companies across the region to solve low power verification challenges including power estimation, reduction, audit, correlation, and efficiency analysis\nDeploy and optimize Synopsys low power tools like PrimePower-RTL, SpyGlass-Power, VC LP, and PTPX across customer design flows, working at both RTL and netlist levels\nDebug power reports, analyze power matrices, and trace issues through UPF, RTL, and gate-level designs to resolve discrepancies and improve accuracy\nCollaborate with Synopsys R&D and product validation teams to develop methodologies that address customer-specific problems and feed real-world requirements back into product roadmaps\nBuild and maintain automation scripts in TCL, Perl, and Unix shell to streamline power analysis workflows and improve turnaround time for customer engagements\nCoordinate with technical account managers and worldwide account teams to shape customer strategies, drive tool adoption, and support successful project completion\nGather, refine, and track flow requirements based on customer feedback, engineering judgment, and emerging tool capabilities\nThe Impact You Will Have\nEnable semiconductor companies to meet aggressive power budgets and ship complex chips on schedule by solving power verification bottlenecks they cannot resolve alone\nInfluence the direction of Synopsys low power tools by bringing real customer pain points and use cases directly to R&D teams\nBuild repeatable, scalable low power methodologies that become the foundation for how customers verify power across multiple projects and product lines\nAccelerate customer adoption of Synopsys solutions, directly contributing to business growth and long-term account relationships in the region\nReduce customer design respins by catching power issues earlier in the flow, saving months of schedule and significant engineering cost\nEstablish yourself as a trusted technical advisor to design teams, the person they call when power verification gets hard\nShape how the next generation of AI, mobile, and automotive chips are designed by helping customers optimize power at every level of the design hierarchy\nWhat You'll Need\nBE/BTech/ME/MTech in Electronics Engineering, Computer Science, or Microelectronics with 3-5 years of hands-on industry experience in ASIC design or verification\nDeep working knowledge of low power verification including power estimation, reduction techniques, power exploration, audit, efficiency analysis, power-load models, memory power analysis, LP simulation, LP linting, and HW/emulation cycle-based power profiling and correlation\nProven experience with Synopsys low power tools such as PrimePower-RTL (logical and physical mode), SpyGlass-Power, VC LP, PTPX/PrimePower, or RTL Architect (PPA), or equivalent industry-standard LP signoff tools\nStrong command of VHDL, Verilog, and SystemVerilog RTL, and solid understanding of ASIC design flows from RTL to tapeout\nHands-on experience debugging power reports and matrices at RTL and netlist levels, and working with UPF for low power verification\nAdvanced scripting skills in TCL, Unix shell, Perl, or Python for automation, flow development, and debugging\nExperience with glitch power analysis and power correlation across RTL, gate-level, and emulation environments is a strong plus\nWho You Are\nYou can walk into a customer meeting, quickly assess where their power verification flow is breaking down, and propose a concrete next step without needing three follow-up calls\nExplaining a complex power correlation issue to a design manager or an R&D engineer feels natural to you, and you adjust your explanation depending on who is in the room\nYou are organized enough to manage multiple customer engagements at once, each with different tools, flows, and timelines, without dropping threads\nWorking across time zones, teams, and functions does not slow you down, you know how to pull the right people in at the right time and keep things moving\nYou push back when a customer request does not make technical sense, but you do it in a way that builds trust rather than friction\nDebugging a stubborn power issue for hours, even days, does not frustrate you, it is the part of the job you actually enjoy\nThe Team You'll Be Part Of\nYou will be part of the Application Engineering team supporting Synopsys' low power verification solutions across semiconductor customers in the Bengaluru region. You will work closely with R&D, product validation, technical account managers, and global AE teams to drive methodologies, solve customer problems, and enable successful project outcomes. This is a customer-facing role with deep technical collaboration across the organization.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Applications Engineering, Staff Engineer - PrimeTime", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-15", "url": "https://careers.synopsys.com/job/bengaluru/applications-engineering-staff-engineer-primetime/44408/100654734256", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent a decade or more in the trenches of silicon timing, and you know that the difference between a chip that tapes out on schedule and one that slips by three months often comes down to how well someone understands PrimeTime and can translate that knowledge into action for a stressed design team. \nYou are equally comfortable running a competitive benchmark that proves tool superiority and sitting with a customer's design team walking through setup and hold violations in their actual netlist. You do not just know the theory of process corners and signal integrity, you have lived through the messiness of real designs where nothing is clean and every decision is a tradeoff. When a customer asks a hard question, you do not deflect, you dig in, and if you do not know the answer, you know exactly who in R&D to pull in and how to frame the problem so it gets solved.\nYou think in workflows, not features. Training is not about showing slides, it is about making sure the person leaves able to do the thing. At Synopsys, you will work with the team behind the industry-leading STA tool and the customers who depend on it to ship the chips that power everything.\n\nWhat You'll Be Doing\nDrive PrimeTime adoption and usage with customers in both pre-sales evaluations and post-sales deployment, including competitive benchmarking, proof-of-concept runs, and technical win strategies\nDeliver hands-on customer training on Static Timing Analysis workflows, timing closure techniques, process variation analysis, and signal integrity debugging using PrimeTime\nProvide tape-out support for customer designs, troubleshooting timing violations, setup/hold issues, and corner-case scenarios in real production environments\nCollaborate with R&D to communicate customer requirements, report tool issues, and drive product enhancements based on field deployment feedback\nWork closely with sales, marketing, and field teams to articulate PrimeTime's technical advantages to design teams and engineering management\nDevelop and refine TCL-based automation scripts and methodologies that improve customer productivity and timing closure efficiency\nSupport customers through the full design flow, interfacing with synthesis, physical design, extraction, and ECO processes to ensure seamless PrimeTime integration\n\nThe Impact You Will Have\nAccelerate customer tape-out schedules by resolving critical timing issues and enabling faster, more confident timing closure\nExpand PrimeTime footprint and deepen usage across customer organizations through technical excellence and trusted advisory relationships\nInfluence the PrimeTime product roadmap by translating real-world customer challenges into actionable R&D priorities\nReduce customer risk and rework by delivering training and methodologies that prevent common timing pitfalls before they become schedule killers\nStrengthen Synopsys competitive position by demonstrating measurable performance, capacity, and accuracy advantages in head-to-head evaluations\nEnable design teams to adopt advanced timing analysis techniques for process variation, multi-mode multi-corner, and signal integrity that improve chip performance and yield\nBuild long-term customer partnerships where Synopsys is seen as an extension of their engineering team, not just a tool vendor\n\nWhat You'll Need\nBachelor's degree in Electrical Engineering or equivalent, with 7+ years of hands-on experience in ASIC/SoC design, timing analysis, or related fields, or Master's degree with 7+ years of experience\nDeep working knowledge of Synopsys PrimeTime, including hands-on experience running STA, analyzing timing reports, and debugging violations in real customer designs\nSolid understanding of timing corners, process variations, on-chip variation (OCV), advanced OCV (AOCV), statistical STA, and signal integrity effects on timing\nFamiliarity with the broader digital design flow, including synthesis, place and route, parasitic extraction, and ECO methodologies\nStrong TCL scripting skills for automation, flow customization, and productivity improvements\nDemonstrated ability to communicate complex technical concepts clearly to both engineering teams and management, prior customer-facing experience is a strong plus\nWillingness to travel to customer sites as needed for training, support, and technical engagements\n\nWho You Are\nYou can walk into a customer meeting with a timing report full of violations and walk out with a clear action plan that the design team trusts and can execute\nYou know when to push back on a customer request because the real problem is upstream in their methodology, and you know how to have that conversation without burning the relationship\nYou are comfortable context-switching between a competitive benchmark for a prospect, a tape-out crisis call with an existing customer, and a product enhancement discussion with R&D, all in the same week\nYou treat customer problems like they are your own, not because it is good service, but because you genuinely want to see the design succeed and you know your tool is the reason it will\nYou can explain a nuanced timing tradeoff to an engineering director in two sentences without losing the technical accuracy that matters\nYou stay current on process technology trends, design challenges, and timing methodologies because you know that what worked at 28nm does not always work at 5nm, and your customers need you to know the difference\n\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\n\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior Low Power Applications Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-15", "url": "https://careers.synopsys.com/job/bengaluru/senior-low-power-applications-engineer/44408/99658152480", "is_hardware": true, "platform": "talentbrew", "jd_text": "Alternate Job Titles\nStaff Applications Engineer, Low Power Verification\nSenior Low Power Applications Engineer\nStaff Field Applications Engineer, Power Signoff\nTechnical Applications Engineer, Low Power Solutions\nStaff Customer Solutions Engineer, Power Verification\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years deep in Low Power flows and learned that power is not just a number in a spreadsheet, it is the thing that determines whether a mobile SoC ships or gets redesigned, whether a data center chip meets its thermal envelope or fails qualification. You know the difference between power estimation that looks good in RTL and power that actually correlates when the netlist comes back from synthesis. You have debugged enough UPF intent files to spot the clock gating issue, the retention flop misconfiguration, or the power domain isolation problem before it becomes a tape-out blocker.\nYou are comfortable sitting with a customer's design team who is missing their power budget by 20% and working backward from PrimePower reports, SpyGlass violations, and simulation waveforms to find the real culprit. You do not wait for the tool to tell you what is wrong, you know where to look. You have written enough Tcl and Perl scripts to automate power audits, correlate emulation data with RTL estimates, and generate the reports that actually help designers make decisions. At Synopsys, you will work directly with semiconductor companies across the region on their highest-stakes Low Power challenges, and what you solve will determine whether their chips meet power targets and ship on time.\nWhat You'll Be Doing\nPartner with semiconductor companies across the region on Low Power verification challenges including power estimation, reduction, audit, correlation, and signoff\nDeploy and support Synopsys Low Power tools including PrimePower-RTL, SpyGlass-Power, VC LP, PTPX, and RTL Architect for customer projects from methodology setup through tapeout\nWork directly with customer design and verification teams to debug power reports, resolve UPF issues, and optimize flows for PPA (Performance, Power, Area) targets\nCollaborate with Synopsys R&D and product validation teams to develop methodologies that solve real customer problems and drive product improvements based on deployment feedback\nLead technical engagements with customers to establish end-to-end Low Power flows including power exploration, memory power analysis, glitch analysis, and emulation-based power profiling\nDevelop automation scripts in Tcl, Perl, and Unix Shell to streamline power analysis, correlation workflows, and reporting for customer deployments\nCoordinate with technical account managers and global AE teams to form strategies that drive adoption of Synopsys Low Power solutions and enable customer project success\nThe Impact You Will Have\nEnable customers to meet aggressive power budgets and ship complex SoCs on schedule by deploying robust Low Power verification and signoff flows\nReduce power-related respins and late-stage design changes that cost customers months of schedule and millions in engineering effort\nDrive adoption of industry-leading Low Power methodologies across the region's semiconductor ecosystem, from mobile and automotive to data center and AI chips\nShape the Low Power product roadmap by surfacing real customer pain points, correlation gaps, and methodology challenges that R&D needs to address\nBuild long-term technical relationships with design teams that make Synopsys the trusted partner for their most critical power challenges\nAccelerate time-to-market for customers by helping them catch power issues at RTL before they become netlist-level crises\nStrengthen Synopsys' competitive position in Low Power by proving out flows, winning evaluations, and demonstrating measurable power reduction and correlation accuracy\nWhat You'll Need\nBachelor's or Master's degree in Electronics Engineering, Computer Science, or Microelectronics with 5+ years of industry experience in Low Power design or applications engineering\nDeep hands-on experience with end-to-end Low Power flows and LP signoff, including power estimation, reduction, audit, and correlation\nProven working knowledge of Synopsys Low Power tools such as PrimePower-RTL (logical and physical modes), SpyGlass-Power, VC LP, PTPX, or RTL Architect\nStrong expertise in UPF-based Low Power verification, power domain analysis, retention strategies, isolation cells, and power state management\nSolid understanding of PPA challenges and analysis, including memory power, glitch power, and emulation-based cycle-accurate power profiling\nAdvanced scripting skills in Tcl, Perl, and Unix Shell for automation, debugging, and custom flow development\nExceptional knowledge of Verilog, VHDL, SystemVerilog RTL, and ASIC design flows from RTL through netlist-level power signoff\nWho You Are\nYou can look at a power report with 10,000 instances and immediately know which three things are driving the problem\nComfortable explaining to a customer why their RTL power estimate does not match their gate-level numbers and what to fix in their UPF to close the gap\nYou manage multiple customer engagements across different companies and project stages without losing track of what is blocking each one\nSelf-directed enough to own a Low Power deployment from kickoff through signoff without waiting for someone to tell you the next step\nYou build relationships with customer design leads and R&D engineers that last beyond a single project, becoming their go-to expert when power gets hard\nOpen to travel across the region for onsite customer engagements, methodology workshops, and technical deep dives when it moves the work forward\nThe Team You'll Be Part Of\nYou will join the regional Applications Engineering team supporting semiconductor companies across the area on their most complex Low Power verification and signoff challenges. This team works closely with global AE experts, R&D, product validation, and technical account managers to deliver end-to-end solutions that drive customer success and business growth. Your recruiter will share more about team structure, coverage model, and collaboration dynamics during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Validation/Characterization Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-15", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25017910", "is_hardware": true, "platform": "oracle", "jd_text": "The DLP Systems Validation team is looking for a highly skilled Validation Engineer to join our team. This role sits at the intersection of physical hardware and intelligent software, requiring a candidate who is equally comfortable with a probe in hand and a Python IDE. You will be responsible for the end-to-end validation of complex systems, ensuring that both the underlying hardware architecture and the high-level software/AI algorithms perform harmoniously. In this role the candidate will be exposed to wide range of DLP products, end user applications and its complexities to develop test capabilities, debug and resolve system level issues prior to releasing products leading to successful customer launch. If you are interested, please send me your resume.\n\nQualifications\nMinimum requirements:\n\nBachelor’s degree in electrical engineering or related field of study\n\nMinimum of 2+ years of experience\n\nBroad system level knowledge, video/imaging operations and industry standard video and hardware interfaces.\n\nSoftware/Test development with Python\n\nKnowledge of lab equipment (signal generators, analyzers, scopes etc.)\n\nExperience in complex systems with extensive embedded software, PC applications and electrical interfaces.\n\nGood verbal and written communication skills.\n\nSelf-motivated strong team member in a collaborative, cross-functional environment with limited supervision.\n\nPreferred qualifications:\n\nAbility to utilize Python-based AI frameworks (such as TensorFlow, PyTorch, or NumPy) to analyze test data or facilitate model-based validation.\n\nExperience validating AI/ML models deployed on edge hardware, ensuring accuracy and performance within constrained hardware environments.\n\nExperience with schematic capture, board design, and PCB layout\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Sr Principal Digital Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-09-15", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506601", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Sr. Principal Digital design, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products, LED drivers, SiC drivers, smart-Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following: \n\n \n\nWork with different product lines for SoC RTL implementation of power driver digital controls for LED/SiC/smartFET/Efuse application, peripherals like I2C, SPI, LIN, CAN protocols \n\nThe candidate will work on digital design architecture, digital RTL, low power design, synthesis and timing analysis with PD engg, Physical Design (PD) interface for the power management chips \n\nThe candidate will be able to work as part of a large and focused team of engineers and will be able to collaborate successfully as needed with design architects, digital verification, project management, and digital and analog design teams in multiple worldwide geographies\n\nDefine and implement micro-architecture to RTL implementation with the refining of features requirements throughout the design process\n\nSupport the bring-up of various features at a system level in various pre-silicon platforms like SOCV, Emulation, FPGA.\n\nOwn technical outcome of design, verification, implementation, and execution of Power Management ICs with complexities that can span from simple regulators to complex designs, control loops, and digital interfaces  \n\nUnderstand project goals, execute with realistic schedule, report status of progress  and understand clarity of project details and milestones \n\nLead and support Customer issues, Production issues, FW and System development, Failure Analysis\n\nSupport post-silicon validation activities for your designs.\n\n#LI-RT1\n\n   \n\nResponsibilities for Internal Candidates\n \n\n     \n\nOnSemi is seeking a Sr. Principal Digital design, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products, LED drivers, SiC drivers, smart-Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following: \n\n \n\nWork with different product lines for SoC RTL implementation of power driver digital controls for LED/SiC/smartFET/Efuse application, peripherals like I2C, SPI, LIN, CAN protocols \n\nThe candidate will work on digital design architecture, digital RTL, low power design, synthesis and timing analysis with PD engg, Physical Design (PD) interface for the power management chips \n\nThe candidate will be able to work as part of a large and focused team of engineers and will be able to collaborate successfully as needed with design architects, digital verification, project management, and digital and analog design teams in multiple worldwide geographies\n\nDefine and implement micro-architecture to RTL implementation with the refining of features requirements throughout the design process\n\nSupport the bring-up of various features at a system level in various pre-silicon platforms like SOCV, Emulation, FPGA.\n\nOwn technical outcome of design, verification, implementation, and execution of Power Management ICs with complexities that can span from simple regulators to complex designs, control loops, and digital interfaces  \n\nUnderstand project goals, execute with realistic schedule, report status of progress  and understand clarity of project details and milestones \n\nLead and support Customer issues, Production issues, FW and System development, Failure Analysis\n\nSupport post-silicon validation activities for your designs.\n\n#LI-RT1\n\n   \n\nQualifications for Internal Candidates\n\nResponsibilities\nBS in Electrical Engineering or related + 14 years of experience, or MS + 12 years of experience in defining and implementing Digital Design, Architecture/u-Architectures and ASIC/Mixed signal SoC chip developments\n\nThe ideal candidate should have thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status\n\nSolid understanding of RTL design, CDC, synthesis, timing analysis and CDC, UPF and system Verilog (assertion)\n\nSolid understanding of Verilog, TCL and Perl/Python/XML programming languages\n\nExperience in developing ASIC/Mixed signal ICs for various Power chips like LED/SiC/GAN drivers, SmartFET and Efuses. \n\nUnderstanding of digital architecture trade-offs for power, performance, and area\n\nSolid track record of releasing complex ICs/ IPs to market \n\nGoal and outcome-focused with the ability to handle multiple projects within the team \n\nAbility to clearly articulate issues, challenges, and concerns to all levels of management \n\nMust have good written and verbal cross-functional communication skills\n\nExperience with microprocessor interconnects and integrating peripherals into the interconnect\n\n#LI-RT1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Electrical Engineer", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2026-09-15", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/Electrical-Engineer_R2628146-1", "is_hardware": true, "platform": "workday", "jd_text": "Who We Are\n\nApplied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI and accelerating the commercialization of next-generation semiconductor chips. Join us and push the boundaries of materials science and engineering in a company at the foundation of the electronics industry. The work we do together advances the world’s technology.\n\nWhat We Offer\n\nLocation:\nBangalore,IND\nYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. \n\nAt Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. \n \n \nAs an Electrical Engineer, you are responsible for designing, modifying, and troubleshooting electrical or electronic engineering assemblies, layouts, schematics, and drawings to advance the equipment that supports our technology. Using your technical experience and critical thinking skills, you will perform engineering analysis, generate test reports, develop innovative solutions, and create documentation for product releases. You will also coordinate the procurement and assembly of components, identify sources of critical parts, and resolve technical issues to ensure peak performance. \n \nRole Responsibilities: \nDesign or modify electrical or electronic engineering assemblies, layouts, schematics, drawings, or specifications of difficult scope \n\nIdentify and troubleshoot a variety of complex electrical problems with limited supervision \n\nDefine, coordinate, perform and generate engineering test reports with limited supervision \n\nPerform engineering analysis of difficult scope with limited supervision \n\nTechnically lead or execute engineering projects, including the development of key suppliers \n\nImplement concepts for a variety of complex product issues and electrical solutions of difficult scope \n\nGenerate electrical product specifications; specify and review engineering documentation \n\nServe as a resource for junior colleagues; lead project teams, as needed\n\nClearly communicate difficult or sensitive information; build consensus \n\nMinimum Qualifications: \nBachelor’s degree\n\n4-7 years of experience in a related field\n\nPreferred Qualifications: \nStrong knowledge of industry best practices, key business drivers, competition in the marketplace, and how your area of expertise integrates with others  \n\nDemonstrated leadership skills to lead small projects as needed  \n\nSystem Level Design and End to End Responsibility\n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nAssignee / Regular\nTravel:\nYes, 10% of the Time\nRelocation Eligible:\nYes\n\nApplied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "Test Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-15", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25017901", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n This is a unique opportunity to be part of a team that drives testing of highly integrated multi-rail power management devices going into markets with significant growth potential. The ideal candidate would have a background that includes probe and final test development of complex mixed signal circuits.\n\nResponsibilities include:\n\nWork with design team to understand design specifications\n\nGenerate test plan, create test and char program, design ATE hardware interface boards\n\nDebug characterizing silicon on ATE, correlate results with bench data\n\nAnalyze silicon results, supporting failure analysis tasks\n\nPerform statistical analysis of yield fallout, debug and fix yield issues; optimize test time\n\nWork with production team to release products to volume production\n\nTest strategy definition and implementation for new DCDC converter products\n\nATE (Automatic Test Equipment) test hardware and software\n\nSilicon qualification& characterization including qual hardware development\n\nComprehensive device debugging, design validation and failure analysis\n\nDrive for robust and cost effective test solutions while being accountable for product quality\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in Electrical Engineering\n\nXX years of relevant experience\n\nATE experience on Teradyne Eagle or equivalent analog ATE (iFlex, LTX, VLCT), although Eagle experience is preferred and is a differentiator\n\nCharacterization test program and hardware development experience, Production test program and hardware development experience\n\nStrong technical knowledge of electronic devices and circuits, and Analog test techniques\n\nData analysis skills using Spotfire, dataPower or equivalent tool based on STDF\n\nExperienced with various lab equipment such as scopes, power supplies, sourcemeters, loads etc.\n\nExperience with product engineering activities such as yield improvement and test time reduction\n\nStrong understanding of the IC product development process, from concept to volume production\n\nPreferred qualifications:\n\nMixed signal test techniques and experience with developing mixed-signal tests on TI roadmap testers\n\nExperienced with test program and hardware offload to TI offshore manufacturing sites\n\nProficiency in programming/scripting in C++, Python, C#\n\nLabview, Teststand experience\n\nRevision control tools experience : Subversion, Git\n\nDemonstrated strong analytical and problem solving skills\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nStrong time management skills that enable on-time project delivery\n\nDemonstrated ability to build strong, influential relationships\n\nAbility to work effectively in a fast-paced and rapidly changing environment\n\nAbility to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Lead Verification Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-09-15", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Verification-Engineer_R56064", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Description: AI Design Validation Specialist (Verification / Workflow SME)\nRole Overview\nWe are seeking an experienced AI EDA Specialist (Verification / Workflow SME) to bridge the gap between semiconductor verification methodologies and AI-driven automation. This role will serve as the domain expert responsible for validating AI-generated verification artifacts, debugging customer verification challenges, developing ground-truth datasets, and ensuring AI solutions align with industry-standard verification workflows.\nThe ideal candidate combines deep expertise in SystemVerilog, UVM, simulation, and formal verification with a passion for enabling next-generation AI-powered engineering solutions.\nKey Responsibilities\nVerification Workflow Validation\nValidate AI-generated outputs across RTL verification workflows.\nReview and assessment generated:UVM testbenches\nAssertions (SVA)\nCoverage strategies\nSimulation and formal verification flows\n\nEnsure compliance with industry-standard verification methodologies and best practices.\nCustomer Technical Support & Debugging\nInvestigate and resolve customer-reported issues involving:UVM environments\nRTL verification testbenches\nFunctional coverage\nAssertion failures\nSimulation regressions\n\nReproduce, analyze, and document root causes of complex verification problems.\nPartner closely with customers, application engineers, and product teams to drive issue resolution.\nGround Truth & Benchmark Development\nDevelop and maintain benchmark verification datasets and golden reference test cases.\nEstablish correctness criteria for evaluating AI-generated verification artifacts.\nBuild validation suites for model qualification and regression testing.\nAI Model Enablement\nCollaborate with AI/LLM engineers to improve accuracy and verification relevance of AI-generated outputs.\nReview model responses and provide feedback for fine-tuning and evaluation.\nTranslate semiconductor verification workflows into structured AI evaluation scenarios.\nHelp reduce hallucinations and improve technical correctness of AI-assisted verification solutions.\nEDA Workflow Integration\nValidate interoperability between AI systems and industry-standard EDA tools.\nSupport workflow automation across:Simulation\nRegression management\nCoverage analysis\nFormal verification\n\nIdentify opportunities to improve verification productivity through AI-assisted automation.\nRequired Qualifications\nEducation\nBachelor's or Master's degree in:Electrical Engineering\nComputer Engineering\nComputer Science\nRelated technical discipline\n\nExperience\n6–10 years of experience in semiconductor verification.\nProven experience developing and debugging complex UVM-based verification environments.\nHands-on experience with RTL, IP, subsystem, or SoC verification projects.\n\nTechnical Skills\nVerification Expertise\nStrong knowledge of:SystemVerilog\nUVM\nRTL Verification\nFunctional Coverage\nCode Coverage\nAssertion-Based Verification (SVA)\nConstrained Random Methodologies\n\nDebug & Analysis\nExpertise debugging:Simulation failures\nAssertion violations\nCoverage gaps\nVerification regressions\nComplex multi-component testbenches\n\nEDA Tools\nExperience with one or more of the following:\nCadence Xcelium\nSynopsys VCS\nSiemens QuestaSim\nCadence JasperGold\nSynopsys VC Formal\nVerification management and regression platforms\nAutomation Skills\nPython\nShell scripting\nTCL scripting\nWorkflow automation and test framework development\nPreferred Qualifications\nExperience supporting customers or field engineering organizations.\nFamiliarity with AI, LLMs, or AI-assisted EDA workflows.\nExperience developing verification automation frameworks.\nKnowledge of agentic AI systems and evaluation methodologies.\nExposure to semiconductor EDA product development or application engineering.\nKey Competencies\nDeep semiconductor verification expertise.\nStrong analytical and problem-solving skills.\nAbility to translate AI outputs into technically correct verification solutions.\nExcellent communication and customer interaction skills.\nCross-functional collaboration across engineering, AI, product, and customer teams.\nPassion for driving innovation through AI-enabled verification technologies.\nSuccess Metrics\nAI-generated verification accuracy against ground-truth benchmarks.\nReduction in customer issue resolution time.\nImprovement in workflow validation pass rates.\nReduction in AI-generated verification errors and hallucinations.\nGrowth of validated benchmark datasets and test suites.\nImproved customer productivity and adoption of AI-assisted verification workflows.\nRole Impact: This role serves as the semiconductor verification authority responsible for ensuring AI-generated verification outputs are technically accurate, workflow-compliant, and production-ready for deployment across customer environments.\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Staff Formal Verification Engineer", "company": "SiFive", "location": "Hyderabad, India", "date_posted": "2026-09-15", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Hyderabad-India/Staff-Formal-Verification-Engineer_R-101481", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nSummary\n\nAs a Staff Hardware Engineer in Formal Verification, you will own verification strategy and execution for complex out‑of‑order (OOO) processor Blocks which are complex and can prove in formally. Experience in understanding OOO processors, vector execution engines etc is a value added.\n\nResponsibilities:\n• Identify blocks suitable for applying Formal Verification\n• Create Formal Test-plan for blocks identifying properties to be implemented and sign-off metrics\n• Implementation and maintenance of Formal Verification environments in Chisel\n• Applying various FV techniques to reduce complexity and prove correctness of DUT\n• Debugging RTL to identify causes of failure scenarios\n• Guide and train team members on effective usage of Formal Verification tools\n• Develop/modify scripts to automate the verification process\n• Review formal setups and proofs with design and verification teams\n• Maintain and extend assertion libraries\n\nRequirements:\n7+ years of experience in Formal Verification of Digital Hardware Design with a Bachelor's or Master's in Engineering\nExtensive experience with Formal Abstraction Techniques and sign-off process\nFamiliarity with industry-standard Formal Verification Tools, such as VC Formal, JasperGold\nKnowledge of Hardware Description and Verification Languages, such as VHDL, Verilog/ SystemVerilog\nKnowledge of Object-oriented Programming is a plus\nA keen interest in Processors and Digital systems\nStrong reasoning skills and excellent attention to detail\nGood inter-personal and teamwork skills!\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Principal Design Engineer - ( Synthesis/LEC/CLP )", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-09-15", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Design-Engineer-----Synthesis-LEC-CLP--_R56396", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\n\nCadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.\nThe Cadence Advantage\nThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.\nCadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.\nThe unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success.\nMultiple avenues of learning and development available for employees to explore as per their specific requirement and interests.\nYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.\n\nLocation: Pune/Bangalore\nExperience: 8–12 Years\nBE/BTech/ME/MS/MTech in Electrical/Electronic or equivalent\nAbout the Role\nWe are looking for a Principal Design Engineer to drive Synthesis, Logical Equivalence Checking (LEC), Conformal Low Power (CLP), and UPF/CPF-based power intent verification. This is an internally facing role contributing to flow methodology & root-cause resolution on synthesis, Logical Equivalence Checking (LEC), low-power sign-off.\nKey Responsibilities\nDrive methodology improvements and best-practice development across Synthesis, LEC, CLP and ECO flows.\nOwn end-to-end LEC sign-off across multiple design blocks including debug of NEQs, aborts.\nDrive Physical synthesis closure on complex blocks including constraint development and PPA closure.\nCLP sign-off for low power intent designs: level shifter, retention, isolation, PSO strategy architecture, supply set/domain conflict resolution.\nOwn technical documentation, status tracking, and write-ups across active blocks.\nRequired Skills\n8–12 years of hands-on ASIC/SoC design experience with strong depth in Synthesis (Genus), LEC (Conformal), and Low Power.\nProven experience across multi-corner, multi-mode sign-off considerations\nStrong scripting ability in TCL, Python, PERL etc.\nDeep understanding of ASIC flow interactions: RTL, synthesis, physical design handoff, DFT.\nExcellent written and verbal communication skills; comfortable owning technical documentation and cross-team discussions\nProven track record and experience working in a fast-paced environment.\n\nPreferred\nExperience with physically aware synthesis flows\n\nRegards\nK Madhu Prasad\nkmadhup@cadence.com\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "FVCTO - Formal Verification Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-15", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/FVCTO---Formal-Verification-Engineer_JR0287033", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nConducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms.\n\nCreates comprehensive formal verification test and coverage plans including definition of formal verification scope, strategy, and techniques.\n\nCreates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques.\n\nDevelops formal proofs to implement the verification plan, reviews the completed proofs, and develops new formal verification methodologies.\n\nPerforms convergence on design by creating formal verification methodology, abstraction, and simulation techniques.\n\nFinds and implements corrective measures to resolve failing tests.\n\nCollaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.\n\nDocuments test plans and drive technical reviews of plans and proofs with design and architecture teams.\n\nMaintains and improves existing functional verification infrastructure and methodology.\n\nUnderstands the binary decision diagram (BDD) and data flow graph (DFG) for data paths and resolves the BDD complexity on arithmetic.\n\nApplies understanding of modeling architecture to simplify and model the problem and uses tools to formally prove protocols and architectures.\n\nQualifications:\nMinimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.\nMinimum Qualifications: 2-18 years of experience in formal verification\n\nPreferred Qualifications: • BTech/MTech in Electronics, Electrical or CS\n\nRequirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Senior Hardware Development Engineer", "company": "Nokia", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-09-15", "url": "https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/40378", "is_hardware": true, "platform": "oracle", "jd_text": "The Senior Hardware Development Engineer will be a key member of our team, responsible for designing and developing high-performance hardware solutions. With a focus on board design, testing, and debugging, this role requires a strong understanding of EDA tools and hands-on experience in lab activities. The successful candidate will have the opportunity to work on innovative projects and contribute to the development of cutting-edge technology.\n\nNILightpath\n\nResponsibilities\nDesign and develop high-performance hardware solutions for our products.\n\nLead the board design process, ensuring optimal performance and functionality.\n\nConduct thorough testing and debugging of hardware components and systems.\n\nCollaborate with cross-functional teams, including software engineers and product managers, to ensure seamless integration.\n\nStay updated with the latest industry trends and technologies, and propose innovative solutions.\n\nDocument and maintain design specifications and test plans.\n\nProvide technical support and guidance to junior team members.\n\nEnsure compliance with quality standards and industry regulations.\n\nParticipate in project planning and provide accurate estimates for hardware development tasks.\n\nQualifications\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.\n6+ years of experience in high-board design, testing, and debugging.\nProficiency in EDA tools and hands-on experience in lab activities.\nStrong knowledge of hardware design principles and best practices.\nExperience with hardware debugging and troubleshooting techniques.\nFamiliarity with industry-standard design tools and simulation software.\nExcellent problem-solving and analytical skills.\nAbility to work independently and manage multiple projects simultaneously.\nEffective communication and collaboration skills.\nWillingness to learn and adapt to new technologies and industry trends.\n\nAbout the company\nAdvancing connectivity to secure a brighter world.\n\nNokia is a global leader in connectivity for the AI era. With expertise across fixed, mobile and transport networks, powered by the innovation of Nokia Bell Labs, we’re advancing connectivity to secure a brighter world. \n\nLearn more about life at Nokia.\n\nOur recruitment process\n\nWe act inclusively and respect the uniqueness of people. Our employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.\n\nIf you’re interested in this role but don’t meet every listed requirement, we still encourage you to apply. Unique backgrounds, perspectives, and experiences enrich our teams, and you may be just the right candidate for this or another opportunity.\n\nThe length of the recruitment process may vary depending on the specific role's requirements. We strive to ensure a smooth and inclusive experience for all candidates. Discover more about the recruitment process at Nokia.\n\nAbout the organization\nSome of our benefits in India:\n\nFlexible and hybrid working arrangements to support work–life balance\n\nHealth and well-being support – medical insurance for you and your family, health check-ups, life and accident insurance, well-being programs, and employee resource groups \n\nA minimum of 90 days of Maternity and Paternity Leave based on eligibility\n\nPersonal Support Service 24/7 – a confidential support channel open to all Nokia employees and their families in challenging situations\n\nCareer growth & mobility – technical career paths, job rotations, international assignments, and relocation support\n\nContinuous learning – technical certifications, mentoring programs, coaching, and digital learning platforms\n\nOpportunities to innovate and contribute through Nokia’s research and development environment\n\nRecognition programs that celebrate outstanding contributions\n\nWorkplace support – ergonomic working support and mobile device programs based on eligibility", "jd_status": "stored"}, {"title": "Design Engineer I ( Synthesis/LEC/CLP )", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-09-15", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Design-Engineer-I---Synthesis-LEC-CLP--_R56394", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\n\nCadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.\nThe Cadence Advantage\nThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.\nCadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.\nThe unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success.\nMultiple avenues of learning and development available for employees to explore as per their specific requirement and interests.\nYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.\nLocation: Bangalore / Pune\nExperience: 0–2 Years\nBE/BTech/ME/MS/MTech in Electrical/Electronic or equivalent\nAbout the Role\nWe are looking for a Design Engineer to join our synthesis/LEC/CLP team, supporting execution-level tasks across the ASIC design flow. This is a strong opportunity for an engineer early in their career to build deep expertise in synthesis, Logical equivalence checking and low-power design.\n\nKey Responsibilities\nAssist in running and monitoring Logical Equivalence Checking (LEC), Logic Synthesis, and Conformal Low Power jobs across design blocks\nSupport constraint reviews, generation, and basic debug\nHelp track and document LEC & synthesis status across blocks.\nLearn and apply power intent basics to support CLP sign-off tasks\nSupport ECO script writing and basic scripting tasks (Tcl/Perl/Python)\nMaintain clean documentation of runs, issues, and findings.\n\nRequired Skills\n0–2 years of experience: internship or academic project experience with ASIC flows is a plus\nBachelor's/master’s degree in Electronics, Electrical Engineering\nBasic understanding of the complete ASIC design flow.\nBasic scripting skills (Python, Perl, Tcl, or Unix shell)\nStrong analytical and problem-solving skills; eager to learn EDA tool flows\nGood communication skills and ability to work well in a team\n\nPreferred\nExposure to Cadence tools (Genus, Conformal) through coursework or internship\nBasic understanding of digital logic design and computer architecture\n\nRegards\nK Madhu Prasad\nkmadhup@cadence.com\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "System Validation Engineer (New Grads)", "company": "SiFive", "location": "Hsinchu, Taiwan", "date_posted": "2026-09-14", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Hsinchu-Taiwan/System-Validation-Engineer--New-Grads-_R-101316", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nThe Role:\nThe successful candidate will join SiFive's System Validation team, which is responsible for the validation of SiFive's RISC-V CPUs utilizing FPGA-based platforms. This role extends beyond FPGA platforms to include development and bring-up boards.\nThis position offers significant exposure to RISC-V processors, the RISC-V software ecosystem, and various development boards, providing exceptional learning opportunities for engineers pursuing a career in the RISC-V domain.\n\nResponsibilities\nExecute root cause and failure analysis across RISC-V CPU hardware and software components.\nUtilize ILA and JTAG debuggers to troubleshoot and validate FPGA designs.\nDevelop failure hypotheses through systematic, step-by-step elimination of potential causes.\nCreate and support Python-based scripts to enhance and automate debug workflows.\n\nRequirements\nA Bachelor’s or Master’s degree in Computer Science or Electronics and Communication Engineering is required.\nA strong comprehension of Computer Architecture and logic design is essential.\nPrior exposure to logic design using Verilog and the subsequent porting of designs onto FPGA platforms is necessary.\nPractical experience with Linux-based operating systems and scripting languages such as Python and BASH is mandatory.\nCandidates must possess a positive attitude, a proactive approach to continuous learning, and a commitment to achieving excellence in their work.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nTaiwan\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Solution Validation Engineer", "company": "Lattice", "location": "Shanghai, China", "date_posted": "2026-09-14", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Shanghai-China/Solution-Validation-Engineer_R-103285", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\n\nThis position will focus on the validation of systems and software related to Lattice system solutions, and the development and optimization of automation test platform for different projects.\n\nAccountabilities: \nConduct system verification, design and execute validation plans to ensure system solutions meet quality standards and required specifications.\n\nPerform embedded software validation, covering core modules such as drivers and firmware; identify issues through testing, drive optimization, and ensure software stability and reliability.\n\nExecute testing processes for software development tools, including but not limited to Propel SDK, Builder, and solution tools, to verify the functional integrity and usability of the tools.\n\nProactively collaborate with development and validation teams, sync validation issues, and work together to promote the implementation of system/software validation work.\n\n负责系统验证工作，设计并执行验证方案，确保系统解决方案符合质量标准与需求规格。\n\n开展嵌入式软件验证，覆盖驱动程序、固件等核心模块，通过测试发现问题并推动优化，保障软件稳定性与可靠性。\n\n执行软件开发工具的测试流程，包括但不限于 Propel SDK、Builder 及解决方案工具，验证工具功能完整性与易用性。\n\n主动与开发、验证等多团队协作，同步验证问题，协同推进系统 / 软件验证工作落地。\n\n \nRequired Skills:\nBachelor's or Master's degree in CS / EE or equivalent.\n\n3+ years of experience in Embedded System/SW automation test development.\n\nProficient in Python and C language, with a solid foundation in programming.\n\nProficient in AI programming tools (such as GitHub Copilot, Cursor, Claude, etc.) to improve coding efficiency will be given priority.\n\nFamiliar with the operation and basic configuration of Windows and Linux operating systems.\n\nPossess good English communication skills in both written and spoken forms.\n\nHave strong teamwork awareness, along with the ability to independently analyze and solve problems and efficiently promote task implementation.\n\n本科或硕士研究生学历，计算机，通信系统相关专业\n\n3年以上嵌入式系统自动化测试开发经验\n\n熟练掌握Python与C 语言，具备扎实的编程基础\n\n能够使用 AI 编程工具（GitHub Copilot，Cursor，Claude等）提升编码效率者优先\n\n熟悉Windows 和 Linux 操作系统的使用与基础配置。\n\n具备良好的英文书面与口头沟通能力\n\n拥有优秀的团队合作意识，同时具备独立分析问题、解决问题的能力，能高效推进任务落地\n\n#LI-DNP\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nChinaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "DFT Manager", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-09-14", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/DFT-Manager_R027037-2", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nDFT manager is expected to manage and technically guide a high-performing DFT team focused on various ASIC engagements. DFT manager shall also be required to execute certain DFT critical tasks. As a part of the profile, DFT manager shall  define chip-level testing plans, including Scan, MBIST, IO/IP tests.\nShould be able to Collaborate with physical design, verification, and manufacturing teams on optimal DFT architectures.  Work with Automated Test Equipment (ATE) post-silicon to achieve test coverage, root cause  failures and improve manufacturing yield.\nCandidate is required to be proficient with industry tools like Siemens Tessent, Synopsys TestMAX, and SpyGlass DFT.\n\nBachelors along with 12+ years of related experience or Masters degree along with 10+ years of related experience would be needed.\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Architect - GPU Performance", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-09-14", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Architect---GPU-Performance_JR2025445", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to seek, which only we can pursue, and which matter to the world. This is our life’s work: to amplify human inventiveness and intelligence.\n\nNVIDIA is now driving innovation at the intersection of visual processing, high performance computing and artificial intelligence. We are looking for passionate, highly motivated, creative  engineers to be part of our HW architecture team. As part of this team, you would be working on projects that will help make our next generation visual computing, automotive, GPU, HPC  systems better. You will get to work on high performance CPU and Memory sub-systems, Next-Gen GPUs , NOC based Interconnect Fabric etc. Make the choice to join us today.\n \nWhat you'll be doing:\nSystem level performance analysis/ bottleneck analysis of complex, high performance GPUs and System-on-Chips (SoCs).\n\nWork on hardware models of different levels of abstraction, including performance models, RTL test benches ,emulators and silicon to analyze performance and find performance bottlenecks in the system.\n\nUnderstand key performance use-cases of the product. Develop  workloads and test suits targeting graphics, machine learning, automotive, video, compute vision applications running on these products.\n\nWork closely with the architecture and design teams to explore architecture trade-offs related to system performance, area, and power consumption.\n\nDevelop required infrastructure including performance models, testbench components, performance analysis and visualization tools.\n\nDrive methodologies for improving turnaround time, finding representative data-sets and enabling performance analysis early in the product development cycle.\n\n \nWhat we need to see:\nBE/BTech, or MS/MTech in relevant area, PhD is a plus, or equivalent experience.\n\n3+ years of experience with exposure to performance analysis and complex system on chip and/or GPU architectures.\n\nStrong understanding of System-on-Chip (SoC) architecture, graphics pipeline, memory subsystem architecture and Network-on-Chip (NoC)/Interconnect architecture.\n\nExpert hands on competence in programming (C/C++) and scripting (Perl/Python). Exposure to Verilog/System Verilog, SystemC/TLM is a strong plus.\n\nStrong debugging and analysis (including data and statistical analysis) skills, including use for RTL dumps to debug failures.\n\nHands on experience developing performance simulators, cycle accurate/approximate models for pre-silicon performance analysis is a strong plus.\n\n \nNVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative, autonomous and love a challenge, we want to hear from you. Come, join our Deep Learning Automotive team and help build the real-time, cost-effective computing platform driving our success in this exciting and quickly growing field. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "ASIC Digital Design, Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-14", "url": "https://careers.synopsys.com/job/bengaluru/asic-digital-design-staff-engineer/44408/100624923904", "is_hardware": true, "platform": "talentbrew", "jd_text": "ASIC Digital Design, Staff\n\nWe Are:\n At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence—from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to help transform the future through continuous technological innovation.\n\nYou Are:\n You are a Staff ASIC Digital Design Engineer who owns a PCIe subsystem end to end. You turn architecture into solid micro-architecture and production RTL, and you are the technical owner for that area across configurations, reviews, and debug.\nYou have substantial experience designing complex high-speed interface IP in RTL. You know PCIe well—or you have done equivalent work on CXL, AMBA, DDR, UCIe, or similar protocols. You work across clocking, resets, flow control and low power, and making parameterized RTL maintainable.\nYou can mentor senior and junior designers through reviews and guidance, and you drive issues to closure with verification, formal, and physical design. \n\nWhat You'll Be Doing:\nOwn RTL and micro-architecture for one or more PCIe controller subsystems or major features (block through subsystem integration).\nWrite design specs, implement production RTL, and drive your area through verification, synthesis/timing closure support, and design convergence.\nResolve complex design and debug issues in your domain; escalate architecture trade-offs with clear options.\nParticipate in and lead design reviews; enforce coding standards, CDC/RDC, and quality for your code.\nCollaborate with verification, formal, emulation, and physical design to close bugs and integration issues.\nSupport post-silicon and customer debug for your area.\nMentor Senior and junior engineers; grow toward broader architectural influence.\nCommunicate status, risks, and dependencies for your subsystem.\nThe Impact You Will Have:\nDeliver robust, high-quality PCIe subsystem RTL that scales across products and configurations.\nDrive code quality and features in your area.\nAccelerate team execution by being a reliable technical owner and mentor.\nContribute to silicon-proven PCIe IP for commercial, enterprise, and automotive customers.\nWhat You'll Need:\nBSEE with 8+ years of relevant experience, or MSEE with 6+ years.\nProven ownership of complex ASIC RTL (subsystem or large block), from spec through tapeout or IP release.\nStrong experience in PCIe digital design, or a similar high-speed protocol (CXL, AMBA interconnect, DDR controller, UCIe, Ethernet MAC, or equivalent) \nProven on ASIC fundamentals: synthesizable RTL, clocking, CDC/RDC, resets, low power, and DFT awareness.\nAbility to define micro-architecture for the area you own and work from architecture specs.\nExperience with parameterized / configurable IP is a strong plus.\nScripting (Python, TCL, Perl) desirable. AI-assisted design tools a plus.\nWho You Are:\nA subsystem owner \nHands-on in RTL and precise in reviews.\nCollaborative with DV and PD; you close the loop and make the difference.\nA mentor to other designer, with ability to ensure code quality.", "jd_status": "stored"}, {"title": "ASIC Digital Design, Principal Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-14", "url": "https://careers.synopsys.com/job/bengaluru/asic-digital-design-principal-engineer/44408/100624923888", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:\n At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence—from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to help transform the future through continuous technological innovation.\n\nYou Are:\n You are a Principal ASIC Digital Design Engineer and a recognized PCIe technical authority. You set architecture and write and review RTL. You define micro-architecture, make trade-offs across performance, power, area, and configurability, and stay in the design until the IP is silicon-proven.\nYou have shipped complex, highly parameterized high-speed interface IP. You are fluent in PCIe (Gen5/Gen6/Gen7) digital design—transaction layer, data path, link/controller functions, RAS, and power management—and you have working knowledge of adjacent protocols such as CXL, AMBA, DDR, or UCIe.\nYou lead through architecture, design reviews, and direct technical engagement. You mentor senior and staff engineers, resolve complex issues, and represent the design in reviews with verification, physical design, customers, and senior management.\n\nWhat You'll Be Doing:\nOwn PCIe digital architecture and RTL for major controller subsystems, from micro-architecture through design convergence and post-silicon support.\nDefine micro-architecture, design specifications, and implementation approach for high-performance, low-power, scalable, configurable PCIe IP.\nMake and document key design decisions; act as the go-to authority for protocol, data-path, clocking/reset, and RAS issues.\nHands-on RTL development: implement critical paths, review detailed design, and drive complex debug (simulation, formal, emulation, and silicon).\nRaise design quality bar through reviews, coding standards, CDC/RDC discipline, and RTL maintainability across a large parameterized codebase.\nWork with verification, formal, emulation, physical design, firmware, and system teams to get IP integrated and silicon-successful.\nInfluence PCIe IP technical strategy, roadmap, and next-generation architecture, including CXL and automotive variants.\nCommunicate status, technical risk, and trade-offs to senior management, architects, and customers.\nThe Impact You Will Have:\nDeliver industry-leading PCIe digital IP used by leading commercial, enterprise, and automotive customers.\nImprove architectural quality, predictability, and execution on current and next-generation cores.\nRaise the technical bar across the design team through architecture leadership and mentorship.\nStrengthen Synopsys’ leadership position in high-speed interface IP.\nWhat You'll Need:\nBSEE with 12+ years of relevant experience, or MSEE with 10+ years.\nDemonstrated Principal / Staff-plus technical leadership in ASIC digital design\nDirect RTL ownership of complex, production digital designs\nDeep PCIe controller/core digital design and architecture experience, CXL, AMBA, DDR, UCIe, or similar protocols strongly desired.\nProven ability to define micro-architecture and take designs from concept through silicon.\nStrong ASIC fundamentals: multi-clock design, CDC/RDC, resets, low power, DFT, synthesizable RTL, and timing-aware design.\nExperience with highly configurable / parameterized IP is strongly desired.\nScripting for design automation (Python, TCL, Perl) is desirable. Familiarity with AI-assisted design tools and flows is a plus.\nWho You Are:\nA hands-on PCIe architect who leads by example in the RTL.\nDecisive on technical trade-offs; calm on the hardest debugs.\nA clear communicator across design, verification, PD, and customers.\nA mentor who multiplies the team and can create other technical leaders", "jd_status": "stored"}, {"title": "Sr Staff Product Engineer, Simulation and Mixed-Signal Verification", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-14", "url": "https://careers.synopsys.com/job/bengaluru/sr-staff-product-engineer-simulation-and-mixed-signal-verification/44408/100607370544", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in the verification trenches, chasing down race conditions and learning that the hardest bugs are never where you first look. You know the difference between a testbench that works and one that scales across a full-chip regression with 10,000 tests. When a customer calls with a simulation mismatch that has stumped their team for a week, you do not panic. You ask three questions, pull waveforms, and usually find it in the interaction between assertion timing and clock domain crossing logic that nobody thought to check.\nWalking into a room with architects who have been designing SoCs for decades does not intimidate you. You earn their trust by understanding their problem faster than they expected and proposing a solution that actually fits their flow. You read RTL, you read logs, you read between the lines when a customer says 'the tool is slow' and figure out they are re-elaborating on every run because of a Makefile issue.\nAt Synopsys, you will work with semiconductor teams building the chips that power AI, automotive, mobile, and networking systems.\nWhat You'll Be Doing\nLead technical engagements with strategic customers deploying simulation and verification solutions for complex SoCs, acting as the primary technical interface for methodology, performance, debug, and signoff\nDrive resolution of challenging issues involving RTL and gate-level simulation, testbench integration, assertion failures, coverage gaps, X-propagation, timing annotation, and non-determinism\nOptimize simulation performance and regression throughput by analyzing compilation flows, elaboration bottlenecks, testbench architecture, and execution efficiency across block, subsystem, and full-chip environments\nSupport analog mixed-signal verification where required, including digital-analog co-simulation, behavioral modeling, Verilog-AMS integration, and convergence trade-offs\nCollaborate with Product Management and R&D to define requirements, prioritize enhancements, and influence the roadmap based on real customer deployment patterns\nDevelop and deliver technical presentations, training sessions, and workshops that translate complex simulation concepts into actionable guidance for customers and internal teams\nCreate application notes, reference flows, deployment guides, and debug playbooks that help customers adopt and scale verification solutions\nThe Impact You Will Have\nEnable semiconductor companies to verify and tape out SoCs that power AI accelerators, automotive systems, mobile processors, and networking infrastructure used by millions\nReduce time-to-tapeout by resolving simulation bottlenecks, debug inefficiencies, and verification signoff blockers that would otherwise delay product schedules by weeks or months\nInfluence the evolution of Synopsys simulation tools by translating real-world customer challenges into product requirements that shape future releases\nScale verification methodologies across customer organizations by building reusable flows and establishing best practices that improve productivity long after your engagement ends\nAccelerate adoption of advanced verification techniques including UVM, assertion-based verification, coverage-driven flows, and mixed-signal co-simulation in customer environments\nMentor applications engineers and customer verification teams, raising technical capability across the ecosystem and building long-term relationships rooted in trust\nDrive customer success metrics that directly affect Synopsys revenue, renewal rates, and competitive positioning in the EDA simulation market\nWhat You'll Need\nBS or MS in Electrical Engineering, Computer Engineering, Computer Science, or related discipline\n5+ years in Product Engineering, Applications Engineering, Functional Verification, ASIC/SoC Verification, or Simulation Technologies with a track record of solving complex verification challenges\nDeep expertise in RTL and gate-level simulation, SystemVerilog, UVM, SVA assertions, coverage-driven verification, simulation compilation and elaboration, debug workflows, and regression automation\nStrong understanding of event-driven simulation semantics, X-propagation, timing simulation and SDF annotation, race conditions, non-determinism, and simulation mismatches\nProven ability to debug complex SoC verification environments and identify root causes across design RTL, testbench code, assertions, models, tool configuration, and infrastructure\nExperience with analog mixed-signal verification is a strong plus, including digital-analog co-simulation, behavioral modeling, Verilog-AMS, AMS testbench integration, and accuracy versus performance trade-offs\nStrong customer engagement skills including the ability to present technical content clearly, lead escalations, and translate customer pain into actionable product feedback\nWho You Are\nYou can walk into a customer war room where a critical tapeout is blocked by a simulation failure and propose a path forward that the team believes in, even when the root cause is not yet clear\nYou read SystemVerilog and UVM code fluently enough to spot a testbench bug during a screenshare, and you explain what you found without making the engineer feel defensive\nYou are comfortable saying 'I do not know yet, but here is how I will find out' when a customer asks a question you have not seen before, and you follow through\nYou can explain a complex simulation performance trade-off or an assertion timing subtlety to a customer architect in two sentences without losing the nuance\nYou do not wait for R&D to fix every issue. When you can script a workaround or build a reference flow that unblocks a customer today, you do it\nYou keep track of five customer engagements at once and do not let things fall through the cracks\n\nThe Team You'll Be Part Of\nThis customer-facing team works with the world's top semiconductor companies to accelerate adoption of advanced simulation and verification technologies, delivering scalable solutions for complex digital and mixed-signal designs.\n\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Software Test Engineer – IP Routing & AI/Data Center Networks", "company": "Nokia", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-09-14", "url": "https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/37314", "is_hardware": true, "platform": "oracle", "jd_text": "We are looking for SW Test engineers who wish to be a part of developing and evolving the current and next generation of routers that form the core of anything internet. These routers are at the heart of Nokia’s IP product offerings, from data centers (including AI fabrics), to providing strong, resilient low latency and dependable IP backhaul for service providers and mission critical networks. In this role, you will have the opportunity to work with one of the best engineering teams in the industry. We value your expertise and offer an environment where you can thrive both professionally and personally. There are more customers we want to win, more networks to penetrate, more technologies to enable and more applications to support. We want to make smaller products, and we want to make bigger products. We want to build products based on newer standards and newer ASICS in the market.\n\nResponsibilities\nOwn software features end to end and ensure their quality is robust across products and platforms\nSpecialize in datacenter and AI networks \nWrite modular, lean, and efficient automation code including libraries and infrastructure\nWork closely with product management and software developers to meet customer requirements\n\nQualifications\nBachelor’s degree with 3–8 years of relevant experience in networking and software automation.\nExposure to any of the below domains:Layer-2 switching and layer-3 routing\nRouting protocols (ospf, isis, bgp)\nMulticast (pim, igmp) \nSegment Routing\nMpls  (ldp, rsvp-te)\nEvpns with vxlan, mpls, sr-te underlays\nQoS (policers, schedulers, shapers) \n\nAutomation experience in python, golang or any programming language\nExperience in virtualized environments such as kvm, dockers, and Kubernetes\nContribution to SONiC test infrastructure and automation frameworks\nGood communication skills to work with different engineering teams \nProven aptitude for methodical problem solving, good communication skills, strong attention to detail, and the ability to work well in a close-knit team.\n\nAbout the company\nAdvancing connectivity to secure a brighter world.\n\nNokia is a global leader in connectivity for the AI era. With expertise across fixed, mobile and transport networks, powered by the innovation of Nokia Bell Labs, we’re advancing connectivity to secure a brighter world. \n\nLearn more about life at Nokia.\n\nOur recruitment process\n\nWe act inclusively and respect the uniqueness of people. Our employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.\n\nIf you’re interested in this role but don’t meet every listed requirement, we still encourage you to apply. Unique backgrounds, perspectives, and experiences enrich our teams, and you may be just the right candidate for this or another opportunity.\n\nThe length of the recruitment process may vary depending on the specific role's requirements. We strive to ensure a smooth and inclusive experience for all candidates. Discover more about the recruitment process at Nokia.\n\nAbout the organization\nSome of our benefits:\n\nFlexible and hybrid working schemes\n\nA minimum of 90 days of Maternity and Paternity Leave, with the option to return to work within a year following the birth or adoption of a child (based on eligibility)\n\nLife insurance to all employees to provide peace of mind and financial security\n\nWell-being programs to support your mental and physical health\n\nOpportunities to join and receive support from Nokia Employee Resource Groups (NERGs)\n\nEmployee Growth Solutions to support your personalized career & skills development\n\nDiverse pool of Coaches & Mentors to whom you have easy access\n\nA learning environment which promotes personal growth and professional development - for your role and beyond\n\nLearn about additional benefits in specific countries.", "jd_status": "stored"}, {"title": "Product Power Engineer", "company": "SiFive", "location": "Santa Clara, California, United States", "date_posted": "2026-09-13", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Santa-Clara-California-United-States/Product-Power-Engineer_R-101527", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nThe Role:\nA successful candidate will work across teams to collect, analyze, and optimize design power with the following responsibilities and requirements.\n\nResponsibilities:\nCollect / analyze SiFive IP power consumption. \n\nGuide architecture and design to optimize our design to achieve state-of-the-art power efficiency\n\nCorrelate power models with RTL and Silicon\n\nInnovate ways to improve power analysis flows\n\nRequirements:\nMS or PhD in Computer Science / Computer Architecture\n\n5+ years of experience in power benchmarking, analysis and modeling\n\nExperience with power impacts at architecture, logic design, and circuit levels.   \n\nGood knowledge of computer architecture of high performance out-of-order CPU designs.  \n\nWorking experience in guiding trade-off between performance and power to arrive at optimal design.\n\nExperience with ASIC power analysis and optimization.\n\nHands-on expertise with either HW development (RTL/implementation flows, verification/validation,backend flows, FPGA flows) or SW development is a strong plus. \n\nSelf-starter, fast learner, strong problem-solving skills\n\nPay & Benefits\n\nConsistent with SiFive values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. \n\nFor candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.  The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.\n\nBase Pay Range\n$178,848.00-$218,592.00\nIn addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! \n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in\nUnited States of America\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.\n\nAs an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.\n\nCalifornia residents: please see our job candidate notice for more information on how we handle your personal information and your privacy rights: Privacy Policy Document.", "jd_status": "stored"}, {"title": "Infra-Sr Staff Design Verification Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-12T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718347972", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nKey Responsibilities:\nDevelop and maintain UVM-based verification environments for high-speed interconnect protocols (PCIe, CXL, AXI).\n\nCreate and execute verification plans for high-speed interconnect protocols including PCIe, CXL, AXI, and CHI.\n\nPerform block-level and top-level verification, including functional coverage, assertion-based verification, and regression testing.\n\nCollaborate with RTL designers, architects, and validation teams to ensure design correctness and coverage closure.\n\nWork closely with design and architecture teams to understand specifications and derive verification strategies.\n\nUse third-party VIPs (e.g., Synopsys, Mentor) for protocol compliance and simulation.\n\nImplement and enhance scoreboards, agents, monitors, and sequences.\n\nIntegrate and validate SMMU and Coresight components in Subsystem environments.\n\nDrive verification closure through coverage convergence and assertion-based verification.\n\nContribute to performance, power, and cost optimization considerations during verification.\n\nMentor junior engineers and contribute to verification methodology improvements.\n\nDebug failures at RTL and gate-level simulations.\n\nRequired Skills:\nStrong proficiency in System Verilog, UVM, and verification methodologies.\n\nDeep understanding of PCIe Gen3/Gen4/Gen5/Gen6, CXL 1.1/2.0/3.0, AXI/CHI protocols, and SMMU/Coresight architecture.\n\nFamiliarity with Synopsys/Mentor VIPs for PCIe/CXL and AMBA protocols.\n\nExpertise in assertion-based verification (SVA) and coverage-driven testing.\n\nProficiency in Perl/Python/Tcl scripting for automation.\n\nKnowledge of power-aware verification (UPF), formal verification, and performance/power optimization.\n\nExperience with coverage-driven verification and random constraint-based testing.\n\nExperience with scripting languages like Python, Perl, or Tcl.\n\nPreferred Qualifications:\nBachelor’s/Master’s/Ph.D. in Electrical, Electronics, or Computer Engineering.\n\n8–12+ years of ASIC/Subsystem/SoC verification experience.\n\nExperience with PCIe, USB, Ethernet, or other peripheral protocols is a plus.\n\nExposure to post-silicon validation and lab bring-up is desirable.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Infra Design Verification Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-12T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720388798", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nJob Overview\nWe are looking to hire a strong DV engineer to work on verification of DDR Subsystem in the Infra IP team\nCreate DV infrastructure for verification\n\nIntegrate VIP's\n\nCreate and execute test plans, debug failures, write assertions, close code and functional coverage\n\nEnsure high quality verification\n\nWorking with all stakeholders to ensure program success\n\nMinimum Qualifications\nBachelor's degree in Engineering, Electronics, Information Systems, Computer Science, or related field.\n5+ years Hardware Engineering experience or related work experience.\nPreferred Qualifications\nFollowing skill set is required:\nStrong Debug, UVM, System Verilog\n\nUnderstanding Specs and Standards and developing relevant test plans\n\nMonitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved\n\nCandidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening\n\nPreferred Qualifications 5+ Year of industry experiences in the following areas: -\nThorough understanding of Digital design concepts\n\nThorough understanding dv methodologies and tools\n\nGood understanding of LPDDR4/LPDDR5 protocols\n\nUnderstanding of Bus protocols like AHB/AXI/ACE/ACE-Lite\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU Emulation Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-12T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718657333", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nAs a CPU Emulation Engineer, you will work as part of CPU verification team to deliver emulation-based solutions for CPU team. You will work closely with all disciplines of CPU team to help verify and validate high performance CPUs.\n \nRole and Responsibilities\nWork closely with CPU RTL, performance, verification and SW teams to deliver emulation-based solutions.\nArchitect and develop test bench infrastructure in C/C++ and Systemverilog for enabling CPU emulation across different platforms.\nDevelop verification methodology, ensuring scalable and portable environment across simulation and emulation.\nDebug emulation performance and area issues to efficiently use emulation resources.\nDevelop environment to run verification test cases, OS boot, performance benchmarks and other vectors.\nDevelop debugging methodology to enable efficient debug and root causing of CPU functional and performance issues.\nDevelop and maintain emulation environment to collect metrics related to emulation environment.\nWork closely with emulation CAD team to resolve infrastructure issues and ensure productivity on emulation models.\nExecute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures.\n \nPreferred Qualifications\n5+ years of experience with emulation platforms – Palladium, Zebu, Veloce, FPGAs.\nExperience with synthesizing and optimizing designs and verification components developed in synthesizable Verilog.\nExperience with C/C++ DPI transactors and monitors.\nExperience in scripting using Perl, Python or shell scripts. Experience with packaging workloads for cloud.\nExperience with debugging ARM CPU based designs. Knowledge on ARM ISA and programmers’ model is a plus.\nExperience with Linux boot and firmware aspects is a plus.\nExperience with CPU architecture and micro-architecture is a plus.\n \nMinimum Qualifications:\n• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.\nOR\nMaster's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.\nOR\nPhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Infra Design Verification Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-12T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720179723", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nWe are looking to hire a strong DV engineer to work on verification of DDR Subsystem in the Infra IP team\nCreate DV infrastructure for verification\n\nIntegrate VIP's\n\nCreate and execute test plans, debug failures, write assertions, close code and functional coverage\n\nEnsure high quality verification\n\nWorking with all stakeholders to ensure program success\n\nMinimum Qualifications\nBachelor's degree in Engineering, Electronics, Information Systems, Computer Science, or related field.\n5+ years Hardware Engineering experience or related work experience.\nPreferred Qualifications\nFollowing skill set is required:\nStrong Debug, UVM, System Verilog\n\nUnderstanding Specs and Standards and developing relevant test plans\n\nMonitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved\n\nCandidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening\n\nPreferred Qualifications 5+ Year of industry experiences in the following areas: -\nThorough understanding of Digital design concepts\n\nThorough understanding dv methodologies and tools\n\nGood understanding of LPDDR4/LPDDR5 protocols\n\nUnderstanding of Bus protocols like AHB/AXI/ACE/ACE-Lite\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "DFx-DV  Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-11T12:56:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92272/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. Sr SILICON DESIGN ENGINEER - DFT VERIFICATION THE ROLE: We are looking for an adaptive, self-motivated design for test verification engineer to join our growing server SOC DFT team. Identified candidate will be responsible for high quality verification of our DFT features for next generation server SOCs. This team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion design for test, and verification. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Create and execute test plans for DFT features for next generation EPYC server SOCs. Carryout verification of DFT features such as JTAG/1500/1687, MBIST, Scan, Fuse, Clocks, Resets, high speed IO testing and much more at SOC level. Will be creating test bench and verification infra using SV or C++. Debug regression test failures and root cause design issues, identify verification gaps and address the same. Debug fails and root cause them to design / verification issues. Planning and projecting timelines for areas owned such as test plan creation, test writing, development of verification components, pattern generation etc. Collaborate with large set of stakeholders such as architects, design engineers, functional verification engineers, post silicon engineers etc. Work on code and functional coverage. Generate patterns for post silicon testing and support ATE bring up. Carryout post silicon debugs and help post silicon team achieve high coverage. Work on emulation platforms to augment verification. PREFERRED EXPERIENCE: Prior experience in verifying DFT features at subsystem / SOC level. Proficient in standard simulation & debug tools such as VCS, Verdi etc. Experienced with Verilog, C, C++, Linux and Windows environments. Scripting language experience: Perl, Python,Ruby, Makefile, shell preferred.   Knowledge in few of the DFT features such as JTAG, Memory BIST, Logic BIST, Scan, ATPG is highly desirable Exposure to post silicon debugs and bring up highly is desired. ACADEMIC CREDENTIALS: Bachelors or Masters degree in Electronics/Electrical Engineering. #LI-AA1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Sr. Silicon Design Engineer (203)", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-11T07:50:00+00:00", "url": "https://global-external-amd.icims.com/jobs/86227/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. SENIOR SILICON DESIGN ENGINEER THE ROLE: We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Develop/Maintain tests for functional verification and performance verification at the core level Build testbench components to support the next generation IP Maintain or improve current test libraries to support IP level testing Create hardware emulation build to verify the IP functional performance Maintain and improve current hardware emulation environment to speed up the runtime performance and improve the debug facility Provide technical support to other teams PREFERRED EXPERIENCE: Good at C/C++ Familiarity with SystemVerilog and modern verification libraries like UVM Experience/Background on Computing/Graphics is a benefit Experience with OpenGL/OpenCL/D3D programming is a benefit ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-NS1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Physical Design Lead(High Speed IP's)", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-11T07:08:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92268/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. SMTS SILICON DESIGN ENGINEER THE ROLE AMD is looking for an experienced and highly motivated Member of Technical Staff (MTS) to join the CT Physical Design team. In this role, you will drive the physical implementation of industry-leading high-speed interface IPs including DDR, LPDDR, GDDR, PCIe, and other next-generation mixed-signal PHY solutions used across client, server, and graphics products. As a technical leader, you will work closely with architects, circuit designers, RTL, package, power integrity, signal integrity, SoC, and methodology teams to define and implement innovative physical design solutions that achieve aggressive PPA, frequency, power, and schedule goals on advanced process nodes. The ideal candidate combines deep physical design expertise with strong leadership capabilities and a proven track record of delivering complex, high-performance IPs to production. THE PERSON You are passionate about solving complex physical design challenges in advanced semiconductor technologies. You thrive in fast-paced environments, influence technical direction beyond your immediate team, and enjoy mentoring engineers while driving innovation in implementation methodologies. You possess deep understanding of high-speed digital and mixed-signal design implementation and have successfully delivered multiple tape-outs in advanced technology nodes. KEY RESPONSIBILITIES Lead physical design implementation of complex high-speed IPs such as DDR/LPDDR/GDDR PHYs, PCIe, SerDes, and related subsystems. Own end-to-end implementation activities including some or all of these domains: Floorplanning Power planning Placement Clock architecture CTS Timing closure Signal integrity closure Physical verification Tapeout signoff Drive high-frequency timing closure for challenging datapaths and clock distribution networks. Partner with architects and circuit designers to optimize PHY architectures for performance, power, and implementation efficiency. Develop and deploy innovative implementation methodologies to improve design quality, productivity, and scalability. Collaborate with cross-functional teams including Architecture, RTL, AMS, Package, SI/PI, Product Engineering, SoC, CAD, and EDA vendors. Mentor junior engineers and help grow the technical capability of the organization. Drive continuous improvement initiatives in automation, AI-assisted design methodologies, and signoff flows. PREFERRED EXPERIENCE 10+ years of industry experience in Physical Design for advanced semiconductor products. Proven track record delivering multiple successful tape-outs on advanced technology nodes (N3/N4/N5 or equivalent). Experience closing timing at aggressive frequencies and implementing complex clocking structures. Expertise with industry-standard EDA tools including Cadence and Synopsys implementation/signoff flows. Experience driving methodology development and automation. Demonstrated leadership across cross-functional teams and geographies. TECHNICAL SKILLS Physical Design and Signoff STA and Timing Closure Clock Architecture and CTS Floorplanning and Power Planning IR/EM Analysis Physical Verification SI/PI Analysis Low Power Design (UPF/CPF) Advanced Node Design Methodologies Tcl/Python/Scripting AI-assisted Design Flows (preferred) LEADERSHIP EXPECTATIONS Leads strategic technical initiatives across multiple IP programs. Mentors and develops engineering talent. Drives innovation that improves product competitiveness, engineering productivity, and design quality. EDUCATION BS/MS in Electrical Engineering, Computer Engineering, VLSI Design, or related field. #LI-PM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "CPU/Cores Post‑Silicon Validation (Virtualization / Hypervisor)", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-11T04:06:00+00:00", "url": "https://global-external-amd.icims.com/jobs/85452/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. CPU/Cores Post‑Silicon Validation (Virtualization / Hypervisor) Role Summary We are looking for aStaff Engineer with strong virtualization and hypervisor fundamentals to drive post‑silicon validation of CPU cores. The engineer will leverage virtualized workloads and customer‑representative scenarios to stress core microarchitecture, identify silicon issues early, and collaborate with design, uCode/FW, BIOS, and platform teams to root‑cause and resolve issues. This role treats virtualization as a primary validation and bug‑hunting vector, rather than a feature enablement check, to uncover real‑world core issues under production‑like stress. Key Responsibilities Execute post‑silicon cores validation using virtualization‑based workloads and scenarios Configure, deploy, and debug workloads on hypervisors (KVM, VMware, Hyper‑V, Xen) across Linux and Windows environments Design and run VM‑based stress tests (migration, pause/resume, overcommit, multi‑VM contention, long‑run soak, reset scenarios) to expose core‑level bugs Analyze system failures and triage issues spanning core microarchitecture, uCode, FW, BIOS, DF/UMC, and platform interactions Correlate failures using logs, MCA, MSRs, debug hooks, and limited post‑silicon observability Work closely with design and architecture teams to provide actionable debug data and validation feedback Contribute to automation and scalable execution infrastructure for large‑scale virtualization runs Track coverage, execution hours, and defect trends to ensure production‑quality readiness Required Qualifications Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, Computer Science, or related field Strong hands‑on experience with virtualization technologies and hypervisors (KVM, VMware ESXi, Hyper‑V, Xen) Solid understanding of x86 CPU architecture and core microarchitectural concepts Experience in Linux internals (scheduler, memory management, interrupts) and system‑level debugging Familiarity with post‑silicon validation, silicon bring‑up, or system validation Ability to debug complex issues across HW/SW boundaries Preferred Qualifications Bachelors or Masters degree in computer engineering/Electrical Engineering Prior experience in CPU cores post‑silicon validation or core stress testing Knowledge of microcode, BIOS, firmware, and platform initialization flows Exposure to customer‑like server or client virtualization workloads Experience with automation frameworks and large‑scale validation infrastructure Strong data analysis and root‑cause skills for low‑frequency, long‑run failures #LI-DB2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "CPU/Cores Post Silicon Validation (Functional)", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-11T04:05:00+00:00", "url": "https://global-external-amd.icims.com/jobs/86681/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. CPU/Cores Post Silicon Validation (Functional) THE ROLE: The AMD Cores system validation team is looking for a dynamic, energetic CPU Cores Validation engineer to join our growing team focused on the Zen CPU. Cores Systems Validation Engineer will architect, drive and perform hands-on system level debug to isolate functional failures to a specific IP or domain. Exposure begins at the architecture level, working with pre-silicon teams to maximize pre-silicon coverage, post-silicon bring-up and enablement, and engagement through production and working with customer facing teams for best adoption. You will work in a dynamic environment, directly with the product, tools, motherboards, and BIOS/OS. THE PERSON: As a key contributor to the success of AMD’s Cores roadmap, you will be driving and directing a high performing team towards the delivery of high quality, industry-leading processors to the market. The validation team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. KEY RESPONSIBILITIES: Orchestrate the functional validation of CPU Cores by participating in the Test plan definition, Content generation, Execution and Debug of critical functional issues. Isolate and triage generic system level failures into a more focused area of the platform or CPU. Drive debug and resolution of Zen CPU validation issues across silicon, firmware/BIOS, and coordinating with memory partners as needed Develop x86 content to exercise new features and reproduce complex bugs in silicon Devise validation strategy from pre-silicon through customer adoption working across architecture, silicon design, firmware, validation, and debug teams Proactively participating in project planning, developing, and maintaining schedules, managing dependencies, and ensuring quality of deliverables at committed milestones. Generates/Maintains regular status representing the Cores Validation team in program meetings providing status to program management PREFERRED EXPERIENCE: Programming/scripting skills (e.g. C/C++, Perl, Ruby, Python) x86 assembly programming Debug techniques and methodologies Extensive experience with board/platform-level debugging, including delivery, sequencing, analysis, and optimization Extensive knowledge of system architecture, technical debug, and validation strategy Strong analytical/problem-solving skills and pronounced attention to details Must be a self-starter, and able to independently drive tasks to completion      ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-DB2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "CPU Post Si Validation Engineer(Power and Performance)", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-11T04:04:00+00:00", "url": "https://global-external-amd.icims.com/jobs/87445/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. CPU Post Si Validation Engineer(Power and Performance)   THE ROLE: The AMD Cores system validation team is looking for a dynamic, energetic CPU Cores Validation engineer to join our growing team focused on the Zen CPU. Cores Systems Validation Engineer will architect, drive and perform hands-on system level debug to isolate functional failures to a specific IP or domain. Exposure begins at the architecture level, working with pre-silicon teams to maximize pre-silicon coverage, post-silicon bring-up and enablement, and engagement through production and working with customer facing teams for best adoption. You will work in a dynamic environment, directly with the product, tools, motherboards, and BIOS/OS. THE PERSON: As a key contributor to the success of AMD’s Cores roadmap, you will be driving and directing a high performing team towards the delivery of high quality, industry-leading processors to the market. The validation team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. KEY RESPONSIBILITIES: Orchestrate the Power and Performance validation of CPU Cores by participating in the Test plan definition, Content generation, Execution and Debug of critical Power and Perfromance issues. Drive debug and resolution of Zen CPU Power and Performance validation issues across silicon, firmware/BIOS, and coordinating with memory partners as needed Develop x86 content to exercise new features and reproduce complex bugs in silicon Devise validation strategy from pre-silicon through customer adoption working across architecture, silicon design, firmware, validation, and debug teams Proactively participating in project planning, developing, and maintaining schedules, managing dependencies, and ensuring quality of deliverables at committed milestones. Generates/Maintains regular status representing the Cores Validation team in program meetings providing status to program management Experienced in applying AI/ML techniques to drive data‑driven insights and optimize system performance and improve team efficiency and throughout for execution and debug. PREFERRED EXPERIENCE: Programming/scripting skills (e.g. C/C++, Perl, Ruby, Python) x86 assembly programming Debug techniques and methodologies Extensive experience with board/platform-level debugging, including delivery, sequencing, analysis, and optimization Extensive knowledge of system architecture, technical debug, and validation strategy Strong analytical/problem-solving skills and pronounced attention to details Must be a self-starter, and able to independently drive tasks to completion   ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-DB2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "CPU Verification Engineer - Core Enablement", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-11T03:25:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92116/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. MTS SILICON DESIGN ENGINEER    THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.     THE PERSON:  You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.   KEY RESPONSIBILITIES:  Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues  Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements   PREFERRED EXPERIENCE:  Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools  Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++   Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment.   Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience.   Scripting language experience: Perl, Ruby, Makefile, shell preferred.   Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions.     ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Sr. Manager CPU Verification", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-11T02:41:00+00:00", "url": "https://global-external-amd.icims.com/jobs/92151/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. Senior Manager, CPU Verification THE ROLE: Person will be part of next generation CPU Cores Verification team. The role will require the candidate to understand and work on all aspects of VLSI development from CPU micro architecture verification, front end verification. Requires strong hands-on IP design verification experience and knowledge of all facets of the IP design process and a good understanding of verification concepts. Key Requirements Minimum 15+ years of solid experience in IP design verification. Developing stimulus, asm based directed tests and exerciser stimulus to verify different complex CPU design features. In depth understanding of CPU core micro-architecture designs, Cache design, cache verification, pipeline, Power Management aspects and Microprocessors is required Ability to review top level test plans Needs to makes effective and timely decisions, even with incomplete information. Should possess a strong understanding of a particular technical area and accumulated significant experience in this area and other related areas. Provides direction, mentoring, and leadership to a small to medium sized groups. Should possess strong communication and leadership skills to ensure effective communication with Program KEY RESPONSIBILITIES: Lead the team performing Core IP verification for functional, power, and performance aspects with simulation and hardware emulation environments. Work in close collaboration with the front end design and physical design teams on the various IP verification efforts Interact with a wide variety of internal and external design verification development teams, DV methodology, and Silicon IP and tool vendors. Manage IP dependencies, planning and tracking of all front end design related tasks Driving the project milestones across the design, verification and physical implementations Advises senior management on specialized technical or business issues. Implements strategic policies when selecting methods, techniques, and evaluation criteria to obtain results. Regularly interacts with senior management or executive levels on difficult matters concerning several functional areas, multiple business units, and/or customers. Key relationships with important customers and vendors have been developed. Requires the ability to change the thinking of, or gain acceptance from, others in sensitive situations, without damage to the relationship. Additional responsibilities include identifying the right candidates, hiring activities, growing the team to accomplish project needs. ACADEMIC CREDENTIALS: Bachelor/Master Degree in Electrical/Computer Engineering. Master preferred LOCATION: Bangalore #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Tech Lead, Physical Design", "company": "Astera Labs", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-11T02:20:38-04:00", "url": "https://job-boards.greenhouse.io/asteralabs/jobs/4733032005", "is_hardware": true, "platform": "greenhouse", "jd_text": "Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\n\nTech Lead Physical Design \n\nExperience - 6-14 years\n\nBengaluru, India \n\nAstera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.  \n\nWhat You’ll Do\n\nOwn and execute end-to-end physical design implementation for complex, high-performance ASIC/SoC designs.\n\nWork on physical design activities including:\n\nFloorplanning and partitioning\n\nPower planning\n\nPlacement and optimization\n\nClock Tree Synthesis (CTS)\n\nRouting and post-route optimization\n\nTiming closure\n\nPhysical verification\n\nECO implementation\n\nPerform Static Timing Analysis (STA) and resolve setup/hold timing violations.\n\nAnalyze and address congestion, IR drop, electromigration, signal integrity, and other physical design challenges.\n\nWork closely with RTL, Design Verification, DFT, STA, and architecture teams to ensure successful design implementation.\n\nDrive PPA optimization while meeting aggressive timing and power targets.\n\nParticipate in design signoff activities and ensure the design meets required timing, power, and physical verification criteria.\n\nDevelop and maintain automation scripts and flows to improve physical design productivity.\n\nDebug complex implementation issues and contribute to improving physical design methodologies and flows.\n\nRequired Qualifications\n\nBachelor's or Master's degree in Electrical/Electronics Engineering, VLSI, Microelectronics, or a related field.\n\nStrong understanding of ASIC physical design flows and methodologies.\n\nHands-on experience with physical design implementation from netlist to GDSII.\n\nGood understanding of:\n\nFloorplanning\n\nPlacement\n\nCTS\n\nRouting\n\nSTA\n\nTiming closure\n\nPhysical verification\n\nExperience with industry-standard EDA tools such as Cadence, Synopsys, or equivalent.\n\nStrong understanding of CMOS digital design and semiconductor fundamentals.\n\nGood scripting/programming skills in Tcl, Python, Perl, or Shell.\n\nStrong analytical and problem-solving skills.\n\nPreferred Qualifications\n\nExperience working on advanced process nodes and high-performance SoCs.\n\nExperience with block-level and/or full-chip physical design.\n\nExperience with multi-voltage/multi-clock designs.\n\nKnowledge of UPF/low-power design methodologies.\n\nExperience with IR/EM analysis and signal integrity.\n\nExperience with physical design automation and flow development.\n\nExposure to SerDes, PCIe, CXL, Ethernet, memory interfaces, or other high-speed connectivity technologies would be an advantage.\n\nExperience taking designs through full physical signoff and tapeout.\n\nWhat You’ll Get to Work On\n\nAt Astera Labs, you will have the opportunity to work on cutting-edge connectivity solutions for AI and cloud infrastructure, collaborating with experienced semiconductor engineers across architecture, RTL, verification, DFT, and physical design.\n\nYou will be part of a highly collaborative engineering environment where your work directly contributes to delivering high-performance, high-bandwidth semiconductor products.\n\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.", "jd_status": "stored"}, {"title": "Emulation Engineer - Lead/Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-11T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718411115", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Systems Engineering\nGeneral Summary:\nJob Summary:          \n6-10 years of experience in Emulation of complex Qualcomm propriety DSP IP\n\nDSP design team is responsible for delivering high-performance DSP cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space\n\nJob Responsibilities: \nWork in emulation and silicon environments\n\nPrior experience with Emulation Platforms (FPGA Prototyping, Veloce, Palladium)\n\nFamiliarity with emulation tools (Synthesis, Place and Route, Constraints, Clocking) and System Debug (Waveform generation and Content Debug support)\n\nUnderstand processor functionality (CPU/DSP Core)\n\nExcellent debugging abilities to resolve complex issues\n\nValidation and debugging of digital circuits\n\nProficient in scripting languages such as Python and TCL\n\nSkillset/Experience:          \n6-10 years of experience in processor/ASIC performance verification\n\nExperience in micro-architecture validation for modern high-performance, low power processors\n\nExperience in writing tests and building infrastructure that tests performance of modern processors\n\nExperience in application performance analysis\n\nProgramming/Scripting Skills — C, C++, Perl, Python, Shell, Make file TCI\n\nSolid background and understanding of Digital Design, RTL design, improving model performance and Processor Architecture\n\nStrong troubleshooting, analytical and debug skills\n\nPrior experience is performance correlation of Processor subsystems (ARM/DSP) is preferred\n\nShould have excellent inter-personal, communication skills and ability to work in a fast-paced exciting environment\n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience.\n                                                                    OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.\n                                                                    OR\nPhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Performance Optimization Architect/Manager", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-11T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721020326", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Systems Engineering\nGeneral Summary:\nQualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.\n\nQualcomm has been at the forefront of driving the revolution in the mobile gaming space by providing state of the art powerful GPUs as part of the Snapdragon program. Snapdragon Elite Gaming delivers the full suite of desktop-level features, including volumetric rendering for hyper-realistic visuals. Qualcomm® Adreno™ GPU is the powerhouse engine behind high-performance graphics and rich user experiences with low power consumption. Our Adreno™ GPU is designed to quickly render complex geometries for next-level visuals in games and apps—with super-fast responsiveness and superior mobile connectivity for truly immersive experiences. As part of GPU performance and architecture team, the candidate will be working on the latest and greatest in GPU architecture and Computer Graphics. The role revolves around working on analyzing the most popular games and benchmarks which use highly advanced rendering techniques, evaluating their performance on Qualcomm GPUs, define new optimizations/algorithms/configurations for the Adreno GPUs and modeling them to define next generation of Adreno™ GPU\n \nResponsibilities:\nConduct system level performance analysis and bottleneck analysis for intricate, high-performance GPUs and System-on-Chips (SoCs).\n\nUtilize hardware models at various levels of abstraction, including performance models, RTL test benches, emulators, and silicon, to scrutinize and identify performance bottlenecks in the system.\n\nComprehend key performance use-cases of the product and formulate workloads and test suits focusing on graphics, machine learning, automotive, video, and computer vision applications.\n\nCollaborate closely with architecture and design teams to explore architecture trade-offs related to system performance, area, and power consumption.\n\nDevelop necessary infrastructure, including performance models, testbench components, and performance analysis and visualization tools.\n\nLead efforts to enhance turnaround time, identify representative data-sets, and facilitate early performance analysis in the product development cycle.\n\n \nQualifications:\nBachelor’s (BE/BTech) or Master’s (MS/MTech) degree in a relevant field; PhD is a plus, or equivalent experience.\n\nKnowledge of Graphics APIs e.g. OpenGL, Vulkan, DirectX, Metal\n\nA minimum of 12 years of experience in Computer Graphics or a related field with exposure to performance analysis and complex System-on-Chip (SoC) and/or GPU architectures.\n\nProfound understanding of System-on-Chip (SoC) architecture, graphics pipeline, memory subsystem architecture, and Network-on-Chip (NoC)/Interconnect architecture.\n\nExpertise in programming languages (C/C++) and scripting languages (Perl/Python). Exposure to Verilog/System Verilog, SystemC/TLM is highly advantageous.\n\nStrong debugging and analysis skills, including data and statistical analysis, and proficiency in using RTL dumps to debug failures.\n\nHands-on experience in developing performance simulators and cycle accurate/approximate models for pre-silicon performance analysis is a significant advantage.\n\n \nKeywords: 3D graphics; benchmark analysis; gpu; performance modeling; compute architecture, Complier, OpenGL, Vulkan, DirectX\n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Systems Engineering or related work experience.\n                                                                    OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Systems Engineering or related work experience.\n                                                                    OR\nPhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior SoC Physical Design Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-11T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720933109", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nJob Description:\nBachelor's degree in Electrical or Electronics Engineering with 2 - 4 years of experience in physical design.\n\nExperience in synthesis, PnR, sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations.\n\nJob Requirement:\nExperience with demanding PPA requirement of complex sub-syste/SOC, place and route, IP integration.\n\nExperience in low power design Implementation including UPF, multi-voltage domains, power gating.\n\nExperience with ASIC design flows and methodology of Physical design. Understanding of circuit design, device physics and deep sub-micron technology.\n\nShould have worked on multiple TO in advance technology nodes.\n\nPerson should also have good understanding of automation to drive the efforts to improve the PPA\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Lead Pre/Post Silicon Validation Engineer - SoC Security and access control Expertise", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-11T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721001065", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all.\n\nSVE (System Validation & Emulation) team within Bangalore Design Center is responsible for validating hardware solutions and to integrate new hardware (IP cores and SoCs) to maximize software productivity and enable faster time to market. The validation organization is central to minimizing the number of chip turns in products, to the efficient transition of sound and reliable HW to SW organizations, and to the development of new validation methodologies. Validation team is currently looking for self-motivated engineers at all levels who will perform Hardware Security validation at core and system level, debug, in emulation and in post-Silicon.\n\nAs a Qualcomm Hardware Engineer within Hardware Security validation team, you will create functional validation test plan, develop validation test content, execute the test content on Pre-Silicon platform(FPGA based emulation platform), and Post-Silicon platform. You'll be responsible for debugging and triaging failures on both Pre-Si as well as Post-Si platform. You'll be working as an individual contributor and also lead junior engineers within the team. You'll will be expected to validate a portfolio of Hardware based Security IPs that manage Hardware based Security Encryption accelerators, SoC Security, Fuses, Access Control, Secure Boot and Trusted Platform Module. The role requires you to work with cross functional teams like Architecture, Product Engineers, Design, Design Verification, Software, Firmware, ATE/PTE, RMA/CE/CQE, and Program Managers. You would be expected to driver overall Security Hardware Validation on different segments of Qualcomm's business like Automotive, Mobile, Modem, Compute, and IOT/XR.\n\nResponsibilities:\nUnderstand HDDs, PRDs, micro architecture document, create Validation/Test plan, develop content, and execute to validate Security IP and integration at the system level on emulation and the post-silicon environment.\n\nCollaborate closely with cross-functional teams to develop, validate targeted tests/UC’s on pre and post-silicon platform and for any debugs that requires.\n\nGet in-depth knowledge of IP and its feature integration into SoC to validate and debug.\n\nJob Qualifications:\nBachelor's/Master's in Electrical/Electronic Engineering or Computer Engineering.\n\n5-8 years of relevant industry experience in SoC Security, Access Control, Trusted Platform Module(CC EAL5+ Certified) , Hardware Accelerators for Symmetric Crypto, Asymmetric Crypto, Random Number Generators etc.\n\nProficiency in C/C++ & Python programming for content development and scripting.\n\nFamiliarity with ARM SoC concepts and architecture specifications like SMMU, GIC, Coresight.\n\nStrong debugging skills, with experience using Lab Equipment such as Protocol Analyzer, Logic Analyzers, Oscilloscopes, and Lauterbach debuggers.\n\nFamiliarity with display concepts, interfaces and power or performance measurement of SoCs.\n\nExcellent communication, interpersonal, and problem-solving skills, with the ability to quickly adapt to new environments and technologies.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Layout Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-11T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721051405", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Services Group, Engineering Services Group > Layout Engineer\nGeneral Summary:\nDevelops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues.\n\nMinimum Qualifications:\n•    Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.\n                                                                    OR\nAssociate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.\n                                                                    OR\nHigh School diploma or equivalent and 8+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.\n\n•    4+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap).\n\n*Completed advanced degrees in a relevant field may be substituted for up to two years (Master’s = one year, Doctorate = two years) of the general custom layout design work experience in a relevant domain (e.g., analog, mixed signal, RF, digital design).\n\n8+ Years of Experience in Custom Analog Layouts\nMinimum 8+ years of experience in SerDes Blocks like PLL, Tx and Rx.\nFinfet Experience is mandatory.\nKnowledge in Cadence Skills Scripting, Totem ESD flows are added advantage\nNeed to Possess Good Attitude and team playe\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SoC Physical Design Engineer (Senior/Lead) - HM PD team", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-11T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720745161", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nJob Description :\nBachelor's degree in Electrical Engineering with 3-8 years of experience in physical design.\n\nExperience managing complex Subsystem and Small team.\n\nExperience in synthesis, PnR, sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations.\n\nJob Requirement:\nExperience with demanding PPA requirement of complex sub-system/SOC, place and route, IP integration.\n\nExperience in low power design Implementation including UPF, multi-voltage domains, power gating.\n\nExperience with ASIC design flows and methodology of Physical design.\n\nUnderstanding of circuit design, device physics and deep sub-micron technology. Should have worked on multiple TO in advance technology nodes.\n\nPerson should also have good understanding of automation to drive the efforts to improve the PPA\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Design Engineer - SoC & RTL", "company": "Lattice", "location": "Pune, India", "date_posted": "2026-09-11", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Pune-India/Digital-Eng--SoC-RTL-_R-103226-1", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\n\nLattice Semiconductor is seeking a SoC RTL Design Engineer to join the HW design team focused on IP design and full chip integration.  This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn, innovate and grow.\nRole specifics:\n·       This is a full-time individual contributor position located in Pune, India.\n·       The role will focus on FPGA projects concentrated in Pune and similar time zones.\n·       The qualified candidate will be working in RTL design, best-in-class coding styles, algorithms, and both Verilog and System Verilog.\n·       The qualified candidate will be working in SoC integration and associated quality checks including lint, CDC, RDC, SDC etc.\n·       The role requires to work with architect and micro-architect team to understand define design specifications\n·       The successful candidate will be open and willing to both (a) teach best-known-methods to an existing FPGA team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and an open-minded student. \n\nAccountabilities:\n·       Serve as a key contributor to FPGA design efforts.\n·       Drive logic design of key FPGA blocks & full chip and bring best-in-class methodologies to accelerate design time and improve design quality.\n·       Ensuring design quality through assertions, checkers, and scripting.\n·       Develop strong relationships with worldwide teams.\n·       Mentor and develop strong partners and colleagues.\n·       Occasional travel as needed.\n\nRequired Skills:\n·       BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent.\n·       6+ years of experience in driving logic design across a multitude of silicon projects.\n·       Expertise in SoC integration, defining micro-architecture and experience of selecting 3rd party IP.\n·       Experience in working with ARM processor, AXI, AMBA bus, ENET, PCIE, safety and security protocols, debug architecture will be plus.\n·       Familiarity with FPGA designs, use-cases, and design considerations is a plus.\n·       Independent worker and leader with demonstrated problem-solving abilities.\n·       Proven ability to work with multiple groups across different sites and time zones.\n\nLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.\n\nLattice\nFeel the energy.\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Staff Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-09-11", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Staff-Design-Engineer_R026392", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nJob Description\n\nThe position requires a breadth of disciplines and responsibilities in supporting the Processor based subsystem verification for the ‘ASIC Products Division’ within Broadcom Limited.\nResponsibilities will include Verification  environment Development, Verification,  Functional verification, performance verification, Coverage Closure, Gate simulations, releases, reviews etc.\nTypical subsystems are based on ARM processors like A72, A55, A53, R8, AMBA Bus matrixes like NOC, CCI, NIC and memory controllers like HBM, Memory management Units MMU/SMMU and various peripherals.  Responsibilities will be both individual and team based with ability to work cross functionally across the organization.\n\nRequirements/Qualifications (Education)\n\nB.E/B.Tech/M.E/M.Tech in Electronics/VLSI Engineering with strong 6+ years of experience in Processor subsystem verification in both directed and random verification\n\nExperience in ARM Processor based subsystem verification using ARM asm and C language\n\nGood exposure to latest ARM processor architectures, Bus Interconnects and AMBA protocols – CHI, AXI, AHB, APB\n\nExperience in Verilog, System Verilog and UVM based testbench and environment development.\n\nWorking knowledge of Verilog, and have programming skills in Perl and TCL scripting languages\n\nExpertise to develop block level / subsystem level verification environments using System Verilog and UVM is a must.\n\nDemonstrate the ability to work through technology challenges with high-performance design verification.\n\nAdditionally, the candidate should possess excellent communications and inter-personal skills to work closely with other team members and be self-motivated to learn new tools and design flows\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Senior Silicon Engineer, Power and Thermal Controllers", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-09-11", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Silicon-Engineer--Power-and-Thermal-Controllers_JR2025300", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a \"learning machine\" that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life's work to amplify human imagination and intelligence. Make the choice to join us today!\n\nJoin NVIDIA's dynamic team as a Senior Hardware Engineer, Power & Thermal Controllers, and help craft the future of computing in Bengaluru. As an NVIDIAN, you'll tackle complex challenges across architecture, silicon, firmware, software, and production, demonstrating your outstanding judgment and technical expertise. Our team plays a key role in ensuring NVIDIA silicon products are tuned, configured, and protected from power and thermal excursions. This allows them to operate flawlessly and efficiently within their built limits.\n\nWhat you will be doing:\nLead the productization of power and thermal controllers from pre-silicon planning through bring-up, tuning, validation, and production.\n\nCollaborate with architecture, design, firmware, and software teams to define controller requirements, identify improvements, and translate new capabilities into production-ready solutions.\n\nCharacterize and tune controller behaviour across workloads, operating conditions, silicon variation, and product power and thermal limits.\n\nCorrelate silicon behaviour with pre-silicon expectations and resolve complex problems involving silicon, firmware, software, power delivery, thermal, and performance to identify root causes and bring issues to resolution.\n\nDevelop and execute tuning strategies that improve power and thermal control while increasing product performance within built operating limits.\n\nApply AI/ML and data-driven methods to analyze characterization and telemetry data, identify anomalies and trends, accelerate controller tuning, and improve debug efficiency across silicon programs.\n\nWhat we need to see:\nBachelors/Master in Electronics Engineering, Electrical Engineering, or a related area, or equivalent experience.\n\nOver 5+ years of experience in silicon power/performance, post-silicon bring-up, power or thermal controller characterization, productization, or a related hardware field.\n\nSolid grasp of silicon power, performance, and thermal characteristics, encompassing voltage/frequency relationships, workloads, operating conditions, and system constraints.\n\nHands-on experience with silicon bring-up, characterization, validation, and system-level hardware debugging.\n\nExperience analyzing hardware, firmware, software, power delivery, and thermal interactions and resolving unclear technical problems to their root cause.\n\nStrong data-analysis and problem-solving skills—you can turn silicon measurements into hypotheses, build experiments, and use the results to drive engineering decisions.\n\nWays to stand out from the crowd:\nExtensive background in power or thermal controllers, DVFS, voltage/frequency management, telemetry, throttling, performance management, or silicon protection mechanisms on advanced ASIC/SoC products.\n\nContributions that improved controller behaviour, silicon performance, power efficiency, thermal management, bring-up, or productization methodology across programs.\n\nExperience connecting controller behaviour across simulation, silicon, firmware, and system-level measurements and converting findings into production tuning.\n\nExperience applying AI/ML to engineering workflows, such as controller tuning, characterization analytics, anomaly detection, or debug assistants deployed beyond personal use.\n\nWith every new architecture and process node, balancing performance against power and thermal limits becomes tougher. Our controllers are at the forefront of this issue: drawing out the performance the silicon was crafted to achieve while shielding it when workloads push its limits. If you like understanding dynamic silicon behaviour, addressing hardware-software challenges, and influencing NVIDIA products at scale, we'd love to connect!\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Chip Power Estimation Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-09-11", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Chip-Power-Estimation-Engineer_JR2025565", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking a passionate, creative, and highly motivated engineer to work on architectural power estimation for the world’s leading GPUs and SOCs. In this position, the responsibility includes development of advanced power models to estimate chip and board power under product driven use cases. You are expected to understand the high-level chip architecture, application use-cases, low power design techniques, process technology aspects which impact dynamic and leakage power, develop the estimation infrastructure, estimate power consumption under various scenarios. You will be working with architecture, design, synthesis, timing, circuit, and post silicon teams to accomplish your tasks.\n\nThis position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nArchitecture, development and correlation of power estimation models/tools for NVIDIA's chips\n\nHelp architect and develop power models for use-cases, Idle power and IO power.\n\nChip in to design the tools based on these models and their testing methodology/infrastructures\n\nCorrelate and Calibrate the power models using measured silicon data\n\nAnalyze and help decide the chip configuration and process technology options to optimize power/performance for NVIDIA's upcoming chips\n\nHelp study and contribute to Performance/Watt improvement ideas for NVIDIA's GPUs and SOCs\n\nWhat we need to see:\nB.Tech./M.Tech and 2+ years of experience related to Power / Performance estimation and optimization techniques\n\nStrong fundamentals in power including transistor-level leakage/dynamic characteristics of VLSI circuits\n\nFamiliarity with low power design techniques such as multi VT, Clock gating, Power gating, and Dynamic Voltage-Frequency Scaling (DVFS)\n\nStrong background in power estimation techniques, flows and algorithms\n\nGood programming skills - Python preferred. Good skills with object-oriented programming and design.\n\nWays to stand out from the crowd:\nExposure to lab setup including power measurement equipment such as scope/DAQ with ability to analyze board level power issues is a plus\n\nExposure to power analysis EDA tools such as PTPX/EPS\n\nGood communication skills & desire to work as a great teammate\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Applications Engineering, Sr Staff Engineer - STA", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-11", "url": "https://careers.synopsys.com/job/bengaluru/applications-engineering-sr-staff-engineer-sta/44408/100490431232", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nAre you passionate about solving the toughest timing constraints and timing challenges ? Join Synopsys’ Signoff Static Timing Analysis (STA) team and work with industry-leading tools like PrimeTime, enabling the world’s most advanced semiconductor designs.\n\nIn this customer-facing role, you will act as a technical expert in timing constraints (end to end) , timing signoff, timing ECO collaborating with semiconductor companies to support Synopsys industry-leading PrimeTime signoff solutions for advanced node designs.\n\nYou will work closely with customers, R&D, and product engineering teams to address complex timing challenges and drive methodology adoption. This is a high-visibility, customer-facing role requiring strong technical depth, execution ownership, and cross-functional collaboration with Product and R&D teams.\n\nWhat You'll Be Doing\nWork with the leading semiconductor companies to solve complex timing constraints related issues \nProvide expert guidance in timing constraints end to end and also work on the timing closure flow \nDebug critical timing issues (lint , promote, demote, block2top , setup/hold, clocking, SI, variability) \nDrive adoption of PrimeTime latest technologies and signoff flows \nWork with R&D/product teams to resolve issues and drive enhancements\nDevelop reference flows, automation scripts (Tcl/Python), and best practices \nDeliver technical training, workshops, and demos to customers\n\nThe Impact You Will Have\nStrong hands-on expertise with Synopsys PrimeTime / TCM (or equivalent STA / Constraints tools) \nDeep understanding of: \nTiming constraints (SDC) end to end \nTiming closure challenges \nStrong debugging and problem-solving skills \nProficiency in Tcl scripting (Python/Perl is a plus) \nExcellent communication and customer engagement skills\n\nWhat You'll Need\nB.Tech in Electronics and Communication Or M.Tech in VLSI/Embedded systems/Communication Systems.\nDeep hands-on expertise with Synopsys PrimeTime, TCM, or equivalent static timing analysis and constraints tools in production design environments\nStrong command of timing constraints end to end, including SDC creation, validation, and debugging across complex hierarchical designs\nExcellent communication skills with demonstrated ability to engage customers, explain technical tradeoffs, and drive issues to resolution\nExperience with RTL-based flows, mode merge, correlation, or high-performance designs like CPU, GPU, or AI/ML chips is beneficial\n\nWho You Are\nExperience with RTL based flow \nKnowledge of Mode merge and correlation \nExposure to high-performance designs (CPU, GPU, AI/ML chips) \nPrior customer-facing / application engineering experience\n\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\n\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Sr Principle Analog Designer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-09-11", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506529", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Senior Principal Analog design Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including LED drivers, SiC/MOS/IGBT/motor/GAN drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following\n\nMentor junior Analog IC design engineers  \n\nLead multiple analog IPs with IP ownership and responsibility from definition, IP execution to release to manufacturing\n\nAble to resolve complex analog problem and propose and implement the solution\n\nProvide design guidance as needed, developing schedules and monitoring progress throughout the project\n\nEvaluate intermediate and results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout\n\nCollaborate with Design Verification teams during the pre-tapeout phase of a project to ensure completion of all technical tasks before tapeout\n\nWork with systems engineers, application engineers and marketing assisting in the definition of the product to meet customer needs as well as contributing to roadmap formulation and new concept creation\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nProvide technical leadership in driving architecture design and circuit design based on high-level specifications \n\nOwn technical outcomes of design, verification, implementation, and execution of power management ICs with complexities that can span from simple regulators to complex mixed-signal designs and control loops \n\nUnderstand project goals, create a realistic schedule and resource plan, track execution schedule to plan, monitor progress, and provide full clarity to the team on the goals and objectives.\n\n#LI-RG1\n\nResponsibilities\nMentor junior Analog IC design engineers  \n\nLead multiple analog IPs with IP ownership and responsibility from definition, IP execution to release to manufacturing\n\nAble to resolve complex analog problem and propose and implement the solution\n\nProvide design guidance as needed, developing schedules and monitoring progress throughout the project\n\nEvaluate intermediate and results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout\n\nCollaborate with Design Verification teams during the pre-tapeout phase of a project to ensure completion of all technical tasks before tapeout\n\nWork with systems engineers, application engineers and marketing assisting in the definition of the product to meet customer needs as well as contributing to roadmap formulation and new concept creation\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nProvide technical leadership in driving architecture design and circuit design based on high-level specifications \n\nOwn technical outcomes of design, verification, implementation, and execution of power management ICs with complexities that can span from simple regulators to complex mixed-signal designs and control loops \n\nUnderstand project goals, create a realistic schedule and resource plan, track execution schedule to plan, monitor progress, and provide full clarity to the team on the goals and objectives \n\n#LI-RG1\n\nQualifications\nBS in Electrical Engineering or related 14 and above years of experience, or MS 12 and above years of experience\n\nQualification\n\nSolid track record of delivering multiple complex IPs with Si learnings\n\nExtensive knowledge of engineering processes, principles, and methodologies \n\nGoal and outcome-focused with the ability to handle multiple projects within the team \n\nAbility to provide technical mentorship\n\nExperience in simplifying complex problems into smaller problems and solving them as a team \n\nGood understanding of various drivers like SiC/GAN/LED, smartFET / Efuses and relevant Analog building blocks \n\nStrong Analog IC design skills, debug of complex silicon problems using simulations and/or bench testing \n\nFamiliarity with advanced Bipolar, CMOS, and High Voltage BCD technology, Process, Device Physics, Semiconductor Manufacturing processes, and their impact on Analog performance \n\nunderstanding of power transistor Design, Layout, and Robustness \n\nProficiency in leading-edge design and verification tools such as Simplis or MATLAB for architectural simulations, Cadence Spectre for schematic capture, simulation, layout, and tape-out \n\nStrong verbal and written communication skills \n\nAbility to quickly ramp on new systems and processes \n\nDemonstrated strong interpersonal, analytical and problem-solving skills \n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results \n\n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Staff Analog Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-09-11", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506531", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Staff Analog design Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including LED drivers, SiC/MOS/IGBT/motor/GAN drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following\n\nDesign and develop an analog IP block from definition to IP delivery\n\nDesign and simulation at the block/IP level during execution phase, present the block results to review team in timely manner.\n\nWork with and provide guidance to layout engg and monitors the progress of IP block layout\n\nWork with validation, product engineering and test engineering teams to enable them to measure Si performance\n\nOwn technical outcomes of design, verification, implementation, and execution of power management IPs with complexities that can span from simple regulators to complex mixed-signal designs and control loops \n\nAble to plan and execute the work in timely manner aligning with full chip schedule.\n\n#LI-RG1\n\nResponsibilities\nDesign and develop an analog IP block from definition to IP delivery\n\nDesign and simulation at the block/IP level during execution phase, present the block results to review team in timely manner.\n\nWork with and provide guidance to layout engg and monitors the progress of IP block layout\n\nWork with validation, product engineering and test engineering teams to enable them to measure Si performance\n\nOwn technical outcomes of design, verification, implementation, and execution of power management IPs with complexities that can span from simple regulators to complex mixed-signal designs and control loops \n\nAble to plan and execute the work in timely manner aligning with full chip schedule.\n\n#LI-RG1\n\nQualifications\nBS in Electrical Engineering or related 10 years of experience, or MS 8 and above years of experience\n\nQualification\n\nSolid track record of delivering block/IP level design \n\nUnderstand and execute IP design, simulations methods, boundary conditions, stress and reliability simulations, PVT/PMC/SOA simulations.\n\nGood communication skills to make detailed technical presentations  \n\nGood understanding of various building blocks like LDOs, gate drivers, comparators, linear regulators, gm-stages, charge pumps etc \n\nExperience in SiC/GAN/LED/Motor, Efuse and smart Switches etc is plus\n\nStrong Analog IC design skills, debug of complex silicon problems using simulations and/or bench testing \n\nUnderstanding of power transistor Design, Layout, and Robustness \n\nExperience in system tools such as Simplis or MATLAB for architectural simulations, Cadence Spectre for schematic capture, simulation \n\nStrong verbal and written communication skills \n\nAbility to quickly ramp on new systems and processes \n\nDemonstrated strong interpersonal, analytical and problem-solving skills \n\nAbility to work in teams\n\n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "MTS Analog Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-09-11", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506532", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Senior MTS Analog design Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including SiC drivers, MOS/IGBT drivers, LED drivers, smart Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following\n\nMentor a diverse team of experienced and junior Analog IC design engineers  \n\nLead an Analog IC design team with product ownership and responsibility from definition to release to manufacturing\n\nMake assignments for team members, providing design guidance as needed, developing schedules and monitoring progress throughout the project\n\nEvaluate intermediate and final results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout\n\nWork with systems engineers, application engineers and marketing assisting in the definition of the product to meet customer needs as well as contributing to roadmap formulation and new concept creation\n\nDefine IP test plan and execution working along with product and test engineer.\n\nDefine and develop IP for both industrial and automotive applications\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nInterface and lead discussions with the customer and/or ONsemi field sales/field applications teams to understand customer designs, problems and support as required\n\nActively participate in hiring, developing and evaluating personnel to ensure efficient operation of the organization and growth of the individuals into leader\n\nLead, motivate, provide technical mentorship to the team \n\nCollaborate with overseas design and systems teams on technical aspects, IP development, sharing of know-how \n\nProvide technical leadership in driving architecture design and circuit design based on high-level specifications \n\nOwn technical outcome of design, verification, implementation, and execution of given products with complexities at the SoC level \n\nUnderstand project goals, create a realistic schedule and resource plan, track execution schedule to plan, monitor progress, and provide full clarity to the team on the goals and objectives\n\n#LI-RG1\n\nResponsibilities\nMentor a diverse team of experienced and junior Analog IC design engineers  \n\nLead an Analog IC design team with product ownership and responsibility from definition to release to manufacturing\n\nMake assignments for team members, providing design guidance as needed, developing schedules and monitoring progress throughout the project\n\nEvaluate intermediate and final results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout\n\nWork with systems engineers, application engineers and marketing assisting in the definition of the product to meet customer needs as well as contributing to roadmap formulation and new concept creation\n\nDefine IP test plan and execution working along with product and test engineer.\n\nDefine and develop IP for both industrial and automotive applications\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nInterface and lead discussions with the customer and/or ONsemi field sales/field applications teams to understand customer designs, problems and support as required\n\nActively participate in hiring, developing and evaluating personnel to ensure efficient operation of the organization and growth of the individuals into leader\n\nLead, motivate, provide technical mentorship to the team \n\nCollaborate with overseas design and systems teams on technical aspects, IP development, sharing of know-how \n\nProvide technical leadership in driving architecture design and circuit design based on high-level specifications \n\nOwn technical outcome of design, verification, implementation, and execution of given products with complexities at the SoC level \n\nUnderstand project goals, create a realistic schedule and resource plan, track execution schedule to plan, monitor progress, and provide full clarity to the team on the goals and objectives.\n\n#LI-RG1\n\nQualifications\nMinimum Requirements\n\nBS in Electrical Engineering or related 16 and above years of experience, or MS 14 and above years of experience\n\nQualification\n\nSolid track record of releasing complex ICs/IPs to market \n\nExtensive knowledge of engineering processes, principles, and methodologies \n\nGoal and outcome-focused with the ability to handle multiple projects within the team \n\nAbility to provide technical mentorship to team \n\nExperience in simplifying complex problems into smaller problems and solving them as a team \n\nAbility to clearly articulate issues, challenges, and concerns to all levels of management \n\nSolid understanding of various drivers like SiC/GAN/LED, smartFET / Efuses and relevant Analog building blocks \n\nStrong Analog IC design skills, debug of complex silicon problems using simulations and/or bench testing \n\nFamiliarity with advanced Bipolar, CMOS, and High Voltage BCD technology, Process, Device Physics, Semiconductor Manufacturing processes, and their impact on Analog performance \n\nunderstanding of power transistor Design, Layout, and Robustness \n\nProficiency in leading-edge design and verification tools such as Simplis or MATLAB for architectural simulations, Cadence Spectre for schematic capture, simulation, layout, and tape-out \n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally \n\nStrong verbal and written communication skills \n\nAbility to quickly ramp on new systems and processes \n\nDemonstrated strong interpersonal, analytical and problem-solving skills \n\nAbility to work in teams and collaborate effectively with people in different functions \n\nAbility to take the initiative and drive for results \n\nStrong time management skills that enable on-time project delivery \n\n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "CPU Circuit Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-11", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/CPU-Circuit-Design-Engineer_JR0287114", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nYou will be part of P-core India, in the circuit design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for leading the design analysis and methodologies of the different types of memory blocks and data path subsystems. Your responsibilities will include but not limited to:\n1. Responsible for methodology enablement for memory blocks to meet over 5GHz Freq and low-power digital designs with optimal area.\n2. In depth understanding of different memory design concepts ((SRAM/RF/ROM).\n3. Expertise in Static timing analysis concepts.\n4. Close work with Layout and Floor planning teams.\n5. Back-end design implementation of new features.\n6. Expertise in Memory post silicon analysis.\n7. Good understanding of statistical variation\n\nQualifications:\nYou must possess a Masters Degree in Electrical or Computer Engineering with atleast 6 or more years of experience in related field or a Bachelors Degree with atleast 8 years of experience. Technical Expertise in synthesis, P and R tools preferred.\nPreferred Qualifications:\n1. Digital Design Experience, with High Speed, Low Power.\n2. Familiarity with Verilog.\n3. Tcl, Perl, Python scripting.\n4. Good understanding of spice simulations and analysis\n5. Strong verbal and written communication skills.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Sr Dir, Packaging Eng", "company": "Lattice", "location": "Taiwan - Remote", "date_posted": "2026-09-11", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Taiwan---Remote/Dir--Packaging-Eng_R-103114", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\n\nKey Responsibilities：\n\n1. OSAT Production Management\nOwn day-to-day production management across multiple OSAT partners, ensuring on-time delivery, output targets, and quality commitments are consistently met.\n\nServe as the primary technical point of contact for OSAT production engineering and operations teams.\n\nConduct regular production reviews, capacity reviews, and escalation meetings with OSAT partners.\n\nEstablish and enforce production control plans, work instructions, and standard operating procedures at OSAT sites.\n\nMonitor and manage OSAT performance against defined KPIs including yield, cycle time, output, and quality metrics.\n\n2. Yield Management\nOwn yield performance across all managed packages and OSAT production lines.\n\nMonitor yield trends, identify excursions, and lead root cause and corrective action (RCCA) processes in collaboration with OSAT process engineering teams.\n\nImplement and maintain statistical process control (SPC) frameworks to sustain yield at production targets.\n\nDrive systematic yield improvement programs through structured data analysis and OSAT engagement.\n\nCommunicate yield status and improvement roadmaps to internal stakeholders and leadership.\n\n3. Supplier Quality\nSupport in supplier quality programs for assigned OSAT partners, including production monitoring, audit execution, and non-conformance management.\n\nSupport Material Review Board (MRB) and Failure Review Board (FRB) activities for production escapes and non-conforming material.\n\nManage corrective and preventive action (CAPA) closure with OSAT partners, tracking effectiveness and on-time resolution.\n\nEnsure ongoing compliance with applicable quality standards and internal policy requirements (e.g., IPC, JEDEC, AEC-Q100/Q101).\n\nConduct periodic supplier quality checks and manufacturing process assessments.\n\n4. Production Ramp Management\nLead the ramp of new or transferred packages into high-volume production at OSAT sites, ensuring manufacturing readiness, capacity confirmation, and output targets are achieved.\n\nExecute run-at-rate (RAR) plans, production readiness reviews, and ramp milestone tracking.\n\nCoordinate cross-functionally with supply chain, test engineering, and product operations to ensure seamless ramp execution.\n\nIdentify and resolve ramp blockers — including process, material, equipment, and capacity constraints — in a timely manner.\n\nTransition programs from ramp phase to stable production, establishing sustaining control and monitoring plans.\n\n5. Supply & Capacity Management\nPartner with supply chain and operations teams to manage material availability, OSAT capacity allocation, and production scheduling.\n\nIdentify and proactively mitigate supply risks, including capacity shortfalls, material constraints, and single-source dependencies.\n\nSupport demand planning inputs and translate product volume requirements into actionable OSAT capacity plans.\n\nSupport escalations related to supply shortages or delivery commitments.\n\n6. Leadership & Cross-Functional Collaboration\nProvide senior technical leadership within the packaging operations organization.\n\nCommunicate production status, risk, and mitigation plans clearly to internal stakeholders and senior leadership.\n\nRequired Qualifications：\nBachelor's degree or higher in Materials Science, Electrical Engineering, Mechanical Engineering, Chemical Engineering, or a related discipline.\n\n20+ years of experience in semiconductor packaging, with a strong focus on high-volume production and OSAT management.\n\nDeep working knowledge of semiconductor assembly and test processes (e.g., flip chip, BGA, WLP/FOWLP, QFN/QFP, SiP).\n\nDemonstrated experience managing production yield, quality programs, and supply continuity at OSAT partners.\n\nProven track record leading production ramps from initial output through stable high-volume manufacturing.\n\nProficiency in quality management methodologies including CAPA, SPC, FMEA, 8D, and MRB/FRB processes.\n\nStrong communication, escalation management, and cross-functional collaboration skills; ability to operate effectively across geographies and cultures.\n\n#LI-DNP\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nTaiwanLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "GPU IP Verification Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-11", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/GPU-IP-Verification-Engineer_JR0286904", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact:\n\nAs a GPU Design Verification Engineer, you'll be at the forefront of ensuring the reliability and performance of graphics logic components, including 3D graphics and media. You will play a vital role in developing verification plans, test benches, and system simulation models to validate designs and uncover potential bugs. Collaborating closely with architects, RTL developers, and physical design teams, your contributions will directly impact the quality and efficiency of Intel's cutting-edge GPU technologies.\n\nBusiness Group:\n\nJoin Intel's innovative team dedicated to developing industry-leading GPU technologies that power advanced computing platforms. This group focuses on functional verification of graphics logic components and aims to enhance performance, reliability, and scalability across Intel's graphics solutions. By working alongside passionate professionals, you will contribute to delivering groundbreaking technologies that support Intel's mission to shape the future of computing.\n\nKey Responsibilities:\n\n- Design, develop, and implement scalable and reusable IP verification plans and test benches to ensure compliance with graphics microarchitecture specifications.\n- Execute system simulation models to analyze power, timing, and functionality while identifying and resolving bugs.\n- Debug issues in presilicon environments, root cause failures, and implement corrective measures.\n- Collaborate with GPU architects, RTL developers, and physical design teams to improve verification methodologies and ensure alignment with functional and performance goals.\n- Document verification plans, drive technical reviews, and maintain the functional verification infrastructure.\n- Participate in defining verification infrastructure and methodologies for complex architectural and microarchitectural features.\n\nQualifications:\nMinimum Qualifications:\n\n- Bachelor's degree in a relevant field (e.g., Electronics, Computer Science, Embedded Systems) with 2-3 years of hands-on experience in domain-specific areas such as functional verification, VLSI design, or testing. Skills can be demonstrated through internships, academic projects, coursework, or hands-on training.\n- Proficiency in RTL Design using Verilog/VHDL and UVM concepts, including developing testbench sequences, drivers, and scoreboards.\n- Strong foundation in digital electronics, embedded systems, computer architecture, and microcontroller/microprocessor fundamentals.\n- Working knowledge of scripting languages, including Python, Perl, or Ruby.\n- Demonstrated problem-solving, debugging, and technical analysis skills.\n\nPreferred Qualifications:\n\n- Familiarity with verifying functionalities of Media IPs (e.g., Video codecs - HEVC, AVC, AV1).\n- Experience in memory Fabric validation and GPU sub-IPs.\n- Understanding of media industry trends and technologies.\n- Strong communication and teamwork skills to drive collaboration across technical teams.\n\nTake the next step in your career by joining Intel's team of experts dedicated to pushing the boundaries of technology. Your contributions will help shape the future of computing, and we look forward to exploring your unique perspective and skills.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Power Architecture Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-09-11", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Power-Architecture-Engineer_JR2025546", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. \n\nNVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! \n\nWhat you’ll be doing:  \n\nBe part of NVIDIA Power Architecture Group that owns end-to-end power aspects such as - ASIC power analysis, power architecture, low power design, power-aware verification, advanced power methodologies, UPF methodologies, power feature bring-up on silicon, and post-Si power correlation for NVIDIA's family of products. \n\nContributing to power analysis by helping to architect, develop, verify & correlate power estimation models/tools for NVIDIA's products \n\nBe part of the team that architects & designs system-level power features for optimizing the dynamic and leakage power dissipation for different usecases.  \n\nWork on power verification which includes structural, functional & power aware verification of power features of NVIDIA products by coming up with test plans, write testcases, build test bench components like Monitors, assertions and coverage points & own verification convergence across RTL, Gates and Silicon.  \n\nValidate the effectiveness of the power features on silicon, conduct studies and contribute to the Performance/Watt improvement ideas.  \n\nHelp build power management solutions and drive innovation in energy efficiency across NVIDIA’s product portfolio.  \n\nWhat we need to see:  \n\nB.Tech./M.Tech with 1+ years of experience related to Power such as Power analysis, Power Design, Power Aware Verification, UPF methodologies and Power Correlation \n\nStrong fundamentals in power including transistor-level leakage/dynamic characteristics of VLSI circuits  \n\nStrong fundamentals in digital design and verilog \n\nFamiliarity with low power design techniques such as multi-VT, Clock gating, Power gating, Voltage Islands and Dynamic Voltage-Frequency Scaling (DVFS)  \n\nGood background in power estimation techniques, flows and algorithms  \n\nKnowledge of power intent formats - UPF/CPF or similar \n\nExperience in Static Power check tools like VCLP/CLP or similar & Dynamic Power verification tools like VCS-NLP or equivalent \n\nWays to stand out from the crowd:  \n\nGood debugging and problem-solving skills \n\nStrong communication skills and ability & desire to work as a great teammate \n\nGood programming skills - Python preferred (Good skills with object-oriented programming & design) preferred.  \n\nExposure to Power analysis tools (such as PTPX, EPS) or exposure to lab setups for power measurements like scope/DAQ with ability to analyze board level power issues is a plus  \n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.  \n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Mixed Signal Design Verification Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-11", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Mixed-Signal-Design-Verification-Engineer_JR0285752-1", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact:\n\nAs a Mixed Signal Design Verification Engineer, you will be instrumental in ensuring Intel's success in delivering innovative and high-quality mixed signal components. By leveraging your technical expertise in verification methodologies, you will validate and enhance the functionality of mixed signal IPs (example PCIE, UCIE, USB4/Type-C PHYs). Your work will directly contribute to Intel's leadership in cutting-edge technology, ensuring the performance, reliability, and efficiency of our products. This role offers a unique opportunity to collaborate with cross-functional teams and contribute to the development of industry-leading solutions.\n\nKey Responsibilities:\nPerform functional verification of mixed signal logic components, including analog behavioral modeling, to ensure compliance with design specifications.\n\nDevelop comprehensive IP verification plans, test benches, and environments to achieve thorough coverage of mixed signal microarchitecture specifications.\n\nDefine and execute simulation models to verify design performance, analyze power and timing, and identify and resolve design bugs.\n\nConduct root cause analysis and implement corrective measures to address failing tests in the pre silicon environment.\n\nCollaborate with digital and analog architects, RTL developers, and physical design teams to refine and optimize architectural and microarchitectural features.\n\nLead technical reviews of test plans and validation proofs with design and architecture teams, ensuring meticulous documentation of findings and processes.\n\nMaintain and enhance functional verification methodologies, infrastructure, and tools to align with evolving industry standards and best practices.\n\nQualifications:\nMinimum Qualifications:\nBachelor's or Master's degree in electronics and communication or electrical engineering, VLSI Engineering, or a related field.\n\n4+ years of experience with a Bachelor's degree, or 3+ years of experience with a Master's degree in ASIC or IP verification, subsystem and function coverage.\n\nProficiency in mixed signal verification and hands on in IP verification using System Verilog, UVM, and Verilog.\n\nHands-on experience with industry-standard EDA tools, such as Synopsys VCS, Cadence Xcelium, or Mentor Questa, for simulation and verification.\n\nStrong scripting skills in Python, Perl, or Tcl for automation and efficiency in testbench development.\n\nFamiliarity with standard protocols including JTAG, IJTAG, CRI, and APB, as well as multi-clock domain mixed signal designs.\n\nExpertise in constraint-random test generation, root cause analysis, and debugging of complex mixed signal designs.\n\nPreferred Qualifications:\nExperience with low-power design techniques, including UPF and clock gating, to optimize power consumption.\n\nKnowledge of Formal Property Verification tools and version control systems such as Git or Perforce.\n\nStrong collaboration and communication skills with the ability to thrive in a dynamic, multi-disciplinary team environment.\n\nJoin us to drive verification excellence at Intel and shape the future of technology. Apply today and be part of our journey to deliver transformative innovations.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Cyber Security Operations Analyst (Tier 2 SOC)", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-09-11", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Cyber-Security-Operations-Analyst--Tier-2-SOC-_2604545", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nJoining Marvell as a CyberSecurity Analyst, you will play a critical role in protecting Marvell's people, data, intellectual property, and infrastructure from evolving cyber threats. As part of the Security Operations Center (SOC), the central nervous system of Marvell's cybersecurity organization, you will be responsible not only for monitoring, detection, investigation, and response, but also for driving innovation through Artificial Intelligence (AI), Security Automation, and proactive Threat Hunting.\nThis role requires a security professional who thinks beyond traditional SOC operations, continuously stays ahead of emerging threats and industry trends, and proactively identifies opportunities to leverage automation and AI technologies to improve detection, response, efficiency, and security outcomes. You will collaborate across global security teams, engineering teams, and business stakeholders to strengthen Marvell's cyber defenses while helping shape the future of SOC operations.\nWhat You Can Expect\nSecurity Operations & Incident Response\nProvide primary triage, investigation, analysis, and operational support for security alerts and events across the enterprise.\nPerform advanced correlation using SIEM, EDR, NDR, threat intelligence platforms, forensic tools, malware analysis tools, and data analytics platforms.\nConduct real-time incident handling, including intrusion investigation, threat containment, remediation, and recovery activities.\nAnalyze security incidents to determine root cause, attack path, scope of compromise, and business impact.\nDevelop and maintain incident response procedures, playbooks, and detection methodologies.\nEffectively communicate security events, risks, and response activities to technical and executive stakeholders.\nThreat Hunting & Detection Engineering\nConduct proactive threat hunting exercises using internal telemetry, threat intelligence, attacker TTPs, and hypothesis-driven hunting methodologies.\nLeverage MITRE ATT&CK and other threat frameworks to identify detection gaps and improve security visibility.\nTransform threat hunting findings into operationalized detections, use cases, analytics rules, and response playbooks.\nIdentify emerging attacker techniques and develop corresponding monitoring and alerting strategies.\nCollaborate with threat intelligence teams to operationalize Indicators of Compromise (IOCs), Indicators of Attack (IOAs), and adversary TTPs.\nSecurity Automation & SOC Optimization\nIdentify opportunities to automate repetitive operational tasks and improve SOC efficiency through scripting, orchestration, and workflow automation.\nDesign and implement SOAR playbooks and automated response workflows.\nDrive false-positive reduction initiatives through analytics tuning, machine learning insights, and detection optimization.\nContinuously improve detection coverage, incident response speed, and operational metrics through automation and innovation.\nAI Security & Innovation\nResearch, evaluate, and recommend AI-driven security technologies and capabilities for SOC operations.\nIdentify opportunities to leverage Generative AI, Machine Learning, and Security Copilots to improve threat detection, investigation, triage, threat hunting, and reporting.\nDevelop ideas and use cases for AI integration across cybersecurity operations.\nAssess security risks associated with AI systems deployed within the enterprise.\nMonitor emerging AI-related threats, adversarial machine learning attacks and industry trends\nContribute to the development of AI security monitoring use cases, detections, and response procedures.\nUse AI-assisted analytics responsibly to accelerate investigations while maintaining analytical rigor.\nStay current on the evolving cybersecurity landscape, attacker methodologies, AI advancements, vulnerability trends, and emerging technologies.\nActively contribute innovative ideas that enhance detection, automation, AI adoption, and overall SOC maturity.\nParticipate in purple team exercises, tabletop simulations, attack emulations, and security validation activities.\n\nWhat We're Looking For\n4+ years of experience as a SOC Analyst, Threat Hunter, Detection Engineer, or Incident Responder, preferably supporting a global enterprise with 5,000+ employees.\nDemonstrated experience in security operations, threat hunting, incident response, automation and detection engineering.\nExperience integrating automation into SOC workflows and operational processes.\nExperience evaluating or utilizing AI/ML technologies within cybersecurity workflows is highly desirable.\nTechnical Expertise\nDeep understanding of MITRE ATT&CK framework with proven experience building detections, hunting methodologies, and response playbooks based on attacker TTPs.\nStrong knowledge of modern attack techniques, cyber kill chain methodologies, and advanced persistent threat (APT) operations.\nExperience conducting intelligence-driven and hypothesis-driven threat hunts.\nAbility to convert threat intelligence and hunting results into actionable detections\nExperience with one or more SIEM platforms such as Microsoft Sentinel, Splunk, QRadar, Elastic, or Chronicle.\nExperience with SOAR platforms and security workflow automation.\nProficiency with DLP technologies and data protection controls.\nStrong working knowledge of SOC tools and technologies.\nAI & Emerging Security Requirements\nStrong understanding of AI security concepts, risks, and attack methodologies.\nDeep Knowledge of AI based attacks and risks\nAbility to identify opportunities where AI can improve detection, investigation, response, reporting, and SOC productivity.\nInterest in evaluating and operationalizing AI solutions to enhance cybersecurity outcomes.\nProblem Solving & Innovation\nDemonstrated ability to think creatively and challenge conventional approaches to security operations.\nStrong analytical and investigative mindset with the ability to solve complex problems amid ambiguity.\nPassion for continuous learning, staying current with cybersecurity and AI trends, and bringing innovative ideas to the organization.\nSelf-motivated with a track record of delivering end-to-end solutions in fast-paced, technology-driven environments.\nCommunication\nStrong verbal and written communication skills.\nAbility to communicate effectively with executives, technical teams, and business stakeholders.\nPreferred Certifications\nGIAC Certifications (GCFA, GCIH, GCIA, GMON, GCTI, etc.)\nCertified Ethical Hacker (CEH)\nAI Security Certifications (where applicable)\n\nThis role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.\nAdditional Compensation and Benefit Elements\nWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\n\nInterview Integrity \nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\n\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\n\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n\n#LI-RV1", "jd_status": "stored"}, {"title": "Senior/Staff Engineer, Design Verification", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-10T09:27:57.632000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000148720369-senior-staff-engineer-design-verification", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Be a part of end‑to‑end verification execution for SOC owning complex digital IP’s and subsystems from specification to sign‑off\nDefine and drive IP‑level verification strategies, including test plans, coverage models, and closure criteria\nDevelop scalable, reusable UVM‑based verification environments for IP and subsystem verification\nLead functional, code, assertion, and cross‑coverage closure, ensuring high‑quality sign‑off with clear metrics\nApply AI/ML‑assisted verification techniques to accelerate coverage convergence, identify stimulus gaps, and optimize regression efficiency\nDrive constraint random and directed test methodologies for thorough protocol, corner‑case, and stress verification\nCollaborate with RTL, Architecture, Emulation, and SoC Verification teams to ensure seamless IP integration\nReview IP specifications and work with architects to translate requirements into robust verification plans and checkers\nDevelop and deploy advanced checkers, scoreboards, assertions (SVA), and protocol monitors\nWork with EDA vendors to evaluate and adopt next‑generation verification, coverage, and analytics tools\nMentor junior engineers and promote best‑in‑class verification practices and continuous improvement\nSupport Gate‑Level Simulation (GLS), low‑power verification, and post‑silicon debug when required.\nEnsure IP deliverables meet quality, schedule, and reusability expectations for SoC integration.\n\nBachelor’s or master’s degree in Electronics Engineering\n2 - 8 years of experience in SoC Verification domains and have working knowledge of industry standard EDA toolkits.  \nStrong expertise in UVM‑based testbench architecture and development\nProven experience in metric‑driven verification, including functional and code coverage closure\nDeep understanding of SystemVerilog, UVM, assertions (SVA), and verification best practices\nExperience with directed and constrained‑random verification methodologies\nExperience debugging complex design issues in simulation, emulation, and post‑silicon environments\nProficiency in Verilog/SystemVerilog, with working knowledge of C/C++, Shell scripting\nStrong analytical, problem‑solving, and communication skills\nPreferred/Plus Qualifications\nHands‑on experience using AI/ML‑based verification tools for:Coverage gap analysis\nTest stimulus optimization\nRegression triage and coverage acceleration\n\nScripting expertise in Python, Perl, or TCL for automation and analytics\nExposure to formal verification and hybrid formal‑simulation flows\nFamiliarity with high‑speed or complex IPs, such as:H.264\nSecurity, debug, or safety‑crititical\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "DV Methodology Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-10T06:59:00+00:00", "url": "https://global-external-amd.icims.com/jobs/91868/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. SILICON DESIGN ENGINEER 2 The AMD Radeon Technology Group (RTG) develops GPU ASIC design that enhances our daily lives as we are entering an age of immersive computing. The RTG hardware engineering teams are distributed across Canada, US, China and India. The team in India is engaging on the enthusiast and high performance GPUs. As part of the RTG Design Verification Infrastructure and Architecture team, your team will be responsible for scoping out and managing the testbench environment that is used for developing the design as well as verifying the design features. This is built up from basics like how work spaces are setup, how IPs are integrated and interacted in a System-On-Chip environment, how the tools/flows are developed to automate processes, and how tests are written and regressed. As always, the team is dedicated to come up with innovative solution to overcome new challenges related to specific project requirements and time-to-market. KEY RESPONSIBILITIES • Will work with various IP & SOC teams across all our sites (GFX, Memory controller, Multimedia engines, IOs, PCIE…) to understand the test bench and DV infrastructure needs and work with the Infra leads in India and North America to implement them. • Will help scoping out the testbench architecture and the simulation configuration • Will help in development of fast initialization sequence for the SOC • Will help supporting scripts related to managing the track resources • Will help supporting test regression flows (perl/mysql/PHP) to support our project development • Will help debugging and enhancing simulation testcases and models • Will help to review new tools and options to improve simulation performance (new flows, tracking, analyzing reports, recoding, benchmarking, …) with the 3rd party vendor • May help supporting some simulation debug and verilog/system verilog coding • May help to support some gate level simulation debug SKILLS AND EXPERIENCE REQUIREMENTS • B.E/B.Tech/M.E/M.Tech in Computer Science/Electrical/Electronic Engineering • BE/B.Tech with 3+ years’ of experience or M.Tech with 1+ years of experience in Infrastructure development with SOCs or IPs verification • Good C/C++ software skills, UVM and Verilog • Good understanding for digital system and computer organization • Should be a confident coder and be comfortable debugging general hardware/software problems. • Must communicate well both written and orally • Must be organized and multitask well WHAT YOU WILL LEARN You will gain valuable experience in different aspects of ASIC design verification. Depends on the time you join the team, you may be able to experience the full project cycle – from project planning to implementation to tapeout. This team is essential to the success of AMD as a growing company. It is a very exciting environment and you will be working with the very best in our technology. You will be working on some of the most exciting projects the industry has to offer. #LI-AA1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Engineer - Physical Design", "company": "Ericsson", "location": "Bangalore,Karnataka,India", "date_posted": "2026-09-10T05:55:53+00:00", "url": "https://jobs.ericsson.com/careers/job/563121776308106", "is_hardware": true, "platform": "eightfold", "jd_text": "Grow with us\n\nAbout this Opportunity \nJoin Ericsson's cutting-edge journey to shape the future of 5G networks! As a Physical Design Engineer, you'll work on pioneering digital ASIC designs vital to Ericsson's mobile network infrastructure. Our team, responsible for the final critical stage of chip design before fabrication, thrives on Lean and Agile principles, promoting close collaboration, daily progress-sharing, and continuous improvement. If you're passionate about advanced technology and ready to make a meaningful impact in telecom, this role is crafted just for you. \n\nAt Ericsson, we support your growth, offering opportunities to advance your skills while contributing to game-changing 5G/6G technologies. Here, you'll find a supportive, innovative environment focused on quality, teamwork, and career development. Join us and help shape the future of telecom! \nWe are hiring a Physical Design Engineer to own the physical implementation flow on high-performance, low-power SoC designs at advanced process nodes. Your primary focus will be die-level floorplanning, full-chip place-and-route, and timing-driven physical closure — while also contributing to synthesis and static timing analysis (STA) signoff as secondary responsibilities. You will work closely with RTL design, synthesis, DFT, and verification teams throughout the full design cycle from netlist hand-off to GDSII sign-off. \n\nWhat you will do:\n\nFloorplanning & Physical Implementation\nOwn die-level and block-level floorplanning using Cadence Innovus or Synopsys ICC2 — defining die size, I/O ring placement, power ring topology, and macro placement strategies. \nPerform early floorplan exploration to evaluate area, aspect ratio, and pin assignment trade-offs in collaboration with the architecture and package teams. \nPlan and implement hierarchical design partitioning — define interface timing budgets, feedthrough corridors, and block-level pin constraints for clean top-level integration. \nCoordinate macro placement with memory compilers, analog IP, and hard macros; manage blockage and halo constraints to minimize routing congestion. \nDrive floorplan-driven synthesis feedback loops with the synthesis team; iterate on netlist placement to reduce post-route timing and congestion surprises. \nPower Planning & Power Delivery Network (PDN) \nDesign and implement the on-chip power delivery network — power rings, power straps, and rail routing — to meet IR drop and electromigration (EM) targets. \nCoordinate with power analysis teams on static and dynamic IR drop budgets; iterate on PDN to achieve sign-off across all power domains. \nImplement and validate multi-voltage domain power structures per UPF/CPF — power switches, isolation cells, level shifters, and always-on logic placement. \nPerform early power grid analysis to identify PDN weaknesses before detailed routing; collaborate with the package team on C4 bump and power delivery co-design. \nPlace and Route \nExecute full-chip and block-level placement and routing targeting timing, congestion, and power objectives across all MMMC corners. \nDrive timing-driven placement strategies — useful skew, path-specific placement constraints, and pre-CTS timing optimization to reduce hold and setup violations. \nPerform clock tree synthesis (CTS) — define clock tree goals, buffer library selection, skew targets, and clock mesh/shielding strategies for high-frequency designs. \nManage routing for signal integrity — differential pairs, shielding of sensitive nets, and antenna rule compliance across all metal layers. \nPerform detail routing, via optimization, and metal fill insertion to meet density DRC and sign-off requirements. \nPhysical Closure \nDrive iterative timing closure — setup and hold — through ECO-driven placement and routing iterations in collaboration with the STA team. \nPerform DRC, LVS, and ERC checks using Synopsys IC Validator or Cadence PVS; own physical verification sign-off to GDSII tape-out. \nCoordinate with power analysis teams to correlate PTPX switching activity maps with IR drop hotspots identified during post-route analysis. \nOwn physical implementation QoR metrics — WNS, TNS, congestion, DRC count, and power — and present sign-off status across tape-out milestones. \nDevelop and maintain PnR run scripts, methodology documentation, and automation flows in Tcl/Python for reuse across projects and technology nodes. \nSynthesis and STA Support \nSupport physical-aware synthesis runs using Fusion Compiler — review QoR results and provide floorplan-driven feedback on netlist quality, congestion hotspots, and pre-CTS timing. \nContribute to STA reviews using PrimeTime (PT) — specifically for timing paths affected by physical implementation changes (CTS, ECO routing, buffer insertion). \n\nThe skills you bring:\n\nB.Tech / M.Tech / M.S. in Electronics Engineering, VLSI Design, Computer Engineering, or a related field with \n10+ years in physical implementation, floorplanning, or place-and-route roles \nExpert-level proficiency with Cadence Innovus and/or Synopsys ICC2 / Fusion Compiler \nStrong experience in die-level floorplanning, macro placement, and PDN design \nHands-on clock tree synthesis (CTS) experience across high-frequency, multi-clock designs \nExpertise in timing-driven physical closure and ECO-based hold/setup fixing \nFamiliarity with physical verification tools (IC Validator, PVS) and DRC/LVS sign-off \nWorking knowledge of synthesis (Fusion Compiler) and STA (PrimeTime) \nProficiency in Tcl; Python scripting a strong plus \nAt least one tape-out on 7nm or below \n\nNice to have:\n\nExperience with low-power physical implementation (UPF/CPF, power domain crossings, multi-Vt strategies) \nKnowledge of advanced routing constraints — signal integrity shielding, differential pair routing, antenna fixing \nDFT physical implementation experience — scan chain reordering, BIST placement, and test-mode timing closure \nExposure to formal equivalence checking (Formality, Conformal) post-ECO \nEDA Tools & Environment \nCadence Innovus, Synopsys ICC2, Fusion Compiler, Synopsys IC Validator, Cadence PVS, PrimeTime, Design Compiler, Tcl / Python \n\n.\n\n“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”\n\nWhat happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.We encourage you to consider applying to jobs where you might not meet all the criteria. We recognize that we all have transferrable skills, and we can support you with the skills that you need to develop.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.\n \nPrimary country and city: India (IN) || Bangalore\nJob details: Developer\nJob Stage: Job Stage 6\nPrimary Recruiter: Ashwini Manda\nHiring Manager: Govinda Raju", "jd_status": "stored"}, {"title": "Validation Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-10T05:55:51.480000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000148677559-validation-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "The Post-Silicon Validation team within the Performance Computing Power Division is building a world-class organization of highly skilled engineers across multiple global sites. Our mission is to push the boundaries of silicon validation for industry-leading integrated circuits enabling high-power, high-efficiency power management systems. \nWe are committed to delivering the highest level of validation quality by continuously improving test coverage, measurement accuracy, repeatability, automation, and execution efficiency while reducing overall validation time. \nAs a Validation Engineer, you will be part of a multidisciplinary global development team and play a key role in ensuring that every new product fully meets its electrical, functional, and performance specifications before release to production. You will work closely with Design, Applications, Product Engineering, Quality, and System teams to identify, debug, and resolve silicon and system-level issues while supporting aggressive product development and New Product Introduction (NPI) schedules. \nFor our office in Bangalore, we are looking for a passionate engineer who thrive on innovation, enjoy solving complex technical challenges, and is committed to delivering high-quality results in a fast-paced environment. \nPrincipal Responsibilities :\nValidate analog, digital, mixed-signal, and power management ICs against electrical, functional, and performance specifications. \n\nPrepare advanced laboratory test setups for complex silicon evaluation. \n\nContribute to the design of custom evaluation boards and supporting hardware for silicon characterization. \n\nDevelop measurement scripts using Python. \n\nPerform data acquisition, statistical analysis, result correlation, preparation of detailed technical reports and silicon evaluation summaries. \n\nEvaluate silicon performance at device, board, and system level, identifying, documenting, and tracking silicon and application issues. \n\nCollaborate closely with Design, Applications, Firmware, Product Engineering, and Quality teams to investigate and resolve silicon and system-level bugs. \n\nContribute innovative ideas that enhance validation quality, automation, productivity, and time-to-market. \n\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related discipline with about 2 years of work-related experience. \n\nGood level of expertise in lab automation, ability to propose improvements to existing measurements techniques. \n\nProficiency with Python programming with particular use for lab automation hardware environments  \n\nBasic knowledge of power management applications in consumer electronic   \n\nBoard level analog and digital circuit design expertise for PCB schematic creation  \n\nStrong analytical and debugging skills with a systematic approach to problem solving. \n\nSelf-motivated, proactive, and able to manage priorities while delivering high-quality results under demanding project schedules. \n\nGoals-oriented and able to deliver on-time results under tight schedules  \n\nExcellent communication skills and ability to collaborate effectively within international cross-functional teams. \n\nImportant \nConcise and precise communication, internal and with customers   \n\nCross cultural awareness and sensitivity within multisite and multicultural environments  \n\nFlexible to undertake occasional international travel  \n\nExcellent command of verbal and written English  \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Engineer - ASIC Backend Synthesis", "company": "Ericsson", "location": "Bangalore,Karnataka,India", "date_posted": "2026-09-10T05:54:22+00:00", "url": "https://jobs.ericsson.com/careers/job/563121775518761", "is_hardware": true, "platform": "eightfold", "jd_text": "Grow with us\n\nJoin Ericsson’s cutting-edge journey to shape the future of 5G networks! As an Physical Synthesis Engineer, you’ll work on pioneering digital ASIC designs vital to Ericsson’s mobile network infrastructure. Our team, responsible for the final critical stage of chip design before fabrication, thrives on Lean and Agile principles, promoting close collaboration, daily progress-sharing, and continuous improvement. If you’re passionate about advanced technology and ready to make a meaningful impact in telecom, this role is crafted just for you. \nAt Ericsson, we support your growth, offering opportunities to advance your skills while contributing to game-changing 5G/6G technologies. Here, you’ll find a supportive, innovative environment focused on quality, teamwork, and career development. Join us and help shape the future of telecom! \nWe are hiring a Physical Synthesis Engineer to own the synthesis flow and constraint development on high-performance, low-power SoC designs. Your primary focus will be physical-aware synthesis, floorplan-driven netlist optimization, and QoR closure — while also contributing to static timing analysis (STA) signoff as well. You will work closely with RTL design, place-and-route, and DFT teams throughout the full design cycle. \n\nWhat you will do:\n\nPhysical-Aware Synthesis (PAS) \nExecute physical-aware and floorplan-driven synthesis flows to minimize post-layout timing and congestion surprises. \nIntegrate synthesis with P&R tools for early physical feedback loops — congestion-aware optimization, placement-aware buffering, and pre-CTS timing. \nCollaborate with P&R engineers on DEF/floorplan hand-off; iterate on netlist quality to reduce downstream ECO effort. \nPerform flat and hierarchical synthesis for large designs; manage partitioning and interface timing budgets. \nPerform formal or equivalence check on the netlist at block or top level. \nQoR & Optimization \nTrack and report key QoR metrics — timing slack, area, cell count, power — across design iterations and process corners. \nIdentify and resolve synthesis bottlenecks: critical path restructuring, datapath optimization, and register retiming. \nProvide RTL coding guideline feedback to design teams to improve synthesizability and QoR from the source. \nManage technology library characterization inputs: Liberty (.lib), LEF, and UPF/CPF for multi-voltage designs. \nOwn synthesis QoR sign-off checklist and contribute to tape-out readiness reviews. \nStatic Timing Analysis  \nRun block-level and full-chip STA using PrimeTime (PT) for timing analysis across PVT corners. \nSupport MMMC (Multi-Mode Multi-Corner) timing closure; analyze and triage timing violations with P&R and synthesis teams. \nReview and validate SDC constraints developed during synthesis against post-layout STA results. \nContribute to clock domain crossing (CDC) checks and timing exception audits during signoff. \n\nThe skills you bring:\n\n8+ years in physical synthesis or logic design implementation \nExpert-level use of Fusion Compiler \nStrong SDC constraint authoring and management skills \nExperience with physical-aware synthesis flows and P&R hand-off \nWorking knowledge of STA (PrimeTime) \nProficiency in Tcl; Python scripting a strong plus \nAt least one tape-out on 7nm or below\n\nNice to have:\n\nFamiliarity with low-power methodologies (UPF/CPF, multi-Vt, clock gating) \nUnderstanding of PTPX-based power analysis flows \nDFT synthesis experience (scan, BIST, boundary scan) \nFamiliarity with congestion-aware and timing-driven P&R closure \nEDA Tools & Environment \nDesign Compiler, Fusion Compiler, Synopsys PrimeTime, Formality, Tcl/Python.\n\nEducation & Background\n\nB.Tech / M.Tech / M.S. in Electronics Engineering, VLSI Design, Computer Engineering, or a related field. \nStrong foundation in digital logic design, CMOS circuit theory, and standard-cell library concepts. \nExcellent scripting and automation skills; comfort with large, multi-million gate designs. \nStrong communication skills — able to clearly present QoR status, risks, and trade-offs to cross-functional teams. \n\n.\n\n“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”\n\nWhy join Ericsson?At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.\n \nWhat happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.\n \nPrimary country and city: India (IN) || Bangalore\nReq ID: 783577", "jd_status": "stored"}, {"title": "Staff Engineer, STA and Synthesis", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-10T05:08:59.029000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000148673159-staff-engineer-sta-and-synthesis", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "The STA Engineer is responsible for ensuring robust timing closure and signoff readiness for block- and full-chip designs across all modes and corners. This role owns timing constraint development and validation, performs detailed setup/hold and variation-aware analysis, and partners closely with Synthesis, CTS, Physical Design, and Design teams to debug violations and drive ECO-based optimizations through tapeout.\nResponsibilities:\nPerform full-chip and block-level Static Timing Analysis (STA) across all modes and corners.\nAnalyze and debug setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations.\nWork closely with Physical Design, Synthesis, CTS, and Design teams to achieve timing closure.\nDevelop and maintain timing constraints including SDC creation, validation, and signoff readiness.\nDrive timing closure through ECO implementation and timing optimization.\nAnalyze timing impact due to process, voltage, and temperature variations.\nSupport timing signoff for pre-layout and post-layout stages.\nPerform cross-functional reviews for timing convergence and provide recommendations.\nGenerate timing reports and communicate closure status to project stakeholders.\n\n7–10 years of experience in Static Timing Analysis (STA) and timing closure for block and/or full-chip designs.\nStrong understanding of CMOS fundamentals, timing concepts, and semiconductor design flow.\nHands-on experience in setup/hold analysis, path-based analysis, OCV/AOCV/POCV, derates, and MMMC concepts.\nGood understanding of clock tree, clock uncertainty, latency, skew, and jitter.\nExperience in timing constraints development and debugging.\nStrong knowledge of SDC, timing exceptions, false paths, multicycle paths, and case analysis.\nFamiliarity with timing closure techniques and ECO methodologies.\nHands-on experience with industry-standard STA tools such as Synopsys PrimeTime or Cadence Tempus.\nGood scripting skills in Tcl, Perl, or Python.\nAbility to analyze and resolve timing violations independently.\nNice to have\nExposure to low-power timing analysis and UPF/CPF-aware STA.\nFamiliarity with SI-aware timing, Crosstalk analysis, and IR-drop-aware timing closure.\nKnowledge of advanced technology nodes and variation-aware signoff methodologies.\nExposure to automation and flow development.\nExperience in cross-functional collaboration with PD, RTL, and Signoff teams.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Lead Logic Design Engineer", "company": "Astera Labs", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-10T04:35:10-04:00", "url": "https://job-boards.greenhouse.io/asteralabs/jobs/4729060005", "is_hardware": true, "platform": "greenhouse", "jd_text": "Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\n\nLead Logic Design Engineer – UALink IP/Subsystem \n\nExperience \n\n6–10 years \n\nJob Summary \n\nLead RTL and microarchitecture development for UALink-based IP/subsystems, focusing on high-bandwidth, low-latency data movement and scalable interconnect design. \n\nKey Responsibilities \n\nLead UALink IP/subsystem RTL development. \n\nTranslate protocol requirements into detailed microarchitecture. \n\nDesign high-performance control and data-path logic. \n\nWork on buffering, arbitration, flow control, ordering, and error handling. \n\nDevelop and review SystemVerilog RTL. \n\nDrive performance, area, power, and latency optimization. \n\nCollaborate with verification, SoC integration, and physical design teams. \n\nDebug complex functional and integration issues. \n\nReview RTL and mentor engineers. \n\nSupport silicon debug and issue resolution. \n\nRequired Skills \n\nStrong RTL and microarchitecture experience. \n\nExperience with high-speed interconnects. \n\nStrong understanding of data movement, flow control, arbitration, and buffering. \n\nExcellent SystemVerilog/Verilog skills. \n\nExperience with CDC, lint, synthesis, and timing. \n\nStrong debugging and technical leadership skills. \n\nPreferred \n\nDirect UALink experience. \n\nExperience with PCIe, CXL, CHI, CCIX, Ethernet, or similar technologies. \n\nExperience with AI/accelerator or high-performance compute SoCs. \n\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.", "jd_status": "stored"}, {"title": "RISCV Infra System IP DV - Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-10T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720642084", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nJob Area Engineering - IP Design Verification\nLocation: Bangalore\n\nEducational Requirements\nBachelor/Master’s Degree in Electronics & Communication / Micro Electronics\n\nJob responsibilities include\n3 to 15 years of solid experience in IP/Sub System design verification\nExpertise on UVM, System Verilog DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage)\nDevelop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench\nWork closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure\nDebug of regression signatures and identifying bug fixes\nUnderstanding of bus protocols like CHI/AHB/AXI/ACE/ACE-Lite and Interconnect concepts\nKnowledgeable on ARM / RISCV system architecture, Memory Management, Virtual Memory concepts, Core sight architecture, power management fundamentals\nUnderstanding of multi-core ARMv8/v9 CPU architecture, coherency protocols and virtualization\nCommunication and collaboration skills to work with a large world-wide design organization\nPost-Silicon bring-up and HW-SW debug experience would be a plus\nProficiency in Gen AI skills, Scripting languages (Python or Perl) for Automation initiatives is desirable\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RISCV Infra System IP DV - Sr Staff Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-10T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720655462", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nJob Area Engineering - IP Design Verification\nLocation: Bangalore\n\nEducational Requirements\nBachelor/Master’s Degree in Electronics & Communication / Micro Electronics\n\nJob responsibilities include\n3 to 15 years of solid experience in IP/Sub System design verification\nExpertise on UVM, System Verilog DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage)\nDevelop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench\nWork closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure\nDebug of regression signatures and identifying bug fixes\nUnderstanding of bus protocols like CHI/AHB/AXI/ACE/ACE-Lite and Interconnect concepts\nKnowledgeable on ARM / RISCV system architecture, Memory Management, Virtual Memory concepts, Core sight architecture, power management fundamentals\nUnderstanding of multi-core ARMv8/v9 CPU architecture, coherency protocols and virtualization\nCommunication and collaboration skills to work with a large world-wide design organization\nPost-Silicon bring-up and HW-SW debug experience would be a plus\nProficiency in Gen AI skills, Scripting languages (Python or Perl) for Automation initiatives is desirable\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SoC STA/Timing Engineer, Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-10T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719467110", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Description:\n7 to 10 years of relavant experience is a must\n\nSTA Setup & Signoff: Perform STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs for SoC & SubSystem\n\nTiming Analysis & Debug: Validate and debug timing across multiple PVT conditions using tools like PrimeTime and Tempus.\n\nFlow Optimization: Run STA flows and correlate Spice to STA results.\n\nMethodology Development: Evaluate timing methodologies/tools across technology nodes and automate STA/PD flows using TCL/Perl/Python.\n\nCross-Functional Collaboration: Work closely with design, DFT, synthesis, technology, CAD and physical implementation teams.\n\nLow-Power Techniques: Knowledge of clock gating, power gating, and multi-voltage designs.\n\nECO Timing Flow: Handle timing ECOs (DMSA, tweaker, PrimeClosure) and logical equivalence checks (RTL to Netlist). \n\nRequired Skills\nStrong expertise in STA fundamentals, AOCV/POCV concepts, CTS, and timing constraints.\n\nHands-on experience with STA tools: PrimeTime, Tempus.\n\nFamiliarity with ASIC back-end flows: ICC2, Innovus.\n\nKnowledge of signal integrity, cross-talk noise, and parasitic extraction.\n\nScripting proficiency: TCL, Perl, Python.\n\nMentoring junior engineers in different areas of timing flows and methodologies\n\nUnderstanding of Spice simulations: Hspice, FineSim, Monte Carlo analysis. \n\nPreferred Experience\nDriving timing convergence at chip-level and hard-macro level.\n\nExposure to RTL-to-GDSII flows.\n\nGood technical writing and communication skills for cross-team collaboration\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RTL Design(Audio)-Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-10T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720215972", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    3+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n\nPrincipal Duties and Responsibilities:\n•    Applies Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Assists in the assessment of complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Custom CPU Physical Design Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-10T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720238163", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\n1 yrs experience in Physical Design and timing signoff for high speed cores.\n\nShould have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology.\n\nMasters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design.\n\nExperience in leading block level or chip level Physical Design, STA and PDN activities.\n\nWork independently in the areas of RTL to GDSII implementation.\n\nAbility to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc.\n\nKnowledge of low power flow (power gating, multi-Vt flow, power supply management etc.)\n\nCircuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.)\n\nTcl/Perl scripting Willing to handle technical deliveries with a small team of engineers.\n\nStrong problem-solving skills\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RTL Design(Audio)-Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-10T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720186004", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    1+ year of experience with circuit design (e.g., digital, analog, RF).\n•    1+ year of experience utilizing schematic capture and circuit simulation software.\n•    1+ year of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n\nPrincipal Duties and Responsibilities:\n•    Applies Hardware knowledge to assist in the planning, optimization, verification, and testing of electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Provides support for the integration of features and functionality into hardware designs in line with proposals or roadmaps.\n•    Assists in conducting simulations and analyses of designs as well as with the implementation of designs with the best power, performance, and area.\n•    Collaborates with team members to assist in the implementation of new requirements and incorporation of the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Assists in the evaluation, characterization, and development of manufacturing solutions for leading edge products in processes and bring up product to meet customer expectations and schedules.\n•    Assists in the evaluation of reliability for materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Assists in the assessment of common design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works under supervision.\n•    Decision-making affects direct area of work and/or work group.\n•    Requires verbal and written communication skills to convey basic, routine factual information.\n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RTL Design (DDR) - Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-10T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718351780", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Description\n\nSkills & Experience\nMTech/BTech in EE/CS with 5 to 12 years of ASIC design experience.\n\nExperience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA\n\nGood understanding of DDR families (LP/PC) and generations (DDR2/3/4/5/6) is added advantage.\n\nUnderstanding of protocols like AHB/AXI/ACE/CHI is desirable.\n\nExperience with post-silicon bring-up and debug is a plus.\n\nAble to work with teams across the globe and possess good communication skills.\n\nHands on experience in Multi Clock designs, Asynchronous interface is a must.\n\nHands on experience in Low power SoC design is required.\n\n Responsibilities\nMirco architecture & RTL development and its validation for linting, clock-domain crossing and DFT rules.\n\nWork with functional verification team on test-plan development and waveform debugs at core, sub-system, SoCs levels.\n\nHands on experience in constraint development and timing closure.\n\nUPF writing, power aware equivalence checks and low power checks.\n\nSupport performance debugs and address performance bottle necks.\n\nProvide support to sub-system, SoC integration and chip level debug.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    8+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates complex features and functionality into hardware designs in line with proposals or roadmaps for complex products.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the novel manufacturing of solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for complex Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making is significant in nature and affects work beyond immediate work group.\n•    Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. \n•    Has a moderate amount of influence over key organizational decisions.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Layout Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-10T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720973544", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Services Group, Engineering Services Group > Layout Engineer\nGeneral Summary:\nDevelops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues.\n\nMinimum Qualifications:\n•    Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.\n                                                                    OR\nAssociate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.\n                                                                    OR\nHigh School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.\n\n•    2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap).\n\n*Completed advanced degrees in a relevant field may be substituted for up to two years (Master’s = one year, Doctorate = two years) of the general custom layout design work experience in a relevant domain (e.g., analog, mixed signal, RF, digital design).\n\n3-5 years of experience in Custom layout and Memory Layout design.\n\nMemory Leafcell layout library design from scratch including top level integration.\n\nProficient in SKILL and PERL for custom tiling and automations\n\nGood knowledge on different types of memory architectures and compilers\n\nGood knowledge in optimized layout design for better performance.\n\nSound knowledge & hands on experience in Finfet technology, DRC limitations and work closely with CAD engineers for better customization of DRC and tiling layout.\n\nProficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions.\n\nProficient in Cadence Virtuoso layout editor and Calibre physical verification flow\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU Physical Design Senior Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-10T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718852670", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\n2+  yrs experience in Physical Design and timing signoff for high speed cores.\n\nShould have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology.\n\nMasters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design.\n\nExperience in leading block level or chip level Physical Design, STA and PDN activities.\n\nWork independently in the areas of RTL to GDSII implementation.\n\nAbility to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc.\n\nKnowledge of low power flow (power gating, multi-Vt flow, power supply management etc.)\n\nCircuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.)\n\nTcl/Perl scripting Willing to handle technical deliveries with a small team of engineers.\n\nStrong problem-solving skills.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Design Engineer(FPGA RTL)", "company": "Lattice", "location": "Hyderabad, India", "date_posted": "2026-09-10", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Hyderabad-India/Senior-Design-Engineer-FPGA-RTL-_R-103070", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nWe are seeking a Senior IP Design engineer with significant hands-on experience in FPGA RTL design, logic simulation, FPGA compilation and timing closure and hardware debug.\n \nRequirements\nKey Skills\nHands-on experience in FPGA RTL design, logic verification, debug and timing closure\nProgramming skills (e.g.: C/C++, Perl, TCL or Python)\nExperience in high-speed IO protocols (e.g.: PCIe, Ethernet, CPRI, JESD204B/C)\nExperience in hardware validation and debug is a plus\nExperience in soft IP packaging, example design and testbench development will be an added advantage\n \nEducation and General:\nBS/MS/PhD in Electronics or Computer Engineering minimum of 5 years of FPGA system design experience.\nIndependent and self-motivated, capable of executing under dynamic environment and uncertainties\n\n#LI-DNP\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Formal Verification Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-09-10", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Formal-Verification-Engineer_JR2025305", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nWe are currently seeking an experienced Formal Verification Engineer with strong CPU/GPU and verification fundamentals to work in NVIDIA's Central Formal team based in Bangalore. NVIDIA builds CPUs and GPUs  that powering up the next generation AI and HPC workloads. This position will have you crafting and optimising formal verification flows across CPU/GPU projects and resolving tool issues for design teams with tool vendors. Additionally, you'll verify the micro-architecture using formal verification tools to employ the latest model checking and equivalence checking techniques. You will be expected to understand the design & implementation, define the verification scope, and ensure design correctness. You will use advanced formal techniques to obtain full proofs, or sufficient bounded proofs, of the design while working with architects, designers, pre- and post-silicon verification teams to accomplish your tasks.\n\nWhat you’ll be doing:\nThe specification, implementation, and maintenance of an integrated end-to-end formal verification flow for the formal verification team.\n\nDeveloping scripts to automate the verification process.\n\nReview formal setups and proofs with design and verification teams.\n\nMaintain and extend assertion libraries, including support for both simulation and FV.\n\nIdentifying key behaviours for verification of DUT and creating a verification plan.\n\nDeveloping verification environment including environment assumptions, assertions and cover properties in context of the verification plan.\n\nApplying various FV techniques to prove correctness of digital designs.\n\nDebugging RTL to identify causes of failure scenarios.\n\nWhat we need to see:\nBachelors/Masters in Electronics & Communications or Computer Science or electrical engineering from a reputed engineering college.\n\nMinimum 2+ years of industry experience on formal techniques for verification.\n\nStrong analytical skills to tackle hard problems.\n\nExcellent command of scripting.\n\nStrong knowledge of architectures of CPU designs and digital logic.\n\nGood understanding of abstraction techniques for effective verification.\n\nHands-on experience with HDLs such as Verilog / System Verilog.\n\nUnderstanding of temporal logic assertions.\n\nPreferable experience with a variety of Formal Verification Tools\n\nStrong communication skills are required along with the ability to work in a dynamic product oriented team and collaborate effectively across sites.\n\nWays to stand out from the crowd:\nWorked on various pieces of CPU/GPU unit/microarchitecture verification\n\nBackground with complex verification projects that had used formal techniques for closure.\n\nExperience of collaborating with geographically diverse cross-functional teams\n\nA history of mentoring junior engineers and interns a huge plus.\n\nWith competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us and, due to unprecedented growth, our elite engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Package Design Staff/Sr.Staff Engineer", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-09-10", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Package-Design-Staff-Engineer_2604408", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nAbout Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.\nYour Team, Your Impact\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, Marvell’s innovative technologies enable new possibilities and power the next generation of performance driven systems.\n\nWithin this ecosystem, Marvell’s central advanced packaging organization plays a critical role in delivering next generation connectivity and compute products. The organization brings deep expertise in architecture, package design, and electrical performance, including SI/PI to develop advanced IC packages that support high speed interfaces. This work directly shapes product performance, reliability, and time to market, making it a key contributor to Marvell’s overall technology leadership.\nWhat You Can Expect\nWhat You Can Expect\nMarvell’s Central Engineering team is seeking a talented High-speed IC package development engineer to contribute to the development of advanced microelectronic packages.\nThe engineer will be responsible for driving microelectronic package development from concept through tapeout, working with package architects and technical leads to select appropriate technologies and ensure manufacturability, performance, reliability, and cost compliance.\nKey responsibilities include developing C4 and BGA ball maps optimized for SI/PI and layout efficiency; planning and validating netlist mappings across dies, interposers, and substrates; and defining die placement, padstacks, net assignments, and package‑level connectivity.\nThe engineer will create and maintain Package Requirement Documents (PRDs) detailing die arrangements, stackups, and design constraints.\n\nWhat We're Looking For\nWhat We're Looking For\n5-12 years of related professional experience.\nPrevious experience developing netlists and schematics for large, complex packages.\nPrevious experience developing C4 and BGA ball maps for high‑pin‑count designs.\nProficiency with design tools Cadence OrbitIO / Integrity System Planner (ISP) or equivalent\nStrong foundational understanding of package design, including design rules, breakout, place and route, signal shielding, reference planes, power distribution, and pinout optimization across package and system requirements.\nSolid grasp of SI/PI fundamentals at the substrate, board, and system levels; familiarity with running and interpreting signal and power simulations is a plus.\nKnowledge of 2D, 2.5D, and emerging packaging architectures such as CoWoS‑S/R/L, EMIB, CPO, and CPC.\nHigh‑level understanding of thermal and mechanical package constraints (e.g., warpage, TIM).\nExperience contributing to tool, process, and flow development, including library maintenance and basic scripting for automation.\nFamiliarity with foundry design rules and substrate manufacturing constraints.\nDemonstrated ability to work across cross‑functional teams and global time zones; strong interpersonal skills and willingness to learn.\nExperience collaborating with chip and board design and electrical simulation teams to optimize package and system co‑design.\nExperience collaborating with chip and board design, and electrical simulation teams for co‑design and optimization.\nStrong communication, presentation, and documentation skills.\n\nThis role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.\nAdditional Compensation and Benefit Elements\nWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\n\nInterview Integrity \nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\n\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\n\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n\n#LI-CP1", "jd_status": "stored"}, {"title": "Package Design Principal Engineer", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-09-10", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Package-Design-Senior-Staff-Engineer_2604409", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nAbout Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.\nYour Team, Your Impact\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, Marvell’s innovative technologies enable new possibilities and power the next generation of performance driven systems.\n\nWithin this ecosystem, Marvell’s central advanced packaging organization plays a critical role in delivering next generation connectivity and compute products. The organization brings deep expertise in architecture, package design, and electrical performance, including SI/PI to develop advanced IC packages that support high speed interfaces. This work directly shapes product performance, reliability, and time to market, making it a key contributor to Marvell’s overall technology leadership.\nWhat You Can Expect\nWhat You Can Expect\nMarvell’s Central Engineering team is seeking a talented High-speed IC package development engineer to contribute to the development of advanced microelectronic packages.\nThe engineer will be responsible for driving microelectronic package development from concept through tapeout, working with package architects and technical leads to select appropriate technologies and ensure manufacturability, performance, reliability, and cost compliance.\nKey responsibilities include developing C4 and BGA ball maps optimized for SI/PI and layout efficiency; planning and validating netlist mappings across dies, interposers, and substrates; and defining die placement, padstacks, net assignments, and package‑level connectivity.\nThe engineer will create and maintain Package Requirement Documents (PRDs) detailing die arrangements, stackups, and design constraints.\n\nWhat We're Looking For\nWhat We're Looking For\n\n13-16 years of related professional experience.\nPrevious experience developing netlists and schematics for large, complex packages.\nPrevious experience developing C4 and BGA ball maps for high‑pin‑count designs.\nProficiency with design tools Cadence OrbitIO / Integrity System Planner (ISP) or equivalent\nStrong foundational understanding of package design, including design rules, breakout, place and route, signal shielding, reference planes, power distribution, and pinout optimization across package and system requirements.\nSolid grasp of SI/PI fundamentals at the substrate, board, and system levels; familiarity with running and interpreting signal and power simulations is a plus.\nKnowledge of 2D, 2.5D, and emerging packaging architectures such as CoWoS‑S/R/L, EMIB, CPO, and CPC.\nHigh‑level understanding of thermal and mechanical package constraints (e.g., warpage, TIM).\nExperience contributing to tool, process, and flow development, including library maintenance and basic scripting for automation.\nFamiliarity with foundry design rules and substrate manufacturing constraints.\nDemonstrated ability to work across cross‑functional teams and global time zones; strong interpersonal skills and willingness to learn.\nExperience collaborating with chip and board design and electrical simulation teams to optimize package and system co‑design.\nExperience collaborating with chip and board design, and electrical simulation teams for co‑design and optimization.\nStrong communication, presentation, and documentation skills.\n\nThis role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.\nAdditional Compensation and Benefit Elements\nWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\n\nInterview Integrity \nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\n\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\n\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n\n#LI-CP1", "jd_status": "stored"}, {"title": "Photonics PDK Development Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-10", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Photonics-PDK-Development-Engineer_JR0286974", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nIn this role, you will help shape the future of Intel's Silicon Photonics design ecosystem by enabling the development and deployment of production-ready PDKs, design automation methodologies, and verification solutions that support Intel's internal silicon photonic ecosystem. Through innovations in Physical Verification, PCell development, AI-assisted electronic-photonic design automation workflows, and automated CI/CD infrastructure, you will drive higher design quality, faster technology adoption, and improved engineering efficiency, directly contributing to Intel's leadership in high-performance optical connectivity and next-generation data center technologies.\n\nBusiness group\nIntel's Integrated Photonics Solutions (IPS) is at the forefront of silicon photonics integration and commercialization, pioneering technologies that drive high-volume manufacturing and data center advancements. The team is dedicated to developing state-of-the-art photonic devices and systems, enabling smaller form factors, higher speeds, and innovative solutions for AI-driven bandwidth growth. The organization also delivers advanced Electronic-Photonic Design Automation (EPDA) solutions, software platforms, and design enablement infrastructure that power Intel's silicon photonics ecosystem. IPS is responsible for developing and enabling internal product PDKs, design flows, automation frameworks, verification methodologies, and scalable cloud-based design environments that accelerate photonic product development across Intel. By joining IPS, you will be part of a forward-thinking group focused on advancing silicon photonics technologies and enabling the broader Intel photonics ecosystem through the development of EPDA tools, design flows, methodologies, internal product PDKs, verification frameworks, and design enablement infrastructure. The team's work accelerates photonic product innovation and foundry adoption while driving next-generation solutions for AI datacenter scale-up, laser sources, pluggable optics, NPO, CPO, OCI, PICs, and future optical communication technologies.\n\nKey Responsibilities\n\t• Develop, validate, and maintain production-ready Silicon Photonics PDKs supporting internal product development and foundry enablement.\n\t• Collaborate with PDK architects and domain experts to define and implement Electronic-Photonic Design Automation (EPDA) Tools, Flows, and Methods (TFM) for PIC design and manufacturing.\n\t• Develop and support Physical Verification methodologies, including DRC, LVS, ERC, reliability checks, rule decks, and signoff flows using Siemens Calibre, Cadence Physical Verification solutions, and Synopsys IC Validator.\n\t• Design, develop, and maintain PCells, design automation solutions, and reusable IP to improve PDK quality, scalability, and designer productivity.\n\t• Apply AI and automation technologies to accelerate design enablement workflows, validation, engineering productivity, and quality improvement initiatives.\n\t• Develop and maintain design enablement infrastructure, including cloud computing environments, EDA tool integrations, storage, licensing, and engineering productivity platforms.\n\t• Build and support CI/CD pipelines for automated validation, testing, packaging, qualification, and release of PDKs, tools, and methodologies.\n\t• Partner with design, process, manufacturing, and foundry teams to gather requirements and deliver robust design enablement solutions.\n\t• Contribute to technical leadership, innovation, and continuous improvement initiatives across PDK, Physical Verification, Physical Design, design automation, and infrastructure development.\n\nQualifications:\nMinimum Qualifications\n- Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or Photonics with 6+ years of experience in Electronic Design Automation (EDA), Electronic-Photonic Design Automation (EPDA), PDK development, design enablement, CAD software development, or physical verification.\n- Experience with custom analog, mixed-signal, and/or Photonic Integrated Circuit (PIC) design flows, including a strong understanding of the design-to-tapeout lifecycle.\n- Experience developing and supporting physical verification solutions using industry-standard EDA platforms such as Siemens Calibre, Synopsys IC Validator (ICV), and Cadence PVS/Pegasus.\n- Strong proficiency with Cadence Virtuoso design environments, including SKILL programming, design automation, PCell development, and flow customization.\n- Strong programming and scripting skills in Python and Linux shell environments (tcsh, bash, Tcl, or equivalent).\n- Experience working in Unix/Linux environments, software development methodologies, version control systems, and automation frameworks.\n- Familiarity with DRC, LVS, ERC, parasitic extraction, verification methodologies, and automated validation flows.\n- Strong technical problem-solving, debugging, and collaboration skills in a multidisciplinary engineering environment.\n\nPreferred Qualifications\n- Master's degree with 4+ years of relevant experience, or Ph.D. with 2+ years of relevant experience, in Electronic Design Automation (EDA), Electronic-Photonic - Design Automation (EPDA), Silicon Photonics, PDK development, Physical Verification, or related fields.\n- Experience developing, validating, and releasing production-ready Silicon Photonics PDKs, PCells, and design enablement infrastructure.\n- Experience developing Electronic-Photonic Design Automation (EPDA) Tools, Flows, and Methods (TFM) for analog, mixed-signal, and photonic design environments.\n- Advanced expertise in Cadence Virtuoso design flows, custom layout automation, SKILL development, PCell architecture, schematic-driven layout (SDL), and design environment customization.\n- Experience developing advanced parametric cells (PCells) and layout automation solutions for Photonic Integrated Circuit (PIC) design, including curvilinear - PCell development and customization using Cadence Virtuoso and CurvyCore technologies.\n- Experience developing and validating physical verification rule decks using Siemens Calibre SVRF/TVF, Synopsys ICV, and Cadence PVS/Pegasus.\n- Experience with hierarchical PIC design, layout automation, floorplanning, and design productivity solutions.\n- Experience building CI/CD pipelines, automated regression frameworks, release automation systems, and validation infrastructure for PDKs and design tools.\n- Experience supporting engineering infrastructure, cloud computing environments, EDA deployment, storage, licensing, and scalable compute platforms.\n- Experience applying AI/ML technologies to design automation, verification, engineering productivity, or workflow optimization.\n- Familiarity with foundry enablement, semiconductor manufacturing processes, technology qualification, and multi-foundry design ecosystems.\n- Demonstrated ability to influence technical direction, mentor engineers, and collaborate effectively across design, process, manufacturing, and software development organizations.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Electrical Engineer", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2026-09-10", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/Electrical-Engineer_R2628170-1", "is_hardware": true, "platform": "workday", "jd_text": "Who We Are\n\nApplied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI and accelerating the commercialization of next-generation semiconductor chips. Join us and push the boundaries of materials science and engineering in a company at the foundation of the electronics industry. The work we do together advances the world’s technology. \n\nWhat We Offer\n\nLocation:\nBangalore,IND\nYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. \n\nAt Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. \n\nRole Responsibilities: \nDesign or modify electrical or electronic engineering assemblies, layouts, schematics, drawings or specifications of moderate scope under general supervision \n\nPerform basic engineering analysis under general supervision \n\nPerform and generate basic engineering test reports; generate related alpha/gamma documentation for product releases \n\nCoordinate the procurement and assembly of electrical or electronic components and equipment, and identify sources of critical parts and subsystems to resolve technical issues \n\nTroubleshoot a variety of moderately complex electrical problems \n\nImplement concepts for product issues and electrical solutions of moderate difficulty \n\nAssist in the development of electrical product specifications \n\nClearly communicate complex information in straightforward situations\n\nMinimum Qualifications:\nBachelor’s degree\n\n2-4 years of related experience\n\nPreferred Qualifications:\nA solid understanding of the industry’s key business drivers  \n\nGood communication/interpersonal skills to explain complex information to others  \n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nAssignee / Regular\nTravel:\nYes, 20% of the Time\nRelocation Eligible:\nYes\n\nApplied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "Principal Physical Design Engineer", "company": "NXP", "location": "Hyderabad", "date_posted": "2026-09-10", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Hyderabad/Lead-Physical-Design-Engineer_R-10063208", "is_hardware": true, "platform": "workday", "jd_text": "Job Summary:\n\nWe are seeking a highly experienced Lead PD Engineer for AI NPU to lead and contribute to the physical design and implementation of complex, high-performance semiconductor integrated circuits. The individual is responsible from RTL synthesis, Floor planning, Placement, CTS, Routing, Timing convergence (STA). The individual contributes to problem solving related to physical design. Contributes to define best Physical design strategy per technology node.\n\nJob Responsibilities\n* Execute physical design activities including floorplanning, power planning, place and route, clock tree synthesis, and static timing analysis (STA).\n* Collaborate with physical verification (DRC, LVS, Antenna) and resolve related issues.\n* Collaborate with power integrity analysis (IR drop, EM) and optimize designs for power efficiency.\n* Collaborate with design, verification, and DFT teams to ensure seamless integration and achieve project milestones.\n* Analyze and resolve design issues related to timing, area, and power.\n* Develop and maintain scripts for automation and efficiency improvements in the physical design flow.\n* Contribute to the continuous improvement of physical design methodologies and flows.\n* Generate comprehensive reports and documentation of design implementation.\n\nJob Qualifications\n* Bachelor's or Master's degree in VLSI or Electronics Engineering or a related field.\n* Minimum 8 years of experience in digital physical design of complex SoCs or ASICs.\n* Proficiency with industry-standard EDA tools for physical design (e.g., Cadence Innovus/Genus/Tempus or Synopsys Fusion Compiler/PrimeTime, Mentor Calibre).\n* Solid understanding and experience of physical design concepts including floorplanning, placement, routing, clock tree synthesis, and physical verification.\n* Strong knowledge of Static Timing Analysis (STA) and timing closure techniques.\n* Experience with scripting languages such as Tcl, Perl, or Python.\n* Familiarity with deep sub-micron process technologies.\n* Good understanding of VLSI design principles and semiconductor physics.\n* Excellent problem-solving skills and attention to detail.\n* Ability to work effectively in a collaborative team environment.\n* Good communication skills, both written and verbal.\n\nMore information about NXP in India...\n\n#LI-9415", "jd_status": "stored"}, {"title": "5G RAN System Verification Engineer", "company": "Ericsson", "location": "Bangalore,Karnataka,India", "date_posted": "2026-09-09T14:06:35+00:00", "url": "https://jobs.ericsson.com/careers/job/563121777187839", "is_hardware": true, "platform": "eightfold", "jd_text": "Join our Team\n\nAbout the Opportunity\n \nAt Ericsson, we are the world leader in 5G innovation and deployment, powering a connected future where technology improves the way we live and work. With unmatched expertise and market penetration in 5G New Radio (NR), we are shaping the future of communication and pioneering advancements that will lead us into the era of 6G. \nReliability earns trust. As part of our RAN System Verification team, you will verify, troubleshoot and deliver Ericsson’s 5G New Radio (NR) solutions on high-performance General Purpose Processors (GPP), with sharp focus on performance, scalability and quality. You will work in advanced lab environments to validate system behaviour under realistic and extreme traffic conditions, influencing release readiness and overall product quality.\n \nWhat will you do\n \n•    Drive end-to-end system-level verification of 5G RAN technologies to secure release readiness.\n•    Perform capacity and performance verification of RAN systems under high-load traffic scenarios comprising Max supported UEs per cell/DU, throughput (DL/UL), control plane capacity and mobility under load.\n•    Troubleshooting system behaviour, performance, throughput, latency, resource load and QoS/QoE indicators for complex issues by analysing logs, traces, KPIs across multiple protocol layers (PHY, MAC, RLC, PDCP, IP).\n•    Perform requirement analysis for feature integration and verification to ensure alignment with customer expectations.\n•    Contribute to continuous improvements of products, test coverage, verification frameworks, automation and CI/CD pipelines.\n•    Collaborate closely with RAN development, integration/CI and product management teams.\n•    Continuously develop competence in relevant technical domains and modern verification practices. Apply AI-assisted verification methods.\n \nWhat you will bring\n\n•    Bachelor’s or Master’s degree in Computer Engineering, Computer Science, Electrical Engineering or equivalent.\n•    2 to 4 years of hands‑on experience in system‑level verification, configuring, deploying, and troubleshooting LTE/5G NR baseband and radio equipment.\n•    Strong understanding of wireless communication systems (LTE/5G NR), RAN architecture/protocol stack and 5G NR air-interface technologies\n•    Demonstrated experience analysing and troubleshooting performance issues at PHY/MAC layer.\n•    Working knowledge of system level KPIs (throughput, latency, resource load, QoS/QoE) and the ability to identify performance bottlenecks.\n•    Experience working in Linux environments and overall IP networking.\n•    Programming/Automation/scripting skills (for example Python, Bash, Java). Understanding of CI/CD concepts.\n•    Exposure to configuration management and automation tools (for example Git, Gerrit, Jenkins).\nGood to have:\n•    Exposure to Cloud-Native RAN, O-RAN Architecture.\n•    Experience with UE simulators, channel emulators, fading technologies and lab test tools.\n•    Experience with commercial UE chipset platform testing (Qualcomm, MediaTek etc).\n•    Knowledge of Cloud Native principles.\n•    Software development skills, particularly in Java and Python.\n“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”\n\nWhy join Ericsson?At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.\n \nWhat happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.\n \nPrimary country and city: India (IN) || Bangalore\nReq ID: 790648", "jd_status": "stored"}, {"title": "Senior Staff Engineer Design", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-09-09T11:56:19+00:00", "url": "https://jobs.infineon.com/careers/job/563808959307102", "is_hardware": true, "platform": "eightfold", "jd_text": "Are you passionate about Analog & Mixed-Signal Design and eager to work on cutting-edge power solutions? We are looking for talented engineers to design and develop innovative analog and mixed-signal circuits in CMOS and Power Technologies, with a strong focus on DC-DC converters and power management applications.\nIn this role, you'll work on critical system blocks such as POR, Bandgap References, LDOs, Amplifiers, and Power Conversion Circuits, collaborating across architecture, physical design, validation, and production teams to deliver high-performance semiconductor solutions.\n\nYour role\nKey responsibilities in your new role\n\nDesign\nanalog and mixed-signal modules in CMOS and Power Technologies, with a\nparticular focus on DC-DC converter for power management ICs\nDesign\nanalog and mixed-signal system resource blocks including POR, Bandgap, LDO,\namplifiers\nAssist\nin defining the requirements for analog and mixed-signal blocks, aligning them\nwith IP Module architecture, and ensuring compliance with requirements through\ndocumentation\n\nProvide\nessential support to physical design engineers, post-silicon validation,\nproduction testing, and other critical activities extending beyond the design\nphase\n\nYour profile\nQualifications and skills to help you succeed \n\nA\nmaster’s degree in electrical/Electronic Engineering, Physics or equivalent\nfield of studies \nExperience\nin analog and mixed-signal circuit design, particularly in CMOS and Power\nTechnologies\nGood\nAnalytical skills and very good understanding of Analog Design Familiarity with\nhigh-efficiency power conversion, such as DC-DC converters, is highly desirable\n\nExperience\nin post silicon debug; Proficiency in computer-aided design tools and\nmethodologies\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nVidhi Thakkar", "jd_status": "stored"}, {"title": "Experienced Engineer - FPGA Verification", "company": "Ericsson", "location": "Bangalore,Karnataka,India", "date_posted": "2026-09-09T09:49:13+00:00", "url": "https://jobs.ericsson.com/careers/job/563121776966545", "is_hardware": true, "platform": "eightfold", "jd_text": "Join our Team\n\nAbout this opportunity:\n \nAre you passionate about driving innovation and working on groundbreaking 5G and 6G mobile communication solutions? Do you thrive in a flexible working culture, where new insights are championed, and you are encouraged to develop new skills?\n \nWe are looking for an FPGA Verifier to join the Ericsson Silicon organization. You will work with dedicated engineers who are passionate about developing world-class Radio and RAN Compute products. You will play a key role in the FPGA team—defining verification strategies and implementing environments for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, you'll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity and teamwork\n\nYou will do:\n\nParticipate in test plan, test case, code review and ensure high standards.\nAssist in defining verification requirements and strategies for FPGA/ASIC projects.\nMeasure functional and code coverage metrics, driving towards completion targets.\nAnalyse simulation results, debug issues, and collaborate with design teams for resolution.\nContribute to the continuous improvement of products, tools, and processes.\nMaintain and enhance regression test suits and support continuous integration flows.\nFollow and contribute to the team’s best practices, processes, and documentation standard.\n\nYou will bring:\n\n3 to 5 years of experience in FPGA/ASIC verification.\nFamiliarity with the process of verifying IPs and subsystem components.\nGood expertise in verification methodologies such as UVM.\nProficiency in SystemVerilog.\nAbility to understand, reuse existing code effectively and/or write reusable, module level and well documented code for verification.\nExperience with simulation and verification tools like Xcelium, VCS, QuestaSim.\nExperience with waveform viewers, debugging techniques and coverage-driven verification.\nExperience with scripting languages such as Python, Tcl, shell scripting, etc.\nUnderstanding of digital design fundamentals.\nFamiliarity in version control GIT.\nA problem-solving attitude, self-motivation, and eagerness to learn and contribute.\nExcellent English verbal and written communication skills\nBachelor/Master degree in Electronics or Computer Engineering or equivalent.\n\n*\n\n“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”\n\nWhy join Ericsson?At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.\n \nWhat happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.\n \nPrimary country and city: India (IN) || Bangalore\nReq ID: 788469", "jd_status": "stored"}, {"title": "Senior/Staff Engineer, Design Verification", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-09T03:08:32.553000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000148401099-senior-staff-engineer-design-verification", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.\nWe are seeking a highly experienced IP Design Verification Engineer to join the Verification R&D team at Renesas. In this role, you will be a part of team responsible for SOC verification, ensuring first‑pass silicon success through building verification environment from scratch using best in class methodologies, metric‑driven verification, and intelligent coverage convergence using AI tools.\nYou will play a key technical role in defining verification strategies, architecting testbenches, defining Test Plans tracing Requirements, driving coverage closure using advanced automation and AI‑assisted techniques, and collaborating closely with Architecture, RTL, chip top, and Validation teams to deliver high‑quality, reusable IPs for next‑generation microcontrollers and microprocessors.\nResponsibilities:\nBe a part of end‑to‑end verification execution for SOC owning complex digital IP’s and subsystems from specification to sign‑off\nDefine and drive IP‑level verification strategies, including test plans, coverage models, and closure criteria\nDevelop scalable, reusable UVM‑based verification environments for IP and subsystem verification\nLead functional, code, assertion, and cross‑coverage closure, ensuring high‑quality sign‑off with clear metrics\nApply AI/ML‑assisted verification techniques to accelerate coverage convergence, identify stimulus gaps, and optimize regression efficiency\nDrive constraint random and directed test methodologies for thorough protocol, corner‑case, and stress verification\nCollaborate with RTL, Architecture, Emulation, and SoC Verification teams to ensure seamless IP integration\nReview IP specifications and work with architects to translate requirements into robust verification plans and checkers\nDevelop and deploy advanced checkers, scoreboards, assertions (SVA), and protocol monitors\nWork with EDA vendors to evaluate and adopt next‑generation verification, coverage, and analytics tools\nMentor junior engineers and promote best‑in‑class verification practices and continuous improvement\nSupport Gate‑Level Simulation (GLS), low‑power verification, and post‑silicon debug when required.\n\nBachelor’s or Master’s degree in electronics Engineering\n5-12 years of experience in SoC Verification domains and have working knowledge of industry standard EDA toolkits.  \nStrong expertise in UVM‑based testbench architecture and development\nProven experience in metric‑driven verification, including functional and code coverage closure\nDeep understanding of SystemVerilog, UVM, assertions (SVA), and verification best practices\nExperience with directed and constrained‑random verification methodologies\nExperience debugging complex design issues in simulation, emulation, and post‑silicon environments\nProficiency in Verilog/SystemVerilog, with working knowledge of C/C++, Shell scripting\nStrong analytical, problem‑solving, and communication skills\nPreferred/Plus Qualifications\nHands‑on experience using AI/ML‑based verification tools for:Coverage gap analysis\nTest stimulus optimization\nRegression triage and coverage acceleration\n\nScripting expertise in Python, Perl, or TCL for automation and analytics\nExposure to formal verification and hybrid formal‑simulation flows\nFamiliarity with high‑speed or complex IPs, such as:H.264\nSecurity, debug, or safety‑crititical\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Staff/Sr Staff Engineer, Physical Design", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-09T02:43:30.289000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000148400239-staff-sr-staff-engineer-physical-design", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.\nRenesas India is seeking an experienced Staff / Senior Staff Physical Design Engineer to lead subsystem- and block-level physical implementation and closure for complex hierarchical SoCs at advanced technology nodes. This role requires deep expertise in timing, congestion, power integrity, and clocking methodologies, along with strong cross-functional collaboration skills. While this role does not own SoC-level physical design, it plays a critical role in aligning subsystem implementation with overarching SoC strategies.\nKey Responsibilities\nLead block- and subsystem-level physical design closure, including timing closure, congestion mitigation, power integrity, and overall physical implementation quality\nCollaborate closely with SoC-level physical design teams to align on clocking strategies, floorplanning intent, and integration requirements, without direct ownership of SoC-level execution\nApply deep understanding of clocking methodologies to ensure subsystem-level clock domains integrate cleanly into the broader SoC clock architecture\nDevelop, refine, and scale subsystem closure methodologies, flows, and automation, improving predictability, quality, and execution efficiency\nMentor and guide physical design engineers within subsystem teams, promoting best practices, technical rigor, and methodology adoption\nWork cross-functionally with RTL design, STA, power, verification, and backend teams to ensure smooth handoffs and robust closure\nProactively identify, assess, and mitigate physical design risks, coordinating closely with SoC teams to manage impacts and drive solutions\n\n7+ years of experience in physical design, with a strong focus on subsystem-level closure for complex hierarchical SoCs\nStrong expertise in:Timing closure and constraint management\nCongestion analysis and resolution\nPower integrity and power-aware physical implementation\nBlock and subsystem-level physical design flows\n\nSolid understanding of SoC-level floorplanning and clocking methodologies, including:Clock domain partitioning\nClock tree architecture\nSkew management\nClock gating\n\n(Candidate is expected to collaborate effectively at the SoC level, not lead these activities.)\n\nHands-on experience with industry-standard tools such as:Synopsys ICC2, Fusion Compiler, PrimeTime\nCadence Innovus, Tempus, Certus\nSignoff and analysis platforms\n\nProficiency in scripting and automation using Tcl, Python, and/or Perl\nDeep knowledge of end-to-end SoC design flows, with strong collaboration experience across timing, power, clocking, verification, and backend teams\nStrong understanding of low-power design techniques and power-aware implementation methodologies\nEducation\nBTech or MTech in Electronics and Communication, Electrical Engineering, Computer Science, or a related field\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Staff/Sr Staff Engineer, Physical Design", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-09T02:37:05.149000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000148400009-staff-sr-staff-engineer-physical-design", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Renesas India is seeking an experienced Senior Staff Physical Design Engineer to lead subsystem- and block-level physical implementation and closure for complex hierarchical SoCs at advanced technology nodes. This role requires deep expertise in timing, congestion, power integrity, and clocking methodologies, along with strong cross-functional collaboration skills. While this role does not own SoC-level physical design, it plays a critical role in aligning subsystem implementation with overarching SoC strategies.\nKey Responsibilities\nLead block- and subsystem-level physical design closure, including timing closure, congestion mitigation, power integrity, and overall physical implementation quality\nCollaborate closely with SoC-level physical design teams to align on clocking strategies, floorplanning intent, and integration requirements, without direct ownership of SoC-level execution\nApply deep understanding of clocking methodologies to ensure subsystem-level clock domains integrate cleanly into the broader SoC clock architecture\nDevelop, refine, and scale subsystem closure methodologies, flows, and automation, improving predictability, quality, and execution efficiency\nMentor and guide physical design engineers within subsystem teams, promoting best practices, technical rigor, and methodology adoption\nWork cross-functionally with RTL design, STA, power, verification, and backend teams to ensure smooth handoffs and robust closure\nProactively identify, assess, and mitigate physical design risks, coordinating closely with SoC teams to manage impacts and drive solutions\n\n10+ years of experience in physical design, with a strong focus on subsystem-level closure for complex hierarchical SoCs\nStrong expertise in:Timing closure and constraint management\nCongestion analysis and resolution\nPower integrity and power-aware physical implementation\nBlock and subsystem-level physical design flows\n\nSolid understanding of SoC-level floorplanning and clocking methodologies, including:Clock domain partitioning\nClock tree architecture\nSkew management\nClock gating\n\n(Candidate is expected to collaborate effectively at the SoC level, not lead these activities.)\n\nHands-on experience with industry-standard tools such as:Synopsys ICC2, Fusion Compiler, PrimeTime\nCadence Innovus, Tempus, Certus\nSignoff and analysis platforms\n\nProficiency in scripting and automation using Tcl, Python, and/or Perl\nDeep knowledge of end-to-end SoC design flows, with strong collaboration experience across timing, power, clocking, verification, and backend teams\nStrong understanding of low-power design techniques and power-aware implementation methodologies\nEducation\nB.Tech or M.Tech in Electronics and Communication, Electrical Engineering, Computer Science, or a related field\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "SoC STA Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-09T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720745167", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nResponsibilities:\nSTA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.\n\nTiming analysis, validation and debug across multiple PVT conditions using PT/Tempus.\n\nRun Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.\n\nEvaluate multiple timing methodologies/tools on different designs and technology nodes.\n\nWork on automation scripts within STA/PD tools for methodology development.\n\nGood Technical writing and Communication skills, should be willing to work in cross-collaborative environment\n\nExperience in design automation using TCL/Perl/Python.\n\nFamiliar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus\n\nFamiliar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo.\n\nEducation : B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI.\nPreferred Qualification/Skills\n5 - 10 years of experience in STA/Timing\n\nStrong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling\n\nHands-on experience with STA tools - Prime-time, Tempus\n\nHave experience in driving timing convergence at Chip-level and Hard-Macro level\n\nIn-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,\n\nKnowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)\n\nKnowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation.\n\nProficient is scripting languages – TCL, Perl, Awk\n\nBasic knowledge of device physics\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SoC Physical Design CAD Engineer (Staff/Sr Staff)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-09T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720700007", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nJob Overview\nWe are looking for a Staff Engineer – Physical Design CAD to drive the development, deployment, and support of Physical Design methodologies, flows, and automation for complex SoC programs. The role involves enabling scalable PD infrastructure, improving design productivity, and partnering with PD, STA, DFT, and EDA teams to deliver best-in-class implementation solutions.\n\nKey Responsibilities\nDevelop and maintain Physical Design flows covering Floorplanning, PnR, CTS, Routing, IR/EM, and Signoff.\n\nBuild automation and infrastructure using Tcl, Python, Perl, and Shell scripting to improve design efficiency and turnaround time.\n\nDrive methodology improvements for timing, power, area, and design convergence across multiple SoC projects.\n\nCollaborate with PD, STA, CAD, and EDA vendors to evaluate and deploy new tools and technologies.\n\nDebug flow, tool, and methodology issues and provide scalable solutions across projects.\n\nDrive flow validation, regression automation, and deployment across advanced technology nodes.\n\nProvide technical leadership and mentor junior engineers.\n\nMinimum Qualifications\nBachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or related field.\n\n7+ years of experience in Physical Design CAD, Methodology, or Design Automation.\n\nStrong understanding of Physical Design implementation and signoff flows.\n\nExpertise in Tcl, Python, Perl, and Linux environments.\n\nExperience with industry-standard EDA tools from Cadence and/or Synopsys.\n\nPreferred Qualifications\nExperience with advanced technology nodes (7nm and below).\n\nKnowledge of STA, IR/EM, Power Integrity, and Physical Verification flows.\n\nExposure to AI/ML-driven design automation and flow optimization.\n\nStrong problem-solving, collaboration, and technical leadership skills.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Engineer - DFT", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-09T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718721216", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    8+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates complex features and functionality into hardware designs in line with proposals or roadmaps for complex products.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the novel manufacturing of solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for complex Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making is significant in nature and affects work beyond immediate work group.\n•    Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. \n•    Has a moderate amount of influence over key organizational decisions.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Physical Design Engineer - Custom Silicon Group", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-09T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720711048", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nBachelor’s or Master’s degree from a top-tier institute.\n\n8 years of experience in physical design from product-based companies.\n\nExperience:\nProven experience in managing complex subsystems and small teams.\n\nProficiency in complete Netlist2GDS: Floorplan, place and route (PnR), and sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations.\n\nHand on experience in lower technology nodes.\n\nJob Requirements:\nExpertise in meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), place and route, and IP integration.\n\nExperience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating.\n\nFamiliarity with ASIC design flows and physical design methodologies.\n\nStrong understanding of circuit design, device physics, and deep sub-micron technology.\n\nExperience working on multiple technology nodes in advanced processes.\n\nProficiency in automation to drive improvements in PPA.\n\nManaging and driving a small team for project execution and PPA targets\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Physical Design , Principal Engineer/Director, (Custom Silicon Group)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-09T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720711054", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next generation experiences and drives digital transformation to help create a smarter, connected future for all. As an ASIC Design Manager (Principal / Director-Level) in the Custom Silicon Group, you will lead the development and delivery of next-generation, high-performance SoCs from concept to tapeout. You will be responsible for driving the complete silicon development lifecycle, spanning architecture, RTL design, integration, physical design, verification, silicon bring-up, and production readiness. In addition to providing technical and organizational leadership, you will serve as a key customer-facing engineering leader, partnering with strategic customers and stakeholders to translate business requirements into successful silicon solutions.\n\nYou will lead a team of engineers and work closely with cross-functional groups across geographies -- including RTL design, verification, CAD, and integration teams. Your role will be pivotal in shaping the physical design strategy, ensuring design convergence, and maintaining signoff integrity across timing, power, and area metrics.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n\nPrincipal Duties and responsibilities:\nDemonstrate proven experience in executing responsibilities across multiple sites.\n\nLead and manage a team across multiple functions.\n\nDesign closure and tapeout expertise in advanced technology nodes.\n\nComplete ownership of PnR implementation, including Floor planning, Placement, CTS, and post-route activities on the cutting-edge nodes.\n\nPossess mandatory signoff knowledge, including STA, Power Analysis, FV, Low Power Verification and PV.\n\nCollaborate effectively to resolve issues related to constraints validation, verification, STA, Physical Design and tapeout\n\nUnderstand deep sub-micron design challenges, including leakage power, signal integrity, and DFM.\n\nSupport pre-sales and business development activities by evaluating technical feasibility and providing design expertise.\n\nProvide technical leadership during design reviews and executive-level customer engagements.\n\nDrive resolution of customer-reported issues by coordinating across design, verification, firmware, software, and validation teams.\n\nMinimum Qualifications\n• Bachelor's or Master’s degree in Electrical/Electronics Engineering and 17- 25 years of Hardware/VLSI Engineering specializing in Physical Design and timing signoff for high-speed SoCs.\n \nPreferred Qualifications:\nExcellent hands-on experience on Floor planning, PnR and STA flows\n\nGood knowledge of Placement/Clock Tree Synthesis (CTS), Low Power/High Performance optimization etc.\n\nThorough understanding of signoff domains– LEC/CLP/PDN etc.\n\n18+ years of experience with Physical Design and timing signoff expertise in latest tech nodes (e.g., 2nm/3nm/4nm/5nm)\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RISCV CPU Design Verification (Multiple Levels)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-09T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720179628", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nQualcomm is hiring strong DV engineers to verify high performance and low power RISC V based CPUs in Bangalore.\nRoles and Responsibilities\no  Develop and execute verification plans for units and features of a CPU design\no  Use simulation and formal verification methodologies to execute test plans, develop testbench components like checkers, assertions, stimulus generators.\no  Work closely with system architects, design team, software teams and Soc team to validate system use cases.\no  Work closely with emulation team to enable verification on emulators and FPGA platforms.\no  Debug and triage failures in simulation, emulation and/or Silicon.\nBE/BTech degree in CS/EE with 4+ years’ experience.\no Implementation of assembly and C language tests for verifying CPU architecture.\no  Experience in C/C++, scripting languages, HDLS like Verilog/System Verilog\no  Good Understanding of CPU architectures and CPU micro-architectures. Industry experience with CPU architecture (eg: x86, ARM, MIPS, RISCV, POWER) will be a plus\no  Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.\nPreferred Requirements:\no  Strong understanding of power management features in CPUs and CPU based Socs.\no  In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture\no  Experience with advanced verification techniques such as formal and assertions is a plus\no  Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Engineer – STA Methodology/CAD", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-09T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720923798", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nJob Overview\nWe are seeking a highly motivated Staff Engineer – STA Methodology to drive the development, deployment, and enhancement of next-generation Static Timing Analysis (STA) methodologies for complex SoCs. The ideal candidate will have strong expertise in timing signoff, constraint methodologies, automation, and timing closure flows across advanced technology nodes.\n\nKey Responsibilities:\nDefine, develop, and improve STA methodologies for block, subsystem, and full-chip designs.\n\nDrive timing signoff flows including MMMC analysis, constraint validation, ECO methodologies, and correlation strategies.\n\nDevelop automation and infrastructure using Tcl/Python/Perl to improve timing analysis efficiency and turnaround time.\n\nOwn methodology development for timing closure, reporting, constraint management, and signoff quality metrics.\n\nCollaborate closely with RTL, Synthesis, Physical Design, DFT, and CAD teams to enable robust timing convergence.\n\nDrive adoption of advanced timing techniques including SOCV/AOCV, hierarchical STA, and signoff optimization flows.\n\nDebug complex timing issues and provide scalable solutions across multiple projects.\n\nEvaluate and deploy new EDA tool capabilities and AI-driven timing closure methodologies.\n\nMentor junior engineers and provide technical leadership across STA methodology initiatives.\n\nMinimum Qualifications:\nBachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or related field.\n\n7+ years of experience in STA, Timing Signoff, Timing Methodology, or CAD/EDA methodology development.\n\nStrong understanding of:\nStatic Timing Analysis (STA)\n\nMMMC timing signoff\n\nTiming constraints (SDC)\n\nSetup/Hold closure methodologies\n\nSOCV/AOCV derates\n\nECO and timing convergence techniques\n\nExpertise with Synopsys PrimeTime or Cadence Tempus.\n\nStrong scripting skills in Tcl and Python.\n\nPreferred Qualifications:\nExperience with advanced technology nodes (7nm and below).\n\nExperience developing timing automation frameworks, dashboards, and reporting infrastructure.\n\nKnowledge of Synthesis, Physical Design, DFT, and power-aware timing analysis.\n\nExposure to AI/ML-driven timing optimization and methodology development.\n\nProven track record of driving methodology improvements adopted across multiple programs.\n\nStrong communication, collaboration, and technical leadership skills.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Physical Verification Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-09T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721015070", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nExperience with physical verification checks DRC, LVS, Antenna, ERC, PERC, ESD etc.\nExperience in PnR tools like ICC/Innovus with regards to physical convergence must.\nUnderstanding sign-off PDV tools like PDK Concepts, SVRF, Calibre and ICV.\nGood overall understanding of the Custom IC design flow.\nGood understanding of layouts and overall backend tool flow would be beneficial.\nUnderstanding sign-off PDV tools like PDK Concepts, SVRF, Calibre and ICV.\nTCL/PERL Scripting is plus.\nHands on experience :Innovus/Fusion Compiler , Tech lef is preferable.\nPeople management /Floorplanning/Power Planning/PDN  experience is BIG Plus\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU Hardware Verification (Power Management) Staff Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-09T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721010101", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nRole Overview\nWe are seeking a highly motivated and technically strong Staff Engineer to drive end-to-end verification of next-generation CPU Co-Processor (CPUCP/PDP) Power Management firmware and hardware features. This role requires deep expertise in SystemVerilog-based verification, power management validation, and cross-functional leadership across Firmware, RTL Design and Post-Silicon teams.\nThe ideal candidate will own verification strategy from architecture definition through signoff, driving quality, scalability, automation, and execution excellence across CPU programs.\n\nMinimum Qualifications:\n• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\nOR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\nOR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nKey Responsibilities\nLead the end-to-end verification of CPUCP/PDP firmware-driven hardware features, with a focus on Power Management, Reliability, and System Readiness.\n\nArchitect and develop robust SystemVerilog/UVM testbenches, transactors, checkers, and verification infrastructure for complex SoC subsystems.\n\nDrive verification of AMBA-based system IPs including timers, mailbox, interrupts, and interconnect fabrics (NoC).\n\nOwn verification planning, test strategy, coverage modeling, coverage closure, and functional signoff.\n\nDefine and implement comprehensive validation for power-management features such as DVFS, Low Power Modes (LPM), clock/power transitions, and firmware-controlled sequences.\n\nLead complex debug and root-cause analysis across Firmware, RTL, Design, Emulation, and Post-Silicon teams.\n\nDevelop reusable stimulus frameworks, automation solutions, debug utilities, dashboards, and productivity tools to improve execution efficiency and scalability.\n\nSupport platform bring-up, SoD readiness, feature qualification, HW/FW release validation, and silicon readiness activities.\n\nInfluence architecture reviews and verification methodologies, ensuring best practices are consistently applied across programs.\n\nMentor junior engineers and foster a culture of technical excellence, ownership, and innovation.\n\nDrive cross-functional initiatives spanning Firmware, Hardware Design, Emulation, and Post-Silicon Verification teams.\n\nRequired Qualifications\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field .\n\nExtensive experience in SoC, CPU or Power-Management verification environments.\n\nStrong expertise in SystemVerilog/UVM, verification methodologies, and testbench architecture.\n\nProven experience developing NoC transactors, protocol checkers, and verification infrastructure.\n\nDeep understanding of AMBA protocols and system-level IPs such as timers, mailboxes, interrupts, and memory-mapped peripherals.\n\nStrong background in RTL simulation, emulation, waveform analysis, debug methodologies, and coverage closure.\n\nExperience validating power-management technologies including DVFS, LPM, idle states, power sequencing, and reset flows.\n\nProficiency in C/C++, SystemVerilog, Python, scripting, automation, and data-driven verification workflows.\n\nStrong analytical and debugging skills with the ability to diagnose issues across HW, FW, and system domains.\n\nDemonstrated ability to lead technical discussions, influence verification strategy, and drive execution across geographically distributed teams.\n\nAdded Advantage: Power Aware verification and Gate level simulation Hands – On experience\n\nPreferred Qualifications\n10–12+ years of industry experience in CPU, GPU, SoC, or complex subsystem verification.\n\nProven expertise in pre-silicon verification methodologies, testbench architecture, and verification infrastructure development.\n\nStrong track record of delivering verification signoff for complex SoC features from architecture definition through silicon bring-up.\n\nHands-on experience with automation frameworks,, regression infrastructure, and CI/CD verification workflows.\n\nKnowledge of system level Power management scenarios.\n\nPrevious experience mentoring engineers and leading cross team technical initiatives across organizations.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Sr Staff DFT Engineer - NPU/AI Processor", "company": "Qualcomm", "location": "Bangalore - Remote, India", "date_posted": "2026-09-09T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718721215", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nMinimum of 11+ years experience in the area of ASIC/DFT\n\n-In depth knowledge of DFT concepts\n-In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis\n-Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations\n-Expertise in scripting languages such as perl, shell, etc.\n-Experience in simulating test vectors\n-Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (Tessent, TK, TetraMax)\n-Working experience in Genus, Synopsys TetraMax/DFTMax and Cadence Encounter Test is a plus\n-Ability to work in an international team, dynamic environment\n-Ability to learn and adapt to new tools and methodologies.\n-Ability to do multi-tasking & work on several high priority designs in parallel.\n-Excellent problem solving skills\n-Excellent communication and team work skills and good English is required\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Camera IP Verification - Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-09T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720636831", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nCandidate will be responsible for IP Level Verification of Qualcomm Spectra Camera Sub Systems Modules for next gen Qualcomm product portfolio. This role will require the candidate to understand details of the camera signal processing modules, verify them at module & subsystem level for enhanced features. Engineer should independently be able to own the verification of IP level modules end to end with continuous enhancements and collaborate with IP Verification, Design and System leads.\nNecessary skills/experience:\n• 1+ years of experience in RTL design verification using SystemVerilog/UVM and industry-standard simulation tools (Mandatory)\n• Experience in power aware simulation is a big plus\n• Experience on camera verification is a big plus\n• Expertise in Coverage closure , RTL debug skills\n• Expertize in SV – UVM, Assertions based verification, DPI\n• Familiarity in Firmware/emulation (ex: Veloce) based verification , GLS\n• Familiarity with bus protocols like AHB, AXI, ARM based system architecture\n• Experience with Perl, Python, or similar scripting language\n• Excellent problem solving skills & Verification aptitude\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Engineer II - Physical Design", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-09-09", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Senior-Engineer-II---Physical-Design_R3784-26-9", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nCompany Description\nMicrochip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products.\nJob Description\nMicrochip AES Design team looking for an experienced and motivated Physical Design Engineer to implement RTL2GDSII for larger SOCs. As a member of Physical Design team, you will be responsible for place and route, timing closure and physical verification checks for multiple blocks and top level. The candidate should have experience with Physical Design tools. The candidate should have in depth knowledge of Innovus/ICC2 tool execution.\n\nLocation: Bangalore, India\n\nRequirements/Qualifications:\n\nJob Responsibilities:\nThe employee is responsible for complete physical design of multiple large & complex blocks & sub-system implementation from 40nm to 3nm and below technology nodes. The employee is expected to take ownership of Full Chip/Subsystem complex design & flow challenges, which would include:\nFloor-planning, Place & Route and CTS using physical design tools like Innovus and ICC2.\nPhysical verification and IP Integration\nPhysical Design Flow and Methodology.\nIR and EM checks.\nAbility to lead Junior team members along with the project execution.\nUse metric-driven techniques to help ensure first-pass working silicon.\nCommunicate regularly with the implementation and project team to resolve issues, and communicate status to leads\nOccasional travel needed.\n\nJob Qualifications:\n\nThis position requires at least B.E/B.Tech/M.Tech in Electronics with 7+ years of Physical Design experience in a fast-paced environment with following experience.\n\nExpertise in Physical Design activities: Floor-planning, CTS, P&R, Extraction, Power IR/EM, Physical Verification (DRC/LVS) and Signal Integrity\nAdvanced knowledge of place and route methodologies and low power methodologies.\nStatic Timing/Crosstalk Analysis and timing closure\nMust have an understanding of Synthesis/DFT concepts and flow\nExperience in working with analog IP, hard and soft macros and delivering hierarchical design projects\nExpertise with Backend Tools (Innovus or ICC2, Calibre or PVS, PrimeTime or Tempus, Redhawk or Voltus, Starrcxt or QRC)\nStrong programming knowledge in Perl, TCL, and/or Shell and Python Scripting\nExcellent oral and written communications skills in order to work with teams across the globe\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "IP Product Mktg Mgr", "company": "Lattice", "location": "Penang, Malaysia", "date_posted": "2026-09-09", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Penang-Malaysia/IP-Product-Mktg-Mgr_R-102713", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\n\nLattice Semiconductor is seeking a Technical Product Marketing Manager to drive the strategy, planning, and go-to-market execution for our industry-leading FPGA IP solutions. This is a high-impact role that sits at the intersection of technology, product management, engineering, and customer engagement, offering the opportunity to influence product direction, drive business growth, and shape the future of FPGA-based solutions.\n\nThe ideal candidate combines strong technical expertise with business acumen and a passion for delivering customer-centric products that enable success across a broad range of applications.\n\nResponsibilities\nDefine product and IP feature requirements that align with customer needs, market opportunities, and business objectives.\n\nDevelop and maintain product roadmaps, prioritizing investments and feature development based on customer feedback, market trends, and strategic goals.\n\nPartner with engineering, applications, marketing, and sales teams to drive execution of new IP capabilities, including requirements definition, MRD/PRD development, and product reviews.\n\nGather, analyze, and translate customer and ecosystem feedback into actionable product planning recommendations.\n\nDrive go-to-market activities for new products and IP releases, including positioning, messaging, competitive analysis, launch planning, and sales enablement.\n\nCollaborate with field sales, FAE, and business development teams to support customer engagements, design wins, and revenue growth.\n\nTrack market opportunities, pipeline progression, and business performance against key objectives.\n\nServe as a subject matter expert for FPGA IP technologies, competitive offerings, and industry trends.\n\nRequired Qualifications\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.\n\n3+ years of experience in product marketing, product management, applications engineering, design engineering, or a related technical role.\n\nTechnical knowledge of one or more of the following areas: High-speed serial interfaces and protocols Video and display connectivity Embedded processing systems Image processing and computer vision.\n\nExperience defining product requirements, developing PRDs/MRDs, or influencing product roadmaps.\n\nStrong analytical and problem-solving skills with the ability to balance technical, customer, and business considerations.\n\nExcellent written, verbal, and presentation skills with the ability to communicate effectively across technical and executive audiences.\n\nCustomer-focused mindset and ability to work effectively across global, cross-functional teams and drive results in a fast-paced environment.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nMalaysiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "HW I/P Lab Lead", "company": "Samsung", "location": "Phoenix Building, Bangalore, India", "date_posted": "2026-09-09", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/Phoenix-Building-Bangalore-India/HW-I-P-Lab-Lead_R119924", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nGroup Leader for HW IP Group\nRole and Responsibilities\n\nAs the leader of Hardware IP Design, development and validation, you will head engineering team responsible for the architecture, design and verification of our next generation purpose specific custom HW IP. This critical leadership role spans both in-house IP development as well as strategic evaluation, integration and validation of various other IP blocks. You will bridge the gap between technical execution and people leadership, ensuring delivery, high quality, high performance and power – efficient hardware Ips that drive and differentiate our product line over competitors\n\nSkills and Qualifications\n\nLEADERSHIP AND PEOPLE MANAGEMENT:\nManage and Mentor a multi-disciplinary team of RTL Design and Design Verification Engineers\nFoster a culture of technical excellence, continuous learning and meaningful collaboration\nDrive Skill up, career development and performance enhancement of the team, in a continuous fashion\nTECHNICAL EXECUTION AND DELIVERY:\nOversee the end-to-end IP lifecycle. Including micro architecture definition, RTL Coding and Advanced verification\nEnsure robust validation methods utilised to ensure zero-bug silicon\nDefine and Implement best-in-class engineering practices, checklists and design flows to maximise efficiency\nTECHNICAL COMPETENCIES:\nRTL Design / Verification / Emulation\nUnderstanding of digital design principles, algorithm, design and Architecture specifications\nUnderstanding of SystemC , C and Python Programming\nDesign direction in terms of performance, gate count and power for various digital designs\nProficient in System Verilog/UVM/OVM\nFPGA IP/Custom ASIC Prototyping and Validation\nDeveloping scalable Test benches in System Verilog and UVM\nUnderstanding of cameras / multimedia / display /NPU subsystems in detail\nProven track record of integrating complex sub-systems (PCIe, USB, DDR, ARM/RISC-V Cores, MIPI etc)\nDesign - knowledge in Verilog, Linting, (CDC) clock domain crossing, synthesis, Timing Analysis, Low Power Implementation (UPF/CPF, Clock Gating, Power Domain)\nUsage for AI Tool e.g., Claude for IP development enhancement, KPI exploration.\nKEY LEADERSHIP TRAIT:\nPeople Developer\nCross Functional Bridge\nResource Optimiser\nDecisive Problem Solver\nInfluencer and Navigator\nDESIRED QUALIFICATION\nGraduate / Postgraduate in Electrical / Electronic Engineering / VLSI Design / Microelectronics\n\n** Samsung/SRI-B has a strict policy on trade secrets. In applying to Samsung/SRI-B and progressing through the recruitment process, you must not/ you are not required to disclose any trade secrets of your current or previous employer.\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "Formal Verification Engineer", "company": "NVIDIA", "location": "India, Gurugram", "date_posted": "2026-09-09", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Gurugram/Formal-Verification-Engineer_JR2025192", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.\n\nNVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nWe need passionate, hard-working, and creative people to help us take on some of these once-in-a-lifetime opportunities. This position offers the opportunity to have real impact in a progressive, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. NVIDIA is seeking Formal Verification Engineers for our Hardware Engineering team.\n\nWhat you’ll be doing:\nProve correctness of design blocks, IPs and SoC components using Formal Verification methods\n\nPrepare testplans and implement them using Formal verification techniques\n\nExperiment with Formal tools and flows to drive performance and quality of results\n\nCollaborate with other members of the design and verification teams to successfully meet verification goals\n\nWhat we need to see:\nB.Tech. / M.Tech. in Electrical Engineering, Computer Science or related fields with 2+ years of relevant experience\n\nStrong analytical skills to tackle complex problems\n\nStrong coding skills in industry-standard scripting or programming languages such as C, Python, Perl or Tcl\n\nAbility to communicate effectively and collaborate in a globally distributed team\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "ASIC CAD Engineer, Clocks Methodology", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-09-09", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/ASIC-CAD-Engineer--Clocks-Methodology_JR2025033", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation fueled by groundbreaking technology and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPUs power computers, robots, and autonomous vehicles that can understand and interact with the world. Achieving what has never been done before requires vision, innovation, and exceptional talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Join us and help make a lasting impact on the world.\n\nThe Clocks Design Methodology Team develops advanced clocking methodologies and custom CAD solutions to address the increasing complexity and scale of next-generation chips. As part of the NVQuartz Team, we build scalable tools and methodologies that enable heterogeneous hardware designs across NVIDIA's product portfolio, including SoCs, CPUs, GPUs, and Networking products. Our mission is to improve engineering productivity, design quality, and scalability by developing innovative automation, validation frameworks, and methodologies used across the company.\n\nWhat You'll Be Doing:\nOwn the validation of clocking methodology solutions for hardware clocking designs across multiple product lines.\n\nUnderstand design requirements and develop robust validation strategies, automation, quality checks, debug infrastructure, bug fixes, and productization workflows.\n\nSolve complex engineering problems by developing scalable methodology and automation solutions that work across multiple chip architectures.\n\nDevelop and maintain tools using C++, Python, Perl, Tcl, and NVIDIA's internal compilers, frameworks, and CAD infrastructure.\n\nPartner closely with design, verification, architecture, and methodology teams to understand requirements and deliver high-quality tool capabilities.\n\nCollaborate with Quality Assurance engineers to ensure robust, production-ready methodology releases.\n\nWork effectively with engineering teams across multiple geographies and time zones.\n\nWhat We Need to See:\nBS or MS in Computer Science, Electrical Engineering, or a related field (or equivalent industry experience).\n\n1+ years of experience and strong understanding of digital logic design and computer architecture.\n\nSolid software engineering skills with expertise in C/C++ and scripting languages such as Python, Perl, and Tcl.\n\nExperience developing CAD tools, engineering automation, or software infrastructure.\n\nUnderstanding of algorithms, data structures, and software design principles.\n\nAbility to work collaboratively across multiple engineering disciplines.\n\nStrong problem-solving skills and the ability to independently drive technical solutions.\n\nExperience building tools for hardware engineering teams is highly desirable.\n\nExposure to VLSI design flows, clocking methodologies, or physical design is a plus.\n\nWe have some of the most forward-thinking and hardworking engineers in the world, and our world-class engineering teams continue to grow rapidly. If you're creative, curious, passionate about technology, and excited to solve challenging problems at scale, we'd love to hear from you.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Staff Analog Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-09-09", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506589", "is_hardware": true, "platform": "oracle", "jd_text": "Responsibilities:\n\nDrive development of state-of-the-art analog blocks and mixed signal CMOS designs which can be reused across different market segments.\n\nAnalytical approach to problem solving is required. CMOS designs provide challenging learning opportunities where performance, power and reliability are all pushed to the limit while maintaining product execution schedule.\n\nDrive analog circuit requirements discussions, technical issues and other design aspects with internal teams and marketing to arrive at agreed upon product specifications.  \n\nBuild/develop circuits based on an IP specification, drive the layout design and final IP characterization. \n\nExecute state-of-the-art analog designs while following the best design practices with on time quality design releases. \n\nPropose innovative and creative solutions where necessary to meet customer & product needs. \n\nWork diligently with the analog team members and others to accomplish project goals and meet schedule requirements. \n\nDebug of complex integrated circuit problems in the laboratory. Support team debug efforts as needed. \n\nPerform bench characterization and support application engineering bench evaluation efforts. \n\nAnalyze design aspects related to DFT and collaborate with other teams to develop DFT strategy for block designs. \n\nDocument designs including architecture and circuit descriptions, testing procedures, and safety mechanisms. \n\nInterface with test, product, and applications engineering to drive the design to a successful production release. \n\nProvide technical leadership including IC specification, project planning, design team management, and layout supervision. \n\nClose collaboration with system architects and product definers\n\n#LI-RG1\n\nQualifications\nAnalog design experience and proficiency in verification, documentation, and post-silicon validation. Includes broad understanding of integrated circuit design such as amplifiers, LDO, BGAP circuits, charge pump etc.\n\nIn-depth knowledge of semiconductor devices like MOS transistors, BJTs etc.\n\nKnowledge with behavioral top-level modeling and mixed signal verification methodology.\n\nKnowledge of UNIX/Linux working environment \n\nKnowledge of multiple semiconductor design tools like Spectre, Spice, Cadence design environment, Matlab, python. AMS simulation experience is a plus.\n\nExcellent written and oral communication.\n\nProven ability to work independently and in teams.\n\nHands-on experience in a lab environment working with sensitive measurement equipment and data acquisition.\n\nVery good debugging ability in circuit operation, and device function\n\n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "STAFF, DESIGN LAYOUT; DSGN", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-09-09", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506478", "is_hardware": true, "platform": "oracle", "jd_text": "We are looking for Principal Analog Layout Engineers to join our Image Sensor team. \n\n The ideal candidate will have strong expertise in analog and mixed-signal layout design, with the ability to independently drive complex layout blocks, mentor junior engineers, and contribute to layout methodologies and quality improvements.\n\nResponsibilities\nLead physical layout implementation of complex analog and mixed-signal blocks such as ADCs, PLLs, Bandgaps, References, LDOs, Bias circuits, and image sensor-related analog IPs.\n\nIndependently own block-level layout activities from floorplanning through verification and final signoff.\n\nDrive layout architecture discussions, floorplanning strategies, matching requirements, power planning, shielding, and area optimization.\n\nEnsure high-quality execution through DRC, LVS, ERC, EM/IR, density, reliability, and other tapeout quality checks.\n\nCollaborate closely with circuit designers to optimize performance, area, and schedule.\n\nIdentify layout-related risks early and propose mitigation plans.\n\nMentor junior layout engineers and provide technical guidance on best practices and layout methodologies.\n\nContribute to layout automation, productivity improvements, and development of reusable methodologies.\n\nParticipate in design reviews and support project execution across multiple product generations.\n\nQualifications\n12-15 years experience in analog layout design\n\nStrong hands-on experience with Cadence Virtuoso.\n\nExpertise in physical verification flows.\n\nSolid understanding of:\n\nDevice matching and common-centroid techniques\n\nSymmetry and critical analog routing\n\nShielding and noise isolation\n\nPower planning and substrate management\n\nESD and reliability considerations\n\nProven ability to independently handle complex analog layout blocks and drive closure.\n\nStrong debugging and problem-solving skills.\n\nEffective communication skills.\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Memory Layout Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-09-09", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Memory-Layout-Design-Engineer_R027047", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nJob Requirements:\n- Minimum 3 years of experience with strong layout knowledge\n- Bachelor's degree required.\n- Proficiency in using Cadence tools (virtuotso layout, layotu XL, Cadence schematic capture, and verification tools - CALIBRE & Hercules).\n- Strong layout knowledge in submicron processes (e.g. 7nm, 5nm, 3nm, 2nm).\n- Experience in digital layout (Standard cell, Memory, I/O); analog layout experience is a plus.\n\nJob Description:\n- Understand and apply layout guidelines, new process rules, and technical requirements for good quality layout.\n- Manage scheduling, timelines, and layout floor-planning.\n- Responsible for start to end deliverables with quality within the planned schedule.\n- Adapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the SOC/library team.\n\nSkill Set (Memory):\n- Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes.\n- Experience with Cadence Layout tools (VIRTUOSO XL, VXL, or EXL) and CALIBRE verification tools.\n- Proficiency in floor-planning, hierarchy layout, and chip integration.\n- Understanding of memory architecture, RC requirement, ability to plan signal and power, based on the layout guidelines\n- Knowledge of AI, automation in layout, Script Programming and SKILL Programming is a plus.\n- Ability to lead, train junior engineers, and manage projects effectively.\n- Good knowledge of memory layout topology; experience with memory compilers is a plus.\n- Ability to lead new technology reviews to document layout methodologies, flows, and guidelines.\n- Self-reliant with the ability to work both independently and collaboratively.\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "IO and Mixed Signal Layout Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-09-09", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/IO-and-Mixed-Signal-Layout-Design-Engineer_R027038", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nDesign full custom layouts of I/O libraries and Analog Mixed Signal IP's in planar and FinFET technologies.\n\nDrive critical floor-planning decisions to ensure optimal placement and routing that meets design requirements and performance metric.\n\nPerform comprehensive layout verification to ensure high quality and compliance\n\nComplete ownership from end to end deliverables with quality within the schedule.\n\nAdapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the teams across all sites.\n\nSkills and Qualifications Required:\nB.Tech/M.Tech in Electronics/Electrical engineering with 8-12 years of experience\n\nHands-on experience in I/O Library and Analog Mixed-signal IP development and verification \n\nSolid understanding of Planar and FinFET layouts and process technology\n\nGood understanding of Full-chip concepts, IO frame and pitch requirements, power planning, IO segment rules and requirements\n\nIn-Depth knowledge of ESD and Latch-up principles for I/O and Analog layouts\n\nProficiency in using Cadence Virtuoso Layout suite and Siemens CALIBRE verification tools.\n\nExpertise in Layout verifications and debugging: DRC/LVS/ANT/ERC/DFM, LPE, PERC, EM and IR etc\n\nFamiliar with the Physical Design flow: LEF generation and PnR\n\nKnowledge of AI, automation in layout, Script Programming and SKILL Programming is a plus.\n\nExcellent written and verbal communication skills to collaborate with circuit designers and teams across all sites\n\nAble to lead, train junior engineers, and manage projects effectively.\n\nSelf-motivated, capable of working independently, and a strong collaborative team player.\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "IP RTL Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-09", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/IP-RTL-Design-Engineer_JR0284060", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nRole and Impact:\n\nAs a Component IP RTL Design Engineer for Intel Unified Chassis, you will be responsible for developing, implementing, and supporting a variety of IP components, with a major focus on protocol bridges. In this role, you will collaborate with architects and senior engineers to define, design, and validate protocol bridge solutions, as well as other IP blocks as required for Unified Intel Chassis designs. Your primary work will involve protocol conversion, access control, and error handling across interfaces such as AXI, AXI-Lite, APB, IOSF-SB, HBW, and LBW, but you may also contribute to other IP development, integration, and debug activities to meet system-level requirements and quality standards.\n\nKey Responsibilities:\nDesign, implement, and verify protocol bridges between different bus and interconnect standards (e.g., AXI, AXI-Lite, APB, IOSF-SB, HBW, LBW).\nContribute to the development and support of other IP components as needed for Intel Chassis projects.\nCollaborate with architects and senior engineers to define microarchitecture and interface requirements for protocol bridges and other IP blocks.\nDevelop RTL code and simulations for protocol bridge logic and other IP, ensuring functional correctness and performance targets.\nImplement access control, privilege qualification, and policy propagation for secure data paths.\nSupport error detection, parity/ECC generation and checking, and transaction error handling in protocol bridges and other IP.\nAssist in integration, verification, and debug of protocol bridges and other IP within larger IP or SoC environments.\nDocument design features, test plans, and results for protocol bridge and other IP deliverables.\nWork with validation, firmware, and post-silicon teams to ensure IP functionality and diagnosability.\nContribute to compliance with quality assurance standards and smooth handoff of IP deliverables.\n\nQualifications:\nMinimum Qualifications:\nBachelor's degree in electrical engineering, Computer Engineering, or related field.\nMinimum 6-15 years of experience in RTL coding, logic design, and simulation.\nProficiency in hardware description languages such as Verilog or VHDL.\nStrong knowledge of digital design principles, including power, performance, and area optimization.\nFamiliarity with tools for synthesis, timing analysis, and formal verification.\nExperience with debugging RTL and resolving failing tests.\n.Expertise in RAS/debug/security/telemetry\n\nPreferred Qualifications:\nMaster's or PhD in Electrical Engineering, Computer Engineering, or related field.\nStrong communication and collaboration skills to work effectively in a cross-functional team environment.\nExperience in supporting SoC customers with IP integration and verification.\nKnowledge of industry trends and emerging technologies in logic design and chip development.\nProven ability to lead projects and provide innovative solutions to complex technical challenges.\nNOC in IP Design, Credit-Based Fabric & Bridge Architectures, High-Throughput SoC Interconnect Design, Fabric / Protocol IP, Scalable Interconnect .\n\nJoin us at Intel and become part of a team where your engineering expertise will shape the future of cutting-edge technologies. Apply today to drive innovation and make an impact.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "High Speed Analog Design Lead", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-08T12:20:00+00:00", "url": "https://canadacareers-amd.icims.com/jobs/88968/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. SMTS SILICON DESIGN ENGINEER THE ROLE: This job opening is for a circuit designer in a team responsible for high-precision custom circuit blocks in AMD’s microprocessor designs. This team owns a wide variety of key IP in Digital and Analog/Mixed-Signal domains catering to products across multiple business units. With a good mix of experienced designers and recent college graduates from top Engineering institutions across the country, this team offers a very competitive atmosphere with excellent scope to learn and improve. Meticulous execution routine resulting in a solid track record, a strong focus on innovation and a balanced work-life distribution makes this one of the top-class teams in this space across the industry. THE PERSON: Ideal candidate would be the one with not only strong circuit design knowledge, but also clear communication and presentation skills along with diligent documentation of work. Passion to go beyond the call of duty and innovate for higher efficiency would be a key differentiator. KEY RESPONSIBILITIES: Complete ownership of individual circuit blocks in a DDR PHY design in cutting edge process technology nodes Responsible for circuit design, layout quality, electrical and timing analysis, and reliability checks Interface with cross-functional teams like RTL, Verification and Physical Design PREFERRED EXPERIENCE: Strong hands-on experience in DDR circuit designs in latest process technology nodes. Good technical knowledge of power-performance trade-offs in high-speed DDR and/or SerDes architectures Direct experience in all phases of design analysis including functional, static timing and electrical sign-off Strong understanding of the impact of variation on design performance ACADEMIC CREDENTIALS: Desired: Masters in Electrical/Electronics Engineering, with specialization in microelectronics or something similar #LI-PM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "CPU Core Design Verification Manager", "company": "Tenstorrent", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-08T12:11:08-04:00", "url": "https://job-boards.greenhouse.io/tenstorrent/jobs/5231981007", "is_hardware": true, "platform": "greenhouse", "jd_text": "Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.\n\nAt Tenstorrent, we build open, state of the art compute for real workloads and real developers.\n\nYou will lead our Bangalore-based CPU Core Design Verification team, driving both the technical strategy and the people leadership behind verification of our high-performance, out-of-order RISC-V CPUs. You will manage a team of core-level verification engineers, partner closely with our Santa Clara and Austin sites, and own delivery of core verification from architecture definition through tapeout readiness.\n\nThis role is hybrid based out of Bangalore, India, with regular collaboration across our globally distributed CPU organization.\n\nWe welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.\n\n \n\nWho You Are\n\n15+ years of CPU/DV experience, including 7+ years leading verification teams, with strong hands-on expertise in high-performance, out-of-order CPU verification.\n\nDeep microarchitecture & verification expertise, including ISA, RTL, UVM/CVM, testbench development, regressions, coverage, and complex debug.\n\nStrong people and technical leadership, with experience hiring, mentoring, developing engineers, and setting verification strategy and methodology across teams.\n\nHighly collaborative and execution-focused, comfortable working across time zones and driving cross-functional debug with Design, DV, Emulation, and Post-Silicon teams, including P0 issues and AI-assisted verification workflows.\n\nWhat We Need\n\nBuild and lead the Bangalore CPU Core DV team, owning hiring, mentoring, performance management, and team growth.\n\nOwn verification strategy and execution for high-performance, out-of-order RISC-V CPU cores, covering ISA, microarchitecture, UVM/CVM methodology, infrastructure, and coverage.\n\nDrive cross-site execution with DV and design leads in Santa Clara and Austin, aligning coverage, schedules, tapeout readiness, and closure of critical bugs and coverage gaps.\n\nStay technically engaged while leading the team, contributing to debug, code/testplan and architecture reviews, and championing AI-assisted tools for triage, stimulus generation, and coverage analysis.\n\nWhat You Will Learn\n\nHow Tenstorrent designs and verifies high-performance RISC-V CPU cores and clusters across a globally distributed organization.\n\nHow to scale a verification team and its infrastructure across core, cluster, and chip-level environments spanning multiple sites.\n\nTechniques for spanning pre-silicon, emulation, and post-silicon verification with shared stimulus and methodology.\n\nHow Tenstorrent applies AI across the DV lifecycle — from test planning and stimulus through regression debug, triage, and coverage analysis — using workflows designed to keep context tight and outputs auditable.\n\nHow to build and run a high-performing verification organization inside a fast-growing, technically ambitious silicon company.\n\n \n\nTenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.\nThis offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.  Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).   These requirements apply to persons located in the U.S. and all countries outside the U.S.  As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.  If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.", "jd_status": "stored"}, {"title": "GFX- IP Verification Lead", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-08T07:19:00+00:00", "url": "https://global-external-amd.icims.com/jobs/88001/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. MTS SILICON DESIGN ENGINEER    THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.     THE PERSON:  You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.   KEY RESPONSIBILITIES:  Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues  Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements   PREFERRED EXPERIENCE:  Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools  Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++   Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment.   Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience.   Scripting language experience: Perl, Ruby, Makefile, shell preferred.   Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions.     ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-NS1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Director Engineering, Analog Design (Power ICs) - Chip Lead", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-08T06:54:47.496000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000148147539-director-engineering-analog-design-power-ics-chip-lead", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking a Director, Engineering with deep expertise in mixed-signal IC development to support Renesas' India-focused growth initiatives. This role is technical, cross-functional, and product-defining. \nThe successful candidate will define optimum system architecture for application-specific ICs, spanning analog signal-chain products, high-power delivery, mixed-signal integration, and digital-controller-based architectures. The role will map product needs to existing Renesas IP across business units and identify where new development is required. \nYou will be expected to collaborate across business units, system engineering, analog packaging, back-end, design, test, and operations teams to execute IC development with an efficient cost structure. You will also identify critical skill-set requirements and build the right technical team from scratch. \n \nProduct & Architecture Leadership \nWork with product definition / IC architect team to optimize system architecture for application-specific ICs serving India market requirements across automotive, industrial, power, and mixed-signal applications. \n\nUnderstand customer use cases, system requirements, cost targets, and application constraints to optimize architecture \n\nCover a broad technical span, ranging from analog signal-chain products to high-power delivery with digital controllers. \n\nDrive architecture trade-offs across performance, integration level, BOM cost, manufacturability, qualification effort, and reuse of existing Renesas technology. \n\nCross-Business Unit IP Reuse & Collaboration \nMap target architectures to available IP across different business units within Renesas and identify gaps requiring new development. \n\nCollaborate with multiple business units, system engineering, analog packaging, back-end, design, test, and operations teams to execute the development plan. \n\nRepurpose existing resources and IP wherever practical, while being clear where reuse creates unacceptable product, schedule, or execution risk. \n\nCreate structured technical alignment across stakeholders who may have different priorities, schedules, and ownership models. \n\nDevelopment Execution \nLead development programs through concept definition, architecture, specification, planning, execution, verification, validation, qualification, and production handoff. \n\nBuild execution plans that include ownership, milestones, technical risks, resource needs, cost assumptions, and decision gates. \n\nEnsure development choices are grounded in realistic foundry, packaging, test, DFT, qualification, and manufacturing constraints. \n\nCollaborate with system engineering teams to define IC requirements and ensure the product solves real application-level problems. \n\nAutomotive Quality, DFT & Reliability Planning \nUnderstand automotive qualification requirements for integrated circuits during design planning and translate them into execution needs. \n\nPlan required DFT structures, test coverage, reliability flows, and production test implications early in the design phase. \n\nUnderstand system-level fault behavior, protection needs, and safety-related requirements where relevant to automotive and industrial applications. \n\nCreate a practical bridge between product ambition and qualification realities, including schedule, cost, and silicon iteration risk. \n\nTeam Building & Technical Leadership \nIdentify critical skill-set requirements and hire the right people for the development team. \n\nBuild and mentor a high-quality technical team, including architecture, design, verification, validation, and execution contributors. \n\nAssess technical depth during hiring and avoid over-reliance on surface-level experience claims. \n\nRepresent the program in senior leadership reviews with clear choices, trade-offs, risks, and asks. \n\n15+ years of experience in mixed-signal IC, analog IC, power IC, or related semiconductor product development. \n\nBachelor or Masters of Electronics Engineering related discipline from a reputed institution. \n\nExperience in leading IC development with multiple functional teams is a must for this role. \n\nGood understanding of history and future trends in semiconductor industry. \n\nAwareness of foundry capabilities for different CMOS, BCD and FET technologies will be an added advantage. \n\nUnderstanding of automotive qualification requirements for integrated circuits in the design phase and ability to plan execution with required DFT circuits. \n\nGood understanding of advanced semiconductor packaging technologies and their impact on cost, thermal performance, integration, and manufacturability. \n\nPrevious experience in building a team from scratch. \n\nComfort and ability to collaborate and be effective in an entrepreneurial (fast-paced and ambiguous) environment. \n\nExcellent interpersonal, communication and presentation skills and comfort in presenting to a wide range of audiences. Capable to communicate issues in a concise and effective way. \n\nDesire and drive to interact with, as well as ability to build and maintain excellent relationships with internal and external stakeholders. \n\nProduct ownership mentality with strong affinity to technical depth.\n\nSelf-driven, strongly motivated individual capable to take full ownership of their activities, and to involve other functions in the company or management when needed to bring them to a successful outcome. \n\nShould be motivated to handle unknowns of a beginner.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Engineer-Low power verification", "company": "Ericsson", "location": "Bangalore,Karnataka,India", "date_posted": "2026-09-08T04:57:38+00:00", "url": "https://jobs.ericsson.com/careers/job/563121775484435", "is_hardware": true, "platform": "eightfold", "jd_text": "About this opportunity\n\nJoin our new ASIC top level verification team.\nWe specialize in the top-level verification of cutting-edge ASICs that power complex high-performance systems. Our designs are either monolithic ASICs or integrated multi-chip-modules holding several hundreds of processor cores, DSPs as well as ARM cores, tailored hardware accelerator IPs and many high-speed interfaces, including Ethernet, CPRI, and PCIe.\nAs an ASIC Top-Level Verification Engineer, you'll be part of a team tackling some of the most challenging verification tasks in the industry, ensuring that our ASICs meet our high standards for performance, functionality, and security.\nYou will play an important role in the team developing environments and/or tests run in SystemC/TLM simulation, RTL environments, hardware emulation, and eventually on Silicon.\n\nWhat you will do\n\nLow power verification is a focus area, but as a senior verifier the person is expected to support in various types of verification.\n\nCreate power verification planning and strategy\nPrepare power aware simulation environments\nSimulate and debug power aware simulations\n \n\nYou will bring\n\nUnderstanding of power techniques - e.g. CG, PG, MV, DVFS, MEM modes\nUnderstanding of power intent format - e.g. UPF or CPF\nExperience in power aware GLS\nExperience using formal for power verification\nRTL debugging with experience using Waveform debugging tools from one of the three largest EDA vendors\nDevelopment of C SW targeting embedded system, using SW debuggers for debugging.\nUpdating testbenches, like adding VIPs.\n\n.\n\n“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”\n\nWhy join Ericsson?At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.\n \nWhat happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.\n \nPrimary country and city: India (IN) || Bangalore\nReq ID: 783398", "jd_status": "stored"}, {"title": "Peripheral Validation Engineer (Lead/Staff)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-08T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719852485", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nJob Description :\nKnowing Low speed protocols such as I3C, QSPI etc.\n\nBare metal/Linux driver development experience and excellent C/C++ programming skills\n\nExperience on working complex SoC software development & HW validation testing aspects functional/performance/compliance/power\n\nDebug & Lab tools experience: Lauterbach, Oscilloscope, Low Speed protocol analyzers, Logic Analyser, Saleae Logic Analyzers\n\n5+ years Hardware Engineering experience or related work experience\n\nPre/post-silicon validation experience\n\n \n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SoC Physical Design Engineer, Senior Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-08T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720713298", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nBachelor’s or Master’s degree from a top-tier institute.\n\n12 years of experience in physical design from product-based companies.\n\nExperience:\nProven experience in managing complex subsystems and small teams.\n\nProficiency in complete Netlist2GDS: Floorplan, place and route (PnR), and sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations.\n\nHand on experience in lower technology nodes.\n\nJob Requirements:\nExpertise in meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), place and route, and IP integration.\n\nExperience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating.\n\nFamiliarity with ASIC design flows and physical design methodologies.\n\nStrong understanding of circuit design, device physics, and deep sub-micron technology.\n\nExperience working on multiple technology nodes in advanced processes.\n\nProficiency in automation to drive improvements in PPA.\n\nManaging and driving a small team for project execution and PPA targets\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Systems Engineer, Staff - SoC Interconnect / NoC Systems Architecture", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-08T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721008916", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Systems Engineering\nGeneral Summary:\nWe are seeking a highly motivated Systems Engineer to drive the architecture and development of next generation System-on-Chip (SoC) interconnect solutions powering data center, automotive, smartphone, notebook, tablet, XR, smart glasses, and emerging compute platforms.\nThe candidate will be a key member of the NoC Systems Architecture Team, responsible for defining system requirements, developing Network-on-Chip (NoC) architecture specifications, and collaborating across multiple engineering disciplines to deliver scalable, high-performance, and power-efficient SoC solutions.\n\nKey Responsibilities\nInterconnect Architecture and System Definition\nContribute to the definition and evolution of SoC interconnect and Network-on-Chip (NoC) architectures.\n\nGather and analyze system requirements, understand product use cases, and translate them into interconnect architecture and functional specifications.\n\nDefine performance, scalability, quality-of-service (QoS), coherency, and latency requirements for interconnect subsystems.\n\nEvaluate and recommend suitable NoC topologies, routing algorithms, arbitration mechanisms, and traffic management schemes.\n\nSystem Modeling and Analysis\nDevelop and utilize behavioral or analytical models to study NoC performance and design trade-offs.\n\nAnalyze system traffic patterns and data flows to optimize interconnect bandwidth, latency, and power efficiency.\n\nCollaborate with performance teams to validate architectural decisions through modeling and simulation.\n\nSoC Architecture Collaboration\nWork closely with CPU, GPU, AI/ML, Multimedia, Memory, Security, Power, and other subsystem teams to define interconnect requirements.\n\nDevelop a strong understanding of:\nSoC boot flows\n\nSecurity architecture\n\nClock and reset architecture\n\nPower management architecture\n\nSystem-level data flows and performance requirements\n\nCross-Functional Engagement\nPartner with architecture, RTL design, verification, physical design, floorplanning, power, and silicon validation teams throughout the product lifecycle.\n\nCollaborate with global engineering teams across multiple sites to ensure alignment on interconnect architecture and implementation.\n\nSupport post-silicon validation efforts by correlating pre-silicon assumptions with measured silicon behavior.\n\nTechnology Leadership and Innovation\nStay current with evolving industry standards, including:\nARM AMBA specifications\n\nCHI, AXI, AHB, ACE/ACE-Lite protocols\n\nPCI Express (PCIe)\n\nCXL\n\nEthernet\n\nUALink\n\nCoherency and virtualization technologies\n\nLow-power design methodologies\n\nDrive continuous improvements in interconnect architecture, design methodologies, performance optimization, and power efficiency.\n\nPropose innovative architectural solutions for future generation NoC and interconnect technologies.\n\nMinimum Qualifications\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\n\n7 to 11 years of experience in SoC architecture, SoC design, NoC architecture, or related system engineering roles.\n\nStrong understanding of on-chip interconnect concepts and industry-standard protocols, including:\nARM CHI\n\nAXI/AHB\n\nACE/ACE-Lite\n\nNoC architectures and coherency concepts\n\nGood understanding of digital design fundamentals and RTL implementation concepts.\n\nHands-on experience with Verilog/SystemVerilog based RTL development and SoC design methodologies.\n\nUnderstanding of multi-core ARMv8/ARMv9 architectures, cache coherency, memory hierarchy, and virtualization concepts.\n\nFamiliarity with performance analysis, system modeling, and architectural trade-off studies.\n\nStrong analytical, problem-solving, communication, and collaboration skills.\n\nPreferred Qualifications\nMaster's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field.\n\nExperience with large-scale SoC architecture for data center, AI/ML, mobile, automotive, or high-performance compute applications.\n\nKnowledge of PCIe, CXL, memory subsystems, coherency fabrics, and virtualization technologies.\n\nExperience working with performance modeling, silicon validation, or system-level architecture analysis.\n\nDemonstrated ability to influence cross-functional teams and drive technical discussions across organizational boundaries.\n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.\n                                                                    OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience.\n                                                                    OR\nPhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Silicon Debug Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-08T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718570230", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Systems Engineering\nQualcomm Overview:\nQualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.\n\nGeneral Summary:\nJoin our Display Processing Unit (DPU) Silicon System Debug team to solve complex, high-impact display issues across leading Qualcomm platforms—working at the intersection of silicon, systems, and software to deliver reliable customer products.\n\nRole Overview\nThe DPU Silicon System Debug Engineer investigates, diagnoses, and resolves complex display subsystem issues across Qualcomm platforms. You will partner with hardware, software, validation, and customer engineering teams to drive rapid root-cause analysis and help the relevant teams implement durable fixes.\n\nLeveling: This position is open at the Engineer and Senior Engineer levels. Level will be determined based on experience, technical depth, and demonstrated ownership.\nEngineer: Contributes to debugging and triage efforts with guidance and builds scripts/tools to improve analysis and turnaround time.\nSenior Engineer: Leads ambiguous, cross-layer investigations end-to-end, influences technical direction across teams, and mentors engineers to scale best practices.\n\nQualcomm is a global leader in wireless technologies and semiconductors, powering many of the world’s connected devices. The DPU Silicon System Debug team sits within the Display Subsystem Hardware Design organization and partners closely with hardware, software, and customer engineering teams to diagnose and resolve critical display failures across multiple product areas, including mobile, automotive, compute, XR/VR, and IoT. Our work helps ensure customer issues are resolved quickly, software teams receive the support they need for their display driver development, and hardware designers get our feedback to roll in changes and fixes for future chips.\n\nThis role focuses on debugging complex display issues that may be SoC-related (e.g., RTL defects, register configuration/sequence issue), system-related (e.g., PCB signal integrity, third-party SerDes interactions), and/or software-related (e.g., HLOS behavior, driver sequencing, race conditions). You will help improve debug efficiency by building workflows and tools to analyze large volumes of system logs, register dumps, and hardware debug data. The team is investing heavily in AI-enabled approaches to accelerate analysis through historical-case learning and agentic automation. You will work in a multidisciplinary, multi-site environment alongside architects, designers, validation engineers, software engineers, and customer engineering teams to resolve high-priority issues with urgency and quality.\n\nQualifications\nWhat you’ll bring (required):\nStrong analytical skills and attention to detail, with the ability to triage and debug complex technical issues\nStrong written and verbal communication skills, including the ability to document findings and align cross-functional stakeholders\nProficiency in C/C++ and Python for tool development, automation, and data analysis\nSolid understanding of digital logic and computer architecture fundamentals\nComfort analyzing large datasets and logs using common analysis tools (e.g., Excel, scripting)\nSystem-level debugging experience (typical ranges: Engineer 2+ years; Senior Engineer 5+ years). Display subsystem experience is a plus.\nNice to have:\nSystem-level debug experience including board bring-up, high-speed signal integrity analysis, and SerDes-based links\nExperience with display interfaces (e.g., MIPI DSI, HDMI, DisplayPort) and related protocols\nExperience with relational databases (e.g., MySQL) for tracking issues, data mining, and/or analytics\nExperience using AI-assisted debugging/development tools or automation to accelerate root-cause analysis\n\nWhat you’ll do\nDebug and root-cause display subsystem issues spanning silicon, board/system interactions, and software/driver behavior\nDevelop and maintain scripts/tools to accelerate analysis of OS logs, register dumps, and hardware debug data\nPartner with hardware, software, validation, and customer engineering teams to reproduce issues, align on hypotheses, and drive fixes to closure\nDocument investigations clearly (symptoms, reproduction steps, root cause, and corrective actions) and communicate status to stakeholders\nSenior Engineer expectation: Lead cross-functional debug efforts end-to-end, mentor teammates, and help define scalable debug processes and best practices\n\nEducation\nBachelor’s degree in Computer Engineering, Electrical Engineering, Computer Science, or a related discipline\nMaster’s degree is preferred but not required\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail myhr.support@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Lead Post-Silicon validation Engineer - SMMU", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-08T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721002234", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nWe’re looking for a hands-on validation engineer to own IP- and subsystem-level verification & validation of System MMU (SMMU) blocks within complex SoCs.\n\nYou will work across ARM-based architectures, MMU/SMMU translation flows, and the surrounding SoC infrastructure—clocks, resets, NoC/fabrics, coherency, and debug (JTAG)—to ensure functional correctness, performance, and robustness from pre-silicon through post-silicon phases.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\n\nWhat You’ll Do (Key Responsibilities)\n\nOwn SMMU validation at block/IP and subsystem levels: coverage-driven test planning, stimulus development, checking/score boarding, and closure.\n\nDevelop test build reusable verification components for SMMU, including page table generators, translation fault injectors, and traffic generators.\n\nValidate system interactions: SMMU with ARM cores, MMU/TLB, NoC/Interconnect, coherency (ACE/CHI or equivalent), and clock/reset domains (including CDC and low-power/clock-gating scenarios).\n\nExercise page table formats and features: stage-1/stage-2 translations, ASIDs/VMIDs, context banks/stream IDs, MSI/IOMMU operations, address translation faults, and SVA/ATS (if applicable).\n\nDebug complex issues using JTAG and on-chip debug/trace infrastructure (ETM/STM/SWO), bring-up scripts, and logic analyzers; drive root cause with design/architecture teams.\n\nPerformance & stress validation: create stress scenarios (burst/atomic/ordering/ QoS), measure bandwidth/latency, and validate backpressure & throttling behavior through NoC.\n\nContribute to emulation/FPGA and post-silicon: port tests, build bare-metal validation, develop board bring-up sequences and lab automation.\n\nOwn quality metrics: functional coverage, code coverage, assertions, defect density/escape rates; author clear test/coverage reports and sign-off criteria.\n\nCollaborate cross-functionally with architecture, RTL design, firmware/driver, physical design, and validation teams to refine specs and close issues quickly.\n\nContinuously improve methodology, tools, and checkers; mentor junior engineers in best practices. \n\nMinimum Qualifications (Must-Haves)\n\nB.E/B.Tech/M.Tech in ECE/EE/CS or equivalent with 3–5 years of relevant experience.\n\nStrong ARM architecture knowledge (A-profile preferred): memory model, privilege levels, exception model, caches, TLBs, MMU concepts, and virtual memory flows.\n\nDeep understanding of SMMU/IOMMU fundamentals: stream IDs, context banks, translation stages, page table formats, fault handling, and device DMA interactions.\n\nFamiliar with NoC/interconnect protocols and coherency (e.g., AXI/ACE/CHI), ordering rules, QoS, and interop with SMMU.\n\nSolid grasp of clocks/resets and their impact on SMMU and NoC behavior; experience validating low-power states and clock gating effects.\n\nJTAG basics to intermediate: scan chains, boundary scan, run-control, breakpoints, basic scripting with OpenOCD/DS-5/Arm Development Studio or similar.\n\nProficient in debugging complex HW/SW issues, using waveforms (e.g., Verdi/DVE), traces, and logs to isolate root cause.\n\nScripting in Python/Perl/TCL/Shell for test automation, log parsing, and lab workflows.\n\nCritical thinking & learning agility: ability to infer failure modes from first principles, design edge-case tests, and quickly onboard new IP/flows.\n\nPreferred Qualifications (Good-to-Have)\n\nPrior tapeouts with SMMU or IOMMU IP (Arm SMMU v2/v3 or equivalent vendor IP).\n\nPost-silicon validation experience: lab bring-up, firmware integration, board-level debug.\n\nExperience with emulation/FPGA prototyping (Veloce, Palladium, Protium, HAPS).\n\nFamiliarity with Linux IOMMU framework, device trees/ACPI, and driver-level validation (DMA mappings, iommu_ops).\n\nKnowledge of PCIe (including ATS/PRI/PASID), CXL, or virtualization stacks (KVM/Hypervisors) and their interaction with SMMU.\n\nExposure to safety/security: memory isolation, SMMU faults as security boundaries, RAS features, error injection and detection.\n\nPerformance modeling/analysis; profiling tools; building synthetic traffic to characterize SMMU/NoC behavior.\n\nCI/CD for verification (Jenkins/GitLab CI), coverage dashboards, and regression triage at scale.\n\nTools & Environment\n\nLanguages/Methodology: ARM assembly, C for bare-metal tests, Python/TCL/Perl for scripting.\n\nEmu/FPGA: Veloce/RUMI\n\nVersioning/CI: Perforce, Jira.\n\nOS/Drivers:  bare-metal frameworks.\n\nKey Performance Indicators (KPIs)\n\nTest plan completeness and functional/code coverage closure against SMMU spec and use-cases.\n\nDefect discovery rate and escape rate (pre- vs. post-silicon).\n\nTime-to-root-cause for complex issues; quality of triage documentation.\n\nRegression stability and automation coverage.\n\nPerformance validation completeness vs. targets (latency, bandwidth, QoS).\n\nExample Work Items You’ll Own\n\nCreate tests for stage-1 and stage-2 translations, ASID/VMID rollover, TLB shootdowns, and context switch stress.\n\nValidate device DMA through SMMU under NoC congestion and clock gating scenarios; confirm ordering and coherency guarantees.\n\nRun JTAG-based bring-up sequences to verify SMMU registers, enable translations, and capture trace for fault analysis.\n\nAutomate validation: configure IOMMU groups, map/unmap devices, inject faults, and parse kernel logs for health signals.\n\nEducation\n\nB.E/B.Tech or M.E/M.Tech in EE/ECE/CS (or equivalent).\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "DDR IP validation and Firmware development (Senior/Lead/Staff)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-08T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721004675", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\n\nUnderstand the IP architecture,  work with IP Design/Verification teams  to understand the validation requirements,  develop/port/enhance  the validation software content and bring up. \n\nDevelop good quality Firmware, understand complex SW scenarios and debug the Firmware issues.\n\nInterface with Design/Software and other teams for the test plan and debugs. \n\nValidate the IP Functionality, expose weakness, find bugs and root cause them\n\nUse silicon debug hooks to measure power/performance/coverage and other KPI metrics \n\nWork with minimal Supervision. Mentor/guide junior co-workers.\n\nGood verbal and written communication skills\n\n MINIMUM QUALIFICATIONS:\nBachelor's/Master's degree in Electrical/Electronics/Computer science Engineering. \n\n2 - 10 years Hardware Engineering experience or related work experience. \n\nExcellent understanding of Embedded systems, Soc Architecture, Processor Architecture and Memory interfacing.\n\nExcellent C expertise and hands-on experience on Firmware development/debug\n\nMust have Experience in  IP Validation\n\nExperience in DDR and other High speed protocols is  added advantage. \n\nExposure to working on emulation/pre-si environment.\n\nExposure to instruments like oscilloscope, Logic analyzer or any other instruments.\n\nUsing JTAG based debuggers, compilers/linkers \n\nShould have good exposure to software development life cycle-Exposure to SoC architecture paradigms  interconnects, power management,  \n\nKnowledge of JTAG based debuggers/compilers/linkers.\n\nSoftware development for silicon enablement, silicon validation \n\nExposure to scripting language preferably python\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "DDR IP validation and Firmware development (Senior/Lead/Staff)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-08T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721004673", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n\nUnderstand the IP architecture,  work with IP Design/Verification teams  to understand the validation requirements,  develop/port/enhance  the validation software content and bring up. \n\nDevelop good quality Firmware, understand complex SW scenarios and debug the Firmware issues.\n\nInterface with Design/Software and other teams for the test plan and debugs. \n\nValidate the IP Functionality, expose weakness, find bugs and root cause them\n\nUse silicon debug hooks to measure power/performance/coverage and other KPI metrics \n\nWork with minimal Supervision. Mentor/guide junior co-workers.\n\nGood verbal and written communication skills\n\n MINIMUM QUALIFICATIONS:\nBachelor's/Master's degree in Electrical/Electronics/Computer science Engineering. \n\n2 - 10 years Hardware Engineering experience or related work experience. \n\nExcellent understanding of Embedded systems, Soc Architecture, Processor Architecture and Memory interfacing.\n\nExcellent C expertise and hands-on experience on Firmware development/debug\n\nMust have Experience in  IP Validation\n\nExperience in DDR and other High speed protocols is  added advantage. \n\nExposure to working on emulation/pre-si environment.\n\nExposure to instruments like oscilloscope, Logic analyzer or any other instruments.\n\nUsing JTAG based debuggers, compilers/linkers \n\nShould have good exposure to software development life cycle-Exposure to SoC architecture paradigms  interconnects, power management,  \n\nKnowledge of JTAG based debuggers/compilers/linkers.\n\nSoftware development for silicon enablement, silicon validation \n\nExposure to scripting language preferably python\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Pre/Post  Silicon Validation Framework/Tools / Infra development engineer, Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-08T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720995821", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nQualcomm's System Validation & Emulation (SVE) organization is seeking exceptional engineers with deep expertise in Embedded Software Architecture, Framework Development, Validation Infrastructure, and System Software Debug. The ideal candidate will possess strong software architecture skills and the ability to root-cause complex issues across multicore, multiprocessor, and heterogeneous SoC environments spanning hardware, firmware, operating systems, validation frameworks, and system infrastructure.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nResponsibilities\n\nArchitect, design, develop, and maintain scalable embedded software frameworks, validation infrastructure, and platform software for pre-silicon and post-silicon SoC validation.\n\nDevelop reusable framework components, platform abstraction layers, middleware, and system software services supporting multicore and heterogeneous compute environments.\n\nDrive software architecture and framework design to enable portability, scalability, maintainability, and reuse across multiple SoC programs and IP validation domains.\n\nDevelop and maintain bring-up, validation, and debug infrastructure for bare-metal, lightweight RTOS, emulation, FPGA, and post-silicon environments.\n\nDebug and root-cause complex system-level issues spanning hardware, firmware, operating systems, framework software, memory subsystems, coherency fabrics, and system infrastructure IPs.\n\nDevelop framework capabilities supporting multicore, multiprocessor, and heterogeneous CPU architectures, including system-level synchronization, coherency, and performance optimization.\n\nDesign, implement, and optimize automated validation, regression, and release workflows to improve productivity, quality, and scalability.\n\nIntegrate static analysis, code-quality tools, build systems, and release processes into Continuous Integration (CI) environments.\n\nCollaborate closely with architecture, design, verification, firmware, software, and validation teams to enable efficient silicon bring-up, feature validation, and debug.\n\nDrive continuous improvements in software quality, framework architecture, automation, and validation methodologies.\n\nMinimum Qualification\nBachelor’s or Master’s degree in Computer Science, Electronics & Communication Engineering, Electrical Engineering, Computer Engineering, or a related field.\n\n6+ to 10 years of industry experience in Embedded Software, System Software, SoC Validation, Silicon Enablement, Platform Software, Framework Development, or related domains.\n\nProven experience in embedded software architecture, framework development, low-level software design, and complex system-level debug.\n\nStrong analytical, problem-solving, and debugging skills in hardware-software integrated environments.\n\nMandatory Skills\nStrong expertise in Embedded Software Architecture, Framework Design, and Infrastructure Development using C, C++, and Assembly.\n\nProven experience designing and developing scalable software frameworks, platform abstraction layers, middleware, validation infrastructure, and reusable system software components.\n\nExtensive experience in low-level software development, including boot code, exception handling, interrupt management, startup sequences, and C-Assembly interworking.\n\nDeep understanding of CPU architectures and microarchitectural concepts, including ARMv8/ARMv9, x86, and PowerPC architectures.\n\nStrong expertise in multicore, multiprocessor, and heterogeneous SoC environments, including SMP, AMP, heterogeneous compute subsystems, and cross-core software interactions.\n\nDemonstrated ability to debug complex system-level issues spanning hardware, firmware, operating systems, framework software, and validation infrastructure.\n\nStrong understanding of cache coherency, I/O coherency, memory ordering, synchronization primitives, inter-processor communication, and concurrency-related issues.\n\nDeep knowledge of SoC architecture, including compute subsystems, memory hierarchies, interconnect fabrics, power management, and system infrastructure IPs.\n\nStrong understanding of Operating Systems, RTOS, and Linux kernel internals, including multithreading, scheduling policies, locking mechanisms, interrupt handling, virtual memory, MMU architecture, and kernel synchronization primitives.\n\nDeep understanding of memory management, weakly ordered memory models, cache architectures, pipelining, memory barriers, TLBs, coherency protocols, and performance optimization techniques.\n\nStrong expertise in software build infrastructure, compiler toolchains, linker internals, Makefiles, linker/scatter scripts, and build system architecture.\n\nProficiency with GCC, Clang/LLVM, ARM toolchains, code optimization techniques, and root-causing complex compiler and linker issues.\n\nStrong debugging expertise using JTAG, trace, emulation, FPGA, and silicon debug tools.\n\nProficiency in Python and Shell scripting for automation, framework development, debug, and productivity tooling.\n\nDesired Skills\nExperience architecting and developing large-scale embedded software frameworks or validation infrastructure used across multiple engineering teams and SoC programs.\n\nExperience with silicon bring-up, board bring-up, post-silicon validation, and hardware-software integration.\n\nHands-on experience with pre-silicon emulation, FPGA prototyping, and post-silicon debug environments.\n\nStrong understanding of ARM-based SoC architectures, memory hierarchies, cache coherency protocols, interconnect fabrics, and system infrastructure IPs.\n\nExperience developing framework abstractions supporting heterogeneous processing elements such as application processors, real-time processors, DSPs, AI/ML accelerators, and security subsystems.\n\nFamiliarity with CI/CD systems, automated regression infrastructure, release management, and software quality methodologies.\n\nExperience with JTAG, Lauterbach Trace32, hardware trace, and performance analysis tools.\n\nExperience with source code management systems such as Git and Perforce.\n\nFamiliarity with build automation, containerized development environments, and scalable software deployment workflows.\n\nExperience mentoring engineers and driving technical direction for framework and infrastructure development initiatives.\n\na\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Emulation Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-08T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446721009170", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field.\n\nPreferred Qualifications:\n•    Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.\n•    3+ years of ASIC design, verification, validation, integration, or related work experience.\n•    2+ years of experience with architecture and design tools.\n•    2+ years of experience with scripting tools and programming languages.\n•    2+ years of experience with design verification methods.\n Principal Duties & Responsibilities:\n•    Applies ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.\n•    Creates architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.\n•    Collaborates across teams (e.g., software architecture, hardware architecture) to develop and execute an implementation strategy that meets system requirements and customer needs.\n•    Evaluates all aspects of process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.\n•    Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable architecture and design of an individual block/SoC or IC Package.\n•    Writes detailed technical documentation for EDA/IP/ASIC projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc.  \n•    Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions).\n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Infra Design Verification Staff Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-08T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720380685", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nWe are looking to hire a strong DV engineer to work on verification of DDR Subsystem in the Infra IP team\nCreate DV infrastructure for verification\n\nIntegrate VIP's\n\nCreate and execute test plans, debug failures, write assertions, close code and functional coverage\n\nEnsure high quality verification\n\nWorking with all stakeholders to ensure program success\n\nMinimum Qualifications\nBachelor's degree in Engineering, Electronics, Information Systems, Computer Science, or related field.\n5+ years Hardware Engineering experience or related work experience.\nPreferred Qualifications\nFollowing skill set is required:\nStrong Debug, UVM, System Verilog\n\nUnderstanding Specs and Standards and developing relevant test plans\n\nMonitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved\n\nCandidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening\n\nPreferred Qualifications 5+ Year of industry experiences in the following areas: -\nThorough understanding of Digital design concepts\n\nThorough understanding dv methodologies and tools\n\nGood understanding of LPDDR4/LPDDR5 protocols\n\nUnderstanding of Bus protocols like AHB/AXI/ACE/ACE-Lite\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Formal Verification Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-08T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446714961100", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Description\nWe are seeking a highly motivated Formal Verification Engineer with 6-8 yeas of experience to join our GCAD Formal team. The ideal candidate will have strong formal verification fundamentals, hands-on experience with formal tools, excellent analytical and scripting skills, and the ability to drive innovative verification methodologies. This role provides the opportunity to collaborate across global architecture, design, and systems teams to influence and strengthen verification sign‑off quality.\nWhat You Will Be Doing\nDrive formal verification of complex design blocks using advanced Formal Apps and robust convergence strategies to achieve exhaustive and high‑confidence sign‑off.\nCollaborate with worldwide architecture, design, and systems teams to achieve verification goals.\nReview and refine formal setups, proofs, constraints, and abstractions with design/DV teams.\nEngage with EDA vendors and evaluate advanced DV methodologies to improve sign‑off quality.\nDevelop automation scripts (Python preferred) to enhance efficiency and scalability of FV flows.\nAnalyze challenging formal problems and propose effective verification strategies.\nLow power formal methodology\nWhat We Need to See\n2+ years of hands-on experience in Formal Verification.\nStrong understanding of formal concepts, proof strategies, and abstraction techniques.\nProficiency with formal tools (Jasper, VC Formal, Questa Formal, etc.).\nWorking knowledge of property-based FV (SVA ) is a plus.\nExcellent scripting skills (Python strongly preferred).\nStrong analytical and problem‑solving abilities.\nClear communication skills and ability to collaborate with global teams.\nA strong willingness to learn, innovate, and deliver high‑quality results.\nLow‑power knowledge is a plus (e.g., power‑aware verification concepts, UPF/CPF, isolation/retention, power/clock gating, power‑aware apps, and basic power‑intent debugging).\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NOC Design Verification Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-08T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720502329", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nLooking for an experience Verification Architect/ Engineer, who will be responsible Verification of next generation Infrastructure IPs (DDRSS, Memory Controllers etc.) which goes into System-on-chip (SoC) for smartphones, tablets and other product categories. In this position you will be expected to plan and implement IP/Cluster/Formal verification flows for the Infra IPs. Also expected to coordinate with different Design and SOC teams throughout the IP development cycle.  \nJob responsibilities include \n·              Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage) \n·              Develop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench \n·              Work closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure \n·              Debug of regression signatures and identifying bug fixes \n·              Responsible for Quality sign off and required documentation \n·              Developing/Deploying scripts/tools for validation (Certitude, VC Formal, VPlan) \n·              Debug and root cause post silicon issues in collaboration with Design, SW and test teams \n·              Work with SoC level performance modeling team on latency, bandwidth analysis \nnext-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\nAdditional Job Description\nRequired skillset include \n·              Strong debugging, Analytical and problem-solving skills \n·              Expertise on UVM based verification  \n·              Knowledgeable about ARM bus protocols, Virtual Memory concepts, SoC system architecture \n·              Experience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved \n·              Communication and collaboration skills to work with a large world-wide design organization \n\nDesired skillset includes \n·              Experience in designs optimized for low power - Dynamic clock gating, Logic/ Memory power collapse  \n·              Experience in verifying designs meeting Automotive Safety Integrity Levels (ASIL) \n·              Proficiency in Scripting languages (Python or Perl) for Automation initiatives, C/C++/SystemC for performance models \n·        Post-si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage \nQualification : \n·        Bachelor/Master’s Degree in Electronics & Communication / Micro Electronics \n·        8+ Years of Experience in IP verification or related\n·        Experience with UVM and ARM Bus protocols. \n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-08T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720513978", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    3+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n\nPrincipal Duties and Responsibilities:\n•    Applies Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Assists in the assessment of complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "LPASS Design Verification Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-08T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720126568", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nQualcomm LPASS HW team in Bangalore is part of a worldwide team responsible for developing and delivering Audio solutions which are setting the benchmark in mobile computing industry. The role of LPASS DV Engineer will involve a deep understanding of the HW architecture while getting an opportunity to work with the latest DV tools and technologies.\nIndividual responsibility will include\nDV ownership of one or more features in the Low power audio subsystem(LPASS) core\n\nDeveloping a robust testbench, optimized for the specific feature/DUT\n\nExplore innovative DV methodologies (formal, simulation and emulation based) to continuously push the quality and efficiency of test benches and process improvements.\n\nEnsure a bug free silicon for Tape Out which eventually leads to a superb user experience of Snapdragon based computing devices\n\nFor better understanding of some of our products, please refer to the links below\nhttps://www.qualcomm.com/products/smartphones\nQualcomm Aqstic | Qualcomm\n\nMinimum Qualifications\nMinimum 1 - 2  years of VLSI industry experience\n\nStrong debugging and analytical skills\n\nStrong knowledge of HDLs like Verilog, System Verilog\n\nProficiency in developing SV/UVM based test benches\n\nProficient in debugging RTL/TB issues using Verdi or similar tools\n\nProficient with scripting languages such as Perl and(or) Python\n\nPreferred Qualifications *\nKnowledge of UPF, low power  architecture\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Wireless R&D Design Verification Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-08T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720973550", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nJob Title: Wireless R&D IP Design Specialist\nLocation: Bangalore\nRoles and Responsibilities\nContribute to flagship Wireless IP development covering WAN, WLAN, GNSS, and Bluetooth technologies.\n\nDefine and develop next-generation Wireless R&D products.\n\nWork on front-end RTL design for wireless IP or DSP-based IPs.\n\nDevelop micro-architecture and RTL coding using System Verilog, Verilog, or VHDL.\n\nCollaborate with multi-geo teams for design and verification.\n\nTechnical Requirements\nStrong experience in IP design (preferably wireless/DSP domain).\n\nExposure to synthesis and Static Timing Analysis (STA).\n\nAwareness of low-power and high-speed design techniques.\n\nFamiliarity with industry-standard front-end flows (lint, CDC, etc.).\n\nProficiency in scripting and automation: Unix/Linux shell, Perl, Python, Makefile.\n\nStrong problem-solving, debugging, and critical thinking skills.\n\nQualifications\nEducation: Bachelor’s or Master’s or PhD in Electrical/Electronics/Computer Science from a reputed institution.\n\nExperience:  2- 12 years\n\nSoft Skills\nGood communication and interpersonal skills.\n\nFlexibility to work with global teams.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "EDA Software Operations", "company": "Lattice", "location": "LPQ", "date_posted": "2026-09-08", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/LPQ/EDA-Software-Operations_R-103221", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nRole Summary\nThe organization is seeking an experienced Staff-level EDA / Software Operations Specialist to manage the end-to-end lifecycle of both EDA and enterprise software vendor engagements. This role serves as the primary liaison between engineering, procurement, finance, and legal functions to ensure that all vendor contracts, renewals, and purchase transactions are executed in a timely, compliant, and cost-effective manner. Given the scale and complexity of the vendor portfolio, the role requires strong project management discipline to track hundreds of concurrent threads across contracts, approvals, and stakeholders, along with excellent communication skills to coordinate effectively across cross-functional and often global teams.\nKey Responsibilities\nManage the complete lifecycle of EDA and Software vendor contracts, including new agreements, renewals, extensions, and terminations, across multiple vendors and tool categories.\nTrack license utilization, renewal timelines, and contract expiry dates across a large and diverse vendor portfolio, proactively initiating renewal discussions to avoid business disruption.\nRaise and manage Purchase Requisitions (PRs) and Purchase Orders (POs) for EDA tools, software licenses, and related services, ensuring accuracy of commercial terms, quantities, and cost centers.\nPartner with Finance teams to obtain budget approvals, validate cost allocations, and ensure alignment with departmental and organizational budgets.\nCoordinate with Legal teams to route vendor contracts, Master Service Agreements (MSAs), Non-Disclosure Agreements (NDAs), and amendments through the appropriate review and clearance process.\nNegotiate commercial terms, pricing structures, and licensing models with EDA and Software vendors in collaboration with sourcing/procurement stakeholders, where applicable.\nApply strong project management practices to simultaneously track hundreds of active threads, spanning contract negotiations, approval workflows, renewal deadlines, and stakeholder follow-ups, ensuring nothing falls through the cracks.\nMaintain accurate, well-organized, and up-to-date records of all vendor contracts, license entitlements, renewal schedules, and approval documentation.\nServe as the key point of contact for internal engineering, IT, and design teams regarding EDA and software license availability, tool access issues, and procurement status.\nCommunicate proactively and clearly with stakeholders across Engineering, Finance, Legal, Procurement, and vendor-side teams, providing regular status updates and escalating risks or delays in a timely manner.\nSupport internal and external audits by ensuring proper documentation, license compliance, and adherence to organizational procurement policies.\nIdentify opportunities for cost optimization, license right-sizing, and consolidation across EDA and software vendor contracts.\nPrepare periodic reports and dashboards on vendor spend, renewal pipeline, and vendor performance for management review.\nCollaborate with cross-functional stakeholders across geographies, given the global nature of EDA and software vendor relationships.\nRequired Skills and Experience\n6 to 9 years of relevant experience in EDA Operations, Software Asset Management, IT Procurement, or a similar vendor/contract management function within a semiconductor or technology organization.\nDemonstrated experience working directly with EDA vendors and familiarity with common EDA licensing models (node-locked, floating, term-based licenses), as well as experience managing enterprise software vendor contracts.\nStrong understanding of procurement processes, including purchase requisition and purchase order workflows within enterprise systems (e.g., SAP, Oracle, Coupa, or similar).\nWorking knowledge of contract lifecycle management, including experience coordinating with Legal teams on contract review and clearance.\nExperience partnering with Finance functions on budgeting, cost tracking, and invoice reconciliation.\nStrong project management skills, with proven ability to track and manage a high volume (hundreds) of parallel threads, deadlines, and stakeholder actions without losing accuracy or momentum.\nExcellent communication skills, both written and verbal, with the ability to clearly convey status, risks, and priorities to diverse stakeholders including senior management, vendors, and cross-functional teams.\nStrong negotiation and stakeholder management skills.\nHigh attention to detail with strong organizational and documentation practices.\nAbility to manage multiple vendor renewals and deadlines simultaneously in a fast-paced environment.\nBachelor’s degree in engineering, Business Administration, Finance, or a related field. An advanced degree is a plus but not mandatory.\nPreferred Qualifications\nPrior experience specifically in a semiconductor design company or design services organization.\nFamiliarity with license management tools (e.g., FlexLM/FlexNet) and license usage monitoring practices.\nFamiliarity with project/task tracking tools (e.g., Jira, Smartsheet, MS Project, or similar) to manage high-volume workstreams.\nExposure to global vendor contract negotiations across multiple regions.\nFormal project management certification (e.g., PMP, PRINCE2) is an added advantage.\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Senior Staff Design Engineer", "company": "Lattice", "location": "Penang, Malaysia", "date_posted": "2026-09-08", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Penang-Malaysia/Senior-Staff-Design-Engineer_R-103219", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\n\nAs a Lead Modeling Design Engineer, you will be responsible for overseeing and contributing to the creation and validation of models used for Lattice FPGAs, ensuring their accuracy and performance.  You will lead the technical development with a team of engineers, collaborate with cross-functional teams, and drive the design and development of high-quality models for our products.\n\nKey Responsibilities:\nLead the development and validation of models for analog, digital, and mixed-signal circuits.\n\nUtilize simulation tools such as Verilog, VHDL, SystemVerilog, or similar, to perform digital circuit analysis.\n\nProvide technical leadership and mentorship to a team of circuit modeling engineers.\n\nCollaborate with design engineers to understand circuit requirements and specifications.\n\nCollaborate with internal customers/consumers of the models to assure their needs are comprehended and objectives are met.\n\nAnalyze simulation results and provide feedback to improve circuit designs.\n\nOptimize circuit models for performance, accuracy, and efficiency.\n\nDocument modeling processes, assumptions, and results for internal and external stakeholders.\n\nStay updated with the latest advancements in circuit modeling techniques and tools.\n\nQualifications:\nBachelor’s or Master’s degree in Electrical Engineering with 10+ years of experience.\n\nProven experience in circuit modeling and simulation.\n\nProficiency in using circuit simulation tools such as SPICE, Verilog, VHDL, System Verilog, or similar.\n\nStrong leadership and team management skills.\n\nExcellent analytical and problem-solving abilities.\n\nExcellent communication and collaboration skills.\n\nExperience with data analysis and visualization tools is a plus.\n\nKnowledge of semiconductor devices and circuit design principles is preferred.\n\n#LI-DNP\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nMalaysiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Server Performance Architect - Hardware", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-09-08", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Architect---Server-Performance_JR2016230", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nNVIDIA is seeking architects to drive architectural performance for its next-generation AI server systems. This position demands a unique capability to bridge deep architectural knowledge, workload analysis, and hands-on silicon investigations. Candidates should be adept at working directly with silicon, high-level models, and simulators. Responsibilities include conducting performance investigations on both NVIDIA and competitive platforms, and developing targeted microbenchmarks to examine specific architectural aspects. The role does not heavily involve modeling tasks (functional or performance), though occasional focused assignments may arise.\n\nWhat you’ll be doing:\nDefining and driving server-level performance targets across CPU, GPU, memory, interconnect, networking, and storage subsystems\n\nConducting hands-on workload characterisation and bottleneck analysis on NVIDIA and competitive server platforms using AI training, inference, and HPC benchmarks\n\nLeveraging profiling, tracing, and analysis tools to root-cause performance issues and identify optimisation opportunities at the system level\n\nPerforming trade-off studies on system topology, thermal/power envelopes, and memory hierarchy to guide architectural decisions\n\nCollaborating with silicon, platform, firmware, and software teams to identify and close performance gaps from bring-up through production\n\nDeveloping automation and tooling for performance regression tracking and reporting\n\nRepresenting the performance perspective in architecture reviews and cross-functional design discussions\n\nBuilding and maintaining analytical performance models and simulation frameworks for next-generation server platforms\n\nPublishing internal performance studies and best-practice guides for partner and customer enablement\n\nWhat we need to see:\nBS, MS, or PhD in Electrical/Computer Engineering, Computer Science, or equivalent experience\n\n10+ years of experience in server/system performance architecture or related disciplines\n\nDeep understanding of modern server architectures — CPU microarchitecture, PCIe/CXL, DDR/HBM memory subsystems, and coherency protocols\n\nStrong hands-on experience with system-level profiling and performance analysis tools on server platform(s)\n\nSolid knowledge of GPU-accelerated compute, high-performance networking, or high-performance storage subsystems\n\nProficiency in Python, C/C++, or similar languages for scripting, data analysis, and tool development\n\nComfortable and proficient using AI-powered coding and productivity tools to accelerate analysis, automation, and documentation workflows\n\nExcellent communication skills with the ability to distil complex performance data into actionable architectural recommendations\n\nWays to stand out from the crowd:\nExperience with AI/ML training and inference workloads at data-centre scale\n\nFamiliarity with NVIDIA GPU architectures (Hopper, Blackwell, Rubin) and associated software stacks (CUDA, NCCL)\n\nBackground in chip-to-chip interconnect performance analysis (C2C, UCIe)\n\nExposure to power/thermal-aware performance optimisation techniques\n\nTrack record of contributions to industry conferences or published performance studies\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Principal ASIC Verification Engineer - DDR/LPDDR", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-08", "url": "https://careers.synopsys.com/job/bengaluru/principal-asic-verification-engineer-ddr-lpddr/44408/100351393200", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou understand that verification is not about writing tests, it is about building an environment where the right bugs cannot hide, and you have the scars from finding those bugs at 2am to prove it.\nLeading a team does not mean delegating tasks, it means knowing when to step in, when to let someone struggle productively, and when to rewrite the testbench architecture because the current one will not scale. You have worked with RTL designers who swear their code is clean and architects who change the spec on Thursday, and you have learned to build verification strategies that survive both.\nMemory protocols like DDR or LPDDR do not intimidate you. Serial interfaces, complex checkers, SystemVerilog assertions that actually mean something, these are tools you reach for without thinking. You care about functional coverage because it tells you what you have not tested yet, not because it is a metric someone asked for. At Synopsys, you will work on DesignWare IP that powers real products, with a team that takes verification as seriously as you do.\n\nWhat You'll Be Doing\nLead a team of verification engineers through full IP verification cycles, from test plan definition through coverage closure and signoff\nBuild and evolve SystemVerilog/UVM verification environments for DesignWare synthesizable IP cores, ensuring they scale across multiple product generations\nDefine test plans that cover corner cases, protocol compliance, and system-level interactions, then review and guide implementation across the team\nWrite and debug complex testbenches, checkers, and assertions for serial interface protocols and memory controllers, including DDR and LPDDR where applicable\nExtract, analyze, and drive functional coverage and code coverage metrics to closure, identifying gaps and adjusting strategy in real time\nCollaborate directly with RTL designers, digital architects, and circuit teams to align verification scope with design intent and catch issues early\nManage regression infrastructure and work with the infra team to keep verification cycles efficient and reliable\n\nThe Impact You Will Have\nDeliver verification signoff on IP cores that ship in millions of devices, ensuring they work correctly the first time in silicon\nRaise the bar for verification quality across the DesignWare team by mentoring engineers and evolving testbench architecture and methodology\nCatch critical bugs before tapeout that would otherwise cost months of schedule and customer trust\nInfluence IP architecture decisions by surfacing verification insights early, when design changes are still cheap\nHelp shape how the team adopts AI-assisted verification flows, improving efficiency without sacrificing rigor\nContribute to Synopsys' leadership in IP by ensuring that what we deliver is not just feature-complete but robustly verified\nBuild verification environments and strategies that other teams will reuse and learn from, multiplying your impact across the organization\n\nWhat You'll Need\nBachelor's or Master's in Electrical Engineering or Electronics and Communication Engineering with 8+ years of hands-on verification experience\nProven track record leading verification teams through IP project delivery, including planning, execution, and signoff\nStrong experience developing SystemVerilog/UVM testbenches from scratch and evolving them as designs grow\nDeep expertise writing test plans, implementing checkers, and building assertions that catch real bugs\nProficiency extracting and interpreting functional coverage and code coverage, and using those metrics to drive verification closure\nExperience verifying serial interface protocols and working through IP design and verification processes, knowledge of DDR or LPDDR protocols is a strong plus\nDemonstrated ability to own end-to-end verification deliverables, including metric closure and formal review signoff, experience with AI-assisted verification tools is a plus\n\nWho You Are\nYou can explain a coverage hole to an architect in two sentences and walk out with a plan to close it\nYou debug by hypothesis, not by adding print statements until something makes sense\nWhen a testbench is too slow or too brittle, you refactor it instead of working around it\nYou give feedback that makes engineers better, not just feedback that makes the code pass\nYou work across time zones and teams without losing context or creating confusion downstream\nYou know when to push back on a design decision and when to adjust the verification plan to match reality\n\nThe Team You'll Be Part Of\nYou will join Synopsys' DesignWare IP Verification R&D team in Bangalore, working with a global group of experienced verification engineers who are responsible for ensuring the quality and reliability of IP cores that power semiconductors across the industry. This team collaborates closely with RTL designers, architects, and infrastructure engineers to deliver robust, production-ready IP.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Principal DFT Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-08", "url": "https://careers.synopsys.com/job/bengaluru/principal-dft-engineer/44408/100351393184", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:\n\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\n You Are:\nYou are a passionate and detail-oriented ASIC DFT professional who thrives in high-tech, fast-paced environments. With a strong foundation in Design-for-Testability (DFT) methodologies, you enjoy taking ownership of complex challenges and delivering reliable, high-quality results. You are eager to collaborate with diverse, global teams and are driven by a desire to continuously learn and grow within the semiconductor industry. Your expertise in technically leading team in scan insertion, ATPG, and scan STA is matched by your ability to adapt to new AI tools and technologies. You value open communication, inclusivity, and knowledge sharing, and you excel at translating intricate technical concepts into actionable solutions. As a proactive problem solver, you are comfortable navigating ambiguity and take pride in mentoring junior engineers while contributing to collective team success. Your leadership abilities allow you to guide technical teams and enhance DFT methodologies, flow ensuring high-quality deliverables.You are committed to upholding Synopsys' culture of innovation, integrity, and excellence, and you are excited about building next-generation semiconductor products that fuel advances in AI, automotive, and beyond.\n \nWhat You'll Be Doing:\n\nLead and drive execution of scan insertion and ATPG (Automatic Test Pattern Generation) flows for complex IP designs along with a team of talented DFT engineers.\nWork closely with RTL and Verification teams to ensure DFT requirements are integrated early in the design cycle.\nAnalyze/resolve DFT-related issues using tools such as Spyglass DFT, ensuring robust test coverage and manufacturability.\nGuide team/Perform scan STA (Static Timing Analysis) to validate timing closure and optimize testability paths.\n\nUse AI tools/flow for DFT tasks execution to improve the efficiency.\nCollaborate with cross-functional teams and central DFT methodology team to define and implement best practices for DFT methodologies and flows.\nContribute to the continuous improvement of automation and design flows to boost efficiency and reduce turnaround time.\n\nThe Impact You Will Have:\nEnhance the testability and reliability of cutting-edge ASIC products, reducing defect rates and improving time-to-market.\nDrive innovation in DFT flows, setting new standards for quality and efficiency within the organization.\nCollaborate with a global team of experienced engineers, fostering a culture of knowledge sharing and continuous learning.\nEnable successful silicon validation and ramp-up, directly contributing to customer satisfaction and business growth.\nRepresent Synopsys as a technical leader in the industry, influencing best practices and future technology directions.\nContribute to the development of next-generation technologies in AI, automotive, and other high-impact sectors.\n\nWhat You'll Need:\n\nBS/MS in Electrical Engineering or Electronics and Communication Engineering with 8+ years of relevant experience.\nPast experience of technically leading a team for DFT execution of IP projects. Experience in effective collaboration and stakeholder management with program management, design/verification and design implementation teams.\nProven experience in DFT methodologies, including scan insertion and ATPG for complex ASIC designs. \nProficiency with industry-standard EDA tools such as Spyglass DFT and scan STA analysis suites.\nDemonstrated ability to debug and resolve DFT-related issues across multiple project phases.\nSome experience of using AI tools for DFT tasks and other basic tasks (script generation/usage) to automate design and test flows.\nBasic understanding of digital logic design, and verification principles is also useful.\n\nWho You Are:\n\nCollaborative team player who communicates effectively across functions and cultures.\nProactive problem solver, comfortable with ambiguity and rapid change.\nDetail-oriented and highly organized, with a commitment to delivering high-quality results.\nInclusive and open-minded, eager to share knowledge and mentor others.\nSelf-motivated and driven by curiosity, with a continuous learning mindset.\n\nThe Team You'll Be A Part Of:\nYou will join a dynamic and innovative front end IP team which includes design, verification and DFT sub teams within Synopsys' Engineering organization in Bangalore. The DFT team is dedicated to advancing ASIC testability and reliability, working collaboratively with design, verification, and software groups across the globe. Our culture values technical excellence, mentorship, and cross-disciplinary innovation, providing opportunities to work on industry-leading products that power the next wave of intelligent systems.\n\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Application Engineer - Sr Staff, DFT/ Design for Test", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-08", "url": "https://careers.synopsys.com/job/bengaluru/application-engineer-sr-staff-dft-design-for-test/44408/100333570000", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years deep in semiconductor design, and you know that getting a chip to tape-out is only half the story. The other half is making sure it can actually be tested at scale, in volume, without blowing up the schedule or the yield. You understand DFT not as a checkbox but as a discipline that makes or breaks manufacturability, and you have the hands-on experience with scan insertion, ATPG, and tool flows to prove it.\nYou are comfortable sitting across from a customer's design team, listening to their constraints, their timeline pressures, their tool frustrations, and walking out with a plan that turns those constraints into a working solution. You do not just demo tools, you configure them, script around their edges, and make them fit the problem. TCL, Python, Perl are not languages you look up, they are tools you reach for without thinking.\nYou translate well. Between customer requirements and R&D roadmaps. Between technical depth and executive summaries. Between what the tool can do today and what the customer needs by next quarter. At Synopsys, you will work on DFT solutions that shape how the industry builds and tests silicon, and the customers you support will remember the difference you made.\nWhat You'll Be Doing\nWork directly with semiconductor customers to understand their DFT challenges, design constraints, and tool flow requirements, then translate those into technical solutions using Synopsys DFT tools including TestMAX Manager\nConfigure, customize, and deploy DFT tool flows tailored to customer designs, including scan insertion, ATPG, and verification using TestMAX ATPG, Formality, and VCS\nDeliver hands-on technical demos and proof-of-concept implementations that show customers exactly how the toolset solves their specific design and test problems\nScript automation solutions in TCL, Python, or Perl to streamline customer workflows, improve tool adoption, and address gaps in existing flows\nCollaborate with Account teams to gather requirements, align on customer priorities, and provide regular technical updates throughout the engagement lifecycle\nPartner with R&D to surface customer feedback, reproduce tool issues, and influence product roadmap decisions based on real-world design challenges\nStay current on DFT methodologies, semiconductor design trends, and emerging test strategies to ensure the solutions you deliver remain relevant and scalable\nThe Impact You Will Have\nEnable customers to achieve faster time-to-market by delivering DFT solutions that reduce design iterations and improve test coverage\nIncrease adoption and satisfaction with Synopsys DFT tools by making them work seamlessly within customer design environments\nStrengthen customer relationships and retention by becoming the trusted technical advisor who understands their design challenges and delivers results\nInfluence the direction of Synopsys DFT product development by bringing real customer requirements and pain points directly to R&D\nImprove silicon yield and manufacturability across the industry by helping customers implement robust, scalable DFT methodologies\nReduce customer support escalations by proactively solving tool flow issues and building automation that prevents common failure modes\nProtect and grow Synopsys' leadership position in semiconductor design by ensuring customers see measurable value from the toolset\nWhat You'll Need\nMaster's degree (M.Tech or equivalent) in Electrical Engineering, Computer Engineering, or a related technical field\n8 to 12 years of hands-on experience in semiconductor design, DFT engineering, or related domains with direct exposure to VLSI design principles and design flows\nDeep working knowledge of Design for Testability methodologies, including scan insertion, ATPG, and DFT verification techniques\nProficiency in scripting languages such as TCL, Python, or Perl for automation, tool customization, and workflow optimization\nDirect experience with semiconductor design tools and flows, exposure to TestMAX Manager, Formality, VCS, or TestMAX ATPG is a strong plus\nDemonstrated ability to work directly with customers, gather technical requirements, and deliver solutions that meet both technical and business objectives\nStrong analytical and problem-solving skills with a track record of diagnosing complex tool or design issues and finding practical paths forward\nWho You Are\nYou can walk into a customer meeting, listen to a messy design problem, and sketch out a tool flow solution on a whiteboard that makes sense to both the engineer and their manager\nYou do not wait for perfect documentation or complete specs, you ask the right questions, fill in the gaps, and move forward with what you have\nYou are comfortable being the bridge between customer frustration and R&D priorities, translating 'this does not work' into reproducible cases and actionable feedback\nYou stay curious about what is changing in DFT, test strategies, and semiconductor design, and you bring that knowledge into the solutions you build\nYou follow through, when you commit to a customer deliverable or a timeline, you make it happen or communicate early when something shifts\nYou are technical enough to debug a tool flow issue yourself and collaborative enough to know when to pull in the right expert from another team\nThe Team You'll Be Part Of\nYou will join a team of Product Engineers and Product Specialists focused on advancing semiconductor design methodologies and delivering measurable value to customers. This team works closely with Application Engineers and R&D to ensure customer needs are met with solutions that are reliable, scalable, and grounded in real-world design challenges. The work you do here protects Synopsys' reputation for excellence in the semiconductor industry and directly influences how customers experience and adopt our DFT toolset.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\n#TPG", "jd_status": "stored"}, {"title": "Staff QA Engineer", "company": "Lattice", "location": "Pune, India", "date_posted": "2026-09-08", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Pune-India/Staff-QA-Engineer_R-103088", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nKey Responsibilities\n• Design and develop comprehensive functional and automation test cases based on detailed analysis of customer workflows, requirement specifications and use cases\n• Create and maintain sophisticated test automation frameworks that interact with hardware, firmware layers, and software components\n• Execute hands-on testing across solutions, including validation of hardware-firmware integration and performance benchmarking\n• Develop expertise in domain specific solutions and translate their operational workflows into comprehensive test scenarios\n• Collaborate with firmware engineers, hardware teams, and product managers to understand technical requirements and customer expectations\n• Identify, document, and verify fixes for defects across the hardware, firmware, and application layers\n• Optimize test execution and automation frameworks to improve efficiency and reduce time-to-quality.\n• Provide technical leadership in QA methodologies, best practices, and test automation architecture\n• Mentor junior QA team members and contribute to continuous improvement of testing processes\n• Generate detailed test reports and provide actionable insights to stakeholders on product quality and readiness\nRequired Qualifications\n• 7+ years of hands-on QA engineering experience, with a minimum of 4+ years specifically in solutions testing, functional and automation testing\n• Demonstrated expertise in developing test automation frameworks and test cases for ASIC/SOC/firmware based systems\n• Strong understanding hardware description languages (Verilog, VHDL), and hardware/firmware design principles\n• Demonstrated experience in developed AI based automation frameworks to reduce time to testing\n• Proven experience with firmware layer testing and hardware-firmware integration validation\n• Proficiency in one or more test automation programming languages (Python, C, C++, SystemVerilog, or Tcl)\n• Experience with hardware test equipment, logic analyzers, oscilloscopes, and embedded system debugging tools\n• Proven ability to analyze solution workflows and translate them into detailed, executable test cases\n• Strong problem-solving skills and the ability to troubleshoot complex hardware-firmware-software integration issues\n• Experience working directly with customer environments and understanding production deployment scenarios\n• Excellent communication skills and ability to collaborate across cross-functional teams\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Senior IP Architect – Unified Intel Chassis (UIC) IP and Platform Architecture", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-08", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Senior-IP-Architect---Unified-Intel-Chassis--UIC--IP-and-Platform-Architecture_JR0286858", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nRole Overview:\n\nWe are looking for an architecture lead to define and drive architecture specifications for Unified Intel Chassis (UIC) IP components and subsystems. This role combines architecture definition with implementation awareness and performance ownership.\n\nThe candidate will work on platform-level performance, including building performance environments and driving closure in partnership with system architects and cross-functional teams.\n\nDefinition of platforms-\nFrom IP level performance modelling platforms (like modelling a routing algorithm, an arbiter policy et al)\nThen scaled to larger subsystem/soc level performance modelling platforms (like full soc network modelling)\n\nThe performance evaluation setups must feed into architectural decisions driving scalable and performant design components.\n\nKey Responsibilities:\n\n- Author architecture specifications for Unified Intel Chassis IP components and subsystem integration.\n- Ensure architecture is implementation-aware, scalable, and power-optimized.\n- Drive platform performance analysis and closure, including bottleneck identification and optimization.\n- Build and enhance platform performance environments, models, and benchmarking flows.\n- Define and validate end-to-end QoS, arbitration, and routing strategies for high-bandwidth traffic.\n- Partner with system architects, RTL/design, verification, firmware/software, and performance teams to align architecture with product goals.\n- Define architecture trade-offs, assumptions, interfaces, and measurable success criteria.\n\nUIC IP Scope:\n\n- UIC Coherent and Non-Coherent Fabric\n- Protocol Adaptors for industry-standard protocols (AXI, CHI, CXL, UAL, etc.)\n- Cache Controller IP\n- MMU / IOMMU IP\n- Clock, Reset, and Power Management IP\n- Debug and Analytics IP\n- Security and Access Management IP\n\nQualifications:\nRequired Qualifications:\n\n- MS degree in a specialized field such as Computer Science, Electrical Engineering, or related discipline along with 4 or more years of relevant technical experience.\n- Strong experience in SoC IP architecture for complex interconnect and subsystem design.\n- familiarity with AMBA protocols, especially AXI, CHI, and APB.\n- Experience arbitration and routing algorithms, end-to-end QoS, and high-bandwidth low latency, scalable designs.\n- Hands-on experience with building platform environments which can be scaled to model small IP components to complete network model\n- Ability to define architecture requirements, interface contracts, performance targets, and power/performance/area trade-offs.\n- familiarly with AI tools to develop machine readable specification documents for spec2silicon fast and reliable execution\n- Strong collaboration and communication skills across architecture and implementation teams.\n\nPreferred Qualifications:\n\n- Experience with fabric-based scalable platforms across multiple markets or generations.\n- Strong exposure to performance modelling, SystemC/TLM/UVM, simulation, and data-driven architecture tuning.\n- Prior experience writing high-quality architecture specifications used by design and verification teams.\n- Familiarity with security architecture and access control frameworks in SoC platforms.\n- understanding of cache architecture and memory management/address translation MMU, IOMMU.\n\nSuccess Profile:\n\n- Translates system goals into practical, scalable, implementation-ready architecture.\n- Balances performance, power, area, and schedule constraints effectively.\n- Brings strong technical depth while driving alignment across teams.\n- Delivers architecture that enables first-time-right integration and faster performance closure.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Design Engineer - Modeling", "company": "Lattice", "location": "Manila, Philippines", "date_posted": "2026-09-08", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Manila-Philippines/Design-Engineer---Modeling_R-103109", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nSummary:\nThe Senior Design Engineer – Modeling position develops, validates, and delivers IP behavioral models and related hardware collateral used by internal engineering teams and software-facing customers. The role translates IP specifications and hardware design intent into accurate, efficient, and maintainable models, while ensuring consistency with custom, analog, or digital implementations.\n\nThe engineer also drives validation, automation, and methodology improvements that strengthen model quality, scalability, and delivery efficiency across multiple projects. The position requires close collaboration with IP Design, Design Verification, Integration, Software, Architecture, and Applications teams.\n\nKey Responsibilities\nDevelop and maintain IP functional and behavioral models using Verilog, SystemVerilog, and, where applicable, SystemC and C++.\nTranslate IP specifications, schematics, RTL, and design intent into clear model requirements, implementation plans, and verification objectives.\nPerform functional testing, audits, lint and CDC checks, regression testing, and consistency or equivalency checks against approved hardware references and specifications.\nLead or support the generation, audit, validation, and release of timing, power, signal-integrity, configuration, and metadata deliverables used for hardware and software integration.\nInvestigate and resolve model behavior, hardware-to-software integration, and customer-facing issues across the IP development lifecycle.\nDevelop scripts and reusable workflows that improve model generation, validation, audit, release, traceability, and reporting.\nPartner with IP Design, Design Verification, Integration, Software, Architecture, and Applications teams to align requirements, ownership, quality expectations, and delivery schedules.\nLead technical reviews, provide sound engineering direction, mentor less-experienced engineers, and promote consistent modeling and verification practices.\nIdentify quality or process gaps and drive practical improvements that reduce manual effort, improve scalability, and shorten turnaround time.\n\n \nRequired Qualifications\nBachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.\nDemonstrated senior-level experience in digital, custom, analog, FPGA, ASIC, or IP modeling and verification environments.\nStrong understanding of digital design fundamentals, RTL concepts, simulation, and the overall design and verification flow.\nProficiency in Verilog and/or SystemVerilog for functional or behavioral modeling and simulation.\nWorking knowledge of semiconductor and integrated-circuit principles, including the effects of device behavior, layout, timing, power, and signal integrity on system behavior.\nExperience with digital simulation tools and familiarity with SPICE-type simulation, device models, or transistor-level design concepts.\nExperience with scripting or programming languages such as Python, Perl, TCL, or Shell for engineering automation.\nAbility to develop verification plans, define measurable completion criteria, analyze results, and drive technical issues to closure.\nStrong collaboration and teamwork skills, with openness to working across multi-site and cross-functional teams\nGood written and verbal communication skills, with the ability to ask clear questions, explain technical ideas, and learn from feedback\nundefined\n\nPreferred Qualifications\nExperience developing models that represent custom digital or analog IP behavior.\nExperience with timing, power, IBIS, signal-integrity, configuration, XML, or other metadata-based IP deliverables.\nExperience with model equivalency, regression automation, lint, CDC, or structured design-quality audits.\nFamiliarity with FPGA development platforms and integrated hardware-software enablement flows.\nExperience improving engineering processes, creating reusable methods, or deploying automation across multiple projects.\nExperience mentoring engineers or providing technical leadership within a project team.\n \n \nGenAI-Enabled Engineering Mindset\nUses approved GenAI tools responsibly to support learning, code review, debugging, documentation, automation, and technical summarization.\nProactively considers where GenAI can reduce repetitive work or improve quality, while independently verifying outputs and applying sound engineering judgment.\nProtects confidential and proprietary information and follows applicable company policies when using AI-assisted tools.\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nPhilippinesLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "EDA Tools Hardware Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-08", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/EDA-Tools-Hardware-Engineer_JR0286756", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nDesigns, implements, verifies, and supports the enablement and adoption of hardware design tools, flows, and methodologies. Defines methodologies for hardware development related to technology node and EDA tool enabling. Creates and verifies unique hardware designs, assembles design platforms, and integrates components into hierarchical systems to provide deployment coverage for endtoend EDA tool testing on new technology nodes. Develops, tests, and analyzes engineering design automation tools, flow, and methodologies to improve efficiency and optimize power and performance. Supports development and enhancement of platforms, databases, scripts, and tools flows for design automation. Builds deep understanding of digital design, verification, structural and physical layout, fullchip integration, power and performance, clocking, and/or timing to enhance future TFM development. Collaborates with EDA vendors on defining and early testing of nextgeneration design tools.\n\nQualifications:\n•\tBachelor's / Master's degree in Electronics Engineering, Computer Science, or a related field.\n•\t3-10 years of experience in CAD software development, VLSI, or Design Enablement.\n•\tProficiency in SKILL, Python, and TCL/PERL programming.\n•\tKnowledge of VLSI concepts and EDA tools (Cadence/Synopsys).\n•\tKnowledge of Custom layout\n•\tKnowledge of Data Structures, Algorithms, and software optimization.\n•\tStrong problem-solving, teamwork, and communication skills.\n•\tFamiliarity with software development practices including version control, testing, and quality assurance\n\nPreferred Qualifications:\n•\tExposure to C/C++ or other object oriented programming languages.\n•\tKnowledge P-cell development and Testchip integration.\n•\tExposure to implementation of AI based applications in EDA tools.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Layout Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-08", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25017797", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\nLayout Engineers develop and prepare multi-dimensional layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by designers. Their work may be completed through use of CAD or other computerized equipment. Layour engineers will checks dimensions, write specifications, and verify the completed drawings, artwork or digitized plots. A bachelor's degree in engineering is typically required.\n\nHiring manager, please answer a few of the following prompts to give applicants a good idea of the role and delete the rest. \n\n A typical day-to-day in this role is… \n\n The team is a great team because… \n\n In this role, you will work most closely with…\n\n Some of the people you'll get to work with include…\n\n The most challenging aspect of this role is…\n\n The best thing about this role is…\n\n An example of a project you would work on in this role is…\n\n During the first 30 days of this role, you will…\n\n Something interesting about this role that wasn't in the job description is…\n\n The key to succeeding in this role is…\n\n The steepest learning curve in this role is…\n\n Our vision for the team is… \n\n Key responsibilities of this role include…\n\n \n\n \n\n \n\n \n\nYou would be great for this role if you've previously… (list experiences or roles here)", "jd_status": "source_unavailable"}, {"title": "Senior Staff Engineer, Physical Verification", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-07T12:59:41.820000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000147933579-senior-staff-engineer-physical-verification", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking an experienced Physical Verification (PV) Engineer to drive signoff verification and tapeout readiness for advanced ASIC/SoC designs. The candidate will be responsible for executing and debugging physical verification checks, driving violation closure, maintaining foundry-qualified verification flows, and ensuring block and full-chip layouts meet manufacturing requirements before tapeout.\nKey Responsibilities\nPerform and drive signoff Physical Verification for block- and chip-level designs.\nExecute and analyze DRC, LVS, ERC, Antenna, and Density checks using industry-standard signoff tools.\nDebug verification violations and provide actionable recommendations to Physical Design and Layout teams.\nDrive closure of signoff issues through effective tracking, prioritization, and cross-functional collaboration.\nMaintain and support foundry-qualified rule decks, runsets, and waiver management processes.\nManage waiver tracking and ensure compliance with foundry guidelines and project signoff requirements.\nCoordinate verification re-runs following design changes and ECOs to identify regressions and maintain signoff quality.\nWork closely with Physical Design, Layout, Foundry/PDK, and Program teams to achieve tapeout milestones.\nGenerate periodic signoff status reports, metrics, and violation summaries for project reviews.\nPrepare final signoff evidence including DRC/LVS-clean reports, waiver summaries, and residual risk assessments for tapeout reviews.\n\nBachelor's or Master's degree in Electronics Engineering or Electrical Engineering.\n10-15 years of experience in Physical Verification, Physical Design, or Backend Implementation.\nStrong expertise in DRC, LVS, ERC, Antenna, and Density verification methodologies.\nHands-on experience with Calibre, Pegasus, or equivalent physical verification tools.\nGood understanding of foundry signoff requirements, PDKs, and semiconductor manufacturing rules.\nExperience in debugging and resolving complex signoff violations at block and full-chip levels.\nFamiliarity with GDSII/OASIS databases, netlists, and tapeout processes.\nProficiency in Tcl, Python, Perl, or Shell scripting.\nPreferred Qualifications\nExperience with advanced technology nodes (7nm, 5nm, 3nm, and below).\nKnowledge of Physical Design, PDN, STA, and implementation flows.\nExperience supporting multiple successful SoC tapeouts.\nStrong problem-solving, communication, and stakeholder management skills.\nWhy Join Us?\nJoin a high-impact team responsible for ensuring silicon manufacturability and signoff quality for next-generation SoCs. You will work closely with design, implementation, and foundry teams to drive successful tapeouts on cutting-edge process technologies.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Staff Engineer, Low Power & Formal Equivalence Verification (VCLP / FEV)", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-07T12:51:39.963000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000147931269-senior-staff-engineer-low-power-formal-equivalence-verification-vclp-fev-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking a highly motivated and experienced engineer to lead Low Power (Power Intent) and Formal Equivalence Verification (FEV/LEC) activities for complex ASIC/SoC programs. The ideal candidate will be responsible for defining and signing off power intent (UPF/CPF), ensuring correct low-power implementation across all design stages, and driving formal equivalence verification from RTL through synthesis, DFT, implementation, and ECOs to tapeout.\nThis role requires close collaboration with Architecture, RTL, Verification, Synthesis, DFT, STA, Physical Design, PDN, and Signoff teams to ensure functional correctness, low-power integrity, and successful tapeout execution.\nKey Responsibilities\nLow Power / Power Intent\nDefine, develop, and maintain low-power architecture and power intent using UPF/CPF.\nOwn power-domain and power-state specifications across IP, subsystem, and chip-level designs.\nDrive implementation and integration of isolation, retention, level shifters, and power-switch methodologies.\nDebug and resolve power-intent issues across RTL, synthesis, implementation, and ECO stages.\nCollaborate with cross-functional teams to ensure power-aware constraints, methodologies, and signoff checks.\nDrive low-power issue closure and tapeout readiness.\nFormal Equivalence Verification\nExecute formal equivalence checks at key design milestones:RTL ↔ Synthesis\nSynthesis ↔ DFT\nDFT ↔ Physical Design\nPre-ECO ↔ Post-ECO\n\nAnalyze and debug equivalence failures related to constraints, mapping, low-power insertion, DFT logic, and ECO changes.\nDrive issue resolution with clear ownership and closure tracking.\nValidate RTL, netlists, library models, constraints, and ECO patches for functional equivalence.\nGenerate signoff-quality reports and support milestone/tapeout reviews.\nMethodology & Automation\nDevelop automation and reusable methodologies to improve verification efficiency and quality.\nCreate scripts and checks for low-power validation, equivalence verification, and issue tracking.\nDrive continuous improvements in low-power and formal verification flows.\n\nBachelor's or Master's degree in Electronics Engineering or Electrical Engineering.\n10-15 years of experience in ASIC/SoC implementation, low-power design, or formal verification.\nStrong expertise in UPF/CPF-based low-power methodologies.\nDeep understanding of power domains, power states, isolation, retention, level shifters, and power gating.\nHands-on experience with Formal Equivalence Verification (FEV/LEC) tools and methodologies.\nStrong understanding of synthesis, DFT, STA, ECO, and implementation flows.\nProficiency in Tcl, Python, Perl, or Shell scripting.\nExcellent debugging, analytical, and problem-solving skills.\nPreferred Qualifications\nExperience with advanced-node technologies (7nm and below).\nKnowledge of Physical Design, PDN, STA, and signoff methodologies.\nExperience supporting full-chip SoC tapeouts.\nStrong collaboration skills and experience working across global design teams.\nWhy Join Us?\nJoin a high-performance engineering team developing next-generation semiconductor products. You will play a critical role in ensuring low-power integrity and functional correctness across the complete RTL-to-GDSII flow, directly contributing to successful tapeouts on advanced technology nodes.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Staff/Senior Staff Engineer, Synthesis & Timing Constraints", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-07T12:45:24.325000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000147929059-staff-senior-staff-engineer-synthesis-timing-constraints", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are looking for an experienced Synthesis and Timing Constraints Engineer to join our ASIC/SoC Implementation team. In this role, you will lead timing constraint development and synthesis methodologies for complex SoC designs, working closely with Architecture, RTL Design, Physical Design, and STA teams to deliver high-quality implementations across advanced technology nodes.\nKey Responsibilities\nDefine, develop, and maintain timing constraints (SDC) at IP, subsystem, and chip levels.\nDrive RTL synthesis and optimization using Synopsys Design Compiler and Fusion Compiler.\nAnalyze and resolve timing, area, power, and implementation challenges to achieve design targets.\nCollaborate with cross-functional teams to ensure robust design convergence throughout the implementation cycle.\nDevelop and enhance methodologies, flows, and automation to improve productivity and design quality.\nSupport timing closure activities and drive best practices for synthesis and constraint management.\nDebug and resolve synthesis and timing-related issues during project execution.\nContribute to flow improvements for advanced-node ASIC/SoC development.\n\nBachelor's or Master's degree in Electronics Engineering or Electrical Engineering.\n10-15 years of experience in ASIC/SoC implementation.\nExpert knowledge of Synopsys Design Compiler and Fusion Compiler.\nStrong understanding of Static Timing Analysis (STA), timing closure, and SDC methodology.\nHands-on scripting experience in Tcl and/or Python.\nExperience with advanced-node implementation flows.\nStrong analytical, problem-solving, and debugging skills.\nAbility to work effectively with global cross-functional teams.\nPreferred Qualifications\nExperience with low-power design methodologies and optimization techniques.\nKnowledge of Physical Design and signoff flows.\nFamiliarity with hierarchical and full-chip implementation methodologies.\nSuccessful experience supporting complex SoC tapeouts.\nWhy Join Us?\nBe part of a high-performing implementation team working on next-generation semiconductor products. You'll have the opportunity to influence methodology, drive technical innovation, and contribute directly to successful tapeouts on cutting-edge process technologies.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Staff Engineer, CAD & Methodology", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-07T12:34:42.492000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000147923604-senior-staff-engineer-cad-methodology", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking a highly motivated CAD & Methodology Engineer to drive the development, deployment, and support of scalable design automation infrastructure for Backend Physical Design teams. The role focuses on enabling efficient, repeatable, and high-quality RTL-to-GDSII implementation and signoff by maintaining robust reference flows, developing automation solutions, and driving methodology standardization across projects.\nThe ideal candidate will work closely with Physical Design, Timing, Signoff, EDA vendors, IT infrastructure teams, and Foundry partners to ensure seamless tool deployment, optimized design methodologies, and predictable project execution through tapeout.\nKey Responsibilities\nDevelop, maintain, and release reference flows for Synthesis, STA, Place & Route, and Signoff.\nBuild automation to improve productivity, including setup generation, QoR checks, report parsing, ECO automation, and deliverable packaging.\nDefine and enforce methodology standards, flow validation, and QoR compliance checks.\nQualify and deploy EDA tools, PDKs, libraries, and signoff runsets across compute environments.\nProvide technical support and root-cause analysis for flow, tool, and infrastructure issues through tapeout.\nCollaborate with Physical Design teams, IT, EDA vendors, and Foundry partners to drive flow improvements and issue resolution.\n\n10+ years of experience in Physical Design CAD, Design Methodology, or Backend Design Automation.\nBachelor's or Master's degree in Electronics, Electrical Engineering.\nStrong understanding of RTL-to-GDSII implementation and signoff methodologies.\nHands-on experience with industry-standard EDA tools from Synopsys, Cadence, and/or Siemens.\nProficiency in Tcl, Python, Shell, or Perl scripting.\nExperience developing CAD automation and methodology solutions for backend design teams.\nPreferred Skills\nExperience with advanced technology nodes (7nm and below).\nKnowledge of PDK, library, and runset enablement.\nFamiliarity with compute farms, Linux environments, Git, and CI/CD frameworks.\nStrong problem-solving and cross-functional collaboration skills.\nJoin us to drive design automation, methodology innovation, and successful tapeouts across cutting-edge semiconductor products.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Principal Engineer/Manager - Design Verification", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-07T10:12:21.592000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000147897569-principal-engineer-manager-design-verification", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking an experienced and highly motivated Principal Engineer/Manager, Design Verification to lead a team responsible for functional verification of complex digital IPs, subsystems, and SoC solutions. The ideal candidate will have deep expertise in verification methodologies, strong people leadership skills, and a proven track record of delivering high-quality silicon products on schedule. \nThis role requires close collaboration with architecture, design, firmware, emulation, validation, and program management teams to drive verification excellence and achieve first-silicon success. \n \nKey Responsibilities \nOwn verification strategy, planning, execution, and sign-off for complex SoCs and SoC Subsystems. \nDefine comprehensive verification plans aligned with architectural specifications and product requirements. \nDrive adoption of industry-standard verification methodologies such as UVM, SystemVerilog, Assertions, Coverage-Driven Verification, Formal Verification, and Emulation. \nEstablish verification metrics, coverage goals, and quality benchmarks to ensure robust product delivery. \nReview verification architectures, testbench frameworks, reusable components, and coverage models. \nLead root cause analysis and resolution of critical functional issues. \nTeam Leadership \nBuild, mentor, and retain a high-performing verification team. \nManage team goals, performance reviews, career development, and succession planning. \nFoster a culture of technical excellence, accountability, collaboration, and innovation. \nDrive recruitment and onboarding of verification engineers across experience levels.  \nPartner with Design, Architecture, Validation, DFT, Firmware, and Program Management teams throughout the product lifecycle. \nTrack project schedules, risks, dependencies, and resource planning. \nProvide regular status updates to senior leadership on project execution and quality metrics. \nEnsure timely achievement of verification milestones and tape-out readiness. \nProcess & Quality Improvement \nDefine and implement best practices for verification productivity and reuse. \nDrive automation initiatives to improve efficiency and reduce turnaround time. \nImprove regression methodologies, debug workflows, and coverage closure processes. \nPromote continuous improvement through post-silicon feedback and lessons learned. \n\nBachelor's or master's degree in Electronics Engineering, Electrical Engineering. \n15+ years of experience in Design Verification with at least 3-5 years in technical leadership or people management roles. \nStrong expertise in:  \nSystem Verilog \nUVM methodology \nFunctional coverage and assertions \nVerification planning and execution \nSimulation, emulation, and formal verification techniques \nExperience verifying complex digital designs, IPs, subsystems, or SoCs. \nStrong debugging skills and understanding of microarchitecture. \nExperience with scripting languages such as Python, Perl, Tcl, or Shell. \nProven experience driving projects from specification through silicon validation. \nPreferred Qualifications \nExperience in Automotive SoCs and MCUs.\nFamiliarity with safety standards such as ISO26262.\nKnowledge of mixed-signal verification methodologies. \nExperience with FPGA prototyping and emulation platforms. \nExperience managing geographically distributed teams. \nStrong stakeholder management and communication skills. \nKey Competencies \nProven technical expertise in Verification  \nPeople Leadership \nStrategic Thinking \nTracking of deliverables and guiding junior members of the team \nProblem Solving \nCross-Functional Collaboration \nDecision Making \nTalent Development \nContinuous Improvement \nSuccess Measures \nAchievement of verification coverage and quality targets. \nOn-time project execution and tape-out readiness. \nReduction in escaped bugs and post-silicon issues. \nTeam engagement, capability development, and retention. \nIncreased verification reuse, automation, and productivity. \nThis role offers an opportunity to lead cutting-edge verification programs and influence the delivery of next-generation semiconductor solutions while building and developing a world-class verification organization. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Staff/Senior Staff/ Principal Engineer, Design Verification", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-07T09:31:59.714000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000147886769-staff-senior-staff-principal-engineer-design-verification", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Be a part of end‑to‑end verification execution for SOC owning complex digital IP’s and subsystems from specification to sign‑off\nDefine and drive IP‑level verification strategies, including test plans, coverage models, and closure criteria\nDevelop scalable, reusable UVM‑based verification environments for IP and subsystem verification\nLead functional, code, assertion, and cross‑coverage closure, ensuring high‑quality sign‑off with clear metrics\nApply AI/ML‑assisted verification techniques to accelerate coverage convergence, identify stimulus gaps, and optimize regression efficiency\nDrive constraint random and directed test methodologies for thorough protocol, corner‑case, and stress verification\nCollaborate with RTL, Architecture, Emulation, and SoC Verification teams to ensure seamless IP integration\nReview IP specifications and work with architects to translate requirements into robust verification plans and checkers\nDevelop and deploy advanced checkers, scoreboards, assertions (SVA), and protocol monitors\nWork with EDA vendors to evaluate and adopt next‑generation verification, coverage, and analytics tools\nMentor junior engineers and promote best‑in‑class verification practices and continuous improvement\nSupport Gate‑Level Simulation (GLS), low‑power verification, and post‑silicon debug when required.\nEnsure IP deliverables meet quality, schedule, and reusability expectations for SoC integration.\n\nBachelor’s or master’s degree in Electronics Engineering\n5-15 years of experience in SoC Verification domains and have working knowledge of industry standard EDA toolkits.  \nStrong expertise in UVM‑based testbench architecture and development\nProven experience in metric‑driven verification, including functional and code coverage closure\nDeep understanding of SystemVerilog, UVM, assertions (SVA), and verification best practices\nExperience with directed and constrained‑random verification methodologies\nExperience debugging complex design issues in simulation, emulation, and post‑silicon environments\nProficiency in Verilog/SystemVerilog, with working knowledge of C/C++, Shell scripting\nStrong analytical, problem‑solving, and communication skills\nPreferred/Plus Qualifications\nHands‑on experience using AI/ML‑based verification tools for:Coverage gap analysis\nTest stimulus optimization\nRegression triage and coverage acceleration\n\nScripting expertise in Python, Perl, or TCL for automation and analytics\nExposure to formal verification and hybrid formal‑simulation flows\nFamiliarity with high‑speed or complex IPs, such as:H.264\nSecurity, debug, or safety‑crititical\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Wireless Datapath Validation Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-07T06:26:00+00:00", "url": "https://global-external-amd.icims.com/jobs/91654/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.   THE ROLE: AMD is seeking an experienced Wireless Datapath Validation Engineer to drive validation of next-generation wireless infrastructure and networking solutions. In this role, you will be responsible for validating high-performance datapath functionality, protocol compliance, performance, and reliability across silicon and system platforms. You will work closely with architecture, design, firmware, and software teams to ensure robust product quality and customer readiness.      THE PERSON:  You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.   KEY RESPONSIBILITIES:  Develop and execute validation plans for wireless datapath and networking features. Validate packet processing, traffic management, QoS, buffer management, and congestion handling. Validate O-RAN, eCPRI, Ethernet, and timing-related features. Drive post-silicon bring-up, debug, and root-cause analysis across hardware, firmware, and software layers. Execute performance, stress, scalability, and reliability testing. Develop automation frameworks, regression suites, and validation infrastructure. Collaborate with cross-functional teams to drive issues to resolution and improve product quality. Work closely with the customer on regular basis to enable them with our products   PREFERRED EXPERIENCE:  8+ years experience in validation, networking, wireless communications, or embedded systems. Strong understanding of wireless systems, 4G/5G architectures, and O-RAN ecosystems. Experience with Ethernet, eCPRI, QoS, PTP/IEEE 1588, TCP/IP, and networking protocols. Hands-on experience with silicon bring-up, protocol debugging, and system-level validation. Proficiency in Python, Linux, and test automation development. Experience with traffic generators, protocol analyzers, Wireshark, and performance benchmarking tools. Exposure to FPGA, emulation, or post-silicon validation environments is a plus.   ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-NS2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Engineer - AMS IP Verification", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-07T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/41229748", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nProvide verification support to design projects by simulating, analyzing, and debugging pre-silicon IP designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products.\n \nGood understanding of analog / mixed signal circuits.\nExperience in Analog and Mixed signal Verification , understand the usage of tools like Virtuoso, primesim/ Finseim, Hspice, Xcellium, Simvision, Waveview.\nHands on experience in writing Verilog Models. Verilog A/MS, RVM model writing experience is encouraged.\nHands on experience in building SPICE testbenches at Block, Fullchip Level. Hands-on experience in building the COSIM/ Mixed signal verification environment is encouraged.\nHands on experience in SV, UVM based Verification Hands on experience in SV/PSL assertions. Good scripting skills using perl, python are highly encouraged.\nPrevious work experience in DRAM memory related fields is beneficial.\nMust possess good communication, debugging skills and ability to work well in a team.\nStrong experience working with AI tools and technologies, with the ability to leverage AI solutions to improve productivity, automation, and business outcomes.\n\nHands-on experience with AI tools, AI-driven workflows, and practical application of Artificial Intelligence technologies in real-world projects\n\nShould be proactive in exploring and bringing to bear AI-related tools in day-to-day tasks.\n \n \nCandidate must have 2+ years of experience in AMS/Mixed Signal design verification with Bachelors or Post Graduate Degree in Electronics Engineering or related engineering field required.\nWe recruit, hire, train, promote, team, and provide other conditions of employment without regard to a person's race, color, religion, sex, age, national origin, disability, sexual orientation, gender identity and expression, pregnancy, veteran’s status, or other classifications protected under law. This includes providing reasonable accommodation for team members' disabilities or religious beliefs and practices.\n \n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Hardware Validation and Voltage Characterization - Senior Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-07T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719465227", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Systems Engineering\nGeneral Summary:\nLooking for self-motivated persons to Lead voltage-plan development, silicon characterization, Vmin analysis, and power optimization activities for Data Center SoCs.\nWork closely with PTE, SW, PMIC, Thermal, and Validation teams to define, characterize, validate, and release production-ready voltage plans across silicon milestones\nAnalyze large silicon characterization datasets. Develop automation tools using Python, SQL, Excel, Power BI, or similar platforms.\nBuild dashboards for Vmin trends, voltage correlations, and silicon-health monitoring.\nRequired Skills\nSoC Power Architecture, Vmin Characterization, PMIC and Regulator Architecture, Silicon Bring-up and Validation, Statistical Data Analysis,\nLinux/Android Debugging, Data Center CPU/AI accelerator platforms , Power integrity, and PDN analysis,\nGood understanding of Schematics and CRO usage for debug, Semiconductor Technology, PVT Processes.\n\nExperience\nB.E./M.E./M.Tech in ECE, EE, Computer Engineering or related field.\n5–6 years in:\nSoC Power Characterization, Data center experience\nSilicon Validation, Voltage Plan Development, Power Optimization\n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.\n                                                                    OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience.\n                                                                    OR\nPhD in Engineering, Information Systems, Computer Science, or related field.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Physical Design Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-07T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719605327", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nExperience:\nProven experience in managing complex subsystems and small teams.\nProficiency in complete Netlist2GDS: Floorplan, place and route (PnR), and sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations.\nHand on experience in lower technology nodes.\nJob Requirements:\nExpertise in meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), place and route, and IP integration.\nExperience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating.\nFamiliarity with ASIC design flows and physical design methodologies.\nStrong understanding of circuit design, device physics, and deep sub-micron technology.\nExperience working on multiple technology nodes in advanced processes.\nProficiency in automation to drive improvements in PPA.\nManaging and driving a small team for project execution and PPA targets\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Principal Engineer- CPU Circuit Design", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-07", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Principal-Engineer--CPU-Circuit-Design_JR0286915", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nAs CPU Circuit Design Lead, you will lead the development of advanced digital circuits for custom blocks such as SRAM, register files, memory compilers, Custom Data path, and caches. You will be instrumental in designing floorplans, optimizing circuits for power, performance, area, timing, and yield goals, and ensuring functionality through rigorous simulation and verification processes. You will also help in build and lead a circuit design team to oversee design creation, testing, and performance analysis, ensuring that projects meet technical specifications and timelines.\n\nBusiness group\nThe Silicon and Platform Engineering Group (SPE) is at the core of Intel's innovation, focusing on designing and building cutting-edge silicon and platform technologies that power Intel's products. With a commitment to excellence, the group drives advancements in circuit design, architecture, and performance optimization to enable transformative computing solutions. Joining SPE means contributing to Intel's broader mission to deliver world-class technologies that shape the future of computing.\n\nKey Responsibilities\n- Design digital circuits for custom blocks, including SRAM, register files, memory compilers, Custom Data path, and caches.\n- Develop floorplans and optimize circuits for power, performance, area, timing, and yield goals.\n- Perform circuit design, schematic entry, simulation, and verification to ensure functionality and reliability.\n- Manage, guide, and support the activities and performance of circuit design engineers in team across memory, and/or custom digital domains.\n- Provide strategic direction on design drawings, test plans, electrical and timing analysis, and component evaluation.\n- Improve and automate design flows and methodologies for streamlined execution.\n- Collaborate with RTL designers, physical designers, and verification engineers to address design inefficiencies and resolve pre- and post-silicon performance issues.\n- Collaborate with architecture and layout teams to optimize circuits for functionality, robustness, and electrical capabilities.\n- Develop and mentor other technical leaders and foster innovation within and across teams.\n- Align organizational goals with technical vision and formulate strategies to deliver leadership solutions.\n\nQualifications:\nMinimum Qualifications\n- Bachelor's OR Master degree in electrical engineering or electronics engineering, or a related field with 17+ years of experience in circuit design\n- Proficiency in circuit design, simulation tools, and methodologies.\n- Expertise in optimizing circuits for performance, power, area, timing, and yield goals.\n- Strong understanding of memory blocks, transistor level design and test tools.\n\nPreferred Qualifications\n- Demonstrated ability to lead and mentor technical teams and foster collaboration.\n- Proven track record in driving technical strategy and delivering leadership solutions across an organization.\n- Strong communication, organization, and problem-solving skills.\n\nApply now to take on this impactful role and contribute to Intel's legacy of innovation, excellence, and leadership in the semiconductor industry.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Design Engineer II", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-09-07", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Design-Engineer-II_R55764", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Opportunity: Foundry PDK Design Enablement Engineer\nExperience Level: 2–4 Years\nDepartment: Methodology & Flow Enablement Group\nEducation: Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, Microelectronics, Semiconductor Technology, or a related field\nPosition Overview\nWe are seeking a highly motivated Foundry Process Technology, PDK & DTCO Engineer with 2–4 years of experience to join our process technology group. In this role, you will bridge the gap between process technology and design, driving next-generation semiconductor technology through cutting-edge path-finding methodologies. The ideal candidate possesses a strong foundation in PDK enablement, physical verification decks, process/design interaction electrical studies, Spice model understanding and design automation.\nKey Responsibilities\nPDK Enablement: Validate, deploy, and maintain foundational PDK components specifically tailored for advanced technology nodes.\nTechnology Study Activities: Conduct rigorous standard cell, SRAM, and custom circuit benchmarking alongside interconnect optimization to maximize power, performance, and area (PPA).\nAutomation & Methodology: Design, develop, and maintain robust scripts and automated execution flows for PDK enablement/validation and PDK analysis.\nCollaborative Path-Finding: Partner closely with internal DTCO groups to turn advanced device architectures into reality.\nRequired Qualifications & Technical Skills\nIndustry Experience: 2–4 years of hands-on experience in semiconductor technology analysis, foundry PDK enablement, and the co-optimization of PDK components like LVS, DRC, Parasitic Extraction, spice models. Strong understanding of PDK design enablement flows. Exposure to multiple foundry & nodes is a plus.\nDevice Physics: Strong fundamental understanding of CMOS device physics, including advanced architectures like GAA (Gate-All-Around), FinFETs, and planar MOSFETs.\nPhysical Verification & EDA: Deep knowledge of Layout Versus Schematic (LVS), Design Rule Checking (DRC), Parasitic Extractions, and Spice models at transistor level. Cadence based tool knowledge is a plus.\nTooling Familiarity: Direct experience or high proficiency with Cadence-based tool suites is highly advantageous.\nTeam Collaboration: Proven experience interfacing with core PDK development teams, technology enablement units, or advanced technology benchmarking groups.\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-07", "url": "https://careers.synopsys.com/job/bengaluru/senior-staff-interface-ip-verification-engineer-pre-silicon-pcie-cxl-ddr-ethernet/44408/100305008240", "is_hardware": true, "platform": "talentbrew", "jd_text": "Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet)\n \nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years verifying silicon that ships into data centers, AI accelerators, and high-performance systems where failure is not an option. The protocols you verify, PCIe, CXL, DDR, Ethernet, are not abstract specs to you. They are living, breathing systems with corner cases that only reveal themselves at 3 a.m. during a regression run, and you are the engineer who finds them before tape-out.\nYou think in layers. You can debug a failing assertion in the UVM environment, trace it back to an RTL timing issue, and then connect it to a protocol compliance gap, all without losing the thread of what actually broke. When someone says 'coverage is at 95%,' you ask which 5% is missing and whether it matters.\nYou do not wait for perfect documentation. Specs are incomplete, architectures evolve, and you have learned to work with what you have, ask the right questions, and build verification environments that adapt as the design matures. You have strong opinions on what makes a testbench reusable versus one that becomes technical debt, and you are not afraid to push back when a verification strategy does not account for real-world integration scenarios.\nAt Synopsys, you will verify Interface IP that powers the semiconductor industry's most critical applications, and the team you work with will expect you to lead, not just execute.\nWhat You'll Be Doing\nOwn end-to-end verification of Interface IP blocks including PCIe, CXL, DDR, and Ethernet, from architecture review through silicon signoff\nBuild and evolve UVM-based verification environments that are reusable across product lines and scalable for future protocol generations\nDefine verification strategies and test plans that account for protocol compliance, performance corner cases, and system-level integration scenarios\nDevelop constrained-random, coverage-driven test scenarios using SystemVerilog and UVM, targeting functional coverage closure and signoff quality\nDebug complex multi-layer issues spanning RTL logic, protocol state machines, timing, and testbench infrastructure using VCS or equivalent simulators\nCollaborate with architecture, design, firmware, and systems teams to identify and resolve issues early in the development cycle\nMentor verification engineers on UVM methodology, coverage analysis, debugging techniques, and verification best practices\nThe Impact You Will Have\nYour verification work will directly determine the quality and reliability of IP integrated into AI platforms, cloud infrastructure, and automotive systems used globally\nThe testbenches and verification IP you build will be reused across multiple product generations, multiplying your impact across the organization\nYour coverage strategies and signoff criteria will set the standard for verification quality across the Interface IP portfolio\nThe protocol bugs you catch pre-silicon will prevent costly respins and delays for customers building next-generation SoCs\nYour technical leadership will shape verification methodology improvements that raise the bar for the entire engineering team\nThe mentorship you provide will accelerate the growth of engineers who will carry forward the verification practices you help establish\nYour collaboration with architecture and design teams will influence early design decisions that make verification more efficient and products more robust\nWhat You'll Need\nBachelor's or Master's in Electrical Engineering or Computer Engineering with 8+ years of hands-on ASIC or SoC verification experience\nDeep expertise in SystemVerilog and UVM methodology, with a track record of building scalable verification environments from the ground up\nStrong protocol knowledge in at least one of PCIe, CXL, DDR, or Ethernet, with the ability to read specs and translate them into verification requirements\nProven experience developing constrained-random and coverage-driven verification solutions that achieve functional signoff\nSolid debugging skills across RTL, verification infrastructure, and protocol compliance, with experience using industry-standard simulators like VCS or ModelSim\nExperience with verification IP development, assertion-based verification, or formal methods is a strong plus\nKnowledge of modern SoC architectures and high-speed communication interfaces is a plus\nWho You Are\nYou can walk into a spec review, identify the verification-critical corner cases that are not explicitly called out, and build a test plan that covers them\nWhen a regression fails at 2 a.m. before a milestone, you are the engineer who triages the root cause, determines if it is a real bug or a testbench issue, and has a fix ready by morning standup\nYou know the difference between coverage that looks good on a dashboard and coverage that actually means the design is verified, and you are willing to have the hard conversation when the two do not align\nYou can explain a complex protocol violation to a design engineer in a way that makes the fix obvious, and then turn around and present the same issue to an architect in terms of system-level impact\nYou are comfortable leading technical discussions with senior engineers and architects, even when your point of view challenges the current plan\nYou see mentorship as part of the job, not an extra task, and you make time to help less experienced engineers understand not just what to do, but why it matters\nThe Team You'll Be Part Of\nYou will join a team of highly skilled verification engineers responsible for developing and verifying industry-leading Interface IP solutions. Working alongside experts in architecture, design, and verification, you will tackle some of the semiconductor industry's most challenging technical problems while contributing to products deployed worldwide. The team operates globally, collaborates across time zones, and values technical depth, ownership, and the kind of problem-solving that makes complex IP actually work in customer silicon.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-07", "url": "https://careers.synopsys.com/job/bengaluru/senior-staff-interface-ip-verification-engineer-pre-silicon-pcie-cxl-ddr-ethernet/44408/100305008224", "is_hardware": true, "platform": "talentbrew", "jd_text": "Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet)\n \nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years verifying silicon that ships into data centers, AI accelerators, and high-performance systems where failure is not an option. The protocols you verify, PCIe, CXL, DDR, Ethernet, are not abstract specs to you. They are living, breathing systems with corner cases that only reveal themselves at 3 a.m. during a regression run, and you are the engineer who finds them before tape-out.\nYou think in layers. You can debug a failing assertion in the UVM environment, trace it back to an RTL timing issue, and then connect it to a protocol compliance gap, all without losing the thread of what actually broke. When someone says 'coverage is at 95%,' you ask which 5% is missing and whether it matters.\nYou do not wait for perfect documentation. Specs are incomplete, architectures evolve, and you have learned to work with what you have, ask the right questions, and build verification environments that adapt as the design matures. You have strong opinions on what makes a testbench reusable versus one that becomes technical debt, and you are not afraid to push back when a verification strategy does not account for real-world integration scenarios.\nAt Synopsys, you will verify Interface IP that powers the semiconductor industry's most critical applications, and the team you work with will expect you to lead, not just execute.\nWhat You'll Be Doing\nOwn end-to-end verification of Interface IP blocks including PCIe, CXL, DDR, and Ethernet, from architecture review through silicon signoff\nBuild and evolve UVM-based verification environments that are reusable across product lines and scalable for future protocol generations\nDefine verification strategies and test plans that account for protocol compliance, performance corner cases, and system-level integration scenarios\nDevelop constrained-random, coverage-driven test scenarios using SystemVerilog and UVM, targeting functional coverage closure and signoff quality\nDebug complex multi-layer issues spanning RTL logic, protocol state machines, timing, and testbench infrastructure using VCS or equivalent simulators\nCollaborate with architecture, design, firmware, and systems teams to identify and resolve issues early in the development cycle\nMentor verification engineers on UVM methodology, coverage analysis, debugging techniques, and verification best practices\nThe Impact You Will Have\nYour verification work will directly determine the quality and reliability of IP integrated into AI platforms, cloud infrastructure, and automotive systems used globally\nThe testbenches and verification IP you build will be reused across multiple product generations, multiplying your impact across the organization\nYour coverage strategies and signoff criteria will set the standard for verification quality across the Interface IP portfolio\nThe protocol bugs you catch pre-silicon will prevent costly respins and delays for customers building next-generation SoCs\nYour technical leadership will shape verification methodology improvements that raise the bar for the entire engineering team\nThe mentorship you provide will accelerate the growth of engineers who will carry forward the verification practices you help establish\nYour collaboration with architecture and design teams will influence early design decisions that make verification more efficient and products more robust\nWhat You'll Need\nBachelor's or Master's in Electrical Engineering or Computer Engineering with 8+ years of hands-on ASIC or SoC verification experience\nDeep expertise in SystemVerilog and UVM methodology, with a track record of building scalable verification environments from the ground up\nStrong protocol knowledge in at least one of PCIe, CXL, DDR, or Ethernet, with the ability to read specs and translate them into verification requirements\nProven experience developing constrained-random and coverage-driven verification solutions that achieve functional signoff\nSolid debugging skills across RTL, verification infrastructure, and protocol compliance, with experience using industry-standard simulators like VCS or ModelSim\nExperience with verification IP development, assertion-based verification, or formal methods is a strong plus\nKnowledge of modern SoC architectures and high-speed communication interfaces is a plus\nWho You Are\nYou can walk into a spec review, identify the verification-critical corner cases that are not explicitly called out, and build a test plan that covers them\nWhen a regression fails at 2 a.m. before a milestone, you are the engineer who triages the root cause, determines if it is a real bug or a testbench issue, and has a fix ready by morning standup\nYou know the difference between coverage that looks good on a dashboard and coverage that actually means the design is verified, and you are willing to have the hard conversation when the two do not align\nYou can explain a complex protocol violation to a design engineer in a way that makes the fix obvious, and then turn around and present the same issue to an architect in terms of system-level impact\nYou are comfortable leading technical discussions with senior engineers and architects, even when your point of view challenges the current plan\nYou see mentorship as part of the job, not an extra task, and you make time to help less experienced engineers understand not just what to do, but why it matters\nThe Team You'll Be Part Of\nYou will join a team of highly skilled verification engineers responsible for developing and verifying industry-leading Interface IP solutions. Working alongside experts in architecture, design, and verification, you will tackle some of the semiconductor industry's most challenging technical problems while contributing to products deployed worldwide. The team operates globally, collaborates across time zones, and values technical depth, ownership, and the kind of problem-solving that makes complex IP actually work in customer silicon.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "ASIC Digital Design, Sr Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-07", "url": "https://careers.synopsys.com/job/bengaluru/asic-digital-design-sr-staff-engineer/44408/100290788336", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years building RTL that tapes out clean, not almost clean, actually clean, and you know the difference between a subsystem that works in simulation and one that survives silicon. The dopamine rush you get from first-time-right RTL is real, and it is what keeps you coming back to the hardest parts of digital design. You have driven multiple tape-outs and learned that the architecture decisions you make in week two will either save or sink the team in month six. You think in hierarchies, timing paths, and power domains without losing sight of what the block is actually supposed to do. Working with verification teams does not slow you down, it sharpens your thinking, and you write RTL that makes their job possible, not harder. You are comfortable owning a subsystem from spec to release, navigating ambiguity, making tradeoffs, and driving cross-functional work without waiting for someone else to connect the dots. At Synopsys, you will work on complex IP and subsystems that power the semiconductor industry, and the RTL you write will matter.\nWhat You'll Be Doing\nOwn the full lifecycle of complex subsystem design from requirements and architecture through RTL development, verification collaboration, implementation handoff, and final release\nCraft subsystem architecture and functional specifications, define micro-architecture, and write production-quality RTL using industry best practices\nDrive RTL quality checks including lint, CDC, RDC, and work closely with verification teams to ensure functional correctness and coverage closure\nIntegrate and design around standard protocols including PCIe, DDR, UFS, USB, and AMBA-based interconnects\nImplement low power design techniques across clock gating, power gating, and multi-voltage domains, ensuring power intent is captured and verified\nCollaborate with logic synthesis, STA, and physical design teams to ensure timing closure, develop synthesis constraints, and resolve equivalence check issues\nWork with DFT teams to architect scan, MBIST, and other testability features into your subsystems from the start\nThe Impact You Will Have\nYour RTL will tape out in production silicon used by leading semiconductor companies building next-generation AI, automotive, and mobile SoCs\nThe subsystems you architect will enable faster time-to-market for Synopsys IP customers who depend on proven, reusable, and robust design blocks\nYour attention to RTL quality and first-time-right design will reduce verification cycles, implementation iterations, and post-silicon debug time across the product\nThe protocols and low power techniques you implement will directly influence power, performance, and area outcomes in customer chips\nYour collaboration with cross-functional teams will set the standard for how design, verification, and implementation work together on complex projects\nThe design practices and methodologies you bring will influence how the team approaches architecture, coding standards, and release quality\nYour ability to drive projects to completion will unlock new IP releases and product milestones that depend on subsystem readiness\nWhat You'll Need\nBachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or equivalent technical field\n8+ years of hands-on RTL design experience with multiple tape-outs under your belt, ideally in complex IP, subsystems, or SoC blocks\nDeep proficiency with Verilog or SystemVerilog and proven ability to write synthesizable, timing-clean, low power RTL at scale\nStrong working knowledge of standard protocols such as PCIe, DDR, UFS, USB, or AMBA (AXI, AHB, APB)\nHands-on experience with low power design techniques including clock gating, power gating, retention, UPF, and multi-voltage domain architecture\nSolid understanding of logic synthesis, constraint development (SDC), static timing analysis (STA), and equivalence checking flows\nFamiliarity with DFT concepts including scan insertion, ATPG, MBIST, and how testability requirements shape design architecture, experience working directly with DFT teams is a plus\nWho You Are\nYou can take a high-level requirement document and turn it into a clean subsystem architecture without needing every detail spelled out for you\nYou write RTL that passes lint, CDC, and synthesis checks on the first pass because you think about those constraints while you code, not after\nYou can sit in a room with verification engineers, implementation leads, and DFT architects and walk out with a plan that actually works for everyone\nYou push back when a specification is ambiguous or a timeline does not account for real design complexity, and you do it in a way that moves the conversation forward\nYou are organized enough to manage multiple release phases, cross-functional dependencies, and shifting priorities without dropping threads\nYou care about the quality of what you release, not just hitting the schedule, and you know how to balance both\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Sr Staff Applications Engineer, Simulation & Debug", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-07", "url": "https://careers.synopsys.com/job/bengaluru/sr-staff-applications-engineer-simulation-and-debug/44408/100290788256", "is_hardware": true, "platform": "talentbrew", "jd_text": "Alternate Job Titles\nSenior Staff Verification Engineer\nSr Staff Applications Engineer, Simulation & Debug\nPrincipal Application Engineer, VCS/Verdi\nSenior Staff FAE, Verification Solutions\nSr Staff Technical Solutions Engineer, EDA\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in verification, the kind where a missed edge case costs six months and millions of dollars, and you have learned to think like both the designer who built it and the engineer trying to break it. You know that simulation is not just about running tests, it is about understanding why a testbench stalls at 3am, why coverage is stuck at 87%, and what it takes to get a customer from 'this doesn't work' to 'this is faster than anything we've run before.'\nYou are comfortable sitting with a customer's verification team, digging into their UVM environment or gate-level timing flow, and walking out with a deployment plan that actually works in their environment, not just in a demo. You do not wait for perfect documentation. You read waveforms, trace through SystemVerilog, script your way around problems, and know when to pull in R&D versus solve it yourself.\nCompetitive benchmarks do not intimidate you. You have run them, you know where VCS wins, and you can explain it in terms that matter to the person signing the contract. You care about the craft. At Synopsys, you will work on verification technology that powers tape-outs across the industry, and the customers you support will remember your name.\nWhat You'll Be Doing\nDrive customer deployments of VCS and Verdi simulation and debug platforms, working directly with design and verification teams to integrate tools into their existing flows\nDiagnose complex technical issues across UVM testbenches, gate-level simulations, low power flows, and timing-aware verification environments\nLead competitive engagements and benchmarking efforts, demonstrating VCS/Verdi performance, capacity, and debug advantages against rival tools\nCollaborate with R&D and product teams to gather customer requirements, reproduce field issues, and influence the product roadmap based on real deployment feedback\nDevelop and optimize automation scripts in Perl, Python, TCL, Shell, and Make to improve customer productivity and streamline verification workflows\nInterface across global teams including product validation, field applications, and customer engineering to propose solutions and drive product improvements\nSupport customers through technical escalations, providing expertise in SystemVerilog, SVA, UVM, low power (UPF), and gate-level simulation methodologies\nThe Impact You Will Have\nEnable customers to close verification faster and reach first-pass silicon success by deploying simulation technology that scales to their toughest designs\nInfluence the VCS and Verdi product roadmap by surfacing real-world customer challenges and competitive gaps that R&D can act on\nWin competitive deals by proving performance, capacity, and debug superiority in head-to-head benchmarks that matter to customer schedules\nAccelerate adoption of advanced features like AI-driven productivity tools, formal integration, and next-gen debug capabilities across your customer base\nReduce time-to-resolution for critical customer issues, turning escalations into deployments and deployments into long-term partnerships\nStrengthen Synopsys' position as the verification platform of choice by making customers successful in ways they can measure and defend internally\nBuild institutional knowledge across the global applications team by documenting solutions, sharing best practices, and mentoring peers on complex verification challenges\nWhat You'll Need\nBachelor's or Master's in Electronics Engineering or equivalent, with 5-12 years of hands-on experience in verification or application engineering\nDeep expertise in simulation technologies, UVM, SystemVerilog Assertions (SVA), and verification methodologies applied to real designs\nStrong command of HDL languages including Verilog, VHDL, and SystemVerilog, with solid understanding of digital design fundamentals\nProven experience with gate-level simulation, timing-aware verification, and low power flows using UPF\nAdvanced scripting ability in Perl, Python, TCL, Shell, and Make, with comfort working in UNIX/Linux environments\nExperience with Synopsys Verdi or similar waveform debug tools is a strong plus, as is knowledge of DPI, C/C++, SystemC, or functional safety standards\nExposure to generative AI technologies or AI-driven EDA workflows is a plus\nWho You Are\nYou can walk into a customer meeting, listen to a verification problem described in half-formed sentences, and walk out with a clear technical plan and next steps\nYou are the person your team pulls in when a customer issue is stuck, not because you know everything, but because you know how to find the answer and who to ask\nYou manage multiple customer engagements at once without dropping threads, and you do not need reminders to follow up or close the loop\nYou push back when a proposed solution does not fit the customer's actual environment, and you are comfortable saying 'that won't work, here's what will'\nTravel does not faze you, whether it is onsite customer visits, regional workshops, or working across time zones with global R&D and field teams\nYou stay current, not because it is required, but because you are genuinely curious about what is next in verification, AI tooling, and EDA technology\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Staff ASIC Verification Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-09-07", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506065", "is_hardware": true, "platform": "oracle", "jd_text": "Job Description – ASIC/SoC Verification Engineer\n\nWe are seeking an experienced Staff ASIC/SoC Verification Engineer to join our dynamic and fast‑paced engineering team. In this role, you will be responsible for ensuring the functional correctness, robustness, and overall quality of our cutting‑edge semiconductor and SoC designs. If you thrive in a collaborative environment and enjoy solving complex technical challenges, this opportunity is an excellent fit.\n\n#LI-VS1\n\nResponsibilities\nResponsibilities:\nVerification Planning and Execution: Develop and execute comprehensive verification plans.\nClose verification with coverage closure, ensuring high-quality results.\nApply standard ASIC verification techniques, including test planning, testbench creation, code and functional coverage, directed and random stimulus generation, and assertions.\n\nTestbench Development: Create and enhance testbenches using SystemVerilog (OVM/UVM) or other standard testbench languages.\nImplement reusable Verification IP (VIP) components.\nCollaborate with third-party VIP providers.\n\nMethodology and Flows: Demonstrate a solid understanding of ASIC design and verification methodologies.\nApply object-oriented programming principles effectively.\nImplement constraint random verification methodology.\n\nTechnical Skills: Proficiency in SystemVerilog (OVM/UVM) and other relevant languages (C/C++, Perl, Tcl, Python, Verilog PLI).\nFamiliarity with industry standards (e.g., I2C/SPI).\nExperience with low-power verification using UPF (Unified Power Format) is a plus.\nKnowledge of formal verification techniques is advantageous.\n\nCollaboration and Communication: \nWork effectively with internal teams and external customers.\nStrong written and verbal communication skills.\nInitiative, analytical problem-solving abilities, and adaptability within a diverse team environment.\n#LI-VS1\n\nQualifications\nQualifications:\nRequired Qualifications\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.\n10 Years of experience in SoC/IP verification,.\nStrong expertise in SystemVerilog, UVM, and advanced verification methodologies.\nHands-on experience with ARM-based SoC architectures, AMBA protocols (AXI/AHB/APB), and system-level interactions.\nProven ability to build reusable, scalable testbench architectures.\nSolid understanding of test planning, coverage-driven verification, and verification metrics.\nExperience with GLS, timing verification, and debug.\nKnowledge of power-aware verification (UPF/CPF).\nStrong scripting and automation skills (Python, Perl, Shell, Make, etc.).\nExposure to AI/ML techniques applied to verification (e.g., intelligent stimulus generation, failure triage, coverage optimization).\nExcellent problem-solving, debugging, and communication skills.\n#LI-VS1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Staff ASIC Verification Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-09-07", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506066", "is_hardware": true, "platform": "oracle", "jd_text": "Job Description – ASIC/SoC Verification Engineer\n\nWe are seeking an experienced Staff ASIC/SoC Verification Engineer to join our dynamic and fast‑paced engineering team. In this role, you will be responsible for ensuring the functional correctness, robustness, and overall quality of our cutting‑edge semiconductor and SoC designs. If you thrive in a collaborative environment and enjoy solving complex technical challenges, this opportunity is an excellent fit.\n\n#LI-VS1\n\nResponsibilities\nResponsibilities:\nVerification Planning and Execution:Develop and execute comprehensive verification plans.\nClose verification with coverage closure, ensuring high-quality results.\nApply standard ASIC verification techniques, including test planning, testbench creation, code and functional coverage, directed and random stimulus generation, and assertions.\n\nTestbench Development:Create and enhance testbenches using SystemVerilog (OVM/UVM) or other standard testbench languages.\nImplement reusable Verification IP (VIP) components.\nCollaborate with third-party VIP providers.\n\nMethodology and Flows:Demonstrate a solid understanding of ASIC design and verification methodologies.\nApply object-oriented programming principles effectively.\nImplement constraint random verification methodology.\n\nTechnical Skills:Proficiency in SystemVerilog (OVM/UVM) and other relevant languages (C/C++, Perl, Tcl, Python, Verilog PLI).\nFamiliarity with industry standards (e.g., I2C/SPI).\nExperience with low-power verification using UPF (Unified Power Format) is a plus.\nKnowledge of formal verification techniques is advantageous.\n\nCollaboration and Communication:Work effectively with internal teams and external customers.\nStrong written and verbal communication skills.\nInitiative, analytical problem-solving abilities, and adaptability within a diverse team environment.\n#LI-VS1\n\nQualifications\nRequired Qualifications\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.\n10 Years of experience in SoC/IP verification,.\nStrong expertise in SystemVerilog, UVM, and advanced verification methodologies.\nHands-on experience with ARM-based SoC architectures, AMBA protocols (AXI/AHB/APB), and system-level interactions.\nProven ability to build reusable, scalable testbench architectures.\nSolid understanding of test planning, coverage-driven verification, and verification metrics.\nExperience with GLS, timing verification, and debug.\nKnowledge of power-aware verification (UPF/CPF).\nStrong scripting and automation skills (Python, Perl, Shell, Make, etc.).\nExposure to AI/ML techniques applied to verification (e.g., intelligent stimulus generation, failure triage, coverage optimization).\nExcellent problem-solving, debugging, and communication skills.\n#LI-VS1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Staff Digital Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-09-07", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506536", "is_hardware": true, "platform": "oracle", "jd_text": "Description for Internal Candidates\n \n\n   \n\nDescription for Internal Candidates\n \n\n        \n\nJob Description details:\n\n \n\nonsemi (Nasdaq: ON) is driving technology breakthroughs that deliver on the promise of a sustainable future focusing on the automotive and industrial markets. The intelligent sensor group, ISG, focuses on image and time of flight sensors. Our sensors are improving people’s lives through improved safety and automation where our products are used in imaging for information applications like scanning, factory automation, smart office, intelligent appliances, and safety/autonomous systems for automotive. We are market leaders in sensors for automotive and machine vision.\n\n \n\nResponsibilities\n\nWe are looking for engineers to join our team working on some of our most innovative and successful products.\n\n \n\nWhat you would work on\n\nMicro architect, implement and verify the digital processing blocks which are part of a CMOS Image Sensor.\n\nInteract with multiple cross functional teams on requirements and deliverables.\n\nResponsibilities\nResponsibilities for Internal Candidates\n \n\n   \n\nWhat you need\n\nBE/ME in electronics or related technical field.\n\nAt least 6 years of relevant experience in semiconductor product development.\n\nExperience going through full ASIC development cycle including concept, specification, design, verification and documentation.\n\nExperience in working on data path elements, control logic, design for synthesis, multi clock domain designs, low power design techniques and behavioural modelling.\n\nKnowledge of System Verilog and scripting and familiarity with C modelling.\n\nShould have good analytical skills for debug work needed during verification.\n\nGood written and verbal communication skills.\n\n#LI-RT1\n\nQualifications\nResponsibilities for Internal Candidates\n \n\n     \n\nExperience with the following is an advantage but not a requirement:\n\nKnowledge of image sensor design.\n\nUnderstanding of a typical mixed signal system requirement.\n\n \n\n \n\n   \n\n \n \n\n     \n\nWhy Join Us\n\nWe create a diverse set of world-class products in a friendly and team-oriented atmosphere. We provide an environment of continual learning and growth opportunities and support volunteer and charitable programs. We offer competitive benefit package and a great place to work. You will be able to build up a career in a successful international company, and you can participate in interesting international projects.\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Senior Design Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-07", "url": "https://careers.arm.com/job/bengaluru/senior-design-engineer/33099/100290470976", "is_hardware": true, "platform": "talentbrew", "jd_text": "Our Solutions Engineering Physical IP team comprises some of the industry’s leading experts in advanced deep-submicron circuit design. This role offers an exciting opportunity to join our Custom Standard Cell Design Engineering team and contribute to innovative technologies at the most advanced process nodes.\nIn this position, you will develop Arm custom standard cells targeting the latest sub-3nm process technologies. Working closely with circuit and physical design engineers, you will co-optimize cell architectures and implementations to improve the power, performance, and area (PPA) of Arm cores integrated into best-in-class SoCs across infrastructure, client, automotive, and IoT market segments.\nYou will collaborate closely with mask design engineers to achieve optimally tuned layouts and will be responsible for standard cell characterization, modeling, EDA view generation, and validation through comprehensive QA flows using industry-standard EDA tools.\nThe ideal candidate brings strong expertise in transistor-level circuit design, standard cell characterization, design verification, and automation. This role is critical to delivering high-performance, low-power logic libraries for next-generation SoCs and custom digital IP.\nKey Responsibilities\nDevelop and optimize Arm custom standard cells for advanced sub-3nm process technology nodes.\nPerform standard cell characterization, modeling, and EDA view generation, ensuring that generated models accurately represent circuit and design intent.\nDesign, analyze, and verify transistor-level circuits to meet demanding power, performance, area, and reliability requirements.\nCo-optimize circuit designs with physical design engineers to improve core- and SoC-level PPA.\nCollaborate closely with mask design engineers to optimize cell layouts for electrical performance, area, manufacturability, and design-rule compliance.\nDevelop and execute robust QA and validation methodologies across standard cell library views using a variety of EDA tools.\nIdentify opportunities to improve characterization methodologies, automation, tools, and development processes, and drive these improvements across project teams and related functions.\nCollaborate effectively across circuit design, physical design, mask design, methodology, and other engineering teams to deliver production-quality standard cell libraries.\nAnalyze complex technical issues, develop practical solutions, and clearly communicate conclusions and recommendations to engineering stakeholders.\nRequired Skills and Experience\nBSEE with 4+ years of relevant circuit design and/or standard cell characterization experience, or MSEE with 3+ years of relevant experience.\nExperience identifying, designing, optimizing, and verifying standard cells specifically targeted at improving core- and SoC-level PPA.\nStrong understanding of MOSFET electrical characteristics, transistor-level device physics, circuit behavior, PPA trade-offs, layout effects, and process variability, particularly for advanced process technologies.\nExpertise in transistor-level design and analysis of static CMOS circuits, including state-retaining elements such as latches and flip-flops.\nExtensive hands-on experience with standard cell characterization, EDA view generation, modeling, and QA/validation.\nProficiency with industry-standard cell characterization tools and SPICE-level circuit simulators.\nProficiency in scripting and automation using languages such as Python and/or Perl.\nStrong analytical and problem-solving skills, with the ability to investigate complex circuit and characterization issues and iteratively develop effective solutions.\nAbility to clearly communicate technical findings, conclusions, trade-offs, and recommendations.\nDemonstrated ability to collaborate effectively across engineering disciplines, manage diverse responsibilities, continuously develop technical skills, and contribute positively to a team environment.\nNice to Have Skills and Experience\nExposure to physical design implementation flows, including place-and-route and signoff methodologies.\nFamiliarity with advanced-node design considerations and their impact on standard cell architecture, characterization, and implementation.\nExperience developing automation or methodology improvements for standard cell design, characterization, or validation flows.\n \n#LI- BB1\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Design Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-07", "url": "https://careers.arm.com/job/bengaluru/design-engineer/33099/100290447600", "is_hardware": true, "platform": "talentbrew", "jd_text": "Our Solutions Engineering Physical IP team comprises some of the industry’s leading experts in advanced deep-submicron circuit design. This role offers an exciting opportunity to join our Custom Standard Cell Design Engineering team and contribute to innovative technologies at the most advanced process nodes.\nIn this position, you will develop Arm custom standard cells targeting the latest sub-3nm process technologies. Working closely with circuit and physical design engineers, you will co-optimize cell architectures and implementations to improve the power, performance, and area (PPA) of Arm cores integrated into best-in-class SoCs across infrastructure, client, automotive, and IoT market segments.\nYou will collaborate closely with mask design engineers to achieve optimally tuned layouts and will be responsible for standard cell characterization, modeling, EDA view generation, and validation through comprehensive QA flows using industry-standard EDA tools.\nThe ideal candidate brings strong expertise in transistor-level circuit design, standard cell characterization, design verification, and automation. This role is critical to delivering high-performance, low-power logic libraries for next-generation SoCs and custom digital IP.\nKey Responsibilities\nDevelop and optimize Arm custom standard cells for advanced sub-3nm process technology nodes.\nPerform standard cell characterization, modeling, and EDA view generation, ensuring that generated models accurately represent circuit and design intent.\nDesign, analyze, and verify transistor-level circuits to meet demanding power, performance, area, and reliability requirements.\nCollaborate closely with mask design engineers to optimize cell layouts for electrical performance, area, manufacturability, and design-rule compliance.\nExecute robust QA and validation methodologies across standard cell library views using a variety of EDA tools.\nIdentify opportunities to improve characterization methodologies, automation, tools, and development processes, and drive these improvements across project teams and related functions.\nCollaborate effectively across circuit design and other engineering teams to deliver production-quality standard cell libraries.\nAnalyze complex technical issues, develop practical solutions, and clearly communicate conclusions and recommendations to engineering stakeholders.\nRequired Skills and Experience\nBSEE with 2+ years of relevant circuit design and/or standard cell characterization experience, or MSEE with 2+ years of relevant experience.\nExperience in designing and verifying standard cells specifically targeted at improving core- and SoC-level PPA.\nStrong understanding of MOSFET electrical characteristics, transistor-level device physics, circuit behavior, PPA trade-offs, layout effects, and process variability, particularly for advanced process technologies.\nExpertise in transistor-level design and analysis of static CMOS circuits, including state-retaining elements such as latches and flip-flops.\nHands-on experience with standard cell characterization, EDA view generation, modeling, and QA/validation.\nProficiency with industry-standard cell characterization tools and SPICE-level circuit simulators.\nProficiency in scripting and automation using languages such as Python and/or Perl.\nStrong analytical and problem-solving skills, with the ability to investigate characterization issues and iteratively develop effective solutions.\nAbility to clearly communicate technical findings, conclusions, trade-offs, and recommendations.\nDemonstrated ability to collaborate effectively across engineering disciplines, manage diverse responsibilities, continuously develop technical skills, and contribute positively to a team environment.\nNice to Have Skills and Experience\nFamiliarity with advanced-node design considerations and their impact on standard cell architecture, characterization, and implementation.\nExperience developing automation or methodology improvements for standard cell design, characterization, or validation flows.\n \n#LI-BB1\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Design Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-07", "url": "https://careers.arm.com/job/bengaluru/design-engineer/33099/100290446080", "is_hardware": true, "platform": "talentbrew", "jd_text": "Role Summary\nOur Solutions Engineering Physical IP team comprises some of the industry’s leading experts in deep submicron circuit design. This position is a wonderful opportunity for you to work with our custom standard cell design engineering team on innovative technologies. Your work will have a significant lasting impact as the designs will be used in Solutions Engineering products servicing the infrastructure, client, automotive, and IoT market segments.\nIn this role, you will be responsible for the layout development of Arm custom standard cells in the latest, sub-3nm process technology nodes. The ideal candidate will be an expert in standard cell layout, physical verification, and automation techniques. You will work in close collaboration with the circuit design team to provide optimally tuned layout, and validate them through QA flows that use a variety of tools. This role is crucial in delivering high-performance, area-optimized, and DRC-clean logic libraries for next-generation SoCs and custom digital IPs.\nKey Responsibilities\nIndependently develop transistor-level physical layouts from circuit schematics.\nCreate and interpret stick diagrams and determine efficient transistor placement and routing strategies.\nOptimize device placement, diffusion sharing, routing and pin accessibility to achieve compact and robust layouts.\nPerform DRC, LVS and physical-verification debugging and independently resolve routine violations.\nUnderstand and apply requirements from technology Design Rule Manuals (DRMs) and established layout guidelines.\nPerform layout modifications resulting from schematic, design-rule or methodology changes.\nUnderstand parasitic resistance and capacitance introduced by physical implementation and their effect on circuit behaviour.\nApply established layout techniques to improve power, performance and area (PPA).\nConsider reliability requirements such as current density, electromigration and routing robustness during implementation.\nPerform layout quality checks and participate in peer reviews.\nReview straightforward layout work produced by other engineers where required.\nWork with circuit designers to identify practical solutions to layout-related implementation challenges.\nManage assigned workload, communicate progress and identify potential technical or schedule risks.\nSupport development of less-experienced engineers through knowledge sharing and occasional on-the-job guidance.\nContribute to continuous improvement of layout practices and team workflows.\nTechnical Skills / Expertise\nCMOS transistor-level circuit layout\nSchematic interpretation\nStick-diagram development\nTransistor placement and diffusion optimization\nDRC and LVS\nPhysical-verification debugging\nDesign Rule Manual interpretation\nParasitic resistance and capacitance\nBasic EM/current-density considerations\nLayout-dependent effects\nPPA-aware physical implementation\nSemiconductor manufacturing/process fundamentals\nPractical AI-tool proficiency is required. Candidates should be able to use approved AI assistants to accelerate technical investigation, generate and refine Python/Tcl/SKILL scripting ideas, analyze logs and verification results, improve documentation and automate repetitive engineering tasks, while independently validating AI-generated outputs for technical correctness and complying with data-security and responsible-AI requirements.\nExperience with industry-standard custom-layout and physical-verification environments such as Cadence Virtuoso, Synopsys Custom Compiler, Siemens Calibre or equivalent tools is desirable/expected depending on seniority.\nWhat We Are Looking For\nComplete straightforward layout assignments with minimal or no supervision.\nTake ownership of assigned layouts from initial implementation through physical-verification closure.\nMake sound engineering decisions using established methodology and previous experience.\nIndependently troubleshoot common layout and verification problems.\nRecognize when a problem requires specialist or senior-level input.\nBalance layout quality, area, performance and schedule requirements.\nCommunicate technical information clearly within the engineering team.\nWork effectively with circuit designers and related engineering teams.\nProvide constructive peer-review feedback.\nConsistently deliver accurate, high-quality work within agreed schedules.\nUse AI tools as a normal engineering productivity aid while retaining ownership of technical decisions, verification and final deliverables.\nEducation / Experience :\nBachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Microelectronics, Semiconductor Engineering or equivalent practical experience. Professional experience in custom IC, standard-cell, memory, analog or related transistor-level layout design is preferred.\n“Nice To Have” Skills and Experience :\nExposure to physical design implementation flow\n \n#LI-BB1\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Design Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-07", "url": "https://careers.arm.com/job/bengaluru/design-engineer/33099/100290425392", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview:\nAs a part of Arm's Solutions Engineering group we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance, and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is the development of comprehensive implementation and analysis methodologies.\n \nResponsibilities:\n \n Synthesis, Physical implementation, Timing closure and Physical signoff of CPU cores, system interconnect, and other ARM Designs.\nAnalyze design timing, area and power to help improve the quality of ARM Design.\nOptimize design, flow and methodologies to achieve best in class PPAT working with various internal and external teams.\nDevelop and deploy new methodologies to improve implementation efficiency and results\nSupport and develop detailed implementation analysis and data-mining methodologies.\nWork with implementation and physical IP RTL design teams to drive analysis and optimization of our IP.\nConverting R&D concepts into real implementation solutions.\nEnable our partners to achieve the best possible quality of results\n \n \nRequired Skills and Experience :\nBachelor’s or master’s degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields.\n3-5 years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification\nStrong Communication and Problem-Solving Skills.\nExperience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams\n \n#LI-BB1\n \nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "ASIC Digital Design, Executive Director", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-07", "url": "https://careers.synopsys.com/job/bengaluru/asic-digital-design-executive-director/44408/100305008208", "is_hardware": true, "platform": "talentbrew", "jd_text": "The Team You’ll Be A Part Of:\n \nYou will be leading a dynamic and innovative R&D verification team focused on developing digital PCI Express controllers within the Intellectual Property Group within Synopsys. This team collaborates closely with the VIP, PHY, Sub-System service, emulation, methodology, support and customer success teams to deploy the PCIe controller to the market space as an overall one Synopsys solution as high quality differentiated products.\n \nYou Are:\nAn inspiring leader with a proven track record in managing and leading teams focused on IP product development. You thrive in a matrixed, international, and team-oriented environment with multiple stakeholders. Your collaborative, supportive, and inspirational leadership style delivers results that exceed expectations. \nYou are a leader that builds structure and growth of teams that enables successful execution to plan a predefined plan of record.\nIdeally you are an expert in PCI Express and ARM based SOC architectures around PCI Express that enables you to drive product definition and roadmaps. \nYou are a verification leader with previous digital controller development background and experience in managing large R&D digital teams. \n \nYou can leverage your expertise in leading innovative world class IP solutions in driving quality leading across a multi-site team to communicate the product verification strategy. \nYou have a deep understanding of digital design verification principles that enables you to lead complex verification projects. Your communication skills are top-notch, allowing you to effectively influence and collaborate with both internal and external stakeholders. \n \nWhat You’ll Be Doing\nUltimately responsible for PCIe/CXL verification strategy and functional quality. \nLeading and managing an organization of large teams of R&D verification engineers focused on verifying digital IP controllers, namely PCIe/CXL, to the product line’s plan-of-record. \nEnsure that the verification team capacity and team structure are setup to meet market demand. With fixed resources, help define the prioritization of asks with stakeholders and align an execution plan to achieve of plan of record. \nAdapting to methodologies that improve the quality of the controllers and productivity of the team.\nManage project scope, project schedule, project resource costs and project risk. Review project convergence metrics with team, identifying risks early and mitigate against such risk. Align with management on project resource needs and trade-offs. \nLead verification R&D activities as required around customer pre-sales engagements and post-sales support and escalation management as pertaining to quality. \n \nThe Impact You Will Have\nEnsuring that the underlying team structure, competency and productivity around verification activity can deliver on-time and with quality to the market requirements \nContributing to Synopsys' leadership in the semiconductor industry through and more specifically PCI Express controllers \nDelivering efficiency & productivity gains in digital design and verification of IP products. \nMinimize both pre and post sales customer escalations past your role\nDrive the quality of the Synopsys PCI Express controller product line to ensure a smooth customer experience and the bolster the reputation of Synopsys as the number #1 IP provider\n \nWhat You’ll Need:\nA verification expert in UVM methodologies, testbench environment creation and verification in constrained Random Verification, CRV, utilizing functional coverage to close verification.\nExpert in leading a large verification teams. \nExperience in creating structures with clean lines of responsibility and accountability down management chain. \nIdeally, deep knowledge of PCIe technologies and related protocols.\nProven track record of leading and managing teams focused on IP product development.\nAbility to agilely learn from team mistakes and either define new process’s or enforce existing process’s as preventative actions.  \nExcellent communication, organizational, risk assessment/mitigation and time management skills. Ability to abstract up and communicate meaningful conclusions and define next steps. \nEmbodying a collaborative, supportive, and inspirational leadership style to deliver results that exceed expectations.\n \nWho You Are:\nInspirational and collaborative leader.\nExcellent communicator and collaborator.\nTeam-oriented and supportive.\nInnovative and forward-thinking.\nResults-driven and detail-oriented.\nAdaptable and comfortable in a matrixed, international environment.\nA strategic thinker with a passion for innovation.\nA mentor and leader with a commitment to developing others.\nAn expert in your field with a deep understanding of digital design principles.\nExcellent communication and leadership skills.\nCapable of fostering a culture of collaboration, innovation, and excellence.\n \nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Sr. RTL Design Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-06T06:47:00+00:00", "url": "https://global-external-amd.icims.com/jobs/91609/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. THE ROLE: We are looking for an adaptive, self-motivatived design engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Design Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Develop/Maintain design and integration for various in-house/vendor IPs, subsystems and SoC. Ensure quality of the IP/Subsystem/SoC through various static QCs viz LINT, CDC, RDC, CLP/VCLP. Develop/Own various constraints like SDC, UPF, etc, Interact with various stakeholders to ensure timing closure and verification robustness of your design. PREFERRED EXPERIENCE: Familiarity with RTL coding and various indistry standard protocols like PCie, AMBA etc. Familiarity with various QC tools/flows and IPXACT. Strong fundamentals of VLSI, FIFO, arbitration techniques etc. ACADEMIC CREDENTIALS: Bachelors or Masters degree in Electronics/VLSI/computer engineering/Electrical Engineering with 5+Yrs of exp #LI-SR4 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Multi-Media Post-Silicon validation Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-06T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720989196", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nQualcomm Multimedia Validation and Integration team is a part of the Silicon Validation and Emulation Engineering Team and is responsible for the overall quality of Multimedia-IP in Silicon. As a member of our MMVI team, the candidate will develop suite of Multimedia/Imaging-cores, related drivers for bring-up, functional, performance, power, debug, & manufacturing tests.\n\nCandidate will be closely working with System-Architects, Designers, Verification, Firmware and Software engineers, participate in design-reviews to gather bring-up requirements, gather-info, interpret, develop low-level/bare-metal code (C/C++), provide the estimated scope of work and schedules, bring-up HW platforms, debug HW/SW issues.\n\nWe are currently seeking self-motivated Engineer who will perform device level and system level verification, validation, and debug, both in Emulation and in Post-Silicon.\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\n\nMinimum Qualifications\n•  6+ years Systems/Debug/Integration Engineering or related work experience.\n•  6+ year of experience with C, C++, Python, Java, Shell-scripting, Version-Control Tools, RTOS\n•  6+ years of experience using in-circuit emulation/debug tools\n•  Experience with Multimedia Engines/Technology (Camera & Image Processing, Video Compression, Compute Vision/XR/AR, GPU, Display)\n•  Familiarity with High-Speed interfaces & Signal Integrity\n•  Embedded SW/drivers & development of low-level HW interfaces in C/ASM. Device test and script, automation development (Python preferred), test-plan development.\n•  Good EE fundamentals, initiative, taking ownership and responsibilities, critical thinking\n• Strong written, verbal, interpersonal, presentation & communication skills\n \nApplicants should have significant experience in below areas:\n•  6+ yrs of Embedded SW development & related experience (C/C++/OOP/Java, Python, Shell, RTOS)\n•  ARM-based System-On-Chip & Emulation debug & validation experience related to board bring-up and low-level software and hardware issues debug; familiarity with ARM Coresight IP, compilers, linkers, scatter-files are desirable\n• Experience in test-validation & debug of (MIPI-based) High-Speed interfaces, signal-integrity issues and Camera/Video Imaging concepts\n•  Experience in digital integrated circuit or core design, digital IC architecture, and complete ASIC lifecycle development\n•  Experience with Machine Learning (TensorFlow, PyTorch), Deep Learning, Neural Networks\n•  Experience in a lab environment using standard test-equipment (Scopes, Logic-Analyzers, etc.)\n• Understanding of JTAG debugging, Lauterbach Trace32 environment & scripting\n• Understanding of low power design concepts, performance and thermal processes\n•  Some knowledge of Verilog/System Verilog, FPGA design is a plus\n•  Familiarity with DFT/DFD & ATE/ATPG is a plus\n•  Familiarity with RMA process\n \nMinimum Qualifications:\n\nBachelor's degree in Electronics and Comm Engineering,  Computer Science, Electrical Engineering, or related field and 6+ years of Hardware Engineering, Systems Engineering, Software Engineering, or related work experience\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU RTL Design - Sr Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-06T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720959548", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    12+ years of Hardware Engineering or related work experience.\n•    3+ years of experience with circuit/logic design/validation (e.g., digital, analog, RF).\n•    3+ years of experience utilizing schematic capture and circuit stimulation software.\n•    3+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test highly critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Participates in or leads the implementation of advanced design rules and processes for electronic hardware, equipment, and/or integrated circuitry.\n•    Conducts highly complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops novel manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of highly critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Advises and leads engineers in the development of complex hardware designs, evaluating various design features to identify potential flaws or issues.\n•    Writes detailed technical documentation for highly complex Hardware projects; reviews technical documentation for junior engineers.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making is significant in nature and affects work beyond immediate work group.\n•    Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. \n•    Has a moderate amount of influence over key organizational decisions.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RTL Design -Sr Eng/lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-06T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720899736", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    3+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n\nPrincipal Duties and Responsibilities:\n•    Applies Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Assists in the assessment of complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Silicon Physical Design Engineer - Bengaluru", "company": "Graphcore", "location": "Bengaluru, India", "date_posted": "2026-09-05T01:56:43-04:00", "url": "https://job-boards.greenhouse.io/graphcore/jobs/8784128002", "is_hardware": true, "platform": "greenhouse", "jd_text": "Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. \n\nAs part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing.  \n\nThe physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). \n\nWe are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge  designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to take ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. \n\nResponsibilities and Duties \n\nApplicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, focusing on achieving robust, high-performance and power-efficient designs in leading-edge process technologies while meeting ambitious development schedules\n\nContributions are expected to span multiple areas and involve: \n\nusing state-of-the-art EDA tools and in-house Graphcore flows to deliver final designs that are of sign-off quality \n\nenhancing existing flows and in-house tools/APIs to support new features and/or methodologies \n\nanalysis and/or debugging of complex engineering problems leading to workable solutions \n\ndeveloping an understanding of emerging technical issues and applying that knowledge to optimise in-house flows and methodologies \n\nCandidates will be expected to work closely both with other teams within Graphcore and with 3rd party support engineers/contractors, ensuring good communication between all parties, and to contribute meaningfully to the overall efficiency and success of the Physical Team\n\nEssential skills: \n\n A Degree in Electronic/Electrical Engineering, Computer Science or related subject with 3+ years of Industry experience \n\n Be highly motivated, a self-starter, and a team player\n\n Excellent problem-solving skills for debugging issues seen and finding root causes\n\n Ability to program/script (required to solve design issues, typically in Tcl and Python)\n\n Experience in 7nm or smaller technologies\n\n A good breadth of experience with physical design flows including: \n\nFloorplanning/Budgeting\n\nSynthesis\n\nPlace and Route\n\nClock CTS\n\nLogical Equivalence\n\nTiming Analysis\n\nPhysical Verification (DRC/LVS/ERC) \n\n Desirable skills: \n\n In depth expertise in one or more aspects of physical design flows\n\n Structuring of builds to maximise PPA\n\n Silicon transistor knowledge including std cell libraries and/or memories\n\n 5D and 3D design (CoWoS, UCIe etc.)\n\n High speed, high power and/or full reticle chip design\n\n Ethernet, PCIe, LPDDR, HBM interfaces\n\n Power integrity and optimization\n\n 2nm or 3nm technologies\n\n Chip finishing (pad rings, chip level LVS/DRC/ERC)\n\n Design for test\n\n Team management\n\n Project Planning\n\nIn addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.", "jd_status": "stored"}, {"title": "Senior Engineer II - Physical Design", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-09-04", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Senior-Engineer-I---Physical-Design_R3270-26-8", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nMicrochip’s DSPIC Business Unit is seeking a skilled and experienced Physical Design Engineer to join our global DSPIC Physical Design team. In this role, you will be instrumental in driving the successful execution of microcontrollers and microcontroller-based SOC designs, delivering the next generation of hierarchical, low power, mixed signal microcontroller solutions.\nKey Responsibilities:\nImplement complex mixed signal, low power designs using state-of-the-art FLASH process technologies.\nWork independently and efficiently on assigned project responsibilities, from new design exploration through delivery of GDS (netlist to GDSII flow) and Metal-only ECO implementation.\nProvide Physical Design support for test chip shuttles, including development work associated with new concepts and flow.\nDevelop and enhance Physical Design flow and methodology, including comprehensive documentation.\nConduct power integrity and reliability analysis, ensuring robust sign-off for all designs.\nDetailed Job function:\nConduct floorplan exploration and optimization for accurate die size estimation.\nPerform power domain and voltage area-based floor planning, including power grid planning and implementation.\nExecute placement and optimization with a focus on timing, area, and power efficiency.\nManage clock tree synthesis, balancing, and debugging to ensure robust clock distribution.\nDrive post-route timing optimization and timing closure to meet design specifications.\nPerform timing and signal integrity analysis at both chip and block levels.\nAbility to lead chip and block level physical implementation activities.\nDevelop and refine physical design flow and methodology for improved efficiency and quality.\nConduct physical verification, including DRC (Design Rule Check) and LVS (Layout Versus Schematic).\nEnsure IR drop and electromigration (EM) signoff for reliable power delivery.\nImplement timing and metal-only ECOs (Engineering Change Orders) as needed.\nInterface with internal and external IP teams, as well as CAD vendors, to resolve technical issues.\nCollaborate closely with synthesis, DFT, and other cross-functional global teams to achieve timely tapeout and ensure first-pass working silicon.\n\nRequirements/Qualifications:\n\nBachelor of Engineering in Electrical / Electronic Engineering or Master of Engineering in Electrical / Electronic Engineering or Equivalent\nMinimum of 6 years of hands-on experience in Physical Design and related technical areas, demonstrating a strong track record of successful project execution.\nAdvanced knowledge of place and route methodologies, as well as low power physical design flows and methodologies.\nProficiency with industry-standard physical implementation and analysis tools such as Innovus or Fusion Compiler, Calibre, Redhawk, Starrcxt, or equivalent EDA tools.\nStrong scripting skills in TCL, PERL, and Shell, along with working knowledge of hardware description languages such as Verilog and VHDL.\nExcellent analytical and debugging abilities, with a proactive approach to identifying and resolving technical challenges.\nIndependent, self-motivated, and capable of managing responsibilities.\nOutstanding oral and written communication skills, with the ability to clearly convey technical concepts and collaborate effectively within a team.\nFamiliarity with advanced nodes is desirable.\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Senior Manager, Post-Silicon Validation Engineering", "company": "Lattice", "location": "Pune, India", "date_posted": "2026-09-04", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Pune-India/Senior-Manager--Post-Silicon-Validation-Engineering_R-103206", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\n\nJob Description\nAs a Senior Manager in Silicon Design Validation, You lead a highly motivated team focused on ensuring the quality and performance of advanced semiconductor products. Your role provides strategic oversight and technical direction across the full post-silicon lifecycle, from first silicon arrival to production release.\n \nKey Leadership Areas:\nTechnology Enablement & Learning Culture\nFostering a learning environment where engineers gain hands-on experience with FPGA architectures and foundational IP blocks such as SERDES (PMA/PCS), DDR memory (DDR4, LPDDR4, DDR5), DPHY, PLLs, DSPs, MIPI, Fabric, and I/O subsystems.\nValidation/Characterization Strategy & Execution\nOverseeing the validation and characterization of analog, digital, and mixed-signal IPs, ensuring robust coverage from initial silicon bring-up through production qualification.\nPlanning & Infrastructure Development\nGuiding the development of validation plans, including bench hardware and software requirements, and ensure the team has the necessary tools and infrastructure to execute effectively.\nRTL Development for Test Enablement\nSupervising the creation of custom RTL test logic to support targeted validation and characterization efforts, enabling deeper insight into IP behavior.\nSilicon Bring-Up & Debug Leadership\nDriving the bring-up of new silicon products, driving validation and debug activities to assess IP functionality and performance. This includes characterizing datasheet parameters, performing statistical analysis of measured data, and overseeing datasheet preparation.\nCross-Functional Collaboration\nActing as the central liaison between design, verification, manufacturing, test, quality, and marketing/application teams, ensuring alignment and smooth transition from silicon arrival to product release.\nCustomer Support & Issue Resolution\nProviding leadership in resolving post-release customer issues, coordinating with internal teams to ensure timely and effective solutions.\n\nYou Have…\n15+ years of experience in silicon validation, including 3–5 years in a leadership role.\nMaster or Bachelor’s degree in Electrical Engineering with a strong passion for engineering and management in silicon design validation.\nProven track record in managing complex validation projects and leading cross-functional teams.\nDeep expertise in high-speed SerDes interface characterization and protocol compliance testing (e.g., PCIe, Ethernet, SDI, CoaXpress, JESD204, MIPI D-PHY, CSI/DSI-2, USB, DisplayPort, HDMI).\nStrong background in high-speed board design, signal integrity evaluation, and debug.\nProficient in Verilog/VHDL and FPGA design implementation using industry-standard tools.\nSkilled in test automation development using Python and Perl.\nSolid understanding of statistical analysis and tools such as JMP and R.\nHands-on experience with bench equipment including BERT, VNA, oscilloscopes, and protocol analyzers.\nExposure to FPGA-based emulation and prototyping environments.\nExcellent written and verbal communication skills for effective collaboration across teams.\nHighly self-motivated, proactive, and strong in critical thinking and problem-solving.\n\nWho Are We?\nAt Lattice, we’re a collaborative and solutions-driven team that values innovation, problem-solving, and having fun along the way. We specialize in developing low-power, programmable logic technologies that power a wide range of applications—from the Edge to the Cloud.\nOur products and solutions span differentiated programmable logic devices, system-level solutions, design services, and IP licensing. As the leader in low-power programmable technology, we help solve complex customer challenges across communications, computing, industrial, automotive, and consumer markets.\nWhat sets us apart is our deep technical expertise, long-standing customer relationships, and commitment to world-class support. Together, we’re enabling a smarter, more secure, and connected world.\n\nJoin Team Lattice…and help us continue to drive innovation that creates a smarter, better-connected world. Together, we enable what’s next.\n\nWhat are you waiting for? Apply today!\nAt Lattice, we believe great engineers come from diverse backgrounds. Even if your experience doesn’t check every box, we encourage you to apply. This role offers a unique opportunity to grow your skills in a supportive environment where learning is part of the journey. With the depth and breadth of knowledge on our team, Lattice is a great place to build your expertise and take your career to the next level\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Staff Engineer - Post Siiicon Validation", "company": "Lattice", "location": "Pune, India", "date_posted": "2026-09-04", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Pune-India/Staff-Engineer---Post-Siiicon-Validation_R-103207-1", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nThe ideal candidate is highly motivated in developing a career in Silicon Design Validation engineering.  You will get significant exposure and training in the following areas:\n \nChance to learn FPGA and it’s buildng block such as SERDES(PMA/PCS), Memory DDR(DDR4, LPDDR4, DDR5 etc), DPHY, PLL, DSP, MIPI, Fabric, I/O etc but not limited.\nValidate and characterize various IPs from silicon arrival to release to production.\nDevelop validation and characterization plans for certain IP, bench hardware and software.\nDevelop test logic RTL to achieve intended validation/characterization test.\nDrive new silicon product bring-up, validation, debug to asses IP functionality/performance. Characterizing data sheet parameters. Analyzing the measured data with statistical view.  Data sheet preparation etc.\nServe as the central resource with design, verification, manufacturing, test, quality and marketing/apps as the product(s) move Silicon arrival to product release.\nSupporting customer issues as required to resolve issues found after product release\nYou Have…\n8+ years of experience\nElectrical Engineering degree with a strong desire to pursue an engineering career in Silicon Design Validation\nCapability to lead small group of teams as tech lead.\nExpertise in High Speed Serdes Interface characterization and protocol compliance testing such as PCIe/Ethernet/SDI/CoaXpress/JESD204, MIPI D-PHY, MIPI CSI/DSI-2, USB and DisplayPort/HDMI etc.\nExpertise in high speed board design and signal integrity evaluation/debug.\nExpertise in Verilog/VHDL and design implementation using FPGA development tools.\nExpertise in test automation development using programming languages such as Python, Perl.\nKnowledge of statistical analysis concepts and use of analysis tools such as JMP, R.\nProficiency with bench equipment for device characterization such as BERT, VNA, Oscilloscopes, Protocol Exerciser/Analyzers.\nExposure on FPGA(emulation/prototyping etc)\nStrong written and verbal communication skills to work with cross-functional team\nSelf-motivated and proactive with critical thinking.\nGood problem solving and debugging skills.\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Silicon Validation Engineer", "company": "Lattice", "location": "Pune, India", "date_posted": "2026-09-04", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Pune-India/Silicon-Validation-Engineer_R-103155", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nDo you have a passion for invention and self-challenge? This position gives you an opportunity to learn and participate in one of the most\ncutting-edge projects that Lattice’s Silicon Engineering team has embarked upon to date. We are validating building blocks in FPGA on board level to ensure functionality and performance aspect of Design intent. FPGA consists of various IPs as a building block such as\nSERDES(PMA/PCS), Memory DDR(DDR4, LPDDR4, DDR5 etc), DPHY, PLL, DSP, Fabric, I/O etc. As a Silicon Design Validation engineer,\nyou will have an opportunity to learn and train yourself on how to validate one/or many of the building blocks within the FPGA. And also, you\nwill be able to acquire knowledge on process/methodology required for validating certain IPs from planning to completion. While you are\nworking on those, you will be exposed to cutting edge equipment and advanced boards as well as Various SW/tools/scripts.\nWhat you’re going to be exposed to and learn:\nThe ideal candidate is highly motivated in developing a career in Silicon Design Validation engineering. You will get significant exposure and\ntraining in the following areas:\nChance to learn FPGA and it’s build block such as SERDES(PMA/PCS), Memory DDR(DDR4, LPDDR4, DDR5 etc), DPHY,\nPLL, DSP, MIPI, Fabric, I/O etc but not limited.\n•\n• Validate and characterize various IPs from silicon arrival to release to production.\n• Develop validation and characterization plans for certain IP, bench hardware and software.\n• Develop test logic RTL to achieve intended validation/characterization test.\nDrive new silicon product bring-up, validation, debug to asses IP functionality/performance. Characterizing data sheet\nparameters. Analyzing the measured data with statistical view. Data sheet preparation etc.\n•\nServe as the central resource with design, verification, manufacturing, test, quality and marketing/apps as the product(s) move\nSilicon arrival to product release.\n•\n• Supporting customer issues as required to resolve issues found after product release\nYou Have…\n• 2+ years of experience\n• Electrical Engineering degree with a strong desire to pursue an engineering career in Silicon Design Validation\nKnowledge in High Speed Serdes Interface characterization and protocol compliance testing such as\nPCIe/Ethernet/SDI/CoaXpress/JESD204, MIPI D-PHY, MIPI CSI/DSI-2, USB and DisplayPort/HDMI etc.\n•\n• Knowledge in high speed board design and signal integrity evaluation/debug.\n• Knowledge in Verilog/VHDL and design implementation using FPGA development tools.\n• Knowledge in test automation development using programming languages such as Python, Perl.\n• Knowledge of statistical analysis concepts and use of analysis tools such as JMP, R.\n• Exposure on bench equipment for device characterization such as BERT, VNA, Oscilloscopes, Protocol Exerciser/Analyzers.\n• Exposure on FPGA(emulation/prototyping etc)\n• Strong written and verbal communication skills to work with cross-functional team\n• Self-motivated and proactive with critical thinking.\n• Good problem solving and debugging skills.\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Senior Engineer, Post Silicon Validation", "company": "Lattice", "location": "Pune, India", "date_posted": "2026-09-04", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Pune-India/Senior-Engineer--Post-Silicon-Validation_R-103156-1", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nDo you have a passion for invention and self-challenge? This position gives you an opportunity to learn and participate in one of the most\ncutting-edge projects that Lattice’s Silicon Engineering team has embarked upon to date.\nWe are validating building blocks in FPGA on board level to ensure functionality and performance aspect of Design intent. FPGA consists of\nvarious IPs as a building block such as SERDES(PMA/PCS), Memory DDR(DDR4, LPDDR4, DDR5 etc), DPHY, PLL, DSP, Fabric, I/O etc.\nAs a Silicon Design Validation engineer, you will have an opportunity to learn and train yourself on how to validate one/or many of the building\nblocks within the FPGA. And also, you will be able to acquire knowledge on process/methodology required for validating certain IPs from\nplanning to completion. While you are working on those, you will be exposed to cutting edge equipment and advanced boards as well as\nVarious SW/tools/scripts.\nWhat you’re going to be exposed to and learn:\nThe ideal candidate is highly motivated in developing a career in Silicon Design Validation engineering. You will get significant exposure and\ntraining in the following areas:\nChance to learn FPGA and it’s build block such as SERDES(PMA/PCS), Memory DDR(DDR4, LPDDR4, DDR5 etc), DPHY,\nPLL, DSP, MIPI, Fabric, I/O etc but not limited.\n•\n• Validate and characterize various IPs from silicon arrival to release to production.\n• Develop validation and characterization plans for certain IP, bench hardware and software.\n• Develop test logic RTL to achieve intended validation/characterization test.\nDrive new silicon product bring-up, validation, debug to asses IP functionality/performance. Characterizing data sheet\nparameters. Analyzing the measured data with statistical view. Data sheet preparation etc.\n•\nServe as the central resource with design, verification, manufacturing, test, quality and marketing/apps as the product(s) move\nSilicon arrival to product release.\n•\n• Supporting customer issues as required to resolve issues found after product release\nYou Have…\n• 2+ years of experience\n• Electrical Engineering degree with a strong desire to pursue an engineering career in Silicon Design Validation\nKnowledge in High Speed Serdes Interface characterization and protocol compliance testing such as\nPCIe/Ethernet/SDI/CoaXpress/JESD204, MIPI D-PHY, MIPI CSI/DSI-2, USB and DisplayPort/HDMI etc.\n•\n• Knowledge in high speed board design and signal integrity evaluation/debug.\n• Knowledge in Verilog/VHDL and design implementation using FPGA development tools.\n• Knowledge in test automation development using programming languages such as Python, Perl.\n• Knowledge of statistical analysis concepts and use of analysis tools such as JMP, R.\n• Exposure on bench equipment for device characterization such as BERT, VNA, Oscilloscopes, Protocol Exerciser/Analyzers.\n• Exposure on FPGA(emulation/prototyping etc)\n• Strong written and verbal communication skills to work with cross-functional team\n• Self-motivated and proactive with critical thinking.\n• Good problem solving and debugging skills.\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Senior Staff Signal and Power Integrity Engineer", "company": "Lattice", "location": "Pune, India", "date_posted": "2026-09-04", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Pune-India/Senior-Staff-Signal-and-Power-Integrity-Engineer_R-102903", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nLattice is seeking candidates for the position of Senior Staff Signal and Power Integrity Engineer. This is a full-time position located in India.\nAccountabilities: \nPerform pre-layout and post-layout simulation flow.\nPerforming DC IR drop and AC impedance simulation.\nExecute SI/PI/EMC design-optimization for chip/package/system integration and electrical performance optimization, e.g., eye diagram, jitter, IR/EM, system-PI, cross-talk, and SSN/SSO.\nDevelop system integration design guidelines with SI/PI total solution for advanced packaging technologies (FC/InFO etc).\nCreate simulation models and develop simulation methodology for SI/PI design.\nUse simulation and lab data to support design troubleshooting and propose   corrective actions, drive failure analysis, root cause efforts, and design of experiments to resolve problems.\nExplore various design elements including different modules, memories, low/high speed buses, components, their physics of operation, and impacts on system performance.\nWork closely with package design team and testing team to optimize Package and/or SI design based on the simulation data.\nGenerate simulation report based on the data with clear Package & SI recommendations.\n \nQualifications:\nMust have an MS or PhD in Electrical Engineering.\nQualified candidate must have 10 years or above of recent Signal Integrity experience\nProved experiences on package level signal and power integrity.\nPackage-level system architecture, I/O structures & topologies\nExperience with signal integrity modeling tools, including 3D EM modeling (Ansys HFSS) and simulation (Agilent ADS or similar) software\nExperience with signal and power integrity analysis tools (ex: HSPICE, Sigrity tools, PowerDC etc)\nCommunication skills are a must as this person will interact with engineers in different disciplines as well as with members of management.\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Sr Design Verification Eng", "company": "Lattice", "location": "Pune, India", "date_posted": "2026-09-04", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Pune-India/Sr-Design-Verification-Eng_R-103056", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nInviting candidates with a passion for invention and self-challenge. This position gives you an opportunity to be a part of one of the most cutting edge and key projects that Lattice’s Silicon Engineering team has embarked upon to date. As part of our team, you will have the opportunity to contribute to verifying complex FPGAs. This team will allow you to integrate multiple sophisticated IP level Design and Verification (DV) environments, craft highly reusable best-in-class UVM TB, implement effective coverage driven and directed test cases, deploy new tools and implement methodologies to improve quality of tape-out readiness. By collaborating with other product development teams across Lattice, you can push the industry boundaries of what FPGA systems can do and improve the product experience for our customers across the world! You will be able to learn all aspects of a FPGA, different types of SOC architecture, many highspeed layered protocols, industry’s standard methodologies on low power architecture, best in class DV methodology, verification on accelerated platforms, FW-HW interactions, complexities of FPGA and SOC debug architecture, etc. You'll be at the center of the design verification effort within our silicon design SOC verification team responsible for crafting and productizing state-of-the-art FPGAs. This position requires someone comfortable will all areas of FPGA design verification engineering. Someone that thrives in a dynamic multi-functional organization and is not afraid to take on challenges and solve complex problems using state of the art verification methodologies.\n\nRequired Skills\nBS/MS Electrical Engineering, Computer Science, Computer Systems Engineering, or equivalent degree\nAt least 6+ years DV experience out of which  2+ years as leading a  complex IP verification\nProven track record of working full ASIC verification from concept to tape-out\nAdvanced knowledge of System Verilog and UVM methodology\nHands-on verification experience in verifying IPs like PCIExpress, Ethernet or USB in UVM environment will be big plus.\nHands-on verification experience in verifying IPs using AMBA bus architecture in UVM environment.\nHands-on verification experience in verifying the firmware used for SOC functions\nExposure on working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification.\nAbility to create IP level module and sub-system verification plans, TBs, portable test benches, sequences, verification infrastructure.\nDevelop UVM based highly reusable test benches and integrate complex multi-instance VIPs, sub-system test benches and verification suites at SOC level, and achieve targeted coverage\nWork with design, architecture, SW, FW, and IP delivery teams to efficiently integrate and verify overall FPGA design.\nShould be a great team member with excellent communication and problem-solving skills and the desire to seek diverse challenges.\nLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1000+ strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.\n\n#LI-DNP\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Lead Validation Engineer (UWB)", "company": "NXP", "location": "Bangalore", "date_posted": "2026-09-04", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Lead-Validation-Engineer--UWB-_R-10065591", "is_hardware": true, "platform": "workday", "jd_text": "Job Summary\nWe are seeking an experienced Validation Engineer with expertise in Pre-Silicon and Post-Silicon validation of SoCs/ASICs, extensive knowledge of high-speed and low-speed peripheral interfaces, and strong Embedded Software/Firmware development skills. The ideal candidate will drive validation strategy, test development, debug, silicon bring-up, and product qualification activities from architecture review through production readiness.\n\nJob Qualifications\nBachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field.\n7+ years of experience in Pre-Silicon and Post-Silicon Validation.\nStrong understanding of SoC architecture and subsystem interactions.\nExperience with ARM-based multicore SoCs and embedded systems.\nDeep understanding of hardware-software interaction.\nExperience with lab equipment and protocol analyzers.\nStrong debugging and problem-solving skills.\n\nKey Responsibilities\nReview architecture, micro-architecture, and design specifications for SoC/IP features.\nDevelop validation plans, test strategies, and coverage metrics.\nWork closely with Design, Verification, Firmware, and Architecture teams to ensure feature completeness and quality.\nDevelop and execute validation test plans on FPGA, Emulation, and Silicon platforms.\nDevelop validation plan for stress test scenarios for subsystem and SoC-level\nLead first-silicon bring-up and characterization activities.\nValidate functional correctness and compliance.\nDebug silicon issues using logic analyzers, protocol analyzers, oscilloscopes, SWD, and trace tools.\nRoot cause failures and drive corrective actions with cross-functional teams.\nSupport customer issue resolution and field failure analysis.\nStrong experience validating and debugging for the peripherals QSPI, XSPI, I2S, UART, SPI, I2C/I3C, CAN / CAN-FD, LIN\nPeripheral Compliance and interoperability testing.Throughput-Speed, latency, stress, and error injection testing.\nPHY and controller-level debug.\n\nDevelop Embedded C firmware for silicon validation.\nCreate board bring-up software and diagnostic frameworks.\nDevelop bare-metal, RTOS, based validation applications.\nDriver development and debugging for peripheral interfaces.\nImplement test automation frameworks for silicon validation.\nDevelop scripts using Python, Shell, or Perl for automation and data analysis.\nAnalyze boot flow, initialization sequences, and firmware interactions.\nDebug firmware, hardware, and system-level issues.\n\nMore information about NXP in India...\n\n#LI-7013", "jd_status": "stored"}, {"title": "Senior Engineer -DFT", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-04", "url": "https://careers.arm.com/job/bengaluru/senior-engineer-dft/33099/100158973920", "is_hardware": true, "platform": "talentbrew", "jd_text": "Responsibilities:\nArchitect, implement, and validate innovative DFT techniques on ARM SoCs. Insert DFT logic into SoC style designs at the RTL level and at the Synthesis gate level, validate all features, and generate ATE targeted test patterns to be run on silicon. Work closely with front-end design and verification teams on DFT RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation.\nRequired Skills and Experience :\nCore DFT skills considered for this position should include some of the following: Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics\nExperience ranges from 3- 20 Years.\nExperience coding Verilog RTL, TCL and/or Perl\nProficient in Unix/Linux environments\nBachelors or Master’s degree or equivalent experience in Electronic Engineering, Computer Engineering, or a related field\n“Nice To Have” Skills and Experience :\nFamiliarity with IEEE 1149, 1500, 1687, 1838\nSynthesis & Static Timing Analysis\nFamiliarity with SoC style architectures including multi-clock domain and low power design practices.\nValidated understanding of Siemens DFT tools\nFamiliarity with Arm IP like the following: Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, CoreSight debug\nExperience with 2.5D and 3D test\nAbility to work both collaboratively on a team and independently\nHard-working and excellent time management skills with an ability to multi-task\nAn upbeat demeanor to working on exciting projects on the cutting edge of technology\nExperience with Siemens, Cadence, and/or Synopsys DFT and simulation tools\n \n#LI-BB1\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "DFT Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-04", "url": "https://careers.arm.com/job/bengaluru/dft-engineer/33099/100158931088", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Description:\nArm’s Solutions group DFT team implements DFT for test-chips and hard-macros to prove Arm's soft IP power, performance, area, and functionality within the context of a SoC using the latest DFT techniques and process technologies. We closely collaborate with RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from an early investigation stage all the way through tape-out and silicon test/characterization on ATE.\nResponsibilities:\nArchitect, implement, and validate innovative DFT techniques on test chips as well as hard macros. Insert DFT logic into SoC style designs at the RTL level and at the Synthesis gate level, validate all features, and generate ATE targeted test patterns to be run on silicon. Work closely with front-end design and verification teams on DFT RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation.\nRequired Skills and Experience :\nThis role is for a  DFT Engineer with proven ability of 2 to 5 years  in Design for Test \nExperience coding Verilog RTL, TCL and/or Perl\nProficient in Unix/Linux environments\nCore DFT skills considered for this position should include some of the following: Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics\nBachelors or Master’s degree or equivalent experience in Electronic Engineering, Computer Engineering, or a related field\n“Nice To Have” Skills and Experience :\nFamiliarity with IEEE 1149, 1500, 1687, 1838\nSynthesis & Static Timing Analysis\nFamiliarity with SoC style architectures including multi-clock domain and low power design practices.\nValidated understanding of Siemens DFT tools\nFamiliarity with Arm IP like the following: Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, CoreSight debug\nExperience with 2.5D and 3D test\nAbility to work both collaboratively on a team and independently\nHard-working and excellent time management skills with an ability to multi-task\nAn upbeat demeanor to working on exciting projects on the cutting edge of technology\nExperience with Siemens, Cadence, and/or Synopsys DFT and simulation tools\n \n#LI-BB1\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Program Management Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-04", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25017631", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n Texas Instruments (TI) is looking for an energetic, service minded leader, who enjoys helping others to succeed by providing team members and clients with motivation and support in a positive and professional work environment as a Program Management Engineer. We are seeking a highly motivated individual who will challenge teammates to achieve flawless execution goals, while maintaining strong working relationships. Success in this role is measured by the ability to grow the number of new products and drive the forecasted return on investment.\n\nResponsibilities include:\n\nLead a cross functional team on the execution of releasing new products and ensuring successful return on investment for every development; the team consists of Design, Marketing, Systems& Applications, Validation, Product& Test Engineering, Firmware/Software Engineering, Manufacturing, Field, and Quality\n\nWork with wafer fabrication, assembly& test sites to guarantee schedule, cost and quality\n\nPlan the project using MS Project from Assess Opportunity Phase to Release to Market and is responsible to make sure the project comes in on budget\n\nProvide clear direction to both, team and external support organizations like device fabrication and assembly and test sites\n\nDrive and motivate all team members critical to the flawless execution of each product and project\n\nProvide weekly and monthly updates to senior management on status of projects, explaining the issues facing a project\n\nInteract with customers in support of project status, key milestones, and deliveries. This includes samples deliveries, special work requests, wafer lot starts and reliability tests\n\nPerform product reliability and characterization of integrated circuits to ensure they meet the product requirement specifications and manufacturing requirements\n\nWork with failure analysis (FA) to determine root cause of any reliability and qualification failures\n\nMaintain thorough and up-to-date project schedules with all related milestones\n\nDevelop and implement Qualification plans\n\nCommunicate weekly to management on status of each project\n\nEffectively coordinate material logistics and shipment/assembly/test prioritization\n\nMaintain Galileo system per new product development guidelines\n\nSuccess will be measured by the ability to grow the number of new products and drive the forecasted return on investment.\n\nQualifications\nMinimum requirements:\n\nMasters in Electrical Engineering, Mechanical Engineering or related engineering degree\n\n6+ years of experience with project engineering/management experience on highly complex products/projects\n\nProven leadership capabilities in leading multifaceted global organizations\n\nSuccessful proven track record in indirect management and influence\n\nPreferred qualifications:\n\nAbility to manage multiple projects simultaneously, and set realistic plans based on required tasks with available resources\n\nAbility to effectively coordinate and lead global development teams on projects that include design, silicon fabrications, production test development, qualification and production ramp; Programs will be driven out of multiple global locations\n\nAbility to provide clear direction to both internal teams and external support organizations like device fabrication and assembly sites\n\nKnowledge of device packaging and wafer fabrication process\n\nKnowledge of reliability requirements and tri-temp characterization methodology using statistical analysis\n\nAbility to work in a team environment and understand cross-functional team dynamics\n\nAbility to work with global customers to align project schedules with customers' key milestones\n\nDemonstrated strong analytical and problem solving skills\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nStrong time management skills that enable on-time project delivery\n\nDemonstrated ability to build strong, influential relationships\n\nAbility to work effectively in a fast-paced and rapidly changing environment\n\nAbility to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "HWQA Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-09-04", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/HWQA-Engineer_JR2025032", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is looking for HWQA Engineer who is passionate to drive quality improvements. This essential role will give you an opportunity to collaborate with other test and development teams to build and qualify exceptional products. We value diversity, you will have the opportunity to develop your skillset and build domain expertise (SME) in the areas of SoC Hardware and Software.\n\nWhat you'll be doing:\nDesign, build and implement test cases and Test plans on Pre-Silicon(FPGA), Silicon on engineering Chip validation platforms using Data Center Server OS/ARM Linux.\n\nTest Plans development and validation  include various components of the platform including OS Kernel, CPU, Memory, IO interfaces(C2C ,USB, PCIe,  Ethernet).\n\nDesigning and implementing automated testing frameworks to enhance verification processes, and reliability in our testing pipelines using LLM / Gen AI tools for Stress and Stability testing.\n\nCreate workloads and identify appropriate tools to validate new chip features and functionalities.\n\nWork closely with Multi-functional teams like hardware ASIC, FPGA teams, SW development teams on new requirements, products or features/improvements of existing products, test plans and test methods.\n\nTroubleshoot bugs and provide resolution, you will play a key role in fixing bugs.\n\nWhat we need to see:\nGraduate/Post Graduate in Computer Science/Electronics/Telecommunication\n\nAt least 3+ years of Extensive Test development, execution/Validation experience on pre-silicon and Silicon in area of Embedded/SoC (Android/Linux/WOA) platforms \n\n Strong hands-on experience in Windows on Arm (WOA) and GPU validation, including test planning, execution, debug, and issue closure on SoC/platform bring-up.\n\nSolid understanding of SoC architecture, platform bring-up, and IP-level validation (e.g., USB, display, GPU, LSIO), with the ability to debug issues across HW, FW, and SW.\n\nPractical knowledge of AI/LLM fundamentals and how to apply them to validation — for example, test strategy, log/trace analysis, triage, and test-tool development.\n\nProven ability to use GenAI and LLM tools to optimize test strategies, automate script/harness generation, and improve coverage, cycle time, and debug efficiency.\n\nProven ability to design and develop custom validation tools, test frameworks, and automation infrastructure.\n\nExperience creating workloads and test methodologies to exercise chip features, including stress and stability testing.\n\nHands-on validation experience on key interfaces such as PCIe, USB3, CPU, and memory, or equivalent SoC/platform interfaces.\n\nStrong knowledge of Linux kernel, bootloader, device-driver, and firmware testing, along with virtualization concepts and multicore/multiprocessing fundamentals.\n\nWays to stand out from the crowd:\nLLM, GenAI Experience (tools like Cursor / Codex etc)\n\nGPU validation experience\n\nExperience in using an Analyzer/Oscilloscope\n\nShow previous experience with IP-level test plan and test cases development with Embedded / Chipset / Data Center - Server Platforms.\n\nProven track record of delivering complex projects and automation solutions — from planning through execution — with tangible, production-ready outcomes.\n\n  \nIntelligent machines powered by Artificial Intelligence computers that can learn, reason and interact with people are no longer science fiction. GPU Deep Learning has provided the foundation for machines to learn, perceive, reason and solve problems. Now, NVIDIA’s GPU runs Deep Learning algorithms, simulating human intelligence, and acts as the brain of computers, robots and self-driving cars that can perceive and understand the world. Come be a part of this exciting world, at NVIDIA.\n\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.", "jd_status": "stored"}, {"title": "Staff Engineer, Design Verification Engineering", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-09-04", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Staff-Engineer--Design-Verification-Engineering_R261840", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nJob Description\n\nAnalog Devices is seeking Digital Design Staff verification Engineer, who will be responsible for design verification of highly integrated solutions and products in a multifunctional team. You will be working on driving real revenue growth on the next generation of Intelligence at the Edge products across multiple products and business units.\n\nAbout ADI:\nAnalog Devices, Inc. is a leading global high-performance analog technology company dedicated to solving our customers' most complex engineering challenges. We play a critical role at the intersection of the physical and digital world by providing the building blocks to sense, measure, interpret, connect, and power devices and systems. We design, manufacture, test, and market a broad portfolio of solutions, including integrated circuits (ICs), software and subsystems that leverage high-performance analog, mixed-signal and digital signal processing technologies. We embrace a culture of innovation and collaboration to push the state of the art.\n\nAbout the Role\nKey member of design verification team  for SOC or subsystem design pre silicon verification.  The candidate will be responsible for formulating verification strategies, Define verification architecture, Flow, Methodology and leading, driving and completing verification of large integrated products. As a senior team member, it is expected that he/she will lead and influence verification methodologies within both DBU and ADI.   The candidate is also encouraged to participate in cross company technical initiatives as well as patent and publish work where possible.\n\nResponsibilities\nLead pre-silicon verification for complex SoC or subsystem designs, driving execution from planning to closure.\n\nVerify microprocessor-based systems, AI/ML accelerators, and high-speed peripherals using advanced methodologies.\n\nArchitect and implement UVM-based testbenches, DV flows, and scalable verification methodologies.\n\nDefine and execute test plans; drive functional and code coverage closure in collaboration with design teams.\n\nWork cross-functionally with emulation, FPGA, and firmware teams to ensure end-to-end system correctness.\n\nApply formal verification techniques for IP and subsystem-level validation.\n\nLead NoC/interconnect verification and ensure robust data flow across the system.\n\nPerform system-level use case validation, including performance verification and analysis.\n\nDevelop and validate end-to-end scenarios to ensure real-world functionality.\n\nDrive innovative verification strategies to meet quality and schedule goals.\n\nDefine overall verification strategy based on product requirements and design specifications, leveraging modern techniques such as formal, emulation, portable stimulus, and virtual platforms.\n\nRequirements\nB.Tech/M.Tech with 8+ years of experience in digital pre-silicon verification.\n\nStrong understanding of SoC/subsystem architectures with hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development and debugging.\n\nProven experience in verification closure using functional and code coverage metrics at block and subsystem levels.\n\nExpertise in NoC, bus, and interconnect verification, including coverage analysis and optimization.\n\nExperience in architecting testbench environments and implementing scalable DV flows and methodologies.\n\nHands-on experience in power-aware verification using UPF, including power analysis and optimization.\n\nExposure to formal verification, including flow setup, connectivity, and functional checks.\n\nFamiliarity with gate-level simulations (GLS) with timing annotation.\n\nStrong knowledge of test planning, constrained-random verification, assertions, and transaction-level modeling using SystemVerilog.\n\nUnderstanding of processor-based systems (ARM, RISC-V, Tensilica), AI/ML or GPU-based architectures is a plus.\n\nProficiency in C/C++, SystemC, and scripting (Python/TCL/Shell).\n\nExcellent communication and collaboration skills with the ability to work across global teams.\n\nStrong problem-solving ability with a mindset to quickly learn and adopt new technologies.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Staff Engineer, Design Verification Engineering", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-09-04", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Staff-Engineer--Design-Verification-Engineering_R261728-1", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nAnalog Devices is seeking Digital Design Staff verification Engineer, who will be responsible for design verification of highly integrated solutions and products in a multifunctional team. You will be working on driving real revenue growth on the next generation of Intelligence at the Edge products across multiple products and business units.\n\nAbout ADI:\nAnalog Devices, Inc. is a leading global high-performance analog technology company dedicated to solving our customers' most complex engineering challenges. We play a critical role at the intersection of the physical and digital world by providing the building blocks to sense, measure, interpret, connect, and power devices and systems. We design, manufacture, test, and market a broad portfolio of solutions, including integrated circuits (ICs), software and subsystems that leverage high-performance analog, mixed-signal and digital signal processing technologies. We embrace a culture of innovation and collaboration to push the state of the art.\n\nAbout the Role\nKey member of design verification team  for SOC or subsystem design pre silicon verification.  The candidate will be responsible for formulating verification strategies, Define verification architecture, Flow, Methodology and leading, driving and completing verification of large integrated products. As a senior team member, it is expected that he/she will lead and influence verification methodologies within both DBU and ADI.   The candidate is also encouraged to participate in cross company technical initiatives as well as patent and publish work where possible.\n\nResponsibilities\nLead pre-silicon verification for complex SoC or subsystem designs, driving execution from planning to closure.\nVerify microprocessor-based systems, AI/ML accelerators, and high-speed peripherals using advanced methodologies.\nArchitect and implement UVM-based testbenches, DV flows, and scalable verification methodologies.\nDefine and execute test plans; drive functional and code coverage closure in collaboration with design teams.\nWork cross-functionally with emulation, FPGA, and firmware teams to ensure end-to-end system correctness.\nApply formal verification techniques for IP and subsystem-level validation.\nLead NoC/interconnect verification and ensure robust data flow across the system.\nPerform system-level use case validation, including performance verification and analysis.\nDevelop and validate end-to-end scenarios to ensure real-world functionality.\nDrive innovative verification strategies to meet quality and schedule goals.\nDefine overall verification strategy based on product requirements and design specifications, leveraging modern techniques such as formal, emulation, portable stimulus, and virtual platforms.\n\nRequirements\nB.Tech/M.Tech with 8+ years of experience in digital pre-silicon verification.\nStrong understanding of SoC/subsystem architectures with hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development and debugging.\nProven experience in verification closure using functional and code coverage metrics at block and subsystem levels.\nExpertise in NoC, bus, and interconnect verification, including coverage analysis and optimization.\nExperience in architecting testbench environments and implementing scalable DV flows and methodologies.\nHands-on experience in power-aware verification using UPF, including power analysis and optimization.\nExposure to formal verification, including flow setup, connectivity, and functional checks.\nFamiliarity with gate-level simulations (GLS) with timing annotation.\nStrong knowledge of test planning, constrained-random verification, assertions, and transaction-level modeling using SystemVerilog.\nUnderstanding of processor-based systems (ARM, RISC-V, Tensilica), AI/ML or GPU-based architectures is a plus.\nProficiency in C/C++, SystemC, and scripting (Python/TCL/Shell).\nExcellent communication and collaboration skills with the ability to work across global teams.\nStrong problem-solving ability with a mindset to quickly learn and adopt new technologies.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Staff Engineer, Design Verification Engineering", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-09-04", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Staff-Engineer--Design-Verification-Engineering_R262741-1", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nStaff Design Verification Engineer\n\nAbout the Role\nAs a Staff Design Verification Engineer at Analog Devices, you will provide technical leadership in developing verification strategies for our most complex analog and mixed-signal designs. You'll architect sophisticated verification environments, mentor junior engineers, and collaborate across organizational boundaries to ensure product quality and reliability.\nWorking with limited direction, you'll apply your deep technical expertise to solve critical verification challenges while representing ADI in interactions with key customers and industry partners. This senior position involves significant influence on verification methodology adoption and technical decisions that impact crucial organizational objectives.\n\nKey Responsibilities\nStrategic Leadership: Architect and lead verification strategy for complex digital and mixed-signal designs, acting as a key contributor in critical verification environments\nVerification Architecture: Design and implement sophisticated UVM-based verification environments that ensure comprehensive test coverage and design quality\nTechnical Mentorship: Guide and develop junior engineers, serving as a resource for colleagues with less experience while modeling professional behaviors\nCross-Functional Direction: Coordinate work across organizational lines, collaborating with design teams on verification requirements and sign-off criteria\nProblem Resolution: Lead complex debugging efforts across RTL and gate-level simulations with minimal direction, developing resolutions that require in-depth analysis\nCoverage Closure: Drive functional and code coverage closure using advanced verification methodologies to ensure design accuracy\nPost-Silicon Support: Lead post-silicon validation activities, contributing expertise to address critical issues\nCustomer Representation: Serve as principal customer contact on projects, representing ADI's technical excellence and customer commitment\n\nMust Have Skills\nSystemVerilog and UVM Expertise: Expert-level knowledge of SystemVerilog and Universal Verification Methodology for architecting advanced verification environments for complex designs\nTest Planning and Strategy: Demonstrated ability to develop comprehensive verification plans that drive coverage-driven methodologies and verification closure\nMixed-Signal Verification: Deep understanding of mixed-signal design principles and verification methodologies, with experience implementing sophisticated verification approaches\nDebugging Mastery: Advanced debugging skills across multiple design abstractions, with proven ability to resolve complex verification issues with minimal direction\nEDA Tool Proficiency: Extensive experience with electronic design automation tools (Cadence/Synopsys) and formal verification techniques\nScripting and Automation: Advanced proficiency in Python, Perl, TCL, or Shell scripting for creating sophisticated verification automation frameworks\nTechnical Leadership: Demonstrated ability to influence verification direction, mentor junior engineers, and drive methodology adoption across teams\n\nPreferred Education and Experience\nMS/PhD in Electrical Engineering, Computer Engineering, or related field\n7-10+ years of relevant digital design verification experience, with particular emphasis on mixed-signal verification\n\nWhy You'll Love Working Here\nAt Analog Devices, you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on professional growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world.\nYour expertise will shape the future of technology, and you'll be supported by a culture that values continuous advancement and professional growth. Join us and help create the technologies that bridge the physical and digital worlds, making a tangible difference in how people live, work, and connect.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Senior ASIC Engineer, Switch SoC", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-09-04", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-ASIC-Engineer--Switch-SoC_JR2023108-1", "is_hardware": true, "platform": "workday", "jd_text": "We are currently seeking an expert SOC Design and Integration Engineer with strong design fundamentals to work in Switch Silicon group. You'll join a group of hardworking engineers to craft and implement the next generation innovative Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing best high-speed communication devices, delivering the highest throughput and lowest latency!\n \nThe Networking Chip Design team in India is a new team which is growing at a fast pace.\n \nWhat you'll be doing:\nYou are encouraged to understand all features of a given project and define project milestones based on internal roadmaps, assign them and track them through agile framework\n\nDefine and develop system-level methodologies, tools, and IPs to build SOCs in an efficient and scalable manner.\n\nWork on SOC Assembly and drive cross-functional teams towards SOC milestone execution.\n\nBe responsible for integrating all the pieces for a given defined project milestone and deliver the model to relevant teams for further verification at cluster/sub-system/SOC/emulation levels.\n\nHave good grasp of Perl, Python, or other industry-standard scripting languages.\n\n \nWhat we need to see:\nBS (or equivalent experience) / MS with 4+ years of practical semiconductor design and architecture experience building complex SoC’s.\n\nMust have firsthand experience & solid understanding of all phases of SOC development in multiple ASIC projects including ASIC architecture, Micro-Architecture, RTL design, verification, timing closure & Physical design.\n\nExposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.).\n\nC/C++ programming or python or any other industry-standard scripting language experience desirable.\n\nExperience working with software teams to tightly define the HW/SW interface including control/status registers, interrupt and error handling.\n\nHands on experience in successful tape outs of multiple complex, high-volume SoCs in advanced process nodes.\n\nExposure to various Chip Design Functions to be able to collaborate and solve complex cross functional problems.\n\nExcellent verbal and written communication skills to interact with cross functional teams to build consensus.\n\nGood teamwork spirit and collaboration skills with team members.\n\nExperience in synthesis, physical design and DFT is a plus.\n\nBackground in RTL Build and Design Automation is a plus.\n\n \nWays to stand out from the crowd:\nChip lead type of technical leadership experience on delivering complex SOCs for enterprise and/or HPC applications.\n\nExperience in RTL coding and debug, as well as performance/power/area analysis and trade-offs\n\nExperience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area.\n\nStrong coding skills in Perl, Python, or other industry-standard scripting languages.\n\n \nWidely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/\n \nNVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "ASIC Verification Engineer - Clocks", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-09-04", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/ASIC-Verification-Engineer---Clocks_JR2024826", "is_hardware": true, "platform": "workday", "jd_text": "The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification. The NVIDIA Clocks Team is committed to deliver high-quality clocking and reset logic to various units in SOC automotive and datacenter ASICs. The complexity of the clocks and resets design has increased many folds. This requires sophisticated verification to deliver a bug free clocks/resets design to power our product lines ranging from Data Centers, Consumer graphics to Self-driving cars and the growing field of artificial intelligence. Modern clocking verification solutions need to be innovative, ensure quality in covering the complex design specifications and balance the constraints on infrastructure, re-usability, testing speed and multi-platform support.\n\nWhat you'll be doing:\nOwn validation of Clocking structures in Tegra automotive and datacenter products from start to finish, including test plan development, automation, validation flows development, coverage metrics, test execution, bug identification/fix and productization.\n\nTackle Sophisticated problems and develop a scalable solution that works across platform.\n\nHands on industry-standard tools and state of the art verification methodologies. This includes coding in System Verilog, UVM, C++, Perl, Python and NVIDIA custom compilers and tools.\n\nPartnering closely with our clocks/reset architecture and design team to validate our clocks/reset design.  \n\nCoordinate with internal and external teams across time zones.\n\nWhat we need to see:\nBS or MS in EE/ECE or equivalent experience.\n\n2+ years of relevant industry work experience.\n\nGood understanding of Logic Design and Architecture.\n\nExpertise in industry-standard verification flows like SV constraint random verification, UVM, Formal Verification, Coverage metrics, profiling tools, X prop, etc.\n\nExposure on block level and system-level verification.\n\nStrong coding skills in System Verilog, scripting languages (Perl/python) and C++.\n\nAbility to collaborate and work with multiple groups.\n\nPrior experience in implementing Test plans for pre-silicon platforms.\n\nUnderstanding of DFT/IST is optional.\n\nWe have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our world-class engineering teams are growing fast. If you are creative, curious, and motivated with real passion for technology, we want to hear from you!\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior Standard Cell and IP Application Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-04", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Senior-Standard-Cell-and-IP-Application-Engineer_JR0285361", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nWe are looking for a Senior FIP Enablement and Support Engineer to join the Intel Foundry / DTP Customer Engineering team. The successful candidate brings deep expertise in Foundational IP (Standard Cell Libraries, GPIOs, PLLs, and Analog/Mixed-Signal IPs) and a strong understanding of IP QA, packaging, and release processes across Synopsys and Cadence design flows.\nIn this role, the engineer will own customer-facing release delivery for Foundational IP, partner with FIP development teams on quality and integration, and serve as a key technical interface for Intel Foundry Services (IFS) ecosystem customers. The role requires sound technical judgment, the ability to navigate ambiguity, and the capacity to drive initiatives independently across multiple stakeholders and organizations.\nThe candidate will work in close collaboration with Foundry Services teams, ecosystem partners, FIP development teams, and cross-org stakeholders across IPG, IFA, CDA, ADG, and PESG to deliver winning solutions for internal and external customers.\n\nPrimary Responsibilities\n•\tPackage, validate, and release high-volume Foundational IP collateral (Standard Cell libraries, PDK content, GPIOs, PLLs) to IP delivery portals and PLM systems including IPX, UCM, Teamcenter, and FLPR, meeting customer commit dates and quality targets.\n•\tDrive end-to-end release execution for assigned IP families, including QA monitoring, packaging throughput, and adherence to SDLC/SDL certification requirements and Intel IP governance standards.\n•\tServe as the primary technical point of contact to internal and external customers for technical analysis, debug, and integration support; liaise with FIP development teams to drive resolution of quality and integration issues.\n•\tCoordinate with Technical Program Managers (TPMs) and customer engineering leads on external release communication, customer-facing documentation, and release notes.\n•\tReview IP performance and quality to ensure conformance with desired standards and targets; contribute to the development of QA flows, verification methodology, and release automation.\n•\tDrive continuous improvement in packaging throughput, release tooling, and customer support workflows (e.g., Jira / JSM-based intake and triage).\n•\tDevelop customer-facing collateral, including application notes, white papers, integration guides, and other supporting documentation to improve customer experience and reduce support load.\n•\tMentor junior engineers and contribute to team-wide best practices in IP release and customer support.\n\nQualifications:\nMinimum Qualifications:\n• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, with 4+ years of relevant industry experience, OR\n• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, with 3+ years of relevant industry experience.\n\nPreferred Qualifications:\n• Demonstrated experience in IP Quality Assessment, IP Release processes, and Technical Customer Support using industry-standard tools and methodologies.\n• Technical background in IC design, verification, QA, and IP release for advanced process nodes.\n• Hands-on experience with Standard Cell Libraries, Analog/Mixed-Signal IPs (PLLs, GPIOs), and library characterization and QA flows.\n• Familiarity with foundry PDK release flows and IP Lifecycle Management (PLM) systems such as Teamcenter and Carbon.\n• Working knowledge of Synopsys and Cadence design and characterization tools used in standard cell and analog IP flows.\n• Experience supporting external foundry customers in an IFS-like ecosystem model is a strong plus.\n\nRequirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Signal and Power Integrity Engineer ", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-03T11:05:19.844000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000147220889-signal-and-power-integrity-engineer-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Role Overview\nWe are seeking a highly skilled Signal and Power Integrity Engineer to support the design, analysis, and validation of high‑speed package and board designs. The ideal candidate will have strong fundamentals in electromagnetics and high‑speed signalling, hands‑on experience with industry‑standard simulation tools, and an ability to collaborate across silicon and systems teams to deliver robust, manufacturable products.\nKey Responsibilities\nPerform signal integrity (SI) and power integrity (PI) analysis for high‑speed package, PCB and system level designs.\nConduct 2D and 3D EM simulations to evaluate interconnect performance to mitigate crosstalk, impedance, and loss.\nAnalyse and optimize power distribution networks (PDN) including power plane design, decoupling strategies, and IR drop analysis.\nExecute frequency‑domain and time‑domain simulations for high‑speed interfaces.\nPerform channel simulations and system‑level analysis using tools such as ADS and HSpice.\nSupport design reviews, layout guidance, and ECO cycles with SI/PI recommendations.\nWork with validation teams to correlate simulation results with lab measurements and debug signal and power integrity issues.\nDevelop and maintain technical documentation, reports, and presentations.\nCollaborate closely with PCB layout, hardware, packaging, and validation teams.\n\nStrong fundamentals in electromagnetics, transmission lines, and microwave theory.\nHands‑on experience with EM simulation tools such as: ANSYS HFSS, SI-Wave, Cadence Power-SI.\nExperience with circuit analysis and simulation tools: ADS, HSpice. Proficiency in handling and analysing IBIS/Spice models.\nExperience in power plane modelling and analysis using tools such as Power-SI, Power DC or SI-wave.\nWorking knowledge of package and PCB technologies including stack‑up analysis, DFM, material behaviour etc.\nSolid understanding of high‑speed signalling in both time and frequency domains.\nNice to have: hands‑on experience with lab measurement equipment including VNA, oscilloscopes, TDR and spectrum analysers.\nExperience in test case development and automation using scripting languages (Python, MATLAB, or similar).\nStrong communication, presentation, and documentation skills with the ability to work effectively in a team environment.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "PD IREM LEAD", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-03T10:50:00+00:00", "url": "https://global-external-amd.icims.com/jobs/86981/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. 🔹 THE ROLE As a PHY‑V Lead, you will own physical verification sign-off, full-chip integration, and packaging interface (RDL) planning for advanced SoC programs. You will drive DRC/LVS clean tapeouts, integration quality, and sign-off predictability across complex multi-IP designs. This role requires strong expertise in physical verification, top-level integration, and advanced packaging alignment, along with the ability to lead cross-functional execution across PD, Analog, and Packaging teams. 🔹 THE PERSON Strong technical leader with deep PD + Physical Verification understanding Proven ownership of sign-off closure for complex SoCs Ability to drive execution across multiple teams and dependencies Detail-oriented with focus on quality, manufacturability, and schedule predictability Comfortable operating in high-pressure tapeout environments 🔹 KEY RESPONSIBILITIES ✅ Physical Verification & Sign-off Ownership Drive end-to-end DRC, LVS, ERC, antenna closure at block and full-chip level Define and enforce sign-off methodology and quality criteria Own foundry rule decks, waivers, and risk assessments Deliver sign-off clean GDS for tapeout ✅ SoC / Full-Chip Integration Lead top-level integration of IPs/macros into SoC Own: GDS assembly Hierarchical LVS reconciliation Resolve: Boundary issues Connectivity mismatches Integration conflicts Ensure robust integration across internal and third-party IPs ✅ RDL & Packaging Integration Drive RDL planning and bump mapping strategy Define IO escape routing and die–package interface Collaborate with Packaging, SI/PI, and system teams Enable flip-chip / 2.5D / 3D integration readiness ✅ Tapeout Execution & Tracking Own sign-off checklist, closure tracking, and tapeout readiness Lead tapeout reviews and milestone tracking Drive cross-team closure to meet schedule and quality targets ✅ Methodology & Flow Development Define and improve physical verification flows (Calibre/ICV/Pegasus) Drive: Automation (TCL/Python) Runtime optimization Debug efficiency Establish best practices for hierarchical and incremental sign-off ✅ Debug & Issue Resolution Lead debug of: Complex DRC violations LVS mismatches (shorts/opens/connectivity issues) Drive closure with PD/layout teams Minimize waivers and ensure risk-managed sign-off ✅ Leadership & Collaboration Lead and mentor PHY‑V engineers Act as primary escalation point for sign-off issues Interface with: PD / PnR teams Analog/layout teams Packaging and foundry teams 🔹 REQUIRED QUALIFICATIONS B.Tech / M.Tech in Electronics / Electrical Engineering 10–15+ years in Physical Design / Physical Verification / SoC Integration Strong expertise in: DRC, LVS, ERC, antenna checks Tools: Calibre / ICV / Pegasus Solid understanding of: Full PD flow (RTL → GDS → sign-off) Advanced process nodes (7nm and below) 🔹 PREFERRED QUALIFICATIONS Experience in: Full-chip SoC integration and GDS assembly RDL planning and advanced packaging flows Exposure to: IR/EM, SI/PI, PEX, reliability checks Chiplet / 2.5D / 3D-IC methodologies Strong scripting (TCL/Python) for automation #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Staff DFT Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-03T10:12:30.343000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000147210469-senior-staff-dft-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "About the team:\nRenesas Electronics Americas (REA) is a dynamic, multi-cultural tech company where employees can learn, mentor and thrive. REA brings together the strong financial foundation of a multi-billion dollar global operation and the flexibility and velocity of a smaller organization. We are developing technologies for the latest advances in mobile computing, secured connected devices, autonomous driving, smart homes and factories and more. Our solutions are at the heart of products developed by the major innovators around the world. Join us and be part of what’s next in electronics.\nThis is an opportunity to join a top-notch Mobile Power IC (PMIC) Design Team within Renesas Electronics America’s leading power management product line. As part of one of Renesas’s most prominent Battery and Power Solutions Design Groups, this Engineer will work on next-generation IC products for multiple fast paced consumer power products.\nWhat we need:\nThe Design team is seeking a Sr. Staff DFT  Design Engineer who is technically savvy and is excited about working on cutting edge power solutions for Mobile Application Processors. You will support all design flow tasks and be the champion in managing our processes and systems, interfacing with multiple departments and external customers.  Given the wide range of responsibility, we’re looking for someone eager to learn, ready to hit the ground running, and help define what Design means for Renesas. This opportunity will allow you to open pathways to by having a greater level of responsibility in the team and across Renesas. If you like problem-solving, building something from the ground up, and challenging the status quo, we’d like to hear from you.\nJob Description:\nDefine and document the comprehensive DFT architecture for multi-core SoCs, including strategies for hierarchical scan compression, Memory BIST (MBIST) for huge memory instances, Functional BISTs, Analog components, Logic BIST, high-speed I/O loopback, and JTAG/IEEE 1149.1/1500/1687/1838 networks.\nImplementation & Verification: Lead the integration of digital subsystems, perform scan insertion, and generate ATPG (Automatic Test Pattern Generation) patterns while ensuring high fault coverage.\nA proven track record in the fields belowDigital DFT of large and small designs: Scan, MBIST, DFT insertion and ATPG\nExperience with leading DFT/ATPG tools (Synopsys, Mentor)\n\nExperience and a good understanding in these fields is desirableFunctional Safety incl. Logic BIST\nATE and test engineering of mixed-signal ICs\nNon-volatile memory (Flash, MRAM, ReRAM)\nMixed-signal design (power management, audio, RF)\n\nExposure to production test related engineering challenges (yield improvement)\nCommand of verbal and written English, ability to use it in a convincing manner for communicating technical concepts\nAbility to assert self while maintaining a cooperative environment within the design team.\nProven ability to lead cross-functional teams and deliver results in a fast-paced, high-complexity environment\nHands-on experience with industry-standard EDA tools (e.g., Synopsys TestMAX, Mentor Tessent)\nStrong understanding of SoC/MCU architecture and digital design flows\nDFT insertion (and generation of test patterns (ATPG)\nVerification of test modes and test patterns prior tapeout\nValidation and debug of test modes and test patterns in the lab or on ATE\nDiagnose fail devices, support PFA.\nWork with Product, Test, and Applications Engineering to complete product release\n \n\nSkills You’ll Need\nB.A./B.S. in engineering, engineering management, or engineering operations required\nBSc/BEng in Electrical or Electronic engineering, MS or PhD preferred\nMinimum of 8 years industry experience with BS working in DFT digital or mixed signal IC design\nExperience in DFT protocols including Scan Compression, MBIST, LBIST, JTAG (IEEE 1149.1), and iJTAG (IEEE 1687).\nDFT insertion\nTest coverage, test application time\nDebug effort required by test engineer to reach milestone of patterns running\nFirst time right success rate\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, or national origin.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "FCT PD lead", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-03T08:17:00+00:00", "url": "https://global-external-amd.icims.com/jobs/91601/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. FCT LEAD THE ROLE: As an FCT Lead within the Physical Design organisation, you will lead Full Chip Timing (FCT) execution and timing signoff activities for complex SoC and subsystem designs. You will work closely with Architecture, Design, PD, STA, DFT, CAD and Methodology teams to achieve first-pass silicon success and deliver timing closure for industry-leading products THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Lead the Full Chip Timing team responsible for timing constraints development and timing signoff. Own end-to-end timing closure and signoff for SoC and subsystem integration projects. Define, develop and validate SDC constraints, clocks and timing methodologies. Drive timing convergence across synthesis, P&R, CTS, route and post-route ECO stages. Partner with Architecture and STA teams to establish timing budgets, statistical timing targets and signoff criteria. Analyze and manage advanced-node timing margins including LVF, SSTA, OCV/AOCV/POCV and variation-aware signoff methodologies. Lead timing ECO planning and execution to ensure on-time tapeout. Collaborate with CAD and EDA vendors to improve timing closure flows, automation and methodologies. Mentor engineers and provide technical leadership for timing closure activities across multiple projects. PREFERRED EXPERIENCE: 14+ years of experience in Physical Design, Static Timing Analysis, Constraints Development and Timing Signoff. Strong expertise in: Full Chip Timing Closure STA Signoff Timing Constraints (SDC) Timing ECO Methodologies Advanced Node Timing Signoff Clock Architecture and Clock Implementation MCMM Timing Analysis DFT Timing and MBIST Timing Verification Hands-on experience with Synopsys PrimeTime (PT) and GCA. Experience with Fusion Compiler and/or ICC2 is highly desirable. Strong understanding of floorplanning, placement, CTS and routing interactions with timing. Proficiency in Tcl, Perl, Shell and Python scripting Leadership Expectations Provide technical leadership for Full Chip Timing execution across multiple programs. Drive cross-functional alignment among Architecture, Design, PD, DFT and CAD teams. Mentor MTS/SDE engineers and develop future FCT leads. Influence timing methodologies and signoff strategies for upcoming technology nodes. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Lead Sr/Staff Engineer (HW board design)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-03T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720867357", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nDesign and develop motherboards/add in cards/modules for Qualcomm new AI System On Chip (SoC)/System In Package (SIP). Primary responsibilities include working with cross functional teams (mechanical, thermal, SI, PTE, regulatory, validation, manufacturing, etc.) for execution of projects from concept to production. Support rack level design and integration of cards, servers and networking switches.\n\nPrincipal Duties and Responsibilities:\n· Develops basic features and components of hardware designs in line with product proposals or roadmaps, under the supervision of more experienced engineers.\n· Applies basic design rules and processes for electronic hardware, equipment, and/or integrated circuitry with minimal supervision from more experienced engineers.\n· Reads device specification sheets and interprets basic details required to design various hardware features with minimal guidance from more experienced engineers.\n· Evaluates devices and documents performance over various operating conditions and configurations.\n· Assists in the assessment of common design features to identify potential flaws (e.g., electrical, mechanical, hardware), compatibility issues, and/or compliance issues under the supervision of more experienced engineers.\n· Documents basic details about materials, components, chipsets, and assemblies for a device, and records important changes to design with minimal supervision from more experienced engineers.\n· Troubleshoots basic issues with product designs.\n· Provides reasonable schedule for own tasks to project lead.\n· Develops understanding of Qualcomm products.\n· Work with ODM on joint design, address technical issues and support mass production\n· Seeks basic knowledge of industry trends, competitor products, and advances in various engineering fields from publicly available information; requires minimal consultation with more experienced engineers to understand and apply advanced concepts.\n\nREQUIRED EXPERIENCE:\n· System/card/rack-level development, including architecture, design, validation, and deployment of enterprise-class hardware platforms. Strengths in any of the following areas:\n\nRack-Level Expertise:\n· Proven experience in rack-level system integration, including chassis, backplane, cabling, airflow, and thermal management across multiple cards/modules.\n· Familiarity with rack-scale power delivery, including PDUs, VRMs, PMICs, and power budgeting across multiple boards.\n· Experience with rack-level diagnostics and bring-up, including debug of interconnects, signal integrity across long traces/cables, and system-level validation.\n· Understanding of rack-level mechanical constraints, EMI shielding, and compliance with data center deployment standards.\n· Collaboration with ODMs/OEMs on rack-level design and manufacturing, including review of mechanical drawings, thermal simulations, and compliance testing.\nBoard-Level Design:\n· Deep knowledge of PCIe cards, motherboards, daughtercards, and backplane signal and power delivery.\n· Expertise in chassis design, airflow optimization, and thermal management.\n· Solid understanding of system software operation from bootloader to OS and application layers.\nComponent Qualification:\n· Experience qualifying PMICs, voltage regulators (VRs), clock buffers, flash memory, and connectors for use in complex card and rack-level designs.\nDesign & Validation:\n· Hands-on experience in dense, high-layer count PCB designs (8–20+ layers).\n· Skilled in PCIe add-in card/module design, debugging in high-performance systems (x86 and ARM).\n· Familiarity with JTAG tools for bring-up and debug.\n· Experience with networking switches and high speed ethernet interfaces\nHigh-Speed Interfaces:\n· Knowledge of high-speed serial I/O (6–10+ Gbps), PCIe Gen5/6, LPDDR4x/5x, DDR4/5, 200/400/800 GbE.\n· Experience with long PCB/cable topologies (0.35–1.5 meter), signal integrity, and compliance with current standards.\n· Ability to debug at packet/protocol level across link, transport, transaction, and command layers.\nMemory & Clocking:\n· Experience with LPDDR4x memory technologies, DIMM layout and validation.\n· Expertise in clock distribution, power distribution, SMBus, PMBus, SPI, PWM/Tach, and BMC integration.\nTools & Collaboration:\n· Proficient in schematic capture and PCB layout tools (Cadence Allegro, Mentor Expedition).\n· Experience with circuit simulation tools (SPICE), signal/power integrity analysis.\n· Skilled in using lab equipment: oscilloscopes, logic analyzers, JTAG, SMBus, serial debuggers.\n· Strong collaboration with ODMs on joint designs, schematic/layout reviews, and compliance to Qualcomm design guidelines.\n\nFirmware & Software:\n· Good understanding of x86 FW/SW stack and firmware architecture.\n· Experience with BMC hardware/software integration and management.\nCompliance & Testing:\n· Familiarity with regulatory, environmental, and compliance testing for rack-level systems.\n\nPREFERRED QUALIFICATIONS:\n· 5 to 12 years hardware engineering/Systems development experience or related work experience.\n· 5 to 12 years of experience with circuit design (e.g., digital, analog, RF).\n· 5 to 12 years of experience utilizing schematic capture and circuit simulation software.\n· 5 to 12 years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, debug tools, etc.\n\nMinimum Qualifications:\n• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5 to 12 years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.\n\nMinimum Experience:\n•5 to 12 years of experience in HW board design and System design\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Serdes PHY Analog Design Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-03T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720923947", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nJob Function\nBDC SerDes Mixed-Signal design team is actively looking for experienced (8+ years) analog circuit designers to work on high speed SerDes PHYs. You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. \n\nResponsibilities\nHands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO, high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc.\nAnalog and or Digital PLLs for frequency synthesis and/or SerDes applications  Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. \nPLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) \n\nAbility to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up.\nWork closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY.\n\nSkills & Experience\nFor lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc.\nUnderstanding of advance Finfet process effects on designs and layout is required.\nExperience in using SPICE simulators, adexl & virtuoso.\nExperience with post-Si bring-up and debug is must.\nGood understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added advantage.\nMaster/Bachelor in Electronics\nShell/Perl-python scripting to automate circuit design and verification work.\nAble to work with teams across the globe and possess good communication and presentation skills.\n\nPreferred  \nMixed signal design experience  \n\nKeywords\nAnalog circuit Design, Rx, Tx, PLL, SerDes, PHY, Serializer, Deserializer, VCO, High-speed Trans receiver\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SerDes PHY Analog Design Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-03T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720923936", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nRole Overview\nBDC SerDes Mixed-Signal Design team is looking for experienced analog circuit designers with 4–12+ years of experience to work on high-speed SerDes PHYs. The role involves delivering next-generation PHY designs for SoCs and contributing to architecture analysis and circuit implementation in leading-edge FinFET and advanced technology nodes. The team focuses on low-power, high-performance analog designs for Qualcomm’s wireless and compute products.\nKey Responsibilities\n-Own hands-on analog circuit design for high-speed SerDes PHY blocks, High-speed TX/RX, Equalizers, Samplers, Phase interpolators, Serializer/De-serializer, Biases, and reference circuits, LDO etc.\n-Design analog and/or digital PLLs for frequency synthesis and SerDes applications, including charge pumps, loop filters, VCO/DCO, PFD/TDC, and high-speed dividers.\n-Take designs from schematic through post-layout verification, integration sign-off, and post-silicon bring-up.\n-Collaborate closely with RTL, digital design, physical design, design verification, and SoC verification teams to integrate and validate the PHY.\nRequired Qualifications\n-4–12+ years of experience in analog or mixed-signal circuit design.\n-Strong understanding of advanced FinFET process effects on analog design and layout.\n-Experience with SPICE simulators, ADE XL, and Virtuoso.\n-Hands-on experience with post-silicon bring-up and debug.\n-Bachelor’s or master’s degree in Electronics, Electrical Engineering, or a related discipline.\n-Ability to work effectively with global teams, with strong communication and presentation skills.\nPreferred Qualifications\n-Experience leading PHY integration into SoCs and working with post-silicon teams such as HSIO, ATE, SVE, and CE.\n-Good understanding of peripheral PHY protocols such as USB, UFS, and PCIe.\n-Experience with Shell, Perl, or Python scripting to automate circuit design and verification\nKeywords\nAnalog Circuit Design, RX, TX, PLL, SerDes, VCO, High-Speed Transceiver, AFE, Equalizer, Sampler, Phase Interpolator, CTLE, PAM, Serializer, Deserializer, FinFET, Post-Silicon Bring-Up\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Serdes PHY Analog Design Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-03T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720923935", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nJob Function\nBDC SerDes Mixed-Signal design team is actively looking for experienced (8+ years) analog circuit designers to work on high speed SerDes PHYs. You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. \n\nResponsibilities\nHands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO, high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc.\nAnalog and or Digital PLLs for frequency synthesis and/or SerDes applications  Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. \nPLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) \n\nAbility to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up.\nWork closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY.\n\nSkills & Experience\nFor lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc.\nUnderstanding of advance Finfet process effects on designs and layout is required.\nExperience in using SPICE simulators, adexl & virtuoso.\nExperience with post-Si bring-up and debug is must.\nGood understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added advantage.\nMaster/Bachelor in Electronics\nShell/Perl-python scripting to automate circuit design and verification work.\nAble to work with teams across the globe and possess good communication and presentation skills.\n\nPreferred  \nMixed signal design experience  \n\nKeywords\nAnalog circuit Design, Rx, Tx, PLL, SerDes, PHY, Serializer, Deserializer, VCO, High-speed Trans receiver\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Analog/Mixed Signal PLL Analog Designers", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-03T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719124952", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nJob Function\nQualcomm Mixed-Signal IP team is actively seeking analog circuit designers with 6–12 years of experience to join our growing team in Bangalore, India (BDC). You will be directly involved in delivering analog and mixed-signal integrated circuits for high-speed PLL/DLL/LDO/Data Converter IPs for SoCs and supporting their integration into Qualcomm's Mobile, Auto, IoT, and Compute products on leading-edge FinFET and advanced process nodes. Design goals include low-power and low-voltage analog designs for Qualcomm's low-power wireless products.\nResponsibilities\nHands-on experience - Analog circuit design \nOwn the architecture, design, and development of analog and mixed-signal hard macros for the PLL IP design team.\nDesign multiple analog building blocks, including bias circuits, references, op-amps, LDOs, VCOs/DCOs, and high-speed custom digital blocks such as dividers and clock distribution.\nPerform custom circuit design in the latest FinFET CMOS process technologies, deliver hard macros, and support customer integration and testing.\nSet up, run, and analyze SPICE circuit simulations, and create behavioral models.\nCollaborate closely with layout, digital design, physical design, and HSIO Bench/ATE teams.\nParticipate in internal customer requirement discussions to create clear design specifications.\nSkills & Experience\nMinimum 6 years of transistor-level analog/mixed-signal design experience, preferably in PLL design, data converters (ADC/DAC), or other high-speed applications.\nExperience using SPICE simulators, ADEXL, and Virtuoso.\nFamiliarity with custom analog layout, parasitic optimization, post-layout extraction, verification, and design review closure.\nUnderstanding of signal integrity in high-speed wireline design is preferred.\nScripting experience to automate circuit design and verification workflows.\nAbility to collaborate effectively with global cross-functional teams and communicate technical concepts clearly through documentation and presentations.\nPreferred  \nMixed-signal design experience, especially in PLL/DLL clocking architectures, high-speed interfaces, SoC integration, advanced CMOS/FinFET nodes, and scripting\nKeywords\nAnalog Circuit Design, Mixed-Signal IP, PLL, DLL, LDO, Bias, Reference, VCO, DCO, Clock Distribution, ADC, DAC, SPICE, Virtuoso, ADEXL, FinFET, Analog Layout, Post-Layout Simulation\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior IP Micro-architect (RTL) - Sr Lead /Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-03T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720362949", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nRole Focus :Core Domains Architecture definition, microarchitecture development, custom protocol design, RTL implementation, performance optimization, and silicon delivery for complex Custom IPs.\n\nCore Domains: Infrastructure IP, NoC, PCIe, CXL, memory systems, cache coherency, UALink, ESUN, and AI scale-up interconnect fabrics.\n\nJob Summary : Hands-on technical leader capable of driving IP from concept through production silicon while mentoring engineers and influencing architecture decisions. We are seeking a highly motivated and experienced Senior IP Micro-architect to join our Custom IP Team focused on developing next-generation Infrastructure IPs, memory subsystem solutions, and scalable interconnect architectures for high-performance SoCs. The ideal candidate will possess deep expertise in architecture definition, microarchitecture development, protocol design, RTL implementation, and performance optimization for complex custom IPs. This role requires strong technical leadership, hands-on design expertise, and the ability to drive IP development from architectural concept through silicon realization.\n\nKey Responsibilities • Drive architecture and microarchitecture definition of complex custom Infrastructure IPs. • Develop detailed microarchitecture specifications including datapath design, control logic, packet formats, flow control, ordering rules, coherency mechanisms, and state machines. • Lead RTL development and collaborate closely with verification, physical design, firmware, and SoC integration teams. • Evaluate and optimize architecture trade-offs across performance, power, area, scalability, latency, and implementation complexity. • Design and develop high-performance interconnect, memory, and protocol-centric IP solutions. • Drive design reviews, microarchitecture reviews, and technical decision-making across multiple projects. • Support verification planning, debug, emulation, FPGA validation, and silicon bring-up activities. • Ensure RTL quality through lint, CDC/RDC, synthesis, and design signoff methodologies. • Mentor junior engineers and provide technical leadership within the IP development team. • Stay abreast of emerging technologies in AI infrastructure, scale-up fabrics, memory systems, and high-speed interconnects.\n\nRequired Qualifications • 8-15 years of experience in SoC/IP architecture, microarchitecture, and RTL design. • Proven experience defining and delivering complex custom IPs from concept through production silicon. • Strong experience in architecture and microarchitecture development of one or more of the following: Infrastructure IPs, NoC, interconnect fabrics, memory subsystem IPs, cache coherency solutions, or high-speed interface IPs. • Strong understanding of computer architecture, SoC architecture, digital design methodologies, performance modeling and analysis, synchronization and flow control mechanisms, and high-performance data movement architectures. • Hands-on RTL design experience using Verilog/SystemVerilog. • Experience with design signoff methodologies including lint, CDC/RDC, synthesis, and timing closure fundamentals. • Strong debugging, analytical, and problem-solving skills. • Excellent verbal and written communication skills. • Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Sr Engineer, CPU Implementation & Flow Automation", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-03", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Sr-Engineer--CPU-Implementation---Flow-Automation_R-101380", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nThe Role:\nAs a Senior Physical Design Engineer, you will be responsible for executing and optimizing the RTL-to-GDS implementation flow for our high-performance CPU cores. In this role, you will take ownership of block-level implementation and contribute to advanced design recipes to drive PPA (Power, Performance, Area) closure on leading-edge N3/N2 process nodes. This position focuses on high-quality technical execution, hands-on design closure, and utilizing automated, ML-enhanced methodologies to hit aggressive frequency and power targets within a highly collaborative team environment.\n\nKey Responsibilities\nFlow Execution & Validation: Implement, validate, and maintain production-ready RTL-to-GDS recipes using Synopsys Fusion Compiler based on established methodology guidelines.\n\nBlock Ownership: Take end-to-end implementation ownership of medium-sized CPU sub-blocks, driving them from RTL synthesis through to final GDS sign-off.\n\nPPA Optimization: Drive block-level PPA closure and contribute to hierarchical closure efforts, utilizing advanced techniques in timing-driven placement, CTS, and routing.\n\nML Deployment: Hands-on utilization of ML optimization tools (such as DSO.ai) to perform design space exploration and achieve optimal PPA targets.\n\nTechnical Execution & Troubleshooting: Identify, debug, and resolve flow and tool-related issues at the block level, collaborating closely with the wider methodology and core engineering teams to bypass bottlenecks.\n\nCross-Functional Collaboration: Partner with IP teams (SRAM/Std Cell) and technical leads to analyze and model PPA impacts within your design blocks.\n\nAutomation & Scripting: Develop, enhance, and maintain robust Tcl/Python scripts to improve flow efficiency, ensuring repeatable and predictable results across design iterations.\n\nRequirements\nExperience: 3+ years of hands-on experience in Physical Design/Methodology, with a strong track record in digital implementation.\n\nNode Knowledge: Solid experience with FinFET nodes (N5/N3); familiarity with N2/GAAFET challenges is a strong plus.\n\nTool Proficiency: Deep hands-on knowledge of the Synopsys digital implementation suite (Fusion Compiler, ICC2, PrimeTime, StarRC).\n\nDesign Understanding: Strong grasp of physical design concepts, including floorplanning, pin assignment, and timing budgeting within a hierarchical environment.\n\nAutomation Skills: High proficiency in Tcl and Python for flow customization, debugging, and data analysis.\n\nProblem Solving: Proven ability to analyze and resolve complex timing, power, and congestion issues in high-speed, high-density blocks.\n\nTeamwork: Excellent communication skills with a proven ability to collaborate effectively within a structured team environment and align with technical milestones.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Sr Engineer, Low Power Verification & Formal Equivalence", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-03", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Sr-Engineer--Low-Power-Verification---Formal-Equivalence_R-101381", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nAbout the Role\n\nWe are seeking a highly skilled Senior Engineer to drive our Low Power Verification and Formal Equivalence signoff execution. In this critical role, you will take ownership of static low power checks and formal verification flows for our advanced, high-performance design blocks and sub-systems. You will partner closely with Physical Design and Power teams to ensure robust power intent implementation and flawless logical equivalence throughout the RTL-to-GDSII flow, including executing complex, late-stage engineering changes (ECOs).\n\nKey Responsibilities\nLow Power Signoff Execution: Take ownership of static low power verification checks across assigned design blocks and sub-systems, ensuring complete coverage and zero low-power structural bugs.\n\nUPF Implementation & Automation: Deploy, optimize, and maintain Unified Power Format (UPF) coding and verification flows, collaborating with architecture and methodology teams to ensure alignment with platform standards.\n\nFormal Equivalence Ownership: Own and drive the Logical Equivalence Checking (LEC) flow for your design blocks, ensuring strict logical equivalence from RTL through post-route netlists, including the execution of complex functional ECOs.\n\nCross-Functional Collaboration: Apply your understanding of Physical Design constraints and power architectures to debug violations and provide optimal, implementable UPF and equivalence solutions alongside backend teams.\n\nRequired Qualifications\nEducation & Experience: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with 3+ years of relevant industry experience in ASIC/SoC design and verification.\n\nPower Intent Proficiency: Strong, practical experience coding, debugging, and maintaining power intent using the Unified Power Format (UPF).\n\nStatic Power Verification: Proven expertise running, analyzing, and debugging static low power checks on both RTL and post-PNR netlists using industry-standard tools (e.g., Synopsys VC Low Power / VCLP).\n\nFormal Signoff: Hands-on experience with Logical Equivalence Checking (LEC) and Formal Equivalence tools (e.g., Synopsys Formality), including experience implementing and verifying formal ECO flows.\n\nLow Power Libraries: Technical understanding of Power Management library cells and their physical/logical implications, including Isolation cells (ISO), Level Shifters (LS), Always-On (AON) cells, and Retention registers.\n\nPreferred Qualifications\nPhysical Design Foundation: Solid foundational knowledge of the backend Physical Design (PD) flow, enabling you to anticipate implementation challenges and bridge the gap between frontend intent and backend realization.\n\nScripting & Automation: Strong scripting proficiency (Tcl, Python, or Perl) to drive flow automation, parse log files, and implement methodology improvements.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Engineer II, Physical Design", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-03", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Engineer-II--Physical-Design_R-101433", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nThe Role:\nAs a Senior Physical Design Engineer, you will be responsible for executing and optimizing the RTL-to-GDS implementation flow for our high-performance CPU cores. In this role, you will take ownership of block-level implementation and contribute to advanced design recipes to drive PPA (Power, Performance, Area) closure on leading-edge N3/N2 process nodes. This position focuses on high-quality technical execution, hands-on design closure, and utilizing automated, ML-enhanced methodologies to hit aggressive frequency and power targets within a highly collaborative team environment.\n\nKey Responsibilities\nFlow Execution & Validation: Implement, validate, and maintain production-ready RTL-to-GDS recipes using Synopsys Fusion Compiler based on established methodology guidelines.\n\nBlock Ownership: Take end-to-end implementation ownership of medium-sized CPU sub-blocks, driving them from RTL synthesis through to final GDS sign-off.\n\nPPA Optimization: Drive block-level PPA closure and contribute to hierarchical closure efforts, utilizing advanced techniques in timing-driven placement, CTS, and routing.\n\nML Deployment: Hands-on utilization of ML optimization tools (such as DSO.ai) to perform design space exploration and achieve optimal PPA targets.\n\nTechnical Execution & Troubleshooting: Identify, debug, and resolve flow and tool-related issues at the block level, collaborating closely with the wider methodology and core engineering teams to bypass bottlenecks.\n\nCross-Functional Collaboration: Partner with IP teams (SRAM/Std Cell) and technical leads to analyze and model PPA impacts within your design blocks.\n\nAutomation & Scripting: Develop, enhance, and maintain robust Tcl/Python scripts to improve flow efficiency, ensuring repeatable and predictable results across design iterations.\n\nRequirements\nExperience: 2+ years of hands-on experience in Physical Design/Methodology, with a strong track record in digital implementation.\n\nNode Knowledge: Solid experience with FinFET nodes (N5/N3); familiarity with N2/GAAFET challenges is a strong plus.\n\nTool Proficiency: Deep hands-on knowledge of the Synopsys digital implementation suite (Fusion Compiler, ICC2, PrimeTime, StarRC).\n\nDesign Understanding: Strong grasp of physical design concepts, including floorplanning, pin assignment, and timing budgeting within a hierarchical environment.\n\nAutomation Skills: High proficiency in Tcl and Python for flow customization, debugging, and data analysis.\n\nProblem Solving: Proven ability to analyze and resolve complex timing, power, and congestion issues in high-speed, high-density blocks.\n\nTeamwork: Excellent communication skills with a proven ability to collaborate effectively within a structured team environment and align with technical milestones.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Staff - Formal Verification Engineer", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-03", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Staff---Formal-Verification-Engineer_R-101233", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nResponsibilities:\nIdentify blocks suitable for applying Formal Verification\nCreate Formal Test-plan for blocks identifying properties to be implemented and sign-off metrics\nImplementation and maintenance of Formal Verification environments in Chisel\nApplying various FV techniques to reduce complexity and prove correctness of DUT\nDebugging RTL to identify causes of failure scenarios\nGuide and train team members on effective usage of Formal Verification tools\nDevelop/modify scripts to automate the verification process\nReview formal setups and proofs with design and verification teams\nMaintain and extend assertion libraries\n \nRequirements:\n8+ years of experience in Formal Verification of Digital Hardware Design\nExtensive experience with Formal Abstraction Techniques and sign-off process\nFamiliarity with industry-standard Formal Verification Tools, such as VC Formal, JasperGold\nKnowledge of Hardware Description and Verification Languages, such as VHDL, Verilog/ System Verilog\nKnowledge of Object-oriented Programming is a plus\nA keen interest in Processors and Digital systems\nStrong reasoning skills and excellent attention to detail\nGood inter-personal and teamwork skills!\nBachelor’s or Master’s degree in Electrical Engineering or Computer Engineering\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Engineer II, Physical Design - Cores", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-03", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Engineer-II--Physical-Design---Cores_R-101161-1", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nAbout the Role --\nAt SiFive, we’re redefining the compute landscape with our industry-leading RISC-V compute platforms. As a Physical Design Engineer (Entry Level), you will jump-start your career by helping build our next generation of high-performance CPUs. Working closely with industry veterans, you will learn the end-to-end ASIC design flow from RTL to GDSII while contributing to real-world products on advanced process nodes.\nWe are looking for engineers who are passionate about the intersection of computer architecture and physical implementation. Rather than just executing a push-button flow, you will be trained to operate across design-abstraction layers. By leveraging a strong foundational understanding of how CPUs work, you will help bridge the gap between RTL design and physical realities, learning how architectural choices directly impact power, performance, and area (PPA).\n\nResponsibilities - What you’ll do\nLearn and Execute: Partner with senior engineers to take CPU blocks through the physical design flow, including synthesis, place & route, and timing closure.\n\nBridge Architecture and Implementation: Apply your academic knowledge of computer architecture to understand the underlying RTL. Participate in cross-abstraction-layer co-design discussions to see how pipeline stages, datapaths, and control logic translate into physical wires and gates.\n\nAnalyze PPA Trade-offs: Assist in analyzing timing reports, routing congestion, and power metrics to help the team meet aggressive Power, Performance, and Area goals.\n\nFlow Automation: Write and maintain scripts (Python, Tcl, Bash) to automate physical design workflows, parse reports, and improve team efficiency.\n\nCollaborate and Grow: Work cross-functionally with RTL, microarchitecture, and methodology teams. Absorb mentorship from world-class engineers to rapidly develop your backend expertise.\n\nRequirements - What you’ll bring\nExperience: 3+ years. We are open to considering new graduates with excellent academic credentials. If you have some work experience with physical design implementation it will be a big plus.\n\nEducation: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. \n\nStrong Architectural Foundation: A solid academic grasp of computer architecture fundamentals (e.g., RISC instruction sets, processor pipelining, hazards, memory hierarchy, and cache basics).\n\nDigital Design Knowledge: Strong understanding of digital logic design and the ability to read and understand RTL (Verilog or SystemVerilog).\n\nVLSI Exposure: Academic coursework, projects, or internship experience related to VLSI design or ASIC flows.\n\nScripting Skills: Proficiency in at least one scripting or programming language commonly used in hardware environments (Python, Tcl, Perl, C++, or Bash).\n\nGrowth Mindset: Highly motivated to learn industry-standard EDA tools (Synopsys or Cadence) and eager to understand the \"why\" behind physical design challenges, not just the \"how.\"\n\nWhy join us?\nBe part of the RISC-V movement and help define the future of computing architecture.\n\nWork on industry-leading IP adopted by top customers and shipped in high volumes worldwide.\n\nCollaborate with world-class engineers in a supportive, fast-paced, learning environment.\n\nEnjoy a culture that values innovation, ownership, and technical excellence.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Senior Engineer, Physical Design - Interconnects", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-03", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Senior-Engineer--Physical-Design---Interconnects_R-101167", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nAbout the Role -\nAs a Senior Physical Design Engineer (Interconnects), you will be responsible for the physical design implementation of the high-speed logic that binds the SoC together. This includes scalable Network-on-Chips (NoC), coherent CPU clusters, and critical Uncore subsystems.\nIn this role, you will move beyond standard block-level implementation to tackle the unique challenges of high-speed Interconnects. You will bridge the gap between RTL design and physical design, ensuring that our complex interconnect architectures achieves aggressive PPA (Power, Performance, Area) targets on the world’s most advanced process nodes.\n\nResponsibilities - What You’ll Do\nEnd-to-End Execution: Own the RTL-to-GDSII implementation of complex System IP components, including NoC fabrics, coherent clusters, and memory subsystem logic.\n\nIP-Physical Co-Design: Partner with design/architecture from early-stage feasibility analysis to IP convergence. You will help identify and resolve physical bottlenecks—such as long-wire delays or routing congestion—by suggesting microarchitectural tweaks or optimized pipelining.\n\nSystem-Level Floorplanning: Develop and refine floorplans for implementing massive, bus-heavy subsystems.\n\nInterconnect Problem Solving: Solve physical challenges unique to system-level integration, such as closing timing on wide, high-frequency buses, managing global clock distribution etc.\n\nMethodology & Automation: Execute and improve automated design flows for synthesis, place-and-route, and sign-off. You will contribute to internal scripts and methodologies to streamline implementation.\n\nRequirements - What You’ll Bring\nRelevant Experience: 4+ years of hands-on physical design experience, with a focus on closing high-performance blocks in FinFET nodes (7nm or below).\n\nSystem IP Knowledge: Solid understanding of SoC building blocks such as NoC architectures, coherent interconnects, or cache-coherent clusters. You should be comfortable reading RTL to understand design intent.\n\nPhysical Implementation Skills: Mastery of hierarchical design techniques, including partitioning, timing budgeting, and multi-mode multi-corner (MMMC) timing closure.\n\nEDA Tool Proficiency: Strong hands-on proficiency with major EDA suites - Synopsys and/or Cadence implementation and sign-off tools.\n\nAnalytical Mindset: A data-driven approach to optimizing PPA trade-offs, combined with the ability to communicate technical challenges clearly to the cross-functional teams.\n\nEducation: BS or MS in Electrical Engineering, Computer Engineering, or a related field.\n\nWhy Join Us?\nShape the Ecosystem: Help build the RISC-V infrastructure that is redefining the global compute landscape.\n\nTechnical Versatility: Gain exposure to a wide array of IPs in our portfolio and opportunities to work across IPs and product lines.\n\nExpert Collaboration: Join a fast-paced environment where innovation and technical ownership are at the heart of everything we do.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Staff Engineer - Physical Design", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-03", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Staff-Engineer---Physical-Design_R-101429", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nAbout the Role\n\nAs a Staff Physical Design Engineer, you will be a key technical contributor driving the physical design implementation of our next-generation IPs. You will be responsible for translating complex RTL into high-performance implementation, ensuring architecture/design achieves its peak physical potential.\n\nWe are looking for a true \"full-stack\" physical design engineer who is deeply curious about the logic they are building. You should be the type of engineer who thrives at the convergence of microarchitecture and physical layout, enjoying the challenge of analyzing how an architectural datapath affects timing closure, how a memory floorplan impacts power density, and how to push the boundaries of Power, Performance, and Area (PPA) through cross-functional collaboration.\n\nKey Responsibilities:\nEnd-to-End Implementation: Drive the complete physical design flow (Synthesis, Floorplanning, P&R, Signoff) for major sub-systems and diverse IP blocks, ensuring they meet or exceed aggressive targets for PPA.\n\nArchitectural & RTL Co-Optimization: Actively partner with RTL and Architecture teams from early-stage design to signoff. Identify physical and structural bottlenecks early—such as routing congestion in complex crossbars, dynamic power hot-spots in execution units, and interconnect span limits—and co-design microarchitectural or structural solutions to overcome them.\n\nCross-Product PPA Push: Apply advanced physical design techniques customized to the unique demands of different design classes. This includes driving extreme leakage/dynamic power efficiency for edge IPs, rigorous reliability and redundancy structures for automotive standards, or maximizing bandwidth and throughput for high-speed fabrics.\n\nTechnical Leadership: Act as the subject matter expert for complex implementation challenges; contribute to flows/methodology/automation; mentor junior engineers and champion best practices.\n\nRequirements - What you’ll bring\nExperience: 7+ years of hands-on physical design experience with a proven track record of successful tape-outs on advanced process nodes (7nm and below preferred).\n\nVersatile IP Implementation Expertise: Deep familiarity with the physical implementation of at least one major IP domain (such as CPUs, high-speed interconnects/fabrics, cache/memory hierarchies, or specialized accelerators) and a proven ability to adapt to new logic classes.\n\nCo-Design Mindset: A strong understanding of how physical design choices influence microarchitecture, with the intellectual curiosity to pick up the specific nuances of diverse product lines.\n\nTool Mastery: Expert-level proficiency with industry-standard EDA tools—specifically Synopsys (Fusion Compiler, PrimeTime) and/or Cadence (Innovus, Tempus) implementation and sign-off suites.\n\nAdvanced Problem Solving: Ability to debug complex physical design challenges, including structural timing violations, routing congestion, and dynamic IR drop with minimal supervision.\n\nEducation: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.\n\nWhy join us?\n\nIn this role, you will be pivotal in driving aggressive PPA optimizations across significant design sections, operating at the critical intersection of physical layout, RTL design, and hardware architecture. You will have the autonomy to make a substantial impact across our entire product portfolio from highly efficient IoT cores, dense memory systems, and demanding high-performance platforms. We offer the opportunity to collaborate with world-class engineers in a supportive, fast-paced, and learning-rich environment.\n \n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Design Verification Eng 2(IP/SoC)", "company": "Lattice", "location": "Pune, India", "date_posted": "2026-09-03", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Pune-India/Design-Verification-Eng-2_R-103057", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nLattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n \nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\n\nResponsibilities\n\nInviting candidates with a passion for invention and self-challenge. This position gives you an opportunity to be a part of one of the most cutting edge and key projects that Lattice’s Silicon Engineering team has embarked upon to date. As part of our team, you will have the opportunity to contribute to verifying complex FPGAs. This team will allow you to integrate multiple sophisticated IP level Design and Verification (DV) environments, craft highly reusable best-in-class UVM TB, implement effective coverage driven and directed test cases, deploy new tools and implement methodologies to improve quality of tape-out readiness. By collaborating with other product development teams across Lattice, you can push the industry boundaries of what FPGA systems can do and improve the product experience for our customers across the world! You will be able to learn all aspects of a FPGA, different types of SOC architecture, many highspeed layered protocols, industry’s standard methodologies on low power architecture, best in class DV methodology, verification on accelerated platforms, FW-HW interactions, complexities of FPGA and SOC debug architecture, etc. You'll be at the center of the design verification effort within our silicon design SOC verification team responsible for crafting and productizing state-of-the-art FPGAs. This position requires someone comfortable will all areas of FPGA design verification engineering. Someone that thrives in a dynamic multi-functional organization and is not afraid to take on challenges and solve complex problems using state of the art verification methodologies.\n\nRequired Skills\nBS/MS Electrical Engineering, Computer Science, Computer Systems Engineering, or equivalent degree\nAt least 3+ years DV experience in  IP/SoC verification\nProven track record of working full ASIC verification from concept to tape-out\nAdvanced knowledge of System Verilog and UVM methodology\nHands-on verification experience in verifying IPs like PCIExpress or Ethernet or USB in UVM environment will be preferred\nHands-on verification experience in verifying IPs using AMBA bus architecture in UVM environment.\nExposure on working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification will be plus.\nAbility to create IP level module and sub-system verification plans, TBs, portable test benches, sequences, verification infrastructure.\nDevelop UVM based highly reusable test benches for IP verification and achieved targeted coverage numbers.\nWork with design, architecture, SW, FW, and IP delivery teams to efficiently integrate and verify overall FPGA design.\nShould be a great team member with excellent communication and problem-solving skills and the desire to seek diverse challenges.\n\nLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.\n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1000+ strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.\n\n#LI-DNP\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Senior ASIC Power and Thermal Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-09-03", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-ASIC-Power-and-Thermal-Engineer_JR2024964", "is_hardware": true, "platform": "workday", "jd_text": "As one of the technology industry's most desirable employers, NVIDIA has been redefining accelerated computing, computer graphics and leading the Artificial Intelligence revolution. NVIDIA's innovation is fueled by its great technology and amazing people. We seek a Senior Power and Thermal Engineer to join our dynamic and fast-paced Silicon Solution Group. As part of the Silicon Solutions Team, we architect and deliver groundbreaking system solutions that integrate all aspects of the system from silicon design, software design to operations and final deployment in multiple market segments that NVIDIA serves. This position offers a unique opportunity to collaborate with multiple organizations in the company and grow your career in a high impact role. We need a passionate, hard-working, and creative individual to architect and productize next generation power and performance controllers.\n\nWhat You Will Be Doing:\nResponsible for developing test methodologies of next generation power and thermal management features and solutions working with multi-functional teams across the company.\n\nDrive board design requirements, FW/SW design requirements to characterize the silicon\n\nCreate methodologies for deployment of features into products.\n\nWork alongside system architects, designers, chip and board designers, software/firmware engineers, HW/SW applications engineering, process/reliability authorities, ATE engineers, and silicon operations, in a fast-paced, high-energy, collaborative work environment to bring industry-defining products to market.\n\nTraining and mentoring highly motivated engineers to solve complex challenges \n\nWhat We Need to See:\nB. Tech or M. Tech in Electronics Engineering, Computer Science, or related field (or equivalent experience)\n\n5+ years of experience in silicon bring-up, validation, and productization.\n\nExperience with control systems, power/thermal controllers and management.\n\nExpertise and deep understanding in the areas of silicon power, transistor/device physics, power modeling and measurement, active power management\n\nProficiency in Python, Perl or C programming languages is a plus\n\nSelf-starter with strong skills in multi-tasking, influencing, communication, presentation, and consensus-building\n\nEnthusiastic, responsive, and keen on process improvement\n\nWith competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our exclusive engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you.\n\nWe are an equal-opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior Digital Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-09-03", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505264", "is_hardware": true, "platform": "oracle", "jd_text": "Job Description\n\n \n\nThe Role\n\n \n\nWe are looking to expand our team with a Senior Digital IC Design Engineer. You will help us develop IP for next generation Automotive, Industrial & Medical products. The successful candidate will participate in the design of complex mixed-signal IPs like DACs, ADCs, PLL and wireless interface etc. \n\nWhy Join Us\n\nWe create a diverse set of world-class products in a friendly and team-oriented atmosphere. We provide an environment of continual learning and growth opportunities and support volunteer & charitable programs. You will be able to build up a career in a successful international company, and you can participate in interesting international projects.\n\nResponsibilities\n\n#LI-RT1\n\nResponsibilities\nWhat You’ll Do\nDefine architecture and participate in feasibility studies for new analog/mixed-signal IP components\nDrive design and verification of state-of-the-art CMOS and SOI designs which can be reused across different market segments.\nLead small teams on sub-projects and contribute to SoC integration\nPropose innovative solutions to meet customer and product needs\nCollaborate on DFT strategies and document designs thoroughly\nPartner with test, product, and applications engineering to ensure successful production release\nDocumentation: including architecture and circuit descriptions, testing procedures, and safety mechanisms.\n#LI-RT1\n\nQualifications\nQualifications\n \nWhat You’ll Need\nMinimum BS/MS in Electrical Engineering or related technical field\n+5 years in ultra-low-power digital design using Verilog/System Verilog\nCapacity to think at the system level and to operate as a technical leader\nCreativity, dynamism, reliability and team spirit\nExcellent English written and verbal communication skills\n \nWhat Else You May Bring \nExperience in some of the following areas is a plus:\nKnowledge Verilog-A or VHDL-AMS.\nExperience with embedded CPUs (e.g. ARM Cortex, DSP), AMBA bus protocols (AHB/APB)\nExperience in ADC, DAC, PLL, power management systems\nProgramming in Python for automation and in C/C++ for embedded software\nDesign intent (timing constraints/SDC, power intent/UPF)\nDesign of accelerators and signal processing components\nRTL to GDS flow, including logic synthesis, place-and-route, STA, power analysis\nAdvanced digital verification methodology (e.g. UVM)\nKnowledge in Functional Safety\n #LI-RT1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-03", "url": "https://careers.arm.com/job/bengaluru/engineer/33099/100112429248", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview:\nAs a part of  Arm's Solutions Engineering group we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies.\nResponsibilities:\nSynthesis, DFT , Floorplan , Place and Route  , CTS and  Optimization of CPU cores, system interconnect and other ARM Designs.\nRTL-GDS closure for Hard Macro\nAnalyze design timing, area and power to help improve the quality of ARM Design.\nAnalyze DRC/LVS/PERC/ERC using Calibre and perform Layout edit for Physical Verification closure.\nAnalyze Timing using primetime and perform Timing  ECO for design closure\nWork with implementation and physical IP RTL design teams to drive analysis and optimization of our IP.\nConverting R&D concepts into real implementation solutions.\nEnable our partners to achieve the best possible quality of results\nRequired Skills and Experience :\nBachelors or Master’s degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields.\n1-2 years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification\nStrong Communication and Problem Solving Skills.\nExperience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams\nExperience working closely in top and block level Synthesis, DFT, Floor planning, Place and Route, CTS, logical and physical optimization, timing closure and power analysis flows.\nProven programming and scripting skills eg. Tcl, Perl, Python, Make.\n“Nice To Have” Skills and Experience :\nKnowledge around Arm based SoCs!\nExperience with a wide range of programming, scripting & data presentation languages Eg. Tcl, sh, csh, make, R, C, C++, Java, JS, HTML, Perl, Python, Ruby.\nExperience with low power design techniques (power gating, voltage/frequency scaling)\nExperience with Verilog RTL design.\nExperience with ATPG tools/and or production testing.\nIn Return:\nAt Arm, we are guided by our core beliefs that reflect our creative culture and guide our decisions, defining how we work together to surpass ordinary and shape extraordinary.\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Chassis IP Senior Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-03", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Chassis-IP-Senior-Design-Engineer_JR0286859", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nIntel is seeking an experienced Logic Design engineer for the Intel Chassis Group, which is chartered to deliver the chassis for SoCs within Intel. The role involves logic design of component and foundation IPs which can be used to build an SoC chassis. The ideal candidate will have strong design and Verilog skills and some background in protocol conversion bridges for AMBA/CXL protocols. Understanding of concepts such as QoS, access control, flow control, debug, RAS, security and error handling is a plus.\n\nKey Responsibilities\n- Develop logic designs, register transfer level (RTL) coding, and simulations required for functional units, IP blocks, and subsystems.\n- Define and implement architecture and microarchitecture features for the interconnect IP block and sub-system which includes high-performance data plane and control plane routers, switches, arbiters, protocol conversion bridges, debug/trace components, and clock and power controls.\n- Perform rigorous quality checks and optimization of RTL designs to improve IP power, performance, area, and timing, ensuring delivery of high-quality IP.\n- Evaluate design trade-offs across area, bandwidth, timing, and reliability to achieve balanced and efficient IP functionality.\n- Support Sub-system/SoC customers with high-quality IP integration and verification workflows.\n\nQualifications:\nMinimum Qualifications\n• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with a minimum of 7 years of experience in logic design and RTL development.\n• Proficiency in hardware description languages, including Verilog and System Verilog.\n• Strong knowledge of digital design principles, such as timing analysis, power optimization, and area trade-offs.\n• Experience with industry-standard EDA tools for design, Quality checks and simulation (e.g., Synopsys, Cadence, Mentor Graphics).\n\nPreferred Qualifications\n• Familiarity with AMBA (CHI, AXI, AHB, APB) and PCIe/CXL protocols is a plus\n• Experience in working with architecture, verification, SoC integration teams\n• Good understanding of PPA trade-offs\n• Ability to work with physical design to solve timing issues\n• Experience with use of AI to assist logic design is a plus\n\nIn addition to the qualifications a successful candidate will demonstrate:\n• Communication skills\n• Capacity to work across large, geographically distributed engineering teams across multiple time zones.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Senior Package Layout Engineer - Hardware", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-09-03", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Package-Layout-Engineer---Hardware_JR2019694", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nNVIDIA's GPUs and SOCs are the world leaders in power, performance and efficiency. We are continually innovating to deliver new and creative, unusual solutions to extraordinary problems in a wide range of sectors. To this purpose, we are now seeking a hard-working Senior Package Layout Engineer who is committed to making a difference in the world through their contributions! This position will collaborate with Technical Package Lead and different design teams in the design and development of sophisticated, detailed layout of IC substrates for NVIDIA products. In addition, work with design teams to plan schedules, resolve costs, manufacturing, and electrical design issues.\n\nWhat you'll be doing:\nAs part of a Layout team, you will collaborate to implement high speed/density ASIC packages.\n\nPerform substrate breakout patterns for ASIC packages.\n\nOptimize package pinout incorporating system level trade-offs of pins assignment.\n\nHelp perform package routing, placement, stack-up, reference plane and power distribution using Cadence APD or SiP tool suite.\n\nPropose layout design trade-offs to the Technical Package Lead for resolution and implementation.\n\nConduct design feasibility studies to evaluate the Package design goals for size, cost, and system performance.\n\nDevelop symbols and CAD library databases using Cadence APD design tools\n\nDevelop methodologies to improve layout productivity\n\nWhat we need to see:\nHold a B.S. Electrical Engineering or equivalent experience\n\n5+ years experience in PCB Layout of graphics cards, motherboards, line cards or other related technology. Experience with HDI designs is a plus\n\nProven experience in substrate layout of wire bond and flip chip packages, preferred\n\nSignificant background with Cadence APD or SiP and/or PCB layout tools (including Constraint Manager)\n\nSolid understanding of high-speed design signal integrity practices\n\nExperience with Virtuoso and Calibre is a plus\n\nExperience using Valor is helpful\n \n\nNVIDIA is widely considered to be one of the technology world’s most desirable employers! We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative and autonomous, we want to hear from you.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "FPGA Prototyping Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-03", "url": "https://careers.arm.com/job/bengaluru/fpga-prototyping-engineer/33099/98426130992", "is_hardware": true, "platform": "talentbrew", "jd_text": "Your Future Team:\nThe FPGA team is part of the Productivity Engineering group. We are responsible for delivering and supporting FPGA platforms at Arm, enabling design debugging and the deployment of advanced pre-silicon verification methodologies. The systems we implement in our FPGAs target a wide range of market segments like mobile technologies, servers, IoT and the automotive sector.\nJob Overview:\nAs a FPGA Engineer, you will have the chance to deliver cutting edge FPGA prototyping platforms, based on the requirements of highly configurable systems. You will collaborate with several teams across the world, to achieve the validation goals.\nWe seek individuals with significant experience of FPGA prototyping, with strong technical skills, a good eye for detail, and good interpersonal skills.\nAre you a creative, positive, and adaptable person with a strong technical background in FPGA prototyping? This is the role for you!\nResponsibilities:\nDevelopment and deployment of FPGA images and debugging technologies, oriented at system prototyping.\nAutomation of the FPGA flows and definition of the methodologies that can be deployed to the community of the FPGA users.\nSupport for the FPGA users and maintenance of the FPGA service.\nCollaboration with EDA vendors to drive requirements for next generation of FPGA hardware and tools.\nRequired Skills and Experience :\n3-6 years of experience in FPGA flows based on Xilinx/AMD devices, including compilation, partitioning, synthesis, debugging, timing performance, place and route troubleshooting.\nProven record of accomplishments in design debugging and execution both as an individual and as a team.\nDeep understanding of digital design concepts and Verilog coding.\nProficiency and proactivity in problem solving.\nCode versioning and review.\n“Nice To Have” Skills and Experience :\nExperience in scripting language such as python, bash, tcl.\nIn Return:\nWe will provide the training and environment to excel in this role. We offer a hybrid approach to remote and office working and strive to provide an adaptable experience for all employees and to promote a strong collaborative environment.\n \n#LI-SA3\nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Engineer I", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-03", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Engineer-I_R-101432", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nResponsibilities:\n\nEngage in the logic design and verification of digital IPs, CPUs, peripherals, and sub-systems across various VLSI domains.\nCreate and implement innovative designs and testbenches that are highly scalable, configurable, and efficient.\nStrong hands-on experience with UVM testbench development is highly valued.\n\nQualifications :\n\nMinimum of 1+ years of experience with Bachelor's or Master's in Engineering\nSolid understanding of electrical engineering concepts, Digital Electronics, and VLSI design concepts\nExcellent communication, problem-solving and analytical skills.\nAbility to work independently and in a team.\nGood understanding in one or more of the following areas:\na)      Computer architecture\nb)      Logic design\nc)      Circuit design and semiconductor devices\nd)      Programming languages such as C/C++,Java, python/Perl, tcl , Haskell\ne)      Hardware Description Language like Verilog, System Verilog or VHDL\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Verification Engineer, PCIE", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-09-03", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Verification-Engineer--PCIE_JR2024943", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science.\n\nThe GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nBe responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nExpected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.\n\nYou will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech or equivalent experience\n\n1+ years of relevant experience\n\nExperience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog\n\nExpertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)\n\nExperience in developing and working in functional coverage based constrained random verification environments\n\nBackground in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nExcellent knowledge of PCIE protocol - Gen3 and above\n\nGood understanding of the system level architecture of PCIE/CXL-based designs\n\nPerl, Python or similar scripting and SW programming language experience\n\nGood debugging and analytical skills\n\nGood interpersonal skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Staff Engineer Design", "company": "Infineon", "location": "Bangalore", "date_posted": "2026-09-02T11:14:43+00:00", "url": "https://jobs.infineon.com/careers/job/563808971934401", "is_hardware": true, "platform": "eightfold", "jd_text": "Join our team to drive next-generation FPGA modeling, system-level validation, and firmware co-verification. If you have expertise in ASIC/FPGA design, SystemVerilog, Python automation, and FPGA prototyping, this is an opportunity to shape innovative semiconductor solutions while collaborating with global engineering teams.\n\nYour role\nKey responsibilities in your new role\n\nDevelop Real Number Models (RNM) using SystemVerilog and svreal for Analog/Mixed-Signal IP modeling.\n\nBuild and maintain FPGA-based prototypes for SoC and system-level validation.\nDrive pre- and post-silicon firmware validation on FPGA platforms.\nDebug hardware-software interfaces using tools like Vivado ILA and SignalTap.\nCreate Python automation frameworks for simulation, FPGA flows, and CI/CD.\nEnhance and standardize FPGA prototyping and modeling methodologies.\nLead FPGA modeling architecture and mentor engineering teams.\nCollaborate with global teams across digital, analog, firmware, and embedded domains.\nSupport faster product validation and accelerated time-to-market.\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor's, Master's, or PhD degree in Microelectronics, Electrical Engineering, Computer Engineering, or a related engineering discipline.\nStrong academic foundation in digital design, FPGA architectures, semiconductor systems, and embedded technologies.\n\n[For multiposting positions, select only the content related to the locations applicable to this position (e.g. if position can be filled in Austria and Canada, remove the content related to the United States). Additionally, you must remove or edit any text that is in red before publishing the job ad.\nIf none of the locations below are applicable for the position to be published, please remove the full content and leave this section blank.]\n \nAdditional information by location\nAustria\n[You can find below 2 options: the first is a generic one for any position in Austria and the second is only valid for leasing positions. Choose the one that applies to your position and delete the other one.]\nWe offer competitive salaries and additional benefits based on your performance, experience, and qualification. The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group [fill employement group] (https://www.feei.at/aktuelles/mindestloehne-und-gehaelter-eei/). The monthly salary is paid 14 times p.a. We offer a higher compensation depending on your expertise and skills.\n \n[Leasing positions] We are filling this position through one of our leasing partners. A valid work permit for Austria (RWR+ Card) or EU citizenship is a prerequisite for this position. This position is subject to the collective agreement for workers and employees of EEI with a minimum salary of € 4.341,85 (https://www.feei.at/wp-content/uploads/2024/04/minimum-salaries-white-collar-workers-2025.pdf). The monthly salary is paid 14 times p.a. A higher payment is negotiable depending on your expertise and skills.\n \nCanada\nThe candidate must be eligible to meet the requirements of export control regulations, including the Canadian Controlled Goods Program and Canadian government security requirements; and/or (as necessary):\nMust be able to obtain a Secret Clearance\nMust not pose a risk for safeguarding of controlled goods\nMust be eligible to handle US export-controlled data\n \nInfineon welcomes and encourages applications from people with disabilities. Accommodations are available on request for candidates taking part in all aspects of the selection process.\n \nUnited States\nInfineon Technologies is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), gender identity, national origin, ancestry, citizenship, age, physical or mental disability, legally protected medical condition, family care status, military or veteran status, marital status, domestic partner status, sexual orientation, or any other basis protected by local, state, or federal laws.\n \nEmployment at Infineon is contingent upon proof of your legal right to work in the United States under applicable law, verification of satisfactory references, successful completion of a background check and drug test, and signing all your on-boarding documents.\n \nIn some instances, if applicable, U.S. export control laws require that Infineon obtain a U.S. government export license prior to releasing technologies to certain persons. This offer is contingent upon Infineon's ability to satisfy these export control laws as related to your employment and anticipated job activities. The decision whether or not to submit and/or pursue an export license to satisfy this contingency, if applicable, shall be at Infineon's sole discretion.\n \nInfineon Technologies takes data privacy and identity theft very seriously. As such, we do not request personally-identifiable information (PII) from applicants over the internet or electronically. Please kindly refrain from disclosing your PII electronically during the application process or to unauthorized websites that may purport to be Infineon or any of our affiliates.\n \n[For HiRel positions only, add the following paragraph; otherwise, remove it.] This position requires access to documentation that is controlled by the export laws of the United States. Candidates are required to provide proof of either US citizenship, Permanent US residency, or classification as a protected individual as defined in 8USC 1324b(a)(3).\n \nSalary pay information:\nIn line with local legal requirements, indicative salary ranges are disclosed for selected locations where applicable.\n \n[Please note that for all the locations stated in the table below it is mandatory to disclose salary. Remove from the table all rows with locations that are not applicable to this position]\nLocation\nIndicative salary range\n\nLocation, Belgium*\n€xxx.xxx – €xxx.xxx\n\nLocation, Canada\nWage range that the company expects to pay for a qualified candidate:\nCA$xxx.xxx – CA$xxx.xxx\n \nIn addition, all employees will be eligible to participate in an incentive plan.\n\nLocation, Italy*\n€xxx.xxx – €xxx.xxx\n\nLocation, United States\nWage range that the company expects to pay for a qualified candidate:\nUS$xxx.xxx – US$xxx.xxx\n\nIn addition, all employees will be eligible to participate in an incentive plan.\n\nLocation, Poland*\nzłxxx.xxx – złxxx.xxx\n\n \n Please remove the sentence below if none of the countries marked with * in the table above applies to your posting:\n*The stated salary comprises annual base pay and target variable compensation. The starting salary is determined using objective, gender neutral criteria, including relevant experience, qualifications, and role scope; prior compensation is not requested or considered. Employees also benefit from a comprehensive total rewards package, which may include further compensation and benefit elements depending on local regulations and company policies.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\n\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Principal CAD Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-02T11:00:58.244000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000146957524-principal-cad-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking a Principal Engineer – CAD to develop and deploy Frontend and Backend tools and flows for Digital Designs done in the company. This role is part of the global CAD team.\nJob Description\nOwn some part of the overall CAD solution and be responsible for WW engagement with customers.\nGood understanding of Digital Implementation Methodologies.\nHands-on in development & debug of CAD flows and with industry leading EDA tools in Digital Designs\nProactively engage with customers through regular follow-ups, tool training sessions, and consistent support throughout the entire deployment process.\nHands-on in mature software development practices, leading programming languages for potential AI/ML development tasks\nExpected to work in a dynamic design environment\nEvaluate EDA tools and flows for improved design efficiency and turnaround time\nExperienced in leading small team.\n\nBTech/MTech in Electrical/Electronic Engineering, Computer Engineering or Computer Science with 15+ years of experience in EDA/CAD.\nProven experience in supporting mature-node technologies (e.g., 22nm, 12nm).\nExpertise in Synopsys/Cadence RTL to GDS digital design flow.\n\n (e.g., synthesis tools, implementation tools and STA tools)\nStrong scripting skills (Tcl, Perl, Python) for automation of RTL to GDS digital design flow  (e.g., synthesis, implementation tools and STA flows)\nStrong communication skills (written and verbal), problem solving, teamwork, attention to detail, commitment to task, and quality focus\nCan – do attitude, openness to new environment, people and culture\nAbility to propose innovative and leading-edge solutions\nStrong drive & ability to coordinate work across highly experienced global teams\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Engineer - FPGA Design", "company": "Ericsson", "location": "Bangalore,Karnataka,India", "date_posted": "2026-09-02T04:17:55+00:00", "url": "https://jobs.ericsson.com/careers/job/563121776532692", "is_hardware": true, "platform": "eightfold", "jd_text": "Join our Team\n\nAbout this Opportunity:\nWe are looking for an FPGA Designer to join the Ericsson Silicon organization. You will work with a group of dedicated engineers passionate about developing world-class Radio and RAN Compute products. You will play a key role in the FPGA team—developing and integrating complex systems for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, you'll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity and teamwork.\n \nYou will do:\nDesign and implement FPGA-based Radio and RAN Compute solutions\nDevelop and optimize FPGA designs for performance, power, and cost-efficiency\nCollaborate with hardware and software engineers to integrate FPGA solutions into larger systems\nApply industry-standard tools and methodologies for FPGA development and implementation\nResearch and stay updated on the latest advancements in FPGA technology, including academia and industry trends in AI and Machine Learning\nDocument design specifications, test procedures, and results\nParticipate in design reviews and contribute innovative ideas to improve FPGA solutions\n \nYou will bring:\n8+ years of experience in FPGA development\nComprehensive knowledge of:FPGA technology, design environments, and design methodologies\nFPGA design tools (e.g., Vivado, Quartus, or similar)\nHardware description languages (HDL), such as Verilog or VHDL\n\nExperience with various communication protocols—DDRX, AXI4, PCIE, SPI, I2C, embedded processing\nExperience with scripting languages such as Python, Tcl, shell scripting, etc.\nFamiliarity with hardware architecture and digital signal processing\nExcellent problem-solving and analytical skills\nExcellent English verbal and written communication skills\nHigh self-motivation and the ability to work independently while being a great teammate\nA track record of successful cross-team and cross-site cooperation\nA Master's degree in Electrical or Computer Engineering or equivalent\n\n*\n\n“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”\n\nWhy join Ericsson?At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.\n \nWhat happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.\n \nPrimary country and city: India (IN) || Bangalore\nReq ID: 786874", "jd_status": "stored"}, {"title": "Network Processor IP Verification Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-02T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719458047", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Description:\n\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nSkills/Experience : \n5-8 years of strong experience in digital front end ASIC design verification\nBachelors or Masters Degree in Engineering in Electronics, VLSI, Communications or related field.\nExpertise in RTL verification in C/System Verilog/UVM of complex designs with multiple clock and power domains\nBeing adaptable and have ability to work at various abstraction levels: Block/Core/IP/SS level. \nDemonstrate strong coding skills in System Verilog and UVM. \nDevelop verification environment and testbench components such as BFMs and checkers. \nAbility to code Assertion for temporal logic testing. \nScripting languages like Perl/Python and development test automation framework for regression automation. \nDeep understanding of Code/Functional coverage report, identify coverage holes, ability to develop new tests and closing design coverage with design/systems team. \nPerformance verification for throughput/latency analysis of Modem Usecases. \nExperience in low power verification methodology and clock domain crossing designs\nExperience of PA GLS verification of DC and PD PG Netlist.\nFamiliarity with various bus protocols like AHB, AXI\nExperience with Formal Verification is a plus.\nExperience in Modem/Wireless IP verification on wireless technologies like NR, LTE, WCDMA, CDMA, WLAN, Bluetooth is a plus.\nExperience in post-Si debug is a plus\nGood documentation skills\nShould possess good communication skills to ensure effective interaction with Engineering Management and team members.\nShould be self-motivated with good teamwork attitude and need to function with minimal guidance or supervision\nResponsibilities:\nDigital design verification working in close collaboration with Multi-site Teams across US and India and other Geos.\nWork in close coordination with Systems, Design, SoC team , SW team, Validation & DFT teams to get the goals completed.\nLead junior engineers and drive project planning and tracking.\nDeveloping the Verification Strategy, Testbench architecture and implementing the design verification plan and tests using SV/UVM/C. \nHW verification using Cadence and Synopsys simulator tools, SV/UVM based TB development, Regression analysis, bug-triage. \nFormal Verification using Jasper, VCF etc.\nPower Aware Verification on RTL and DC/PD Gate lebel Netlist. \nConducting High-/Mid-/Low- level verification reviews, coverage closure and sign-off on block and Sub-system testing. \nAssisting SOC team with IP Integration testing at SOC level.\nPost-Silicon Debugs in close collaboration with Design, Validation and SW teams.\nSelf-Motivated to Execute the defined tasks almost independently with minimal guidance \n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior IP Micro Architect -Sr Lead/Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-02T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720362601", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nRole Focus :Core Domains Architecture definition, microarchitecture development, custom protocol design, RTL implementation, performance optimization, and silicon delivery for complex Custom IPs.\n\nCore Domains: Infrastructure IP, NoC, PCIe, CXL, memory systems, cache coherency, UALink, ESUN, and AI scale-up interconnect fabrics.\n\nJob Summary : Hands-on technical leader capable of driving IP from concept through production silicon while mentoring engineers and influencing architecture decisions. We are seeking a highly motivated and experienced Senior IP Micro-architect to join our Custom IP Team focused on developing next-generation Infrastructure IPs, memory subsystem solutions, and scalable interconnect architectures for high-performance SoCs. The ideal candidate will possess deep expertise in architecture definition, microarchitecture development, protocol design, RTL implementation, and performance optimization for complex custom IPs. This role requires strong technical leadership, hands-on design expertise, and the ability to drive IP development from architectural concept through silicon realization.\n\nKey Responsibilities • Drive architecture and microarchitecture definition of complex custom Infrastructure IPs. • Develop detailed microarchitecture specifications including datapath design, control logic, packet formats, flow control, ordering rules, coherency mechanisms, and state machines. • Lead RTL development and collaborate closely with verification, physical design, firmware, and SoC integration teams. • Evaluate and optimize architecture trade-offs across performance, power, area, scalability, latency, and implementation complexity. • Design and develop high-performance interconnect, memory, and protocol-centric IP solutions. • Drive design reviews, microarchitecture reviews, and technical decision-making across multiple projects. • Support verification planning, debug, emulation, FPGA validation, and silicon bring-up activities. • Ensure RTL quality through lint, CDC/RDC, synthesis, and design signoff methodologies. • Mentor junior engineers and provide technical leadership within the IP development team. • Stay abreast of emerging technologies in AI infrastructure, scale-up fabrics, memory systems, and high-speed interconnects.\n\nRequired Qualifications • 8-15 years of experience in SoC/IP architecture, microarchitecture, and RTL design. • Proven experience defining and delivering complex custom IPs from concept through production silicon. • Strong experience in architecture and microarchitecture development of one or more of the following: Infrastructure IPs, NoC, interconnect fabrics, memory subsystem IPs, cache coherency solutions, or high-speed interface IPs. • Strong understanding of computer architecture, SoC architecture, digital design methodologies, performance modeling and analysis, synchronization and flow control mechanisms, and high-performance data movement architectures. • Hands-on RTL design experience using Verilog/SystemVerilog. • Experience with design signoff methodologies including lint, CDC/RDC, synthesis, and timing closure fundamentals. • Strong debugging, analytical, and problem-solving skills. • Excellent verbal and written communication skills. • Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SOC Design - Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-02T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720696955", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    5+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "EM/IR Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-02T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720933780", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nEMIR Signoff: Perform static and dynamic IR drop analysis, electromigration (EM) checks, and power grid optimization for complex SoCs. Perform power estimation runs using Primepower. Provide regular update to Team lead on EMIR status of design through detailed dashboard.\nDebugging & Troubleshooting: Analyze and resolve issues arising due to EMIR simulation setup and tool related issues. Suggest update to flows as and when necessary for new features and new tech nodes and for design corner cases.\nAutomation & Scripting: Write and maintain automated scripts using Python, Tcl, or Perl to parse results, build dashboards, and streamline signoff flows.\nCross-Functional Work: Partner with physical design, static timing analysis (STA), and packaging teams to clear layout bottlenecks, suggest fixes and run trials.\nEDA Collaboration: Work with electronic design automation (EDA) vendors to test tool flows, qualify new features, debug issues and drive robust solutions. \nMinimum Qualifications\n\nEducation: Bachelor's or Master’s degree in Electrical Engineering, Electronics, VLSI, or a related field.\nExperience: 5+ years of hardware engineering experience focusing on physical design signoff, power integrity, or IR/EM analysis.\nTool Knowledge: Hands-on experience with Ansys RedHawk, Cadence Voltus and Primepower.\nTechnical Skills: Strong knowledge in EMIR fundamentals, Strong foundation in physical design flows (floorplanning, routing, extraction) alongside robust scripting in Python or Tcl.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU Hardware Verification (Power Management) Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-02T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720238237", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nWe are seeking a highly motivated and technically strong Staff Engineer to drive end-to-end verification of next-generation CPU Co-Processor (CPUCP/PDP) Power Management firmware and hardware features. This role requires deep expertise in SystemVerilog-based verification, power management validation, and cross-functional leadership across Firmware, RTL Design and Post-Silicon teams.\nThe ideal candidate will own verification strategy from architecture definition through signoff, driving quality, scalability, automation, and execution excellence across CPU programs.\nMinimum Qualifications:\n• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\nOR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\nOR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.Key Responsibilities\nLead the end-to-end verification of CPUCP/PDP firmware-driven hardware features, with a focus on Power Management, Reliability, and System Readiness.\nArchitect and develop robust SystemVerilog/UVM testbenches, transactors, checkers, and verification infrastructure for complex SoC subsystems.\nDrive verification of AMBA-based system IPs including timers, mailbox, interrupts, and interconnect fabrics (NoC).\nOwn verification planning, test strategy, coverage modeling, coverage closure, and functional signoff.\nDefine and implement comprehensive validation for power-management features such as DVFS, Low Power Modes (LPM), clock/power transitions, and firmware-controlled sequences.\nLead complex debug and root-cause analysis across Firmware, RTL, Design, Emulation, and Post-Silicon teams.\nDevelop reusable stimulus frameworks, automation solutions, debug utilities, dashboards, and productivity tools to improve execution efficiency and scalability.\nSupport platform bring-up, SoD readiness, feature qualification, HW/FW release validation, and silicon readiness activities.\nInfluence architecture reviews and verification methodologies, ensuring best practices are consistently applied across programs.\nMentor junior engineers and foster a culture of technical excellence, ownership, and innovation.\nDrive cross-functional initiatives spanning Firmware, Hardware Design, Emulation, and Post-Silicon Verification teams.\nRequired Qualifications\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field .\nExtensive experience in SoC, CPU or Power-Management verification environments.\nStrong expertise in SystemVerilog/UVM, verification methodologies, and testbench architecture.\nProven experience developing NoC transactors, protocol checkers, and verification infrastructure.\nDeep understanding of AMBA protocols and system-level IPs such as timers, mailboxes, interrupts, and memory-mapped peripherals.\nStrong background in RTL simulation, emulation, waveform analysis, debug methodologies, and coverage closure.\nExperience validating power-management technologies including DVFS, LPM, idle states, power sequencing, and reset flows.\nProficiency in C/C++, SystemVerilog, Python, scripting, automation, and data-driven verification workflows.\nStrong analytical and debugging skills with the ability to diagnose issues across HW, FW, and system domains.\nDemonstrated ability to lead technical discussions, influence verification strategy, and drive execution across geographically distributed teams.\nAdded Advantage: Power Aware verification and Gate level simulation Hands – On experience\nPreferred Qualifications\n10–12+ years of industry experience in CPU, GPU, SoC, or complex subsystem verification.\nProven expertise in pre-silicon verification methodologies, testbench architecture, and verification infrastructure development.\nStrong track record of delivering verification signoff for complex SoC features from architecture definition through silicon bring-up.\nHands-on experience with automation frameworks,, regression infrastructure, and CI/CD verification workflows.\nKnowledge of system level Power management scenarios.\nPrevious experience mentoring engineers and leading cross team technical initiatives across organizations.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RTL Design(DDR) - Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-02T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720934220", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    3+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n\nPrincipal Duties and Responsibilities:\n•    Applies Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Assists in the assessment of complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Formal Verification Engineer", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-02", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Staff-Formal-Verification-Engineer_R-101243", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nResponsibilities:\nIdentify blocks suitable for applying Formal Verification\nCreate Formal Test-plan for blocks identifying properties to be implemented and sign-off metrics\nImplementation and maintenance of Formal Verification environments in Chisel\nApplying various FV techniques to reduce complexity and prove correctness of DUT\nDebugging RTL to identify causes of failure scenarios\nGuide and train team members on effective usage of Formal Verification tools\nDevelop/modify scripts to automate the verification process\nReview formal setups and proofs with design and verification teams\nMaintain and extend assertion libraries\n\nRequirements:\n7+ years of experience in Formal Verification of Digital Hardware Design\nBS/MS/PhD in EE/CE/CS or related field.\nExtensive experience with Formal Abstraction Techniques and sign-off process\nFamiliarity with industry-standard Formal Verification Tools, such as VC Formal, JasperGold\nKnowledge of Hardware Description and Verification Languages, such as VHDL, Verilog/ SystemVerilog\nKnowledge of Object-oriented Programming is a plus\nA keen interest in Processors and Digital systems\nStrong reasoning skills and excellent attention to detail\nGood inter-personal and teamwork skills!\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Design Architect", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-09-02", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Design-Architect_R55335-1", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nThis is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols.  The successful candidate will be a highly motivated self-starter who is able to work independently and collaboratively to complete tasks within required project timelines with high quality.  The candidate will contribute to digital architecture, digital RTL, low power design, synthesis and timing analysis, and behavioral coding for all IPs in the SerDes physical IP portfolio as well as executing various tool flows for IP quality control.  The candidate will be able to work as part of a small and focused team of engineers and will be able to collaborate successfully as needed with design architects, digital verification, project management, and digital and analog design teams in multiple worldwide geographies. \n\nThis includes but is not limited to: \nDigital architecture that has an understanding of the trade-offs for power, performance, and area\nDrive architecture to micro-architecture to RTL implementation with the refining of features/requirements throughout the design process\nUnderstanding of synthesis, constraint generation, power management and DFT\nUnderstanding of low-power designs and features (power islands, state retention, isolation)\nWork with verification team to specify coverage points, testing strategy, corner conditions and stimulus creation\nFamiliarity with uC Based subsystems and their architecture\nFamiliarity with AI assisted design practices\nQualifications\n15+  years of experience in working with Digital Design and Architecture.\nMust have good written and verbal cross-functional communication skills.\nProven experience in most of the following:Design Architecture\nDesign implementation\nEmbedded uC Designs\nSynthesis and SDC Creation\nScripting of design automation\nDebugging verification test cases / SVA’s to cover the design\n\nKnowledge of existing Serial standards such as PCIE, USB, Ethernet, etc.\nMust be comfortable interacting across the SSG development team including the ability to work with Mixed-signal, Verification and Analog teams\nShould be open to work with AI assisted design practices. Knowledge of AI assisted design flow is plus.\nKnowledge of multiple programming languages. System Verilog, Python, C/C++, etc, are a plus\nWorking knowledge of revision control tools such as Perforce, Git, SVN is a plus\nEducational qualifications - minimum Bachelor’s degree in Electronics/Electrical, Master’s preferred\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Test Sustaining Lead", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-02", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25017434", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\nThe Linear Power team is looking for bright engineers to drive our next generation of cutting-edge power products across Automotive, Industrial, Data Center, and Personal Electronics markets. As traditional power architectures rapidly transition toward higher power, higher voltage, and functionally safe systems, our team is actively developing highly differentiated solutions by pushing the boundaries of silicon process, advanced packaging, IP design, and test engineering. We believe in acquiring deep end-equipment knowledge, solving complex high-voltage challenges to achieve the best performance for the application. Our teams define, design, verify, validate, and take products to high-volume manufacturing through deep involvement with customers and a thorough understanding of the market - across a broad portfolio of Power Path Protection, High-Side Switches, Precision References, Power Monitoring Solutions, and best-in-class LDOs. Join this team if you want to be at the forefront of power design and shape the future of semiconductors.\n\nTest Sustaining Lead (JD)\n \nSummary\nThis role owns production continuity and test health for released products, driving rapid resolution of manufacturing and yield issues while building a proactive sustaining system, guiding multiple engineers. The engineer leads root-cause analysis, corrective actions, and cross-functional problem solving across design, quality, and operations teams. Sustaining learnings are systematically fed back to new product development to strengthen future product, validation, and test strategies.\nWhat You Will Do\nAs Sustaining Lead, you will own production stability end-to-end - resolving critical manufacturing, test, yield, and reliability issues with urgency while eliminating recurring problems through rigorous root-cause and permanent corrective action. You will develop and execute strategies to continuously improve yield and reduce test cost across the product portfolio, working directly with factory teams to implement solutions and sustain gains on the production floor. You will identify trends and risks before they escalate, continuously improve the sustaining process (prioritization, escalation, closure, and automation), and drive measurable improvements in test coverage, test time, and overall product robustness. You will partner closely with Test, Product, Design, Quality, Manufacturing, and Operations teams to close complex issues and build a structured feedback loop that transfers sustaining learnings into development to improve future designs and test strategies. You will establish clear ownership and accountability within the sustaining team and develop the team's technical problem-solving capabilities.\nWhat We Are Looking For\nWe are looking for an engineer with hands-on ATE and production test experience - including familiarity with ETS800 or V98K tester platforms (software and hardware) - a strong background in structured problem solving (8D, RCCA, or equivalent), and a track record of driving yield and cost improvements in a high-volume manufacturing environment, leading a small team. The ideal candidate combines deep technical judgment, strong analog fundamental skills and pcb design experience with cross-functional leadership - able to work across design, quality, factory, and operations teams, influence without direct authority, and build systems and processes that scale. Experience with sustaining metrics, data analysis, and proactive risk identification is essential; prior team leadership or ownership of a sustaining or NPI-to-sustaining transition is a strong plus\n\nQualifications\nMinimum requirements:\nBachelor's degree in Electrical Engineering\n5+ years of relevant experience\nATE experience on Teradyne Eagle or equivalent analog ATE (iFlex, LTX, VLCT), although Eagle experience is preferred and is a differentiator\nCharacterization test program and hardware development experience, Production test program and hardware development experience\nStrong technical knowledge of electronic devices and circuits, and Analog test techniques\nData analysis skills using Spotfire, dataPower or equivalent tool based on STDF\nExperience with product engineering activities such as yield improvement and test time reduction\nStrong understanding of the IC product development process, from concept to volume production\nPreferred qualifications:\nAnalog/Mixed signal test techniques and experience\nExperienced with test program and hardware offload to TI offshore manufacturing sites\nDemonstrated strong analytical and problem solving skills\nStrong verbal and written communication skills\nAbility to work in teams and collaborate effectively with people in different functions\nStrong time management skills that enable on-time project delivery\nDemonstrated ability to build strong, influential relationships\nAbility to work effectively in a fast-paced and rapidly changing environment\nAbility to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Analog IC Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-02", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25017459", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n  Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\n  This is a great opportunity to be part of an established team that's continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electronics, mobile computing and communications.\n\nIn this role, responsibilities may include:\n\nLead an Analog IC design team with product ownership and responsibility from definition to release to manufacturing\n\nDirect, guide and participate in activities of a research or technical design function responsible for designing, developing, modifying and evaluating electronic parts, components, integrated circuits for a variety of applications\n\nMake assignments for team members, providing design guidance as needed, developing schedules and monitoring progress throughout the project\n\nEvaluate intermediate and final results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout\n\nCollaborate with Design Verification teams during the pre-PG phase of a project to ensure completion of all technical tasks before PG\n\nWork with systems engineers, application engineers and marketing to prepare product briefs, datasheets, application notes and assisting in the definition of the product to meet customer needs as well as contributing to roadmap formulation and new concept creation\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nInterface and lead discussions with the customer and/or TI field sales/field applications teams to understand customer designs, problems and support as required\n\nActively participate in hiring, developing and evaluating personnel to ensure efficient operation of the organization and growth of the individuals into leader\n\nQualifications\nMinimum requirements:\nBachelor's degree in Electrical Engineering\n3+ years of relevant experience\n\nPreferred qualifications:\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\nStrong verbal and written communication skills\nAbility to quickly ramp on new systems and processes\nDemonstrated strong interpersonal, analytical and problem-solving skills\nAbility to work in teams and collaborate effectively with people in different functions\nAbility to take the initiative and drive for results\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Analog IC Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-02", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25017670", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n  Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\nAnalog Design Engineer Success Profile: Success Factors & Descriptions\n\nCircuit Design, Analysis & Execution\n\n  Designs, and implements analog, analog-mixed signal & integrated circuits (ICs) that enable new TI products and customer solutions.\n\n  Leads IP and chip architecture, schematic design & simulation (pre- and post-layout) basis the specification requirements.\n\n  Applies deep understanding of analog fundamentals, process technologies, and circuit design techniques.\n\n  Delivers robust, innovative, and efficient designs aligning with customer needs.\n\n  Meets project milestones while adapting to changing requirements.\n\n  Develops and executes experiments to debug and improve designs.\n\n  Able to understand & use relevant software tools (MATLAB, Cadence, etc.) for drawing schematics, simulations, data processing, Modeling etc.\n\n  Understands and applies the concepts of feedback loops, design reliability, stability analysis, and debug analysis\n\n  Demonstrates a high sense of ownership on design decisions & accountability while executing technical developments.\n\n  Understands and applies TI’s NPDE Methodology; Proactively identifies and addresses risks in design & execution\n\n  Strives to improve execution efficiency using automation\n\n  Innovation, Problem Solving & Continuous learning\n\n  Stays abreast of industry trends and emerging Circuit topologies & architectures. Proactively proposes and implements innovative solutions\n\n  Demonstrates curiosity to go beyond assigned tasks to learn and understands the entire product development\n\n  Applies classroom/theoretical knowledge to real-world problems and expands expertise across application areas.\n\n  Engages in deep technical discussions and “what if” scenarios\n\n  Keeps the end-user in mind, anticipates market/application needs\n\n  Able to explain complex concepts and innovations to technical and non-technical stakeholders\n\n  Actively pursues professional development, continuous learning and shares knowledge with peers.\n\n  Seeks feedback; Responds constructively to failures or missed goals\n\n  Cross-functional Collaboration\n\n  Works with cross-disciplinary teams (Systems, layout, test, validation, design verification, digital design) across the full product lifecycle—front end to back end.\n\n  Participates & contributes to design reviews, product definition, requirements capture, bench characterization etc.\n\n  Builds trust and rapport across teams; listens to and incorporates diverse perspectives\n\n  Brings together input from different functions to optimize the design for layout ease, test, manufacturability and reliability\n\n  Demonstrates accountability and professionalism in team settings; proactively resolves technical and interpersonal obstacles.\n\n  Documents and Communicates results clearly through presentations and technical reports to diverse stakeholders.\n\n  Table 2: Development actions\n\n  Success Factor\n\n  On the Job Development Actions\n\n  Circuit Design, Analysis & Execution\n\n  • Deepen technical expertise by leading the design and simulation of a new type of analog IP block or circuit, progressing from schematic through post-layout validation.\n\n  • Seek and integrate feedback from a senior designer or mentor on design approach, simulation methodology, and results interpretation.\n\n  • Enroll in (or complete) advanced coursework or internal training on data processing, modeling, or new simulation tools.\n\n  • Lead a root-cause analysis for a failed lab or silicon debug, document & share learnings\n\n  • Build proficiency in modeling and data analysis by working on real design datasets.\n\n  • Take initiative in a root cause analysis of a complex silicon or system-level failure, documenting lessons learned and sharing them with the broader team.\n\n  Innovation, Problem Solving & Continuous learning\n\n• Work directly with a system, product or applications engineer to better understand customer requirements, and map at least one design decision to a specific end-user or market need\n\n  • Regularly review recent technical literature and patents related to analog/mixed-signal design.\n\n  • Propose process, topology and, methodology improvements and pilot it in a project.\n\n  • Volunteer to present a “tech talk” or lead a brainstorming session on emerging architectures.\n\nCross-functional Collaboration\n\n• Develop and deliver a clear technical report or presentation summarizing your project’s impact for both internal and external stakeholders.\n\n  • Lead or actively participate in a cross-functional design review (with layout, test, and verification teams), focusing on surfacing and resolving at least one major interdisciplinary issue.\n\n  • Practice and strengthen communication by presenting a design challenge and solution to both technical and non-technical audiences, seeking feedback on clarity and impact.\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in Electrical Engineering\n\n2-5 years of relevant experience\n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Engineer-PDN", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-02", "url": "https://careers.arm.com/job/bengaluru/engineer-pdn/33099/100083846784", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview:\n Arm's Solutions Engineering we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies.\nResponsibilities:\nYour responsibilities will involve developing challenging electrical signoff methodologies. These methodologies will balance accuracy and yield on silicon.\nThe following are the immediate challenges we will be working on as a team:\nWe will develop robust flows & Methodologies to support PDN Sign-Off Methodologies on the latest nodes and applying the latest SoC 2.5D and 3D technologies.\nWork on some of the Sign-Off methodologies like Static, Dynamic Power Distribution analysis, Electro-migration, ESD Analysis etc.\nDevelop and deploy new methodologies to improve implementation efficiency and results.\nSupport and develop detailed implementation analysis and data-mining methodologies.\nConverting R&D concepts into real implementation solutions.\nEnable our partners to achieve the best possible quality of results.\nRequired Skills and Experience :\nBachelors or Master’s degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields.\n1-2 years of proven experience in ASIC Implementation, EM IR, PDN, Physical design and STA on advanced process nodes\nPossess a high level of dedicated, initiative and problem-solving skills.\nExperience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams\nPrevious experience in and knowledge of the entire IC design flow, from RTL through to GDS2.\nExperience working closely in top and block level Design Implementation and Sign-off flows.\nProven programming and scripting skills eg. Tcl, Perl, Python, Make\n“Nice To Have” Skills and Experience :\nKnowledge around Arm based SoCs!\nExperience with a wide range of programming, scripting & data presentation languages Eg. Tcl, sh, csh, make, R, C, C++, Java, JS, HTML, Perl, Python, Ruby.\nExperience with low power design techniques (power gating, voltage/frequency scaling)\n \n#LI-BB1\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Staff Applications Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-09-02", "url": "https://careers.synopsys.com/job/bengaluru/staff-applications-engineer/44408/100063255152", "is_hardware": true, "platform": "talentbrew", "jd_text": "Alternate Job Titles\nStaff Applications Engineer\nTechnical Applications Engineer\n \nWe Are\nSynopsys drives innovation from silicon to systems, enabling customers to develop next-generation AI-powered products. We provide industry-leading solutions across silicon design, IP, simulation, analysis, and design services.\nBy partnering closely with customers across industries, we help accelerate innovation, improve engineering productivity, and deliver differentiated products to market.\n \nYou Are\nYou are an experienced, customer-focused engineer who combines strong technical expertise with disciplined execution. You thrive in dynamic environments, navigate ambiguity effectively, and translate complex design challenges into practical, scalable solutions. You bring a hands-on approach to debugging, automation, and methodology development. You communicate clearly across technical and business audiences, collaborate effectively with customers and internal teams, and take ownership from problem definition through resolution. You are motivated by measurable impact, including improved customer productivity, stronger design outcomes, and successful adoption of advanced Synopsys technologies.\n \nWhat You’ll Be Doing\nPartner with customers to understand technical requirements and solve complex design challenges using Synopsys solutions.\nDrive the deployment, integration, and adoption of Synopsys EDA tools within customer design environments.\nAnalyze design flows, reproduce technical issues, identify root causes, and develop effective solutions or workarounds.\nProvide pre-sales technical support, including evaluations, demonstrations, troubleshooting, and issue resolution.\nCollaborate with R&D, product engineering, and product management to resolve product issues and communicate customer requirements.\nDevelop scripts, automation, and design methodologies that improve quality of results and engineering productivity.\nCreate application notes, best-practice guides, and reusable technical solutions.\nManage assigned customer engagements and technical deliverables with a high level of ownership.\n \nThe Impact You Will Have\nAccelerate customer adoption and effective utilization of Synopsys technologies.\nImprove customer design quality, productivity, and time to market.\nSupport successful product evaluations, design milestones, and production deployments.\nReduce issue-resolution time through structured debugging and cross-functional collaboration.\nExpand Synopsys’ presence within strategic accounts through technical excellence and trusted customer partnerships.\nIncrease team effectiveness through reusable methodologies, automation, documentation, and knowledge sharing.\n \nWhat You’ll Need\nBachelor’s or master’s degree in electrical engineering, Electronics Engineering, or a related field.\nRelevant industry experience in ASIC, FPGA, or SoC design, implementation, or verification.\nHands-on experience with EDA tools across one or more areas, including synthesis, physical design, simulation, timing analysis, formal verification, or functional verification.\nStrong understanding of digital design, SoC architectures, semiconductor design flows, and manufacturing processes.\nProficiency in scripting languages such as Tcl, Python, Perl, or Shell.\nExperience analysing design reports, tool logs, quality-of-results metrics, and complex technical issues.\nDemonstrated ability to develop practical solutions, automation, and design-flow improvements.\nStrong written and verbal communication skills.\nAbility to collaborate effectively with customers, R&D, product engineering, and product management teams.\n \nWho You Are\nCustomer-focused and committed to delivering high-quality technical solutions.\nAnalytical and structured in your approach to problem-solving.\nAccountable for driving technical issues through closure.\nAdaptable in fast-paced environments with evolving priorities.\n \nThe Team You’ll Be Part Of\nYou will join a high-performing Applications Engineering team at the forefront of semiconductor and EDA innovation. The team works closely with customers, R&D, product engineering, and product management to deploy advanced technologies, resolve critical design challenges, and improve customer outcomes.\nOur culture emphasizes technical excellence, customer success, collaboration, continuous learning, and professional growth.\n \nRewards and Benefits\nSynopsys offers a comprehensive range of health, wellness, and financial benefits designed to support employees and their families. Our total rewards include monetary and non-monetary offerings.\nYour recruiter will provide additional details regarding the applicable salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Sr Principal Engineer- Switch Architecture", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-09-02", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Sr-Principal-Engineer--Switch-Architecture_2604365", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nYou will join the high-performance Teralynx Switch Architecture Team, the group responsible for defining the architecture of Marvell’s next-generation data center switch ASICs. This team owns:\n•\tProduct architecture definition\n•\tBehavioral modeling\n•\tPerformance modeling & analysis\n•\tArchitecture validation\n•\tFeature & protocol definition\n•\tCross-functional technical leadership\nYou will collaborate directly with ASIC design, Software, SerDes, firmware, validation, systems engineering, and product teams to bring new switch architectures from concept to silicon and production.\n\nWhy Marvell Is an Employer of Choice\n•\tCutting-edge networking silicon: Work on switch ASICs that define the next era of data center scale-up and scale-out AI cluster interconnects.\n•\tImpact at industry scale: The architectures you design will be deployed across hyperscale data centers globally.\n•\tTechnical leadership environment: Marvell empowers senior engineers to think big, drive cross-functional alignment, and influence long-term product direction.\n•\tCollaborative on-site culture: Daily in-person collaboration accelerates innovation, strengthens technical rigor, and enables rapid iteration.\n•\tStability + growth: Marvell continues to expand in high-growth markets including AI, cloud, carrier networks, optical interconnects, and custom silicon.\nWhat You Can Expect\nAs a Senior Principal Engineer, you will serve as a key technical leader driving architecture and execution for next-generation Teralynx switch products. You will:\nDefine new features, pipelines, and protocols for next-generation data center switch chips.\nDeliver detailed behavioral and performance models to validate architectural decisions and ensure scalability for cloud-scale deployments.\nDrive end-to-end switch architecture from high-level concept through micro-architecture engagement and silicon bring-up.\nPartner with cross-functional engineering teams to ensure architectural intent is delivered through implementation and verification.\nAnalyze tradeoffs across latency, throughput, memory architecture, power, area, and QoS to guide design decisions.\nParticipate in customer-facing technical discussions, aligning product capabilities with real-world use cases and requirements.\nContribute to long-term architectural direction and roadmap planning for the Teralynx product line.\nMentor engineers, share best practices, and elevate architectural rigor across the organization.\n\nWhat You Can Expect\nHigh ownership and visibility in defining and guiding major architectural features of Marvell’s flagship switch products.\nA deep, hands-on role in shaping silicon that scales to the next generation of cloud and AI data centers.\nA highly collaborative on-site engineering culture that accelerates problem solving and innovation.\nOpportunities to work across domains — hardware, software, systems, and customer engineering — broadening your technical influence.\nA stable environment with the resources of a global semiconductor leader, paired with the agility of a fast-moving product organization.\nA compensation and benefits package designed to attract top technical talent.\n\nWhat We're Looking For\nBachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or related field and 15+ years of relevant experience, OR\nMaster’s/PhD with 10–12+ years of experience in semiconductor architecture or ASIC development.\nStrong background designing or architecting complex ASICs, ideally in networking or switch domains.\nExpertise with behavioral and performance modeling, architectural validation, and system-level tradeoff analysis.\nStrong programming skills in C/C++ and Python.\nDemonstrated ability to collaborate effectively across geographies and multi-disciplinary engineering teams.\nExcellent communication skills with the ability to explain complex architectural concepts clearly and persuasively.\nPreferred / Nice-to-Have\nExperience with multi-die / chiplet architectures, die-to-die interfaces, or advanced packaging.\nFamiliarity with switch pipeline architectures, buffer management, traffic engineering, and programmable datapaths.\nExperience engaging with customers or standards bodies.\nPublished papers, patents, or previous leadership roles in architecture teams.\n\nThis role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.\nAdditional Compensation and Benefit Elements\nWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\n\nInterview Integrity \nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\n\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\n\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n\n#LI-RV1", "jd_status": "stored"}, {"title": "Memory Layout Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-09-02", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Memory-Layout-Design-Engineer_R026993", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nJob Requirements:\n  - Minimum 3+ years of experience with strong layout knowledge.\n  - Bachelor's degree required.\n  - Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - CALIBRE & Hercules).\n  - Strong layout knowledge in submicron processes (e.g., A14, 2nm, 3nm, 5nm, 7nm).\n  - Experience in digital layout (Standard cell, Memory, I/O); analog layout experience is a plus.\n\nJob Description:\n  - Understand and apply layout guidelines, new process rules, and technical requirements for good quality layout.\n  - Manage scheduling, timelines, and layout floor-planning.\n  - Responsible for start-to-end deliverables with quality within the planned schedule.\n  - Adapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the SOC/library team.\n\nSkill Set (Memory):\n  - Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes.\n  - Experience with Cadence Layout tools (VIRTUOSO XL, VXL, or EXL) and CALIBRE verification tools.\n  - Proficiency in floor-planning, hierarchy layout, and chip integration.\n  - Understanding of memory architecture, RC requirements, and the ability to plan signal and power based on layout guidelines.\n  - Knowledge of AI, automation in layout, Script Programming, and SKILL Programming is a plus.\n  - Ability to lead, train junior engineers, and manage projects effectively.\n  - Good knowledge of memory layout topology; experience with memory compilers is a plus.\n  - Ability to lead new technology reviews to document layout methodologies, flows, and guidelines.\n  - Self-reliant with the ability to work both independently and collaboratively.\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "IO and Mixed Signal Circuit Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-09-02", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/IO-and-Mixed-Signal-Circuit-Design-Engineer_R026864", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nWork as part of Mixed Signal and IO Library Development team in Central Engineering. Primary responsibilities include:\nDesign and verification of IO interfaces and mixed signal blocks such as POR, process monitors, voltage/temperature sensors, crystal oscillators etc.\nRTL coding, synthesis and verification of digital wrappers that interface with analog circuitry\nInterface with both custom and P&R layout engineers and oversee physical design and verification.\nDevelop functional models and perform timing characterization of these cells.\nDirectly interface with end customers to understand their requirements, come up with specifications and implement circuit designs that support them.\nCreate necessary infrastructure and generate test vectors to support silicon validation of these blocks on test chips.\nWork with test engineers to support silicon validation either on ATE or on the bench.\nDevelop accurate documentation in the form of datasheets, application notes and integration guides\n\nSkills and Qualifications Required:\nEducational requirements: MSEE with a minimum of 5-10 years of hands-on experience in independently designing mixed signal circuits especially in newer CMOS technologies such as 5nm or 3nm\nMust have experience in designing analog circuits such as PLLs, LDOs, Bandgap references, ADCs or DACs--knowledge of AMS methodology and analog circuit modeling will be a plus\nMust be proficient with Cadence Virtuoso Schematic Capture and ADE along with an excellent knowledge of spice based simulators such as Spectre and/or Hspice\nWorking knowledge of LVS, DRC along with EM/ESD verification tools such as Totem/Pathfinder/PER\nStrong written and oral communication skills in English to be able to work effectively across geographies as well as to be able to interface with end customers\nRequire proficiency in automation using shell scripting or any other languages such as SED, AWK, TCL or PERLˇ\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Chip Integration Design Lead", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-09-02", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Chip-Integration-Design-Lead_R026777-6", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nDesign Lead for Chip Integration working closely with other functional teams (block design, DV, IP, PD, uArch, SW, Board Design) to execute complex cutting edge ASIC chips. Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use.\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Sr . STA / Timing constraints Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-01T17:35:00+00:00", "url": "https://global-external-amd.icims.com/jobs/91610/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. KEY RESPONSIBILITIES: Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Ensuring constraints quality (SDC) using industry tools like Fishtail , GCA Well versed with timing signoff methodology and corner definitions Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts) Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip. Ensuring full chip level Interface timing closure along DRV closure Generating timing ECO using tools DMSA/Tweaker and leading subsystem/Subchip/FC timing closure PREFERRED EXPERIENCE: 5+ years of experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. Experience with analyzing the timing reports and identifying both the design and constraints related issues. Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc. Experience in timing closure of high frequency blocks & subsystems (> Ghz range ) Strong Understanding of DFT modes requirements for timing signoff Good understanding of physical design flow and ECO implementation. Strong understanding of SDC constraints, OCV,AOCV,POCV analysis. Strong TCL/scripting knowledge is mandatory.   ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior ASIC Physical Design Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-01T17:09:00+00:00", "url": "https://global-external-amd.icims.com/jobs/91608/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.     THE ROLE: The focus of this role in the AECG ASIC organization is to lead physical design for next generation ASICs that meet Engineering, Business and Customer requirements. Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. THE PERSON: AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanning and physical design flows for best in class ASIC solutions. KEY RESPONSIBLITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Deft at Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus. Tasks to include Full Chip Level Floor planning, Bus / Pin Planning, feed-thru planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, Physical Verification and Sign Off Identify complex technical problems, break them down, summarize multiple possible solutions, Drive and hands-on flow development and scripting PREFERRED EXPERIENCE: 8+years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: BS or MS degree in in Electrical Engineering or Computer Science. 8+years of experience in physical design role leading to an understanding of RTL to GDS development. #LI-SR4 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "ASIC Physical Design & Implementation Lead", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-01T17:05:00+00:00", "url": "https://global-external-amd.icims.com/jobs/91607/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. AECG ASIC Physical Design & Implementation Engineer :   THE ROLE: The focus of this role in the AECG ASIC organization is to lead physical design for next generation ASICs that meet Engineering, Business and Customer requirements. Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. THE PERSON: AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanning and physical design flows for best in class ASIC solutions. KEY RESPONSIBLITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Deft at Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus. Tasks to include Full Chip Level Floor planning, Bus / Pin Planning, feed-thru planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, Physical Verification and Sign Off Identify complex technical problems, break them down, summarize multiple possible solutions, Drive and hands-on flow development and scripting PREFERRED EXPERIENCE: 12+years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: BS or MS degree in in Electrical Engineering or Computer Science. 12+years of experience in physical design role leading to an understanding of RTL to GDS development. #LI-SR4 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Firmware Engineer Tech Lead", "company": "Astera Labs", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-01T14:56:09-04:00", "url": "https://job-boards.greenhouse.io/asteralabs/jobs/4726996005", "is_hardware": true, "platform": "greenhouse", "jd_text": "Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\n\nFirmware Engineer Tech Lead\n\nBangalore, India\n\nAstera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\n\nRole Overview\n\nThe mission of this role is to architect and develop firmware and microcontroller subsystems for Astera Labs’ SoC and systems products. As a Firmware Engineer Tech Lead you are responsible for implementing the major differentiating features of Astera Labs’ products. As such, firmware is considered equally important to the hardware, and the firmware team is often customer-facing accordingly to ensure the needs of the customer are fully comprehended. \n\nBasic Qualifications \n\nStrong academic and technical background in electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required, and a Master’s is preferred. \n\nMinimum 5 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. \n\nExperience developing firmware to execute in on-chip microcontrollers as well as C-language software development kits (SDKs) to execute on system management controllers (e.g. BMC). \n\nExperience working with logic designers to architect and verify HW-SW interfaces on complex SoCs. \n\nProfessional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer meetings in advance, and to work with minimal guidance and supervision. \n\nEntrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! \n\nRequired Experience \n\nExperience working on PCIe-Express (Gen-3 and above) protocol, including working with analyzers and exercisers to debug protocol issues. \n\nHigh level of proficiency in C (preferred) or C++, including development of C-based SDKs. \n\nHigh level of proficiency in Python for automating pre-processors/post-processors and FW QC. \n\nWorking knowledge of software/firmware build environments, gcc/Make, Doxygen, and GitHub.  \n\nFamiliarity with SoC interfaces to common IP blocks such as PCIe Controllers, DDR Controllers, NVME Controllers, AMBA/AHB interfaces, on-chip memory interfaces, and other similar interfaces. \n\nPreferred Experience \n\nExperience with PAM4 SerDes with working knowledge of Tx/Rx equalization, adaptation, CDR and SerDes link budgets. \n\nHands-on experience with PCIe devices in Server, Storage, and/or Networking equipment.  \n\nExperience developing embedded firmware for PCIe or Ethernet Switch products. \n\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.", "jd_status": "stored"}, {"title": "SDC, Synthesis and STA Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-01T09:31:00+00:00", "url": "https://global-external-amd.icims.com/jobs/91694/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. SDC, Synthesis and STA Engineer   THE ROLE: The focus of this role is to plan and execute the front end implementation of IPs and its closure. This involves ownership of SDC development, SDC generation, verification, promotion/demotion and equivalence checking. The role might also epxand to (if needed) synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure. Co-ordinate with design team and PNR teams. Guide team members on technical issues.   KEY RESPONSIBILITIES:  Main responsibility is to own constratins, SDC developement for IPs, SS and SoCs. Including SDC generation, verification, promotion, demotion and equivalence using third party or self built tools. Additonal responsibilities for front end implementation of IPs might include synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure Prior experience with Lint, CDC and RTL & Netlist based static checks is a plus Collaborate with designer and PNR teams to achieve closure. Understand duration required, plan and execute as per schedule. Complete quality delivery for synthesis and timing closure. Debug and resolve technical issues   PREFERRED EXPERIENCE:  Existing SDC, constraints development with or without using fisthail, excellicon or TCM. Experienced in synthesis, LEC, CLP and timing closure Preferred top level or SOC level experience Have handled blocks with complex designs, high frequency clocks and complex clocking complete understanding of timing constraints, low power aspects and concepts of DFT Have debug experience to solve issues. Interst in AI, Scripting and automation   ACADEMIC CREDENTIALS:  Bachelors with 8 years of experience or Masters degree with 6 years of experience in Electrical Engineering #LI-AB1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "SDC, Synthesis and STA Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-01T09:29:00+00:00", "url": "https://global-external-amd.icims.com/jobs/91693/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. SDC, Synthesis and STA Engineer   THE ROLE: The focus of this role is to plan and execute the front end implementation of IPs and its closure. This involves ownership of SDC development, SDC generation, verification, promotion/demotion and equivalence checking. The role might also epxand to (if needed) synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure. Co-ordinate with design team and PNR teams. Guide team members on technical issues.   KEY RESPONSIBILITIES:  Main responsibility is to own constratins, SDC developement for IPs, SS and SoCs. Including SDC generation, verification, promotion, demotion and equivalence using third party or self built tools. Additonal responsibilities for front end implementation of IPs might include synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure Prior experience with Lint, CDC and RTL & Netlist based static checks is a plus Collaborate with designer and PNR teams to achieve closure. Understand duration required, plan and execute as per schedule. Complete quality delivery for synthesis and timing closure. Debug and resolve technical issues   PREFERRED EXPERIENCE:  Existing SDC, constraints development with or without using fisthail, excellicon or TCM. Experienced in synthesis, LEC, CLP and timing closure Preferred top level or SOC level experience Have handled blocks with complex designs, high frequency clocks and complex clocking complete understanding of timing constraints, low power aspects and concepts of DFT Have debug experience to solve issues. Interst in AI, Scripting and automation   ACADEMIC CREDENTIALS:  Bachelors with 8 years of experience or Masters degree with 6 years of experience in Electrical Engineering #LI-AB1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Staff Engineer, Physical Design", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-09-01T08:26:50.167000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000146650520-staff-engineer-physical-design", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Renesas India is seeking an experienced Senior Staff Physical Design Engineer to lead subsystem- and block-level physical implementation and closure for complex hierarchical SoCs at advanced technology nodes. This role requires deep expertise in timing, congestion, power integrity, and clocking methodologies, along with strong cross-functional collaboration skills. While this role does not own SoC-level physical design, it plays a critical role in aligning subsystem implementation with overarching SoC strategies.\nKey Responsibilities\nLead block- and subsystem-level physical design closure, including timing closure, congestion mitigation, power integrity, and overall physical implementation quality\nCollaborate closely with SoC-level physical design teams to align on clocking strategies, floorplanning intent, and integration requirements, without direct ownership of SoC-level execution\nApply deep understanding of clocking methodologies to ensure subsystem-level clock domains integrate cleanly into the broader SoC clock architecture\nDevelop, refine, and scale subsystem closure methodologies, flows, and automation, improving predictability, quality, and execution efficiency\nMentor and guide physical design engineers within subsystem teams, promoting best practices, technical rigor, and methodology adoption\nWork cross-functionally with RTL design, STA, power, verification, and backend teams to ensure smooth handoffs and robust closure\nProactively identify, assess, and mitigate physical design risks, coordinating closely with SoC teams to manage impacts and drive solution. \n\n6+ years of experience in physical design, with a strong focus on subsystem-level closure for complex hierarchical SoCs\nStrong expertise in:Timing closure and constraint management\nCongestion analysis and resolution\nPower integrity and power-aware physical implementation\nBlock and subsystem-level physical design flows\n\nSolid understanding of SoC-level floorplanning and clocking methodologies, including:Clock domain partitioning\nClock tree architecture\nSkew management\nClock gating\n\n(Candidate is expected to collaborate effectively at the SoC level, not lead these activities.)\n\nBTech or MTech in Electronics and Communication, Electrical Engineering, Computer Science, or a related field\n \nHands-on experience with industry-standard tools such as:Synopsys ICC2, Fusion Compiler, PrimeTime\nCadence Innovus, Tempus, Certus\nSignoff and analysis platforms\n\nProficiency in scripting and automation using Tcl, Python, and/or Perl\nDeep knowledge of end-to-end SoC design flows, with strong collaboration experience across timing, power, clocking, verification, and backend teams\nStrong understanding of low-power design techniques and power-aware implementation methodologies\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "DFx-DV Lead", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-09-01T05:42:00+00:00", "url": "https://global-external-amd.icims.com/jobs/91481/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. SMTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning PREFERRED EXPERIENCE: Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.) Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-AA1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Staff Silicon Verification Engineer - Bengaluru", "company": "Graphcore", "location": "Bengaluru, India", "date_posted": "2026-09-01T02:42:15-04:00", "url": "https://job-boards.greenhouse.io/graphcore/jobs/8759454002", "is_hardware": true, "platform": "greenhouse", "jd_text": "Silicon Verification Engineer\n\nMultiple roles across different levels\n\nGraphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. \n\nAs part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing.  \n\nThe verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The silicon verification engineer is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery.\n\nResponsibilities\n\nVerification planning, specification and closure of functional coverage\n\nProviding feedback to architects\n\nTest generation and failure diagnosis/triage\n\nContributing to shared verification infrastructure\n\nEnsuring good communication between sites\n\nEssential skills:\n• Verification experience in relevant industry\n• Proven leadership and planning skills\n• Highly motivated, a self starter, and a team player\n• Ability to work across teams and programming languages to find root causes of deep and complex issues\n• Experience of the verification process applied in CPU and/or ASIC environments\n• System Verilog, Python, C++, Linux\n\nDesirable skills:\n• UVM\n• SVA\n• Assembly languages\n• LLVM, GCC\n• DVCS e.g. Git\n• SGE or other DRMS\n• XML and XPath/XSLT\n• Web programming – HTML/DOM, Javascript, SQL  \n\nBenefits:\n\nIn addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.", "jd_status": "stored"}, {"title": "Senior Silicon Verification Engineer - Bengaluru", "company": "Graphcore", "location": "Bengaluru, India", "date_posted": "2026-09-01T02:42:02-04:00", "url": "https://job-boards.greenhouse.io/graphcore/jobs/8759472002", "is_hardware": true, "platform": "greenhouse", "jd_text": "Silicon Verification Engineer\n\nMultiple roles across different levels\n\nGraphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. \n\nAs part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing.  \n\nThe verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The silicon verification engineer is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery.\n\nResponsibilities\n\nVerification planning, specification and closure of functional coverage\n\nProviding feedback to architects\n\nTest generation and failure diagnosis/triage\n\nContributing to shared verification infrastructure\n\nEnsuring good communication between sites\n\nEssential skills:\n• Verification experience in relevant industry\n• Proven leadership and planning skills\n• Highly motivated, a self starter, and a team player\n• Ability to work across teams and programming languages to find root causes of deep and complex issues\n• Experience of the verification process applied in CPU and/or ASIC environments\n• System Verilog, Python, C++, Linux\n\nDesirable skills:\n• UVM\n• SVA\n• Assembly languages\n• LLVM, GCC\n• DVCS e.g. Git\n• SGE or other DRMS\n• XML and XPath/XSLT\n• Web programming – HTML/DOM, Javascript, SQL  \n\nBenefits:\n\nIn addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.", "jd_status": "stored"}, {"title": "Senior Silicon Logical Design Engineer - Bengaluru", "company": "Graphcore", "location": "Bengaluru, India", "date_posted": "2026-09-01T02:41:47-04:00", "url": "https://job-boards.greenhouse.io/graphcore/jobs/8759523002", "is_hardware": true, "platform": "greenhouse", "jd_text": "About Us\n\nGraphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. \n\nAs part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies.\n\nJob Summary\n\nWorking within the logical design team, the silicon logical design engineer is responsible for a wide range of logical design tasks. The team is responsible for delivering the Microarchitecture and RTL design to implement the chip architecture specification for Graphcore Silicon, working closely with other engineers within the Silicon team. The successful candidate will be responsible for helping the team deliver high quality micro-architecture and RTL for Graphcore chips, working within the logical design team and with the broader Silicon team to ensure we meet the company objectives for Silicon delivery. \n\n Responsibilities and Duties\n\nIntegrate IP and subsystems into top-level SoC designs\n\nDevelop and maintain build and configuration environments\n\nPerform synthesis, linting, CDC/RDC, and timing checks at the SoC level\n\nSupport verification and physical design teams through clean interface hand-offs\n\nDebug and resolve integration-related issues across multiple hierarchies\n\nContribute to the continuous improvement of integration flows and automation\n\nProducing high quality microarchitecture and other documentation\n\nEnsure good communication between sites to maintain consistent working practises\n\nCandidate Profile\n\nEssential skills:\n\nLogical design experience in relevant industry\n\nExperience range 4-8 years in Semiconductor Industry/Product development exposure.\n\nBe highly motivated, a self-starter, and a team player\n\nAbility to work across teams and debugging issues seen to find root causes\n\nDegree in Computer Science, Engineering or related subject\n\nAbility to script in Python and/or TCL for automation and to solve design issues\n\nSystemVerilog\n\nKnowledge of digital design flows\n\nDesirable skills:\n\nProcessor design\n\nApplication specific blocks\n\nHigh-speed serial interfaces\n\nComplex third-party IP integration\n\nArithmetic pipeline design\n\nFloating-point design\n\nDesign for test\n\nSynthesis\n\nTiming Analysis\n\nProject Planning\n\nPower Integrity\n\nSilicon transistor\n\nBenefits:\n\nIn addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.", "jd_status": "stored"}, {"title": "CPU Design Verification Principal Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-01T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720894575", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n\nQualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement.\nRoles and Responsibilities\no  Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling.\no  Work closely with design/verification teams within CPU to develop comprehensive test plan.\no  Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus.\no  Verify power intent through use of methodologies like UPF.\no  Work closely with system architects, software teams and Soc team to validate system use cases.\no  Work closely with emulation team to enable verification on emulators and FPGA platforms.\no  Debug and triage failures in simulation, emulation and/or Silicon.\nMinimum Qualifications:\n• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\nOR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\nOR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.BE/BTech degree in CS/EE with 4+ years’ experience.\no  Experience in power management verification.\no  Implementation of assembly and C language embedded firmware.\no  Experience in C/C++, scripting languages, Verilog/system Verilog.\no  Strong understanding of power management features in CPUs and CPU based Socs.\no  Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.\nPreferred Requirements:\no  Good Understanding of CPU architectures and CPU micro-architectures.\no  In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture\no  Experience with advanced verification techniques such as formal and assertions is a plus\no  Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Verification Engineer / Lead Verification Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-01T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720901582", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nWe are seeking a Senior Verification Engineer / Lead Verification Engineer with 7+ years of experience in ASIC/SoC verification to drive verification and validation of complex IPs and SoCs across simulation, emulation, and FPGA prototyping environments. The ideal candidate will possess strong expertise in SystemVerilog/UVM, a solid understanding of RTL design, and hands-on experience with emulation and FPGA-based validation platforms.\n\nKey Responsibilities\n· Develop and execute verification plans for IP, subsystem, and SoC-level designs.\n· Build reusable verification environments using SystemVerilog, UVM, assertions, scoreboards, and coverage models.\n· Drive functional verification, regression execution, debug, and coverage closure.\n· Debug RTL, testbench, and system-level issues across simulation, emulation, and FPGA platforms.\n· Support software-driven validation, pre-silicon bring-up, and system-level verification.\n· Enable and support emulation and FPGA prototyping environments.\n· Collaborate with design, architecture, firmware, and software teams to ensure product quality and schedule execution.\n· Drive automation, verification methodology improvements, and mentoring junior engineers.\n\nRequired Qualifications\n· Bachelor's or master’s degree in electrical/Electronics/Computer Engineering or related field.\n· 7+ years of ASIC, SoC, or IP verification experience.\n\nTechnical Skills\n· Strong expertise in SystemVerilog, UVM, SVA, constrained-random verification, functional coverage, and verification closure methodologies.\n· Good understanding of Verilog RTL design, ASIC/SoC flows, CDC, reset verification, and low-power concepts.\n· Strong programming and scripting skills in C/C++, Python, and Tcl/Perl/Shell.\n· Experience with Git, regression automation, and CI/CD workflows.\n\nEmulation & FPGA Prototyping\n· Hands-on experience with Siemens Veloce/Veloce TBX, Cadence Zebu, Palladium, or equivalent emulation platforms.\n· Familiarity with SCE-MI, DPI-C, transaction-based acceleration, hybrid verification flows, software-driven validation, and co-emulation methodologies.\n· Experience with Xilinx FPGA prototyping and validation flows, including familiarity with AMD/Xilinx UltraScale+ and Versal architectures and Vivado tools.\n\nProtocol Knowledge\n· Experience verifying and debugging one or more industry-standard protocols including LPDDR5/LPDDR5X/LPDDR6, PCIe, Ethernet, USB, UART, I2C/I3C, MIPI C-PHY/D-PHY, AXI, AHB, and APB.\n\nPreferred Qualifications\n· Experience with large-scale SoC verification, emulation, and FPGA prototyping.\n· Familiarity with AI-assisted verification and design methodologies.\n· Experience with software bring-up, system-level validation, and post-silicon debug.\n· Exposure to automation frameworks and AI/Generative AI-based verification productivity tools.\n\nSoft Skills\n· Strong analytical and problem-solving skills with the ability to debug complex system issues.\n· Excellent communication and collaboration skills in a cross-functional environment.\n· Self-motivated, proactive, and capable of working independently with minimal supervision.\n· Ability to lead technical discussions, influence decisions, and mentor engineers.\n· Strong ownership, accountability, and commitment to quality and execution.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Engineer – Synthesized Model IP Design", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-01T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720901781", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nWe are seeking a Staff Engineer with 10+ years of experience in ASIC/SoC design to develop and deliver synthesized IP models for emulation and FPGA prototyping platforms. The ideal candidate will possess strong expertise in RTL design, C/C++ modeling, FPGA implementation, and emulation technologies. The role requires technical leadership, architecture contributions, project planning, and collaboration across design, verification, software, and platform teams.\n\nKey Responsibilities\n· Lead the design and development of synthesizable IP models for emulation and FPGA prototyping platforms.\n· Contribute to architecture and micro-architecture definition, design reviews, and implementation strategies.\n· Develop and optimize RTL implementations using Verilog/SystemVerilog with focus on functionality, performance, area, and timing closure.\n· Develop and maintain C/C++ reference models and ensure alignment with RTL implementations.\n· Drive IP integration, debug, validation, and bring-up activities across simulation, emulation, and FPGA environments.\n· Support FPGA implementation activities including synthesis, timing closure, hardware validation, and performance optimization.\n· Work closely with architecture, verification, software, and system teams to enable platform bring-up and software development.\n· Prepare project plans, estimate schedules, identify technical risks, and drive execution to committed milestones.\n· Mentor 2-4 engineers and contribute to technical guidance, code reviews, and engineering best practices.\n· Drive adoption of automation, AI-assisted design methodologies, and productivity improvements.\nRequired Qualifications\n· Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering, or related field.\n· 10+ years of experience in ASIC, SoC, FPGA, RTL design, or emulation/prototyping domains.\n· Experience delivering complex IP, subsystem, or SoC projects from development through validation.\nTechnical Skills\n· Strong expertise in synthesizable model development, Verilog/System Verilog RTL design, and ASIC/SoC design methodologies.\n· Experience contributing to architecture and micro-architecture discussions and translating specifications into high-quality RTL.\n· Strong C/C++ programming skills with experience developing reference models and validation frameworks.\n· Good understanding of AXI/AHB/APB protocols, CDC, reset architecture, power management, and system-level integration.\n· Experience with Git, CI/CD workflows, and scripting using Python, Tcl, Perl, or Shell.\nEmulation & FPGA Prototyping\n· Hands-on experience with Xilinx FPGA design and prototyping flows, including AMD/Xilinx UltraScale+ and Versal architectures.\n· Experience with FPGA synthesis, implementation, timing closure, debug, and hardware bring-up using Vivado tools.\n· Familiarity with Siemens Veloce/Veloce TBX, Cadence Zebu, Palladium, or equivalent emulation platforms.\n· Understanding of SCE-MI, DPI-C, transactors, transaction-based acceleration, software-driven validation, and co-emulation methodologies.\nProtocol Knowledge\n· Familiarity with one or more industry-standard protocols including LPDDR5/LPDDR5X/LPDDR6, PCIe, Ethernet, USB, UART, I2C/I3C, MIPI C-PHY/D-PHY, AXI, AHB, and APB.\nPreferred Qualifications\n· Experience with large-scale SoC prototyping, software bring-up, and emulation-based validation.\n· Experience with multi-FPGA partitioning and system integration.\n· Familiarity with AI-assisted semiconductor design methodologies and productivity tools.\n· Exposure to HLS methodologies and cloud-based EDA workflows.\nLeadership & Soft Skills\n· Strong analytical and problem-solving skills with the ability to debug complex hardware and system-level issues.\n· Excellent communication and collaboration skills in a cross-functional environment.\n· Experience mentoring junior engineers and leading technical discussions across teams.\n· Ability to plan, prioritize, and execute projects with a strong sense of ownership and accountability.\n· Self-motivated with a focus on engineering excellence, innovation, and continuous improvement.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff ASIC Validation Engineer (Chaz/Characterization))", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-09-01T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/42433569", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nJob Description\nKey Responsibilities:\nLead first‑silicon bring‑up, board validation, and early silicon debug.\nDevelop and complete detailed electrical characterization plans covering DC, AC, parametric, and functional measurements.\nCharacterize high‑speed interfaces such as DDR/LPDDR, SerDes, MIPI, UFS, or custom Micron PHYs.\nPerform post‑silicon electrical characterization of ASIC/SoC/Memory products across process, voltage, and temperature (PVT) corners.\nConduct lab measurements using equipment such as Oscilloscopes, BERTs, VNAs, Spectrum analyzers, Waveform generators, and support tools.\nInvolve in Board design activities with team to gather and place custom requirements as per Chaz.\nPerform signal integrity (SI), power integrity (PI), Jitter, Eye‑diagram, and compliance testing.\nDebug silicon issues related to timing, noise, stability, margin loss, and functional failures.\nAnalyze failures and recommend design, firmware, or test fixes.\nDevelop Python/MATLAB-based automation for measurements, data collection, and analysis.\nProcess large volumes of lab and silicon data to extract trends, margins, and correlations.\nGenerate concise characterization reports with clear conclusions and recommendations.\nWork closely with design, pre‑silicon verification, product engineering, firmware, test, and systems teams.\nCorrelate post‑silicon results with simulation and pre‑silicon expectations to identify root causes of gaps.\nWork closely with Design Team & propose enhancements and design changes to tackle next generation challenges.\nContribute to silicon learning documentation and guidelines for comprehensive Chaz activities.\n\nRequired Qualifications:\n6 to 8 years of Industry experience in High Speed Post Silicon Electrical Characterization Domain\nBachelor’s or Master’s degree in Electrical / Electronics or related field.\nStrong understanding of CMOS fundamentals, analog/digital circuits, and high‑speed interfaces.\nHands‑on experience with High-Speed Post‑silicon electrical characterization.\nDeep knowledge of signal integrity, power integrity, timing analysis, jitter, noise coupling, Channel loss & SerDes.\nLeverage AI-enabled tools and technologies\n\nProficiency in lab equipment operation and debugging methodologies.\nExperience with scripting and automation (Python preferred).\nBackground in (DDR/LPDDR/PCIe), SerDes, or high‑speed PHY characterization.\nFamiliarity with ATE correlation, compliance specs, and JEDEC/PCI-SIG standards.\nExperience owning end‑to‑end characterization of a subsystem or interface.\nProven track record of silicon issue root‑cause analysis and resolution\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Senior Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-01T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719436530", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    3+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n\nPrincipal Duties and Responsibilities:\n•    Applies Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Assists in the assessment of complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "BT - Design Verification Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-01T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720810832", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nQCT's Bangalore Wireless R&D Bluetooth HW team is looking for experienced Wireless HW design verification engineers to work on Qualcomm’s best in class chipsets for mobile phones, wearables and IOT. Candidate will be working with ASIC designs on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, emulation, GLS and Formal techniques. The role also requires deep understanding of the Bluetooth Hardware Architecture. Candidate will require close interactions with Global Design, Systems, SoC, Validation and FW teams for design convergence and required to work with minimal supervision. Candidate must be able to take ownership of IP/Block/Sub-System verification. Incumbent will be analyzing HW design spec and develop a verification test plan/strategy for it, breaking down the work for new features, perform feasibility studies, estimate effort and mitigate risk. The role also required the candidate to mentor new joiners and less experienced colleagues. The candidate will work with design team on RTL debug during Pre-silicon HW development phase.\n\nSkills/Experience:\n3 years to 6 years of strong experience in design verification\nStrong knowledge of HDLs like Verilog, System Verilog\nProven experience of writing efficient constraint random tests\nProven experience of building or maintaining a medium to complex SV/UVM environments\nStrong debugging and analytical skills and independent problem solving ability\nProficient in debugging RTL/TB issues using Verdi or similar tools\nDemonstrate good judgment in selecting methods and techniques for obtaining solutions\nStrong communication skills, both written and verbal, with ability to evaluate and create test plans detailing complex features and relationships\nBachelor’s or Master’s Degree in Engineering in Electronics, VLSI, Communications or related field\n\nMinimum Qualifications:\nBachelor’s Degree in Engineering in Electronics, VLSI, Communications or related field\n6 months of VLSI industry experience in verification\n\nPreferred Qualifications:\nExposure to Bluetooth/BLE Technologies\nKnowledge on scripting languages such as Perl and(or) Python\n\nSkills:\nFunctional Verification, Functional/Code Coverage, SystemVerilog Assertions, Universal Verification Methodology (UVM), Verification IP (VIP) Integration, SoC Integration, Formal checks\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "LPASS Design Verification Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-01T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720156623", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nAdditional Job Description\n\nQualcomm LPASS HW team in Bangalore is part of a worldwide team responsible for developing and delivering Audio solutions which are setting the benchmark in mobile computing industry. The role of LPASS DV Engineer will involve a deep understanding of the HW architecture while getting an opportunity to work with the latest DV tools and technologies.\nIndividual responsibility will include\nDV ownership of one or more features in the Low power audio subsystem(LPASS) core\n\nDeveloping a robust testbench, optimized for the specific feature/DUT\n\nExplore innovative DV methodologies (formal, simulation and emulation based) to continuously push the quality and efficiency of test benches and process improvements.\n\nEnsure a bug free silicon for Tape Out which eventually leads to a superb user experience of Snapdragon based computing devices\n\nFor better understanding of some of our products, please refer to the links below\nhttps://www.qualcomm.com/products/smartphones\nQualcomm Aqstic | Qualcomm\n\nMinimum Qualifications\nMinimum 1 - 2  years of VLSI industry experience\n\nStrong debugging and analytical skills\n\nStrong knowledge of HDLs like Verilog, System Verilog\n\nProficiency in developing SV/UVM based test benches\n\nProficient in debugging RTL/TB issues using Verdi or similar tools\n\nProficient with scripting languages such as Perl and(or) Python\n\nPreferred Qualifications *\nKnowledge of UPF, low power  architecture\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "GPU Functional Verification Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-01T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718158792", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nQualcomm is a company of inventors that unlocked 5G, ushering in an age of rapid acceleration in connectivity and new possibilities. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform its potential into world-changing technologies and products.\nIn the role of GPU Functional Verification Engineer, your project responsibilities will include the following,\nDevelop deep understanding of 3-D Graphics hardware pipeline, feature sets, data paths, block functionalities & interfaces\n\nStrategize, brainstorm, and propose a DV environment, develop test bench, own test plan, debug all RTL artefacts, and achieve all signoff matrices\n\nEngage with EDA vendors, explore new and innovative DV methodologies to push the limits of sign off quality\n\nCollaborate with worldwide architecture, design, and systems teams to achieve all project goals\n\nCurrently, we are looking for candidates who can match one or more of the profiles listed below,\nStrong knowledge of UVM based System Verilog TB Knowledge of GPU pipeline design is a plus, not mandatory Proficiency with formal tools – working knowledge of Property based FV is a plus, not mandatory Strong communication skills (both written and verbal) Most importantly, ability to learn, improve and deliver\nExperience\nMinimum 5 years of Design verification experience\n\nSenior positions will be offered to candidates with suitable years of experience and proven expertise matching the profiles listed above\n\nEducation Requirements\nBE/ME/M.Sc. in Electrical, Electronics, VLSI, Microelectronics, or equivalent courses from reputed universities\n\nSelected candidates will be part of the GPU HW team which is passionate about developing and delivering the best GPU Cores for all Qualcomm Snapdragon SOC products. Qualcomm GPU is an industry-leading solution which is driving the benchmarks in mobile computing industry and the future of mobile AR/VR.\nThe pre-Si verification team in Bangalore is currently heavily involved in the following\nUVM/SV based constrained random test bench for functional verification\n\nSubsystem level TB for complete GPU workload analysis and compliance\n\nEmulation platforms to analyze performance and pipeline bottlenecks\n\nFormal tools – both for reduced time to bug & property based FV sign-off\n\nPower Aware & Gate level simulations to deliver a high-quality GPU implementation\n\nPerl/Python scripts for automation in managing regressions, optimize run time, manage database and bug\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Infra Design Verification Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-09-01T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720403616", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nKey Responsibilities:\nDevelop and maintain UVM-based verification environments for high-speed interconnect protocols (PCIe, CXL, AXI).\nCreate and execute verification plans for high-speed interconnect protocols including PCIe, CXL, AXI, and CHI.\nPerform block-level and top-level verification, including functional coverage, assertion-based verification, and regression testing.\nCollaborate with RTL designers, architects, and validation teams to ensure design correctness and coverage closure.\nWork closely with design and architecture teams to understand specifications and derive verification strategies.\nUse third-party VIPs (e.g., Synopsys, Mentor) for protocol compliance and simulation.\nImplement and enhance scoreboards, agents, monitors, and sequences.\nIntegrate and validate SMMU and Coresight components in Subsystem environments.\nDrive verification closure through coverage convergence and assertion-based verification.\nContribute to performance, power, and cost optimization considerations during verification.\nMentor junior engineers and contribute to verification methodology improvements.\nDebug failures at RTL and gate-level simulations.\nRequired Skills:\nStrong proficiency in System Verilog, UVM, and verification methodologies.\nDeep understanding of PCIe Gen3/Gen4/Gen5/Gen6, CXL 1.1/2.0/3.0, AXI/CHI protocols, and SMMU/Coresight architecture.\nFamiliarity with Synopsys/Mentor VIPs for PCIe/CXL and AMBA protocols.\nExpertise in assertion-based verification (SVA) and coverage-driven testing.\nProficiency in Perl/Python/Tcl scripting for automation.\nKnowledge of power-aware verification (UPF), formal verification, and performance/power optimization.\nExperience with coverage-driven verification and random constraint-based testing.\nExperience with scripting languages like Python, Perl, or Tcl.\nPreferred Qualifications:\nBachelor’s/Master’s/Ph.D. in Electrical, Electronics, or Computer Engineering.\n8–12+ years of ASIC/Subsystem/SoC verification experience.\nExperience with PCIe, USB, Ethernet, or other peripheral protocols is a plus.\nExposure to post-silicon validation and lab bring-up is desirable.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "DFT Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-01", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/DFT-Design-Engineer_JR0286726", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nStrong knowledge and experience in Spyglass DFT, Scan Architecture (SSN Topology), ATPG and various fault models.\nHands on skills to implement JTAG, Memory BIST and Memory Repair (BIRA/BISR) circuitry using industry standard tools.\nHands on experience in DFT verification using Gate Level Simulations with timing annotations.\nHands on experience in solving DFT problems, simulation failures, ATPG coverage improvements and DRC debug.\nGood understanding of timing constraints and DFT mode timing analysis.\nProficiency in RTL coding, shell scripting.\nExperience working with post-Silicon/manufacturing teams on ATE, including debugging and resolving issues.\n\nQualifications:\nB.E/B.Tech/M.E/M.Tech in Electrical/Electronics/Communication Engineering with 2+ years of DFT experience.\n          \n\nJob Type:\nIntel Contract Employee\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Senior Design Engineer - Post Silicon Validation", "company": "Lattice", "location": "Pune, India", "date_posted": "2026-09-01", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Pune-India/Senior-Design-Engineer---Post-Silicon-Validation_R-103157", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nDo you have a passion for invention and self-challenge? This position gives you an opportunity to learn and participate in one of the most\ncutting-edge projects that Lattice’s Silicon Engineering team has embarked upon to date.\nWe are validating building blocks in FPGA on board level to ensure functionality and performance aspect of Design intent. FPGA consists of\nvarious IPs as a building block such as SERDES(PMA/PCS), Memory DDR(DDR4, LPDDR4, DDR5 etc), DPHY, PLL, DSP, Fabric, I/O etc.\nAs a Silicon Design Validation engineer, you will have an opportunity to learn and train yourself on how to validate one/or many of the building\nblocks within the FPGA. And also, you will be able to acquire knowledge on process/methodology required for validating certain IPs from\nplanning to completion. While you are working on those, you will be exposed to cutting edge equipment and advanced boards as well as\nVarious SW/tools/scripts.\nWhat you’re going to be exposed to and learn:\nThe ideal candidate is highly motivated in developing a career in Silicon Design Validation engineering. You will get significant exposure and\ntraining in the following areas:\nChance to learn FPGA and it’s build block such as SERDES(PMA/PCS), Memory DDR(DDR4, LPDDR4, DDR5 etc), DPHY,\nPLL, DSP, MIPI, Fabric, I/O etc but not limited.\n•\n• Validate and characterize various IPs from silicon arrival to release to production.\n• Develop validation and characterization plans for certain IP, bench hardware and software.\n• Develop test logic RTL to achieve intended validation/characterization test.\nDrive new silicon product bring-up, validation, debug to asses IP functionality/performance. Characterizing data sheet\nparameters. Analyzing the measured data with statistical view. Data sheet preparation etc.\n•\nServe as the central resource with design, verification, manufacturing, test, quality and marketing/apps as the product(s) move\nSilicon arrival to product release.\n•\n• Supporting customer issues as required to resolve issues found after product release\nYou Have…\n• 5+ years of experience\n• Electrical Engineering degree with a strong desire to pursue an engineering career in Silicon Design Validation\nKnowledge in High Speed Serdes Interface characterization and protocol compliance testing such as\nPCIe/Ethernet/SDI/CoaXpress/JESD204, MIPI D-PHY, MIPI CSI/DSI-2, USB and DisplayPort/HDMI etc.\n•\n• Knowledge in high speed board design and signal integrity evaluation/debug.\n• Knowledge in Verilog/VHDL and design implementation using FPGA development tools.\n• Knowledge in test automation development using programming languages such as Python, Perl.\n• Knowledge of statistical analysis concepts and use of analysis tools such as JMP, R.\n• Exposure on bench equipment for device characterization such as BERT, VNA, Oscilloscopes, Protocol Exerciser/Analyzers.\n• Exposure on FPGA(emulation/prototyping etc)\n• Strong written and verbal communication skills to work with cross-functional team\n• Self-motivated and proactive with critical thinking.\n• Good problem solving and debugging skills.\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Lead Product Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-09-01", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Product-Engineer_R56136", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nCadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.\n\nThe Cadence Advantage\n\nThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.\n\nCadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.\n\nThe unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success\n\nMultiple avenues of learning and development available for employees to explore as per their specific requirement and interests\n\nYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.\nJob responsibilities:\n\nPerform Product Engineering work for Genus Synthesis Solution (Genus), a logic synthesis software used for synthesizing a design described in a high-level language into logic gates, to achieve best-in-class Power, Performance & Area (PPA) for latest digital ASICs\nUnderstand the internal flow within the Genus for newly developed features and verify the correctness and perform experiments to determine an optimal solution\nSolve new and challenging problems in physical aware synthesis space with the goal to bridge the gap between logic synthesis and place and route\nSupport the field engineers in Cadence Design Systems, Inc. and its customers in using Genus. In addition, interface between R&D and customer as the first line of support for the R&D and the customers\nProvide support to verify the interoperability of Genus with other digital logic software tools within Cadence Design Systems, Inc. to provide seamless flows\nUnderstand the future requirements of the software by interfacing with the internal and external customers of Genus and document the Product Requirement Specifications (PRS) for newly developed features using the standard documentation software\n\nPreferred Qualifications:\nExperience in design and EDA with an emphasis on Cadence tools of Synthesis, Physical Design & timing closure at 20nm or below nodes\nPrior Designer, Product Engineering or Application Engineering experience in digital implementation, especially synthesis\nUnderstand industry challenges in digital implementation & sign off domain with exposure to 28nm & below foundry process nodes\nIndustry experience with EDA tools in the IC digital implementation flow, preferably on Genus and Innovus\nExperience in Logic Design and Synthesis, Formal Verification, Low Power design, Physical Design and Timing Closure for block level and top level designs\nAutomation skills using Perl, Tcl and shell scripting essential\nKnowledge of HDL – Verilog or System Verilog is preferred\nMust have logic design and timing closure skills\nStrong analysis skills required to debug complex timing closure, logical and physical design problems. Ability to perform root-cause analysis to suggest solutions to customers and provide feedback to R&D\n\nQualifications\nBE/BTech/ME/MS/MTech or equivalent\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Lead Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-09-01", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Design-Engineer_R56130-2", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nAnalog Mixed-Signal Lead Design Engineer (T3) – SerDes \n\nPosition Summary \n\nWe are seeking an Analog Mixed-Signal Lead Design Engineer (T3) to develop high-speed, low-power SerDes transceivers for data-center, networking, AI, and high-performance computing applications. The engineer will translate system requirements into silicon-ready circuit architectures and collaborate with the architecture, digital, layout, verification, signal integrity, and post-silicon teams. \n\nKey Responsibilities \n\nDesign and verify high-speed SerDes blocks, including TX drivers, serializers, RX front ends, CTLEs, samplers, comparators, ADCs, DACs, PLLs, DLLs, clock dividers and distribution networks, regulators, bias circuits, and calibration loops. \n\nTranslate link-level requirements into circuit specifications and optimize performance across PVT, mismatch, aging, and extracted parasitics. \n\nDevelop behavioral models and support mixed-signal and top-level verification. \n\nCollaborate with layout and signal-integrity teams on physical implementation, channel/package effects, and post-layout signoff. \n\nSupport tapeout, silicon bring-up, characterization, debug, and production release. \n\nDocument results and participate in technical design reviews. \n\nRequired Qualifications \n\nB.S. in Electrical Engineering or a related field with 3+ years of relevant experience, or an M.S. with 1+ years. \n\nStrong analog CMOS, noise, jitter, feedback, signal-integrity, and data-converter fundamentals. \n\nHands-on transistor-level design experience with high-speed SerDes circuits. \n\nExcellent command of Cadence Virtuoso, Spectre, Spectre RF, ADE, parasitic extraction, and mixed-signal verification flows. \n\nStrong analytical, communication, collaboration, and engineering judgment. \n\nPreferred Qualifications \n\nExperience with PAM4/NRZ SerDes, advanced CMOS or FinFET technologies, and standards such as Ethernet, PCIe, or CXL. \n\nMATLAB or C for architecture development; SystemVerilog or Verilog-A for functional modeling; and Perl or Python for automation. \n\nExperience using AI-assisted engineering tools responsibly for design exploration, verification, debugging, documentation, and workflow automation. \n\nCustom analog layout experience is a plus. \n\nLab characterization experience is a plus, along with experience taking mixed-signal IP from architecture through tapeout and silicon validation. \n\nSuccess in This Role \n\nThe ideal candidate combines strong circuit intuition, disciplined verification, ownership, and clear communication to deliver reliable, power-efficient SerDes solutions. \n\n \n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Lead Product Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-09-01", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Product-Engineer_R55860-1", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Title: Lead Product Engineer\nLocation: Bangalore\n\nAbout Us\nCadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. We apply our Intelligent System Design strategy to deliver software, hardware, and IP that turn design concepts into reality. This strategy is supplemented by AI-augmented development practices throughout all our organizations to empower our team to focus on creative problem-solving and innovation. Our customers are the world’s most innovative companies, delivering extraordinary electronic products—from chips to boards to systems—for dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial, and health. Join us and be part of a culture that values innovation, collaboration, and customer success.\n \nPosition Overview\nJoin a growing and dynamic IP team and help lead the development of best in class digital and mixed signal IP products.  This is a tremendous opportunity to work with an experienced team focusing on development of high-performance IP related to protocols such as UCIe, PCIe, USB, DPHY and Ethernet PHYs.\nThe role will be a key member of technical staff in an organization responsible for IP activities including but not limited to Pre-sales engagement with potential customers, Pre-Silicon integration and Post silicon bring-up and test support for the customers. This candidate will be the primary interface between customer and CDNS R&D team. Candidate should possess strong communication skills with ability to manage multiple priorities on day-to-day basis. Ownership of tasks, ability to collaborate with remote teams located worldwide and clear communication of status, are must have attributes in this role.\n \nKey Responsibilities\nResponsible for supporting integration / customization of CDNS SERDES IP subsystems.\n\nAnalyze and resolve complex subsystem application or implementation issues and provide professional guidance to customers.\n\nSupport PHY and controller SOC integration reviews, and integration questions.\n\nPerform RTL and gate level simulations to verify functionality.\n\nAssist customers with gate level simulations and timing closure.\n\nParticipate in development of CDNS documentations and checklists for customers.\n\nSupport post silicon bringup and deployment activities by our customers.\n\nEnhance customer experience by providing prompt updates to customers\n\nAI Incorporation: Leverage AI-powered tools and assistants to enhance productivity, improve decision making, and maintain high-quality customer deliverables. Apply AI-powered analytics tools to extract insights, identify patterns, and generate actionable recommendations from complex datasets. \n\n \nPosition Requirements\nExperience working with UCIe, PCIe, Ethernet, 112G or similar interface IP.\n\nVerilog RTL design and gate level verification experience.\n\nSynthesis and STA experience, back-end experience is a plus\n\nFamiliarity with industry standard DFT flows and test methodologies.\n\nFamiliarity with package and board design.\n\nAbility to read schematics and participate in SI/PI reviews for customer board/package implementation\n\nKnowledge of circuits such as Phase Locked Loops, Tx and Rx Equalizers, ADC’s etc.\n\nFamiliar with concepts of Jitter, Noise, and other non-idealities in circuits\n\n \nSkills & Qualifications\nRequired\nBroad technical background with understanding of standard design flows, tools, and usage of hard and soft IPs.\n\nStrong communication and organizational skills.\n\nExperience with case management systems (SFDC, Jira).\n\nAbility to prioritize cases, anticipate escalations, and manage technical reviews.\n\nHigh-level understanding of technical issues; able to coordinate with subject matter experts.\n\nProactive in gathering feedback and driving continuous improvement.\n\nInfluential and collaborative, able to manage resources across the organization.\n\nSkilled at listening to customer concerns and identifying potential issues.\n\nCommitted to customer satisfaction and timely case closure.\n\nBachelor’s in computer science or electrical engineering + 5 years of related experience, or Masters +3 years of related experience.\n\n \nPreferred\nExperience in memory and/or communication interface IP protocols (DDR, LPDDR, GDDR, HBM, PCIExpress, Ethernet, USB, UCIe, etc).\n\nA general grasp of circuit architecture and design fundamentals\n\nUnderstanding of Analog/Mixed signal design practices\n\nBachelor’s in computer science or electrical engineering + 8 years of related experience, or Masters + 5 years of related experience.\n\nExperience with usage of AI tools in rapid prototyping and development (vibe coding) and general experience with effective AI prompting.\n\n \nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Senior Digital Design Engineer", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-09-01", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Senior-Digital-Design-Engineer_R264658", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nAnalog Devices is seeking a highly qualified Physical Design Engineer to drive the execution and support of physical design projects using world-class EDA tools. In this role, you will own the full-cycle RTL-to-GDSII implementation across complex mixed-signal and digital designs. Additionally, you will  contribute to workflow automation, evaluate emerging EDA tools, and drive methodology enhancements.\n\n    Key Responsibilities\nExecute Full RTL-to-GDSII Flow: Own complete physical implementation, including synthesis, linting, full-chip/hierarchical floorplanning, place-and-route (P&R), clock tree synthesis (CTS), and timing/SI/power closure. [\nImplement ECOs: Generate and execute functional and timing Engineering Change Orders (ECOs) late in the design cycle. \nConduct Sign-Off Analysis: Perform Logical Equivalence Checking (LEC), parasitic extraction, Static Timing Analysis (STA), and Power/EM/IR-drop analysis to ensure robust, silicon-ready design performance.\nDrive Physical Verification: Lead Physical Design Verification (PDV) workflows to deliver DRC/LVS/ERC error-free layouts.\nImplement Low-Power Architectures: Execute UPF-driven low-power designs, perform in-rush current analysis, and deliver comprehensive low-power verification.\nAdvance Flow Automation & AI Innovation: Develop and maintain TCL, Perl, and Shell scripts to automate design pipelines, evaluate emerging EDA tools, and integrate AI methodologies to accelerate the design cycle.\n\n \n    Job Requirements\nEducation: Master’s/bachelor's degree (ME/MTech/ME/BE/BTech) in Electrical, Electronics, or Computer Engineering.\nExperience: 7+ years of production-level physical design implementation experience  (RTL2GDSII) on complex tape-outs using industry-leading EDA tools. \nTechnical Depth: Proven expertise in advanced Synthesis/CDC/RDC/Linting/P&R/LEC/Timing/SI/Power closure flows and late-stage functional/timing ECO implementation.\nLow-Power Expertise: Hands on with UPF-driven low-power design methodologies, including in-rush current analysis and low-power verification.\nAutomation & Innovation: Proficiency in scripting (Python, TCL, Perl, Shell) for automation, with an aptitude for leveraging AI methodologies to accelerate design cycles. \nGood Knowledge in DFT concepts. \n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Architect – AI-Powered Performance Verification Automation", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-09-01", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Architect---AI-Powered-Performance-Verification-Automation_JR2024489", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.\n\nNVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world. As part of this team, you would be working on projects that will help make our next generation visual computing, automotive, GPU, HPC  systems better. You will get to work on high performance CPU and Memory sub-systems, Next-Gen GPUs , NOC based Interconnect Fabric etc. Make the choice to join us today.\n\nWe are looking for a motivated engineer to drive the transformation of performance verification workflows through AI and automation. In this role, you will design, develop, and deploy solutions that accelerate verification cycles, improve coverage, and reduce manual effort across hardware performance verification project lifecycles. You will be at the forefront of redefining how performance verification is done at scale — replacing repetitive manual analysis with intelligent, self-improving automation that helps engineers focus on what matters most.\n\nWhat you'll be doing:\nAutomate verification workflows by building AI/ML-based tools that generate, triage, and analyse performance test cases and results\n\nDevelop intelligent agents that can identify performance regressions, root-cause failures, and recommend corrective actions\n\nIntegrate LLM-based assistants into existing verification infrastructure to enable natural-language querying of results, specs, and coverage data\n\nDesign data pipelines to collect, curate, and label verification data for model training and continuous improvement\n\nCollaborate with verification engineers to understand pain points, define automation priorities, and validate AI-driven solutions against real-world workflows\n\nEstablish metrics and dashboards to measure automation impact (cycle time reduction, coverage improvement, engineer productivity)\n\nStay current with state-of-the-art techniques in generative AI, reinforcement learning, and formal methods as they apply to hardware verification\n\nWhat we need to see:\nB.Tech/M.Tech/PhD in Electrical Engineering, Computer Science, or a related field\n\n3+ years of experience in hardware verification, performance validation, or EDA tool development\n\nStrong programming skills in Python; familiarity with C/C++, SystemVerilog/UVM is a plus\n\nHands-on experience with ML/AI frameworks (PyTorch, TensorFlow, scikit-learn) or LLM APIs (OpenAI, NVIDIA NIM/NeMo)\n\nUnderstanding of performance verification methodologies (benchmarking, profiling, regression analysis)\n\nExperience with CI/CD pipelines and infrastructure automation\n\nWays to stand out from the crowd:\nExperience applying ML to EDA or verification problems (e.g., coverage closure, bug prediction, test generation)\n\nFamiliarity with RAG architectures, prompt engineering, and agentic AI frameworks (LangChain, CrewAI, etc.)\n\nKnowledge of NVIDIA GPU/SoC architecture or similar complex hardware platforms\n\nPublished work or patents in AI-for-verification or related domains\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior Verification Engineer, Switch SoC", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-09-01", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer--Switch-SoC_JR2022315", "is_hardware": true, "platform": "workday", "jd_text": "We are currently seeking Verification Engineer with strong verification fundamentals to work in Switch Silicon group. You'll join a group of hardworking engineers to craft and implement the next generation innovative Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing best high-speed communication devices, delivering the highest throughput and lowest latency! The Networking Chip Design team in India is a new team which is growing at a fast pace.\n\nWhat you'll be doing:\nVerify Switch design's architecture and micro-architecture using advanced methodologies.\n\nBuild reference models, verify and simulate chip blocks/entities according to specifications.\n\nWork closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW.\n\nYou are encouraged to understand the design and implementation, define the verification scope, develop the verification infrastructure, test plans and tests and verify the correctness of the design at SOC level.\n\nUse sophisticated verification methodologies like e-specman, SV-UVM etc.\n\nWhat we need to see:\nBS (or equivalent experience) / MS with 4+ years of experience in design verification.\n\nExposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.).\n\nPerl/python scripting language experience desirable.\n\nWays to stand out from the crowd:\nPrior experience of Ethernet or InfiniBand Switches, and/or smartNICs or DPUs, and/or high-speed interconnects.\n\nStrong debugging, problem-solving and analytical skills.\n\nScripting knowledge (Python/Perl/shell).\n\nGood social skills and ability & desire to work as an excellent teammate.\n\nWidely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com\n\nNVIDIA is committed to encouraging a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Principal Hardware Development Engineer - Signal Integrity", "company": "Nokia", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-09-01", "url": "https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/39937", "is_hardware": true, "platform": "oracle", "jd_text": "Join Nokia's Optical Networks Hardware team and play a key role in shaping next-generation high-speed optical transport platforms. As a Principal Hardware Development Engineer specializing in Signal Integrity, you will drive the design, simulation, validation, and optimization of high-speed interconnects and printed circuit boards supporting advanced 800G and future 1.6T optical networking solutions.\nWorking closely with hardware, PCB layout, mechanical, firmware, and optical engineering teams, you will help ensure industry-leading performance, reliability, and scalability of cutting-edge networking products. Your expertise will contribute directly to the successful delivery of high-speed systems that power the world's critical communications infrastructure.\n\nNILightpath\n\nResponsibilities\nLead signal integrity analysis for high-speed PCB and system designs.\nPerform pre-layout and post-layout SI/PI simulations and validation.\nDefine PCB stack-ups and select appropriate laminate materials.\nAnalyze S-parameters, eye diagrams, crosstalk, jitter, and COM metrics.\nDevelop and validate models for connectors and complex interconnect structures.\nCollaborate with cross-functional teams to optimize system performance.\nSupport laboratory correlation using VNA, TDR, and related measurements.\nDrive SI best practices and technical innovation across development programs.\n\nQualifications\nMust Have\nBachelor's degree or higher in Electronics, Electrical Engineering, or related field.\n12+ years of signal integrity engineering experience.\nStrong knowledge of PCB technologies, construction, and design constraints.\nExpertise with SI simulation tools such as ADS, HFSS, or equivalent.\nExperience using measurement equipment including VNA and TDR.\nProven expertise in PCB stack-up design and material selection.\nStrong understanding of high-speed signaling fundamentals and channel behavior.\nExperience with SI/PI simulations and analysis of eye opening, crosstalk, jitter, and COM.\n \nNice to Have\nExperience with optical module design, including QSFP-DD and OSFP.\nKnowledge of 112G and 224G PAM4 signaling technologies.\nUnderstanding of RF design techniques and structures.\nFamiliarity with EMI/EMC analysis and mitigation.\nExperience with PCB-level hardware design and debugging.\nKnowledge of signal quality impairments such as jitter and wander.\nAbility to navigate technical challenges within dynamic supply-chain environments.\n\nAbout the company\nAdvancing connectivity to secure a brighter world.\n\nNokia is a global leader in connectivity for the AI era. With expertise across fixed, mobile and transport networks, powered by the innovation of Nokia Bell Labs, we’re advancing connectivity to secure a brighter world. \n\nLearn more about life at Nokia.\n\nOur recruitment process\n\nWe act inclusively and respect the uniqueness of people. Our employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.\n\nIf you’re interested in this role but don’t meet every listed requirement, we still encourage you to apply. Unique backgrounds, perspectives, and experiences enrich our teams, and you may be just the right candidate for this or another opportunity.\n\nThe length of the recruitment process may vary depending on the specific role's requirements. We strive to ensure a smooth and inclusive experience for all candidates. Discover more about the recruitment process at Nokia.", "jd_status": "stored"}, {"title": "Program Management Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-01", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25017433", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n  Texas Instruments (TI) is looking for an energetic, service minded leader, who enjoys helping others to succeed by providing team members and clients with motivation and support in a positive and professional work environment as a Program Management Engineer. We are seeking a highly motivated individual who will challenge teammates to achieve flawless execution goals, while maintaining strong working relationships. Success in this role is measured by the ability to grow the number of new products and drive the forecasted return on investment.\n\nResponsibilities include:\n\nLead a cross functional team on the execution of releasing new products and ensuring successful return on investment for every development; the team consists of Design, Marketing, Systems& Applications, Validation, Product& Test Engineering, Firmware/Software Engineering, Manufacturing, Field, and Quality\n\nWork with wafer fabrication, assembly& test sites to guarantee schedule, cost and quality\n\nPlan the project using MS Project from Assess Opportunity Phase to Release to Market and is responsible to make sure the project comes in on budget\n\nProvide clear direction to both, team and external support organizations like device fabrication and assembly and test sites\n\nDrive and motivate all team members critical to the flawless execution of each product and project\n\nProvide weekly and monthly updates to senior management on status of projects, explaining the issues facing a project\n\nInteract with customers in support of project status, key milestones, and deliveries. This includes samples deliveries, special work requests, wafer lot starts and reliability tests\n\nPerform product reliability and characterization of integrated circuits to ensure they meet the product requirement specifications and manufacturing requirements\n\nWork with failure analysis (FA) to determine root cause of any reliability and qualification failures\n\nMaintain thorough and up-to-date project schedules with all related milestones\n\nDevelop and implement Qualification plans\n\nCommunicate weekly to management on status of each project\n\nEffectively coordinate material logistics and shipment/assembly/test prioritization\n\nMaintain Galileo system per new product development guidelines\n\nSuccess will be measured by the ability to grow the number of new products and drive the forecasted return on investment.\n\nQualifications\nMinimum requirements:\n\nMasters in Electrical Engineering, Mechanical Engineering or related engineering degree\n\nXX years of experience with project engineering/management experience on highly complex products/projects\n\nProven leadership capabilities in leading multifaceted global organizations\n\nSuccessful proven track record in indirect management and influence\n\nPreferred qualifications:\n\nAbility to manage multiple projects simultaneously, and set realistic plans based on required tasks with available resources\n\nAbility to effectively coordinate and lead global development teams on projects that include design, silicon fabrications, production test development, qualification and production ramp; Programs will be driven out of multiple global locations\n\nAbility to provide clear direction to both internal teams and external support organizations like device fabrication and assembly sites\n\nKnowledge of device packaging and wafer fabrication process\n\nKnowledge of reliability requirements and tri-temp characterization methodology using statistical analysis\n\nAbility to work in a team environment and understand cross-functional team dynamics\n\nAbility to work with global customers to align project schedules with customers' key milestones\n\nDemonstrated strong analytical and problem solving skills\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nStrong time management skills that enable on-time project delivery\n\nDemonstrated ability to build strong, influential relationships\n\nAbility to work effectively in a fast-paced and rapidly changing environment\n\nAbility to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Design Verification Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-01", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25017435", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n Texas Instruments is seeking Design Verification Engineer. In this role you will confirm the accuracy of designs for analog and mixed signal electronic parts, components, or integrated circuitry for analog and mixed signal electronic equipment and other hardware systems before pattern generation/mask development. The role will require working independently from the product development team who designed the devices to confirm adherence to known design rules, procedures, and best practices. Additional job functions include analyzing equipment to establish operating data and conducting experimental tests and evaluating results to confirm the device meets all requirements in the specifications. You may also run software simulations, selecting components and equipment based on analysis of specifications and reliability. As a Design Verification Engineer you may also review vendor capability to support product development. Requires a BS degree or equivalent experience in the design of equipment, components or circuitry.\n\nQualifications\nMinimum requirements\n\nMinimum education (i.e., bachelor's degree in electrical engineering)\n\nMinimum of XX years of experience\n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Senior Engineer - Physical design", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-01", "url": "https://careers.arm.com/job/bengaluru/senior-engineer-physical-design/33099/100024340160", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Description: In Arm's Solutions Engineering group, our primary focus extends beyond the development of advanced System-on-Chips (SoCs). In the endeavour to deliver a quality silicon we need to ensure all our signoff checks across various domains are diligently performed. Delivering quality silicon leads to quality rewards and every effort and skill is recognized and appreciated at ARM. Our responsibilities also encompass improvising methodologies, influencing EDA tools and build a knowledge base which will help in our product design. Learning and sharing knowledge is part of ARM culture and is very much appreciated and encouraged. If your interested in working with a team of collaborative and smart engineers responsible for validating RTL-to-Gate and Gate-to-GDS implementations, ensuring power intent correctness, and enabling high-quality silicon tapeout\n \nResponsibilities:\nSynthesis, Physical design and implementation of Arm cores, systems and SoCs\nAbility to lead synthesis and constraints development , technical leadership\nAnalyze design timing, area and power to help improve the quality of Arm IP.\nDevelop and deploy new methodologies to improve implementation efficiency and results.\nSupport and develop detailed implementation analysis and data-mining methodologies.\nAutomation , Python knowledge and bringing in faster and efficient execution\nWork with implementation and physical IP RTL design teams to drive analysis and optimization of our IP.\nRequired Skills and Experience :\nMaster’s degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields.\n8+ years of proven experience in ASIC system-on-chip implementation flow from RTL to GDS.\nExperience in Timing Constraints development, Synthesis, Timing Closure\nPossess a high level of dedicated, initiative and problem-solving skills.\nExperience of tape outs of multi-million gate designs on latest technologies\nAbility to develop and work with timing constraints for build and signoff\nThe ability to effectively work alone as well as in a team\nAbility to create trusting relationship and good work environment. Good professional attitude.\nLEC, CLP and ECO implementation knowledge to handle ECO cycles.\n“Nice To Have” Skills and Experience :\nExperience with a wide range of programming, scripting & data presentation languages Eg. Tcl, Shell, Perl, Python.\nExperience with low power design techniques (power gating, voltage/frequency scaling).\nExperience with Verilog RTL design\nUnderstanding of DFT modes and their implications on Physical Design\nLearn quickly new flows and adapt to new developing  environment.\n#LI-BB1\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Staff Software Engineer – SoC SW Productisation", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-01", "url": "https://careers.arm.com/job/bengaluru/staff-software-engineer-soc-sw-productisation/33099/100031425824", "is_hardware": true, "platform": "talentbrew", "jd_text": "Staff Software Engineer – SoC SW Productisation\n \nArm is redefining what is possible in cloud and data center computing. Our Neoverse platforms are helping power a new era of infrastructure – combining advanced silicon with the system software required to turn ambitious technology into production-ready solutions.\nAre you excited by solving complex system-level problems, driving validation strategy and ensuring sophisticated SoC platforms meet the quality standards required for production?\nWe are looking for a Staff Software Engineer in the Infrastructure Solutions Software team in our CE-SW group. This is currently a hands-on technical contributor role, with no line management responsibilities, focused on driving system-level validation and quality for our infrastructure platforms. You will provide technical leadership in validation, develop effective test strategies and automation, and help ensure high-quality delivery across pre-silicon and silicon environments.\nAs the team grows, there may be opportunities for the role to evolve to include team leadership responsibilities.\nCome and make an impact at scale!\nResponsibilities:\nYou will:\nProvide technical leadership in system-level validation, test methodology and automation.\nDevelop test automation and infrastructure, improving tools, frameworks, CI and regression capabilities.\nDrive system-level validation and defect resolution across pre-silicon and silicon environments.\nCollaborate across software, firmware and hardware teams to resolve issues and support product readiness.\nRequired Skills and Experience :\nStrong experience in software testing and system-level validation for SoC, firmware, platform software or embedded systems.\nProven technical leadership, with the ability to guide engineering decisions and influence across teams.\nSolid understanding of test methodologies, automation, CI and regression testing.\nExperience using test coverage, quality metrics and defect management to drive quality.\nStrong debugging, problem-solving and communication skills across software, firmware and hardware.\n“Nice To Have” Skills and Experience :\nKnowledge of server-class SoCs, including RAS, power management, PCI Express (PCIe), Compute Express Link (CXL), memory and virtualization.\nFamiliarity with the Linux kernel, Trusted Firmware-A (TF-A), UEFI EDK II, OpenBMC or Kernel-based Virtual Machine (KVM).\nExperience with automated system validation, hardware test environments, server farms or continuous integration infrastructure\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Engineer- PDN", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-01", "url": "https://careers.arm.com/job/bengaluru/senior-engineer-pdn/33099/100019618288", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview:\nAs a Staff Engineer in Arm's Solutions Engineering group we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies.\nResponsibilities:\nYour responsibilities will involve developing challenging electrical signoff methodologies. These methodologies will balance accuracy and yield on silicon.\nThe following are the immediate challenges we will be working on as a team:\nWe will develop robust flows & Methodologies to support PDN Sign-Off Methodologies on the latest nodes and applying the latest SoC 2.5D and 3D technologies.\nWork on some of the Sign-Off methodologies like Static, Dynamic Power Distribution analysis, Electro-migration, ESD Analysis etc.\nDevelop and deploy new methodologies to improve implementation efficiency and results.\nSupport and develop detailed implementation analysis and data-mining methodologies.\nConverting R&D concepts into real implementation solutions.\nEnable our partners to achieve the best possible quality of results.\nRequired Skills and Experience :\nBachelors or Master’s degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields.\n4+ years of proven experience in ASIC Implementation, EM IR, PDN, Physical design and STA on advanced process nodes\nPossess a high level of dedicated, initiative and problem-solving skills.\nExperience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams\nPrevious experience in and knowledge of the entire IC design flow, from RTL through to GDS2.\nExperience working closely in top and block level Design Implementation and Sign-off flows.\nProven programming and scripting skills eg. Tcl, Perl, Python, Make\n“Nice To Have” Skills and Experience :\nKnowledge around Arm based SoCs!\nExperience with a wide range of programming, scripting & data presentation languages Eg. Tcl, sh, csh, make, R, C, C++, Java, JS, HTML, Perl, Python, Ruby.\nExperience with low power design techniques (power gating, voltage/frequency scaling)\n \n#LI-BB1\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Analog EDA Backend Lead", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-09-01", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25016758", "is_hardware": true, "platform": "oracle", "jd_text": "EDA is a central organization in TI responsible for developing, deploying and supporting EDA methodology, tools, flows and solutions for worldwide TI Businesses. The EDA solutions span across different domains of IC development, covering IP and SoC development. The team supports all Analog and Embedded business groups across worldwide sites. The team’s charter includes definition of differentiated solutions by defining and developing in-house tools, flows and methodologies augmenting the tools available from EDA vendors. The team enables business teams succeed with best PPA and faster time to market deliveries.\n\nAs an Analog EDA engineer in the team, you will be working on below EDA solutions.\n\nWork with cross-functional teams within EDA and internal customers and stakeholders in IP and SoC design teams to define, evaluate, develop, deploy and support new EDA solutions\n\nCollaborate with vendors (Cadence, Synopsys etc) towards tool/flow evaluations, automations, regress these for various process nodes, create training materials and deploy them as worldwide applications.\n\nQualifications\nMinimum Requirements:\nBachelor’s/Master’s degree in Electronics, Electrical Engineering or related field of study\n6+ years of relevant EDA/CAD experience combined with a passion for automation \nPreferred Qualifications:\nGood CMOS circuits basics, analog circuits and simulation experience\nDemonstrated strong analytical and problem solving skills\nAbility to work in teams and collaborate effectively with people in different functions\nAbility to work effectively in a fast-paced and rapidly changing environment\nAbility to take the initiative and drive to results\nSkills to manage time and multi-task at work\nStrong verbal and written communication skills\nTeam-work is imperative in this role\nPreferred Skills/ Experience\n0-2 years of experience in EDA/CAD in Backend Analog Design Tools (Virtuoso, Layout, DRC, LVS, Extraction, Basic simulation, etc )\nProficiency in programming languages and technologies as needed for projects: Python, TCL, Cadence SKILL, Unix, Shell programming etc\nOptional: AI/ML solutions, Compute infrastructure, Data management\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Senior Manager, QA Engineering – Hardware & Firmware", "company": "Lattice", "location": "Pune, India", "date_posted": "2026-09-01", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Pune-India/Senior-Manager--QA-Engineering---Hardware---Firmware_R-103188-1", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nKey Responsibilities\nActively participate in and drive end-to-end solution testing using real hardware/firmware infrastructure, spending hands-on time conducting functional and non-functional testing solutions\nPersonally develop, review, and refine comprehensive QA test plans covering functional, integration, and system-level testing scenarios for both firmware and hardware layers\nDesign and execute black-box and grey-box testing to validate functional requirements, uncover edge cases, and perform deep-level debugging of issues\nDevelop and contribute to test automation frameworks, scripts, and infrastructure; actively code automation solutions for complex testing scenarios\nLead and mentor a Solutions QA team, fostering a culture of technical excellence, quality ownership, and continuous improvement\nEstablish and enforce quality gates and acceptance criteria aligned with product requirements, risk analysis, and business objectives\nCollaborate daily with engineering and design teams to understand implementation details, identify testability challenges, and coordinate comprehensive testing strategies\nPlan, track, and manage QA tasks and team workload, ensuring realistic timelines and resource optimization while maintaining hands-on involvement\nConduct regular status reporting to leadership with quality metrics, test coverage analysis, identified risks, and mitigation strategies\nIdentify and implement process improvements and enhanced methodologies to strengthen testing effectiveness and efficiency\nRequired Qualifications\n10+ years of hands-on QA engineering experience, with 5+ years specifically in hardware or firmware/embedded systems testing, plus team leadership experience\nExtensive hands-on experience with firmware and embedded systems testing, including driver-level, protocol-level, and system integration testing\nDemonstrated expertise in writing and executing functional and non-functional test cases, test automation scripts, and test frameworks\nStrong practical experience with black-box and grey-box testing methodologies, including hardware debugging and root cause analysis\nExtensive hands-on experience conducting end-to-end solution testing using real hardware infrastructure and test benches (not simulation-only environments)\nProven track record of successfully leading and growing high-performing QA teams while maintaining strong technical contributions\nDemonstrated experience in building AI tools for creating test-cases from requirements specification, and test execution using orchestration\nProficiency in test automation languages/tools (e.g., Python, C, Tcl, SystemVerilog) with demonstrated ability to develop sophisticated test frameworks\nStrong project management skills, process ownership mindset, and excellent communication abilities\nBachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent hands-on technical experience\nPreferred Qualifications\nFamiliarity with CI/CD pipelines and DevOps practices in hardware testing environments\nKnowledge of debugging tools and techniques for embedded systems and hardware validation\nExperience with version control systems and test management tools\nUnderstanding of formal verification and simulation-based validation\nAgile/Scrum methodology experience\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Engineer -Memory Layout", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-01", "url": "https://careers.arm.com/job/bengaluru/engineer-memory-layout/33099/100019619312", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview:\nThe Physical IP Division in Arm creates Memory IPs which are extensively used by thousands of SoC designers around the world to design groundbreaking chips. We are currently developing memory fast cache instances on advanced technologies like 14A, 2nm from the leading foundries of the world. The various SRAM solutions are optimized for high speed, low power and high density, to cater to a variety of applications, ranging from Server to mobile and IoT.\nResponsibilities:\nCandidate will be responsible for working on design, margining, characterization, verification and release of Memory instances. This activity will give candidate exposure to different types of memories like Single port/dual port SRAM/Register File; different types of views like Verilog, liberty, schematics, lef and gds; different EDA tools used for the development and verification flow. It will also give candidate opportunity to learn automation techniques which is one of the essential skills in the industry today.\nRequired Skills and Experience :\nQualification & Experience\nBachelors or Master’s Degree in Electronics Engineering with excellent academic credentials\n2-5 years experience in Memory design or characterization.\nEssential Technical Experience\nVery good understanding of SRAM, digital circuits fundamentals and SOC concepts\nGood understanding of device physics\nUnderstanding of computer architecture (optional)\nWorking knowledge of scripting (Shell, TCL) and AI usage\nCharacteristics & Requirements\nHard-working and self-motivated\nQuick learner, good problem solving and debugging skills\nWillingness to be flexible and accept new challenges\nCapable of working as a great teammate or independently\nGood analytical and reasoning skills\nGood interpersonal skills\ncollaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\n \n#LI-BB1\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Principal Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-09-01", "url": "https://careers.arm.com/job/bengaluru/principal-engineer/33099/95385119712", "is_hardware": true, "platform": "talentbrew", "jd_text": "The Systems Media IP group is responsible for the development of Image Signal Processors (ISPs), Display Processors, and Video codecs for deploying within Arm Compute Subsystems for various end markets, including automotive, IoT, and client market segments. Our intellectual property encompasses RTL, reference drivers, tools, and libraries, enabling our customers to build upon our work to create innovative products!\n \nWe are currently looking for creative and enthusiastic design engineers to be part of a diverse team that constantly pushes the boundaries of power, performance, and area across our multimedia IP portfolio, while also generating designs that are robust, maintainable, and deliverable to the extraordinary quality our customers expect. This is a new team with plenty of opportunities to shape its future, and your own growth and career progression.\n \nResponsibilities:\nDepending on prior experience the responsibilities of the role can include:\nOwnership of unit level development or multiple unit hierarchy or technical lead of an overall IP.\nDesign and test new hardware modules to implement innovative imaging algorithms and/or video codecs.\nEngage in all aspect of hardware design including architectural investigations and modeling, specifications, design and simulation, backend implementation support and IP maintenance.\nIdentify cross Media IP process or methodology improvement opportunities, implementing changes to advance the hardware design efficiency.\nCollaborate closely with colleagues in the verification teams, modelling teams, software driver developers, multimedia architects and imaging researchers.\nMentor & support other members of the team\n \nRequired skills and experience:\n15+ years of experience in ASIC RTL design, ideally for Multimedia IP (ISPs, DPUs, VPUs) or related IP (CPU, GPU, interconnect, memory controllers, high-performance peripherals).\nProficiency in System Verilog, Verilog or VHDL.\nExposure to all stages of design: concept, specification, implementation, testing, documentation, and support.\nProficiency in UNIX and scripting languages such as TCL, Perl, Python, or shell scripting.\nPrior technical and/or team leadership skills required for more senior positions.\n \nDesirable skills and experience:\nKnowledge of advanced image processing algorithms, such as local tone mapping, noise reduction, motion estimation, transform coding etc or AI/ML based computer vision algorithms.\nExperience of designing to meet industry standard protocols (e.g. AMBA interfaces, DDR specifications)\nExperience of Functional Safety product development for the Automotive market (applying standards such as ISO 26262 and/or IEC 61508)\nProgramming language, such MATLAB, 'C' or C++\nExperience with SystemVerilog Assertions (SVA) and Continuous Integration flows\n \nIn Return:\n\nYou will get to utilise your engineering skills to build multimedia technologies and influence millions of devices for years to come. You will be able to drive and bring your ideas to a wider audience, while building your technical leadership and influencing skills.\n \nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\n \n \n#LI-SA3\nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Analog Layout Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-09-01", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Senior-Analog-Layout-Design-Engineer_JR0285589", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nDesigns complex layouts of analog signal circuits for a given design specification and runs complete set of design verification tools for process design rules, electron migration, voltage drop (IR), ESD, and other reliability checks on the layouts. Designs and analyzes floorplans, power grid, ESD, bumps, and performs all required verification on the analog blocks. Performs the microfloor planning and detail signal planning of complex analog circuits to meet performance and electrical requirements (shielding, matching) for critical signals to optimize for area, power, RV, and performance. Develops and drives new and innovative analog layout methodologies to improve layout productivity and quality. Collaborates with analog circuit design, process technology, and package design teams to meet design specifications, plan work, and negotiate layout tradeoffs as needed. Troubleshoots a wide variety of issues up to and including design and tool/flow/methodology used in analog layout design.\n\nQualifications:\nAcademic Qualification: BE/B.Tech/M-Tech in Electronics/Electronics and Communication/VLSI Design.\n6 + years of experience with strong VLSI design knowledge, circuit design knowledge, custom/analog layout design and layout validation including DRCs, density, antenna etc.\nExperience in RV, high voltage flows and noise fixes.\nWork experience in Charge pump, LDO, VDC, ADC or similar AMS layouts.\nEDA tools: Virtuoso XL.\nStrong analytical ability, problem solving and communication skills.\nScripting skills is a plus.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Post-Silicon Product Engineer, Silicon Systems Group", "company": "Amazon", "location": "Bengaluru, Karnataka, IND", "date_posted": "2026-09-01", "url": "https://www.amazon.jobs/en/jobs/10523877/post-silicon-product-engineer-silicon-systems-group", "is_hardware": true, "platform": "amazon", "jd_text": "Come join Amazon Devices and work within Amazon Lab126, where top engineers, researchers, and scientists invent, design, and build Amazon's new consumer electronics devices and services. Amazon Lab126 has produced the best-selling Kindle devices, the ground breaking Fire tablets and Fire TV, and the revolutionary Echo.\n\nWe are seeking a seasoned Senior Post-Silicon Product Engineer to lead and execute critical post-silicon validation, characterization, and production ramp activities for our advanced semiconductor products. This role demands a deep understanding of the semiconductor product lifecycle, from initial silicon bring-up to high-volume manufacturing, ensuring product performance, quality, and reliability meet the highest standards.\n\nOur final product is a complete consumer electronics system, not just the silicon. As a Post-Silicon Product Engineer, you'll go beyond traditional product engineering boundaries to address system-level challenges—offering rich opportunities to understand and influence system architecture and end-user performance.\n\nKey job responsibilities\n\nPost-Silicon Validation & Characterization:\n   • Lead the bring-up and characterization of new silicon, ensuring functionality and performance meet design specifications.\n   • Develop and execute detailed validation plans, including defining test methodologies, coverage metrics, and corner conditions.\n   • Define and validate silicon and ATE-level test coverage, ensuring comprehensive validation aligned with customer application scenarios.\n\nData Analysis & Yield Improvement:\n   • Analyze data from WAT, wafer sort, ATE, and system-level tests to identify trends, anomalies, and systematic issues.\n   • Implement automation pipelines for data analysis across the test flow to improve traceability, root-cause identification, and feedback into design and test.\n   • Develop and implement strategies that align test environments and methodologies with defined yield, quality, and performance objectives.\n• Apply advanced data analytics—including regression, correlation, and predictive modelling—to optimize test efficiency and drive yield improvements.\n\nTest Development & Optimization:\n   • Collaborate with design and test engineering teams to develop and optimize test programs for wafer and package-level testing.\n   • Partner with ATE engineers to debug test failures, refine test coverage, and identify limitations in test hardware/software infrastructure.\n   • Lead test time reduction and cost optimization initiatives while maintaining required test coverage and quality standards.\n\nCross-Functional Collaboration:\n   • Collaborate with Design, SoC, DFT, Reliability, Quality, and Manufacturing teams to resolve silicon issues and support successful product ramp.\n   • Lead structured failure analysis and root cause investigations to address quality, reliability, and customer-return issues.\n   • Coordinate with cross-functional leaders to ensure alignment on key product KPIs such as yield, DPPM, quality escapes, and production readiness.\n\nDocumentation & Reporting:\n   • Generate comprehensive engineering reports detailing validation results, failure analyses, and recommended actions.\n   • Maintain accurate records of test methodologies, data analyses, and process changes.\n\nBasic qualifications\n- Bachelor's degree in Electrical Engineering or a related field\n- Experience communicating technical details verbally and in writing\n- Minimum 8 years of experience in post-silicon validation, product engineering, or semiconductor development roles.\n- Strong understanding of semiconductor testing methodologies, including ATE, wafer sort, and SLT.\n- Hands-on experience with silicon bring-up, validation, characterization, and debug.\n- Proficiency in data analysis tools such as JMP, Python, and SQL.\n- Familiarity with statistical methods such as SPC, CPK, DOE, and other yield improvement methodologies.\n- Strong problem-solving skills, including root cause analysis across silicon, package, and system levels.\n- Experience working in high-volume manufacturing environments, supporting NPI (New Product Introduction) to mass production transition.\n\nPreferred qualifications\n- Master's degree in Electrical or Communications Engineering or a related field\n- Experience with reliability testing standards (e.g., HTOL, HAST, TC) and failure analysis methodologies.\n- Knowledge of wafer fabrication and packaging processes.\n- Familiarity with defining test coverage for critical IP blocks and validating against customer use cases.\n- Experience using AWS cloud tools — including Lambda functions, SageMaker, and QuickSight — for data analysis and automation.\n- Exposure to system-level validation, including correlation between silicon behavior and system-level performance.\n- Experience collaborating with SoC Design, DFT, Debug Leads, Reliability, and Quality teams.\n- Strong understanding of customer RMA handling and product sustenance strategies. Experience with end-to-end product ownership from early silicon evaluation through to high-volume production.\n\nOur inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "jd_status": "stored"}, {"title": "Design Engineer II", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-09-01", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Design-Engineer-II_R51106", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nThe role will be a key player in organization responsible for Characterizing and validating Analog and Digital IP based Silicon Solutions at Cadence.\nCandidate should possess strong leadership skills with ability to manage multiple priorities and guide team members on day-to-day lab tests and silicon characterization activities. Ownership of tasks, ability to collaborate with remote teams located worldwide and clear communication skills, are must have attributes in this role.  Coordination with R&D, Marketing teams in defining the scope and delivering the results in time are critical.\nMinimum Qualifications & Professional Experience:\n•            2-10years (with BTech) or 10 years (with MTech) experience in Post-Silicon PHY, Systems Interop and Compliance testing.\n•            5-7 years of management experience leading/mentoring a small team of engineers \n•            Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on Ethernet/PCIe/CXL/UCIe/\n•            Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers.\nProficient with Ethernet, PCIe, UCIe standards and Protocols. Proven experience  to interpret the standard’s specification to develop Electrical and Protocol, Interoperability and Compliance test suites to validate the silicon.\n Ability to isolate the PHY and controller (MAC/PCS) features to test, develop calibration / compliance lab suites and characterize.\nArchitect and design Printed circuit boards in Schematic and layout level. Familiarity with peripheral chips, high speed interface design techniques, Signal and Power integrity checks / analysis and fixes needed to meet the performance requirements.\nExperience in PCIe/UCIe LTSSM states / UCIe Interfaces / Ethernet standards is a plus.\nProven experience in developing lab automation scripts and test result analysis to debug  and root cause silicon failures.\nExpertise in developing ESD/Latchup/ HTOL  tests to  meet industry standards reliability  qualification & specification\nExpert  level knowledge   in Verilog RTL coding for FPGA, python,C/C++\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Electrical Engineer 1", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-09-01", "url": "https://careers.skyworksinc.com/job/Electrical-Engineer-1/78109", "is_hardware": true, "platform": "successfactors", "jd_text": null, "jd_status": "source_unavailable"}, {"title": "Staff Engineer, System Applications Engineer", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-08-31T16:49:18+00:00", "url": "https://jobs.infineon.com/careers/job/563808971906938", "is_hardware": true, "platform": "eightfold", "jd_text": "As a Senior System Applications Engineer in our IoT and Edge AI Solutions team, you will design and deliver system-level projects that showcase how Infineon silicon and software can enable differentiated features in Edge Artificial Intelligence (AI) and Internet of Things(IoT) applications. Projects can include proof-of-concept demonstrations, reference designs, and application specific evaluation /development platforms. You will be part of Infineon’s Consumer, Computing, & Communication (C3) Segment, focused on Edge AI and IoT applications. If you enjoy creating creative system-level embedded solutions to solve real-world problems focused on Edge AI & IoT applications, then apply now! \n\nYour role\nKey responsibilities in your new role\n\nTranslate marketing requirements into technical requirements and specifications \nArchitect hardware for system projects \nWork with project managers to develop engineering project plans \nCollaborate with different groups and partners to deliver hardware-based systems \nCreate technical documentation \nSupport go-to-market activities for solutions including conducting technical training, attending trade shows to demo solutions, and supporting lead customers\n\nYour profile\nQualifications and skills to help you succeed \n\nA Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Electronics and Communication Engineering (required);advanced degree preferred \n5-8 years' experience with embedded system design \nExperience with C, C++ -,,Experience with real-time operating systems (RTOS) such as Free RTOS or Zephyr \nExperience with Embedded software or microcontroller platforms such as Infineon, XMC, PSoC, OPTIGA, Arduino, STM32, iMX RT or Raspberry Pi \nExperience with hardware design and debug skills including PCB schematic review, oscilloscope, logic analyzer, and hands-on board bring-up \nExperience with Wi-Fi, Bluetooth, and modern IoT protocols (Matter,BLE Mesh, Thread) including experience with cloud platforms such as AWS, Azure IoT Hub, or Google Cloud IoT \nStrong communication skills \nCollaborates effectively across different functional groups Preferred Qualifications: \nExperience with Python scripting and data analysis, TensorFlow or PyTorch frameworks \nExperience with model optimization or quantization for embedded AI(TinyML, Tensorflow Lite, etc.) \nPublications, patents, or conference presentations in the embedded AI or IoT domain\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\n\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\numeshdatta.bamrule@infineon.com", "jd_status": "stored"}, {"title": "STA Silicon Design Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-08-31T09:01:00+00:00", "url": "https://global-external-amd.icims.com/jobs/89856/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. MTS SILICON DESIGN ENGINEER  (STA/Timing) KEY RESPONSIBILITIES: Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Ensuring constraints quality (SDC) using industry tools like Fishtail , GCA Well versed with timing signoff methodology and corner definitions Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts) Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip. Ensuring full chip level Interface timing closure along DRV closure Generating timing ECO using tools DMSA/Tweaker and leading subsystem/Subchip/FC timing closure PREFERRED EXPERIENCE: 8+ years of experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. Experience with analyzing the timing reports and identifying both the design and constraints related issues. Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc. Experience in timing closure of high frequency blocks & subsystems (> Ghz range ) Strong Understanding of DFT modes requirements for timing signoff Good understanding of physical design flow and ECO implementation. Strong understanding of SDC constraints, OCV,AOCV,POCV analysis. Strong TCL/scripting knowledge is mandatory.   ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering hip is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions.     ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-AB1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "DDR STA/Timing Engineer (Staff/ Senior Staff)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-31T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720743687", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nResponsibilities:\nSTA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.\n\nTiming analysis, validation and debug across multiple PVT conditions using PT/Tempus.\n\nRun Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.\n\nEvaluate multiple timing methodologies/tools on different designs and technology nodes.\n\nWork on automation scripts within STA/PD tools for methodology development.\n\nGood Technical writing and Communication skills, should be willing to work in cross-collaborative environment\n\nExperience in design automation using TCL/Perl/Python.\n\nFamiliar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus\n\nFamiliar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo.\n\nEducation : B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI.\nPreferred Qualification/Skills\n7 to 13 years of experience in STA/Timing\n\nStrong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling\n\nHands-on experience with STA tools - Prime-time, Tempus\n\nHave experience in driving timing convergence at Chip-level and Hard-Macro level\n\nIn-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,\n\nKnowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)\n\nKnowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation.\n\nProficient is scripting languages – TCL, Perl, Awk\n\nBasic knowledge of device physics\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Sr Eng/Lead Eng/Staff Eng - Hardware Design  - Multiple positions", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-31T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718367214", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. Qualcomm Cloud System Hardware and Validation Engineering develops cutting-edge rack level AI inference solutions for next generation liquid-cooled data centers. As part of its rapid expansion, the team is looking for experienced engineers to join and contribute to the next round of innovative AI products that Qualcomm intends to bring to the market.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nAs a Qualcomm Hardware Engineer, you will:\n\nDesign and develop motherboards/add in cards/modules for Qualcomm new AI System On Chip (SoC)/System In Package (SIP). Primary responsibilities include working with cross functional teams (mechanical, thermal, SI, PTE, regulatory, validation, manufacturing, etc.) for execution of projects from concept to production. Support rack level design and integration of cards, servers and networking switches.\n\nPrincipal Duties and Responsibilities:\n· Develops basic features and components of hardware designs in line with product proposals or roadmaps, under the supervision of more experienced engineers.\n· Applies basic design rules and processes for electronic hardware, equipment, and/or integrated circuitry with minimal supervision from more experienced engineers.\n· Reads device specification sheets and interprets basic details required to design various hardware features with minimal guidance from more experienced engineers.\n· Evaluates devices and documents performance over various operating conditions and configurations.\n· Assists in the assessment of common design features to identify potential flaws (e.g., electrical, mechanical, hardware), compatibility issues, and/or compliance issues under the supervision of more experienced engineers.\n· Documents basic details about materials, components, chipsets, and assemblies for a device, and records important changes to design with minimal supervision from more experienced engineers.\n· Troubleshoots basic issues with product designs.\n· Provides reasonable schedule for own tasks to project lead.\n· Develops understanding of Qualcomm products.\n· Work with ODM on joint design, address technical issues and support mass production\n· Seeks basic knowledge of industry trends, competitor products, and advances in various engineering fields from publicly available information; requires minimal consultation with more experienced engineers to understand and apply advanced concepts.\n\nREQUIRED EXPERIENCE:\n· System/card/rack-level development, including architecture, design, validation, and deployment of enterprise-class hardware platforms. Strengths in any of the following areas:\n\nRack-Level Expertise:\n· Proven experience in rack-level system integration, including chassis, backplane, cabling, airflow, and thermal management across multiple cards/modules.\n· Familiarity with rack-scale power delivery, including PDUs, VRMs, PMICs, and power budgeting across multiple boards.\n· Experience with rack-level diagnostics and bring-up, including debug of interconnects, signal integrity across long traces/cables, and system-level validation.\n· Understanding of rack-level mechanical constraints, EMI shielding, and compliance with data center deployment standards.\n· Collaboration with ODMs/OEMs on rack-level design and manufacturing, including review of mechanical drawings, thermal simulations, and compliance testing.\nBoard-Level Design:\n· Deep knowledge of PCIe cards, motherboards, daughtercards, and backplane signal and power delivery.\n· Expertise in chassis design, airflow optimization, and thermal management.\n· Solid understanding of system software operation from bootloader to OS and application layers.\nComponent Qualification:\n· Experience qualifying PMICs, voltage regulators (VRs), clock buffers, flash memory, and connectors for use in complex card and rack-level designs.\nDesign & Validation:\n· Hands-on experience in dense, high-layer count PCB designs (8–20+ layers).\n· Skilled in PCIe add-in card/module design, debugging in high-performance systems (x86 and ARM).\n· Familiarity with JTAG tools for bring-up and debug.\n· Experience with networking switches and high speed ethernet interfaces\nHigh-Speed Interfaces:\n· Knowledge of high-speed serial I/O (6–10+ Gbps), PCIe Gen5/6, LPDDR4x/5x, DDR4/5, 200/400/800 GbE.\n· Experience with long PCB/cable topologies (0.35–1.5 meter), signal integrity, and compliance with current standards.\n· Ability to debug at packet/protocol level across link, transport, transaction, and command layers.\nMemory & Clocking:\n· Experience with LPDDR4x memory technologies, DIMM layout and validation.\n· Expertise in clock distribution, power distribution, SMBus, PMBus, SPI, PWM/Tach, and BMC integration.\nTools & Collaboration:\n· Proficient in schematic capture and PCB layout tools (Cadence Allegro, Mentor Expedition).\n· Experience with circuit simulation tools (SPICE), signal/power integrity analysis.\n· Skilled in using lab equipment: oscilloscopes, logic analyzers, JTAG, SMBus, serial debuggers.\n· Strong collaboration with ODMs on joint designs, schematic/layout reviews, and compliance to Qualcomm design guidelines.\n\nFirmware & Software:\n· Good understanding of x86 FW/SW stack and firmware architecture.\n· Experience with BMC hardware/software integration and management.\nCompliance & Testing:\n· Familiarity with regulatory, environmental, and compliance testing for rack-level systems.\n\nPREFERRED QUALIFICATIONS:\n· 3 to 15 years hardware engineering/Systems development experience or related work experience.\n· 3 to 15 years of experience with circuit design (e.g., digital, analog, RF).\n· 3 to 15 years of experience utilizing schematic capture and circuit simulation software.\n· 3 to 15 years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, debug tools, etc.\nMinimum Qualifications:\n• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3 to 15 years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.\nMinimum Experience:\n•3 to 15 years of experience in HW board design and System design.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NOC Design - Sr  Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-31T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720429934", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nLooking for an experience Verification Architect/ Engineer, who will be responsible for verification of next generation Infrastructure IPs (DDRSS, Memory Controllers etc.) which goes into System-on-chip (SoC) for smartphones, tablets and other product categories. In this position you will be expected to plan and implement IP/Cluster/Formal verification flows for the Infra IPs. Also expected to coordinate with different Design and SOC teams throughout the IP development cycle.  \n\nJob responsibilities include \nOwnership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage) \nDevelop test plan and test cases to cover design feature set, follow up with stakeholders on code coverage, functional coverage closure at different levels of test bench \nWork closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure \nDebug of regression signatures and identifying bug fixes \nResponsible for Quality sign off and required documentation \nDeveloping/Deploying scripts/tools for validation (Certitude, VC Formal, VPlan) \nDebug and root cause post silicon issues in collaboration with Design, SW and test teams \nWork with SoC level performance modeling team on latency, bandwidth analysis next-generation experiences and drives digital transformation to help create a smarter, connected future for all.\n\nRequired skillset include \nStrong debugging, Analytical and problem-solving skills \nExpertise on UVM based verification  \nKnowledgeable about ARM bus protocols, Virtual Memory concepts, SoC system architecture \nExperience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved \nCommunication and collaboration skills to work with a large world-wide design organization \n\nDesired skillset includes \nExperience in designs optimized for low power - Dynamic clock gating, Logic/ Memory power collapse  \nExperience in verifying designs meeting Automotive Safety Integrity Levels (ASIL) \nProficiency in Scripting languages (Python or Perl) for Automation initiatives, C/C++/SystemC for performance models \nPost-si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage \nQualification : \nBachelor/Master’s Degree in Electronics & Communication / Micro Electronics \n8 Years of Experience in IP verification or related\nExperience with UVM and ARM Bus protocols. \n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NOC (RTL) Design - Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-31T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720362615", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    5+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Silicon Design Validation, Senior Manager", "company": "Lattice", "location": "Pune, India", "date_posted": "2026-08-31", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Pune-India/Silicon-Design-Validation--Senior-Manager_R-100541-1", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nAs a Senior Manager in Silicon Design Validation, You lead a highly motivated team focused on ensuring the quality and performance of advanced semiconductor products. Your role provides strategic oversight and technical direction across the full post-silicon lifecycle, from first silicon arrival to production release.\n \nKey Leadership Areas:\nTechnology Enablement & Learning Culture\nFostering a learning environment where engineers gain hands-on experience with FPGA architectures and foundational IP blocks such as SERDES (PMA/PCS), DDR memory (DDR4, LPDDR4, DDR5), DPHY, PLLs, DSPs, MIPI, Fabric, and I/O subsystems.\n\nValidation/Characterization Strategy & Execution\nOverseeing the validation and characterization of analog, digital, and mixed-signal IPs, ensuring robust coverage from initial silicon bring-up through production qualification.\n\nPlanning & Infrastructure Development\nGuiding the development of validation plans, including bench hardware and software requirements, and ensure the team has the necessary tools and infrastructure to execute effectively.\n\nRTL Development for Test Enablement\nSupervising the creation of custom RTL test logic to support targeted validation and characterization efforts, enabling deeper insight into IP behavior.\n\nSilicon Bring-Up & Debug Leadership\nDriving the bring-up of new silicon products, driving validation and debug activities to assess IP functionality and performance. This includes characterizing datasheet parameters, performing statistical analysis of measured data, and overseeing datasheet preparation.\n\nCross-Functional Collaboration\nActing as the central liaison between design, verification, manufacturing, test, quality, and marketing/application teams, ensuring alignment and smooth transition from silicon arrival to product release.\n\nCustomer Support & Issue Resolution\nProviding leadership in resolving post-release customer issues, coordinating with internal teams to ensure timely and effective solutions.\n\nYou Have…\n15+ years of experience in silicon validation, including 3–5 years in a leadership role.\n\nMaster or Bachelor’s degree in Electrical Engineering with a strong passion for engineering and management in silicon design validation.\n\nProven track record in managing complex validation projects and leading cross-functional teams.\n\nDeep expertise in high-speed SerDes interface characterization and protocol compliance testing (e.g., PCIe, Ethernet, SDI, CoaXpress, JESD204, MIPI D-PHY, CSI/DSI-2, USB, DisplayPort, HDMI).\n\nStrong background in high-speed board design, signal integrity evaluation, and debug.\n\nProficient in Verilog/VHDL and FPGA design implementation using industry-standard tools.\n\nSkilled in test automation development using Python and Perl.\n\nSolid understanding of statistical analysis and tools such as JMP and R.\n\nHands-on experience with bench equipment including BERT, VNA, oscilloscopes, and protocol analyzers.\n\nExposure to FPGA-based emulation and prototyping environments.\n\nExcellent written and verbal communication skills for effective collaboration across teams.\n\nHighly self-motivated, proactive, and strong in critical thinking and problem-solving.\n\nWho Are We?\nAt Lattice, we’re a collaborative and solutions-driven team that values innovation, problem-solving, and having fun along the way. We specialize in developing low-power, programmable logic technologies that power a wide range of applications—from the Edge to the Cloud.\nOur products and solutions span differentiated programmable logic devices, system-level solutions, design services, and IP licensing. As the leader in low-power programmable technology, we help solve complex customer challenges across communications, computing, industrial, automotive, and consumer markets.\nWhat sets us apart is our deep technical expertise, long-standing customer relationships, and commitment to world-class support. Together, we’re enabling a smarter, more secure, and connected world.\n\nJoin Team Lattice…and help us continue to drive innovation that creates a smarter, better-connected world. Together, we enable what’s next.\n\nWhat are you waiting for? Apply today!\nAt Lattice, we believe great engineers come from diverse backgrounds. Even if your experience doesn’t check every box, we encourage you to apply. This role offers a unique opportunity to grow your skills in a supportive environment where learning is part of the journey. With the depth and breadth of knowledge on our team, Lattice is a great place to build your expertise and take your career to the next level\n\n#LI-DNP\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Sr Staff QA/Test Eng(RTL, FPGA backend tools)", "company": "Lattice", "location": "Pune, India", "date_posted": "2026-08-31", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Pune-India/Sr-Staff-QA-Test-Eng_R-101018", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nKey responsibilities:\nVery strong experience and understanding of FPGA backend tools using Radiant, Vivado or any other similar software suite (Synthesis, Synplify, Map, Place and Route, Bitgen, etc.)\nCreate and maintain test suites to ensure that existing and new features targeted for a release in Radiant backend tools for a variety of designs and running them in regression frameworks\nMonitor the regressions – analyse the failures and report them to fix, drive the closure of the observed issue ASAP by working closely with stake holders\nPrepare and execute on test plans for upcoming features / changes in Radiant backend tools etc.\nStrong debugging skills in simulation, hardware\nFocused mindset on automation of the test activities using lates AI offerings\n \nSkill set (Mandatory):\nBS/MS in Electrical, Electronics or Computer Science or Computer Engineering.\n12+ years of experience in EDA / RTL development / verification.\n \nVery strong understanding of FPGA architectures\nGood understanding of Lattice Diamond / Radiant or similar FPGA tool flow\nGood experience with RTL using Verilog to create test designs for testing the backend tools, including complex, customer like scenarios\nStrong verbal & written communication with good experience involving multiple teams spread across geographical locations\n \nSkill set (Preferred):\nAny experience to scripting languages like Python, Perl, TCL\nExperience with high speed I/O (PCIe, DDR)\n\n#LI-DNP\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Sr. Custom Circuit Design Engineer (Memory, FPGA Fabric Designer)", "company": "Lattice", "location": "Pune, India", "date_posted": "2026-08-31", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Pune-India/Sr-Custom-Circuit-Design-Engineer_R-100621-1", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nKey Responsibilities:\nDesign and Development: Development of high-speed and low-power Custom Circuit Designer (ex. Memory, FPGA Fabric Designer). These designs to be implemented in advanced semiconductor technologies, including FinFET and nanometer CMOS.\nSimulation and Verification: Work involves schematic capture, SPICE simulations, and margin and functional verification of major circuit blocks.\nLayout Planning: Oversee layout planning and ensure tight pitch-matched memory layout and area optimized custom layout.\nCollaboration: Work closely with architecture and design teams to define PPA (Performance, Power, Area) and yield targets.\nFull Design Flow: Manage the full design flow, including circuit design, physical implementation, compiler usage, characterization, timing, and model generation.\nInnovation: Bring innovative and revolutionary ideas to life in our products, influencing various parts of our FPGA designs.\nQualifications:\nEducation: Bachelor’s degree in electrical engineering, or a related field. A Master’s is preferred.\nExperience: Over 5 years of experience in memory and custom circuit design, verification, validation, and integration.\nTechnical Skills:Strong knowledge of custom memory design, high speed, low power as well as custom circuit design\nExpertise in high-performance and low-power design techniques.\nFamiliarity with variation-aware design in advanced semiconductor technologies.\n\nSoft Skills: Excellent problem-solving skills, strong communication abilities, and the ability to work collaboratively in a team environment.\nPreferred Qualifications:\nExperience with large density memory cell design for high yield\nKnowledge of semiconductor device fundamentals\nExperience in custom circuit design\n\n#LI-DNP\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Sr. Staff RTL Eng", "company": "Lattice", "location": "Pune, India", "date_posted": "2026-08-31", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Pune-India/Sr-Staff-RTL-Eng_R-100786-1", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nLattice Overview\nLattice Semiconductor (NASDAQ: LSCC) is the global leader in smart connectivity solutions, providing market leading intellectual property and low-power, small form-factor devices that enable more than 8,000 global customers to quickly deliver innovative and differentiated cost and power efficient products.\n\nThe Company's broad, end-market exposure solves customer problems across the network from the Edge to the Cloud for clients in consumer electronics, industrial equipment, communications infrastructure, computing and automotive. Our technology, long-standing relationships and commitment to world-class support enables our customers to quickly and easily unleash innovative solutions to create a smart, secure and connected world.\n\nOur control, connect and compute solutions enable the Internet of Things to operate safely, easily and more autonomously at the edge of the network core. While you may not see our products, you are interacting with them all day, every day. We make your experience smarter and better-connected. Join Team Lattice…and help us continue to drive innovation that creates a smarter, better-connected world. Together, we enable what’s next.\n\nResponsibilities & Skill\nsensAI team at Lattice Semiconductor, innovates and creates solutions to enable edgeAI with programmable low power devices. Our vision is to unleash FPGA to add intelligence to every sensor used in Automotive, industrial and consumer products. As a senior member of the team, you will be responsible for developing and enhancing machine learning engine that infers neural networks on resource constrained devices. You need to bring expertise in machine learning to enable computer vision, robotics, human-machine interaction, or other related domains.\n\nJob Description\nWe are seeking a highly motivated Senior Staff design engineer who will be responsible for design and development of RTL for Machine Learning engine.  You are responsible to implement ML operators efficiently using resources on low power FPGA. You need to bring experience in optimizing data path for high throughput and low latency. Good understanding of neural network accelerators and/or DSP processors is essential to be successful in this job.\n\nRequirements\nKey Skills\nIn-depth experience in designing and developing RTL using Verilog, System Verilog-HDL.\nAbility to carry out functional simulation using industry standard simulation tools such as Xcelium-Cadence, VCS-Synopsys.\nGood understanding of ML operations like convolution.\nArchitect and design RTL for Machine Learning compute engines targeting low‑power FPGA platforms.\nCollaborate with algorithm and architecture teams to translate ML models/operators into efficient hardware micro‑architectures.\nExperience in image processing and DSP algorithms implementation\nDeep understanding of machine learning, data models to optimally map it with hardware.\nExperience in FPGA/ASIC synthesis flow, timing closure.\nWorking knowledge of computer architecture and memory management.\nExperience with C and/or SystemC is a plus\n\nEducation and General:\nBE/MTech/PhD in Electronics, Electrical or Computer Engineering\nMinimum of 14 years (12 years for MTech and 8 years for PHD) experience in RTL design\nIndependent and self-motivated, capable of executing under dynamic environment and uncertainties\nInnovative, problem solver who likes to come up with newer and better solutions for existing problems\nGood cross team communication and technical documentation desired\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Field Application Engineer, Verification", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-31", "url": "https://careers.synopsys.com/job/bengaluru/field-application-engineer-verification/44408/99982548976", "is_hardware": true, "platform": "talentbrew", "jd_text": "Alternate Job Titles\nField Application Engineer, Verification\nSenior Applications Engineer, RTL Signoff\nCustomer Success Engineer, Verification Solutions\nTechnical Application Engineer, Design Verification\nSolutions Engineer, Verification and Low Power\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years deep in RTL verification flows and you have learned that the hardest problems are rarely the ones in the datasheet. They show up three weeks before tapeout when a CDC violation surfaces in a corner case no one thought to model, or when a low power domain interaction breaks in ways the testbench never caught. You live for those moments because solving them well is what keeps chips from respinning.\nYou are equally comfortable reading SystemVerilog assertions, walking a customer through a SpyGlass run, and sitting with an R&D team to explain why a methodology needs to flex for a real design. You do not wait for someone to hand you a script. You write it, test it, and then show the customer how to own it themselves.\nWorking across time zones does not faze you. Neither does jumping into a customer war room when a project is stuck. You know that adoption is not about features, it is about trust, and trust comes from showing up, understanding the problem, and delivering something that actually moves the schedule forward. At Synopsys, you will work with semiconductor teams building the chips that power everything, and what you enable will matter.\nWhat You'll Be Doing\nWork directly with semiconductor design teams across the region to deploy and optimize Synopsys verification solutions including VC SpyGlass, VCS, VC LP, VC Formal, and Verdi\nDebug complex RTL signoff issues in customer designs, CDC violations, lint errors, RDC problems, low power UPF conflicts, and formal property failures, and turn those into repeatable methodology improvements\nPartner with Synopsys R&D and product validation teams to develop new flows, reproduce customer issues, and drive tool enhancements that solve real tapeout blockers\nLead technical engagements during critical project phases, onsite or remote, ensuring customers hit their verification milestones and tapeout schedules\nGather requirements from customer feedback and design challenges, translate them into flow improvements, and work with product teams to prioritize and track delivery\nCoordinate with account managers and technical account managers to shape customer strategies, drive tool adoption, and support business growth across your accounts\nTrain customer engineering teams on verification methodologies, tool usage, and best practices that reduce verification cycle time and improve signoff quality\nThe Impact You Will Have\nEnable customers to close CDC, lint, and low power signoff weeks or months faster by deploying the right methodology at the right time in their flow\nReduce customer respins by catching critical RTL issues early, before they reach gate-level or silicon\nDrive adoption of Synopsys verification tools across new projects and teams, expanding footprint and deepening technical relationships with key accounts\nInfluence Synopsys product roadmaps by surfacing real customer pain points and working with R&D to deliver features that matter\nBuild repeatable flows and reference methodologies that scale across multiple customer projects and design teams\nStrengthen customer confidence in Synopsys solutions by being the engineer they call when something breaks and needs to get fixed now\nContribute to the success of chips powering AI, automotive, mobile, and cloud infrastructure by ensuring verification does not become the bottleneck\nWhat You'll Need\nBE/BTech/ME/MTech in Electronics Engineering, Computer Science, or Microelectronics with 3-5 years of hands-on industry experience in ASIC design or verification\nStrong command of VHDL, Verilog, and SystemVerilog RTL, and a solid understanding of ASIC design and verification flows from RTL to tapeout\nProven experience with RTL signoff flows including linting, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and property checking using static and formal verification tools\nHands-on work with low power verification techniques using UPF or CPF, and experience debugging power intent issues in real designs\nExposure to simulation and verification methodologies including directed tests, constrained random testing, assertions, coverage-driven verification, and gate-level simulation (GLS)\nWorking knowledge of Synopsys EDA tools such as VC SpyGlass, VCS, VC LP, VC Formal, FishTail, or Verdi is a strong plus\nComfort working in ambiguity, you can take a vague customer problem, ask the right questions, and turn it into a clear technical plan\nWho You Are\nYou can walk into a customer meeting, listen to a verification challenge, and sketch out a solution approach on the whiteboard that the team actually believes in\nYou are the kind of engineer who does not just report a tool issue, you create a minimal reproducible test case, propose a workaround, and follow up until it is resolved\nWorking across global teams and time zones does not slow you down, you coordinate effectively, keep stakeholders aligned, and do not let details fall through the cracks\nYou know how to explain a complex CDC violation or formal proof failure to a design lead in a way that makes sense without oversimplifying the technical reality\nYou build relationships by being reliable, when you say you will deliver a flow or a debug session, it happens\nYou are curious about what is coming next in chip design, AI workloads, automotive safety, advanced nodes, and you want to be part of enabling it\nThe Team You'll Be Part Of\nYou will join the Customer Success Group, a global team that partners directly with semiconductor companies to solve high-value verification and design problems. The team works closely with R&D, product validation, account management, and technical account managers to drive adoption of Synopsys solutions and ensure customer projects succeed through tapeout. You will be part of a regional applications engineering team supporting customers across India, collaborating with engineers worldwide, and contributing to methodologies that scale across the business.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Applications Engineering, Staff Engineer - Physical Verification", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-31", "url": "https://careers.synopsys.com/job/bengaluru/applications-engineering-staff-engineer-physical-verification/44408/99982548928", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nOur team is all about delivering high-value solutions to our customers while driving growth. This is an exciting opportunity to be part of the applications engineering team that supports the industry-leading solutions for Physical Verification. The primary focus of the Application Engineer (AE) is to drive increased usage of the product by collaborating with R&D and the Sales team in a dynamic, innovative environment. Some of the tasks include conducting competitive benchmarks and evaluations where they articulate the superiority of our customer’s design team and management. In addition, AE’s deliver customer training, tape-out support, and collaborate on initiatives for product enhancements. The job involves working closely with users/customers and multiple organizations like R&D, marketing, and sales among others.\n\nYou Are\nWe’re looking for an Application Engineer to join a world-class AE team responsible for driving adoption of our industry-leading physical verification solution. In this role, you will be an Applications Engineer who will play a critical role in our TSG Organization enabling the success of our customers in designing advanced chips on leading-edge process technologies. You will provide technical and engineering insight and direction to improving usability, applicability, and adoption of implementation products, platforms, and solutions to meet the customer business needs.\n\nThe candidate is expected to play an effective role in account planning, where they work as part of the account team to develop solutions to customer problems by bringing their technical understanding of the customer needs and issues. You must be effective and proactive at interacting with customer's technical staff and the first or second level management. An important aspect of this job will be to leverage your knowledge and experience of customers' design processes to Synopsys product development teams for future product/solution improvements. Does this sound like a good role for you?\n\nWhat You'll Be Doing\n• Use in-depth product knowledge to provide technical expertise and support for our top customers.\n• Diagnose, troubleshoot, and resolve complex technical issues on customer designs.\n• Work directly with Research and Development (R&D) to develop and implement our technical roadmap, specifications, and validation for improvements and enhancements.\n• Partner with customers and Sales to identify business challenges, develop effective technical solutions, and increase utilization and retention of products on current accounts.\n\nThe Impact You Will Have\nUse in-depth product knowledge to provide technical expertise and support for our top customers.\nDiagnose, troubleshoot, and resolve complex technical issues on customer designs.\nWork directly with Research and Development (R&D) to develop and implement our technical roadmap, specifications, and validation for improvements and enhancements.\nPartner with customers and Sales to identify business challenges, develop effective technical solutions, and increase utilization and retention of products on current accounts.\n\nWhat You'll Need\nBS/MS EE, ECE, CS, CE or related discipline and 5+ years of experience.\nHands-on experience with Physical Verification & usage of tools like ICV, Calibre etc\nExperience with advanced technology nodes.\nExperience with signoff and physical design methodologies.\nExcellent interpersonal and communication skills with a passion for world-class customer service.\n\nWho You Are\nYou can explain a complex runset issue to a customer design lead in a way that makes sense without oversimplifying the technical details\nYou stay calm and focused when a customer escalation lands in your inbox two days before tapeout and you know how to triage, prioritize, and resolve it\nYou are comfortable pushing back on R&D when a proposed feature does not match what customers actually need, and you do it with data\nYou think about the customer's workflow, not just the tool in isolation, and you can see where the friction points are before they become blockers\nYou can present technical content to a room of engineers or to a VP of Engineering and adjust your message without losing clarity\nYou are organized enough to manage multiple customer engagements, internal projects, and R&D collaborations without dropping threads\n\nThe Team You'll Be Part Of\nYou will join a world-class applications engineering team responsible for driving adoption of Synopsys industry-leading physical verification solutions. This team works closely with R&D, Sales, and Marketing to deliver high-value technical solutions to customers and drive growth across strategic accounts. The role is based in Bangalore and you will collaborate with global teams and customers across multiple time zones.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Sr Principal Verification Engineer", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-08-31", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Sr-Principal-Verification-Engineer_R264574-1", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nAnalog Devices is seeking Digital Design Sr Principal Verification Engineer, who will be responsible for design verification of highly integrated solutions and products in a multifunctional team. You will be working on driving real revenue growth on the next generation of Intelligence at the Edge products across multiple products and business units.\nAbout ADI:\nAnalog Devices, Inc. is a leading global high-performance analog technology company dedicated to solving our customers' most complex engineering challenges. We play a critical role at the intersection of the physical and digital world by providing the building blocks to sense, measure, interpret, connect, and power devices and systems. We design, manufacture, test, and market a broad portfolio of solutions, including integrated circuits (ICs), software and subsystems that leverage high-performance analog, mixed-signal and digital signal processing technologies. We embrace a culture of innovation and collaboration to push the state of the art.\n\nAbout the Role\nLead design verification team for SOC or subsystem design pre silicon verification.  The candidate will be responsible for formulating verification strategies, Define verification architecture, Flow, Methodology and leading, driving and completing verification of large integrated products. As a senior team member, it is expected that he/she will lead and influence verification methodologies within both DBU and ADI.   The candidate is also encouraged to participate in cross company technical initiatives as well as patent and publish work where possible.\nResponsibilities\nLead end-to-end SoC verification for complex digital SoCs, driving execution from planning to signoff.\n\nVerify complex microprocessor-based designs, AI/ML accelerators, and high-speed peripherals using advanced verification methodologies.\n\nDefine and drive team execution by planning tasks, tracking progress, and providing technical leadership, mentoring, and guidance.\n\nCollaborate closely with architecture and design teams to define requirements and align on verification deliverables and dependencies.\n\nDrive pre-silicon readiness by aligning with emulation, FPGA, and software teams to cover post-silicon validation scenarios early.\n\nDevelop and execute end-to-end system-level use cases for comprehensive functional validation.\n\nArchitect and implement scalable UVM-based testbenches, DV flows, and methodologies.\n\nDefine and review test plans; ensure closure of functional and code coverage across block, subsystem, and SoC levels.\n\nWork cross-functionally with emulation, FPGA, firmware, and system teams to ensure full-system correctness.\n\nApply formal verification techniques for IP and subsystem-level validation.\n\nLead NoC/interconnect verification and ensure robust data flow across the SoC.\n\nPerform performance verification and system-level analysis across real-world use cases.\n\nDrive innovation in verification strategies to meet aggressive schedules and quality goals.\n\nDefine overall verification strategy based on product requirements and design specifications, leveraging modern techniques such as formal, emulation, portable stimulus, and virtual platforms.\n\nRequirements\nB.Tech/M.Tech with 20+ years of experience in digital pre-silicon verification, including leadership across IP, subsystem, or SoC-level DV.\n\nStrong understanding of SoC/Subsystem architectures with hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development, debugging, and methodology implementation.\n\nProven track record in verification closure using functional and code coverage metrics across block, subsystem, and SoC levels.\n\nExpertise in NoC, bus, and interconnect verification, along with coverage analysis and optimization.\n\nExperience in architecting scalable testbench environments and defining robust DV flows and methodologies.\n\nStrong background in power-aware verification (UPF), including power analysis and optimization.\n\nHands-on experience with formal verification, including flow definition, connectivity, and functional property checking.\n\nSolid protocol knowledge and verification experience across high-speed and low-speed interfaces such as I2C, SPI, Ethernet, UART, AXI/AHB, DMA, and SVI3.\n\nExperience in security and safety verification, ensuring compliance with secure design and functional safety requirements.\n\nFamiliarity with gate-level simulations with timing annotation (GLS).\n\nStrong expertise in test planning, constrained-random verification, assertions, and transaction-level modeling.\n\nGood understanding of processor-based systems (ARM, RISC-V, Tensilica), AI/ML accelerators, and proficiency in C/C++, SystemC, and scripting (Python/TCL/Shell).\n\nExposure to mixed-signal/analog verification (ADC/DAC/PLL/PHY) is a plus.\n\nExcellent communication and leadership skills with the ability to collaborate across global teams and drive verification innovation.\n\nStrong problem-solving mindset with the ability to quickly learn and adopt new technologies\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Applications Engineer - ICV Runset Development", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-31", "url": "https://careers.synopsys.com/job/bengaluru/applications-engineer-icv-runset-development/44408/100006720096", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in the trenches of physical verification, debugging LVS mismatches at 2 a.m. and hunting down obscure DRC violations that block tapeout. The difference between a runset that works and one that causes three weeks of respins is something you understand viscerally, and you are the engineer who catches the edge case before it becomes a customer escalation.\nYou are fluent in the language of foundries, process nodes, and design rules. When a new technology node drops, you do not wait for perfect documentation. You dig into the specs, write test cases, script your way through qualification, and deliver a working rule deck while others are still scheduling kickoff meetings. Perl, Tcl, and Python are not just tools for you, they are how you turn repetitive manual work into reliable automation.\nMentorship matters to you. You have seen junior engineers struggle with the same problems you solved years ago, and you take the time to walk them through it, not just hand them the answer. When a customer calls with a complex layout issue, you can translate their panic into a structured debug plan and explain the root cause in a way that makes sense to both the designer and the FAE.\nAt Synopsys, you will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build.\nWhat You'll Be Doing\nDevelop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond\nWork directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks\nAutomate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases\nDebug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts\nInterface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track\nMentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques\nTrack competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market\n\nThe Impact You Will Have\nEnable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise\nAccelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space\nReduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip\nBuild automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects\nShape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team\nStrengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes\nGrow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards\n\nWhat You'll Need\nB.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline\n5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development\nDeep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools\nStrong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes\nSolid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield\nExperience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus\nFamiliarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms\n\nWho You Are\nYou can take a 500-page foundry design manual and turn it into a working DRC deck without needing someone to hold your hand through every rule\nWhen an LVS run fails with 10,000 errors, you do not panic, you filter the noise, find the root cause, and fix it systematically\nYou are comfortable on a call with a stressed customer two days before tapeout, walking them through a layout issue while keeping them confident the problem will get solved\nMentoring is not a checkbox for you, when a junior engineer asks a question, you take the time to explain the why, not just the what\nYou stay current on process technology and EDA tool developments because you are genuinely curious, not because it is in a performance goal\nYou can manage three runset development projects, two customer escalations, and a foundry qualification cycle at the same time without dropping threads or missing deadlines\n\nThe Team You'll Be Part Of\nYou will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\n#TPG", "jd_status": "stored"}, {"title": "Verification Engineer", "company": "Nokia", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-08-31", "url": "https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/38749", "is_hardware": true, "platform": "oracle", "jd_text": "As Verification Engineer, conducts target-oriented research to support the design, development, integration, verification, testing, and maintenance of hardware, software, and systems. Contributes to the continuous improvement of products and processes, supports customer-specific feature development, and performs integration, verification, and testing (IVT) to ensure system components meet defined requirements and specifications. Maintains laboratory equipment, tools, and test environments.\n\nResponsibilities\nConducted target-oriented research to support hardware, software, and system development.\nPerformed integration, verification, and testing (IVT) of software and hardware components.\nValidated integrated systems against functional and technical requirements.\nSupported the design, implementation, and continuous improvement of products and processes.\nIdentified, analyzed, and resolved verification and integration issues.\nMaintained laboratory equipment, test setups, and verification tools.\nCollaborated with cross-functional teams to ensure product quality and timely delivery.\nDocumented test results, verification activities, and technical findings in accordance with project standards.\n\nQualifications\nYou have:\nBachelor's degree with 5-8 years of relevant experience. \nApplied strong knowledge of communication and networking systems to support verification and testing activities.\nDeveloped and maintained Python-based automation scripts to improve test efficiency and coverage.\nWorked with test automation frameworks to streamline validation and regression testing.\nPerformed data analysis to identify trends, defects, and opportunities for quality improvement.\nIt would be nice if you also had:\nLeveraged AI/ML fundamentals and AI-assisted tools, including LLMs, Copilot, and Cursor, to enhance test generation and troubleshooting.\nTroubleshot complex networking scenarios to identify root causes and validate solutions.\nCollaborated with cross-functional teams to resolve technical issues and ensure product quality.\nDemonstrated a strong learning mindset and adapted quickly to fast-paced, high-technology development environments.\n\nAbout the company\nAdvancing connectivity to secure a brighter world.\n\nNokia is a global leader in connectivity for the AI era. With expertise across fixed, mobile and transport networks, powered by the innovation of Nokia Bell Labs, we’re advancing connectivity to secure a brighter world. \n\nLearn more about life at Nokia.\n\nOur recruitment process\n\nWe act inclusively and respect the uniqueness of people. Our employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.\n\nIf you’re interested in this role but don’t meet every listed requirement, we still encourage you to apply. Unique backgrounds, perspectives, and experiences enrich our teams, and you may be just the right candidate for this or another opportunity.\n\nThe length of the recruitment process may vary depending on the specific role's requirements. We strive to ensure a smooth and inclusive experience for all candidates. Discover more about the recruitment process at Nokia.\n\nAbout the organization\nSome of our benefits:\n\nFlexible and hybrid working schemes\n\nA minimum of 90 days of Maternity and Paternity Leave, with the option to return to work within a year following the birth or adoption of a child (based on eligibility)\n\nLife insurance to all employees to provide peace of mind and financial security\n\nWell-being programs to support your mental and physical health\n\nOpportunities to join and receive support from Nokia Employee Resource Groups (NERGs)\n\nEmployee Growth Solutions to support your personalized career & skills development\n\nDiverse pool of Coaches & Mentors to whom you have easy access\n\nA learning environment which promotes personal growth and professional development - for your role and beyond\n\nLearn about additional benefits in specific countries.", "jd_status": "refreshed"}, {"title": "IO and Mixed Signal Layout Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-08-31", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/IO-and-Mixed-Signal-Layout-Design-Engineer_R026958-1", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nJob Description:\nDesign full custom layouts of I/O libraries and Analog Mixed Signal IP's in planar and FinFET technologies.\n\nDrive critical floor-planning decisions to ensure optimal placement and routing that meets design requirements and performance metric.\n\nPerform comprehensive layout verification to ensure high quality and compliance\n\nComplete ownership from end to end deliverables with quality within the schedule.\n\nAdapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the teams across all sites.\n\nSkills and Qualifications Required:\nB.Tech in Electronics/Electrical engineering with 3+ years of experience\n\nHands-on experience in I/O Library and Analog Mixed-signal IP development and verification \n\nSolid understanding of Planar and FinFET layouts and process technology\n\nIn-Depth knowledge of ESD and Latch-up principles for I/O and Analog layouts\n\nProficiency in using Cadence Virtuoso Layout suite and Siemens CALIBRE verification tools.\n\nExpertise in Layout verifications and debugging: DRC/LVS/ANT/ERC/DFM, LPE, PERC, EM and IR etc\n\nFamiliar with the Physical Design flow: LEF generation and PnR\n\nKnowledge of AI, automation in layout, Script Programming and SKILL Programming is a plus.\n\nExcellent written and verbal communication skills to collaborate with circuit designers and teams across all sites\n\nSelf-motivated, capable of working independently, and a strong collaborative team player.\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Layout Sr. Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-31", "url": "https://careers.synopsys.com/job/bengaluru/layout-sr-engineer/44408/99982548912", "is_hardware": true, "platform": "talentbrew", "jd_text": "to be added.", "jd_status": "stored"}, {"title": "Custom CPU Physical Design Engineer (Lead/Staff/Sr Staff)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-30T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720238161", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\n5 to 16  yrs experience in Physical Design and timing signoff for high speed cores.\n\nShould have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology.\n\nMasters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design.\n\nExperience in leading block level or chip level Physical Design, STA and PDN activities.\n\nWork independently in the areas of RTL to GDSII implementation.\n\nAbility to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc.\n\nKnowledge of low power flow (power gating, multi-Vt flow, power supply management etc.)\n\nCircuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.)\n\nTcl/Perl scripting Willing to handle technical deliveries with a small team of engineers.\n\nStrong problem-solving skills\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Power Infrastructure Engineer", "company": "SiFive", "location": "Santa Clara, California, United States", "date_posted": "2026-08-30", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Santa-Clara-California-United-States/Power-Infrastructure-Engineer_R-101138", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nThe Role:\nA successful candidate will work with the team to develop and deploy methodology and infrastructure to measure and analyze SiFive IP power consumption. \n\nResponsibilities:\nDevelop and deploy power analysis flows, models to collect and analyze power consumption\n\nCorrelate power models with RTL and Silicon\n\nDevelop and deploy power measurement infrastructure\n\nDevelop power models for architecture exploration and development\n\nRequirements:\nMS or PhD in Computer Science / Computer Architecture\n\n8+ years of experience in power benchmarking, analysis and modeling\n\nExperience with power impacts at architecture, logic design, and circuit levels.   \n\nKnowledge of computer architecture of high performance out-of-order CPU designs.  \n\nExperience with ASIC power analysis and optimization.\n\nHands-on expertise with either HW development (RTL/implementation flows, verification/validation, backend flows, FPGA flows) or SW development is a strong plus. \n\nCompetency in software engineering best practices needed to maintain and refactor very large object oriented code bases.  \n\nSelf-starter, fast learner, strong problem-solving skills\n\nPay & Benefits\n\nConsistent with SiFive values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. \n\nFor candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.  The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.\n\nBase Pay Range\n$205,740.00-$251,460.00\nIn addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! \n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in\nUnited States of America\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.\n\nAs an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.\n\nCalifornia residents: please see our job candidate notice for more information on how we handle your personal information and your privacy rights: Privacy Policy Document.", "jd_status": "stored"}, {"title": "Power Infrastructure Lead", "company": "SiFive", "location": "Santa Clara, California, United States", "date_posted": "2026-08-29", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Santa-Clara-California-United-States/Power-Infrastructure-Engineer_R-101133", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nThe Role:\nA successful candidate will leverage their experience to develop and deploy methodology and infrastructure to measure and analyze SiFive IP power consumption.  The candidate will also use this knowledge to guide the architecture, design and PD teams to build energy efficient IPs with the following responsibilities and requirements.\n\nResponsibilities:\nDevelop and deploy power analysis flows, models to collect and analyze power consumption\n\nCorrelate power models with RTL and Silicon\n\nDevelop power models for architecture exploration and development\n\nDevelop innovative methods to predict power of design changes\n\nRequirements:\nMS or PhD in Computer Science / Computer Architecture\n\n5+ years of experience in power benchmarking, analysis and modeling\n\nExperience with power impacts at architecture, logic design, and circuit levels.   \n\nGood knowledge of computer architecture of high performance out-of-order CPU designs.  \n\nWorking experience in guiding trade-off between performance and power to arrive at optimal design.\n\nExperience with ASIC power analysis and optimization.\n\nHands-on expertise with either HW development (RTL/implementation flows, verification/validation, backend flows, FPGA flows) or SW development is a strong plus. \n\nCompetency in software engineering best practices needed to maintain and refactor very large object oriented code bases.  \n\nSelf-starter, fast learner, strong problem-solving skills\n\nPay & Benefits\n\nConsistent with SiFive values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. \n\nFor candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.  The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.\n\nBase Pay Range\n$205,740.00-$251,460.00\nIn addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! \n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in\nUnited States of America\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.\n\nAs an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.\n\nCalifornia residents: please see our job candidate notice for more information on how we handle your personal information and your privacy rights: Privacy Policy Document.", "jd_status": "stored"}, {"title": "Product Power Engineer", "company": "SiFive", "location": "Santa Clara, California, United States", "date_posted": "2026-08-29", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Santa-Clara-California-United-States/Product-Power-Engineer_R-101139", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nThe Role:\nA successful candidate will work across teams to collect, analyze, and optimize design power with the following responsibilities and requirements.\n\nResponsibilities:\nCollect / analyze SiFive IP power consumption. \n\nGuide architecture and design to optimize our design to achieve state-of-the-art power efficiency\n\nCorrelate power models with RTL and Silicon\n\nInnovate ways to improve power analysis flows\n\nRequirements:\nMS or PhD in Computer Science / Computer Architecture\n\n5+ years of experience in power benchmarking, analysis and modeling\n\nExperience with power impacts at architecture, logic design, and circuit levels.   \n\nGood knowledge of computer architecture of high performance out-of-order CPU designs.  \n\nWorking experience in guiding trade-off between performance and power to arrive at optimal design.\n\nExperience with ASIC power analysis and optimization.\n\nHands-on expertise with either HW development (RTL/implementation flows, verification/validation, backend flows, FPGA flows) or SW development is a strong plus. \n\nSelf-starter, fast learner, strong problem-solving skills\n\nPay & Benefits\n\nConsistent with SiFive values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. \n\nFor candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.  The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.\n\nBase Pay Range\n$205,740.00-$251,460.00\nIn addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! \n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in\nUnited States of America\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.\n\nAs an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.\n\nCalifornia residents: please see our job candidate notice for more information on how we handle your personal information and your privacy rights: Privacy Policy Document.", "jd_status": "stored"}, {"title": "Product Power Engineer", "company": "SiFive", "location": "Santa Clara, California, United States", "date_posted": "2026-08-29", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Santa-Clara-California-United-States/Product-Power-Engineer_R-101450", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nThe Role:\nA successful candidate will work across teams to collect, analyze, and optimize design power with the following responsibilities and requirements.\n\nResponsibilities:\nCollect / analyze SiFive IP power consumption. \n\nWork with architecture and design to optimize our design to achieve state-of-the-art power efficiency\n\nCorrelate power models with RTL and Silicon\n\nInnovate ways to improve power analysis flows\n\nRequirements:\nMS or PhD in Computer Science / Computer Architecture\n\n3+ years of experience in power benchmarking, analysis and modeling\n\nExperience with power impacts at architecture, logic design, and circuit levels.   \n\nGood knowledge of computer architecture of high performance out-of-order CPU designs.  \n\nWorking experience in guiding trade-off between performance and power to arrive at optimal design.\n\nExperience with ASIC power analysis and optimization.\n\nHands-on expertise with either HW development (RTL/implementation flows, verification/validation,backend flows, FPGA flows) or SW development is a strong plus. \n\nSelf-starter, fast learner, strong problem-solving skills\n\nPay & Benefits\n\nConsistent with SiFive values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. \n\nFor candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.  The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.\n\nBase Pay Range\n$178,848.00-$218,592.00\nIn addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! \n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in\nUnited States of America\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.\n\nAs an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.\n\nCalifornia residents: please see our job candidate notice for more information on how we handle your personal information and your privacy rights: Privacy Policy Document.", "jd_status": "stored"}, {"title": "Product Owner Hardware Web Experience", "company": "Infineon", "location": "Bangalore", "date_posted": "2026-08-28T11:21:32+00:00", "url": "https://jobs.infineon.com/careers/job/563808971903050", "is_hardware": true, "platform": "eightfold", "jd_text": "Drive the end-to-end digital customer journey on Infineon.com by owning and enhancing web experiences such as evaluation boards, the Evaluation Board Finder, and related developer-focused tools. Partner with cross-functional stakeholders to define product strategy, prioritize web enhancements, analyze customer behavior and web performance, and deliver innovative, user-centric solutions. Lead the development and optimization of web functionalities through data-driven decisions, customer validation, and continuous improvement, ensuring exceptional user experience, business impact, and product success.\n\nYour role\nKey responsibilities in your new role\n\nOwn the complete end-to-end customer journey on infineon.com(covering web functionalities for products such as evaluation boards, the Evaluation Board Finder tool, and related digital experiences)\nUnderstand developer needs through data analysis, CX reports and other tools and develop solutions to meet those needs\nIdentify changes in user behavior and adapt the web product approach as needed\nContinuously collect and review new requirements from stakeholders(e.g., divisions, marketing, sales, and product teams)\nCoordinate with management to adjust web plans and road map as needed\nLead the development of new web functionalities, including ideation, prototyping, and customer validation, with a focus on user experienced quality assurance\nManage, refine, and prioritize the web features product back log continuously\nAccountable for product release, and ensuring product success\nAnalyze and evaluate web data to identify optimization opportunities and develop A/B testing plans\nCoordinate stakeholder communication on business goals, market opportunities, and priorities in the web area.\nCollaborate closely with other web owners and central departments(e.g. UX/UI, CX, Analytics, IT)\nContinuously improve process quality and evaluate web progress and user satisfaction\nMonitor new trends and technologies\nContinuously monitor changes in the Infineon competitive environment\nServe as a resource for less experienced Product Owners Web\n\nYour profile\nQualifications and skills to help you succeed \n\nProven track record as a Product Owner in agile environments, ideally for customer-facing web platforms, portals, or digital tools in high-tech/B2B context\nPrior engineering role at a semiconductor company, with a proven track record of supporting customers to achieve design wins (securing adoption of company products into customer designs and driving them through to production)\nHands-on development of production-level hardware systems, including board-level design, system integration, validation, and successful transition to volume manufacturing.\nBonus multiplier: Proven involvement with AI-based acceleration technologies for hardware design-such as AI-augmented EDA flows, agentic AI for chip optimization, accelerated power/performance analysis, generative AI in design workflows, or AI-powered digital twins/ portals that compress design cycles and enable faster hardware innovation.\nMBA from a reputable business school (top-tier preferred).\nExcellent communication and stakeholder management skills\nAbility to analyze data and make informed decisions\nStrong problem-solving and prioritization skills\nExperience with A/B testing and experimentation\nKnowledge of web analytics tools and methodologies\nAbility to work in a fast-paced environment and adapt to changing priorities\nStrong collaboration and teamwork skills\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "DFT Architect", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-08-28T05:26:00+00:00", "url": "https://global-external-amd.icims.com/jobs/86626/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are seeking a seasoned SoC Architect with expertise or significant interest in System Architecture. You have had significant success driving architecture, product roadmaps and product requirements. You are meticulous about Power, Performance and Area while driving schedule and managing cost. This senior role will stretch you as you lead architecture teams in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design teams, marketing, and business unit executives. THE PERSON: You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: Define product features and capabilities, close architecture, and micro-architecture requirements, drive technical specifications for SoC and IP blocks to meet those requirements, and provide technical direction to execution teams Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features, optimizing for performance and power Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements Knowledge sharing and other contributions to Platform & System Architecture As an overall product owner, responsible for architecture analysis and technical solutions for marketing/feature change requests Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs Support Post-Si teams for Product Performance, Power and functional issues debug/resolution PREFERRED EXPERIENCE: Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-system, Fabrics, CPU/GPU coherency, Multimedia, I/O subsystems, Clocks, Resets, Virtualization and Security Experience analyzing CPU, GPU or System-level Micro-Architectural features to identify performance bottlenecks within different workloads Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture, logic design, and circuit levels Excellent communication, management, and presentation skills. Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies ACADEMIC CREDENTIALS: Bachelor’s or Master’s degree in related discipline preferred LI-PM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Staff Engineer - PCB Design", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-08-28T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/42834371", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nOur vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\nJob responsibilities:\nTechnical Expertise: Should possess very strong PCB technical knowledge on high-speed layouts with HDI technology and have very good experience with DDR4/DDR5, PCIe4/5/6, ONFI4.0/ONFI5.0, SMBus and I2C interfaces placement and routing consideration. Strong design experience of power delivery network routing using PMIC devices.\nDesign and Development:  Lead the design and development of, SSD's drive PCB layouts, EDSFF (E3.S, E1.L, E3.L) and U.2 form factors, daughter cards, Evaluation and Test PCB layouts.\nQuality Assurance: Ensure all designs comply with industry standards (IPC) and regulatory requirements (UL, IEC).\nProblem Solving: Troubleshoot and resolve issues related to PCB design and manufacturing.\nDocumentation: Maintain detailed documentation of PCB designs, modifications, and testing procedures.\nCollaboration: Work closely with other engineering teams, including hardware, simulation (SI/PI), and mechanical engineers, to integrate PCBs into larger systems.\nContinuous improvement: Participate in internal technical, DFM/DFA, Continuous Improvement, Industry standard and other meetings as necessary ​\nQualifications:\nEducation: Candidate must have Bachelor/ Diploma degree in Electronics Engineering, Electrical Engineering or related field.\nExperience: Candidate should have minimum of 12 years of experience in PCB design & development and able to deliver the complex PCB layout as an individual contributor.\nSkills: Proficiency in PCB design software (Cadence Allegro), strong understanding of electronic circuits, Knowledge of HDI Stack up and different via technologies, and excellent problem-solving skills.\nStrong knowledge on DFM/DFA constraints are essential.\nAlso, hands on experience in valor and Cam350 preferred.\nA thorough understanding of Signal Integrity (SI), Power Integrity (PI), and Electromagnetic Compatibility (EMC) requirements is very much important.\n\nCommunication: Strong verbal and written communication skills to effectively collaborate with team members and stakeholders across different geographic centers.\nAttention to Detail: High level of attention to detail to ensure precision in designs and compliance with standards.\n\nAI Proficiency & AI-Enabled Ways of Working\nDemonstrates AI proficiency by leveraging AI-enabled tools (e.g., M365 Copilot, GenAI assistants) in PCB design and engineering workflows\n\nApplies AI-assisted methods to:\nAnalyze design data, validation results, and debug logs\nAccelerate failure analysis and root cause identification\nImprove design decisions through data-driven insights\n\nUses AI tools for workflow optimization, including:\nSummarizing design reviews and technical discussions\nAutomating documentation, reporting, and knowledge capture\nEnhancing collaboration efficiency across global teams\n\nIdentifies opportunities to integrate AI into PCB design processes, such as:\nAutomated design rule analysis\nSI/PI trend evaluation and optimization support\nValidation data analysis and pattern recognition\n\nPromotes AI-enabled ways of working within the team, aligning with Micron’s AI transformation initiatives\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Physical Design Engineer (Senior/Lead) – Modem Team", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-28T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720750903", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nExperience : 2–6 Years of experience in physical design from product-based companies.\n \nEducation : B.E/M.E in ECE, EE, VLSI, Microelectronics, or related fields from a top-tier institute.\n\nJob Summary:\nLooking for a hands-on Physical Design Engineer with strong expertise in the complete PnR flow, from netlist to GDSII. The candidate will be responsible for block-level implementation, timing closure, and signoff activities for advanced Modem SoC designs.\n\nKey Responsibilities:\nDrive end-to-end Physical Design flow including Floorplanning, Placement, CTS, Routing, Timing Closure, and Signoff.\n\nPerform block-level implementation and optimization for PPA targets.\n\nWork closely with STA, RTL, DFT, and CAD teams to achieve design closure.\n\nDebug and resolve implementation issues using Synopsys Fusion Compiler.\n\nDevelop automation and flow improvements using Tcl/Shell scripting.\n\nRequired Skills:\nStrong hands-on experience in Floorplanning, Placement, CTS, Routing, Timing Closure, and Signoff.\n\nExpertise in Synopsys Fusion Compiler (FC)/Innovus and implementation flows.\n\nProficiency in Tcl and Shell Scripting\n\nGood understanding of STA, MMMC, IR/EM, DRC/LVS, and Physical Verification.\n\nMust have practical block-level implementation experience with strong command-level knowledge of FC/Innovus tools.\n\nExperience with advanced technology nodes and full-chip/tapeout environments.\n\nStrong debugging, problem-solving, and communication skills.\n\n \n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Staff Design Engineer", "company": "Lattice", "location": "Penang, Malaysia", "date_posted": "2026-08-28", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Penang-Malaysia/Senior-Staff-Design-Engineer_R-103077", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\n\nJoin the winning team! Lattice is looking for a motivated and experienced Senior Staff Engineer to lead the development, integration, and productization of high-performance interface solutions, including PCI Express (PCIe), Ethernet, USB, MIPI, SerDes, and related PHY technologies for next-generation FPGA products.\n\nThe successful candidate will bring a subsystem ownership mindset, with strong RTL expertise and the ability to drive technical decisions across protocol architecture, PHY and analog behavior, soft IP, software and firmware enablement, package and platform integration, validation, interoperability, and customer deployment. The role works closely with hardware, analog and mixed-signal, software, validation, applications, product engineering, and external IP partners.\n\nKey Responsibilities:\nLead architecture, RTL development, integration, verification, and productization of PCIe, Ethernet, USB, MIPI, SerDes, and related interface subsystems.\n\nOwn subsystem requirements and dependencies across digital logic, PHY/PMA, soft IP, firmware, FPGA software tools, package, platform, and validation.\n\nDrive structured root-cause analysis for complex pre-silicon, post-silicon, software-interaction, interoperability, and customer-reported issues.\n\nWork with software and firmware teams to define configuration, feature enablement, diagnostic, and user-flow requirements.\n\nDrive technical engagement with third-party IP suppliers and technology partners for digital, PHY, and mixed-signal IP. Define requirements, evaluate deliverables, resolve integration and verification issues, and drive technical closure through product development and silicon bring-up.\n\nIdentify technical risks and dependencies, support milestone and release-readiness reviews, and communicate clear recommendations to stakeholders.\n\nMentor engineers and improve design, debug, review, and release methodologies across the team.\n\nRequired Qualifications:\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.\n\n15+years of experience in ASIC, SoC, or FPGA design and product-development. \n\nStrong RTL design and subsystem integration experience, including clock/reset architecture, configuration interfaces, timing, and CDC/RDC considerations.\n\nDeep expertise in at least one high-speed interface area such as PCIe, Ethernet, USB, MIPI, SerDes, or related PHY/controller technology.\n\nDemonstrated ability to understand an interface as a complete subsystem and drive dependencies beyond the RTL block.\n\nExperience applying AI-assisted tools and workflows to accelerate engineering productivity, technical investigation, data analysis, and documentation.\n\nExperience working with DFT and DFD methodologies, including scan, ATPG, debug observability, silicon bring-up, or production-test considerations.\n\nExperience working with Design Verification teams and using system simulation, emulation, or FPGA prototyping environments to validate end-to-end subsystem behavior and accelerate pre-silicon debug.\n\nExperience leading complex cross-functional debug and driving issues from initial investigation through verified closure.\n\nExperience with pre-silicon verification, silicon bring-up, laboratory debug, interoperability, or customer issue resolution.\n\nStrong technical communication, stakeholder alignment, and independent decision-making skills.\n\nPreferred Qualifications:\nExperience with more than one interface family, including connectivity or video protocols such as PCIe, Ethernet, USB, MIPI CSI-2/DSI, D-PHY/C-PHY, or SerDes.\n\nUnderstanding of PHY and mixed-signal behavior associated with high-speed interface IP, including clocking, calibration, termination, equalization, jitter, reset sequencing, power management, initialization, and bring-up. Direct analog circuit design experience is not required.\n\nExperience working with third-party suppliers of digital controller, PHY, or mixed-signal IP to define requirements, assess deliverables, and resolve architecture, integration, verification, and silicon issues.\n\nFamiliarity or experience in Physical Design e.g.: Synthesis, LEC or Timing Closure.\n\nExperience in design quality checks methodology e.g.: Lint, CDC, RDC, Fishtail or UPF flow.\n\nKnowledge of firmware, device configuration, APIs, scripts, drivers, or FPGA software-tool enablement.\n\nExposure to package, board, platform, signal-integrity, compliance, and interoperability considerations for high-speed interfaces.\n\nExperience influencing architecture or methodology and mentoring engineers across organizational boundaries.\n\n#LI-DNP\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nMalaysiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Senior Design Verification Engineer", "company": "Lattice", "location": "LHY", "date_posted": "2026-08-28", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/LHY/Design-Verification-Engineer_R-101039-1", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nResponsibilities:\nDraft DV scope, strategy & feasibility in response to marketing requirements\nDevelop test plans based on Design Specifications\nDesign & Implement constrained-random testbenches & metrics\nCode & Execute tests, Debug encountered issues\nCollate & Analyze test results to closure\nRequirements:\nBS or MS in Computer/Electronics/Electrical Engineering with a minimum of 5 years of relevant design verification experience.\nGood communication, collaboration & documentation skills.\nGood grasp of & Hands-on experience with SystemVerilog/UVM, with solid understanding of different available SV/UVM constructs. Experience with languages like Python, make, C, C++ is an advantage.\nGood analysis & debugging skills. Understanding of HDL & FPGA concepts is an advantage.\nExperience with industry standard digital design simulators & debugging tools. Experience with Siemens EDA tools specifically is an advantage. Experience with Perforce, Git, Jenkins, & generative AI is also an advantage.\nExperience in the following technology areas is an advantage: Cryptography, Security, AMBA protocols, SPI, I2C/I3C\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Software Configuration Management Engineer – Hardware", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-28", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Software-Configuration-Management-Engineer---Hardware_JR2019717", "is_hardware": true, "platform": "workday", "jd_text": "For two decades, we have pioneered visual computing, the art and science of computer graphics. With our invention of the GPU - the engine of modern visual computing - the field has expanded to encompass video games, movie production, product design, medical diagnosis and scientific research. Today, we stand at the beginning of the next era, the AI computing era, ignited by a new computing model, GPU deep learning. This new model - where deep neural networks are trained to recognize patterns from massive amounts of data - has shown to be deeply effective at solving some of the most complex problems in everyday life. NVIDIA runs a very large GitLab environment, supporting 10s of thousands of engineers and massive repositories across the globe. Our Software Configuration Management (SCM) Tools and Infrastructure group is looking for a top SCM architect. You will tackle the challenges that we face with operating at scale to produce a best-in-industry solution and enable us to continue to provide unprecedented performance and reliability for our users. You will take on the challenges that come with operating and scaling our ever-growing GitLab deployment. In this role, you will design and code processes and automation tools to improve productivity managing and administering the SCM systems and applications used by our globally distributed engineering teams.\n\nWhat You’ll Be Doing:\nResponsible for the full SCM environment including application, OS, and server hardware components, developing the continued automation and innovation needed for our large environment\n\nCreate new solutions to improve the reliability and performance of our ever-growing infrastructure, and work with automated orchestration tools to deploy those improvements to hundreds of systems worldwide\n\nBe part of a global team and will evaluate technology alternatives, work closely with other project members to specify solutions, craft schedules, and lead ongoing enhancements and support\n\nLead or contribute to GitLab upgrades and migrations, architectural reviews and design docs, root cause analysis and systemic fixes\n\nLearn and greatly improve the daily productivity of the world’s top chip designers and software engineers\n\nWhat We Need to See:\nMS (preferred) or BS in Computer Science (or equivalent experience) or a related field with at least 3+ years of experience\n\nDeep understanding of SCM processes and large-scale, multi-site GitLab environments (experience with other SCM tools such as Perforce, Subversion, or ClearCase is a plus).\n\nYou've configured/deployed Continuous Integration (CI) and Continuous Deployment (CD) systems in your past experience\n\nExcellent interpreted language skills highly desired – Object Oriented Perl or Python preferred and Strong software engineering process skills required\n\nStrong skills in scripting and object-oriented languages such as Python or Ruby, with solid software engineering practices and familiarity with design patterns.\n\nHands-on experience with relational databases (PostgreSQL preferred)\n\nExperience with DevOps or system administration on Linux systems required (Rocky Linux 8, CentOS/RHEL, and Ubuntu preferred)\n\nStrong experience with automation required, Ansible or Puppet preferred and Excellent\n\ninterpersonal skills, including written and verbal communication\n\nYou are comfortable and enjoy working with dynamic and ever evolving environments\n\nWays to Stand Out from the Crowd:\nMeticulous and proactive problem-solver with a positive, can-do attitude.\n\nDemonstrate use of out-of-box thinking for creative solutions to highly sticky problems\n \n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Hardware Development Engineer - Process", "company": "Nokia", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-08-28", "url": "https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/39881", "is_hardware": true, "platform": "oracle", "jd_text": "As an Hardware Development Engineer, you will play a crucial role in our NI ON  department. Your primary focus will be on optical pluggable products, from concept to manufacturing, with a strong emphasis on manufacturability, efficiency, and quality. You will act as a key interface between various teams, ensuring a seamless product development journey.\n\nNILightpath\n\nResponsibilities\nOwn the product transition process from concept to high-volume manufacturing for optical pluggable modules.\nDrive product design decisions, considering manufacturability, cost, quality, and automation aspects.\nAct as the engineering liaison between Product Design, Manufacturing, Quality, and other relevant teams.\nLead DFM, DFA, PFMEA activities, process qualification, and production ramp-up initiatives.\nSupport various optical transceiver platforms, including OSFP, OSFP-XD, QSFP-DD etc.\nReview GD&T, module housings, thermal lids, heat spreaders, and other critical components from assembly and cost effectiveness perspective\nCreate process flows, work instructions, and assembly procedures for efficient manufacturing.\n\nQualifications\nBachelor's or Master's degree in Mechanical, Manufacturing, Mechatronics, or Production Engineering.\n3+ years of engineering experience, with a strong background in mechanical product design.\nProficiency in Creo Parametric,  GD&T (ASME Y14.5)\nExperience in NPI and production readiness, supporting EVT, DVT, PVT, and production ramp-up.\nStrong DFM expertise for optical modules, precision mechanical assemblies, and high-density electronic products.\nAbility to develop manufacturing tooling and fixtures, with knowledge of automated screw driving and machine vision systems.\nExperience with PFMEA, DFMEA, and process improvement methodologies like 8D, DMAIC, and 5 Why.\nFamiliarity with optical module domain knowledge, including OSFP MSA, QSFP-DD MSA, and coherent optics.\nUnderstanding of thermal engineering principles and experience with FloTHERM or similar thermal analysis tools.\n\nAbout the company\nAdvancing connectivity to secure a brighter world.\n\nNokia is a global leader in connectivity for the AI era. With expertise across fixed, mobile and transport networks, powered by the innovation of Nokia Bell Labs, we’re advancing connectivity to secure a brighter world. \n\nLearn more about life at Nokia.\n\nOur recruitment process\n\nWe act inclusively and respect the uniqueness of people. Our employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.\n\nIf you’re interested in this role but don’t meet every listed requirement, we still encourage you to apply. Unique backgrounds, perspectives, and experiences enrich our teams, and you may be just the right candidate for this or another opportunity.\n\nThe length of the recruitment process may vary depending on the specific role's requirements. We strive to ensure a smooth and inclusive experience for all candidates. Discover more about the recruitment process at Nokia.", "jd_status": "stored"}, {"title": "Senior DFT Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-08-28", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505265", "is_hardware": true, "platform": "oracle", "jd_text": "About the Role\n\n \n\nonsemi is seeking a DFT Engineer to support the design and implementation of Design‑for‑Test (DFT) features for complex ASIC/SoC products across automotive and industrial applications. This role focuses on scan, ATPG, MBIST, and boundary scan, with close collaboration across design, PD, and test teams.\n\n \n\nKey Responsibilities\n\nDevelop and integrate DFT architectures including Scan, ATPG, MBIST, and JTAG\n\nImplement and debug DFT logic to ensure high fault coverage and test quality\n\nGenerate and analyze ATPG patterns using industry‑standard tools\n\nSupport at‑speed and transition fault testing\n\nCollaborate with RTL, Physical Design, STA, and Test Engineering teams\n\nAddress timing, CDC, and low‑power DFT considerations\n\nSupport test coverage analysis, DFT signoff, and silicon bring‑up\n\n \n\n#LI-RT1\n\nResponsibilities\nRequired Qualifications\n3–5 years of experience in ASIC / SoC DFT\nStrong understanding of: Scan, ATPG, MBIST, JTAG\nFault models: stuck‑at, transition, at‑speed\n\nHands‑on experience with DFT tools such as: Synopsys DFT Compiler / TestKompress\nSiemens Tessent or equivalent\n\nFamiliarity with timing, CDC, and low‑power DFT flows\nBS/MS (B.Tech/M.Tech) in Electrical Engineering or related field\n #LI-RT1\n\nQualifications\nPreferred Qualifications\nExperience with advanced nodes and large SoCs\nExposure to physical‑aware DFT and test‑related ECOs\nWorking knowledge of UPF and low‑power test strategies\n#LI-RT1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Integration Design Engineer", "company": "Lattice", "location": "Penang, Malaysia", "date_posted": "2026-08-28", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Penang-Malaysia/Integration-Design-Engineer_R-100972-1", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nRequired Skills:\n•    BS or MS in Electronics/Computer/Electrical Engineering\n•    At least 12 years of proven in-depth experience in Custom and Digital Design Implementation. Expertise in Verilog and System Verilog is a must.\n•    Experience in FPGA/CPLD design and integration is a plus.\n•    Expertise on the following:\no    Custom Design Flow\n    Semiconductor principles and transistor-level analysis\n    Industry standard tools for schematic and layout Entry (Cadence Virtuoso)\n    Characterization, performance, and power simulations (spice is preferred)\no    Digital Design Flow\n    RTL coding and verification\n    Lint Check, Elaboration/Compilation, Synthesis, Equivalence Check, SDC, and STA using industry standard tools (Xcelium, Genus, Innovus, Tempus) \n    DFT flow and ATPG generation\n•    Experience in IP and Fullchip functional verification is a plus.\n•    Expertise in coding/scripting (Perl, TCL, Shell, Skill, Phyton)\n•    Experience in project leadership and product development cycle (planning, resourcing, tapeout, silicon characterization/validation) is a plus.\n \n#LI-DNP\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nMalaysiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Senior Soft IP Design Engineer", "company": "Lattice", "location": "Penang, Malaysia", "date_posted": "2026-08-28", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Penang-Malaysia/Senior-Soft-IP-Design-Engineer_R-100795-1", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nJob Description:\nWe are seeking a Senior IP Design Engineer, passionate individual with technical leadership capabilities to build Connectivity IP portfolios for Lattice FPGA. The individual should have the ability to work closely with architect to translate specifications into high-speed RTL design, for the best Performance, Power and logic utilization.\n\nRequirements\nKey Skills\nExperience in high speed SERDES and video protocols (e.g.: DisplayPort, HDMI, MIPI, SDI) or Peripherals (SPI, I2C or I3C) is a plus.\n\nHands-on experience in FPGA RTL design, CDC/lint, verification, debug and timing closure is preferred\n\nProgramming skills (e.g.: Verilog, SystemVerilog, C/C++, Perl, TCL or Python).\n\nExperience in hardware validation or hardware interoperability test.\n\nExperience in soft IP packaging, example design and testbench development will be an added advantage.\n\nEducation and General:\nBS/MS/PhD in Electronics or Computer Engineering minimum of 7 years of FPGA IP design experience.\n\nIndependent and self-motivated, capable of executing under dynamic environment and uncertainties\n\n#LI-DNP\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nMalaysiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Staff Applications Engineer", "company": "Lattice", "location": "Penang, Malaysia", "date_posted": "2026-08-28", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Penang-Malaysia/Applications-Engineer-4_R-100668-1", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\n\nJoin the winning team! Lattice is looking for a motivated and experienced factory Applications Engineer to support high-speed IPs & designs, vendors and customers with our current and future industry-leading devices. As part of the IP Product Enablement team, we bridge the customer-factory relationship, clear technical hurdles and provide timely and reliable solutions. While Lattice is successful in helping our customers slash their time-to-market and bottom-line with our market-driven solutions, we want to continue to invite experts to challenge the status quo. Our IP Product Enablement team is seeking an outstanding team member to help design and execute \"best-in-class\" solutions for our best-in-class low power, small form factor, high reliability and performance product line. \n\nSpecific job skill requirements:\nExperience in image/video processing, memory standards or high speed interfaces is an advantage.\n\nExperience in a wide variety of physical interface standards, including SSTL, HSTL, LVSTL, HSUL is highly desirable.\n\nExperience in timing closure, PLL/DLLs, physical interface strategies and signal integrity is highly desirable.\n\nHands-on FPGA development experience, including RTL development and verification is highly desirable.\n\nGeneral requirements:\nBS/MS in EE with 8+ years of experience.\n\nHands-on FPGA and/or firmware bring-up/debugging experience using oscilloscopes and signal analyzers is required.\n\nExpertise in FPGA design flows, Verilog and/or VHDL .\n\nOutstanding English communication skills, both written and verbal required.\n\nHands-on experience delivering revenue-generating hardware products is required.\n\nParticipation in all aspects of product development, from architecture and specification through documentation, market release and customer support.\n\nMust be able to work independently and also in a team environment.\n\n#LI-DNP\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nMalaysiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Staff IP Design Engineer", "company": "Lattice", "location": "Penang, Malaysia", "date_posted": "2026-08-28", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Penang-Malaysia/Staff-IP-Design-Engineer_R-100914-1", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nLattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\n\nResponsibilities & Skills We are seeking a Staff IP Design engineer, passionate individual with technical leadership capabilities to build Connectivity IP portfolios for Lattice FPGA. The individual should have the ability to work closely with architect to translate specifications into high-speed RTL design, for the best Performance, Power and logic utilization.\n\nRequirements Key Skills\nExperience in high speed SERDES and video protocols (e.g.: DisplayPort, HDMI, MIPI, SDI) or Peripherals (SPI, I2C or I3C) is a plus.\nHands-on experience in FPGA RTL design, logic verification, debug and timing closure is preferred\nProgramming skills (e.g.: C/C++, Perl, TCL or Python).\nExperience in hardware validation or hardware interoperability test is a plus.\nExperience in soft IP packaging, example design and testbench development will be an added advantage.\nEducation And General\nBS/MS/PhD in Electronics or Computer Engineering minimum of 8 years of FPGA or system design experience.\nIndependent and self-motivated, capable of executing under dynamic environment and uncertainties\nInnovative, problem solver who likes to come up with newer and better solutions for existing problems.\nIndividual who works well with a team of diverse engineers, open to feedback and opinions.\nAble to galvanize and enable a team to execute on a project to completion.\nGood communication skill\n\n#LI-DNP\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nMalaysiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "IP Design Verification Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-08-28", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/IP-Design-Verification-Engineer_JR0286694", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact:\nAs an IP Design Verification Engineer, you will play an integral role in shaping Intel's advanced IP technologies that empower innovation and redefine digital experiences. In this role, you will be responsible for ensuring the functional quality of our IP designs, enabling cutting-edge product development with precision and efficiency. Your contributions will directly impact Intel's ability to deliver world-class silicon solutions, driving forward the technology landscape. If you enjoy solving complex technical challenges, collaborating with cross-functional teams, and influencing the future of technology, this position offers an exciting platform for impact and growth.\n\nKey Responsibilities:\n- Perform functional verification of IP logic to ensure designs meet specification requirements.\n- Develop and execute IP verification plans, test benches, and environments to confirm compliance with microarchitecture specifications.\n- Define and run system simulation models to verify designs, analyze power and timing, and identify bugs.\n- Replicate, root cause, and debug issues in the presilicon environment and implement corrective measures to resolve failing tests.\n- Collaborate with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.\n- Document test plans and spearhead technical reviews of plans and proofs with design and architecture teams.\n- Maintain and improve existing functional verification infrastructure and methodologies.\n- Participate in defining verification infrastructure and related TFMs needed for functional design verification.\n\nQualifications:\nMinimum Qualifications:\n- Bachelor's or BS degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.\n- 6+ years of experience with a Bachelor's degree, 4+ years with a Master's degree, or 2+ years with a PhD.\n- Strong coding skills in Perl or Python.\n- Proficiency in SystemVerilog and UVM/OVM methodology.\n- Hands-on experience with AMBA protocols (AXI, AHB, APB).\n- Proven ability to design and implement verification test environments.\n\nPreferred Qualifications:\n- Experience bringing up coherent protocols from inception to implementation.\n- Knowledge of Network-on-Chip verification methodologies.\n- Familiarity with formal verification techniques.\n- Exposure to power-aware verification and knowledge of PCIe protocols.\n- Excellent problem-solving and communication skills, with a demonstrated ability to work effectively across teams.\n\nJoin Intel to make a meaningful difference in technology and empower the world's digital evolution.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Hardware Development Engineer", "company": "Nokia", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-08-28", "url": "https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/39910", "is_hardware": true, "platform": "oracle", "jd_text": "The Hardware Development Engineer will be a key member of our team, responsible for designing and developing high-performance hardware solutions. With a focus on board design, testing, and debugging, this role requires a strong understanding of EDA tools and hands-on experience in lab activities. The successful candidate will have the opportunity to work on innovative projects and contribute to the development of cutting-edge technology.\n\nNILightpath", "jd_status": "source_unavailable"}, {"title": "PDK Development Engineer", "company": "Analog Devices", "location": "India, Bangalore, Nova", "date_posted": "2026-08-28", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-Nova/PDK-Development-Engineer_R264820", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nJob Title: PDK Development Engineer\nMinimum requirements: 6 Years Experience \nLocation: Bangalore, India \nJob Description:  \nAs part of the Engineering Enablement organization at ADI, this senior-level CAD engineer will work on developing and testing of the QA framework used in the validation of Process design kits (PDK) for internal and external semiconductor process technologies used in the design and manufacturing of analog, mixed signal, power management and DSP products in ADI.  As an individual contributor, you will be expected to possess the necessary programming skills and circuit design knowledge to develop, support, enhance and test the PDK QA flow used at ADI. The PDK QA functions involve checking of the PDK deliverables such as schematic symbols, layout p-cells, CDFs, DRC/LVS decks, technology files used in Parasitic extraction, ESD verification and other reliability-based flows for quality issues prior to the release of a PDK. You will also develop process design kits (PDKs) for internal and external process technologies in support of Analog, RF, Mixed-Signal, and Digital design flows using Cadence, Mentor, Keysight and internally developed CAD software. \nPrimary responsibilities:  \nDevelop device level layout generators (PCELLs) \nDevelop  physical verification (DRC/LVS) rules and parasitic extraction flows \nClosely work with developers of front-end and back-end components of PDK to create/enhance test cases to actively improve QA coverage. \nAbility to interpret process as well as assembly/packaging design rule specifications to ensure test cases are representative of design rule checks implemented in DRC decks. \nUnderstand Layout Vs. Schematic (LVS) flow intent and create representative test cases for validating LVS decks. \nAutomatic Test case generation and unit testing to ensure there is adequate test coverage for validating the different PDK components.  \nTest case debugging – investigate if PASS/FAIL test cases are being generated and functioning as per requirements. \nProvide technical CAD support for ADI design community \nWork closely with the design teams to understand their requirements and colloborate with device modeling, process development and foundry groups to enable the efficient use of CAD tools and methodologies \nCreate test cases for validating netlists generated for internal/external analog circuit simulation tools. \nTest case generation for testing the accuracy of Parasitic Resistance/Capacitance extraction technology files. \nPerform validation of techfiles used in ESD verification, such as topology checks, ESD resistance and current density checks. \nWork closely with the EDA software vendors to resolve tool bugs and drive new feature additions. \n \nQualifications:   \nMinimum 6 years of experience in developing PDKs and writing programs for automation \nBS/MS in Electrical or Computer Engineering with an emphasis on IC design and semiconductor processes \nKnowledge of Python Programming Language and Cadence Skill Language is essential. \nProven skills in other programming languages (Perl, Tcl, Bash) \nMust have undertaken automation projects. \nUnderstanding of analog/mixed signal simulation tools \nFamiliarity with physical verification (DRC/LVS) tools \nKnowledge of parasitic extraction tools. \nFamiliarity with revision control systems and collaboration tools is a plus. \nMust possess excellent verbal and written communication skills \nMust be detail oriented, well organized and a versatile team player.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Principal Design Verification Engineer", "company": "Astera Labs", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-08-27T15:35:07-04:00", "url": "https://job-boards.greenhouse.io/asteralabs/jobs/4728417005", "is_hardware": true, "platform": "greenhouse", "jd_text": "Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\n\nWe are seeking talented Design Verification Professionals with proven expertise in industry-standard protocols such as PCIe and CXL. You will play a key role in the functional verification of designs, from developing block-level and system-level verification plans to writing test sequences, executing tests, and collecting and closing coverage.\n\nResponsibilities:\n\nDevelop and execute block-level and system-level verification plans.\n\nWrite and execute test sequences and collect and close coverage.\n\nCollaborate with RTL designers to debug failures and refine verification processes.\n\nUtilize coding and protocol expertise to contribute to functional verification.\n\nDevelop user-controlled random constraints in transaction-based verification methodologies.\n\nWrite assertions, cover properties, and analyze coverage data.\n\nCreate VIP abstraction layers for sequences to simplify and scale verification deployments.\n\nBasic Qualifications:\n\nMinimum of 12 years’ experience in supporting or developing complex SoC/silicon products for server, storage, and/or networking applications.\n\nStrong academic and technical background in Electrical Engineering or Computer Engineering (bachelor’s degree required, master’s preferred).\n\nProfessional attitude with the ability to prioritize tasks, prepare for customer meetings, and work independently with minimal guidance.\n\nKnowledge of industry-standard simulators, revision control systems, and regression systems.\n\nEntrepreneurial, open-minded behavior and a can-do attitude, with a focus on customer satisfaction.\n\n \n\nRequired Experience:\n\nInterpreting PCIe/CXL standard protocol specifications to develop and execute verification plans in simulation environments.\n\nExperience using Verification IPs from third-party vendors for PCIe/CXL, focusing on Gen3 or above.\n\nAbility to independently develop test plans and sequences in UVM to generate stimuli.\n\nExperience writing assertions, cover properties, and analyzing coverage data.\n\nDeveloping VIP abstraction layers for sequences to simplify and scale verification deployments.\n\nPreferred Experience:\n\nExpertise in verifying Physical Layer, Link Layer, and Transaction Layer of PCIe/CXL protocols, including compliance on PCIe/CXL EP/RC.\n\nExperience with buffering and queuing with QoS on complex NOC-based SoCs.\n\nAnalyzing performance at the system level on switching fabrics.\n\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.", "jd_status": "stored"}, {"title": "Tech Lead– Verification Methodology/CAD", "company": "Astera Labs", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-08-27T15:32:18-04:00", "url": "https://job-boards.greenhouse.io/asteralabs/jobs/4728420005", "is_hardware": true, "platform": "greenhouse", "jd_text": "Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\n\nTechLead– Verification Methodology / CAD / Automation Engineer \n\nExperience - 6–12 years \n\nJob Summary \n\nWe are looking for a Tech Lead – Verification Methodology/CAD/Automation Engineer to drive verification infrastructure, methodology, automation, and productivity across IP and SoC verification teams. \n\nThe candidate will build scalable verification frameworks, automate verification workflows, improve regression infrastructure, and partner with design verification teams to establish efficient and reusable methodologies. \n\nKey Responsibilities \n\nOwn and drive verification methodology and infrastructure across projects. \n\nDevelop scalable frameworks for simulation, regression, coverage, debug, and verification signoff. \n\nBuild and maintain verification CAD/automation flows. \n\nDevelop automation scripts and tools using Python, Tcl, Perl, Shell, and/or C++. \n\nAutomate test generation, compilation, regression execution, result collection, coverage analysis, and reporting. \n\nDevelop infrastructure for large-scale UVM/SystemVerilog verification environments. \n\nImprove simulation and regression turnaround time through parallelization and optimization. \n\nIntegrate simulation, lint, CDC/RDC, formal, coverage, and other verification tools into common workflows. \n\nDevelop dashboards and metrics for verification quality, coverage, regression health, and project status. \n\nDebug infrastructure and tool-flow issues and provide rapid support to verification teams. \n\nEstablish reusable verification components, scripts, libraries, and methodology guidelines. \n\nDrive adoption of best practices across multiple verification teams. \n\nEvaluate new verification technologies and tools and recommend improvements. \n\nWork closely with EDA vendors to troubleshoot tool issues and improve flows. \n\nSupport migration and integration of new EDA tool versions and methodologies. \n\nDevelop documentation and training for verification teams. \n\nMentor verification CAD/methodology engineers and provide technical leadership. \n\nRequired Technical Skills \n\nStrong experience in verification methodology, CAD, and automation. \n\nStrong programming/scripting skills in Python, Tcl, Perl, Shell, and preferably C/C++. \n\nStrong understanding of SystemVerilog/UVM. \n\nExperience with simulation tools such as VCS, Xcelium, Questa, or equivalent. \n\nExperience building and maintaining regression infrastructure. \n\nStrong knowledge of coverage collection and analysis. \n\nUnderstanding of verification flows including: \n\nSimulation \n\nUVM \n\nLint \n\nCDC/RDC \n\nFormal \n\nCode/functional coverage \n\nRegression \n\nDebug \n\nStrong Linux/Unix environment experience. \n\nExcellent automation and problem-solving skills. \n\nPreferred Experience \n\nExperience with large-scale SoC/IP verification environments. \n\nExperience integrating multiple EDA tools into a unified verification flow. \n\nExperience with CI/CD infrastructure such as Jenkins, GitLab CI, or equivalent. \n\nExperience with distributed/parallel regression infrastructure. \n\nExperience with cloud-based or scalable compute environments. \n\nKnowledge of databases, dashboards, APIs, or web-based verification infrastructure is an advantage. \n\nExperience working with EDA vendors and managing tool-flow issues. \n\nLeadership Expectations \n\nAct as the technical owner for verification methodology and automation. \n\nIdentify opportunities to improve verification productivity, quality, and turnaround time. \n\nDefine and enforce verification methodology standards. \n\nMentor engineers and drive adoption of common frameworks. \n\nWork across multiple projects and teams to solve infrastructure challenges. \n\nStrong ability to balance immediate project requirements with long-term methodology improvements. \n\nEducation \n\nB.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Computer Science, Computer Engineering, VLSI, or a related discipline. \n\n \nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.", "jd_status": "stored"}, {"title": "Lead Emulation Engineer", "company": "Astera Labs", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-08-27T15:28:47-04:00", "url": "https://job-boards.greenhouse.io/asteralabs/jobs/4728416005", "is_hardware": true, "platform": "greenhouse", "jd_text": "Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\n\nLead Emulation Engineer\n\nExperience - 6–10 years \n\nJob Summary \n\nWe are looking for a Lead Emulation Engineer to lead the deployment and execution of complex SoC/IP verification on hardware emulation platforms. The candidate will work closely with design verification, RTL, architecture, firmware, and post-silicon teams to accelerate functional verification, software development, performance validation, and system-level debug. \n\nKey Responsibilities \n\nLead emulation strategy and execution for complex SoC/IP designs. \n\nDevelop and maintain emulation environments for large-scale ASIC/SoC designs. \n\nBring up RTL designs on emulation platforms and debug compilation, mapping, and runtime issues. \n\nDevelop and execute emulation-based verification plans. \n\nEnable software and firmware teams to execute workloads on emulated hardware. \n\nSupport early software bring-up and system-level validation. \n\nDevelop transactors, monitors, BFMs, and other emulation components as required. \n\nOptimize emulation builds for performance, capacity, and compile/runtime efficiency. \n\nDebug functional issues across RTL, testbench, emulation environment, and software. \n\nWork closely with DV teams to migrate suitable simulation-based tests to emulation. \n\nDevelop automation for test execution, regression, data collection, and debug. \n\nAnalyze emulation failures and drive root-cause identification with RTL/DV teams. \n\nSupport performance and stress testing using realistic system workloads. \n\nDrive emulation methodology improvements and infrastructure enhancements. \n\nMentor junior and senior emulation engineers. \n\nProvide technical leadership during major IP/SoC bring-up milestones. \n\nSupport silicon bring-up by developing reusable emulation-based debug strategies. \n\nRequired Technical Skills \n\nStrong experience with ASIC/SoC emulation. \n\nHands-on experience with platforms such as Cadence Palladium, Synopsys ZeBu, or equivalent. \n\nStrong understanding of RTL and digital design. \n\nExperience with SystemVerilog/Verilog. \n\nExperience with UVM-based verification environments and simulation-to-emulation flows. \n\nStrong understanding of emulation compile, mapping, partitioning, acceleration, and runtime concepts. \n\nStrong debugging and problem-solving skills. \n\nScripting/programming experience using Python, Tcl, Perl, or C/C++. \n\nPreferred Experience \n\nExperience with large, complex SoCs and multi-IP environments. \n\nExperience with PCIe, UALink, CXL, Ethernet, NoC, memory systems, or other high-speed interfaces. \n\nExperience with software-driven validation and early firmware enablement. \n\nExperience developing custom transactors and acceleration models. \n\nExperience with performance benchmarking and system-level workload validation. \n\nExperience supporting pre-silicon and post-silicon debug. \n\nLeadership Expectations \n\nIndependently own emulation bring-up and execution for major IPs/subsystems. \n\nLead technical discussions with DV, RTL, firmware, and architecture teams. \n\nMentor engineers and improve emulation productivity. \n\nDrive issues to closure while working against aggressive project/tape-out schedules. \n\nEstablish reusable emulation flows and best practices. \n\nEducation \n\nB.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Computer Engineering, VLSI, or a related discipline. \nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.", "jd_status": "stored"}, {"title": "Staff Engineer Analog Mixed signal verification", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-08-27T11:43:53+00:00", "url": "https://jobs.infineon.com/careers/job/563808971897584", "is_hardware": true, "platform": "eightfold", "jd_text": "We are looking for a highly motivated AMS Verification Engineer with 5+ years of experience in System Verilog Real Number Modeling (SV RNM), WREAL modeling, Mixed-Signal Verification, and DMS-based SoC verification. The candidate will be responsible for developing and validating behavioral models of analog IPs, creating verification environments, implementing SV Assertions, and driving AMS verification for power management and mixed-signal designs.\n\nYour role\nKey responsibilities in your new role\n\nDevelop and maintain SV RNM and WREAL models for analog and mixed-signal IPs.\n Verify and correlate RNM/WREAL models against transistor-level schematics and analog simulation results.\nDevelop automated checkers and reusable verification components.\nCreate and deploy System Verilog Assertions (SVA) to verify protocol, functionality, timing, and design correctness.\nPerform SoC-level analog vector verification using DMS verification flows involving UVM testbenches and RNM models.\nVerify AMS IPs such as:\n ADCs\n LDOs\n Buck/Boost Controllers\n Multi-phase Controllers\n Power Switches\nAnalyze simulation results, debug failures, and ensure comprehensive functional coverage.\nCollaborate with analog design teams to establish model-to-schematic correlation.\nDevelop automation frameworks and regression infrastructure using scripting languages.\nContribute to AMS verification methodology enhancements and simulator adoption.\n\nYour profile\nQualifications and skills to help you succeed \n\n5+ years of experience in AMS/Mixed-Signal Verification.\nStrong expertise in:\n SystemVerilog RNM (Real Number Modeling)\n WREAL Modeling\n UVM Methodology\n Digital Mixed Signal (DMS) Verification\n System Verilog Assertions (SVA)\nHands-on experience in developing behavioral models for analog IPs and validating them against schematic-level simulations.\nExperience in SoC-level AMS verification involving RNM models and UVM environments.\nStrong understanding of analog and mixed-signal concepts including:\n Data Converters (ADC)\n Voltage Regulators (LDO)\n Power Management ICs\n Buck/Boost Converters\n Multi-phase Controllers\n Power Switches\n Good understanding of EDA tools and simulators:\n Cadence Virtuoso Schematic Editor\n Cadence Xcelium\n APS (Accelerated Parallel Simulator)\n XPS\n AMS/DMS Simulation Environments\nExperience with verification planning, coverage closure, debugging, and regression management.\nKnowledge of assertion-based verification techniques and methodologies.\n\nStrong scripting skills in:\n Python\n Perl\n Shell Scripting\nExperience developing verification automation, checkers, and regression flows.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\n\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nVidhi Thakkar", "jd_status": "stored"}, {"title": "DFT Architect - Lead", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-08-27T09:02:00+00:00", "url": "https://global-external-amd.icims.com/jobs/80340/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. PMTS SILICON DESIGN ENGINEER THE ROLE: We are seeking a seasoned SoC Architect with expertise or significant interest in System Architecture. You have had significant success driving architecture, product roadmaps and product requirements. You are meticulous about Power, Performance and Area while driving schedule and managing cost. This senior role will stretch you as you lead architecture teams in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design teams, marketing, and business unit executives. THE PERSON: You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: Define product features and capabilities, close architecture, and micro-architecture requirements, drive technical specifications for SoC and IP blocks to meet those requirements, and provide technical direction to execution teams Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features, optimizing for performance and power Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements Knowledge sharing and other contributions to Platform & System Architecture As an overall product owner, responsible for architecture analysis and technical solutions for marketing/feature change requests Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs Support Post-Si teams for Product Performance, Power and functional issues debug/resolution PREFERRED EXPERIENCE: Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-system, Fabrics, CPU/GPU coherency, Multimedia, I/O subsystems, Clocks, Resets, Virtualization and Security Experience analyzing CPU, GPU or System-level Micro-Architectural features to identify performance bottlenecks within different workloads Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture, logic design, and circuit levels Excellent communication, management, and presentation skills. Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies ACADEMIC CREDENTIALS: Bachelor’s or Master’s degree in related discipline preferred #LI-AA1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Lead/Sr. Manager CPU verification engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-08-27T05:57:00+00:00", "url": "https://global-external-amd.icims.com/jobs/88478/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. SMTS SILICON DESIGN ENGINEER CPU verification engineer role - Core Verification Engineer The AMD Cores design & verification group develops high-end, next generation CPU’s that power different AMD SoC’s which are eventually set to change the course of how computing is visualized. The engineering teams are distributed across US and India. The CPU verification team in India is one of AMD India’s first teams & involved in contributing to the tape out of numerous AMD systems. As part of the CPU Design Verification team, our team will be responsible for the maintainability & scalability of RTL & testbench environment that is used for development & verification of the design. As always, the team is dedicated to come up with innovative solution to overcome new challenges related to specific project requirements and time-to-market. KEY RESPONSIBILITIES • Will work with different stake holders in getting a thorough understanding of high-level feature/s & get clarification(if any). Also evaluate cross-feature dependencies. • After feature understanding, populate high level testplan that details out how we plan(Stimulus, debug, coverage) to verify the feature & what we cover/don’t cover as a part of the feature verification. Get it reviewed & incorporate feedback. • Develop directed/random test cases to target the feature bringup. Debug fails(debug needs an understanding of computer architecture, micro-architecture & TB environment), file RTL/Verif bugs, fix testbench issues. • Ensure feature health is stable & in parallel work on evaluating stimulus coverage. If needed, tweak/add stimulus as appropriate. • If the feature demands, develop new C++ checkers. All this while learning & understanding uarch is an integral part. • Work on ensuring 100% FCOV that might involve developing new stimulus. Also, it might demand working with other feature owners to close on cross-feature coverage. • On a need basis, work on Post-Si bug recreation. SKILLS AND EXPERIENCE REQUIREMENTS B.E/B.Tech/M.E/M.Tech in Computer Science/Electrical/Electronic Engineering. 14+ years of experience in CPU verification. Good understanding about basics of computer architecture & digital systems Understanding of assembly(x86) code. Good understanding of Verilog, System Verilog, C++. Knowledge of shell/perl scripting is a plus. Understanding of Formal Verification methodology (with tools VSI-FV/JASPER/IFV/IEV) is a plus. Should be a good team player, quick thinker, pro-active, adaptable & outspoken/approachable. Must communicate well both written and orally. Must have led teams of few Must be well-organized and should be able to multitask well with due diligence on closing his/her tasks. Additional KEY RESPONSIBILITIES (Leadership & Team Management) Provide technical leadership and mentorship to a team of verification engineers, guiding feature bring-up, debug methodologies, and verification best practices. Drive verification planning and execution across multiple features/projects, ensuring alignment with program milestones, quality goals, and tapeout schedules. Lead technical reviews for test plans, verification environments, coverage closure strategies, and debug approaches to improve overall verification quality. Coordinate across global teams (Architecture, Design, DV, Emulation, Post-Si, and Program Management) to resolve technical challenges and execution risks. Identify verification gaps, project risks, and resource constraints proactively, and drive mitigation plans to ensure successful project execution. Champion process improvements, automation initiatives, and adoption of new verification methodologies to improve team productivity and verification effectiveness. Drive knowledge sharing within the team through technical trainings, design reviews, and mentoring sessions. Provide technical direction during critical debug activities and help unblock engineers working on complex micro-architectural issues. Participate in hiring, onboarding, and development of verification engineers, helping build a high-performing verification team. Foster a culture of collaboration, accountability, innovation, and engineering excellence across geographically distributed teams. Additional SKILLS AND EXPERIENCE REQUIREMENTS Demonstrated experience in leading verification teams and driving execution of complex CPU verification projects. Strong technical leadership skills with the ability to mentor junior and senior engineers and influence technical decisions across teams. Proven track record of successfully delivering verification milestones for large-scale CPU/SoC programs. Excellent stakeholder management skills with experience collaborating with Architecture, RTL Design, Firmware, Post-Silicon, and Program Management teams. Strong project planning, prioritization, and execution skills with the ability to manage multiple deliverables in a fast-paced environment. Experience driving verification methodology improvements, automation initiatives, and productivity enhancements. Ability to effectively communicate technical concepts and project status to both technical and management audiences. Experience participating in hiring, performance coaching, and career development of engineering team members is highly desirable. WHAT YOU WILL LEARN You will gain valuable experience in different aspects of CPU design & verification. You will also be familiarized with the nuances & challenges associated in design/verification of high-performance, pipelined CPU architecture. This helps you gain valuable insight & enhance your understanding of CPU micro-architecture. This team is essential to the success of AMD as a growing company. It is a very exciting environment, and you will be working with the very best in our technology. You will be working on some of the most exciting projects the industry has to offer. #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "DDR Design Verification Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-27T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720388710", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nQualcomm India Private LimitedJob Area:\nEngineering Group, Engineering Group > Hardware EngineeringGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\nMinimum Qualifications:\n• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\nOR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\nOR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.We are looking to hire a strong DV engineer to work on verification of DDR Subsystem in the Infra IP team\nCreate DV infrastructure for verification\nIntegrate VIP's\nCreate and execute test plans, debug failures, write assertions, close code and functional coverage\nEnsure high quality verification\nWorking with all stakeholders to ensure program success\nMinimum Qualifications\nBachelor's degree in Engineering, Electronics, Information Systems, Computer Science, or related field.\n5+ years Hardware Engineering experience or related work experience.\nPreferred Qualifications\nFollowing skill set is required:\nStrong Debug, UVM, System Verilog\nUnderstanding Specs and Standards and developing relevant test plans\nMonitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved\nCandidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening\nPreferred Qualifications 5+ Year of industry experiences in the following areas: -\nThorough understanding of Digital design concepts\nThorough understanding dv methodologies and tools\nGood understanding of LPDDR4/LPDDR5 protocols\nUnderstanding of Bus protocols like AHB/AXI/ACE/ACE-Lite\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU RTL Design Engineer - Sr Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-27T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718325980", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nGeneral Summary\n\nQualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.\n\nWe are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you will work with chip architects to conceive of the micro-architecture, and also help with architecture/product definition through early involvement in the product life-cycle.\n\nRoles And Responsibilities\n \nPerformance exploration. Explore high performance strategies working with the CPU modeling team.\n\nMicroarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification.\n\nRTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals.\n\nFunctional verification support. Help the design verification team execute on the functional verification strategy.\n\nPerformance verification support. Help verify that the RTL design meets the performance goals.\n\nDesign delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and po\n \n\nPreferred Qualifications\n \nThorough knowledge of microprocessor architecture including expertise in one or more of the following areas: instruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, prefetching, cache and memory subsystems\n\nKnowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools\n\nKnowledge of logic design principles along with timing and power implications\n\nUnderstanding of low power microarchitecture techniques\n\nUnderstanding of high performance techniques and trade-offs in a CPU microarchitecture\n\nExperience using a scripting language such as Perl or Python\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Application Engineer – Physical Implementation", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-27", "url": "https://careers.synopsys.com/job/bengaluru/staff-application-engineer-physical-implementation/44408/99789701536", "is_hardware": true, "platform": "talentbrew", "jd_text": "Alternate Job Titles:\nStaff Application Engineer – Physical Implementation\nSenior Implementation Solutions Engineer\nStaff Engineer – RTL-GDS Flow\nCustomer Success Engineer – EDA Tools\nTechnical Application Engineer – AI/ML Implementation\nWe Are:\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are:\nYou are driven by the kind of challenges that don’t have a single right answer—only sharper questions, better tradeoffs, and a team that’s willing to iterate until the outcome is undeniable. You thrive in environments where the bar keeps moving, where priorities shift with new data, and where you’re expected to stay calm, curious, and decisive at the same time. You don’t wait to be told what to do; you look for the friction points, the recurring pain, and the moments where a small change in approach can unlock a big jump in results.\nYou bring a customer-first mindset that shows up in how you work every day. You listen carefully, clarify goals, and make sure everyone is solving the same problem before anyone starts optimizing. You communicate with precision and empathy—direct enough to prevent surprises, thoughtful enough to keep relationships strong. When something goes wrong, you treat it as a shared puzzle, not a personal failure, and you keep the focus on progress: isolate the issue, align on next steps, and close the loop with clear outcomes.\nYou’re a natural bridge-builder. You enjoy connecting dots across teams, translating needs into action, and keeping feedback grounded in real-world impact. You balance attention to detail with an instinct for the bigger picture, and you measure success by the momentum you create—helping others move faster, make better decisions, and deliver results they can stand behind.\nWhat You’ll Be Doing:\nSolving complex PPA (Performance, Power, Area) challenges using Synopsys’ latest implementation technologies, including AI/ML Implementation, Physical Synthesis RTL-GDS.\nSolving complex Formal verification challenges, early power estimation using latest technologies\nBenchmarking Synopsys solutions against competitors to displace alternative implementation flows and demonstrates uperior results.\nDeveloping, debugging, and optimizing Synthesis implementation methodologies and flows for emerging semiconductor technologies.\nProviding technical solutions by identifying design and EDA tool issues and delivering actionable resolutions for customers.\nTranslating technical findings into requirements for R&D, driving tool enhancements and adaptive long-term solutions.\nDeploying new technology features in the latest EDA tool versions and enabling customer migration for best-in-class PPA.\nProactively identifying customer pain points and proposing innovative solutions to address them.\nCollaborating closely with Synopsys R&D and product development teams to shape future technology directions.\n\nActing as a customer advocate during internal discussions and as a brand ambassador when engaging externally.\nThe Impact You Will Have:\nElevating customer success by delivering robust technical solutions and enabling optimal tool utilization.\nDriving Synopsys’ competitive advantage by displacing rival implementation flows and show casing superior PPA outcomes.\nContributing to the enhancement of Synopsys products by providing critical feedback and requirements to R&D.\nAccelerating customer adoption of new technology nodes and EDA tool versions to achieve best-in-class results.\nStrengthening Synopsys’ reputation as the industry leader in physical implementation and innovation.\nFostering long-term customer relationships through proactive engagement and continuous support.\nWhat You’ll Need:\nAt least 5+ years of experience in Synthesis, with proven ability to debug and resolve synthesis challenges, including low power understanding.\nStrong exposure to methodology changes aimed at achieving targeted PPA metrics for complex designs.\nProficiency in synthesis and formal verification tools and flows is highly advantageous.\nAdvanced scripting skills (TCL, Unix, Perl) for automation and debugging.\nExcellent communication skills, including the ability to interface effectively with customers and internal teams.\nWho You Are:\nSelf-motivated and dedicated, with a passion for continuous learning and improvement.\nStrong analytical thinker with outstanding debug skills and attention to detail.\nCollaborative team player who thrives in dynamic, fast-paced environments.\nCustomer-centric, always advocating for the best outcomes and solutions.\nResilient and adaptable, able to manage multiple priorities and deliver results.\n\nThe Team You’ll Be A Part Of:\nJoin our Application Engineering team in Bangalore, where you’ll work directly with industry pioneers and innovators. The team’s mission is to solve critical design challenges, enhance quality-of-results metrics, and empower customers to achieve best-in-class performance. Collaboration with R&D and product development is central, ensuring that customer needs drive future technology advancements. Together, we set the standards for excellence in semiconductor design and implementation.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Staff Analog layout Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-08-27", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506096", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Staff Analog layout Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and e-fuses for consumer, industrial and automotive applications. In this role, you will focus on the following.\n\n#LI-RG1\n\nResponsibilities\nProduce high quality layout for complex AMS IP blocks (voltage regulators, bandgap, current sense-amp, amplifier, high voltage switches, drivers etc) \n \nContribute to area estimation and optimization, floor planning, power routing, shielding, physical verification (DRC, ERC, LVS, ESD, etc.), as well power analysis (EM / IR-Drop) \nContribute and support team in taping out high-performance microcontroller chip \nActively seek out opportunities to work with cross-functional teams (Chip team, Tech, CAD) \nDevelop scripts and methods for layout design automation \n#LI-RG1\n\nQualifications\nBE in Electrical Engineering or related + 7 years of experience, or MS +6 years of experience preferred with experience in analog/mixed-signal layout design of deep submicron CMOS and BCD technologies\nQualification \nExperience in delivering high quality analog layout IPs \nGood understanding of layout fundamentals and best practices \nProficiency in interpretation of CALIBRE DRC, ERC, LVS, reports \nProgramming knowledge in SKILL, Perl, and/or Python is a bonus \nExperience with CADENCE or MENTOR GRAPHICS layout tools \nSolid understanding of semiconductor manufacturing process and DFM techniques \nProficient at debugging/fixing LVS/DRC errors \nMust be familiar with Cadence Design Environment (CDE) and Unix OS \nMust have strong communication skills and be a team player \n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Principal Analog Layout Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-08-27", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506101", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Principal Analog layout Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and e-fuses for consumer, industrial and automotive applications.\n\n#LI-RG1\n\nResponsibilities\nIn this role, you will focus on the following \n  Produce high-quality layout for complex AMS IP blocks (voltage regulators, bandgap, current sense-amp, amplifier, high voltage switches, drivers etc) \nContribute to area estimation and optimization, floor planning, power routing, shielding, physical verification (DRC, ERC, LVS, ESD, etc.), as well power analysis (EM / IR-Drop) \nContribute and support team in taping out high-performance microcontroller chip \nActively seek out opportunities to work with cross-functional teams (Chip team, Tech, CAD) \nDevelop scripts and methods for layout design automation \n#LI-RG1\n\nQualifications\nMinimum Requirements \nBS in Electrical Engineering or related + 10 years of experience, or MS + 8 years of experience preferred with experience in analog/mixed-signal layout design of deep submicron CMOS and BCD technologies \nQualification \nExperience in delivering high-quality analog layout IPs \nGood understanding of layout fundamentals and best practices \nProficiency in interpretation of CALIBRE DRC, ERC, LVS, reports \nProgramming knowledge in SKILL, Perl, and/or Python is a bonus \nExperience with CADENCE or MENTOR GRAPHICS layout tools \nSolid understanding of semiconductor manufacturing process and DFM techniques \nProficient at debugging/fixing LVS/DRC errors \nMust be familiar with Cadence Design Environment (CDE) and Unix OS \nMust have strong communication skills and be a team player \n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Product Test Engineer", "company": "Lattice", "location": "Hillsboro, OR", "date_posted": "2026-08-27", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Hillsboro-OR/Product-Test-Engineer_R-100991", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nWe are looking for a Product Test Engineer to join our team. This person will create test plans, design FPGA test circuits, and build automation scripts for pre-silicon verification.\n\nResponsibilities\n\nDevelop test plans using established methodologies targeted on chip IP functions and features.\n\nDesign and implement test circuits using FPGA fabric and embedded IP using Lattice’s proprietary design SW.\n\nDevelop scripts to automate test generation and own Pre-Si verification of content to ensure Si readiness.\n\nExecute Post-Si pattern validation using wafer-level ATE, package-level ATE, and package-level bench platforms across process, temperature, and voltage conditions.\n\n Identify and analyze to root cause product marginalities, communicating and coordinating root cause closure to appropriate cross-functional team (eg. Applications Engineering, Design Engineering, etc.)\n\nTake ownership of IP content development and drive any issues to resolution.\n\nPlan and execute test content delivery to meet or exceed schedules required for internal and external customers samples.\n\nExtract coverage metrics of test patterns using fault grading and review for coverage improvements.\n\nRequired Skills\n\nBS degree (Electrical, Electronics or Computer Engineering) with 8 years of industry experience, or\n\nMS degree (Electrical, Electronics or Computer Engineering) with 6 years of industry experience\n\nGood working knowledge of semiconductor devices and test methodologies\n\nExperience in ATE test program development, integration and debug on Nextest Magnum, Advantest T2K or Teradyne UltraFLEX preferred.\n\nExperience in IC characterization and/or failure analysis using various bench tools (i.e. Oscilloscope, Pattern Generators, Data Timing Generator, Multimeters, etc)\n\nExperience with WAT/etest, wafer sort, package assembly, final test (i.e. full backend IC process)\n\nExperience in Programmable Logic is desired\n\nExperience in RTL Design, Design Verification an advantage\n\nKnowledge in test, DFT methodologies (ie. scan, BIST), memory test, and fault grade methodologies an advantage\n\nKnowledge in Hardware Description Language such as Verilog or VHDL an advantage\n\nKnowledge in programming languages (ie. Python, C++)\n\nExcellent verbal and written skills.  Demonstrated ability to work with multiple groups and across cultures\n\nGood analytical and problem-solving abilities\n\nStrong Windows, Unix, and MS Office skills\n\nCurious with strong self-motivation to learn and explore\n\n#LI-DNP\nRequired Skills\n•    BS degree (Electrical, Electronics or Computer Engineering) with 8 years of industry experience, or\n•    MS degree (Electrical, Electronics or Computer Engineering) with 6 years of industry experience\n•    Good working knowledge of semiconductor devices and test methodologies\n•    Experience in ATE test program development, integration and debug on Nextest Magnum, Advantest T2K or Teradyne UltraFLEX preferred.\n•    Experience in IC characterization and/or failure analysis using various bench tools (i.e. Oscilloscope, Pattern Generators, Data Timing Generator, Multimeters, etc)\n•    Experience with WAT/etest, wafer sort, package assembly, final test (i.e. full backend IC process)\n•    Experience in Programmable Logic is desired\n•    Experience in RTL Design, Design Verification an advantage\n•    Knowledge in test, DFT methodologies (ie. scan, BIST), memory test, and fault grade methodologies an advantage\n•    Knowledge in Hardware Description Language such as Verilog or VHDL an advantage\n•    Knowledge in programming languages (ie. Python, C++)\n•    Excellent verbal and written skills.  Demonstrated ability to work with multiple groups and across cultures\n•    Good analytical and problem-solving abilities\n•    Strong Windows, Unix, and MS Office skills\n•    Curious with strong self-motivation to learn and explore\n \nIn addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! \nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nUnited States of AmericaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.\n\nAs an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.", "jd_status": "stored"}, {"title": "Senior Analog IC Design Engineer", "company": "Lattice", "location": "San Jose, CA", "date_posted": "2026-08-27", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/San-Jose-CA/Senior-Analog-IC-Design-Engineer_R-102921-1", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\n\nJob Description:\nWe are looking for a Senior Analog IC Design Engineer to join our team. This person is responsible for the design and development of analog, mixed-signal IC circuit blocks from initial specification and architecture to final, post-silicon verification to ensure specifications are met.\n\nResponsibilities include:\nAnalog, mixed-signal circuit design and simulation\n\nWork with mask designers to deliver physical design\n\nIntegration of analog/mixed-signal blocks into large, complex, digital chips\n\nDefine bench-level test plans for post-silicon characterization and debug\n\nLead/mentor junior engineers\n\nQualifications:\nBS, MS, and/or PhD in Electrical Engineering or related fields\n\nMultiple years of experience working in analog/mixed-signal circuit design (BSEE, 10+ years, MS 8+ years, PhD 5+ years)\n\nProven design experience in most of the following analog, mixed-signal circuits: SerDes receivers/transmitters, low-jitter PLLs, oscillators, phase interpolators, ADC/DAC, high speed clock distribution, bandgap/bias, and voltage regulators\n\nIn-depth knowledge of transistor mismatch, linearity, stability, low-power and low-noise techniques\n\nExperience designing circuits in advanced FinFET technologies\n\nProficient in AMS design flows, tools, and methodologies like Cadence schematic capture, Virtuoso, Spectre, layout, and analog behavioral modeling\n\nDetailed oriented, with excellent problem-solving skills, communication skills, and the ability to work collaboratively in a fast-paced, team environme\n\n#LI-DNP\n\nPay & Benefits\n\nConsistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. \n\nFor candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.  The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.\n\nBase Pay Range\n211200\nIn addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! \n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in the United States.\n\nLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.\n \nAs an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.", "jd_status": "stored"}, {"title": "Digital Eng (RTL, implementation)", "company": "Lattice", "location": "Pune, India", "date_posted": "2026-08-27", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Pune-India/Digital-Eng_R-101169", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nRole specifics:\n·       This is a full-time individual contributor position located in Pune, India.\n·       The qualified candidate will be implementing RTL to GDSII flow for complex design.\n·       The qualified candidate will lead and work on full chip backend integration and physical design including power and bump planning, floorplanning , EM-IR signoff\n·       The qualified candidate will work on DRC, LVS and other signoff checks (PERC, ESD etc) for seamless tapeout activities\n·       The qualified candidate is expected to have experience in power and bump planning and support package tapeout activities\nRole specifics:\n·       This is a full-time individual contributor position located in Pune, India.\n·       The qualified candidate will be implementing RTL to GDSII flow for complex design.\n·       The qualified candidate will lead and work on full chip backend integration and physical design including power and bump planning\n·       The qualified candidate will work on DRC, LVS and other signoff checks for seamless tapeout activities\n·       The qualified candidate is expected to have strong experience in power and bump planning and support package tapeout activities\n·       The qualified candidate is expected to have strong experience in EM-IR , signal EM, power grid integrity analysis and signoff\n·       The qualified candidate is expected to have some scripting knowledge or perl /python etc to improve design efficiency and methodology development.\n·       Collaborate with cross functional teams on timing , power and design optimization\n·       The successful candidate will be open and willing to both (a) teach best-known-methods to an existing FPGA team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and a open-minded student.\n\nAccountabilities:\n·       Drive full chip integration, EM-IR, signal EM and physical verification activities and bring best-in-class methodologies to achieve best power, performance, and area.\n·       Ensuring design quality through all physical design quality checks and signoff.\n·       Develop strong relationships with worldwide teams.\n·       Mentor and develop strong partners and colleagues.\n·       Occasional travel as needed.\n\nRequired Skills:\n·       BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent.\n·       10+ years of experience in driving backend integration activities of ASIC blocks and full chip.\n·       Experience on working with industry standard physical design tools including Innovus, Calibre, Virtuso, voltus, Tempus, conformal etc.\n·       Independent worker with demonstrated problem-solving abilities.\n·       Proven ability to work with multiple groups across different sites and time zones\n·       The qualified candidate is expected to have some scripting knowledge or perl /python etc to improve design efficiency and methodology development.\n·       Collaborate with cross functional teams on timing , power and design optimization\n·       The successful candidate will be open and willing to both (a) teach best-known-methods to an existing FPGA team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and a open-minded student.\n\n#LI-DNP\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Senior Verification Engineer, Digital IP", "company": "NXP", "location": "Bangalore", "date_posted": "2026-08-27", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Senior-Verification-Engineer--Digital-IP_R-10066046", "is_hardware": true, "platform": "workday", "jd_text": "Job Responsibility:\nResponsible for the pre-silicon verification of IP modules or, IP subsystems\nResponsible for defining and writing IP verification plans based on requirements documents (industry standards, product requirements, IP architecture and IP implementation specifications)\nInterface to HW, FW, and SW design teams, as well as to architecture and system engineering teams, to understand functionality and application of the IP or subsystem.\nResponsible for executing verification plan according to the product specification and verification requirements defined by product architects.\nResponsible for architecting, developing, debugging and running UVM based verification environment for RTL simulation.\nDefine and develop test cases in an appropriate verification framework. Create stimulus and assertions, run simulation, debug test cases on the design models (RTL, power aware RTL, gate level, FPGA, Emulation platform), run regression, collect and analyze code/functional coverage.\nJob Qualification:\nDegree in Electrical Engineering or Computer Science, with 4+ years of experience on IP/Sub-System Verification\nProven experience in testbench design and development using UVM methodology for IP/Subsystem and SOC.\nAdvanced knowledge of Verilog, System Verilog, C/C++, Shell.\nHigh proficiency in Metric Driven Verification concepts, functional and code coverage.\nHigh proficiency in directed and constrained random methodologies.\nGood knowledge of formal verification methodologies and assertions.\nExperience with debugging of designs pre- and post-silicon, in simulation and on the bench.\nExcellent written and verbal communication skill. \nGood knowledge in scripting like Perl, TCL or Python is a plus\n\nMore information about NXP in India...\n\n#LI-7013", "jd_status": "stored"}, {"title": "SoC Design Verification Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-08-27", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/SoC-Design-Verification-Engineer_JR0286654", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nAbout the Team:\nYou will be joining Intel's cutting-edge product development group, a team focused on designing and verifying advanced semiconductor solutions. This group is at the forefront of innovation, delivering high-quality, scalable products that drive Intel's leadership in technology and performance. By contributing your skills here, you will help shape the future of computing and enable groundbreaking advancements in the industry.\n\nPosition Overview:\nAs a SoC Design Verification Engineer, you will play a pivotal role in ensuring that Intel's complex System-on-Chip (SoC) designs meet functional specifications and deliver high-quality performance. You will design scalable and reusable verification plans, develop test environments, and execute tests to uncover issues and improve functionality. Your contributions will directly enhance Intel's product quality and ensure optimal performance in presilicon development.\n\nKey Responsibilities:\nCreate and update UVM-based test bench generation and test case creation\n\nDefine and develop scalable and reusable block, subsystem, and SoC verification plans\n\nCreate test benches and verification environments that align with microarchitecture specifications\n\nExecute verification plans, including emulation and system simulation models, to ensure design functionality and uncover bugs\n\nDebug and root cause issues in presilicon environments, implementing corrective measures to address failures\n\nCollaborate with architects, RTL developers, postsilicon teams, and physical design teams to improve verification of complex architectural features\n\nDocument and maintain test plans, driving technical reviews with design and architecture teams\n\nIntegrate security coverage activities within test plans, including regression and debug tests\n\nMaintain and improve existing functional verification infrastructure and methodologies\n\nAbsorb learnings from postsilicon development and incorporate feedback into improved verification strategies.\n\nTo Be Successful, You Should Demonstrate the Following:\nAbility to work collaboratively across interdisciplinary teams\n\nStrong communication skills with the ability to work across interdisciplinary teams\n\nPassion for tackling complex problems and delivering innovative solutions\n\nQualifications:\nMinimum Qualifications:\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 7+ years of hands-on experience in SoC design verification, including demonstrated expertise in OVM/UVM methodologies, debugging, and test planning\nOR\n\nMaster's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 6+ years of hands-on experience in SoC design verification, including demonstrated expertise in OVM/UVM methodologies, debugging, and test planning.\n\nThe experience must include:\nAMBA protocols such as CHI, AXI, AHB, and APB with industry-standard VIP from various EDA vendors\n\nCreation and updating of UVM-based test benches and test case creation\n\nPreferred Qualifications:\nExperience with postsilicon validation and incorporating feedback into presilicon test plans\n\nFamiliarity with emulation models and system simulation tools for performance analysis\n\nWe invite you to bring your expertise and creativity to Intel, where your contributions will make a lasting impact on future technology. Join us and shape the future of computing with your skills and dedication.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "SoC Design Verification Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-08-27", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/SoC-Design-Verification-Engineer_JR0286653", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nAbout the Team:\nYou will be joining Intel's cutting-edge product development group, a team focused on designing and verifying advanced semiconductor solutions. This group is at the forefront of innovation, delivering high-quality, scalable products that drive Intel's leadership in technology and performance. By contributing your skills here, you will help shape the future of computing and enable groundbreaking advancements in the industry.\n\nPosition Overview:\nAs a SoC Design Verification Engineer, you will play a pivotal role in ensuring that Intel's complex System-on-Chip (SoC) designs meet functional specifications and deliver high-quality performance. You will design scalable and reusable verification plans, develop test environments, and execute tests to uncover issues and improve functionality. Your contributions will directly enhance Intel's product quality and ensure optimal performance in presilicon development.\n\nKey Responsibilities:\nCreate and update UVM-based test bench generation and test case creation\n\nDefine and develop scalable and reusable block, subsystem, and SoC verification plans\n\nCreate test benches and verification environments that align with microarchitecture specifications\n\nExecute verification plans, including emulation and system simulation models, to ensure design functionality and uncover bugs\n\nDebug and root cause issues in presilicon environments, implementing corrective measures to address failures\n\nCollaborate with architects, RTL developers, postsilicon teams, and physical design teams to improve verification of complex architectural features\n\nDocument and maintain test plans, driving technical reviews with design and architecture teams\n\nIntegrate security coverage activities within test plans, including regression and debug tests\n\nMaintain and improve existing functional verification infrastructure and methodologies\n\nAbsorb learnings from postsilicon development and incorporate feedback into improved verification strategies.\n\nTo Be Successful, You Should Demonstrate the Following:\nAbility to work collaboratively across interdisciplinary teams\n\nStrong communication skills with the ability to work across interdisciplinary teams\n\nPassion for tackling complex problems and delivering innovative solutions.\n\nQualifications:\nMinimum Qualifications:\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 7+ years of hands-on experience in SoC design verification, including demonstrated expertise in OVM/UVM methodologies, debugging, and test planning\nOR\n\nMaster's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 6+ years of hands-on experience in SoC design verification, including demonstrated expertise in OVM/UVM methodologies, debugging, and test planning.\n\nThe experience must include:\nAMBA protocols such as CHI, AXI, AHB, and APB with industry-standard VIP from various EDA vendors\n\nCreation and updating of UVM-based test benches and test case creation\n\nPreferred Qualifications:\nExperience with postsilicon validation and incorporating feedback into presilicon test plans\n\nFamiliarity with emulation models and system simulation tools for performance analysis\n\nWe invite you to bring your expertise and creativity to Intel, where your contributions will make a lasting impact on future technology. Join us and shape the future of computing with your skills and dedication.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Sr. Memory Layout Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-08-27", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Sr-Memory-Layout-Design-Engineer_R026703-1", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nJob Requirements:\n- Minimum 5 years of experience with strong layout knowledge\n- Bachelor's degree required.\n- Proficiency in using Cadence tools (virtuotso layout, layotu XL, Cadence schematic capture, and verification tools - CALIBRE & Hercules).\n- Strong layout knowledge in submicron processes (e.g. 7nm, 5nm, 3nm, 2nm).\n- Experience in digital layout (Standard cell, Memory, I/O); analog layout experience is a plus.\n\nJob Description:\n- Understand and apply layout guidelines, new process rules, and technical requirements for good quality layout.\n- Manage scheduling, timelines, and layout floor-planning.\n- Responsible for start to end deliverables with quality within the planned schedule.\n- Adapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the SOC/library team.\n\nSkill Set (Memory):\n- Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes.\n- Experience with Cadence Layout tools (VIRTUOSO XL, VXL, or EXL) and CALIBRE verification tools.\n- Proficiency in floor-planning, hierarchy layout, and chip integration.\n- Understanding of memory architecture, RC requirement, ability to plan signal and power, based on the layout guidelines\n- Knowledge of AI, automation in layout, Script Programming and SKILL Programming is a plus.\n- Ability to lead, train junior engineers, and manage projects effectively.\n- Good knowledge of memory layout topology; experience with memory compilers is a plus.\n- Ability to lead new technology reviews to document layout methodologies, flows, and guidelines.\n- Self-reliant with the ability to work both independently and collaboratively.\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Staff Engineer Applications", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-08-26T11:40:39+00:00", "url": "https://jobs.infineon.com/careers/job/563808969989688", "is_hardware": true, "platform": "eightfold", "jd_text": "Seeking an experienced Senior Hardware Engineer with 6-9 years of expertise to lead design and development of evaluation kits and reference designs for Infineon Microcontrollers, including advanced edge computing, control series, and radio devices.\n\n \n\nYour Role\n \n Key responsibilities in your new role:-\nLead development of evaluation and reference design for MCUs and Radio devices.\nCreate complex schematics using Cadence tools (OrCAD, Allegro), manage PCB layout, prototype testing, and ensure industry compliance.\nPerform bring-up, testing and debugging of     boards including signal integrity, power integrity, and EMI/EMC analysis.\nCollaborate with cross-functional teams and mentor junior engineers.\nInterface with stakeholders and derive system architecture and technical documentation.\n\n \n\nYour Profile\n \n Qualifications and skills to help you succeed:\n\nEducation & Experience:\n\nBachelor's or Master's degree in Electronics/Electrical Engineering.\n6-9 years hardware design experience with proven product launches.\nExperience with microcontroller-based design and industrial control systems design\nTechnical Expertise:-\nAdvanced proficiency in Cadence tools (OrCAD,     Allegro)\nDigital and analog circuit design expertise including basic serial communication protocols like UART, SPI, I2C, USB and advanced protocols like SDHC, MIPI, etc.\nSolid understanding of power electronics     circuits and topologies including regulator design and drive controls.\nExpertise in Microcontroller based system     designs\nStrong understanding and real-time control systems including motor control.\nProficient with lab instrumentation for hardware debugging and validation.\nGood understanding of designs involving Radio     devices\nProfessional Skills: \nStrong problem-solving and analytical abilities for systematic root cause analysis and sound technical decision\nProven leadership and communication skills to mentor engineers, leads technical discussions with stakeholders.\nExperience managing cross-functional teams and multiple projects with measurable results\nNice to Have:\n\nFamiliarity with programming languages, such as C, C++, or Python.\nFamiliarity with AI/ML frameworks.\nKnowledge of industry standards and regulations, including FCC, CE, and RoHSz.\n\n \n\n#WeAreIn for driving decarbonization and\ndigitalization.\n As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\n Are you in?\n \n We are on a journey to create the best Infineon for everyone.\nThis means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.\n Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.\n Click here for more information about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Principal Analog Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-26T09:30:39.156000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000145696440-principal-analog-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Individual Contributor role for Technical leader with 15+ years of experience in Analog and Power IC development within 2.6B$ Power Business Unit at Renesas. Primary responsibilities include leading the design and development of power management ICs, including voltage regulators, power converters, and other related components and collaborate with cross-functional teams to ensure successful integration of ICs into larger systems. The candidate will work on a wide range of exciting and cutting edge PMICs, including Linear and Switching DC-DC converters powering the next generation of most sought-after phones and handheld devices. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas’s massive Power product portfolio. In the Technical leader role, candidate will be directly responsible for end-to-end IC design (from specifications to PRA). Will be expected to work with other team members to do successful Chips along with mentoring the junior members. This is an IC role with complete focus on product development and no people management.\nEssential Functions:\nMust have led and should be experienced of developing multiple Power ICs with Switching Converters, starting from system level specifications and taking ICs to production.\nIdentify and resolve technical challenges and risks. Provide technical expertise and mentorship to junior engineers. Able to lead group of Engineers and navigate through all stages of IC development while handling and mitigating challenges, ensuring high quality silicon while adhering to the schedules based on business needs.\nMust be proficient in designing complete switching converters and all involved I/Ps. Should be fully aware of all challenges pertaining to high current/power switching converters design including Noise, Power dissipation etc and their mitigation.\nShould have a very good understanding of Power devices, operations and design trade-offs for better performance & reliability.\nShould be able to lead and guide development, integration of complex I/Ps like +ve/-ve Charge Pumps, Source-Sink LDOs, Ultra-low power Oscillators (including Relaxation type), Temperature Sensor, Current Sense, SAR ADCs, House Keeping blocks, Protection (Thermal, Under-Voltage, Over-Voltage, Over Current etc) and other analog blocks including Bandgap references, V2I, Analog Buffers, Op-Amps, Comparators, High speed level shifters etc. Thorough understanding of Switch Cap circuits is a must.\nMust have in-depth understanding of and should be able to choose, design & compensate Control loops keeping in mind the target performance.\nMust have done multiple silicon debugs, root cause analysis of issues, design to silicon correlation etc.\nShould be able to architect the IC and break down System/Chip-top level requirements into block level specifications and then work with Team members and develop the blocks, integrate the blocks into Top level and ensure desired performance.\nMust have good understanding of commonly used control loop architectures (Constant Freq, Constant ON/OFF Time, Current mode etc) and pros/limitations of each.\nMust be able to bring in innovative ideas to improve designs to meet challenging specifications and achieve better system performance.\nShould have in-depth knowledge of Analog layouts, FET layouts, Noise isolation techniques and be able to guide the layout development from floor planning till Chip Top completion and verification and do trade-offs based on desired performance.\nMust be conversant with the standard design, extraction and simulation flows & tools, speed, convergence, accuracy trade-offs and should be able to optimize setups based on Pre/Post (with/without) Parasitic using simulator options, debug and navigate through tool related challenges.\nShould be able to setup design flows and methodologies including checklists, reviews to ensure quality designs and take them all the way to Silicon success.\nShould be able to mentor Freshers and Junior engineers for upscaling their technical skills as well as other skills needed for better efficacy.\nShould have in-depth understanding of ESD, LU and other IC level issues and be able to define protection for the I/O ring for the IC\n\nMinimum Requirements:\nBachelor’s or master’s degree in electrical engineering\n15+ years in Analog Circuit Design.\nSolid understanding and design experience of complex analog designs with full ownership.\nChip design, Verification, Silicon validation, debugs, Qual support and taking ICs to production.\nMust be a technical leader & natural team player, mentor and should strive towards fostering a highly creative and productive working environment\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Project Manager Analog Mixed Signal Methodology", "company": "Infineon", "location": "Bangalore", "date_posted": "2026-08-26T05:31:54+00:00", "url": "https://jobs.infineon.com/careers/job/563808971874517", "is_hardware": true, "platform": "eightfold", "jd_text": "Join our Semiconductor I/O Development team and drive complex projects from concept to delivery. Lead cross-functional teams, collaborate with global stakeholders, and play a key role in delivering high-quality, innovative I/O solutions while shaping the future of semiconductor technology. If you are passionate about project leadership, technical excellence, and driving results in a dynamic environment, we'd love to hear from you.\n\nYour role\nKey responsibilities in your new role\n\nLead project management for I/O component development projects with medium to high complexity.\nManage cross-functional and geographically distributed project teams to ensure successful project execution.\nTake end-to-end ownership of project delivery, ensuring timely completion within budget, scope, and quality targets.\nAlign project requirements, including functionality, quality, schedule, and budget, with internal and external stakeholders.\nDrive project planning activities, including resource allocation, schedule management, and technical deliverable tracking.\nMonitor and control project progress, costs, risks, and timelines to ensure execution against commitments.\nPrepare and present regular project status updates, reports, and key metrics to stakeholders and management.\nLead escalation management and proactively resolve project challenges and risks.\nManage customer and stakeholder communication, ensuring alignment and transparency throughout the project lifecycle.\nFoster strong collaboration and effective interaction among all involved teams, functions, and external partners.\nContinuously identify opportunities to improve project execution, processes, and team effectiveness.\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor’s or Master’s degree in Electronics Engineering, Electrical Engineering, or a related field.\n12+ years of overall industry experience, with at least 5+ years of project management experience in the semiconductor industry.\nStrong technical background in I/O development or related semiconductor design domains.\nProven ability to manage complex projects, mitigate risks, and thrive in challenging environments.\nDemonstrated ambition to drive excellence, innovation, and continuous improvement.\nStrong execution skills with a focus on efficiency, quality, and timely delivery.\nExcellent communication and presentation skills, with the ability to engage senior stakeholders.\nPMP or other Project Management certifications are highly desirable and considered a strong advantage.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\n\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Video Design Verification Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-26T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720710670", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nLooking for candidates between 1 to 13 years of experience. \nWorked on coverage driven module verification.\nStrong in System Verilog, UVM\nSound experience in testbench (stimulus, agent, monitor, checker) development.\nFailure debugging with Verdi & log file.\nWorked in the verification having c based reference model inside the testbench\nExperience with assertion development.\nFamiliar with the EDA tools IUS, VCS, Verdi etc.\nExposure in scripting(perl, Python).\nGood team player. Need to interact with the designers and other verification engineers proactively.\nPrior experience with video pipeline is added advantage. \nKnowledge of tensilica\nWorked with sub-system verification with tensilica\nExperience in C based system modelling.\nDebug with C based reference model.\nHave exposure to the other verification tasks : gate level simulation, Power aware simulation, formal verification, sub-system verification and emulation.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Hardware Board Design Engineer, Senior", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-26T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720721186", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nSummary of Responsibilities: Design, review, and debug digital PCB designs, breakout boards, and test platforms using industry-standard CAD tools such as Mentor Graphics Xpedition/DA or Cadence Allegro. Apply strong electronics engineering fundamentals and PCB manufacturing knowledge to support board design, bring-up, validation, and issue resolution. Perform board-level bring-up, debugging, and failure analysis of high-speed digital systems and interfaces. Drive Signal Integrity (SI) and Power Integrity (PI) analysis for PCB designs, leveraging simulation tools such as HFSS, ADS, and PowerSI to optimize performance. Characterize and validate high-speed digital channels using measurements including S-parameters, TDR, eye diagrams, jitter, isolation, and crosstalk. Support design, validation, and debug of high-speed interfaces such as PCIe, CSI, USB, and PAM-based links, ensuring compliance with protocol and performance requirements. Execute lab-based validation and debug using equipment such as Vector Network Analyzers (VNA), Digital Storage Oscilloscopes (DSO), and Logic Analyzers. Collaborate closely with cross-functional teams including Hardware, SI/PI, ASIC, System, Manufacturing, and Test Engineering teams to drive product development and issue closure. Document design reviews, validation results, debug findings, and technical recommendations in a clear and structured manner. Support program execution by communicating technical status, risks, and key findings effectively with global engineering teams and stakeholders.\n \n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Electro-Magnetic Design Engineer, Senior", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-26T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720724327", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nJob Overview:\nQualcomm is the industry leader in 3G, 4G and 5G communication technology and designs the most advanced radio technology in the commercial wireless marketplace, from 5G/6G to Bluetooth.\nQCT's RF Electro-Magnetic (EM) Design Team is actively seeking engineers with demonstrated experience in the design, EM simulation, and circuit modeling of RF passive components for use in our RFIC designs. Exposure to RF package, module, and PCB design and modeling is a plus.\nKnowledge of PCB level Power Distribution Network (PDN) and RF transmission line layout and analysis is an asset.\nWorking experience and knowledge of Power Amplifier (PA) and Low Noise Amplifier (LNA) matching is an advantage.\nBasic understanding of patch antenna design parameters and matching is also desired.\n  Responsibilities:\nDesign and develop RF passive components for use in the next generation of highly integrated RF integrated circuits in deep sub-micron 28nm/14nm/6nm/2nm CMOS and SOI technologies.\nWork with the circuit design team to optimize component sizes and performance for use in on-chip RF circuit blocks.\nDeliver components that include compact models, and DRC clean physical designs.\nExecute isolation analysis and optimization to reduce on-chip and chip to package coupling.\nOptimization of multichip carriers for RF systems, focusing on loss and isolation.\nParticipate in RF package, module, and PCB modeling to optimize overall system performance \nSkills and Experience:\nExperience in the design and simulation of RF passive components such as inductors, transformers, MOM/MIM capacitors and passive filters.\nDemonstrated abilities with EM simulation techniques and tool including MoM EM solvers and HFSS.\nExperience with circuit design and layout using Cadence tools and Agilent ADS.\nCompact RLCK Model extraction of multiport passive components.\nAbility to use EM tools to predict circuit level electric and magnetic coupling.\nUnderstanding of Chip fabrication process and design understanding\nElectromagnetic theory, microwave theory and design\nAntenna design and understanding of radiation and propagation wave\nGood understanding of SI and PI at chip, package, and PCB level\nBasic RF system understanding\nUnderstanding of noise propagation mechanism in chip, package, and PCB\nTools: Ansys Suit (HFSS, Q3D, SiWave, Layout), Lorentz, Helic, EMX, Cadence virtuoso, Allegro or similar for Package/Module layout, Expedition (or similar) for PCB layout and schematic, VRF\nPassionate self-starter and team player with experience in project leadership and multi-tasking.\nKeywords:\nOn-chip passive, Inductor, Transformer, MOM/MIM Capacitor, Antenna, Signal and Power Integrity, PDN, Substrate coupling, RF Module, RF Package modeling, HFSS, Ansys, ADS, VRF\nEducational Requirements:\nRequired: Bachelor’s degree in science, Engineering, or related field. Preferred: Master's and PhD\n\nMinimum Qualifications:\n•    Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nMaster's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.\n                                                                    OR\nPhD in Science, Engineering, or related field.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SOC Design -Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-26T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720696957", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    5+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Engineer- EDA ML Tools - Customer Engineering(Physical Design)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-26T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718485876", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Software Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Machine Learning Engineer, you will create and implement machine learning techniques, frameworks, and tools that enable the efficient discovery and utilization of state-of-the-art machine learning solutions over a broad set of technology verticals or designs. Qualcomm Engineers collaborate with cross-functional teams to enhance the world of mobile, edge, auto, and IOT products through machine learning hardware and software.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Engineering, Information Systems, or related field and 4+ years of Hardware Engineering, Software Engineering, Systems Engineering, or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Engineering, Information Systems, or related field and 3+ years of Hardware Engineering, Software Engineering, Systems Engineering, or related work experience.\n                                                                    OR\nPhD in Computer Science, Engineering, Information Systems, or related field and 2+ years of Hardware Engineering, Software Engineering, Systems Engineering, or related work experience.\n\nStaff – Application/ Customer Engineering  \nRole Overview \nWe are looking for a Staff Engineer with strong domain expertise in VLSI/EDA tools and workflows to drive adoption, usability, and reliability of internal GenAI/Agentic AI tools and platform. \nThis role requires deep hands-on usage, triaging expertise, and customer engineering experience, acting as the bridge between Physical Design Engineers/CAD teams, Software and Systems engineering team. \nThe ideal candidate has exposure to AI/GenAI systems and can understand and debug workflows involving EDA tools, AI agents, orchestration pipelines, and non-deterministic system behaviors. \nKey Responsibilities \n- Own end-to-end user support and triage workflows; debug complex EDA environment, configuration and software integration issues \n- Diagnose workflow failures across toolchains, configurations, and infrastructure \n- Drive deep product understanding through hands-on tool usage across real workflows \n- Translate user requirements and issues into clear, actionable engineering inputs \n- Configure and onboard new projects and users; enable scalable adoption \n- Define and maintain real-world test cases and reproducible debugging scenarios \n- Collaborate with dev/QA teams to improve observability, debuggability, and stability \n- Debug AI/GenAI agent workflows, including orchestration failures, tool invocation issues, and non-deterministic behavior \n- Ensure tools operate in an agentic model with autonomous execution (MCP-based access) and minimal manual intervention \n- Define and validate clear functional specifications covering capabilities, inputs, outputs, and expected behavior \n- Drive structured enablement plans with phased onboarding, deliverables, acceptance criteria, and timelines \n- Develop comprehensive test strategies including shared and hidden testcases for robust validation \n- Measure tool performance using objective QoR metrics (TNS, WNS, congestion, runtime, memory) \n- Integrate tools into automated validation/regression pipelines for continuous testing and reporting \n- Enable usage telemetry collection (feature usage, runtime distribution, error trends) to support data-driven improvements \nRequired Skills & Experience \n- 9-12 years in Applications Engineering / Customer Engineering preferably in Physical Design (PNR/Floor planning) \n- Strong domain knowledge in VLSI / Physical Design / EDA workflows \n- Knowledge of Agentic AI /MCP/RAG workflows \n- Proven expertise in triaging and debugging complex software/tool issues \n- Strong Python/Linux/scripting experience \n- Ability to independently run and debug end-to-end workflows \n- Strong problem decomposition and root-cause analysis skills \n- Excellent communication and cross-functional collaboration \nPreferred Qualifications \n- Experience with AI/GenAI tools, agent frameworks, or orchestration systems \n- Familiarity with evaluation, benchmarking, or validation pipelines \n- Exposure to CI/CD, large-scale systems and HPC environments \n- Experience improving workflows, UX, or developer productivity \nPositioning \nThis is a hands-on Applications / Customer Engineering role with strong domain expertise, triage ownership, and AI/GenAI workflow understanding — not a Product Manager role.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU Design Verification Assoc Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-26T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446717553913", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nQualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement.\n\nRoles and Responsibilities\n\no   Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling.\no   Work closely with design/verification teams within CPU to develop comprehensive test plan.\no   Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus.\no   Verify power intent through use of methodologies like UPF.\no   Work closely with system architects, software teams and Soc team to validate system use cases.\no   Work closely with emulation team to enable verification on emulators and FPGA platforms.\no   Debug and triage failures in simulation, emulation and/or Silicon.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nBE/BTech degree in CS/EE with 12+ years’ experience.\n\no   Experience in power management verification.\no   Implementation of assembly and C language embedded firmware.\no   Experience in C/C++, scripting languages, Verilog/system Verilog.\no   Strong understanding of power management features in CPUs and CPU based Socs.\no   Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.\n\nPreferred Requirements:\n\no   Good Understanding of CPU architectures and CPU micro-architectures.\no   In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture\no   Experience with advanced verification techniques such as formal and assertions is a plus\no   Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Applications Engineering, Staff Engineer STA Expert", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-26", "url": "https://careers.synopsys.com/job/bengaluru/applications-engineering-staff-engineer-sta-expert/44408/99760751888", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nYou treat ambiguity as an invitation to bring clarity, not as a reason to slow down. Stepping into complex, high-stakes moments with a steady presence comes naturally to you. You listen carefully for what's unsaid, ask the questions that unlock momentum, and align people around the real problem, not just the loudest symptom. Tight timelines and high expectations energize you because you know how to prioritize what matters, communicate tradeoffs early, and keep progress visible without creating noise.\nPartnership over posturing defines how you approach customers and internal teams. The back-and-forth of discovery energizes you, and you naturally translate between technical, business, and everything in between so decisions get made with confidence. You don't just deliver answers. You build trust by being transparent, direct, and constructive, especially when the message is hard. When something breaks, curiosity and methodical thinking guide you as you trace causes with patience while keeping the bigger picture in view.\nConstantly looking for leverage is part of who you are. Patterns reveal themselves to you, one-off fixes become repeatable playbooks, and you leave behind cleaner processes than you found. Precision balanced with pragmatism helps you know when to go deep and when to move forward with a well-framed assumption. Above all, you bring a collaborative intensity that is calm, driven, and generous, helping the team move faster together while keeping quality and integrity non-negotiable.\n\nWhat You'll Be Doing\nSupport Synopsys PrimeTime Static Timing Analysis tool across pre-sale evaluations, post-sale deployments, and ongoing customer engagements\nDrive product adoption by running competitive benchmarks, leading customer evaluations, and articulating technical advantages to design teams and engineering management\nDeliver customer training sessions, technical presentations, and hands-on workshops that maximize user proficiency and satisfaction with PrimeTime\nProvide tape-out support by troubleshooting complex timing issues, resolving signal integrity problems, and ensuring successful project completion under deadline pressure\nCollaborate with R&D, product marketing, and sales teams to relay customer feedback, influence product enhancements, and shape roadmap priorities\nDevelop and maintain technical documentation, best practices guides, and knowledge base resources that scale your expertise across the customer base\nParticipate in advanced customer collaboration initiatives that drive innovation, uncover new use cases, and strengthen long-term partnerships\n\nThe Impact You Will Have\nAccelerate customer project timelines by enabling efficient use of PrimeTime and optimizing design flows that remove timing closure bottlenecks\nEnhance customer satisfaction and loyalty through expert support, proactive problem-solving, and training that builds internal capability\nStrengthen Synopsys' leadership in static timing analysis and semiconductor design solutions by delivering measurable wins in competitive engagements\nFacilitate feedback loops between customers and internal teams that drive continuous innovation in product features, usability, and performance\nEmpower customers to achieve superior chip performance, power efficiency, and cost optimization that directly affect their product success\nContribute to successful tape-outs and high-impact design wins for industry-leading clients building next-generation silicon\nBuild reusable methodologies and documentation that multiply your impact across the global customer base and internal teams\n\nWhat You'll Need\nDeep hands-on expertise in Synopsys PrimeTime STA tool, including advanced features, timing analysis methodologies, and real-world application across multiple design nodes\nStrong understanding of timing corners, process variations, signal integrity issues, and how they affect timing closure in modern semiconductor designs\nFamiliarity with synthesis, physical design, extraction, and ECO methodologies, and how they integrate with static timing analysis workflows\nProficiency in TCL scripting for automation, tool customization, and workflow optimization\nExcellent verbal and written communication skills with experience in customer-facing roles, experience delivering technical training or presentations is a plus\nBSEE or equivalent with 5+ years of relevant experience, or MSEE or equivalent with 3-4 years of experience in applications engineering, design, or verification roles\n\nWho You Are\nYou collaborate naturally, valuing diverse perspectives and fostering environments where different technical viewpoints strengthen the outcome\nProactive problem-solving defines your approach. You work independently, manage multiple priorities without losing threads, and know when to escalate or pull in help\nAdaptable and resilient, you thrive when priorities shift, timelines compress, or technical challenges require creative thinking under pressure\nDetail-oriented with a commitment to delivering high-quality results, you catch the edge cases and corner conditions that others miss\nYou can explain a complex timing closure tradeoff to a customer VP in two sentences without losing the nuance, and then turn around and debug a TCL script with an engineer\nYou notice when a customer question signals a deeper workflow issue, and you address both the immediate ask and the underlying gap\n\nThe Team You'll Be Part Of\nYou'll join a talented applications engineering team that supports the industry-leading Static Timing Analysis tool, PrimeTime. The team's core purpose is to drive increased product usage, ensure customer success, and collaborate closely with R&D, marketing, and sales to foster innovation. Together, you will enable customers to build next-generation silicon chips faster and more efficiently, playing a vital role in Synopsys' global leadership in chip design and verification.\n\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Hardware Development Engineer", "company": "Nokia", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-08-26", "url": "https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/39880", "is_hardware": true, "platform": "oracle", "jd_text": "As an Hardware Development Engineer, you will play a crucial role in the NI ON PSE HW&TE GX Syst HW & CentEng 5 (L06) department. They will work on mechanical design, collaborating closely with cross-functional teams to deliver cutting-edge optical transceiver products. This role offers an exciting opportunity to contribute to the development of next-generation pluggable form factors and drive the future of optical networking.\n\nNILightpath\n\nResponsibilities\nWork on mechanical design and packaging for OSFP, OSFP-XD, QSFP-DD, and other pluggable form factors.\nDesign high-density, thermally optimized solutions for 100G, 400G, 800G, and 1.6T transceiver modules.\nWork closely with Optics, Electronics, Thermal, and other teams from concept to production.\nDrive design-for-manufacturing (DFM) and cost optimization initiatives.\nEnsure compliance with MSA standards, customer requirements, and manufacturing processes.\nLead the mechanical architecture decisions for next-generation pluggable products.\nSupport product qualification and validation activities, including FAI, DVT, and PVT.\nPerform root-cause analysis and implement corrective actions for manufacturing issues.\nCollaborate with global suppliers and manufacturing partners to ensure smooth operations.\n\nQualifications\nB.E./B.Tech/M.Tech in Mechanical Engineering or a related field.\n3+ years of mechanical product design experience, preferably in optical modules or compact electronic systems.\nExpertise in Creo Parametric or equivalent 3D CAD tools for part and assembly modeling.\nStrong understanding of mechanical packaging, tolerance engineering, and GD&T.\nHands-on experience with precision machining, sheet metal fabrication, and other manufacturing processes.\nAbility to perform engineering calculations for latch forces, insertion/extraction forces, and more.\nUnderstanding of material properties and selection for various components.\nExcellent communication and problem-solving skills for cross-functional collaboration.\nExperience in a high-volume manufacturing environment is preferred.\nA proven track record of delivering optical transceiver products from concept to production is an asset.\n\nAbout the company\nAdvancing connectivity to secure a brighter world.\n\nNokia is a global leader in connectivity for the AI era. With expertise across fixed, mobile and transport networks, powered by the innovation of Nokia Bell Labs, we’re advancing connectivity to secure a brighter world. \n\nLearn more about life at Nokia.\n\nOur recruitment process\n\nWe act inclusively and respect the uniqueness of people. Our employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.\n\nIf you’re interested in this role but don’t meet every listed requirement, we still encourage you to apply. Unique backgrounds, perspectives, and experiences enrich our teams, and you may be just the right candidate for this or another opportunity.\n\nThe length of the recruitment process may vary depending on the specific role's requirements. We strive to ensure a smooth and inclusive experience for all candidates. Discover more about the recruitment process at Nokia.\n\nAbout the organization\nSome of our benefits in India:\n\nFlexible and hybrid working arrangements to support work–life balance\n\nHealth and well-being support – medical insurance for you and your family, health check-ups, life and accident insurance, well-being programs, and employee resource groups \n\nA minimum of 90 days of Maternity and Paternity Leave based on eligibility\n\nPersonal Support Service 24/7 – a confidential support channel open to all Nokia employees and their families in challenging situations\n\nCareer growth & mobility – technical career paths, job rotations, international assignments, and relocation support\n\nContinuous learning – technical certifications, mentoring programs, coaching, and digital learning platforms\n\nOpportunities to innovate and contribute through Nokia’s research and development environment\n\nRecognition programs that celebrate outstanding contributions\n\nWorkplace support – ergonomic working support and mobile device programs based on eligibility", "jd_status": "stored"}, {"title": "Analog Design Flow and Infrastructure Design Automation Manager", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-08-26", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Analog-Design-Flow-and-Infrastructure-Design-Automation-Manager_JR0286600-1", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nWe are seeking an experienced Analog Design and Infrastructure DA Manager to lead the development, deployment, and governance of analog/mixed-signal design environments and CAD infrastructure. This role owns EDA tool ecosystems, PDK integration, compute infrastructure, design data governance, and tapeout manifest management to ensure high productivity, reproducibility, and audit readiness across silicon programs..The ideal candidate combines deep analog/mixed-signal design flow and e-test structure development expertise with strong infrastructure leadership and disciplined configuration/data management practices.\nKey Responsibilities-1. Analog Design Environment and Flow Management-Own and maintain analog and mixed-signal design flows using platforms such as Virtuoso ,Develop and maintain schematic, layout, verification, and extraction flows (LVS, DRC).Support simulation environments including HSPICE, Corner analysis.Drive automation and methodology improvements to reduce turnaround time and increase design robustness.\n\n2. Infrastructure and Compute Management\n\nOversee Linux-based DA infrastructure including compute farms, storage systems, and license servers (FlexLM).\nManage LSF/grid environments and job scheduling systems.\nEnsure scalability, system monitoring, high availability, and performance optimization.\nPartner with IT on hardware lifecycle planning, cloud integration, and disaster recovery.\nMaintain secure, access-controlled design environments aligned with IP protection policies.\n\n3. Design Data, Manifest and Configuration Management\n\nDesign Data Governance\nManage large-scale analog design libraries, hierarchical database structures, and technology libraries.\nDefine backup, archival, and retention policies for tapeout-critical data.\nImplement data integrity validation and corruption prevention controls.\nOversee distributed storage systems optimized for EDA workloads.\nManifest and Tapeout Release Management\nOwn creation and governance of tapeout manifests including: PDK Versions, Tool Versions, Extraction/Verification Decks, Simulation Models, Signoff Configurations\nEstablish reproducible environment release frameworks for analog programs.\nImplement controlled qualification flows for tool/PDK upgrades prior to production rollout.\nMaintain environment snapshots to ensure reproducibility and post-silicon traceability.\nSupport formal tapeout readiness and design signoff reviews.\nVersion Control and Configuration Management\nDeploy and manage version control systems (Git, Cliosoft, SVN, Perforce,) for: CAD scripts and automation, Methodology flows, PDK overlays, Verification decks\nDefine branching, tagging, and release strategies for multi-project and multi-node environments.\nImplement dependency tracking across tools, PDKs, IP, and infrastructure.\n\nApply infrastructure-as-code principles where applicable.\n\nAutomation and Traceability\n\nDevelop automated environment capture tools to log tool versions, library states, and system configurations.\nEnable reproducible simulations and environment packaging.\nCreate dashboards and reporting metrics for design data health and DA service KPIs.\n\n4. Leadership and Cross-Functional Collaboration\n\nLead and mentor DA and infrastructure engineers.\nServe as the primary interface between analog design, digital CAD, IT, and EDA vendors.\nDrive tool evaluations, upgrades, and vendor negotiations.\nDevelop internal documentation, training programs, and best practices.\nEstablish measurable service-level KPIs and continuously improve DA operations.\n\nQualifications:\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.\n10+ years of experience in analog/mixed-signal design or CAD support.\n5+ years of leadership experience.\nStrong hands-on experience with analog design platforms such as Virtuoso and p-cell development. Custom Compiler.\nDeep understanding of analog layout, verification flows, PDK integration, and tapeout processes.\nProven experience managing design data governance and tapeout manifest control.\nStrong Linux system administration and scripting skills (Python, Tcl, Shell, SKILL).\nExperience with compute grid management, storage architecture, and license management.\nExpertise in version control and configuration management systems\n\nPreferred Qualifications\n Experience with advanced nodes (FinFET, GAA).\nKnowledge of CI/CD practices applied to EDA environments.\nExperience supporting geographically distributed design teams\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Staff High-Speed Analog Designer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-26", "url": "https://careers.synopsys.com/job/bengaluru/staff-high-speed-analog-designer/44408/100351393168", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years designing analog circuits that need to hit power, area, and performance targets in unforgiving process nodes, and you have learned that the best architectures are the ones you can actually close in layout. You think in tradeoffs, not ideals. When you read a SerDes standard, you see the circuit blocks underneath it, and you already have two or three candidate topologies sketched out before the spec is finalized.\nYou are comfortable moving between transistor-level design and system-level thinking. You know that a VCO phase noise spec is meaningless without understanding the PLL loop dynamics, and you can explain that relationship to a digital designer or a customer without losing the thread. Layout is not something that happens after you finish the schematic. It is part of your design process, and you have strong opinions about how parasitics, stress, and mismatch should shape your floorplan from day one.\nYou do not wait for perfect simulation corners to declare a design done. You run the right simulations, interpret the data, and make calls. At Synopsys, you will work on multi-Gbps NRZ and PAM4 SerDes IP in the latest FinFET nodes, alongside a team that takes analog design seriously and has the tools and support to back it up.\nWhat You'll Be Doing\nDesign and develop analog sub-blocks for multi-Gbps NRZ and PAM4 SerDes IP, including equalizers, samplers, drivers, VCOs, PLLs, DLLs, ADCs, DACs, and serializers/deserializers\nReview SerDes standards and translate them into block-level specifications that balance power, area, and performance across the latest FinFET process nodes\nIdentify and refine circuit architectures, evaluating multiple topologies and making design decisions that account for layout constraints, process variation, and reliability\nOversee physical layout implementation, working closely with layout engineers to minimize parasitics, manage device stress, and ensure robust matching and ESD protection\nDevelop simulation strategies using SPICE simulators, Verilog-A behavioral models, and scripting (TCL, Perl, Python, MATLAB) to verify circuit performance across corners and conditions\nPresent simulation data and design reviews to peers and customers, documenting design features, test plans, and tradeoffs\nConsult on post-silicon characterization and propose design updates based on electrical test results\nThe Impact You Will Have\nYour circuit architectures will directly shape the power, area, and performance of SerDes IP that ships in high-volume semiconductor products\nThe design strategies and verification methods you develop will become reference flows for the analog team, raising the bar for quality and efficiency\nYour layout oversight will reduce post-silicon surprises, cutting time to market and improving first-pass silicon success rates\nThe simulation data and documentation you produce will enable faster customer adoption and smoother integration of SerDes IP into SoC designs\nYour collaboration with digital designers and software teams will strengthen cross-functional design practices and improve overall IP robustness\nThe design-for-reliability and ESD techniques you implement will extend product lifetime and reduce field failures\nYour contributions to post-silicon debug will close the loop between design intent and measured performance, driving continuous improvement\nWhat You'll Need\nBachelor's degree with 6+ years of relevant experience or Master's degree with 4+ years of relevant experience in Electrical Engineering, Computer Engineering, or a related field\nDeep transistor-level circuit design experience with strong CMOS design fundamentals and hands-on work in advanced process nodes\nDetailed design experience with at least one SerDes sub-circuit (receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializers, VCO, phase mixer, DLL, PLL, bandgap reference, ADC, DAC) and familiarity with several others\nProficiency with SPICE simulators and simulation methods, including corner analysis, Monte Carlo, and aging simulations\nWorking knowledge of Verilog-A for analog behavioral modeling, simulation control, and data capture\nExperience with schematic entry, physical layout, and design verification tools, hands-on layout experience with high-speed circuits is a plus\nFamiliarity with scripting languages such as TCL, Perl, Python, C, or MATLAB for automation and data analysis is desired\nWho You Are\nYou can look at a block spec and quickly sketch two or three circuit topologies, then articulate the tradeoffs between them in a design review without needing slides\nYou treat layout as part of the design, not an afterthought, and you know how to work with layout engineers to get matching, parasitics, and floorplanning right the first time\nYou are comfortable presenting simulation data to customers and peers, defending your design choices, and adjusting your approach when the data tells you to\nYou know the difference between a simulation that gives you confidence and one that just checks a box, and you design your verification strategy accordingly\nYou can move between deep circuit-level work and system-level discussions with digital designers, understanding how your block fits into the larger SerDes architecture\nYou document your work clearly, not because someone asked you to, but because you know the next person (or future you) will need to understand what you built and why\nThe Team You'll Be Part Of\nYou will join a growing analog and mixed-signal R&D team focused on high-speed SerDes IP development in the latest FinFET process nodes. The team works cross-functionally with digital designers, software engineers, and a dedicated CAD team that supports custom in-house tools alongside a full suite of industry-standard IC design tools. Your recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Hardware Engineer, Silicon Power and Productization", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-26", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Hardware-Engineer--Silicon-Power-and-Productization_JR2023289", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been redefining computer graphics, PC gaming, and accelerated computing for more than 25 years. Today, we are tapping into the unlimited potential of AI to define the next era of computing. As an NVIDIAN, you will address challenges spanning architecture, silicon, firmware, software, and production — and excellent judgment matters as much as technical depth!\nEvery major NVIDIA silicon product family—from the chips powering AI and datacentre systems to gaming, professional, embedded, and automotive platforms—passes through our productization work on its way to production. NVIDIA’s Silicon Co-Design Productization team works from pre-silicon strategy and feature development through bring-up, characterization, correlation, and optimization. Our charter spans power & performance modelling, bring up & tuning of low-power features, power & thermal controllers, and system-level optimization that ultimately shape how NVIDIA products are configured, binned, specified, and shipped.\n\nWhat you'll be doing\nDrive silicon power productization from pre-silicon planning through bring-up and production, including test strategy, feature readiness, characterization, and optimization.\n\nPartner with architecture and design teams to identify improvements, validate features, and help translate them into production-ready solutions.\n\nCorrelate measured silicon behaviour with pre-silicon expectations, investigate gaps, and drive complex issues to root cause.\n\nBuild power and performance models and characterization methodologies that decide silicon binning, product specifications, productization decisions, and customer guidance.\n\nUse AI/ML and data-driven methods to analyse characterization & telemetry data, identify anomalies & trends, and accelerate issue debug across silicon, board, power delivery, firmware, and software.\n\nWhat we need to see\nBS/MS in Electronics Engineering, Electrical Engineering, or a related field, or equivalent experience.\n\n2+ years of experience in silicon bring-up, characterization, validation, productization, or a related hardware field.\n\nUnderstanding of silicon power and performance, including process technology, voltage, frequency, workloads, and operating conditions.\n\nExperience with system-level hardware debugging and interactions across silicon, board hardware, firmware & software.\n\nData analysis and problem-solving skills—you can turn measurements into hypotheses and design experiments to test them.\n\nWays to stand out from the crowd\nExperience with Windows/Linux systems, low-power states, power controllers, silicon power, device physics, or power delivery.\n\nContributions that improved silicon bring-up, characterization coverage, pre/post-silicon correlation, debug efficiency, or productization methodology.\n\nExperience with power modelling, silicon binning, productization.\n\nExperience applying AI/ML to engineering workflows, such as debug assistants, characterization analytics, or automated anomaly and trend detection.\n\nEach new process node and architecture brings power challenges that simulation alone cannot answer. This team works where architecture, design, silicon, systems, firmware, and software meet—with the opportunity to influence both how new silicon is built and how it ultimately ships. If you want to get close to new silicon, use data and AI to solve problems across engineering boundaries, and help turn first silicon into products at scale, we'd like to hear from you.\n\nWith competitive salaries, generous benefits package and an outstanding culture, we are broadly recognized as one of the technology world’s most desirable employers. We are an equal-opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, colour, national origin, sex, gender, gender expression, sexual orientation, age, marital status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Trainee Specialist - Hardware Engineer", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-08-25T10:24:01+00:00", "url": "https://jobs.infineon.com/careers/job/563808971891929", "is_hardware": true, "platform": "eightfold", "jd_text": "We are seeking a\nhighly skilled and experienced Hardware Engineer to design and develop\nevaluation kits and reference designs for Infineon Microcontroller devices. The\nsuccessful candidate will be responsible for creating schematic designs using\nCadence, as well as bringing up and testing new Microcontroller Units (MCUs).\nThis is an excellent opportunity for a talented engineer to join our team and\ncontribute to the development of innovative technologies.\n\nYour role\nKey responsibilities in your new role\n\n· Design and develop\nevaluation kits and reference designs for new MCUs, including schematic design,\nPCB layout, and prototype testing\n · Design schematic using Cadence, ensuring\ncompliance with industry standards and company specifications\n · Bring up and test MCU boards, including\ndebugging and troubleshooting of hardware and software issues\n · Collaborate with cross-functional teams,\nincluding software, firmware, and system engineering, for integration of\nevaluation kits with overall system\n · Develop and maintain technical documentation,\nincluding user manuals, datasheets, and test reports\n · Participate in design reviews and provide\nfeedback to ensure high-quality design and reliability of evaluation kits\n · Stay up-to-date with industry trends and\nemerging technologies, and apply this knowledge to improve reference designs\nand development\n\nYour profile\nQualifications and skills to help you succeed \n\n· Bachelor's or\nMaster's degree in Electronics and communication Engineering, or a related\nfield\n\n· Minimum 1~3 years of experience in hardware\ndesign and development\n\n· Proficiency in Cadence schematic design tools,\nincluding OrCAD and Allegro\n\n· Strong knowledge of digital and analog circuit\ndesign principles.\n\n· Strong understanding of basic serial\ncommunication protocols, and extended communication protocols such as SMIF,\nSDIO, CAN, MIPI, etc.\n\n· Strong understanding on power supply and motor\ncontrol designs.\n\n· Experience with bring-up and testing,\nincluding debugging of hardware and software issues\n\n· Excellent problem-solving skills, with the\nability to analyze complex technical issues and develop creative solutions\n\n· Strong communication and collaboration skills,\nwith the ability to work effectively with cross-functional teams\n\n· Ability to work in a fast-paced environment,\nwith multiple projects and deadlines.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Director Engineering, Analog Design (Power ICs)", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-25T09:40:32.828000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000145468629-director-engineering-analog-design-power-ics-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking a Director, Engineering with deep expertise in mixed-signal IC development to support Renesas' India-focused growth initiatives. This role is technical, cross-functional, and product-defining. \nThe successful candidate will define optimum system architecture for application-specific ICs, spanning analog signal-chain products, high-power delivery, mixed-signal integration, and digital-controller-based architectures. The role will map product needs to existing Renesas IP across business units and identify where new development is required. \nYou will be expected to collaborate across business units, system engineering, analog packaging, back-end, design, test, and operations teams to execute IC development with an efficient cost structure. You will also identify critical skill-set requirements and build the right technical team from scratch. \n \nProduct & Architecture Leadership \nWork with product definition / IC architect team to optimize system architecture for application-specific ICs serving India market requirements across automotive, industrial, power, and mixed-signal applications. \n\nUnderstand customer use cases, system requirements, cost targets, and application constraints to optimize architecture \n\nCover a broad technical span, ranging from analog signal-chain products to high-power delivery with digital controllers. \n\nDrive architecture trade-offs across performance, integration level, BOM cost, manufacturability, qualification effort, and reuse of existing Renesas technology. \n\nCross-Business Unit IP Reuse & Collaboration \nMap target architectures to available IP across different business units within Renesas and identify gaps requiring new development. \n\nCollaborate with multiple business units, system engineering, analog packaging, back-end, design, test, and operations teams to execute the development plan. \n\nRepurpose existing resources and IP wherever practical, while being clear where reuse creates unacceptable product, schedule, or execution risk. \n\nCreate structured technical alignment across stakeholders who may have different priorities, schedules, and ownership models. \n\nDevelopment Execution \nLead development programs through concept definition, architecture, specification, planning, execution, verification, validation, qualification, and production handoff. \n\nBuild execution plans that include ownership, milestones, technical risks, resource needs, cost assumptions, and decision gates. \n\nEnsure development choices are grounded in realistic foundry, packaging, test, DFT, qualification, and manufacturing constraints. \n\nCollaborate with system engineering teams to define IC requirements and ensure the product solves real application-level problems. \n\nAutomotive Quality, DFT & Reliability Planning \nUnderstand automotive qualification requirements for integrated circuits during design planning and translate them into execution needs. \n\nPlan required DFT structures, test coverage, reliability flows, and production test implications early in the design phase. \n\nUnderstand system-level fault behavior, protection needs, and safety-related requirements where relevant to automotive and industrial applications. \n\nCreate a practical bridge between product ambition and qualification realities, including schedule, cost, and silicon iteration risk. \n\nTeam Building & Technical Leadership \nIdentify critical skill-set requirements and hire the right people for the development team. \n\nBuild and mentor a high-quality technical team, including architecture, design, verification, validation, and execution contributors. \n\nAssess technical depth during hiring and avoid over-reliance on surface-level experience claims. \n\nRepresent the program in senior leadership reviews with clear choices, trade-offs, risks, and asks. \n\n15+ years of experience in mixed-signal IC, analog IC, power IC, or related semiconductor product development. \n\nBachelor or Masters of Electronics Engineering related discipline from a reputed institution. \n\nExperience in leading IC development with multiple functional teams is a must for this role. \n\nGood understanding of history and future trends in semiconductor industry. \n\nAwareness of foundry capabilities for different CMOS, BCD and FET technologies will be an added advantage. \n\nUnderstanding of automotive qualification requirements for integrated circuits in the design phase and ability to plan execution with required DFT circuits. \n\nGood understanding of advanced semiconductor packaging technologies and their impact on cost, thermal performance, integration, and manufacturability. \n\nPrevious experience in building a team from scratch. \n\nComfort and ability to collaborate and be effective in an entrepreneurial (fast-paced and ambiguous) environment. \n\nExcellent interpersonal, communication and presentation skills and comfort in presenting to a wide range of audiences. Capable to communicate issues in a concise and effective way. \n\nDesire and drive to interact with, as well as ability to build and maintain excellent relationships with internal and external stakeholders. \n\nProduct ownership mentality with strong affinity to technical depth.\n\nSelf-driven, strongly motivated individual capable to take full ownership of their activities, and to involve other functions in the company or management when needed to bring them to a successful outcome. \n\nShould be motivated to handle unknowns of a beginner.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Sr Staff Engineer, STA ", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-25T05:30:35.024000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000145421999-sr-staff-engineer-sta-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking a seasoned Backend Design Expert specializing in Static Timing Analysis (STA) and Logic Synthesis. You will own the RTL-to-Gate conversion, constraint development, and final timing closure, ensuring our chips deliver maximum performance at the lowest possible power and area.  \nKey Responsibilities \nPhysical-Aware Synthesis and PPA optimization: Own and execute hierarchical synthesis flows to translate SystemVerilog RTL into optimized gate-level netlists. Execute physical-aware and floorplan-driven synthesis flows to minimize post-layout congestion and achieve PPA targets, identify bottlenecks and drive optimizations (e.g., critical path restructuring, datapath optimization). Conduct flat and hierarchical synthesis, ensuring seamless interface timing budgets. Manage formal verification (LEC) to ensure logical equivalence between RTL and netlist. UPF management for multiply power domains. \nTiming Closure & STA: Perform block-level and full-chip STA across multi-mode and multi-corner (MMMC) scenarios using industry-standard tools. Collaborate with PNR team, understand the clock tree and provide timely feedback to optimize the clock tree and achieve best QOR and perform STA signoff checks to closure.  \nConstraint Development: Architect, validate, and manage files, addressing both functional and DFT modes. Develop and manage comprehensive block-level and top-level constraints (SDC / UPF). \nLow-Power Implementation: Implement and verify UPF-based (Unified Power Format) low-power architectures and multi-voltage domains \nProgramming/Scripting: Strong scripting skills in Tcl, Python, or Perl to automate flows and improve design methodologies \n\nExperience of about 10-13 years in synthesis and STA closure. \nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. \nAbility to understand design specifications, can contribute to design planning, partitioning, and setup a feasible seed for convergence PD cycle. \nExtensive experience in STA closure on complex design with ability to understand the clocks structure from both functional and DFT side and provide solutions to complete design closure.  \nWorked on synthesis of high frequency designs and come up PPA solutions to meet the targets. \nGood understanding of EDA tools such as Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC. \nStrong understanding of static timing analysis, power analysis, and signal integrity analysis. \nExcellent problem-solving skills and attention to detail. \nExcellent scripting skills and development of utilities to reduce overall TAT. \nAbility to work effectively in a team environment and communicate clearly with cross-functional teams. \nExperience in mentoring and coaching junior engineers is a plus. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "WRD(RTL ) Design - Staff/Manager", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-25T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720694154", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nBDC WRD (Wi-Fi) is responsible for developing Qualcomm’s Wi-Fi chips. We are looking for a digital design engineer, with some signal processing background.\nAs a design engineer, you will be working with the lead on designing one of the IPs of the WiFi PHY for the upcoming WiFi standard and in the process contribute to the entire life cycle of a design from understanding spec, micro-architecture, RTL coding, RTL QA and making the releases. You will be participating along with the lead in discussions with the WiFi PHY systems team during the requirements phase. It is expected you to have the background and inclination to implement Signal processing module of WiFi in RTL and/or HLS.\nSkills & Experience\nMTech/BTech in Electronics & Communication Engineering with 8-15 years in design, micro-architecture & RTL coding.\n\nExperience with HLS will be a plus.\n\nProficient in Verilog, System-Verilog programming languages\n\nSolid experience with RTL QA flows like PLDRC, CDC, CLP (optional)\n\nGood to have the working experience either of Implementation or STA flows.\n\nKnowledge of signal processing concepts/algorithms and Wi-Fi standards (802.11a/b/g/n/ac/ax) is good to have.\n\nGood experience in any scripting languages (Perl, Tcl, etc..)\n\nStrong debugging and problem-solving skills.\n\nMinimum Qualifications:\nBachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\nOR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\nOR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\nResponsibilities\nDesign, Micro-architecture design, RTL coding and development and its validation for linting, CDC rules.\n\nWork with project lead in coming up with the IP micro architecture.\n\nWork with functional verification team on test-plan development and debug.\n\nDevelop timing constraints, if required, to synthesize the RTL.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n•    8+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates complex features and functionality into hardware designs in line with proposals or roadmaps for complex products.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the novel manufacturing of solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for complex Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making is significant in nature and affects work beyond immediate work group.\n•    Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. \n•    Has a moderate amount of influence over key organizational decisions.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SOC Design - Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-25T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720696961", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\n8 to 11 years of work experience in ASIC/SoC Design\n\nExperience in Logic design /micro-architecture / RTL coding is a must.\n\nMust have hands on experience with SoC design and integration for complex SoCs.\n\nExperience in Verilog/System-Verilog is a must.\n\nknowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC.\n\nUnderstanding of Memory controller designs and microprocessors is an added advantage\n\nWork closely with the SoC verification and validation teams for pre/post Silicon debug\n\nHands on experience in Low power SoC design is required\n\nHands on experience in Multi Clock designs, Asynchronous interface is a must.\n\nExperience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.\n\nUnderstanding of constraint development and timing closure is a plus.\n\nExperience in Synthesis / Understanding of timing concepts is a plus.\n\nExperience creating padring and working with the chip level floorplan team is an added advantage.\n\nExcellent oral and written communications skills\n\nProactive, creative, curious, motivated to learn and contribute with good collaboration skills. \n\nRequired: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Principal Engineer- DEG Layout", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-08-25T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/41970490", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nRole and Responsibilities\nResponsible for layout design and development of critical analog, mixed-signal, custom digital block, standard cells  and full chip level.\nPerform layout verification like LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem checks,  quality check and documentation.\nResponsible for development of digital block layouts using auto placement and route tools\nResponsible for basic understanding of skill coding and automation\nResponsible for on-time delivery of block-level layouts with acceptable quality.\nDemonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/breakthroughs in multiple project environment.\nGuide team members in their execution of Sub block-level layouts & review their work\nEffectively communicating with Global engineering teams to assure the success of layout project.\nResponsible for the reducing the layout effort by using AI\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "GPU Function Verification Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-25T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718158979", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nAdditional Job Description\n\nQualcomm is a company of inventors that unlocked 5G, ushering in an age of rapid acceleration in connectivity and new possibilities. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform its potential into world-changing technologies and products.\nIn the role of GPU Functional Verification Engineer, your project responsibilities will include the following,\nDevelop deep understanding of 3-D Graphics hardware pipeline, feature sets, data paths, block functionalities & interfaces\n\nStrategize, brainstorm, and propose a DV environment, develop test bench, own test plan, debug all RTL artefacts, and achieve all signoff matrices\n\nEngage with EDA vendors, explore new and innovative DV methodologies to push the limits of sign off quality\n\nCollaborate with worldwide architecture, design, and systems teams to achieve all project goals\n\nCurrently, we are looking for candidates who can match one or more of the profiles listed below,\nStrong knowledge of UVM based System Verilog TB Knowledge of GPU pipeline design is a plus, not mandatory Proficiency with formal tools – working knowledge of Property based FV is a plus, not mandatory Strong communication skills (both written and verbal) Most importantly, ability to learn, improve and deliver\nExperience\nMinimum 3 years of Design verification experience\n\nSenior positions will be offered to candidates with suitable years of experience and proven expertise matching the profiles listed above\n\nEducation Requirements\nBE/ME/M.Sc. in Electrical, Electronics, VLSI, Microelectronics, or equivalent courses from reputed universities\n\nSelected candidates will be part of the GPU HW team which is passionate about developing and delivering the best GPU Cores for all Qualcomm Snapdragon SOC products. Qualcomm GPU is an industry-leading solution which is driving the benchmarks in mobile computing industry and the future of mobile AR/VR.\nThe pre-Si verification team in Bangalore is currently heavily involved in the following\nUVM/SV based constrained random test bench for functional verification\n\nSubsystem level TB for complete GPU workload analysis and compliance\n\nEmulation platforms to analyze performance and pipeline bottlenecks\n\nFormal tools – both for reduced time to bug & property based FV sign-off\n\nPower Aware & Gate level simulations to deliver a high-quality GPU implementation\n\nPerl/Python scripts for automation in managing regressions, optimize run time, manage database and bug\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "WRD (RTL) Design -Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-25T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720694036", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nWireless HW Design Engineer (ASIC) – Lead Engineer, Senior\nBDC WRD (Wi-Fi) is responsible for developing Qualcomm’s Wi-Fi chips. We are looking for a digital design engineer, with some signal processing background.\nAs a design engineer, you will be working with the lead on designing one of the IPs of the WiFi PHY for the upcoming WiFi standard and in the process contribute to the entire life cycle of a design from understanding spec, micro-architecture, RTL coding, RTL QA and making the releases. You will be participating along with the lead in discussions with the WiFi PHY systems team during the requirements phase. It is expected you to have the background and inclination to implement Signal processing module of WiFi in RTL and/or HLS.\nSkills & Experience\nMTech/BTech in Electronics & Communication Engineering with 5-7 years in design, micro-architecture & RTL coding.\n\nExperience with HLS will be a plus.\n\nProficient in Verilog, System-Verilog programming languages\n\nSolid experience with RTL QA flows like PLDRC, CDC, CLP (optional)\n\nGood to have the working experience either of Implementation or STA flows.\n\nKnowledge of signal processing concepts/algorithms and Wi-Fi standards (802.11a/b/g/n/ac/ax) is good to have.\n\nGood experience in any scripting languages (Perl, Tcl, etc..)\n\nStrong debugging and problem-solving skills.\n\nMinimum Qualifications:\nBachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\nOR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\nOR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nResponsibilities\nDesign, Micro-architecture design, RTL coding and development and its validation for linting, CDC rules.\n\nWork with project lead in coming up with the IP micro architecture.\n\nWork with functional verification team on test-plan development and debug.\n\nDevelop timing constraints, if required, to synthesize the RTL.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Engineer - DFT", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-25T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718081467", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    8+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates complex features and functionality into hardware designs in line with proposals or roadmaps for complex products.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the novel manufacturing of solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for complex Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making is significant in nature and affects work beyond immediate work group.\n•    Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. \n•    Has a moderate amount of influence over key organizational decisions.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "HSIO Characterization Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-25T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720710355", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJD: HSIO - Electrical Validation and Characterization Engineer\nThe HSIO Post Silicon Engineering group has an opening for a HSIO Characterization Engineer.\nAs part of the HSIO Post Silicon Engineering group, you will be responsible for bench characterization and electrical validation of leading-edge High-Speed IO interfaces and LPDDR subsystems across mobile, automotive, compute, and datacenter platforms. You will work on High-Speed Interfaces such as PCIe, USB2/3/4, DisplayPort, HDMI, MIPI CSI/DSI, MIPI D-PHY/C-PHY, UFS, Ethernet, and PLLs.\nYou will:\nEvaluate parametric and electrical performance of High-Speed IO IPs\n\nPerform post-silicon validation, characterization, and compliance testing of HSIO interfaces\n\nAnalyze signal quality including eye diagrams, jitter, BER, receiver tolerance, equalization, and link performance\n\nPerform failure analysis and root-cause design, silicon, board, and system-level issues\nBring up complex validation platforms, boards, and test environments\nDevelop validation plans, test methodologies, automation frameworks, and test scripts\nCollaborate closely with PHY design, system engineering, software, hardware, and customer engineering teams across the globe in a time-critical environment\n\nQualifications\nM.Tech, B.Tech, or equivalent in Electronics or Electrical Engineering\n0-2 years of related work experience\nSkills & Knowledge\nFamiliarity with post-silicon validation and characterization of DDR and High-Speed IO interfaces\nKnowledge of HSIO standards such as PCIe, USB, UFS, MIPI, Ethernet, DisplayPort, and HDMI at PHY and protocol levels\n\nUnderstanding of electrical compliance specifications including eye diagram analysis, jitter measurements, BER testing, receiver jitter tolerance, link equalization, differential signaling, signal integrity, power integrity, transmission line effects, and de-embedding techniques\nStrong electrical engineering fundamentals and understanding of analog/digital ICs, semiconductor devices, and VLSI technologies\nHands-on experience with bench instruments such as oscilloscopes, BERT/J-BERT, protocol analyzers, vector network analyzers, spectrum analyzers, signal generators, timing sources, and logic analyzers\nExposure to board bring-up, debug, and test setup development\nProgramming and automation skills using Python, C/C++, C#, Shell scripting, LabVIEW, or equivalent\nExperience developing test automation and data analysis frameworks is a plus\nExposure to FPGA platforms and development tools such as Xilinx or Intel/Altera is an added advantage\nSoft Skills\nStrong interpersonal, analytical, problem-solving, and debugging skills\nAbility to work effectively in a fast-paced and highly collaborative environment\nSelf-motivated with strong ownership and execution skills\nExcellent verbal and written communication skills\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Technical Staff Engineer - Design", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-08-25", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Senior-Technical-Staff-Engineer---Design_R152-26", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nRole Overview\nThe candidate will join Microchip’s rapidly growing Data Center Solutions (DCS) business unit, delivering high-performance silicon solutions used by leading server and storage OEMs and hyperscale data centers. DCS products enable workloads ranging from cloud and big data storage to AI/ML acceleration, shaping the next generation of data center infrastructure.\nThe DCS portfolio includes SAS, PCIe, NVMe, and CXL infrastructure products, Flash Controllers, High-Performance Switches, and advanced memory infrastructure solutions. This role provides a unique opportunity to drive architecture, design excellence, and methodology innovation in complex data center–class ASICs.\n\nKey Responsibilities\nLead architecture and micro-architecture definition for complex IPs, subsystems, or full-chip designs.\n\nDrive end-to-end RTL design execution, from concept through synthesis, sign-off, and silicon bring-up support.\n\nServe as a technical authority for digital design, ensuring high standards in quality, performance, power, and area (PPA).\n\nResolve complex, cross-domain design and EDA tool challenges impacting schedule or silicon quality.\n\nCollaborate closely with verification, physical design, DFT, system, and product teams to ensure robust and predictable delivery.\n\nGuide low-power, high-performance design strategies suitable for data center workloads.\n\nInfluence protocol and platform roadmap decisions, particularly in PCIe, CXL, NVMe, SAS, and related interconnects.\n\nMentor and technically guide Senior and Staff engineers, providing architectural reviews and design direction.\n\nRepresent the design organization in technical reviews with senior leadership and cross-functional stakeholders\n\nIdentify opportunities to apply data driven approaches to improve design quality, efficiency and time-to-market\n\nDefine and enforce design methodologies, sign-off criteria, and best practices across projects.\n\nChampion AI/ML-assisted automation and intelligent workflows that scale across teams and projects.\n\nRequirements/Qualifications:\n\nBachelor degree in Electronics or Electrical Engineering minimum\n15+ years of experience in ASIC or SoC digital design.\n\nBachelor degree in Electronics or Electrical Engineering minimum\n\nStrong expertise in SystemVerilog RTL design and micro-architecture development.\n\nProven success delivering multiple complex tape-outs in high-performance or data center–class silicon.\n\nDeep hands-on experience with Lint, CDC, formal verification, logic synthesis, and static timing analysis.\n\nStrong understanding of physical design interactions, including timing, power, and congestion considerations.\n\nSolid experience with low-power design methodologies and flows.\n\nMandatory knowledge of DFT, including scan, testability considerations, and DFT sign-off interactions.\n\nProficiency in scripting languages such as Tcl, Perl, and/or Awk.\n\nHands-on experience with high-speed protocols such as PCIe, CXL, NVMe, SAS/SATA, or similar serial interfaces.\n\nHands-on experience with Cadence-based ASIC design environments is an assset\n\n \n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Senior Engineer, Research Science Engineering", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-08-25", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Senior-Engineer--Research-Science-Engineering_R264662-1", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nWe are seeking a highly motivated Senior Engineer to develop, calibrate, and optimize compact models for bulk CMOS, BJT, and LDMOS devices used in RF, analog, automotive, and high-voltage applications. The successful candidate will combine expertise in semiconductor device physics, compact modeling, and AI/ML techniques to develop next-generation modeling methodologies and automation workflows. This position is part of Analog Devices’ Engineering Enablement organization based in Bangalore, India.\nThe role demands strong expertise in semiconductor device physics, circuit simulation, and industry‑standard compact models such as BSIM4, BSIM-BULK, PSP, and Mextram. The engineer will also be responsible for building and applying machine‑learning‑based modeling methodologies. This role combines device characterization, compact model development, and machine-learning methodologies to address challenging semiconductor modeling problems and improve modeling productivity.\nOur global device‑modeling team consists of approximately 20 engineers located across various ADI sites. We are a diverse group of talented professionals, serving as the critical link between the process development teams and circuit designers. The team offers excellent opportunities for technical growth, innovation, and collaboration across global ADI organizations.\nResponsibilities include, but are not limited to:\nDevelop, enhance, and maintain compact models for CMOS, BJT, and LDMOS devices.\nCreate semiconductor device compact models for SPICE simulators.\nValidate and correlate compact models against measured device data.\nDebug and resolve convergence challenges encountered during circuit simulations.\nDevelop deep‑learning–based methods for parameter extraction and optimization.\nApply machine learning workflows to accelerate the parameter‑extraction process.\nBuild scripting tools to automate extraction tasks and generate reports.\nProduce comprehensive reports summarizing project results and findings.\nMinimum Qualifications\nPh.D. in Semiconductor Device Physics, Characterization, Modeling, or a related field.\nSkilled in optimization algorithms, data correlation, and automated extraction processes.\nStrong analytical skills, execution mindset, and sense of urgency\nAbility to collaborate across process, modeling, and PDK teams\nPreferred Qualifications\nExperience with semiconductor device characterization and measurement techniques.\nExperience with Python and Verilog-A programming\nExperience developing deep-learning, neural-network, and scientific machine-learning solutions using modern frameworks such as PyTorch, TensorFlow, or JAX.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Physical Design Engineer", "company": "Tesla", "location": "Bengaluru, India ; India", "date_posted": "2026-08-25", "url": "https://hire-r1.mokahr.com/social-recruitment/tesla/100004142?#/job/0f939843-bc9a-4b86-b129-8cf7565e264a", "is_hardware": true, "platform": "mokahr", "jd_text": "What to Expect\nThe Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life.\n\nTesla's AI Hardware Team is looking for experienced, highly skilled VLSI engineers who enjoy working across the logic, circuit, methodology, and physical design levels. Our physical design team is growing to tackle a wider range of projects, building on our in-house SOC design expertise. This position entails the design, construction and integration of SOCs, IP, circuits, tool flows, and methodologies into systems using advanced technologies - from definition through characterization.\n\nWhat You’ll Do\nWork on complex design blocks and SOCs from early design stage to tape out\nFloorplan and partition designs to meet area, timing, and power requirements\nConstruct high-speed blocks, from synthesis, place, and route, out through timing, physical, and electrical closure to meet performance, robustness, reliability, and power targets\nRead RTL, understand block micro-architecture, perform RTL modifications and prove logical equivalence as needed\n\nWhat You’ll Bring\nEngineering degree in a relevant field, or equivalent work experience \n2+ years of industry work experience in VLSI/IC design \nKnowledge and experience with logic design and synthesis tools and techniques\nProficient in place and route tools and approaches \nProficient in timing and electrical analysis in advanced nodes, including high-frequency design closure, IR drop, power, and reliability \nSkilled with CAD tools and scripting languages (Perl or Python) \nUnderstand cell and transistor level digital circuit design, memory and clock structures, and design methodologies \nGood understanding of RTL, DFT, and microarchitecture \nGood communication skills and a demonstrated team player and flexible and able to work independently in a fast-paced environment\nExperience in any of these areas is a plus: SOC level physical integration and validation, post-silicon characterization", "jd_status": "stored"}, {"title": "Staff Engineer - FuSA", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-25", "url": "https://careers.synopsys.com/job/bengaluru/staff-engineer-fusa/44408/99719320192", "is_hardware": true, "platform": "talentbrew", "jd_text": "Staff FuSa EngineerWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nYou have spent years in the automotive safety world and you know that functional safety is not a checkbox exercise. It is the discipline that keeps systems from failing in ways that matter. You understand that ISO 26262 compliance starts long before the audit and that the difference between a solid safety case and a fragile one is usually in the rigor of the work three months earlier.\nYou are comfortable reading through a Technical Safety Concept, spotting the gap in an FMEDA, or walking a design team through why their architecture creates a single point of failure they have not yet seen. You do not treat standards as obstacles. You treat them as frameworks that make better products possible, and you know how to translate safety requirements into engineering decisions that actually stick.\nWorking across global teams does not intimidate you. Neither does sitting with a customer who has hard questions about ASIL D compliance and expects answers that hold up under scrutiny. You bring structure to ambiguity, you build tools when the manual process does not scale, and you care about getting it right because you know what is at stake when safety critical systems go into production.\nAt Synopsys, you will work on automotive IP that powers the next generation of self-driving cars, ADAS systems, and smart vehicles. The standards are real, the customers are demanding, and the work you do will directly affect how safe those systems are.\n\nWhat You'll Be Doing\nOwn functional safety compliance for automotive DesignWare IP products, ensuring conformance to ISO 26262 across the full development lifecycle\nDevelop and review ISO 26262 work products including Technical Safety Concepts, FMEDA, FTA, DFMEA, DFA, Safety Plans, and Safety Cases for digital IP at ASIL levels up to ASIL D\nCollaborate with global product development teams to integrate functional safety requirements into IP design, verification, and release processes\nEngage directly with automotive customers to address functional safety, quality, and reliability requirements, providing technical guidance and compliance documentation\nBuild automation scripts and tools to streamline safety analyses, improve consistency, and scale functional safety workflows across multiple IP projects\nLead and participate in functional safety reviews, audits, and assessments, delivering clear reports and actionable recommendations to internal and external stakeholders\nMaintain, refine, and enhance functional safety methods, templates, and processes to keep pace with evolving automotive standards and customer expectations\nThe Impact You Will Have\nEnable Synopsys automotive IP to meet the safety and reliability standards that OEMs and Tier 1s depend on for next-generation vehicle platforms\nReduce time to compliance for new IP releases by building reusable safety artifacts, automation, and repeatable workflows that scale across product lines\nStrengthen customer confidence in Synopsys IP by delivering rigorous, audit-ready safety documentation and responsive technical support during their safety assessments\nInfluence IP architecture and design decisions early, catching safety risks before they become costly redesigns or certification blockers\nAdvance the maturity of functional safety practices across Synopsys IP teams, raising the bar for how safety is integrated into silicon development\nSupport the deployment of safer autonomous and ADAS systems by ensuring the IP inside them has been developed to the highest functional safety standards\nBuild tools and methods that make safety analysis faster, more accurate, and less dependent on manual effort, freeing engineers to focus on higher-value work\nWhat You'll Need\nBachelor's degree in Electrical Engineering with 8+ years of relevant experience, or Master's degree with 7+ years\nFormal training in ISO 26262, with demonstrated experience applying it to hardware development in safety critical applications\nHands-on experience qualifying systems to ISO 26262 ASIL levels, including ASIL D, with a solid understanding of hardware and software functional safety lifecycles\nProficiency in creating and reviewing ISO 26262 work products such as FMEDA, FTA, DFMEA, Technical Safety Concepts, and Safety Cases\nUnderstanding of semiconductor development flows and experience with digital design at the IP or SoC level\nExperience working on ISO 26262 Part 5 (hardware level) is a strong plus\nFamiliarity with hardware description languages (Verilog, VHDL, or SystemVerilog) is an advantage\nWho You Are\nYou can walk into a design review, spot a safety gap in the architecture, and explain the risk in terms the team understands without derailing the conversation\nYou are comfortable building scripts in Python, Perl, or similar languages to automate repetitive safety analysis tasks and improve workflow efficiency\nYou know how to work with customers who have deep expertise in automotive safety and you hold your own in technical discussions about failure modes, diagnostic coverage, and safety mechanisms\nYou bring structure to ambiguous projects, you create plans that keep cross-functional teams aligned, and you follow through without needing constant oversight\nYou understand that functional safety is a team sport, and you know how to influence engineers, product managers, and customers without formal authority\nYou stay current with automotive reliability standards like AEC Q100 and quality frameworks like ISO 9001 or IATF 16949, and you see how they connect to functional safety work\n\nThe Team You'll Be Part Of\nYou will join the Automotive Functional Safety team within the Silicon IP business unit, working closely with DesignWare IP development teams across digital interfaces, processors, memory, and analog IP. The team operates globally, collaborating with engineers in the US, Europe, and Asia, and engages directly with automotive customers including OEMs and Tier 1 suppliers. Your work will span multiple IP product lines, and you will contribute to building the safety infrastructure that enables Synopsys IP to meet the rigorous demands of the automotive market.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Staff Engineer- PDN", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-25", "url": "https://careers.arm.com/job/bengaluru/staff-engineer-pdn/33099/99721915520", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview:\nAs a Staff Engineer in Arm's Solutions Engineering group we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies.\nResponsibilities:\nYour responsibilities will involve developing challenging electrical signoff methodologies. These methodologies will balance accuracy and yield on silicon.\nThe following are the immediate challenges we will be working on as a team:\nWe will develop robust flows & Methodologies to support PDN Sign-Off Methodologies on the latest nodes and applying the latest SoC 2.5D and 3D technologies.\nWork on some of the Sign-Off methodologies like Static, Dynamic Power Distribution analysis, Electro-migration, ESD Analysis etc.\nDevelop and deploy new methodologies to improve implementation efficiency and results.\nSupport and develop detailed implementation analysis and data-mining methodologies.\nConverting R&D concepts into real implementation solutions.\nEnable our partners to achieve the best possible quality of results.\nRequired Skills and Experience :\nBachelors or Master’s degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields.\n7+ years of proven experience in ASIC Implementation, EM IR, PDN, Physical design and STA on advanced process nodes\nPossess a high level of dedicated, initiative and problem-solving skills.\nExperience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams\nPrevious experience in and knowledge of the entire IC design flow, from RTL through to GDS2.\nExperience working closely in top and block level Design Implementation and Sign-off flows.\nProven programming and scripting skills eg. Tcl, Perl, Python, Make\n“Nice To Have” Skills and Experience :\nKnowledge around Arm based SoCs!\nExperience with a wide range of programming, scripting & data presentation languages Eg. Tcl, sh, csh, make, R, C, C++, Java, JS, HTML, Perl, Python, Ruby.\nExperience with low power design techniques (power gating, voltage/frequency scaling)\n \n \n \n#LI-BB1\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Director of Software Engineering, SoC SW Productization", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-25", "url": "https://careers.arm.com/job/bengaluru/director-of-software-engineering-soc-sw-productization/33099/99721914512", "is_hardware": true, "platform": "talentbrew", "jd_text": "Director of Software Engineering, SoC SW Productization\n \nArm is redefining what is possible in cloud and data center computing. Our Neoverse platforms are helping power a new era of infrastructure – combining advanced silicon with the system software required to turn ambitious technology into production-ready solutions.\nAre you excited by the prospect of building and leading the engineering organization responsible for validating and delivering some of the industry’s most complex compute systems?\nWe are looking for an Engineering Director in the infrastructure solutions software team in our CE-SW group who will shape how our future infrastructure platforms are validated, from pre-silicon development through silicon bring-up and deployment. You will lead all aspects of an engineering group of 50+ professionals working remotely across the intersection of silicon, firmware, and system software.\nThis is an opportunity to make an impact at scale!\nResponsibilities:\nYou will:\nOwn and drive the validation and quality strategy for our Infrastructure System Solutions, providing technical direction across SoC, firmware and end-to-end system validation, from pre-silicon development to production readiness.\nBuild and lead a high-performing, globally distributed Software Engineering organization, driving scalable automation, CI, quality metrics and engineering practices while developing strong engineering leadership at all levels.\nPartner with senior leaders across hardware, software, architecture and product teams to align validation with product goals, manage quality risks and influence key engineering and release decisions.\nRequired Skills and Experience :\nExtensive experience delivering complex system software and leading large, globally distributed engineering organizations through managers and technical leaders.\nStrong technical background in System-on-Chip (SoC), firmware, platform software and system-level validation across pre-silicon and silicon environments.\nDeep expertise in validation strategy, test automation, continuous integration, regression and release readiness for complex systems.\nExcellent technical judgement, leadership and communication skills, with a proven ability to influence senior collaborators and drive decisions across engineering organizations.\n“Nice To Have” Skills and Experience :\nKnowledge of server-class SoCs, including RAS, power management, PCI Express (PCIe), Compute Express Link (CXL), memory and virtualization.\nFamiliarity with the Linux kernel, Trusted Firmware-A (TF-A), UEFI EDK II, OpenBMC or Kernel-based Virtual Machine (KVM).\nExperience scaling automated system validation, hardware test environments, server farms or continuous integration infrastructure.\nIn Return:\nIf you want to shape how the next generation of Arm infrastructure technology reaches production, you will have the opportunity to lead a critical engineering function, influence technology and product decisions, and develop a distributed team accountable for the quality and readiness of some of our most sophisticated infrastructure platforms.\nJoin us and help define what world-class system validation looks like at Arm!\nWe will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-25", "url": "https://careers.arm.com/job/bengaluru/senior-engineer/33099/99721914048", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview:\nAs a part of  Arm's Solutions Engineering group we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies.\nResponsibilities:\nSynthesis, DFT , Floorplan , Place and Route  , CTS and  Optimization of CPU cores, system interconnect and other ARM Designs.\nRTL-GDS closure for Hard Macro\nAnalyze design timing, area and power to help improve the quality of ARM Design.\nAnalyze DRC/LVS/PERC/ERC using Calibre and perform Layout edit for Physical Verification closure.\nAnalyze Timing using primetime and perform Timing  ECO for design closure\nWork with implementation and physical IP RTL design teams to drive analysis and optimization of our IP.\nConverting R&D concepts into real implementation solutions.\nEnable our partners to achieve the best possible quality of results\nRequired Skills and Experience :\nBachelors or Master’s degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields.\n3+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification\nStrong Communication and Problem Solving Skills.\nExperience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams\nExperience working closely in top and block level Synthesis, DFT, Floor planning, Place and Route, CTS, logical and physical optimization, timing closure and power analysis flows.\nProven programming and scripting skills eg. Tcl, Perl, Python, Make.\n“Nice To Have” Skills and Experience :\nKnowledge around Arm based SoCs!\nExperience with a wide range of programming, scripting & data presentation languages Eg. Tcl, sh, csh, make, R, C, C++, Java, JS, HTML, Perl, Python, Ruby.\nExperience with low power design techniques (power gating, voltage/frequency scaling)\nExperience with Verilog RTL design.\nExperience with ATPG tools/and or production testing.\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Technical Staff Engineer  - SOC Verification", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-08-25", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Sr-Manager---SOC-Verification_R3269-26-1", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nAre you passionate about solving complex verification challenges and driving first-pass silicon success for industry-leading microcontrollers?\n\nAs a Senior Technical Staff Engineer in our dsPIC Microcontroller Business Unit, you will be a key technical leader responsible for ensuring the functional integrity of next-generation 16-bit and 32-bit MCU products. You will architect and execute advanced verification strategies for complex SoCs featuring ARM-based and proprietary processor architectures, while influencing verification methodology, automation, and technical direction across multiple programs.\nThis role is ideal for a highly experienced verification engineer who thrives on deep technical problem solving, enjoys mentoring others, and wants to make a broad impact on product quality and verification excellence.\n\nWhat You Will Do\nContribute as a senior technical member of a global verification team developing advanced microcontroller products.\nOwn and execute comprehensive SoC-level verification plans from architectural specification through tape-out.\nServe as a technical leader across projects by driving verification strategy, influencing architectural decisions, and establishing best practices that enable verification excellence and first-pass silicon success.\nDevelop verification environments, reusable testbench components, and stimulus using SystemVerilog and UVM methodologies.\nVerify complex digital IP and subsystem integrations at block, subsystem, and full-chip levels.\nDrive RTL, gate-level, and full-chip verification for next-generation microcontroller products.\nDevelop functional safety verification strategies, fault-injection tests, coverage models, and safety metrics.\nDebug challenging full-chip issues spanning architecture, RTL design, firmware interaction, and verification infrastructure.\nDefine and track coverage goals including functional, code, assertion, and safety coverage to ensure verification completeness.\nPartner closely with architecture, design, firmware, and validation teams to resolve complex technical issues and improve product quality.\nChampion verification best practices, reusable methodologies, and automation frameworks that improve productivity, quality, and predictability across projects.\nMentor junior engineers and provide technical leadership through design reviews, methodology guidance, and hands-on problem solving.\nDrive adoption of advanced verification techniques including formal verification, assertion-based verification, automation, and AI-assisted engineering workflows.\n\nWhy Join Us\nYou will work on cutting-edge microcontroller technologies, collaborate with world-class engineering teams, and influence verification strategy for future product generations. This role offers the technical depth of a senior individual contributor position while providing significant impact on architecture, methodology, automation, and engineering excellence across the organization.\n\nHiring Manager Perspective\nThe strongest version of this posting positions the candidate as:\nTechnical owner, not a people manager.\nVerification methodology leader, not just a testbench developer.\nAutomation and AI adopter, not merely a user of verification tools.\nMentor and technical influencer, without requiring direct management responsibility.\nDriver of first-pass silicon success, functional safety, and full-chip verification closure.\n\nThat combination is designed to appeal to high-caliber Staff and Principal verification engineers.\n\nRequirements/Qualifications:\n\nRequired Qualifications\nBS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related discipline.\n12+ years of experience in digital design verification with a proven track record of successful SoC or MCU product tape-outs.\nStrong expertise in SystemVerilog, UVM, and coverage-driven verification methodologies.\nHands-on experience verifying complex SoCs containing ARM or comparable embedded processor architectures.\nDeep understanding of AMBA protocols including AXI, AHB, and APB.\nExperience developing verification plans, testbenches, checkers, assertions, and coverage models.\nStrong debugging skills across RTL, simulations, regressions, and full-chip integration environments.\nAbility to influence technical decisions and collaborate effectively across geographically distributed engineering teams.\nExcellent communication and technical leadership skills.\n\nPreferred Qualifications\nExperience with Formal Verification methodologies and tools such as JasperGold or VC Formal.\nExpertise in gate-level simulations, low-power, and power-aware verification methodologies.\nFamiliarity with functional safety standards and safety verification approaches, including ISO 26262.\nExperience with fault-injection simulations and functional safety coverage analysis.\nStrong expertise in verification automation, scripting, and productivity tools (Python, Perl, or similar), with experience leveraging AI-assisted technologies to improve verification quality, accelerate debug, optimize regression efficiency, and drive faster coverage closure.\nKnowledge of post-silicon validation and alignment between pre-silicon verification and silicon bring-up activities.\nExposure to mixed-signal or AMS verification environments.\nPrior experience providing technical leadership, mentoring engineers, or leading methodology and automation initiatives within a verification organization.\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Lab Manager - Hardware Engineering", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-25", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Lab-Manager---Hardware-Engineering_JR2018735", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. Today, we are tapping into the unlimited potential of AI to define the next era of computing — an era in which our GPUs act as the brains of computers, robots, and self-driving cars that understand the world. Doing what has never been done before takes vision, innovation, and the world’s best talent.\n\nNVIDIA’s Silicon Co-Design Group is the team that gets every GPU, SoC, and CPU silicon program from first power-on to high-volume production. We are hiring a Lab Manager to own hardware engineering lab operations across our Bangalore, Hyderabad and Pune Design Center.Your labs are where silicon meets reality — where every bring-up, validation experiment, and rework cycle happens, and where a day lost hits the program directly. You own the section: multiple labs, varied product classes, and a team of rework, reflow, and logistics technicians delivering daily for engineering. Your decisions show up in lab uptime, bring-up readiness, capital plan accuracy, and audit outcomes on safety and physical IP. You are the leader the program turns to when a new product class needs a lab spun up fast, when an EHS or security gap surfaces, or when capacity for the next roadmap year hasn’t been planned.\n\nWhat you will be doing:\nOwn and Run multiple labs across varied product classes — silicon bring-up, validation, and engineering experiments. Lead rework, reflow, and logistics technicians (including outsourced workers); develop them to self-manage opex procurement, planning, and day-to-day execution.\n\nPlan ahead of the roadmap. Forecast long-term lab needs — space, power, cooling, thermal, reflow capability, equipment — and own the capital and expense plan that supports it. Drive growth, reconfiguration, and ramp-down as programs evolve.\n\nEngage Bring-up early. Partner with Bring-up managers to scope incoming silicon programs — requirements, procurement, budget, staffing — so infrastructure and personnel land ahead of priority milestones, on cost.\n\nHold the safety and security bar. Drive lab EHS compliance and security control. Be the recognized safety champion and physical IP asset expert — set guidelines, run reviews, operate with audit-ready discipline.\n\nRun equipment cradle-to-grave. Own capital and expense planning, purchasing, warranty, calibration, and inventory — shipment, import, EC components, bonding — with a clear, auditable process across all labs.\n\nStandardize across sites. Coordinate with global lab managers to learn and propagate best practices and standardize lab operations where it adds leverage.\n\nRole may involve travel across our Bangalore, Hyderabad, and Pune Design Centers\n\nWhat we need to see:\nBachelor’s degree in Electrical Engineering or a related field (or equivalent experience), with overall 8+ years of experience in silicon/HW lab setup, management, and maintenance.\n\nAt least 3+ years managing a technical lab environment and leading teams across sites, with a track record of owning a multi-lab section — including capital and expense equipment planning, vendor and outsourced-worker management, and inventory/logistics tracking.\n\nHands-on experience operating lab equipment (oscilloscope, DAQ, and other common equipment) and consumer hardware assembly/teardown, solder/rework — with familiarity in HW bring-ups, computer systems, and debugging.\n\nExperience working with multi-functional teams — SW, validation, ASIC, and other hardware/software functions — with excellent communication abilities across sites.\n\nWays to stand out from the crowd:\nExperience with CPU/SOC chip bring-up and validation process.\n\nMulti-site or global lab coordination experience — shared standards, vendor frameworks, or capacity planning across regions.\n\nComfortable using AI productivity tools (Claude, Copilot, or equivalent) to compress reporting, analysis, and operational workflows — with judgment about where AI helps and where it doesn’t.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior Formal Verification Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-25", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Formal-Verification-Engineer_JR2023406-1", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nAs a Formal Verification Engineer at NVIDIA, you will be responsible for formally verifying complex designs. NVIDIA has developed a strong functional formal verification methodology that not only enables hardware design and verification engineers to use lightweight FV tools and techniques successfully but also allows FV engineers to use advanced property proving techniques on complex and/or critical RTL logic. The job involves very close interaction with the design team, architecture team, with other validation teams, and with NVIDIA's internal FV R&D group that develops functional verification tools using formal verification technology.\n\nWhat you'll be doing:\nYou will help decide on the best applications of formal verification techniques to various parts of the design.\n\nReview functional and micro-architectural specifications, define the scope for formal verification, and create high-quality formal verification testplans to sign-off on the corresponding design implementation.\n\nBuild formal verification testbenches, code assertions and constraints, and apply abstraction techniques to converge the targeted properties or to achieve reasonable proof-depth.\n\nApply formal coverage techniques for analyzing over-constraints and for measuring functional coverage.\n\nDesign and develop functional verification flows that involve both vendor and internally developed formal tools.\n\nWhat we need to see:\nB.Tech./ M.Tech. with 5+ years of relevant experience.\n\nGood understanding of hardware micro-architecture and design.\n\nConversant with formal verification technologies, including complexity reduction techniques.\n\nFormal property verification experience on multiple complex units.\n\nProficiency in creating high quality testplans, building formal testbenches, and root-causing counter-examples.\n\nWays to stand out from the crowd:\nGood debugging and problem solving skills\n\nScripting knowledge (Python/Perl/shell)\n\nGood interpersonal and communication skills and dream to work as a great team member\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.\n\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Principal Digital Engineer (DFT Design)", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-24T14:48:08.623000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000145302199-principal-digital-engineer-dft-design-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "This is an opportunity to join a top-notch Power Management IC Team with Renesas leading Automotive Business Unit. You will be part of a very skilled group of engineers who are helping build world-class automotive PMIC products that will power tomorrow’s automobiles. You will design complex chips that includes various analog and digital control circuitry and work very closely with all aspects of chip design – from writing specifications to developing tests for mass production. You will be a key contributor to the digital DFT design team and work closely with the digital design team for meeting TEST requirements for Automobile and work closely with test engineering teams for validating the test patterns and meeting ASIL-B/D requirements. You will have an opportunity to work on new designs, insert Lbist and shape the company’s pathway for success. Your responsibilities, depending on your level of experience and skill level, will be a mix of the following:\nInserting DFT/Scan on digital logic, ATPG, validating test patterns on pre and post layout gate level netlist.\nDelivering test patterns to TEST engineering team and validating them on silicon.\nInserting Logicbist with industry standard tools.\nImproving scan coverage and modifying RTL for scan.\nReduce ATE tester time by reducing scan patterns while achieving the required coverage.\nParticipate in all aspects of digital design flow - Micro-architecture, Design partitioning, RTL Verilog / System Verilog coding, DFT insertion, generating Timing Constraints, Synthesis, Interaction with P&R Team, Timing Analysis, LINT, CDC.\nWorking closely with Architects, Design, P&R, Test and Silicon validation teams.\nAssisting with top level test-bench creation for scan and running gate level simulations.\nDebug scan pattern fails on ATE and fix the scan patterns.\nWriting detailed design documents and help writing DFT specifications, reviewing the specs with different stake holders and own the design to meet the spec.\nOrganizing and participating in key design reviews and completion of various checklists.\nWorking on-site for 3 days a week is a must.\n\nFollowing are rough guidelines for the qualifications (if you feel you have much more or somewhat less, let that not stop you from applying):\nRequired\nMasters plus 12+ years or Bachelors plus 15+ years experience in digital design and DFT implementation.\nMust be a team player and yet be an independent thinker with strong digital design and DFT fundamentals\nHands on experience in Scan insertion, improving scan coverage, ATPG, experience in Logicbist insertion during synthesis or rtl.\nGate level simulations with test patterns, delivering test patterns to Test engineering team and work closely with them to get the patterns validated. \nMust have basic digital RTL coding experience besides synthesis exposure.\nMust have experience with at least 8 tapeouts with hands on experience with DFT/Scan.  \nIdeal candidate will have solid understanding of synthesizable design, timing constraints and exceptions.\nMust have experience with industry standard Synopsys, Cadence, Mentor, Siemens for scan, Lbist insertion and ATPG. Tetramax experience is a huge plus.\nAttention to detail, accuracy and expertise in DFT required.\nMust have good written and verbal cross-functional communication skills\nHave an analytical mind - be open to new ideas and have capability to persuade others in convincing and implementing better flows and processes.\nDesirable\nMixed signal experience highly preferred.\nExposure to automotive test requirements, ASIL, is highly preferred.\nEducation\n• BSEE required (MSEE preferred) \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nRenesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.", "jd_status": "stored"}, {"title": "Staff/ Sr Staff Engineer, Digital Design", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-24T06:53:29.079000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000145197139-staff-sr-staff-engineer-digital-design", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.\nWe are seeking a highly motivated and innovative Staff IC Design Engineer (RTL Design) with strong experience in SoC development flows. In this role, you will play a pivotal part in the design and development of advanced integrated circuits that power Renesas MCU products. You will lead complex RTL design efforts, own key IP/subsystem deliverables, mentor junior engineers, and help evolve design methodologies and best practices.\nKey Responsibilities\nLead RTL design and development of complex IPs and subsystems within MCU SoCs, ensuring compliance with performance, power, and area (PPA) targets\nDrive micro-architecture definition and high-level digital design for assigned blocks\nSupport SoC integration, delivering high-quality subsystem views and documentation to Back-end and Design Verification teams\nOwn design quality checks, including lint, CDC, and RDC, and actively support functional verification of assigned blocks\nCollaborate closely with system architects, verification engineers, physical design teams, and software teams to define specifications and ensure seamless end-to-end integration\nProvide technical guidance and mentorship to junior engineers, raising overall team capability and design quality\nContribute to continuous improvement of RTL design methodologies, coding guidelines, and design processes\n\nRequired Qualifications\nBachelor’s degree in Electronics & Communication Engineering, Electrical Engineering, Computer Engineering, or related technical field\nMinimum of 8 years of hands-on experience in digital IC/ASIC design, with a strong track record of delivering high-quality silicon\nStrong expertise in RTL design using Verilog/VHDL\nSolid understanding of digital design principles, timing analysis, clocking, resets, and verification methodologies\nExperience using industry-standard EDA tools for synthesis, simulation, and static timing analysis\nStrong problem-solving skills with the ability to own blocks end-to-end\nPreferred Qualifications\nExperience owning complex IPs or subsystem designs in large SoCs\nStrong background in micro-architecture design and high-level digital design\nHands-on experience with RTL quality tools such as Spyglass (Lint, CDC, RDC)\nExperience with low-power design techniques and methodologies\nFamiliarity with SoC-level design and integration\nUnderstanding of synthesis flows and timing constraints\nScripting experience in Shell, Perl, Python or use of AI for design is a strong plus.\nWhy Renesas\nAt Renesas India, you will work on industry-leading MCU platforms, collaborate with global teams, and influence next-generation semiconductor products. This role offers deep technical ownership, growth into architectural leadership, and the opportunity to shape how we design and deliver high-quality silicon.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Principal Engineer, Digital Design", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-24T06:53:20.201000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000145196274-principal-engineer-digital-design", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.\nWe are seeking a highly motivated and innovative Principal IC Design Engineer (RTL Design) with strong experience in SoC development flows. In this role, you will play a pivotal part in the design and development of advanced integrated circuits that power Renesas MCU products. You will lead complex RTL design efforts, own key IP/subsystem deliverables, mentor junior engineers, and help evolve design methodologies and best practices.\nKey Responsibilities\nLead RTL design and development of complex IPs and subsystems within MCU SoCs, ensuring compliance with performance, power, and area (PPA) targets\nDrive micro-architecture definition and high-level digital design for assigned blocks\nSupport SoC integration, delivering high-quality subsystem views and documentation to Back-end and Design Verification teams\nOwn design quality checks, including lint, CDC, and RDC, and actively support functional verification of assigned blocks\nCollaborate closely with system architects, verification engineers, physical design teams, and software teams to define specifications and ensure seamless end-to-end integration\nProvide technical guidance and mentorship to junior engineers, raising overall team capability and design quality\nContribute to continuous improvement of RTL design methodologies, coding guidelines, and design processes\n\nRequired Qualifications\nBachelor’s degree in Electronics & Communication Engineering, Electrical Engineering, Computer Engineering, or related technical field\nMinimum of 15 years of hands-on experience in digital IC/ASIC design, with a strong track record of delivering high-quality silicon\nStrong expertise in RTL design using Verilog/VHDL\nSolid understanding of digital design principles, timing analysis, clocking, resets, and verification methodologies\nExperience using industry-standard EDA tools for synthesis, simulation, and static timing analysis\nStrong problem-solving skills with the ability to own blocks end-to-end\nPreferred Qualifications\nExperience owning complex IPs or subsystem designs in large SoCs\nStrong background in micro-architecture design and high-level digital design\nHands-on experience with RTL quality tools such as Spyglass (Lint, CDC, RDC)\nExperience with low-power design techniques and methodologies\nFamiliarity with SoC-level design and integration\nUnderstanding of synthesis flows and timing constraints\nScripting experience in Shell, Perl, Python or use of AI for design is a strong plus.\nWhy Renesas\nAt Renesas India, you will work on industry-leading MCU platforms, collaborate with global teams, and influence next-generation semiconductor products. This role offers deep technical ownership, growth into architectural leadership, and the opportunity to shape how we design and deliver high-quality silicon.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Principal ATE Test Engineer ", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-24T05:37:09.038000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000145188149-principal-ate-test-engineer-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "As a Principal Test Engineer, you will be responsible to apply a broad level of expertise and knowledge in test discipline, leading and contributing to the development of the company objectives and principles to achieve goals in creative and effective ways. You will need to provide leadership and training.  You will own the schedule and work on issues that impact program success and future concepts and products. You will need to work with limited information and full ability to make clear judgements.  Long term view is required to align with strategics goals and objectives as results may impact multiple functions. You will need to network with key decision makers to determine future direction.  You are recognized as an expert by leadership and teams.  You can provide technical leading both internal and with external community and vendors. You may serve as an organization spokesperson. Maintain stable work relationships for exchanging information with colleagues and leadership to collaboratively solve problems.  You will need to coordinate with different groups and maintain stable work relationships for exchanging information with colleagues and leadership \nThis role is a key technical position combining deep hands-on expertise with strategic influence across product development and production. As a senior individual contributor, the selected candidate will define and lead test methodologies, guide complex technical decisions, and act as a reference point for the broader engineering team. \nRenesas Electronics, a leading global semiconductor company, is rapidly scaling investing in power delivery business. Products include Point of loads (POL), Hotswap/Efuse, Drivers. \nKey Responsibilities \nLead end-to-end test strategy definition for new product development, ensuring scalability, quality, and cost efficiency \n\nDefine and drive adoption of best-in-class test methodologies, test plan development, DFT approaches, and ATE hardware design \n\nAct as technical leader and mentor for test engineers, supporting capability growth across the team \n\nEnsure robust production release, including high coverage, test time optimization, and manufacturability \n\nLead root cause analysis and yield improvement initiatives, applying advanced statistical and data-driven techniques \n\nCollaborate cross-functionally with Design, Product Engineering, Operations, and Quality teams worldwide \n\nProvide technical leadership in customer interactions, escalations, and quality investigations \n\nInfluence test roadmap and long-term strategy, aligning with business and product requirements \n\nSupport cost reduction initiatives through test optimization and efficiency improvements \n\nBachelor’s degree in electrical/computer engineering (master’s preferred) \nTypically 12+ years of experience in test engineering for analog/mixed-signal or power management ICs \n\nExtensive expertise in ATE test development (COHU DMDX, DXV, Accotest) \n\nStrong knowledge of DFT techniques, test coverage analysis, and production flows \n\nProven experience in complex product bring-up, debug, and production ramp \n\nAdvanced skills in data analysis, statistical methods, and yield optimization \n\nStrong programming skills C/C++, python or similar is a plus \n\nDeep understanding of ATE instrumentation, signal integrity, and hardware design constraints \n\nExperience in debugging analog and mixed-signal systems, including serial interfaces \n\nKey Competencies \nStrong technical leadership without formal people management responsibility \n\nAbility to work independently and drive complex problems to resolution \n\nStrategic mindset with attention to technical details \n\nExcellent communication skills in global, cross-functional environments \n\nCapability to mentor engineers and elevate overall team performance \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Lead/Staff AI/ML Validation Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-08-24T05:34:00+00:00", "url": "https://global-external-amd.icims.com/jobs/87968/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Role Overview We are seeking an experienced SMTS Software Quality Engineer to join the HIP Runtime Quality Engineering team within the ROCm ecosystem. In this role, you will focus on defect triage, root‑cause analysis, and scalable test automation for the HIP runtime, ensuring robustness, portability, and performance across AMD and NVIDIA GPU backends. The role sits at the intersection of runtime systems, GPU APIs, and CI-driven quality assurance, working closely with HIP runtime developers, compiler teams, and system software engineers to improve test coverage and accelerate issue resolution across a fast-evolving open‑source stack. HIP is a C++ runtime API and kernel language designed for CUDA portability and heterogeneous GPU programming in the ROCm platform. Key Responsibilities Defect Triage & Root Cause Analysis Own end-to-end triage of HIP runtime failures observed in CI, nightly, and release testing pipelines. Analyze failures across HIP runtime APIs, including memory management, streams, events, kernels, graphs, and device management. Perform log analysis, repro reduction, and backtrace debugging across Linux and Windows environments. Correlate failures across: ROCr system runtime HIP runtime Driver / firmware interfaces Compiler (hipcc / clang) interactions File high‑quality bug reports with clear reproduction steps, root cause hypotheses, and impact assessment. Test Automation & Framework Development Design, enhance, and maintain automated test frameworks for HIP runtime validation using existing HIP test infrastructure (Catch2-based and custom harnesses). Expand functional, negative, stress, and regression coverage for: HIP Runtime APIs Graph APIs Memory copy variants (1D/2D/3D, async/sync) Multi-GPU and peer-to-peer use cases Integrate tests into CI/CD pipelines with actionable failure reporting. Develop Python, C++, and shell-based automation for test execution, result aggregation, and trend analysis. Drive test flakiness reduction and improve signal-to-noise ratio in large-scale CI. Cross-Team Collaboration Partner with HIP runtime developers to: Review test gaps for new features and APIs Validate bug fixes and performance-sensitive code paths Collaborate with: Compiler and language runtime teams ROCr system runtime teams Release engineering and CI infrastructure teams Contribute test fixes and enhancements upstream in open-source HIP/ROCm repositories. Quality Metrics & Continuous Improvement Define and track quality metrics such as failure escape rate, test coverage, and mean-time-to-resolution (MTTR). Identify systemic issues and propose data-driven quality improvements. Participate in release readiness assessments for HIP runtime drops. Required Qualifications Technical Skills Strong experience in software quality engineering, test automation, or SDET roles. Solid proficiency in C++ with debugging experience (gdb/lldb). Working knowledge of HIP or CUDA runtime concepts, including kernels, streams, memory models, and device execution. Experience with Linux-based development and debugging. Familiarity with CI systems (Jenkins, GitHub Actions, GitLab CI, or similar). Experience writing and maintaining automated tests for low-level systems or runtime libraries. Debugging & Analysis Skills Ability to reason about runtime abstractions, concurrency, and asynchronous execution. Strong skills in failure reproduction, minimization, and log-driven debugging. Experience triaging issues across hardware–software boundaries is a plus. Preferred Qualifications Experience with GPU programming models (HIP, CUDA, OpenCL). Familiarity with ROCm stack components (HIP, ROCr, compilers, drivers). Experience testing graph APIs, async execution models, or multi-GPU systems. Prior contributions to open-source system software or test frameworks. Knowledge of Python-based test orchestration and reporting tools. Knowledge and application of AI tools in validation and testing. What Success Looks Like Faster, higher-quality issue triage with actionable root cause insights. Improved automation coverage for HIP runtime APIs and edge cases. Reduced CI noise and faster feedback for developers. Strong collaboration with runtime and compiler engineers to ship stable, high-quality HIP releases. #LI-NR1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Lead Verification Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-08-24T03:44:00+00:00", "url": "https://global-external-amd.icims.com/jobs/86821/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Senior Lead Verification Engineer THE ROLE: As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON:  The preferred candidate will have proven experience verifying complex design blocks at the IP, Sub-system or SoC level using System Verilog/UVM or related technologies. He or she should be comfortable creating and executing on test plans in collaboration with design and verification colleagues in a metric-focused environment.   KEY RESPONSIBILITIES:  Develop and enhance System Verilog / UVM-based testbenches to verify new features for client, server, graphics, and semi-custom interconnects. Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture. Understand TestBench Architecture and develop expertise in TestBench Verification Components. Mentor junior engineers. PREFERRED EXPERIENCE:  Proficient in IP or Sub-system level ASIC verification Architected and developed complex verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar. Exposure to RTL design, software development, formal verification, or other related domains. Experience in UVM TestBench Development for complex designs preferred. 12+ years of industry experience is preferred ACADEMIC CREDENTIALS:  Bachelor’s or master’s degree in Electronics or Electrical or Computer engineering #LI-SR5 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Wireless R&D IP Verification Engineer, Senior Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-24T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446715788568", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n\nLocation: Bangalore\n\nKey Responsibilities\nTechnical Leadership Define and own verification strategy for IP/Block/Subsystem-level DV.\nGuide the team in developing robust verification environments and methodologies.\nEnsure best practices in coverage-driven and assertion-based verification.\n\nExecution Oversee end-to-end DV tasks: design analysis, verification planning, testbench development, simulation, and coverage closure.\nDrive adoption of advanced DV methodologies (formal, simulation, emulation) for efficiency and quality.\nReview and optimize test plans, environments, and scripts for scalability and reuse.\n\nCollaboration Work closely with global design, architecture, and cross-functional teams to meet project milestones.\nCommunicate effectively with stakeholders on progress, risks, and mitigation plans.\n\nMentorship Coach and mentor junior engineers, fostering technical growth and best practices.\n\nRequired Skills & Experience\nVast experience in IP-level design verification\nStrong expertise in SystemVerilog/UVM and coverage-driven verification methodologies.\nProven experience architecting and maintaining complex SV/UVM environments.\nProficiency in constraint-random testing and achieving coverage closure.\nStrong debugging skills using tools like Verdi or similar.\nExposure to wireless IPs (Wi-Fi, Modem PHY, DSP blocks) is a plus.\nFamiliarity with formal/static verification techniques.\nPower-aware verification and Gate-Level Simulation (GLS) experience is highly desirable.\nScripting skills (Python, Perl) for automation.\nQualifications\nEducation: Bachelor’s or Master’s or PhD in Electrical/Electronics/Computer Science from a reputed institution.\nExperience: 12-18 years\nSoft Skills\nExcellent communication and collaboration skills.\nAbility to lead and motivate a technical team.\nStrong problem-solving and decision-making abilities.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SoC RTL Design- Sr Staff Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-24T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446717615531", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nExperience in Logic design /micro-architecture / RTL coding is a must.  \n\nMust have hands on experience with SoC design and integration for SoCs. \n\nExperience in Verilog/System-Verilog is a must. \n\nShould have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC.  \n\nUnderstanding of Memory controller designs and microprocessors is an added advantage  \n\nHands on experience in constraint development and timing closure\n\nWork closely with the SoC verification and validation teams for pre/post Silicon debug  \n\nHands on experience in Low power SoC design is required\n\nExperience in Synthesis / Understanding of timing concepts for ASIC is required.  \n\nHands on experience in Multi Clock designs, Asynchronous interface is a must.  \n\nExperience creating pad ring and working with the chip level floorplan team is an added advantage  \n\nExperience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.  \n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nPreferred Skills & Experience:\n12+ years of experience in digital front-end ASIC/RTL design.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Display Synthesis Engineer, Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-24T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720679766", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nResponsibilities include:\n3+ years Experience\nSynthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation.\nDevelopment of signoff quality constraints and the development of power intent constraints.\nMay also include running RTL Lint, CLP, MEMBIST, DFT DRC etc.\nTCL script development in addition to running/analyzing/debugging designs.\nHands on with Synopsys DCG/Genus/Fusion Compiler.\nHands on with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains.\nHands on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development\nExperience with either RTL development or Physical Design is also a plus\n\nAdditional Job Description\nLooking for a highly talented and a technically strong leader with an eye for quality to lead a high performing and talented team of engineers in the implementation domain for Display Sub-System.\nAble to handle multiple project execution that are time critical and complex\nAble to communicate effectively with all stakeholders across the organization\nAble to collaborate with cross functional teams for upholding the best practices and enabling smooth execution\nFocus on improving execution efficiency and improve on the optimizations in area, power and performance.\nAble to grow the team in terms of technical depth and size as we do more and more projects\nAble to innovate and bring fresh ideas\nBachelor’s or master’s degree in engineering with 5+ Years of experience.\nShould have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.\nExperience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.\nExperience in all aspects of timing closure for multi-clock domain designs.\nShould be familiar with MCMM synthesis and optimization.\nShould have good understanding of low-power design implementation using UPF.\nExperience with scripting language such as Perl/ Python, TCL.\nExperience with different power optimization flows or technique such as clock gating.\nShould be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation\nShould be able to handle ECOs and formal verification and maintain high quality matrix\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Engineer - EDA ML Tools - Customer Engineering(Physical Design)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-24T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719366093", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Software Engineering\nGeneral Summary:\nRole Overview \n\nWe are looking for a Senior Engineer with strong domain expertise in VLSI/EDA tools and workflows to drive adoption, usability, and reliability of internal GenAI/Agentic AI tools and platform. \n\nThis role requires deep hands-on usage, triaging expertise, and customer engineering experience, acting as the bridge between Physical Design Engineers/CAD teams, Software and Systems engineering team. \n\nThe ideal candidate has exposure to AI/GenAI systems and can understand and debug workflows involving EDA tools, AI agents, orchestration pipelines, and non-deterministic system behaviors. \n\nKey Responsibilities \n\n- Own end-to-end user support and triage workflows; debug complex EDA environment, configuration and software integration issues \n\n- Diagnose workflow failures across toolchains, configurations, and infrastructure \n\n- Drive deep product understanding through hands-on tool usage across real workflows \n\n- Translate user requirements and issues into clear, actionable engineering inputs \n\n- Configure and onboard new projects and users; enable scalable adoption \n\n- Define and maintain real-world test cases and reproducible debugging scenarios \n\n- Collaborate with dev/QA teams to improve observability, debuggability, and stability \n\n- Debug AI/GenAI agent workflows, including orchestration failures, tool invocation issues, and non-deterministic behavior \n\n- Ensure tools operate in an agentic model with autonomous execution (MCP-based access) and minimal manual intervention \n\n- Define and validate clear functional specifications covering capabilities, inputs, outputs, and expected behavior \n\n- Drive structured enablement plans with phased onboarding, deliverables, acceptance criteria, and timelines \n\n- Develop comprehensive test strategies including shared and hidden testcases for robust validation \n\n- Measure tool performance using objective QoR metrics (TNS, WNS, congestion, runtime, memory) \n\n- Integrate tools into automated validation/regression pipelines for continuous testing and reporting \n\n- Enable usage telemetry collection (feature usage, runtime distribution, error trends) to support data-driven improvements \n\nRequired Skills & Experience \n\n- 2 to 6 years in Applications Engineering / Customer Engineering preferably in Physical Design (PNR/Floor planning) \n\n- Strong domain knowledge in VLSI / Physical Design / EDA workflows \n\n- Knowledge of Agentic AI /MCP/RAG workflows \n\n- Proven expertise in triaging and debugging complex software/tool issues \n\n- Strong Python/Linux/scripting experience \n\n- Ability to independently run and debug end-to-end workflows \n\n- Strong problem decomposition and root-cause analysis skills \n\n- Excellent communication and cross-functional collaboration \n\nPreferred Qualifications \n\n- Experience with AI/GenAI tools, agent frameworks, or orchestration systems \n\n- Familiarity with evaluation, benchmarking, or validation pipelines \n\n- Exposure to CI/CD, large-scale systems and HPC environments \n\n- Experience improving workflows, UX, or developer productivity \n\nPositioning \n\nThis is a hands-on Applications / Customer Engineering role with strong domain expertise, triage ownership, and AI/GenAI workflow understanding — not a Product Manager role. \n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience.\n                                                                    OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience.\n                                                                    OR\nPhD in Engineering, Information Systems, Computer Science, or related field.\n\n•    2+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Display Synthesis Engineer, Senior", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-24T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720679765", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nResponsibilities include:\n3+ years Experience\nSynthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation.\nDevelopment of signoff quality constraints and the development of power intent constraints.\nMay also include running RTL Lint, CLP, MEMBIST, DFT DRC etc.\nTCL script development in addition to running/analyzing/debugging designs.\nHands on with Synopsys DCG/Genus/Fusion Compiler.\nHands on with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains.\nHands on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development\nExperience with either RTL development or Physical Design is also a plus\n\nAdditional Job Description\nLooking for a highly talented and a technically strong leader with an eye for quality to lead a high performing and talented team of engineers in the implementation domain for Display Sub-System.\nAble to handle multiple project execution that are time critical and complex\nAble to communicate effectively with all stakeholders across the organization\nAble to collaborate with cross functional teams for upholding the best practices and enabling smooth execution\nFocus on improving execution efficiency and improve on the optimizations in area, power and performance.\nAble to grow the team in terms of technical depth and size as we do more and more projects\nAble to innovate and bring fresh ideas\nBachelor’s or master’s degree in engineering with 5+ Years of experience.\nShould have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.\nExperience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.\nExperience in all aspects of timing closure for multi-clock domain designs.\nShould be familiar with MCMM synthesis and optimization.\nShould have good understanding of low-power design implementation using UPF.\nExperience with scripting language such as Perl/ Python, TCL.\nExperience with different power optimization flows or technique such as clock gating.\nShould be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation\nShould be able to handle ECOs and formal verification and maintain high quality matrix\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SMMU Design Verification Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-24T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720384410", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nOwnership of System Memory Management [SMMU] IP test bench and collaterals for the next generation System-on-chip (SoC) for smartphones, tablets and other product categories. System Memory Management Unit does virtual to physical address translation, dynamic allocation and access control of DDR memory, designed as per ARM SMMU architecture spec.\nJob responsibilities include\nOwnership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage)\n\nDevelop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench\n\nWork closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure\n\nDebug of regression signatures and identifying bug fixes\n\nDeveloping/Deploying scripts/tools for validation (Certitude, VC Formal, Fishtail)\n\nDebug and root cause post silicon issues in collaboration with Design, SW and test teams\n\nWork with SoC level performance modeling team on latency, bandwidth analysis\n\nRequired skillset include\nStrong debugging, Analytical and problem-solving skills\n\nExpertise on UVM, System Verilog coding\n\nKnowledgeable about ARM bus protocols (AXI, AHB, APB, CHI), Virtual Memory concepts, SoC system architecture\n\nExperience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved\n\nPost-si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage\n\nCommunication and collaboration skills to work with a large world-wide design organization\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RISCV Infra System IP DV - Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-24T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720641743", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nJob Area Engineering - IP Design Verification\nLocation: Bangalore\n\nEducational Requirements\nBachelor/Master’s Degree in Electronics & Communication / Micro Electronics\n\nJob responsibilities include\n3 to 15 years of solid experience in IP/Sub System design verification\nExpertise on UVM, System Verilog DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage)\nDevelop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench\nWork closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure\nDebug of regression signatures and identifying bug fixes\nUnderstanding of bus protocols like CHI/AHB/AXI/ACE/ACE-Lite and Interconnect concepts\nKnowledgeable on ARM / RISCV system architecture, Memory Management, Virtual Memory concepts, Core sight architecture, power management fundamentals\nUnderstanding of multi-core ARMv8/v9 CPU architecture, coherency protocols and virtualization\nCommunication and collaboration skills to work with a large world-wide design organization\nPost-Silicon bring-up and HW-SW debug experience would be a plus\nProficiency in Gen AI skills, Scripting languages (Python or Perl) for Automation initiatives is desirable\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Infra Design Verification Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-24T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720202498", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nKey Responsibilities:\nDevelop and maintain UVM-based verification environments for high-speed interconnect protocols (PCIe, CXL, AXI).\n\nCreate and execute verification plans for high-speed interconnect protocols including PCIe, CXL, AXI, and CHI.\n\nPerform block-level and top-level verification, including functional coverage, assertion-based verification, and regression testing.\n\nCollaborate with RTL designers, architects, and validation teams to ensure design correctness and coverage closure.\n\nWork closely with design and architecture teams to understand specifications and derive verification strategies.\n\nUse third-party VIPs (e.g., Synopsys, Mentor) for protocol compliance and simulation.\n\nImplement and enhance scoreboards, agents, monitors, and sequences.\n\nIntegrate and validate SMMU and Coresight components in Subsystem environments.\n\nDrive verification closure through coverage convergence and assertion-based verification.\n\nContribute to performance, power, and cost optimization considerations during verification.\n\nMentor junior engineers and contribute to verification methodology improvements.\n\nDebug failures at RTL and gate-level simulations.\n\nRequired Skills:\nStrong proficiency in System Verilog, UVM, and verification methodologies.\n\nDeep understanding of PCIe Gen3/Gen4/Gen5/Gen6, CXL 1.1/2.0/3.0, AXI/CHI protocols, and SMMU/Coresight architecture.\n\nFamiliarity with Synopsys/Mentor VIPs for PCIe/CXL and AMBA protocols.\n\nExpertise in assertion-based verification (SVA) and coverage-driven testing.\n\nProficiency in Perl/Python/Tcl scripting for automation.\n\nKnowledge of power-aware verification (UPF), formal verification, and performance/power optimization.\n\nExperience with coverage-driven verification and random constraint-based testing.\n\nExperience with scripting languages like Python, Perl, or Tcl.\n\nPreferred Qualifications:\nBachelor’s/Master’s/Ph.D. in Electrical, Electronics, or Computer Engineering.\n\n6–10+ years of ASIC/Subsystem/SoC verification experience.\n\nExperience with PCIe, USB, Ethernet, or other peripheral protocols is a plus.\n\nExposure to post-silicon validation and lab bring-up is desirable.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Sr Staff Engineer - Hardware Design", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-24T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718770963", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    5+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RISCV Infra System IP DV - Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-24T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720642660", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nJob Area Engineering - IP Design Verification\nLocation: Bangalore\n\nEducational Requirements\nBachelor/Master’s Degree in Electronics & Communication / Micro Electronics\n\nJob responsibilities include\n3 to 15 years of solid experience in IP/Sub System design verification\nExpertise on UVM, System Verilog DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage)\nDevelop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench\nWork closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure\nDebug of regression signatures and identifying bug fixes\nUnderstanding of bus protocols like CHI/AHB/AXI/ACE/ACE-Lite and Interconnect concepts\nKnowledgeable on ARM / RISCV system architecture, Memory Management, Virtual Memory concepts, Core sight architecture, power management fundamentals\nUnderstanding of multi-core ARMv8/v9 CPU architecture, coherency protocols and virtualization\nCommunication and collaboration skills to work with a large world-wide design organization\nPost-Silicon bring-up and HW-SW debug experience would be a plus\nProficiency in Gen AI skills, Scripting languages (Python or Perl) for Automation initiatives is desirable\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "LPASS Design Verification Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-24T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719926174", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nQualcomm LPASS HW team in Bangalore is part of a worldwide team responsible for developing and delivering Audio solutions which are setting the benchmark in mobile computing industry. The role of LPASS DV Engineer will involve a deep understanding of the HW architecture while getting an opportunity to work with the latest DV tools and technologies.\nIndividual responsibility will include\nDV ownership of one or more features in the Low power audio subsystem(LPASS) core\n\nDeveloping a robust testbench, optimized for the specific feature/DUT\n\nExplore innovative DV methodologies (formal, simulation and emulation based) to continuously push the quality and efficiency of test benches and process improvements.\n\nEnsure a bug free silicon for Tape Out which eventually leads to a superb user experience of Snapdragon based computing devices\n\nFor better understanding of some of our products, please refer to the links below\nhttps://www.qualcomm.com/products/smartphones\nQualcomm Aqstic | Qualcomm\n\nMinimum Qualifications\nMinimum 1 - 2  years of VLSI industry experience\n\nStrong debugging and analytical skills\n\nStrong knowledge of HDLs like Verilog, System Verilog\n\nProficiency in developing SV/UVM based test benches\n\nProficient in debugging RTL/TB issues using Verdi or similar tools\n\nProficient with scripting languages such as Perl and(or) Python\n\nPreferred Qualifications *\nKnowledge of UPF, low power  architecture\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Peripherals Design Verification Staff Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-24T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719886148", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\n9+ years’ experience in unit and IP level verification.\nWorked on coverage driven constraint random verification.\n\nKnowledge of standard protocols such as PCIe, CXL, USB, Ethernet.\n\nStrong in System Verilog, UVM, Test planning\n\nSound experience in testbench (stimulus, agent, monitor, checker) development.\n\nWorked in the verification having c based reference model inside the testbench\n\nExposure in scripting(perl, Python).\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Packaging Associate, IN Packaging", "company": "Amazon", "location": "Bengaluru, Karnataka, IND", "date_posted": "2026-08-24", "url": "https://www.amazon.jobs/en/jobs/10511698/packaging-associate-in-packaging", "is_hardware": true, "platform": "amazon", "jd_text": "At Amazon, we strive to be Earth’s most customer-centric company where people can find and discover anything they want to buy online. We hire the world’s brightest minds, offering them an environment in which they can relentlessly improve the experience for customers. Innovation and creativity are built into the DNA of the company and are encouraged at all levels of employment. Every day we solve complex technical and business problems with ingenuity and simplicity. We’re making history and the good news is we’ve only just begun.\n\nKey roles and responsibilities will include:\n1. Perform visual testing against attributes for PWP/any other workstream in Imaging team.\n2. Responsible for achieving the metric goals for imaging team.\n3. Identify and manage small-scale process improvement opportunities by performing root cause analysis.\n\nSkills:\n•\tExcellent analytical and statistical skills\n•\tProblem solving through data driven approach\n•\t0-1 year experience and process understanding of AMZ\n•\tExcellent written & verbal communication skills including writing skills in Word, Power point, and Excel\n•\tBachelor’s degree or higher.\n•\tAbility to relocate to Bangalore as per the requirement.\nJob Location- Bangalore, Karnataka\n\nKey job responsibilities\n1. Perform visual testing against attributes for PWP/any other workstream in Imaging team.\n2. Responsible for achieving the metric goals for imaging team.\n3. Identify and manage small-scale process improvement opportunities by performing root cause analysis.\n\nAbout the team\nWe are a high performance team working closest with the customer.\n\nBasic qualifications\n- Bachelor's degree\n- Experience using clear communication skills and experience delivering training to groups and creating corresponding communications and training materials\n- Experience in problem solving and delivering results\n\nPreferred qualifications\n- Knowledge of Microsoft Office products and applications\n- Experience in problem solving and delivering results\n\nOur inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "jd_status": "stored"}, {"title": "Sr. Design Automation Engineer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-08-24", "url": "https://careers.skyworksinc.com/job-invite/77977/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 77977\n\nDescription\n\nWe are building an intelligent analog and mixed-signal design automation flow that applies agentic AI and machine learning to modernize design and verification practice. You will join a central engineering team developing a next-generation, AI-enabled design and verification platform for complex analog/mixed-signal and RF products and modules - from die-level blocks to integrated module architectures.\nThis role calls for an engineer who has built UVM verification environments and has an automation mindset to encode that expertise into scalable flows. You will inform how the platform reasons about testbenches, coverage, and regressions, and guides engineers through complex digital and mixed-signal verification workflows. Your job is to bridge proven DV practice and new automation so the platform stays grounded in how high-performance products are verified and signed off.\n\nResponsibilities\n\nDesign and deploy ML inference models for engineering use cases: prediction, classification, anomaly detection, and recommendation over design/simulation data\n\nBuild data engineering pipelines to ingest, clean, label, and version datasets from design and layout databases, as well as simulation and physical verification results\n\nDevelop LLM-based applications with chain-of-thought prompting for guided troubleshooting, documentation Q&A, and methodology assistance\n\nImplement MLOps practices: model versioning, A/B testing, monitoring for drift, and reproducible training pipelines\n\nCreate APIs and services that integrate ML capabilities into existing EDA and engineering platforms\n\nCollaborate with domain experts to define features, labels, and evaluation metrics grounded in engineering outcomes\n\nStay current with industry-standard techniques in deep learning, transformers, and efficient inference\n\nRequired Experience and Skills\n\nB.S. or higher in Electrical Engineering, Computer Engineering, or Computer Science\n\n3+ years of professional digital design verification experience\n\nStrong experience building SystemVerilog/UVM testbenches (architecture, agents, scoreboards, coverage) - not only writing tests in an existing environment\n\nStrong experience with scripting languages (Python, Bash)\n\nStrong debugging and analytical skills\n\nExcellent communications skills with the ability to work and thrive in a team environment\n\nDesired Experience and Skills\n\nSimulator and regression experience (VCS, Xcelium, Questa, or equivalent) including batch/farm runs\n\nAssertions (SVA), formal, or mixed-signal / AMS co-verification\n\nExperience creating, verifying, and simulating with behavioral models for analog circuits.\n\nAutomation for testbench setup, results parsing, coverage reporting, or regression orchestration\n\nProficiency with git version control and CI/CD pipelines\n\nPractical ML/AI skills: Python-based development with frameworks such as PyTorch, TensorFlow, or LangChain/LlamaIndex (or equivalent); experience building LLM applications, RAG pipelines, or ML inference services\n\nExperience building or integrating agentic workflows that call EDA tools (simulation, formal, job schedulers) as tools in a loop\n\nScripts that integrate with HPC/job farms for batch simulation or regression\n\nInterest in applying ML to verification artifacts (coverage, logs, traces, test stimulus) beyond text-only LLM use\n\n#LIPR1\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Sr. Design Automation Engineer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-08-24", "url": "https://careers.skyworksinc.com/job-invite/77976/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 77976\n\nDescription\n\nWe are building an intelligent analog and mixed-signal design automation flow that applies agentic AI and machine learning to modernize design and verification practice. You will join a central engineering team developing a next-generation, AI-enabled design and verification platform for complex analog/mixed-signal and RF products and modules - from die-level blocks to integrated module architectures.\nThis role calls for an engineer who can bring analog/RF IC design and verification knowledge and an automation mindset to encode that expertise into scalable flows. You will inform how the platform reasons about circuits, runs verification, and guides engineers through complex AMS and RF workflows. Your job is to bridge proven AMS/RF practice and new automation so the platform stays grounded in how high-performance products are built and signed off.\n\nResponsibilities\n\nUnderstand design, simulate, and layout challenges in RF/analog blocks including PAs, LNAs, switches, and filter networks in Cadence Virtuoso across multiple process technologies and be able to encode that knowledge into an intelligent automation flow\n\nUnderstand how design, simulation and physical verification data is generated across distributed platforms and develop strategies for engineering that data for a machine learning and/or agentic AI platform\n\nPartner with PDK, layout, and verification teams to align design practices with process capabilities, DRM limits, and foundry release schedules\n\nDevelop connections between design steps and tools in the analog, RF and mixed-signal domains using agentic AI framework with the goal of developing a self-evolving design flow\n\nRequired Experience and Skills\n\nB.S. or higher in Electrical Engineering, Computer Engineering, or Computer Science\n\n3+ years of professional experience in analog/RF IC design and verification or EDA engineering in an analog or RF environment\n\nStrong automation skills for analog/RF flows (Python, SKILL, Tcl, or equivalent)\n\nDemonstrated ability of turning informal design and verification practice into structured workflows\n\nStrong debugging and analytical skills\n\nExcellent communications skills with the ability to work and thrive in a team environment\n\nDesired Experience and Skills\n\nHands-on Cadence Virtuoso: schematic entry, simulation, layout\n\nExperience creating and verifying Verilog-A and SystemVerilog RNM behavioral models for analog circuits.\n\nAutomation for flow orchestration, testbench setup, results parsing, or layout-assisted routines\n\nExposure to internal/custom process technologies and/or external foundry PDKs for analog/RF work\n\nPractical ML/AI skills: Python-based development with frameworks such as PyTorch, TensorFlow, or LangChain/LlamaIndex (or equivalent); experience building LLM applications, RAG pipelines, or ML inference services\n\nExperience building or integrating agentic workflows that call EDA tools (simulation, DRC/LVS, EM, or job schedulers) as tools in a loop\n\nWorking knowledge of agentic AI systems: multi-step agents, tool use / function calling, planning and orchestration, and evaluation of agent behavior — useful on this seat, not the core of it\n\nExperience with filter co-design in a module environment, EM-aware layout, or AMS co-simulation — useful as domain grounding for automated and agent behavior\n\nScripts that integrate with HPC/job farms for batch simulation or regression\n\nInterest in applying ML to circuit/layout representations (graphs, embeddings) beyond text-only LLM use\n\n#LIPR1\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Principal Engineer- Interface IP Verification (Pre-Silicon- PCIe/CXL/DDR/Ethernet)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-24", "url": "https://careers.synopsys.com/job/bengaluru/principal-engineer-interface-ip-verification-pre-silicon-pcie-cxl-ddr-ethernet/44408/99675054336", "is_hardware": true, "platform": "talentbrew", "jd_text": "Principal Engineer- Interface IP Verification (Pre-Silicon- PCIe/CXL/DDR/Ethernet)We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years verifying silicon that ships into data centers, AI accelerators, and high-performance systems where failure is not an option. The protocols you verify, PCIe, CXL, DDR, Ethernet, are not abstract specs to you. They are living, breathing systems with corner cases that only reveal themselves at 3 a.m. during a regression run, and you are the engineer who finds them before tape-out.\nYou think in layers. You can debug a failing assertion in the UVM environment, trace it back to an RTL timing issue, and then connect it to a protocol compliance gap, all without losing the thread of what actually broke. When someone says 'coverage is at 95%,' you ask which 5% is missing and whether it matters.\nYou do not wait for perfect documentation. Specs are incomplete, architectures evolve, and you have learned to work with what you have, ask the right questions, and build verification environments that adapt as the design matures. You have strong opinions on what makes a testbench reusable versus one that becomes technical debt, and you are not afraid to push back when a verification strategy does not account for real-world integration scenarios.\nAt Synopsys, you will verify Interface IP that powers the semiconductor industry's most critical applications, and the team you work with will expect you to lead, not just execute.\nWhat You'll Be Doing\nOwn end-to-end verification of Interface IP blocks including PCIe, CXL, DDR, and Ethernet, from architecture review through silicon signoff\nBuild and evolve UVM-based verification environments that are reusable across product lines and scalable for future protocol generations\nDefine verification strategies and test plans that account for protocol compliance, performance corner cases, and system-level integration scenarios\nDevelop constrained-random, coverage-driven test scenarios using SystemVerilog and UVM, targeting functional coverage closure and signoff quality\nDebug complex multi-layer issues spanning RTL logic, protocol state machines, timing, and testbench infrastructure using VCS or equivalent simulators\nCollaborate with architecture, design, firmware, and systems teams to identify and resolve issues early in the development cycle\nMentor verification engineers on UVM methodology, coverage analysis, debugging techniques, and verification best practices\nThe Impact You Will Have\nYour verification work will directly determine the quality and reliability of IP integrated into AI platforms, cloud infrastructure, and automotive systems used globally\nThe testbenches and verification IP you build will be reused across multiple product generations, multiplying your impact across the organization\nYour coverage strategies and signoff criteria will set the standard for verification quality across the Interface IP portfolio\nThe protocol bugs you catch pre-silicon will prevent costly respins and delays for customers building next-generation SoCs\nYour technical leadership will shape verification methodology improvements that raise the bar for the entire engineering team\nThe mentorship you provide will accelerate the growth of engineers who will carry forward the verification practices you help establish\nYour collaboration with architecture and design teams will influence early design decisions that make verification more efficient and products more robust\nWhat You'll Need\nBachelor's or Master's in Electrical Engineering or Computer Engineering with 10+ years of hands-on ASIC or SoC verification experience\nDeep expertise in SystemVerilog and UVM methodology, with a track record of building scalable verification environments from the ground up\nStrong protocol knowledge in at least one of PCIe, CXL, DDR, or Ethernet, with the ability to read specs and translate them into verification requirements\nProven experience developing constrained-random and coverage-driven verification solutions that achieve functional signoff\nSolid debugging skills across RTL, verification infrastructure, and protocol compliance, with experience using industry-standard simulators like VCS or ModelSim\nExperience with verification IP development, assertion-based verification, or formal methods is a strong plus\nKnowledge of modern SoC architectures and high-speed communication interfaces is a plus\nWho You Are\nYou can walk into a spec review, identify the verification-critical corner cases that are not explicitly called out, and build a test plan that covers them\nWhen a regression fails at 2 a.m. before a milestone, you are the engineer who triages the root cause, determines if it is a real bug or a testbench issue, and has a fix ready by morning standup\nYou know the difference between coverage that looks good on a dashboard and coverage that actually means the design is verified, and you are willing to have the hard conversation when the two do not align\nYou can explain a complex protocol violation to a design engineer in a way that makes the fix obvious, and then turn around and present the same issue to an architect in terms of system-level impact\nYou are comfortable leading technical discussions with senior engineers and architects, even when your point of view challenges the current plan\nYou see mentorship as part of the job, not an extra task, and you make time to help less experienced engineers understand not just what to do, but why it matters\nThe Team You'll Be Part Of\nYou will join a team of highly skilled verification engineers responsible for developing and verifying industry-leading Interface IP solutions. Working alongside experts in architecture, design, and verification, you will tackle some of the semiconductor industry's most challenging technical problems while contributing to products deployed worldwide. The team operates globally, collaborates across time zones, and values technical depth, ownership, and the kind of problem-solving that makes complex IP actually work in customer silicon.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-24", "url": "https://careers.synopsys.com/job/bengaluru/senior-staff-interface-ip-verification-engineer-pre-silicon-pcie-cxl-ddr-ethernet/44408/99675054304", "is_hardware": true, "platform": "talentbrew", "jd_text": "Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet)\n \nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years verifying silicon that ships into data centers, AI accelerators, and high-performance systems where failure is not an option. The protocols you verify, PCIe, CXL, DDR, Ethernet, are not abstract specs to you. They are living, breathing systems with corner cases that only reveal themselves at 3 a.m. during a regression run, and you are the engineer who finds them before tape-out.\nYou think in layers. You can debug a failing assertion in the UVM environment, trace it back to an RTL timing issue, and then connect it to a protocol compliance gap, all without losing the thread of what actually broke. When someone says 'coverage is at 95%,' you ask which 5% is missing and whether it matters.\nYou do not wait for perfect documentation. Specs are incomplete, architectures evolve, and you have learned to work with what you have, ask the right questions, and build verification environments that adapt as the design matures. You have strong opinions on what makes a testbench reusable versus one that becomes technical debt, and you are not afraid to push back when a verification strategy does not account for real-world integration scenarios.\nAt Synopsys, you will verify Interface IP that powers the semiconductor industry's most critical applications, and the team you work with will expect you to lead, not just execute.\nWhat You'll Be Doing\nOwn end-to-end verification of Interface IP blocks including PCIe, CXL, DDR, and Ethernet, from architecture review through silicon signoff\nBuild and evolve UVM-based verification environments that are reusable across product lines and scalable for future protocol generations\nDefine verification strategies and test plans that account for protocol compliance, performance corner cases, and system-level integration scenarios\nDevelop constrained-random, coverage-driven test scenarios using SystemVerilog and UVM, targeting functional coverage closure and signoff quality\nDebug complex multi-layer issues spanning RTL logic, protocol state machines, timing, and testbench infrastructure using VCS or equivalent simulators\nCollaborate with architecture, design, firmware, and systems teams to identify and resolve issues early in the development cycle\nMentor verification engineers on UVM methodology, coverage analysis, debugging techniques, and verification best practices\nThe Impact You Will Have\nYour verification work will directly determine the quality and reliability of IP integrated into AI platforms, cloud infrastructure, and automotive systems used globally\nThe testbenches and verification IP you build will be reused across multiple product generations, multiplying your impact across the organization\nYour coverage strategies and signoff criteria will set the standard for verification quality across the Interface IP portfolio\nThe protocol bugs you catch pre-silicon will prevent costly respins and delays for customers building next-generation SoCs\nYour technical leadership will shape verification methodology improvements that raise the bar for the entire engineering team\nThe mentorship you provide will accelerate the growth of engineers who will carry forward the verification practices you help establish\nYour collaboration with architecture and design teams will influence early design decisions that make verification more efficient and products more robust\nWhat You'll Need\nBachelor's or Master's in Electrical Engineering or Computer Engineering with 8+ years of hands-on ASIC or SoC verification experience\nDeep expertise in SystemVerilog and UVM methodology, with a track record of building scalable verification environments from the ground up\nStrong protocol knowledge in at least one of PCIe, CXL, DDR, or Ethernet, with the ability to read specs and translate them into verification requirements\nProven experience developing constrained-random and coverage-driven verification solutions that achieve functional signoff\nSolid debugging skills across RTL, verification infrastructure, and protocol compliance, with experience using industry-standard simulators like VCS or ModelSim\nExperience with verification IP development, assertion-based verification, or formal methods is a strong plus\nKnowledge of modern SoC architectures and high-speed communication interfaces is a plus\nWho You Are\nYou can walk into a spec review, identify the verification-critical corner cases that are not explicitly called out, and build a test plan that covers them\nWhen a regression fails at 2 a.m. before a milestone, you are the engineer who triages the root cause, determines if it is a real bug or a testbench issue, and has a fix ready by morning standup\nYou know the difference between coverage that looks good on a dashboard and coverage that actually means the design is verified, and you are willing to have the hard conversation when the two do not align\nYou can explain a complex protocol violation to a design engineer in a way that makes the fix obvious, and then turn around and present the same issue to an architect in terms of system-level impact\nYou are comfortable leading technical discussions with senior engineers and architects, even when your point of view challenges the current plan\nYou see mentorship as part of the job, not an extra task, and you make time to help less experienced engineers understand not just what to do, but why it matters\nThe Team You'll Be Part Of\nYou will join a team of highly skilled verification engineers responsible for developing and verifying industry-leading Interface IP solutions. Working alongside experts in architecture, design, and verification, you will tackle some of the semiconductor industry's most challenging technical problems while contributing to products deployed worldwide. The team operates globally, collaborates across time zones, and values technical depth, ownership, and the kind of problem-solving that makes complex IP actually work in customer silicon.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-24", "url": "https://careers.synopsys.com/job/bengaluru/senior-staff-interface-ip-verification-engineer-pre-silicon-pcie-cxl-ddr-ethernet/44408/99675054288", "is_hardware": true, "platform": "talentbrew", "jd_text": "Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet)\n \nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years verifying silicon that ships into data centers, AI accelerators, and high-performance systems where failure is not an option. The protocols you verify, PCIe, CXL, DDR, Ethernet, are not abstract specs to you. They are living, breathing systems with corner cases that only reveal themselves at 3 a.m. during a regression run, and you are the engineer who finds them before tape-out.\nYou think in layers. You can debug a failing assertion in the UVM environment, trace it back to an RTL timing issue, and then connect it to a protocol compliance gap, all without losing the thread of what actually broke. When someone says 'coverage is at 95%,' you ask which 5% is missing and whether it matters.\nYou do not wait for perfect documentation. Specs are incomplete, architectures evolve, and you have learned to work with what you have, ask the right questions, and build verification environments that adapt as the design matures. You have strong opinions on what makes a testbench reusable versus one that becomes technical debt, and you are not afraid to push back when a verification strategy does not account for real-world integration scenarios.\nAt Synopsys, you will verify Interface IP that powers the semiconductor industry's most critical applications, and the team you work with will expect you to lead, not just execute.\nWhat You'll Be Doing\nOwn end-to-end verification of Interface IP blocks including PCIe, CXL, DDR, and Ethernet, from architecture review through silicon signoff\nBuild and evolve UVM-based verification environments that are reusable across product lines and scalable for future protocol generations\nDefine verification strategies and test plans that account for protocol compliance, performance corner cases, and system-level integration scenarios\nDevelop constrained-random, coverage-driven test scenarios using SystemVerilog and UVM, targeting functional coverage closure and signoff quality\nDebug complex multi-layer issues spanning RTL logic, protocol state machines, timing, and testbench infrastructure using VCS or equivalent simulators\nCollaborate with architecture, design, firmware, and systems teams to identify and resolve issues early in the development cycle\nMentor verification engineers on UVM methodology, coverage analysis, debugging techniques, and verification best practices\nThe Impact You Will Have\nYour verification work will directly determine the quality and reliability of IP integrated into AI platforms, cloud infrastructure, and automotive systems used globally\nThe testbenches and verification IP you build will be reused across multiple product generations, multiplying your impact across the organization\nYour coverage strategies and signoff criteria will set the standard for verification quality across the Interface IP portfolio\nThe protocol bugs you catch pre-silicon will prevent costly respins and delays for customers building next-generation SoCs\nYour technical leadership will shape verification methodology improvements that raise the bar for the entire engineering team\nThe mentorship you provide will accelerate the growth of engineers who will carry forward the verification practices you help establish\nYour collaboration with architecture and design teams will influence early design decisions that make verification more efficient and products more robust\nWhat You'll Need\nBachelor's or Master's in Electrical Engineering or Computer Engineering with 8+ years of hands-on ASIC or SoC verification experience\nDeep expertise in SystemVerilog and UVM methodology, with a track record of building scalable verification environments from the ground up\nStrong protocol knowledge in at least one of PCIe, CXL, DDR, or Ethernet, with the ability to read specs and translate them into verification requirements\nProven experience developing constrained-random and coverage-driven verification solutions that achieve functional signoff\nSolid debugging skills across RTL, verification infrastructure, and protocol compliance, with experience using industry-standard simulators like VCS or ModelSim\nExperience with verification IP development, assertion-based verification, or formal methods is a strong plus\nKnowledge of modern SoC architectures and high-speed communication interfaces is a plus\nWho You Are\nYou can walk into a spec review, identify the verification-critical corner cases that are not explicitly called out, and build a test plan that covers them\nWhen a regression fails at 2 a.m. before a milestone, you are the engineer who triages the root cause, determines if it is a real bug or a testbench issue, and has a fix ready by morning standup\nYou know the difference between coverage that looks good on a dashboard and coverage that actually means the design is verified, and you are willing to have the hard conversation when the two do not align\nYou can explain a complex protocol violation to a design engineer in a way that makes the fix obvious, and then turn around and present the same issue to an architect in terms of system-level impact\nYou are comfortable leading technical discussions with senior engineers and architects, even when your point of view challenges the current plan\nYou see mentorship as part of the job, not an extra task, and you make time to help less experienced engineers understand not just what to do, but why it matters\nThe Team You'll Be Part Of\nYou will join a team of highly skilled verification engineers responsible for developing and verifying industry-leading Interface IP solutions. Working alongside experts in architecture, design, and verification, you will tackle some of the semiconductor industry's most challenging technical problems while contributing to products deployed worldwide. The team operates globally, collaborates across time zones, and values technical depth, ownership, and the kind of problem-solving that makes complex IP actually work in customer silicon.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Staff Interface IP Verification Engineer (Pre-Silicon)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-24", "url": "https://careers.synopsys.com/job/bengaluru/staff-interface-ip-verification-engineer-pre-silicon/44408/99675054256", "is_hardware": true, "platform": "talentbrew", "jd_text": "Staff Interface IP Verification Engineer (Pre-Silicon)We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years verifying silicon that has to actually work, not just pass regression, actually work, in production systems where a protocol violation or a corner case bug can cost a customer months of schedule and millions in respins. You know that the difference between IP that ships clean and IP that comes back with errata is usually a testbench decision made six months earlier, and you are the kind of engineer who catches that gap before tapeout.\nYou are comfortable moving between PCIe link training sequences, CXL cache coherency protocols, and DDR timing constraints without losing sight of what you are actually building: reusable verification environments that have to scale across product families and customer use cases. You do not need a perfect spec to get started. You read between the lines, ask the right questions of architects, and build coverage models that reflect real-world integration scenarios, not just checklist compliance.\nDebugging energizes you. Not because it is heroic, but because finding the root cause of a multi-layer protocol issue and fixing it upstream makes the difference for every team that integrates your IP downstream. You have opinions on what good UVM architecture looks like, and you are not afraid to push back when a verification plan misses the actual risk.\nAt Synopsys, you will work on Interface IP that powers AI accelerators, data centers, and next-generation SoCs used by the world's leading semiconductor companies. The team is global, the protocols are real, and what you verify will matter.\nWhat You'll Be Doing\nOwn end-to-end verification of complex Interface IP including PCIe, CXL, DDR, and Ethernet, from architecture review through signoff and customer release\nArchitect and build scalable UVM-based verification environments and reusable verification IP components that work across multiple product variants and customer configurations\nDefine verification strategies and detailed test plans by analyzing specifications, identifying protocol corner cases, and mapping coverage goals to real integration risks\nDevelop constrained-random, coverage-driven testbenches using SystemVerilog and UVM, with a focus on protocol compliance, performance validation, and system-level interaction scenarios\nDrive functional coverage closure by analyzing gaps, writing targeted tests, and working with design teams to ensure all architectural intent is verified before tapeout\nDebug complex RTL, protocol, and system-level issues across simulators like VCS or ModelSim, using waveform analysis, assertions, and protocol monitors to isolate root cause\nMentor verification engineers on UVM methodology, coverage techniques, and debugging approaches while contributing to verification infrastructure and process improvements across the team\nThe Impact You Will Have\nYour verification work will directly determine the quality and reliability of Interface IP integrated into AI platforms, hyperscale data centers, and high-performance computing systems used worldwide\nYou will reduce customer-found bugs and post-silicon errata by catching protocol violations, timing issues, and integration corner cases during pre-silicon verification\nYour reusable verification IP and testbench architectures will accelerate verification timelines for future product generations and reduce bring-up time for derivative designs\nYou will influence verification methodology and best practices across the Interface IP engineering organization, raising the bar for coverage rigor and automation efficiency\nYour coverage models and test strategies will become the reference standard for how complex protocols like PCIe Gen6, CXL 3.0, and DDR5 are verified at Synopsys\nYou will help develop the next generation of verification engineers by sharing expertise in protocol verification, UVM architecture, and systematic debugging techniques\nYour technical leadership will drive successful product releases that meet the quality expectations of the world's most demanding semiconductor customers\nWhat You'll Need\nBachelor's or Master's in Electrical Engineering or Computer Engineering with at least 5 years of hands-on ASIC or SoC verification experience\nDeep expertise in SystemVerilog and UVM methodologies, including building constrained-random testbenches, functional coverage models, and reusable verification components\nStrong protocol knowledge in one or more of PCIe, CXL, DDR memory interfaces, or Ethernet, with demonstrated experience verifying protocol compliance and system-level interactions\nProven experience developing coverage-driven verification environments and driving coverage closure on complex designs through tapeout\nStrong debugging skills across RTL, verification infrastructure, and protocol layers, with experience using industry-standard simulators such as VCS, ModelSim, Xcelium, or Questa\nExperience with verification IP development, assertion-based verification, or formal methodologies is a strong plus\nKnowledge of modern SoC architectures, high-speed SerDes interfaces, or cache coherency protocols is a plus\nWho You Are\nYou can walk into a spec review, spot the ambiguities that will become verification holes three months later, and ask the questions that force clarity before RTL is written\nYou write UVM code that other engineers can actually read and extend, you care about class hierarchy, encapsulation, and making your testbench maintainable for the team that inherits it\nYou do not declare victory when regression passes, you dig into coverage reports, find the scenarios you are not hitting, and write the tests that close the gaps before someone else finds them in silicon\nYou can explain a complex protocol deadlock scenario to a design engineer in two sentences without losing the technical nuance, and you know when to escalate an issue versus when to debug it yourself\nYou work effectively across global teams and time zones, keeping verification plans aligned with architecture, design, and customer timelines without waiting for perfect information\nYou mentor junior engineers by showing them how to think about verification strategy, not just how to write a test, and you make the team around you better\nThe Team You'll Be Part Of\nYou will join a team of highly skilled verification engineers responsible for developing and verifying industry-leading Interface IP solutions. Working alongside experts in architecture, design, and verification, you will tackle some of the semiconductor industry's most challenging technical problems while contributing to products deployed worldwide.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Layout Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-08-24", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25011289", "is_hardware": true, "platform": "oracle", "jd_text": "Roles and responsibilities:\n\nFrame the layout schedule, effort estimation, risk and mitigation plan of layout activities for all layout engineers in the project\n\nWork closely with designers to understand the architecture and key requirements for the IC\n\nStrike right balance of area, performance and schedule during layout development by collaborating with design, packaging and process teams\n\nWork closely with Process development team to carry out PDK, P-cell and Design rule updates\n\nWork closely with Packaging engineer to develop custom lead-frames for various packages \n\nAnalysis and closure of Electro Migration, Thermal gradients, ESD/LU performance and layout parasitic\n\nRoutinely develop test vehicles for new process & package technology development\n\nMentor and guide junior layout engineers/contract engineers, review their work and provide feedback to meet the quality and schedule norms \n\nResponsible for the final layout which meets the design expectations and layout checklist.\n\nIdentify improvements needed in process/ quality/ cycle time and take up necessary initiatives\n\nQualifications\nKnowledge and skills:\n\nFull chip layout experience from definition through release of IC to production\n\nStrong LVS, DRC, ERC, and antenna debug skills\n\nProficient in analog and mixed-signal layout techniques and verification process including Device Matching, Power Bus design, avoiding Cross-talk, ESD/LU protection techniques\n\nGood understanding about all layout parasitics (R, C, diodes, BJTs)\n\nGood understanding of device physics and semiconductor fabrication process\n\nMust have worked on some of the Technologies like: 40nm, 65nm, 90nm, 130nm, 180nm, BiCMOS, BCD\n\nShould be well versed with tools such as Virtuoso XL/Assura /PVS/Voltas\n\nAbility to quickly ramp up on new tools/ process and mentor LEs\n\nExperience in automation/ SKILL coding for reducing cycle time/ quality checks will be an added advantage\n\nRequires excellent teamwork, good communication, strong problem-solving and documentation skills.\n\nStrong time management skills for on-time project delivery\n\nAbility to take initiatives and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Program Management Engineering Lead", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-08-24", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25011681", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n Texas Instruments (TI) is looking for an energetic, service minded leader, who enjoys helping others to succeed by providing team members and clients with motivation and support in a positive and professional work environment as a Program Management Engineer. We are seeking a highly motivated individual who will challenge teammates to achieve flawless execution goals, while maintaining strong working relationships. Success in this role is measured by the ability to grow the number of new products and drive the forecasted return on investment.\n\nResponsibilities include:\n\nLead a cross functional team on the execution of releasing new products and ensuring successful return on investment for every development; the team consists of Design, Marketing, Systems& Applications, Validation, Product& Test Engineering, Firmware/Software Engineering, Manufacturing, Field, and Quality\n\nWork with wafer fabrication, assembly& test sites to guarantee schedule, cost and quality\n\nPlan the project using MS Project from Assess Opportunity Phase to Release to Market and is responsible to make sure the project comes in on budget\n\nProvide clear direction to both, team and external support organizations like device fabrication and assembly and test sites\n\nDrive and motivate all team members critical to the flawless execution of each product and project\n\nProvide weekly and monthly updates to senior management on status of projects, explaining the issues facing a project\n\nInteract with customers in support of project status, key milestones, and deliveries. This includes samples deliveries, special work requests, wafer lot starts and reliability tests\n\nPerform product reliability and characterization of integrated circuits to ensure they meet the product requirement specifications and manufacturing requirements\n\nWork with failure analysis (FA) to determine root cause of any reliability and qualification failures\n\nMaintain thorough and up-to-date project schedules with all related milestones\n\nDevelop and implement Qualification plans\n\nCommunicate weekly to management on status of each project\n\nEffectively coordinate material logistics and shipment/assembly/test prioritization\n\nMaintain Galileo system per new product development guidelines\n\nSuccess will be measured by the ability to grow the number of new products and drive the forecasted return on investment.\n\nQualifications\nMinimum requirements:\nMasters in Electrical Engineering, Mechanical Engineering or related engineering degree\n10+ years of experience with project engineering/management experience on highly complex products/projects\nProven leadership capabilities in leading multifaceted global organizations\nSuccessful proven track record in indirect management and influence\nPreferred qualifications:\nAbility to manage multiple projects simultaneously, and set realistic plans based on required tasks with available resources\nAbility to effectively coordinate and lead global development teams on projects that include design, silicon fabrications, production test development, qualification and production ramp; Programs will be driven out of multiple global locations\nAbility to provide clear direction to both internal teams and external support organizations like device fabrication and assembly sites\nKnowledge of device packaging and wafer fabrication process\nKnowledge of reliability requirements and tri-temp characterization methodology using statistical analysis\nAbility to work in a team environment and understand cross-functional team dynamics\nAbility to work with global customers to align project schedules with customers' key milestones\nDemonstrated strong analytical and problem solving skills\nStrong verbal and written communication skills\nAbility to work in teams and collaborate effectively with people in different functions\nStrong time management skills that enable on-time project delivery\nDemonstrated ability to build strong, influential relationships\nAbility to work effectively in a fast-paced and rapidly changing environment\nAbility to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Staff Interface IP Verification Engineer (Pre-Silicon)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-24", "url": "https://careers.synopsys.com/job/bengaluru/staff-interface-ip-verification-engineer-pre-silicon/44408/99675054240", "is_hardware": true, "platform": "talentbrew", "jd_text": "Staff Interface IP Verification Engineer (Pre-Silicon)We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years verifying silicon that has to actually work, not just pass regression, actually work, in production systems where a protocol violation or a corner case bug can cost a customer months of schedule and millions in respins. You know that the difference between IP that ships clean and IP that comes back with errata is usually a testbench decision made six months earlier, and you are the kind of engineer who catches that gap before tapeout.\nYou are comfortable moving between PCIe link training sequences, CXL cache coherency protocols, and DDR timing constraints without losing sight of what you are actually building: reusable verification environments that have to scale across product families and customer use cases. You do not need a perfect spec to get started. You read between the lines, ask the right questions of architects, and build coverage models that reflect real-world integration scenarios, not just checklist compliance.\nDebugging energizes you. Not because it is heroic, but because finding the root cause of a multi-layer protocol issue and fixing it upstream makes the difference for every team that integrates your IP downstream. You have opinions on what good UVM architecture looks like, and you are not afraid to push back when a verification plan misses the actual risk.\nAt Synopsys, you will work on Interface IP that powers AI accelerators, data centers, and next-generation SoCs used by the world's leading semiconductor companies. The team is global, the protocols are real, and what you verify will matter.\nWhat You'll Be Doing\nOwn end-to-end verification of complex Interface IP including PCIe, CXL, DDR, and Ethernet, from architecture review through signoff and customer release\nArchitect and build scalable UVM-based verification environments and reusable verification IP components that work across multiple product variants and customer configurations\nDefine verification strategies and detailed test plans by analyzing specifications, identifying protocol corner cases, and mapping coverage goals to real integration risks\nDevelop constrained-random, coverage-driven testbenches using SystemVerilog and UVM, with a focus on protocol compliance, performance validation, and system-level interaction scenarios\nDrive functional coverage closure by analyzing gaps, writing targeted tests, and working with design teams to ensure all architectural intent is verified before tapeout\nDebug complex RTL, protocol, and system-level issues across simulators like VCS or ModelSim, using waveform analysis, assertions, and protocol monitors to isolate root cause\nMentor verification engineers on UVM methodology, coverage techniques, and debugging approaches while contributing to verification infrastructure and process improvements across the team\nThe Impact You Will Have\nYour verification work will directly determine the quality and reliability of Interface IP integrated into AI platforms, hyperscale data centers, and high-performance computing systems used worldwide\nYou will reduce customer-found bugs and post-silicon errata by catching protocol violations, timing issues, and integration corner cases during pre-silicon verification\nYour reusable verification IP and testbench architectures will accelerate verification timelines for future product generations and reduce bring-up time for derivative designs\nYou will influence verification methodology and best practices across the Interface IP engineering organization, raising the bar for coverage rigor and automation efficiency\nYour coverage models and test strategies will become the reference standard for how complex protocols like PCIe Gen6, CXL 3.0, and DDR5 are verified at Synopsys\nYou will help develop the next generation of verification engineers by sharing expertise in protocol verification, UVM architecture, and systematic debugging techniques\nYour technical leadership will drive successful product releases that meet the quality expectations of the world's most demanding semiconductor customers\nWhat You'll Need\nBachelor's or Master's in Electrical Engineering or Computer Engineering with at least 5 years of hands-on ASIC or SoC verification experience\nDeep expertise in SystemVerilog and UVM methodologies, including building constrained-random testbenches, functional coverage models, and reusable verification components\nStrong protocol knowledge in one or more of PCIe, CXL, DDR memory interfaces, or Ethernet, with demonstrated experience verifying protocol compliance and system-level interactions\nProven experience developing coverage-driven verification environments and driving coverage closure on complex designs through tapeout\nStrong debugging skills across RTL, verification infrastructure, and protocol layers, with experience using industry-standard simulators such as VCS, ModelSim, Xcelium, or Questa\nExperience with verification IP development, assertion-based verification, or formal methodologies is a strong plus\nKnowledge of modern SoC architectures, high-speed SerDes interfaces, or cache coherency protocols is a plus\nWho You Are\nYou can walk into a spec review, spot the ambiguities that will become verification holes three months later, and ask the questions that force clarity before RTL is written\nYou write UVM code that other engineers can actually read and extend, you care about class hierarchy, encapsulation, and making your testbench maintainable for the team that inherits it\nYou do not declare victory when regression passes, you dig into coverage reports, find the scenarios you are not hitting, and write the tests that close the gaps before someone else finds them in silicon\nYou can explain a complex protocol deadlock scenario to a design engineer in two sentences without losing the technical nuance, and you know when to escalate an issue versus when to debug it yourself\nYou work effectively across global teams and time zones, keeping verification plans aligned with architecture, design, and customer timelines without waiting for perfect information\nYou mentor junior engineers by showing them how to think about verification strategy, not just how to write a test, and you make the team around you better\nThe Team You'll Be Part Of\nYou will join a team of highly skilled verification engineers responsible for developing and verifying industry-leading Interface IP solutions. Working alongside experts in architecture, design, and verification, you will tackle some of the semiconductor industry's most challenging technical problems while contributing to products deployed worldwide.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior Staff- Interface IP Verification (Pre-Silicon- PCIe/CXL/DDR/Ethernet)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-24", "url": "https://careers.synopsys.com/job/bengaluru/senior-staff-interface-ip-verification-pre-silicon-pcie-cxl-ddr-ethernet/44408/99675054352", "is_hardware": true, "platform": "talentbrew", "jd_text": "Senior Staff- Interface IP Verification (Pre-Silicon- PCIe/CXL/DDR/Ethernet)\n \nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years verifying silicon that ships into data centers, AI accelerators, and high-performance systems where failure is not an option. The protocols you verify, PCIe, CXL, DDR, Ethernet, are not abstract specs to you. They are living, breathing systems with corner cases that only reveal themselves at 3 a.m. during a regression run, and you are the engineer who finds them before tape-out.\nYou think in layers. You can debug a failing assertion in the UVM environment, trace it back to an RTL timing issue, and then connect it to a protocol compliance gap, all without losing the thread of what actually broke. When someone says 'coverage is at 95%,' you ask which 5% is missing and whether it matters.\nYou do not wait for perfect documentation. Specs are incomplete, architectures evolve, and you have learned to work with what you have, ask the right questions, and build verification environments that adapt as the design matures. You have strong opinions on what makes a testbench reusable versus one that becomes technical debt, and you are not afraid to push back when a verification strategy does not account for real-world integration scenarios.\nAt Synopsys, you will verify Interface IP that powers the semiconductor industry's most critical applications, and the team you work with will expect you to lead, not just execute.\nWhat You'll Be Doing\nOwn end-to-end verification of Interface IP blocks including PCIe, CXL, DDR, and Ethernet, from architecture review through silicon signoff\nBuild and evolve UVM-based verification environments that are reusable across product lines and scalable for future protocol generations\nDefine verification strategies and test plans that account for protocol compliance, performance corner cases, and system-level integration scenarios\nDevelop constrained-random, coverage-driven test scenarios using SystemVerilog and UVM, targeting functional coverage closure and signoff quality\nDebug complex multi-layer issues spanning RTL logic, protocol state machines, timing, and testbench infrastructure using VCS or equivalent simulators\nCollaborate with architecture, design, firmware, and systems teams to identify and resolve issues early in the development cycle\nMentor verification engineers on UVM methodology, coverage analysis, debugging techniques, and verification best practices\nThe Impact You Will Have\nYour verification work will directly determine the quality and reliability of IP integrated into AI platforms, cloud infrastructure, and automotive systems used globally\nThe testbenches and verification IP you build will be reused across multiple product generations, multiplying your impact across the organization\nYour coverage strategies and signoff criteria will set the standard for verification quality across the Interface IP portfolio\nThe protocol bugs you catch pre-silicon will prevent costly respins and delays for customers building next-generation SoCs\nYour technical leadership will shape verification methodology improvements that raise the bar for the entire engineering team\nThe mentorship you provide will accelerate the growth of engineers who will carry forward the verification practices you help establish\nYour collaboration with architecture and design teams will influence early design decisions that make verification more efficient and products more robust\nWhat You'll Need\nBachelor's or Master's in Electrical Engineering or Computer Engineering with 8+ years of hands-on ASIC or SoC verification experience\nDeep expertise in SystemVerilog and UVM methodology, with a track record of building scalable verification environments from the ground up\nStrong protocol knowledge in at least one of PCIe, CXL, DDR, or Ethernet, with the ability to read specs and translate them into verification requirements\nProven experience developing constrained-random and coverage-driven verification solutions that achieve functional signoff\nSolid debugging skills across RTL, verification infrastructure, and protocol compliance, with experience using industry-standard simulators like VCS or ModelSim\nExperience with verification IP development, assertion-based verification, or formal methods is a strong plus\nKnowledge of modern SoC architectures and high-speed communication interfaces is a plus\nWho You Are\nYou can walk into a spec review, identify the verification-critical corner cases that are not explicitly called out, and build a test plan that covers them\nWhen a regression fails at 2 a.m. before a milestone, you are the engineer who triages the root cause, determines if it is a real bug or a testbench issue, and has a fix ready by morning standup\nYou know the difference between coverage that looks good on a dashboard and coverage that actually means the design is verified, and you are willing to have the hard conversation when the two do not align\nYou can explain a complex protocol violation to a design engineer in a way that makes the fix obvious, and then turn around and present the same issue to an architect in terms of system-level impact\nYou are comfortable leading technical discussions with senior engineers and architects, even when your point of view challenges the current plan\nYou see mentorship as part of the job, not an extra task, and you make time to help less experienced engineers understand not just what to do, but why it matters\nThe Team You'll Be Part Of\nYou will join a team of highly skilled verification engineers responsible for developing and verifying industry-leading Interface IP solutions. Working alongside experts in architecture, design, and verification, you will tackle some of the semiconductor industry's most challenging technical problems while contributing to products deployed worldwide. The team operates globally, collaborates across time zones, and values technical depth, ownership, and the kind of problem-solving that makes complex IP actually work in customer silicon.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-24", "url": "https://careers.synopsys.com/job/bengaluru/senior-staff-interface-ip-verification-engineer-pre-silicon-pcie-cxl-ddr-ethernet/44408/99675054320", "is_hardware": true, "platform": "talentbrew", "jd_text": "Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet)\n \nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years verifying silicon that ships into data centers, AI accelerators, and high-performance systems where failure is not an option. The protocols you verify, PCIe, CXL, DDR, Ethernet, are not abstract specs to you. They are living, breathing systems with corner cases that only reveal themselves at 3 a.m. during a regression run, and you are the engineer who finds them before tape-out.\nYou think in layers. You can debug a failing assertion in the UVM environment, trace it back to an RTL timing issue, and then connect it to a protocol compliance gap, all without losing the thread of what actually broke. When someone says 'coverage is at 95%,' you ask which 5% is missing and whether it matters.\nYou do not wait for perfect documentation. Specs are incomplete, architectures evolve, and you have learned to work with what you have, ask the right questions, and build verification environments that adapt as the design matures. You have strong opinions on what makes a testbench reusable versus one that becomes technical debt, and you are not afraid to push back when a verification strategy does not account for real-world integration scenarios.\nAt Synopsys, you will verify Interface IP that powers the semiconductor industry's most critical applications, and the team you work with will expect you to lead, not just execute.\nWhat You'll Be Doing\nOwn end-to-end verification of Interface IP blocks including PCIe, CXL, DDR, and Ethernet, from architecture review through silicon signoff\nBuild and evolve UVM-based verification environments that are reusable across product lines and scalable for future protocol generations\nDefine verification strategies and test plans that account for protocol compliance, performance corner cases, and system-level integration scenarios\nDevelop constrained-random, coverage-driven test scenarios using SystemVerilog and UVM, targeting functional coverage closure and signoff quality\nDebug complex multi-layer issues spanning RTL logic, protocol state machines, timing, and testbench infrastructure using VCS or equivalent simulators\nCollaborate with architecture, design, firmware, and systems teams to identify and resolve issues early in the development cycle\nMentor verification engineers on UVM methodology, coverage analysis, debugging techniques, and verification best practices\nThe Impact You Will Have\nYour verification work will directly determine the quality and reliability of IP integrated into AI platforms, cloud infrastructure, and automotive systems used globally\nThe testbenches and verification IP you build will be reused across multiple product generations, multiplying your impact across the organization\nYour coverage strategies and signoff criteria will set the standard for verification quality across the Interface IP portfolio\nThe protocol bugs you catch pre-silicon will prevent costly respins and delays for customers building next-generation SoCs\nYour technical leadership will shape verification methodology improvements that raise the bar for the entire engineering team\nThe mentorship you provide will accelerate the growth of engineers who will carry forward the verification practices you help establish\nYour collaboration with architecture and design teams will influence early design decisions that make verification more efficient and products more robust\nWhat You'll Need\nBachelor's or Master's in Electrical Engineering or Computer Engineering with 8+ years of hands-on ASIC or SoC verification experience\nDeep expertise in SystemVerilog and UVM methodology, with a track record of building scalable verification environments from the ground up\nStrong protocol knowledge in at least one of PCIe, CXL, DDR, or Ethernet, with the ability to read specs and translate them into verification requirements\nProven experience developing constrained-random and coverage-driven verification solutions that achieve functional signoff\nSolid debugging skills across RTL, verification infrastructure, and protocol compliance, with experience using industry-standard simulators like VCS or ModelSim\nExperience with verification IP development, assertion-based verification, or formal methods is a strong plus\nKnowledge of modern SoC architectures and high-speed communication interfaces is a plus\nWho You Are\nYou can walk into a spec review, identify the verification-critical corner cases that are not explicitly called out, and build a test plan that covers them\nWhen a regression fails at 2 a.m. before a milestone, you are the engineer who triages the root cause, determines if it is a real bug or a testbench issue, and has a fix ready by morning standup\nYou know the difference between coverage that looks good on a dashboard and coverage that actually means the design is verified, and you are willing to have the hard conversation when the two do not align\nYou can explain a complex protocol violation to a design engineer in a way that makes the fix obvious, and then turn around and present the same issue to an architect in terms of system-level impact\nYou are comfortable leading technical discussions with senior engineers and architects, even when your point of view challenges the current plan\nYou see mentorship as part of the job, not an extra task, and you make time to help less experienced engineers understand not just what to do, but why it matters\nThe Team You'll Be Part Of\nYou will join a team of highly skilled verification engineers responsible for developing and verifying industry-leading Interface IP solutions. Working alongside experts in architecture, design, and verification, you will tackle some of the semiconductor industry's most challenging technical problems while contributing to products deployed worldwide. The team operates globally, collaborates across time zones, and values technical depth, ownership, and the kind of problem-solving that makes complex IP actually work in customer silicon.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Electrical Engineer 8-12 yrs", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2026-08-24", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/UL508A-Electrical-Engineer_R2626589", "is_hardware": true, "platform": "workday", "jd_text": "Who We Are\n\nApplied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI and accelerating the commercialization of next-generation semiconductor chips. Join us and push the boundaries of materials science and engineering in a company at the foundation of the electronics industry. The work we do together advances the world’s technology.\n\nWhat We Offer\n\nLocation:\nBangalore,IND\nYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. \n\nAt Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. \n \n \nAs an Electrical Engineer, you are responsible for designing, modifying, and troubleshooting electrical or electronic engineering assemblies, layouts, schematics, and drawings to advance the equipment that supports our technology. Using your technical experience and critical thinking skills, you will perform engineering analysis, generate test reports, develop innovative solutions, and create documentation for product releases. You will also coordinate the procurement and assembly of components, identify sources of critical parts, and resolve technical issues to ensure peak performance. \n \nKey Responsibilities\nDesign or modify electrical/electronic engineering assemblies, layouts/schematics and/or detailed drawings/specifications of difficult scope\nProblem identification and troubleshooting a variety of complex electrical problems with limited supervision\nDefine, coordinate, perform and generate engineering test reports with limited supervision\nPerform engineering analysis of difficult scope with limited supervision\nTechnically lead and/or executes engineering projects, including development of key suppliers\nImplements concepts for variety of complex product issues and electrical solutions of difficult scope\nGenerate electrical product specifications\nSpecify and review engineering documentation\n\nFunctional Knowledge\nDemonstrates conceptual and practical expertise in own discipline and basic knowledge of related disciplines\n\nBusiness Expertise\nHas knowledge of best practices and how own area integrates with others; is aware of the competition and the factors that differentiate them in the market\n\nLeadership\nActs as a resource for colleagues with less experience; may lead small projects with manageable risks and resource requirements\n\nProblem Solving\nSolves complex problems; takes a new perspective on existing solutions; exercises judgment based on the analysis of multiple sources of information\n\nImpact\nImpacts a range of customer, operational, project or service activities within own team and other related teams; works within broad guidelines and policies\n\nInterpersonal Skills\nExplains difficult or sensitive information; works to build consensus\n\nEducation & Experience\nBachelor's Degree in engineering with Electrical background and 8-10 years of experience\nAdditional Job Description\nElectrical Equipment design for any industries such as Process, Batch or manufacturing\nSelection of Switch gear, Protections circuit, sensors & Controllers\nIdentifying Safety interlocks & different system Safety requirements\nWorking knowledge of relevant standards i.e. NFPA70, NFPA79, Semi S2, S8, F47 and UL508A etc.\nUnderstanding or experience of working with power control designs and applications\nDemonstrated knowledge of working with major electrical components and ability to troubleshoot them when required\nBasics communication protocols  (RS232,RS485,ECAT,ENET)\n\nTools Knowledge\nE3S\nTeamcenter\n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nAssignee / Regular\nTravel:\nYes, 10% of the Time\nRelocation Eligible:\nYes\n\nApplied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "Physical Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-08-24", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Physical-Design-Engineer_JR0285863-1", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nIntel Central Engineering Group is seeking Physical Design Engineers to join our dynamic team and contribute to the development of cutting-edge custom IP and SoC designs for Intel products and Intel Custom ASIC Customers. In this role, you will play a pivotal part in translating RTL to GDS, enabling manufacturing-ready design databases that drive innovation in products.\n\nPerforms physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.\nConducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.\nAnalyzes results and makes recommendations to fix violations for current and future product architecture.\nPossesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.\nOptimizes design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.\n\nQualifications:\nMinimum Qualifications:\n- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 5+ Years of experience in Physical Design execution.\n- Master's degree with 3+ Years of experience in Physical Design execution.\n- Deep knowledge in RTL-to-GDS workflows, including synthesis, place and route, and static timing analysis.\n- Expertise in optimization techniques for power, performance, and area (PPA).\n- Hands-on experience with industry-standard EDA tools for physical design and verification.\n- Comprehensive knowledge of clock tree synthesis and low-power design techniques.\n- Experience with competitive timing, floor planning methodologies (TFM), and multi-power domain analysis.\n\nPreferred Qualifications:\n- Demonstrated ability to collaborate within cross-functional teams to achieve strategic design goals.\n- Strong critical thinking and problem-solving skills to manage complex design challenges.\n- Excellent communication and organizational abilities to coordinate across disciplines.\n- A passion for innovation and continuous improvement in design methodologies.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-24", "url": "https://careers.synopsys.com/job/bengaluru/senior-staff-interface-ip-verification-engineer-pre-silicon-pcie-cxl-ddr-ethernet/44408/99675054272", "is_hardware": true, "platform": "talentbrew", "jd_text": "Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet)\n \nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years verifying silicon that ships into data centers, AI accelerators, and high-performance systems where failure is not an option. The protocols you verify, PCIe, CXL, DDR, Ethernet, are not abstract specs to you. They are living, breathing systems with corner cases that only reveal themselves at 3 a.m. during a regression run, and you are the engineer who finds them before tape-out.\nYou think in layers. You can debug a failing assertion in the UVM environment, trace it back to an RTL timing issue, and then connect it to a protocol compliance gap, all without losing the thread of what actually broke. When someone says 'coverage is at 95%,' you ask which 5% is missing and whether it matters.\nYou do not wait for perfect documentation. Specs are incomplete, architectures evolve, and you have learned to work with what you have, ask the right questions, and build verification environments that adapt as the design matures. You have strong opinions on what makes a testbench reusable versus one that becomes technical debt, and you are not afraid to push back when a verification strategy does not account for real-world integration scenarios.\nAt Synopsys, you will verify Interface IP that powers the semiconductor industry's most critical applications, and the team you work with will expect you to lead, not just execute.\nWhat You'll Be Doing\nOwn end-to-end verification of Interface IP blocks including PCIe, CXL, DDR, and Ethernet, from architecture review through silicon signoff\nBuild and evolve UVM-based verification environments that are reusable across product lines and scalable for future protocol generations\nDefine verification strategies and test plans that account for protocol compliance, performance corner cases, and system-level integration scenarios\nDevelop constrained-random, coverage-driven test scenarios using SystemVerilog and UVM, targeting functional coverage closure and signoff quality\nDebug complex multi-layer issues spanning RTL logic, protocol state machines, timing, and testbench infrastructure using VCS or equivalent simulators\nCollaborate with architecture, design, firmware, and systems teams to identify and resolve issues early in the development cycle\nMentor verification engineers on UVM methodology, coverage analysis, debugging techniques, and verification best practices\nThe Impact You Will Have\nYour verification work will directly determine the quality and reliability of IP integrated into AI platforms, cloud infrastructure, and automotive systems used globally\nThe testbenches and verification IP you build will be reused across multiple product generations, multiplying your impact across the organization\nYour coverage strategies and signoff criteria will set the standard for verification quality across the Interface IP portfolio\nThe protocol bugs you catch pre-silicon will prevent costly respins and delays for customers building next-generation SoCs\nYour technical leadership will shape verification methodology improvements that raise the bar for the entire engineering team\nThe mentorship you provide will accelerate the growth of engineers who will carry forward the verification practices you help establish\nYour collaboration with architecture and design teams will influence early design decisions that make verification more efficient and products more robust\nWhat You'll Need\nBachelor's or Master's in Electrical Engineering or Computer Engineering with 8+ years of hands-on ASIC or SoC verification experience\nDeep expertise in SystemVerilog and UVM methodology, with a track record of building scalable verification environments from the ground up\nStrong protocol knowledge in at least one of PCIe, CXL, DDR, or Ethernet, with the ability to read specs and translate them into verification requirements\nProven experience developing constrained-random and coverage-driven verification solutions that achieve functional signoff\nSolid debugging skills across RTL, verification infrastructure, and protocol compliance, with experience using industry-standard simulators like VCS or ModelSim\nExperience with verification IP development, assertion-based verification, or formal methods is a strong plus\nKnowledge of modern SoC architectures and high-speed communication interfaces is a plus\nWho You Are\nYou can walk into a spec review, identify the verification-critical corner cases that are not explicitly called out, and build a test plan that covers them\nWhen a regression fails at 2 a.m. before a milestone, you are the engineer who triages the root cause, determines if it is a real bug or a testbench issue, and has a fix ready by morning standup\nYou know the difference between coverage that looks good on a dashboard and coverage that actually means the design is verified, and you are willing to have the hard conversation when the two do not align\nYou can explain a complex protocol violation to a design engineer in a way that makes the fix obvious, and then turn around and present the same issue to an architect in terms of system-level impact\nYou are comfortable leading technical discussions with senior engineers and architects, even when your point of view challenges the current plan\nYou see mentorship as part of the job, not an extra task, and you make time to help less experienced engineers understand not just what to do, but why it matters\nThe Team You'll Be Part Of\nYou will join a team of highly skilled verification engineers responsible for developing and verifying industry-leading Interface IP solutions. Working alongside experts in architecture, design, and verification, you will tackle some of the semiconductor industry's most challenging technical problems while contributing to products deployed worldwide. The team operates globally, collaborates across time zones, and values technical depth, ownership, and the kind of problem-solving that makes complex IP actually work in customer silicon.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "ASIC Design Engineer - RTL and Circuits", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-24", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/ASIC-Design-Engineer---RTL-and-Circuits_JR2023989", "is_hardware": true, "platform": "workday", "jd_text": "We are now looking for a motivated ASIC Design Engineer to join our dynamic and growing team in our Circuit Solutions Group! NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.\n\nNVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nWhat you'll be doing:\nCollaborate with cross-functional teams to define system-level architecture of mixed-signal chips for power delivery and power management solutions.\n\nDefine micro-architecture and specifications of digital IP blocks to improve the power and performance of NVIDIA’s next generation GPUs\n\nPartner with RTL and Design Verification engineers to ensure delivery meets performance and quality expectations.\n\nWork with front-end teams to overlook correctness of the design (Lint/NA/CDC/Synthesis/DFT/LEC/STA)\n\nPartner and work with back-end team until chip tape-out.\n\nWork with firmware teams to define program flow and interface with digital IPs.\n\nCraft and develop behavioral models in RTL for mixed-signal blocks.\n\nWhat we need to see:\nB.S. or MS degree in Electrical Engineering (or equivalent experience)\n\n1+ years of proven experience and a background in logic design, Verilog and/or System-Verilog with a deep understanding of physical design and VLSI\n\nExperience with RTL development, Custom Digital Design, and Behavioral Circuit Modeling for mixed-signal blocks.\n\nWell-versed with Verilog/SystemVerilog\n\nStrong familiarity and experience with all stages of ASIC design flow including front end design and verification, DFT, and timing analysis\n\nStrong team player with outstanding interpersonal skills.\n\nWays to stand out from the crowd:\nStrong knowledge or work experience in Mixed signal and custom designed IPs solutions.\n\nExperience with industry standard communication standards such as JTAG, I2C, SPMI, etc.\n\nFamiliarity with power management IPs.\n\nUnderstanding of firmware and embedded controllers.\n\nWhether you’re an experienced professional or a recent graduate, there’s a place for you in our inclusive environment. Together, let’s push the boundaries of innovation and make a lasting impact on the world. Make the choice, join our diverse team today!\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Physical Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-08-24", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Physical-Design-Engineer_JR0285864-1", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nIntel Central Engineering Group is seeking Physical Design Engineers to join our dynamic team and contribute to the development of cutting-edge custom IP and SoC designs for Intel products and Intel Custom ASIC Customers. In this role, you will play a pivotal part in translating RTL to GDS, enabling manufacturing-ready design databases that drive innovation in products.\n\nPerforms physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.\nAnalyzes results and makes recommendations to fix violations for current and future product architecture.\nPossesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.\nOptimizes design to improve product level parameters such as power, frequency, and area.\nParticipates in the development and improvement of physical design methodologies and flow automation.\n\nQualifications:\nMinimum Qualifications:\n- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field with 2+ Years of experience in Physical Design execution.\n- Deep knowledge in RTL-to-GDS workflows, including synthesis, place and route, and static timing analysis.\n- Expertise in optimization techniques for power, performance, and area (PPA).\n- Hands-on experience with industry-standard EDA tools for physical design and verification.\n- Comprehensive knowledge of clock tree synthesis and low-power design techniques.\n- Experience with competitive timing, floor planning methodologies (TFM), and multi-power domain analysis.\n\nPreferred Qualifications:\n- Demonstrated ability to collaborate within cross-functional teams to achieve strategic design goals.\n- Strong critical thinking and problem-solving skills to manage complex design challenges.\n- Excellent communication and organizational abilities to coordinate across disciplines.\n- A passion for innovation and continuous improvement in design methodologies.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Physical Design Engineer ICE", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-08-24", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Physical-Design-Engineer-ICE_JR0286430", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nJoin our team as a Physical Design Engineer, where you'll contribute to creating advanced chip designs pivotal to Intel's innovation. In this role, you'll design and verify critical elements of chip layouts, ensuring accuracy and functionality across cell, block-level, and full-chip designs. Your work will have a direct impact on delivering high-performance solutions that drive Intel's technological advancements.\n\nBusiness group\nYou will be part of Intel's technology development organization, focused on delivering cutting-edge chip designs that support Intel's broader mission of shaping the future of computing. This group is dedicated to enhancing design methodologies and tools, enabling efficiency and innovation in chip design and verification processes.\n\nKey Responsibilities\n- Create and verify cell and block-level semi-custom layouts, including floor plans, abstract view generation, and schematic-to-layout verification.\n- Conduct reliability verification, debug processes, and parasitic extraction to ensure design integrity.\n- Utilize auto-place and route algorithms, custom polygon editing, and floor planning techniques for chip assembly.\n- Execute full-chip assembly, packaging, and verification processes to meet project timelines and quality standards.\n- Troubleshoot complex design issues and proactively implement solutions.\n- Schedule, staff, and execute chip development projects, ensuring adherence to methodologies and flow developments.\n\nQualifications:\nMinimum Qualifications\n- Bachelor's degree in Electronics, Electrical Engineering, or a related field.\n- Basic understanding of layout design and verification processes.\n- Familiarity with ICC2 tools and methodologies.\n- Demonstrated skills in TCL scripting, with practical application experience preferred.\n\nPreferred Qualifications\n- Strong problem-solving abilities and attention to detail in design verification.\n- Effective communication and collaboration skills within cross-functional teams.\n- Enthusiasm for staying updated on industry trends in physical design and chip development.\nEmbark on a rewarding journey with Intel, where your skills and creativity will contribute to world-class technology solutions.\n          \n\nJob Type:\nIntel Contract Employee\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Packaging Associate, IN Packaging", "company": "Amazon", "location": "Bengaluru, Karnataka, IND", "date_posted": "2026-08-24", "url": "https://www.amazon.jobs/en/jobs/10511697/packaging-associate-in-packaging", "is_hardware": true, "platform": "amazon", "jd_text": "At Amazon, we strive to be Earth’s most customer-centric company where people can find and discover anything they want to buy online. We hire the world’s brightest minds, offering them an environment in which they can relentlessly improve the experience for customers. Innovation and creativity are built into the DNA of the company and are encouraged at all levels of employment. Every day we solve complex technical and business problems with ingenuity and simplicity. We’re making history and the good news is we’ve only just begun.\n\nKey roles and responsibilities will include:\n1. Perform visual testing against attributes for PWP/any other workstream in Imaging team.\n2. Responsible for achieving the metric goals for imaging team.\n3. Identify and manage small-scale process improvement opportunities by performing root cause analysis.\n\nSkills:\n•\tExcellent analytical and statistical skills\n•\tProblem solving through data driven approach\n•\t0-1 year experience and process understanding of AMZ\n•\tExcellent written & verbal communication skills including writing skills in Word, Power point, and Excel\n•\tBachelor’s degree or higher.\n•\tAbility to relocate to Bangalore as per the requirement.\nJob Location- Bangalore, Karnataka\n\nKey job responsibilities\n1. Perform visual testing against attributes for PWP/any other workstream in Imaging team.\n2. Responsible for achieving the metric goals for imaging team.\n3. Identify and manage small-scale process improvement opportunities by performing root cause analysis.\n\nAbout the team\nWe are a high performance team working closest with the customer.\n\nBasic qualifications\n- Bachelor's degree, or Bachelor's degree or above", "jd_status": "source_unavailable"}, {"title": "RTL Design Lead", "company": "MediaTek", "location": "Bangalore", "date_posted": "2026-08-23T16:00:00+00:00", "url": "https://careers.mediatek.com/en/jobs/MTB120260824001", "is_hardware": true, "platform": "mediatek", "jd_text": "Design Lead works with hardware engineering teams to build complex chips, System-on-Chips (SoCs), and IP/Sub-system blocks.\nGuides microarchitecture definition, RTL design, verification, and physical implementation from conception through tape-out, balancing power, performance, area, and schedule goals.\n\nKey Responsibilities\n\n• Execution & Delivery: Drive end-to-end design development of IP/Sub-system blocks and SoCs to meet the Performance, Area, Power and Schedule targets.\n• Team Leadership: Manage, mentor, and set goals for a team of digital engineers involved in design, synthesis, and timing.\n• PPA Optimization: Oversee design reviews to optimize Power, Performance, and Area (PPA) metrics.\n• Cross-Functional Collaboration: Partner with architecture, verification, and physical design teams.\n• Sign-off & Debug: Drive resolution on complex bugs, logic issues, and sign-off checks.\n\nCore Technical Skills\n\n• Design Languages: Advanced proficiency in Verilog, System-Verilog, and scripting tools like Python or Perl.\n• Architecture Knowledge: Familiarity with ARM or RISC-V processors, bus protocols (AXI/AHB), and high-speed interfaces (PCIe, USB, DDR).\n• Sign-off Methodologies: Experience with Static Timing Analysis (STA), Clock Domain Crossing (CDC), and Logical Equivalence Checking (LEC).", "jd_status": "stored"}, {"title": "WIFI PHY Senior Design Verification Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-22T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720222340", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nQCT's Bangalore Wireless R&D (WRD) HW team in Bangalore is looking for experienced Wireless HW design verification engineers to work on Qualcomm’s best in class chipsets for mobile phones, wearables and IOT . Candidate will be working with ASIC designs on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies.  In this role of WRD Verification Engineer, you will be verifying Wifi and/or Modem from both TX and RX perspective.\n\nThe responsibilities will majorly include:\nUnderstanding of Wireless systems PHY TX and RX design paths, Algorithms that control the various aspects of wireless systems.\n\nOwn complete IP/Block/SS level DV.\n\nOwn end to end DV tasks from design analysis, Verification Plan development , Coding Test bench and test cases, write assertions, running simulations and achieving all coverage goals.\n\nExplore innovative DV methodologies (formal, simulation and emulation based) to continuously improve the quality and efficiency of test benches.\n\nSuccessful candidate will be required to collaborate with worldwide design, architecture teams and other stake holder to achieve all project goals. Hence, strong communication skills are a must.\n\nSkills/Experience:\n2-4 years of strong experience in design verification\n\nStrong knowledge of System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodology\n\nProven experience of building or maintaining a medium to complex SV/UVM environments\n\nProven experience of writing efficient constraint random tests\n\nPrior Experience in verifying WIFI, Modem PHY layer is a strongly desirable.\n\nStrong debugging and analytical skills and independent problem-solving ability\n\nProficient in debugging RTL/TB issues using Verdi or similar tools\n\nExperience in formal / static verification methodologies will be a plus\n\nGood understanding of Wireless protocols, Modem/Wifi Standards is a plus\n\nExperience with Power Aware verification, GLS, and scripting languages such as Perl, Python is a plus.\n\nExperience in formal / static verification methodologies will be a plus\n\nPreferred Qualifications:\nUnderstanding of Wireless protocols, Modem/Wifi Standards\n\nExperience in IP verification of DSP related HW blocks.\n\nKnowledge on scripting languages such as Perl and(or) Python\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "DFT  Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-08-21T10:55:00+00:00", "url": "https://global-external-amd.icims.com/jobs/89032/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. MTS SILICON DESIGN ENGINEER    As key member of the AMD EPYC Server team, the successful candidate will play a significant role in ensuring the quality of next generation EPYC Server SoCs through structural DFT, Automatic Test Pattern Generation (ATPG) and Logic Built-In Self-Test (LBIST) techniques. Primary responsibilities will include Working closely with the Architecture team to understand the DFT Architecture and implementation Interfacing with the Design teams to ensure DFT design rules and guidelines are met Working with the PD team to ensure to correct DFT implementation and closing timing Generating high quality manufacturing test patterns for stuck-at, transition fault models and through the use of on-chip test compression techniques. Simulating and verifying the ATPG and LBIST patterns Analyzing and working with the different stakeholders to get the required design changes in to get the maximum ATPG coverage Working with the Product engineering teams on the delivery of manufacturing test patterns. Working with the Product Engineering teams on Silicon bring-up and debugs Developing, enhancing and maintaining scripts as necessary Requirements: Exposure to DFT Architecture and Design Good working knowledge of ATPG tools (Mentor TK) Exposure to Static timing analysis & Timing closure is required. Excellent hands-on debug skills and scripting skills are critical. Must have good communication skills and the ability to work in a worldwide team environment. Qualifications: B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering with 9+ years of DFT experience #LI-AA1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Staff Engineer, Analog Design (Power & Analog ICs)", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-21T09:50:07.351000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000144728900-senior-staff-engineer-analog-design-power-analog-ics-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking a Senior Staff Analog Design Engineer with deep expertise in power management, analog, and mixed-signal IC development. This is a senior individual-contributor role requiring ownership of complex analog IP, subsystem architecture, converter design, and silicon execution from concept through production. \nThe successful candidate will lead the design of key analog and power-management functions including switching converters, LDOs, charge pumps, references, sensors, protection circuits, data converters, and signal-conditioning blocks used across Renesas power and analog products. The role requires strong technical judgment, architecture ownership, cross-functional collaboration, and the ability to drive first-silicon success. \nYou will be expected to operate independently, resolve ambiguous technical challenges, establish design methodology, mentor engineers, and influence product architecture and execution through deep technical expertise. \nResponsibilities:  \nAnalog Architecture & Circuit Design \nDefine and own the architecture of complex analog and power-management IP used in PMICs, converters, battery-management products, and mixed-signal devices. \nDesign and own blocks such as positive and negative charge pumps, buck converters, source-sink LDOs, ultra-low-power oscillators, temperature sensors, current-sense circuits, SAR ADCs, voltage and current references, op-amps, comparators, analog buffers, level shifters, and protection circuits. \nTranslate product and top-level chip requirements into detailed block specifications, architecture decisions, circuit implementations, and verification plans. \nPerform block-level error budgeting and system-level trade-off analysis across performance, area, power, cost, robustness, and manufacturability. \nConverter & Control Loop Design \nIndependently architect and design complete switching converters including buck, boost, and buck-boost converters, as well as LDOs and point-of-load devices. \nDemonstrate deep understanding of analog feedback loops, control-loop stability, compensation implementation, and trade-offs across compensation strategies. \nEvaluate control architectures such as constant-frequency, constant-on-time, constant-off-time, voltage-mode, and current-mode control, and select the appropriate approach for product requirements. \nEnsure robust converter performance across process, voltage, temperature, load, line, startup, shutdown, and fault conditions. \nVerification, Silicon & Production Support \nDrive analog verification and simulation strategy across schematic, extracted, pre-layout, and post-layout environments. \nOptimize simulation setups based on speed, convergence, accuracy, and parasitic conditions, and resolve simulator, model, and tool-related challenges. \nOwn or support silicon validation, characterization, debug, qualification, production readiness, and root-cause analysis for silicon issues. \nCollaborate with product engineering, test engineering, applications, reliability, and manufacturing teams across the complete product lifecycle. \nPhysical Design, Reliability & Sign-off \nCollaborate closely with layout engineers from floor planning through chip-top completion, extraction, verification, and tape-out. \nGuide layout trade-offs related to matching, noise, parasitics, isolation, current density, electromigration, IR drop, thermal behavior, and high-current operation. \nDemonstrate strong understanding of ESD, latch-up, I/O-ring protection, and other IC-level reliability requirements. \nReview physical implementation and extracted performance to ensure the design meets electrical, yield, reliability, and manufacturability targets. \nTechnical Leadership & Methodology \nDrive analog design methodology, checklists, design reviews, reusable IP practices, and quality standards from concept through silicon success. \nLead technical reviews and provide clear architecture, design, verification, risk, and sign-off assessments to project leadership. \nMentor junior and mid-level engineers through architecture reviews, circuit design, simulation strategy, layout collaboration, and silicon debug. \nInfluence product architecture and technical roadmap decisions through demonstrated technical depth, while operating as a senior individual contributor rather than a formal people manager. \n\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related discipline. \n\n12+ years of relevant experience in analog, mixed-signal, or power-management IC design. \n\nDemonstrated ownership of complex analog IP, converter subsystems, or complete smaller ICs from architecture through silicon and production. \n\nDeep hands-on expertise in PMICs, switching regulators, LDOs, charge pumps, and complex analog IP development. \n\nStrong understanding of analog feedback loops, control-loop compensation, stability analysis, and converter-architecture trade-offs. \n\nExperience with references, op-amps, comparators, buffers, level shifters, oscillators, sensors, current sensing, ADCs, and protection circuitry. \n\nExperience with industry-standard schematic design, simulation, extraction, and post-layout verification flows and tools. \n\nStrong understanding of analog layout effects, parasitics, matching, noise, reliability, ESD, latch-up, and IC-level robustness. \n\nExperience taking products through design, verification, tape-out, silicon validation, debug, qualification support, and production release. \n\nProven ability to establish design methodology, lead technical reviews, mentor engineers, and influence cross-functional decisions without requiring formal people-management authority. \n\nStrong communication and collaboration skills across global, multisite, and multicultural teams. \n\nSelf-driven, results-oriented, and able to deliver high-quality designs under tight schedules with limited supervision. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Staff Engineer, Digital Design (Power & Analog ICs)", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-21T09:48:32.675000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000144728339-senior-staff-engineer-digital-design-power-analog-ics-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking a Senior Staff Digital Design Engineer to architect and implement the digital content within power, analog, and mixed-signal IC products. This is a senior individual-contributor role requiring ownership from requirements and microarchitecture through RTL, synthesis, timing closure, DFT support, and silicon bring-up. \nThe successful candidate will design control, sequencing, protection, diagnostics, trimming, communication, test, and safety-related logic that works closely with analog circuitry. The emphasis is not on large processor SoCs. It is on high-quality digital design embedded inside power and analog ICs. \nYou will be expected to resolve ambiguous requirements, make sound area-power-performance trade-offs, develop reusable design practices, mentor engineers, and collaborate across analog design, verification, physical design, test, applications, and product teams. \nResponsibilities :\nDigital Architecture & RTL Design \nTranslate product and circuit requirements into robust digital microarchitecture and detailed block specifications. \n\nDesign optimized RTL for control, sequencing, protection, diagnostics, trimming, communication, test, and low-power functions within power and analog ICs. \n\nOwn block-level integration and contribute to chip-level digital architecture, interfaces, clocking, reset, power-state, and register-map decisions. \n\nMake and document trade-offs across functionality, area, power, testability, timing, reuse, and implementation risk. \n\nImplementation, Timing & DFT \nDevelop synthesizable Verilog/SystemVerilog RTL, synthesis scripts, timing constraints, and implementation collateral. \n\nOwn or guide synthesis, lint, CDC/RDC, low-power checks, static timing analysis, and handoff to physical design. \n\nSupport DFT architecture and implementation, including scan insertion, ATPG enablement, test modes, and production-test requirements. \n\nWork with place-and-route teams on timing closure, congestion, power, and post-layout issues. \n\nVerification & Silicon Support \nCollaborate with verification engineers on verification planning, assertions, coverage, debug, and specification closure. \n\nDevelop directed tests, reference checks, or test vectors where useful to accelerate design validation and production-test development. \n\nSupport gate-level and post-layout verification, silicon bring-up, device evaluation, failure analysis, and root-cause investigation. \n\nDevelop and document practical workarounds where device errata or silicon limitations require them. \n\nTechnical Leadership & Reuse \nDrive reusable RTL, design methodology, coding standards, review practices, and automation across projects. \n\nMentor junior and mid-level digital engineers and lead architecture, RTL, and implementation reviews. \n\nIdentify technical and schedule risks early and communicate clear options and recommendations to project leadership. \n\nCollaborate effectively with analog, applications, test, layout, CAD, and product teams across global locations. \n\nBachelor or Masters degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline. \n\n10+ years of relevant experience in digital design, RTL development, and implementation for semiconductor products. \n\nDeep hands-on experience in logic design, microarchitecture, Verilog/SystemVerilog RTL coding, synthesis, and static timing analysis. \n\nExperience designing digital control logic embedded in PMICs, power-management, automotive, audio, or other mixed-signal integrated circuits. \n\nStrong understanding of clocks, resets, low-power states, finite-state machines, register interfaces, fault handling, and hardware-software interaction. \n\nHands-on experience developing block-level and top-level timing constraints for STA and physical-design sign-off. \n\nWorking knowledge of DFT, scan insertion, ATPG, test modes, CDC/RDC analysis, lint, and gate-level verification. \n\nExperience with scripting and automation using TCL, Python, Perl, shell, or similar languages. \n\nProven ability to own complex design blocks, influence chip-level decisions, mentor engineers, and lead technical reviews. \n\nSelf-driven, results-oriented, and able to deliver high-quality designs under tight schedules in a multisite and multicultural environment. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Staff Validation Engineer, Silicon Validation (DC-DC Converters)", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-21T05:22:03.340000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000144685799-staff-validation-engineer-silicon-validation-dc-dc-converters-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "About the Role:\nWe are seeking a highly experienced and deeply hands-on Staff Validation Engineer to join our dynamic Silicon Validation team in Bengaluru. In this critical role, you will serve as a technical lead and mentor, driving the post-silicon validation of cutting-edge DC-DC converter products. Your profound expertise in power electronics, silicon validation methodologies, and PCB design will be instrumental in ensuring the quality, performance, and reliability of our next-generation power management ICs. You will not only lead complex validation efforts but also guide and technically ramp up junior validation engineers, fostering a culture of technical excellence.\nResponsibilities:\nTechnical Leadership & Architecture:Technical lead for post-silicon validation of complex DC-DC converter products (e.g., LDO, Buck, Boost, Buck-boost, Drivers, Controllers, etc…).\nDevelop comprehensive validation test plans and methodologies from silicon bring-up to characterization, focusing on performance, reliability, and robust operation across various load and environmental conditions (including load transient, ripple, parasitic effects).\nDrive the definition and implementation of validation techniques, including automated test development and data analysis.\n\nHands-on Validation & Debug:Perform hands-on initial silicon bring-up, debugging, and characterization on the bench using advanced lab equipment (oscilloscopes, multimeters, logic analyzers, power supplies, SMUs, spectrum analyzers, network analyzers, thermal chambers, etc.).\nLead root cause analysis of complex silicon issues, collaborating closely with design, system, and test engineering teams to drive timely resolutions.\nDevelop custom test setups, validation boards (PCB schematics and layout review), and fixtures to thoroughly test DC-DC converter performance.\n\nMentorship & Guidance:Provide technical mentorship and guidance to junior validation engineers on DC-DC converter principles, validation methodologies, test planning, debugging techniques, and best practices.\nFoster a technical learning environment within the team, promoting knowledge sharing and continuous improvement.\n\nTest Development & Automation:Define requirements for, and potentially contribute to, the development of automated test scripts and frameworks for efficient validation execution.\nContribute to the selection, adoption, and optimization of validation tools and infrastructure to improve overall team efficiency.\n\nCross-Functional Collaboration:Act as a lead between the Silicon Validation team and cross-functional teams including IC Design, System Design, Firmware, Product Engineering, and Application Engineering.\nDrive effective communication of validation findings, risks, and recommendations to various stakeholders.\n\nQuality & Compliance:Ensure validation activities adhere to rigorous quality standards, functional safety requirements, and operational protocols (e.g., ESD, safety).\nContribute to the continuous improvement of validation processes (e.g., SWIFT process adoption) and documentation standards.\n\nRequired Skills & Experience:\n9+ years of extensive, hands-on experience in Electrical/Electronic Post-Silicon Validation, with a significant focus on DC-DC converters and power management ICs.\nStrong technical experience in DC-DC converter topologies (e.g., Buck, Boost, Buck-Boost, LDOs, Gate Drivers), control schemes, and their critical performance parameters (efficiency, ripple, load transient, stability, EMI/EMC).\nGood proficiency in PCB schematics, layout review, and design considerations for high-frequency, high-current power circuits. Experience with validation board design is a significant plus.\nExpert of bench validation methodologies and debugging techniques. Highly skilled in using and interpreting data from lab equipment such as high-bandwidth oscilloscopes, arbitrary waveform generators, electronic loads, network analyzers, spectrum analyzers, power meters, etc.\nProven ability to perform root cause analysis of complex silicon issues and drive solutions collaboratively with design teams.\nExperience with test planning and execution for silicon validation across various corners (PVT), operating modes, and stress conditions.\nFamiliarity with industry-standard EDA tools for schematic/layout viewing, simulation analysis, and potentially test pattern generation (e.g., Cadence Virtuoso/Spectre, Siemens Calibre, Synopsys Verdi, etc.).\nExcellent communication, interpersonal, and mentorship skills.\nAbility to work effectively in a hybrid work environment with a strong presence in the Bengaluru lab.\n\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.\nWhy Join Our Team:\nThis is a unique opportunity to be a lead in our growing Silicon Validation team in India. You will play a pivotal role in bringing cutting-edge DC-DC products to market, shaping our validation methodologies, and directly contributing to the technical growth of your team members. If you are passionate about power electronics, enjoy hands-on validation, and thrive in a mentorship role, we encourage you to apply.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Staff Validation Engineer, Silicon Validation (DC-DC Converters)", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-21T05:08:30.196000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000144684769-senior-staff-validation-engineer-silicon-validation-dc-dc-converters-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "About the Role:\nWe are seeking a highly experienced and deeply hands-on Senior Staff Validation Engineer to join our dynamic Silicon Validation team in Bengaluru. In this critical role, you will serve as a technical architect and mentor, driving the post-silicon validation of cutting-edge DC-DC converter products. Your profound expertise in power electronics, silicon validation methodologies, and PCB design will be instrumental in ensuring the quality, performance, and reliability of our next-generation power management ICs. You will not only lead complex validation efforts but also guide and technically ramp up junior and senior validation engineers, fostering a culture of technical excellence.\nResponsibilities:\nTechnical Leadership & Architecture:Serve as the primary technical expert for post-silicon validation of complex DC-DC converter products (e.g., LDO, Buck, Boost, Buck-boost, Drivers, Controllers, etc…).\nArchitect comprehensive validation test plans and methodologies from silicon bring-up to characterization, focusing on performance, reliability, and robust operation across various load and environmental conditions (including load transient, ripple, parasitic effects).\nDrive the definition and implementation of advanced validation techniques, including automated test development and data analysis.\n\nHands-on Validation & Debug:Perform hands-on initial silicon bring-up, debugging, and characterization on the bench using advanced lab equipment (oscilloscopes, multimeters, logic analyzers, power supplies, SMUs, spectrum analyzers, network analyzers, thermal chambers, etc.).\nLead root cause analysis of complex silicon issues, collaborating closely with design, system, and test engineering teams to drive timely resolutions.\nDevelop custom test setups, validation boards (PCB schematics and layout review), and fixtures to thoroughly test DC-DC converter performance.\n\nMentorship & Guidance:Provide deep technical mentorship and guidance to junior and senior validation engineers on DC-DC converter principles, validation methodologies, test planning, debugging techniques, and best practices.\nFoster a strong technical learning environment within the team, promoting knowledge sharing and continuous improvement.\n\nTest Development & Automation:Define requirements for, and potentially contribute to, the development of automated test scripts and frameworks for efficient validation execution.\nContribute to the selection, adoption, and optimization of validation tools and infrastructure to improve overall team efficiency.\n\nCross-Functional Collaboration:Act as a key technical liaison between the Silicon Validation team and cross-functional teams including IC Design, System Design, Firmware, Product Engineering, and Application Engineering.\nDrive effective communication of validation findings, risks, and recommendations to various stakeholders.\n\nQuality & Compliance:Ensure all validation activities adhere to rigorous quality standards, functional safety requirements, and operational protocols (e.g., ESD, safety).\nContribute to the continuous improvement of validation processes (e.g., SWIFT process adoption) and documentation standards.\n\nRequired Skills & Experience:\n12+ years of extensive, hands-on experience in Electrical/Electronics Post-Silicon Validation, with a significant focus on DC-DC converters and power management ICs.\nDeep technical expertise in DC-DC converter topologies (e.g., Buck, Boost, Buck-Boost, LDOs, Gate Drivers), control schemes, and their critical performance parameters (efficiency, ripple, load transient, stability, EMI/EMC).\nStrong proficiency in PCB schematics, layout review, and design considerations for high-frequency, high-current power circuits. Experience with validation board design is a significant plus.\nMastery of bench validation methodologies and debugging techniques. Highly skilled in using and interpreting data from lab equipment such as high-bandwidth oscilloscopes, arbitrary waveform generators, electronic loads, network analyzers, spectrum analyzers, power meters, etc.\nProven ability to perform root cause analysis of complex silicon issues and drive solutions collaboratively with design teams.\nExperience with test planning and execution for silicon validation across various corners (PVT), operating modes, and stress conditions.\nFamiliarity with industry-standard EDA tools for schematic/layout viewing, simulation analysis, and potentially test pattern generation (e.g., Cadence Virtuoso/Spectre, Siemens Calibre, Synopsys Verdi, etc.).\nExcellent communication, interpersonal, and mentorship skills.\nAbility to work effectively in a hybrid work environment with a strong presence in the Bengaluru lab.\n\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.\nWhy Join Our Team:\nThis is a unique opportunity to be a foundational technical leader in our growing Silicon Validation team in India. You will play a pivotal role in bringing cutting-edge DC-DC products to market, shaping our validation methodologies, and directly contributing to the technical growth of your team members. If you are passionate about power electronics, enjoy hands-on validation, and thrive in a mentorship role, we encourage you to apply.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "MTS-RTL Verification Engineer", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-08-21T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/41973187", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nKey Responsibilities\nOwn verification strategy and planning; translate specifications into executable verification plans and closure metrics\nArchitect and develop scalable, reusable SystemVerilog/UVM verification environments\nDrive functional and code coverage closure, including assertions and targeted stimulus\nLead debug and issue resolution across verification and design teams\nProvide verification status, risk assessment, and release readiness updates\nEnsure verification readiness for high‑speed operation, including initialization, reset, CDC, and mode‑transition scenarios\nImprove verification methodologies, automation, and regression efficiency\nMentor engineers and provide technical guidance consistent with senior‑level expectations\nApply AI-enabled engineering tools\n\nRequired Qualifications\nExpert in SystemVerilog and UVM, including verification passionate about detailed testing and constrained‑random testing, Formal Verification\nStrong fundamentals in clocks, resets, FSMs, CDC, and debug\nProven experience verifying high‑speed digital designs in advanced process nodes\nHands‑on experience with industry simulators, coverage, and debug tools\nScripting proficiency (Python, Perl, or Tcl) for automation and productivity\nPreferred\nExposure to power‑aware verification\nExperience with high‑speed memory or adjacent subsystems\nExperience working with global, cross‑site teams\nSuccess Indicators\nStable, reusable verification environments with clear closure metrics\nData‑driven coverage closure with minimal late escapes\nEarly identification and resolution of high‑speed verification risks\nEffective and compliant use of Micron‑approved AI tools to augment verification activities, improve execution efficiency, and support continuous improvement.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Principal Engineer, High‑Speed RTL Design", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-08-21T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/43645228", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nKey Responsibilities \n\nHigh‑Speed RTL Design & Implementation \n\nDesign and implement timing‑critical RTL blocks, including:  \n\nControl and sequencing FSMs \n\nPower‑up, shutdown, and mode‑transition logic \n\nRegister banks and configuration logic \n\nTelemetry and monitoring datapath \n\nDevelop RTL with attention to latency, deterministic behavior, race‑free logic, and metastability avoidance. \n\n \n\n Nanometer‑Process‑Aware RTL Coding \n\nWrite RTL that is robust to:  \n\nTight setup and hold margins \n\nClock skew and uncertainty \n\nMulti‑cycle and false‑path constraints \n\nProcess, voltage, and temperature (PVT) variation \n\nEnsure RTL is clean for synthesis, static timing analysis, and ECO cycles in sophisticated technology nodes. \n\nClocking, Reset & Power‑Aware Logic \n\nImplement and review clock‑domain crossings (CDC) using proven synchronization techniques. \n\nDesign reset and initialization logic to ensure predictable system startup and recovery. \n\nSupport power‑aware and mode‑dependent behavior as the need arises by system operation. \n\nIntegration & Debug \n\nIntegrate RTL blocks into larger subsystems or top‑level designs, resolving:  \n\nPort‑list mismatches \n\nClock and reset dependencies \n\nMode interaction issues \n\nDebug RTL and integration issues using simulation waveforms and tool feedback. \n\nVerification & Timing Closure Support \n\nWork closely with verification engineers to:  \n\nClarify design intent and corner cases \n\nFix RTL issues uncovered during verification \n\nAddress timing issues identified during synthesis or place‑and‑route by refining logic, simplifying control paths, or adding limited pipelining under guidance. \n\nDesign Reviews & Documentation \n\nParticipate actively in RTL and design reviews, incorporating feedback from senior engineers. \n\nMaintain clear documentation describing block functionality, assumptions, and known limitations. \n\n \n\nRequired Technical Skills \n\nRTL & Digital Design \n\nStrong proficiency in SystemVerilog / Verilog RTL \n \n\nExperience with:  \n\nFSM design and implementation\n\nReset synchronization \n\nClock‑domain crossing concepts \n\nSolid understanding of timing‑critical control logic. \n\nHigh‑Speed & System Awareness \n\nSolid understanding of:  \n\nSetup/hold timing fundamentals \n\nCritical‑path sensitivity \n\nMulti‑mode and settings‑based behavior  \n\nExposure to mixed‑signal interaction (digital logic controlling or responding to analog behavior). \n\nFlow Awareness \n\nFamiliarity with:\n\nRTL lint and CDC checks \n\nSynthesis and basic STA reports \n\nDFT‑friendly RTL practices \n\nUPF and LEC \n\nAbility to debug issues exposed during RTL sign‑off or late integration stages. \n\n \n\nGood‑to‑Have or equivalent experience  \n\nExperience with PMICs, mixed‑signal SoCs, or companion ICs\n\nExposure to industry-standard specifications  \n\nBasic scripting skills (Python / Tcl) for automation \n\nExperience working across RTL–DV–PD handshakes \n\nApply AI-enabled engineering tools\n\n \n\nBehavioral Expectations \n\nWorks independently on assigned RTL modules or subsystems \n\nRaises risks early with analysis and proposed solutions \n\nDemonstrates growing ownership of RTL quality and delivery \n\nLearns from reviews and feedback to deepen high‑speed design expertise \n\nEffective and compliant use of Micron‑approved AI tools to augment verification activities, improve execution efficiency, and support continuous improvement.\n\n \n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "CPU Floorplan Lead", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-08-21", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/CPU-Floorplan-Lead_JR0286570", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nDefines the physical dimensions of the CPU IP with consideration for overall product costs such as die size optimization, die per reticle/good die per wafer maximization, and right technology selection as it pertains to metal layers and reuse strategy across different SKUs in a product family. Performs integration of all dies in a package and completes the relevant checks before tapeout. Creates and physical database for the IP. Collaborates with architects to optimize the placement of IPs for latency as well as die area/aspectratio. Creates specifications and collaterals for the IP blocks to execute the floorplan and automatic place and route (APR) at subsequent hierarchies. Collaborates with the clock design and logic design teams to deliver the physical block level floorplans for APR. Collaborates with the power delivery team on tradeoffs for metal allocation for signal and power.\n\nQualifications:\nJob Requirement:\nIn this role you will be responsible for all the aspects of Floorplan and pin placement activities. You will engage with Architecture, DFT and package to arrive at optimal chip planning early in the design cycle. You will work closely with physical design cluster leads to comprehend design challenges and arrive at optimal floorplan. You will play critical role in die size estimation and in evaluating Floorplan tools, methods and flows. Planning boundaries and pin densities to facilitate high confidence timing closure and routability. With your broad understanding of physical design you will play a critical role in identifying and solving multitude design issues at partition/cluster and full chip. Expertise with multiple aspects of ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I-O planning and hard IP integration.\n\nQualifications:\n Education: B.Tech. or M.Tech. in Electrical-Electronics Engineering with 10+ years' of experience.\n Preference: Master's Degree in Electrical-Electronics Engineering with VLSI-microelectronics specialization\n Minimum 4 years in floor planning. Expert user of Floorplanning tools such as ICC2 DP or Cadence Encounter.\n\nKey Skills:\n Experience with SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and advanced package technologies.\n Hierarchical design approach, top-down design, budgeting, timing and physical convergence.\n From a CAD tool perspective, experience with Floor planning tools, P and R flows, Physical Design Verification Flows is required.\n Familiar with various process related design issues including Design for Yield and Manufacturability.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "CPU Physical Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-08-21", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/CPU-Physical-Design-Engineer_JR0286567", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nPerforms physical design implementation of CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams. Possesses CPUspecific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT. Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, lowpower synthesizable CPU. Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.\n\nQualifications:\nAs a CPU Physical Design Engineer, you will play a pivotal role in implementing high-performance, low-power CPU designs from RTL to GDSII. You will focus on detailed processes such as synthesis, placement, routing, timing analysis, and power optimization, enabling designs that meet stringent performance and efficiency targets. Your work will directly influence the success of Intel's next-generation CPUs and their manufacturing readiness, contributing to innovative advancements in computing technology.\n\nYou will join a dynamic team dedicated to designing Intel's latest high-performance CPUs using cutting-edge technologies. This group focuses on delivering innovative solutions that propel Intel's leadership in the semiconductor industry. Collaborating across multiple domains, the team drives groundbreaking designs that support Intel's mission of creating world-changing technologies to enrich the lives of every person on Earth.\n\nKey Responsibilities\n- Perform physical design implementation from RTL to GDSII, including synthesis, placement, routing, clock tree synthesis, and optimization.\n- Conduct static timing analysis, power distribution analysis, and reliability verification to ensure design convergence and high manufacturability.\n- Collaborate with logic, circuit, architecture, and automation teams to improve CPU microarchitectures and design methodologies.\n- Work closely with industry-leading EDA vendors to enhance tool capabilities for high-speed, low-power CPU development.\n- Optimize designs for power, frequency, and area, ensuring product-level parameter excellence.\n- Participate in developing and improving physical design methodologies and flow automation for future projects.\n\nQualifications\n- B. Tech or M. Tech degree in Electrical, Electronics with 10+ years of relevant experience.\n- Technical expertise in synthesis, placement, clock tree synthesis (CTS), and routing tools, particularly using Synopsys and Cadence platforms.\n- Proficiency in timing signoff, formal verification, and low-power design techniques.\n- Solid understanding of submicron process node technologies and layout verification methods such as LVS/DRC.\n- Skilled in power estimation, power optimization, and power delivery methodologies.\n\nPreferred Qualifications\n- Familiarity with scripting languages like Tcl, Perl, and Python for automating physical design workflows.\n- Experience with Verilog or VHDL for hardware description and design execution.\n- Strong communication skills, both verbal and written, for collaborative problem-solving.\n- Demonstrated ability to work effectively in dynamic environments across geographies.\n- Knowledge of innovative feature feasibility studies and SD flow methodologies.\n\nBe part of a world-class team driving innovation in CPU design. Apply today to contribute to Intel's mission of shaping the future of technology.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Manager - Electrical Engineer", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2026-08-21", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/Manager---Electrical-Engineer_R2626754", "is_hardware": true, "platform": "workday", "jd_text": "Who We Are\n\nApplied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI and accelerating the commercialization of next-generation semiconductor chips. Join us and push the boundaries of materials science and engineering in a company at the foundation of the electronics industry. The work we do together advances the world’s technology. \n\nWhat We Offer\n\nLocation:\nBangalore,IND\nYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. \n\nAt Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. \n\nKey Responsibilities\nSupervises an engineering group with specific responsibility for lab and office safety, staffing, technical mentoring as required within the engineering group, staff professional and personal development and budget adherence. Technically lead and/or execute engineering projects\nEnsure customer satisfaction via on time delivery of product releases and prompt resolution of critical complex issues for range of products of difficult scope\nEnsure the integration of engineering resources with cross-functional teams to meet product goals\nDefine product specification, alpha/beta/gamma exit requirements and coordinate/execute the engineering development\nProvides management with updates pertaining to progress in specific projects and initiatives\nInterface with internal and external customers regarding complex electrical issues for specific projects\nHolds and contributes to technical reviews necessary for product design\nMake recommendations for the electrical engineering strategy and roadmap and business processes\n\nExp : 12+ Years\n\nFunctional Knowledge\nWorks on issues where analysis of situation or data requires review of relevant factors\n\nBusiness Expertise\nReceives assignments in the form of objectives with goals and the process by which to meet goals. Recommends changes to unit or sub-unit policies. Management reviews work to measure meeting of objectives\n\nLeadership\nProvides direction to employees according to established policies and management guidance. Administers company policies that directly affect subordinate employees\n\nProblem Solving\nExercises judgment within defined procedures and policies to determine appropriate action.\n\nImpact\nErroneous decisions or failure to achieve results will cause delays in schedules.\n\nInterpersonal Skills\nInteraction normally requires the ability to gain cooperation of others, conducting presentations of technical information concerning specific projects or schedules.\n\nPosition requires understanding of Applied Materials global Standards of Business Conduct and compliance with these standards at all times. This includes demonstrating the highest level of ethical conduct reflecting Applied Materials' core values.\n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nAssignee / Regular\nTravel:\n\nRelocation Eligible:\nNo\n\nApplied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "Verification Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-21", "url": "https://careers.arm.com/job/bengaluru/verification-engineer/33099/99522024784", "is_hardware": true, "platform": "talentbrew", "jd_text": "Build what powers the world.\nAt Arm, the technology you build doesn’t sit in isolation—it ends up in billions of devices. From smartphones and AI workloads to automotive and cloud, Arm-based systems are everywhere.\nIn our Bangalore team, you’ll work on real system-level problems, helping validate next-generation Arm CPU and System IP used by leading global companies.\n \nWhat You’ll Work On\nYou’ll be part of a team that builds complete reference systems around Arm IPs and use it for and Arm IP stress verification, giving you exposure far beyond traditional DV roles.\nIntegrate Arm CPU and system IPs into full reference platforms\nBring up systems across simulation and emulation\nDebug real system issues spanning hardware + low-level software\nDevelop system-level tests (C/C++/Assembly driven)\nWork closely with design, architecture, and global teams\nContribute to improving verification flows, tools, and efficiency\n \nWhy This Role Stands Out\n🔧 Early System-level exposure – go beyond UVM/testbench work\n🧠 Strong learning curve – CPU architecture, AMBA, memory systems\n🚀 High ownership – own IP integration, features, debug, and bring-up\n🌍 Global collaboration – work with teams across UK, US, and Europe\n⚡ Real impact – your work directly influences quality of Arm IPs.\n \nWhat We’re Looking For\nMust-Have\n2–8 years of experience in SoC/IP development or verification\nSolid understanding of verification fundamentals & debug\nExperience with C/C++ or Assembly-based testing\nExposure to pre-silicon environments (simulation/emulation)\nBasic understanding of CPU or SoC architecture\n \nGood to Have\nKnowledge of Arm architecture / AMBA protocols\nExperience in embedded software or firmware bring-up\nExposure to SoC integration or system-level validation\nScripting in Python/Perl\nFamiliarity with Verilog/SystemVerilog\n \nWho You’ll Fit In Best As\nYou enjoy debugging and figuring out system integration problems\nYou want to work close to real hardware and full systems\nYou’re looking to move beyond pure DV into system understanding\nYou take ownership and can drive tasks end-to-end\n \nEducation\nBE/BTech/MS in Electrical, Electronics, Computer Science, or related fields\n \nWhy Join Arm Bangalore\nWork on cutting-edge CPU and system technologies\nBe part of a high-impact, high-visibility team\nLearn from some of the best engineers in the industry\nContribute to products used by top semiconductor and tech companies globally\n \nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Verification Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-21", "url": "https://careers.arm.com/job/bengaluru/senior-verification-engineer/33099/99522024752", "is_hardware": true, "platform": "talentbrew", "jd_text": "Build what powers the world.\nAt Arm, the technology you build doesn’t sit in isolation—it ends up in billions of devices. From smartphones and AI workloads to automotive and cloud, Arm-based systems are everywhere.\nIn our Bangalore team, you’ll work on real system-level problems, helping validate next-generation Arm CPU and System IP used by leading global companies.\n \nWhat You’ll Work On\nYou’ll be part of a team that builds complete reference systems around Arm IPs and use it for and Arm IP stress verification, giving you exposure far beyond traditional DV roles.\nIntegrate Arm CPU and system IPs into full reference platforms\nBring up systems across simulation and emulation\nDebug real system issues spanning hardware + low-level software\nDevelop system-level tests (C/C++/Assembly driven)\nWork closely with design, architecture, and global teams\nContribute to improving verification flows, tools, and efficiency\n \nWhy This Role Stands Out\nEarly System-level exposure – go beyond UVM/testbench work\nStrong learning curve – CPU architecture, AMBA, memory systems\nHigh ownership – own IP integration, features, debug, and bring-up\nGlobal collaboration – work with teams across UK, US, and Europe\nReal impact – your work directly influences quality of Arm IPs.\n \nWhat We’re Looking For\nMust-Have\n4–8 years of experience in SoC/IP development or verification\nSolid understanding of verification fundamentals & debug\nExperience with C/C++ or Assembly-based testing\nExposure to pre-silicon environments (simulation/emulation)\nBasic understanding of CPU or SoC architecture\n \nGood to Have\nKnowledge of Arm architecture / AMBA protocols\nExperience in embedded software or firmware bring-up\nExposure to SoC integration or system-level validation\nScripting in Python/Perl\nFamiliarity with Verilog/SystemVerilog\n \nWho You’ll Fit In Best As\nYou enjoy debugging and figuring out system integration problems\nYou want to work close to real hardware and full systems\nYou’re looking to move beyond pure DV into system understanding\nYou take ownership and can drive tasks end-to-end\n \nEducation\nBE/BTech/MS in Electrical, Electronics, Computer Science, or related fields\n \nWhy Join Arm Bangalore\nWork on cutting-edge CPU and system technologies\nBe part of a high-impact, high-visibility team\nLearn from some of the best engineers in the industry\nContribute to products used by top semiconductor and tech companies globally\n\n \nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Design Engineer : Custom Digital Hard Macros (Physical IP)", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-21", "url": "https://careers.arm.com/job/bengaluru/senior-design-engineer-custom-digital-hard-macros-physical-ip/33099/99522007376", "is_hardware": true, "platform": "talentbrew", "jd_text": "Role Overview\nThe Arm Solutions Engineering Physical IP group is building a team focused on the development of custom and semi-custom digital hard macros used across Arm CPU, GPU, NPU, and SoC products. These hard macros enable functionality that cannot be efficiently implemented using standard-cell methodologies alone, including power delivery, clocking structures, asynchronous interfaces, reliability mechanisms, and digital circuits interacting with analog and mixed-signal systems.\nAs a Design Engineer, you will contribute to the implementation and delivery of digital hard macros while developing a broad understanding of the complete macro development lifecycle. You will work across RTL, physical implementation, timing closure, simulation, characterization, and integration activities, gaining exposure to all aspects of Physical IP development.\nThe ideal candidate will possess strong implementation skills while also demonstrating curiosity and willingness to understand the underlying circuit, layout, simulation, and characterization aspects of macro development. Although not expected to be a specialist in analog design or characterization, the engineer should be capable of investigating issues across multiple abstraction levels and collaborating effectively with design, AMS, verification, and SoC integration teams.\nKey Responsibilities\nSupport design and implementation of custom and semi-custom digital hard macros.\nDevelop and maintain RTL, timing constraints, implementation scripts, and automation flows.\nExecute synthesis, floorplanning, place-and-route, timing closure, physical verification, and signoff activities.\nAnalyze and debug timing, power, congestion, DRC, LVS, and implementation issues.\nReview schematics and layout structures to understand macro operation and implementation tradeoffs.\nSupport functional, gate-level, and mixed-signal simulation activities.\nAssist in characterization activities including timing, power, and functional model validation.\nGenerate and validate macro deliverables including Liberty models, LEF abstracts, physical views, and integration collateral.\nCollaborate with AMS, DFT, verification, and SoC integration teams during development and product integration.\nParticipate in silicon validation activities and support correlation of silicon behavior with pre-silicon expectations.\nContribute to methodology improvements, scripting, and automation initiatives.\nRequired Skills & Experience\n2-5 years of experience in digital design, physical implementation, Physical IP, or related semiconductor development.\nGood understanding of RTL design and digital design fundamentals.\nHands-on experience with synthesis, floorplanning, place-and-route, static timing analysis, and physical verification.\nFamiliarity with advanced implementation tools such as Cadence Innovus, Tempus, Genus, or equivalent.\nUnderstanding of timing constraints, SDC development, CDC concepts, and multi-clock designs.\nWorking knowledge of transistor-level concepts, digital circuit operation, and custom layout fundamentals.\nBasic understanding of simulation methodologies including RTL, gate-level, and behavioral simulations.\nFamiliarity with Liberty timing models and characterization concepts.\nExperience with Verilog/SystemVerilog and scripting languages such as Tcl or Python.\nStrong analytical, debugging, and problem-solving skills.\nGood communication and teamwork abilities.\nPreferred Qualifications\nExposure to hard-macro, memory, standard-cell, custom digital, or mixed-signal IP development.\nExperience at advanced process nodes.\nExposure to low-power design methodologies and power-domain crossings.\nUnderstanding of metastability, asynchronous interfaces, and reliability concepts.\nExposure to silicon validation or post-silicon debug activities\n \n#LI-PS2\n \nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Layout Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-21", "url": "https://careers.arm.com/job/bengaluru/senior-layout-engineer/33099/99522005200", "is_hardware": true, "platform": "talentbrew", "jd_text": "Role Summary\nOur Solutions Engineering Physical IP team comprises some of the industry’s leading experts in deep submicron circuit design. This position is a wonderful opportunity for you to work with our custom standard cell design engineering team on innovative technologies. Your work will have a significant lasting impact as the designs will be used in Solutions Engineering products servicing the infrastructure, client, automotive, and IoT market segments.\nIn this role, you will be responsible for the layout development of Arm custom standard cells in the latest, sub-3nm process technology nodes. The ideal candidate will be an expert in standard cell layout, physical verification, and automation techniques. You will work in close collaboration with the circuit design team to provide optimally tuned layout, and validate them through QA flows that use a variety of tools. This role is crucial in delivering high-performance, area-optimized, and DRC-clean logic libraries for next-generation SoCs and custom digital IPs.\nKey Responsibilities\nLayout design of logic standard cells (inverters, muxes, flops cells, complex logic gates) optimized for performance, area, and power.\nWork with automation and QA teams to support library validation flows.\nCollaborate with circuit designers to understand schematics and translate them into clean, compact layouts.\nDrive design rule clean (DRC) and  layout vs. schematic (LVS) closure using industry-standard verification tools (e.g., Calibre ).\nPerform layout debugging and root-cause analysis for DRC, LVS, and other physical sign-off issues.\nHandle cell abutment, cell profiling, and cell integration constraints for logic libraries.\nAddress layout-dependent effects (LDE) and  double patterning/EUV compliance in advanced nodes.\nReview and debug standard cell physical views (LEF, GDS, abstract views) for integration into digital flows.\nAutomate layout QA, regression checks, and PDK-driven layout verifications using scripts (e.g., SKILL, Python).\nParticipate in library quality audits and delivery cycles including signoff package creation and documentation.\nRequired Skills and Experience\n3+ years of custom layout experience in logic standard cell development.\nProven track record of working at 5nm, 3nm, or 2nm nodes with FinFET/GAA-based technologies.\nProficiency in Cadence Virtuoso.\nDeep understanding of advanced DRC rules, LVS methodologies, and multi-patterning constraints.\nSolid experience in cell layout optimization for PPA (Power, Performance, Area).\nStrong grip on pin accessibility, cell architecture trade-offs, and physical synthesis-aware design.\nAutomate layout-related tasks and workflows using scripting languages like Python, PERL, SKILL, and TCL.\nMaintain accurate documentation of layout designs, changes, and verification results.\nWorking knowledge of version control, configuration management, and flow automation\nMake effective use of AI tools and automation to improve productivity, accelerate learning, and enhance the quality of technical solutions\nStrong documentation and communication skills to interface with cross-functional teams (PDK, design, QA).\nStay updated on best practices for standard cell layout, design rules, and advanced node requirements.\n“Nice To Have” Skills and Experience :\nExposure to physical design implementation flow\n \n#LI-PS2\n \nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\n \nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "ASIC Methodology, Flow and Integration Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-21", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/ASIC-Methodology--Flow-and-Integration-Engineer_JR2023990", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We are now looking for ASIC Flow and Integration Engineer to drive design methodology, automation, and integration for our High Speed IO team.\n\nWhat you'll be doing:\nAs one of the primary methodology engineer, you’ll work across all NVIDIA-delivered projects, owning the integration process and collaborating with global teams to define and implement best-in-class methodologies. You’ll operate beyond RTL coding—building infrastructure and systems that are modular, reusable, and easily deployable across diverse silicon platforms. During the course of a project you would end up driving the following aspects of:\nOwn the full-chip and block-level integration process across multiple NVIDIA SoC and GPU projects.\n\nStitch together RTL units and ensure seamless connectivity, and hierarchy management.\n\nDefine and evolve internal design methodologies to improve scalability, quality, and turnaround time.\n\nBuild automation pipelines using Python/Perl to streamline integration, debug, and delivery.\n\nDevelop modular and reusable systems that can be easily delivered and adapted across different SoC and GPU architectures.\n\nCollaborate extensively with RTL, verification, physical design, and architecture teams to ensure flow compatibility and design readiness.\n\nDrive full-chip debug efforts, connectivity, and functional issues across multiple hierarchies and technology nodes.\n\nContribute to continuous improvement of internal standards and mentor engineers on flow usage and integration practices.\n\nWhat we need to see:\nBS or B.Tech or MS or M.tech in EE, ECE, CS, or equivalent degree with 2+ years or more experience in design integration and methodologies for ASIC design.\n\nComprehensive understanding of IP development flows, build flows is a must\n\nExcellent influencing skills resulting in collaboration with cross-cultural, multi geography and matrixed teams\n\nGood debugging, analytical and problem solving skills\n\nGreat interpersonal skills and ability to work as an excellent teammate\n\nWorking exposure with AI tools like Claude and Cursor would be a plus\n\nWe have some of the most brilliant and talented people in the world working for us. If you're creative and independent, with a genuine real passion for technology and improving the state of art, we want to hear from you! Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "ASIC Digital Design, Sr Staff/Principal Engineer - DDR", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-21", "url": "https://careers.synopsys.com/job/bengaluru/asic-digital-design-sr-staff-principal-engineer-ddr/44408/92599737760", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\n\nYou Are:\nYou are a passionate and accomplished digital design engineer with an unyielding drive for excellence. You thrive in technically challenging environments, where your deep understanding of RTL design and system architecture allows you to craft innovative solutions for complex problems. With a solid foundation in electrical engineering or VLSI, you have accumulated over five years of hands-on experience in designing and implementing ASIC solutions, particularly focusing on high-performance protocols such as DDR PHY, PCIe, USB, or HBM. Your expertise extends beyond individual contribution—you are equally comfortable leading and mentoring small design teams, fostering an environment of collaboration and shared learning.\n\nYou are adept at translating functional specifications into detailed micro-architecture and design documents, always ensuring clarity and precision. Your technical toolkit includes mastery of Verilog/SystemVerilog, and you are well-versed in industry-standard flows encompassing linting, CDC analysis, synthesis, and static timing. You’re not just a Sr technical expert; you are a proactive communicator, an enthusiastic collaborator, and a natural problem solver who takes initiative and ownership of deliverables. Your ability to adapt to a global, multi-site team environment is matched only by your commitment to continuous learning and professional growth. If you’re ready to take on a pivotal role in shaping next-generation silicon IP, Synopsys is where your aspirations and impact can soar.\n\nWhat You’ll Be Doing:\nLead and Drive all aspects of complete IP Design execution from start to end.\nArchitecting, designing, and implementing state-of-the-art RTL for the next-generation high-performance DDR PHY and related IP cores.\nTranslating standard and functional specifications into detailed architecture, micro-architecture, and design documentation for medium- to high-complexity features.\nContributing as an individual designer and also lead other engineers in —handling RTL coding, lint/CDC analysis, synthesis, debug, and test plan development. \nCollaborating with global teams across multiple sites, ensuring cohesive project execution and knowledge sharing.\nLead and mentor teams of RTL designers, providing technical guidance and fostering professional development.\nEngaging in continuous process improvement, proposing and implementing enhancements to design flows and methodologies.\nTroubleshooting and resolving design and verification issues, ensuring robust and high-quality deliverables.\n\nThe Impact You Will Have:\nDirectly contributing to the design and delivery of high-performance IP cores that power industry-leading semiconductor solutions worldwide.\nElevating Synopsys’ reputation for technical excellence and innovation in the IP design space.\nAccelerating the adoption of advanced protocols and interfaces in cutting-edge technologies.\nEnabling customers to achieve faster time-to-market and superior silicon performance.\nMentoring and uplifting team members, fostering a culture of knowledge sharing and technical growth.\nDriving continuous improvement in design methodologies, enhancing efficiency and product quality.\nSupporting Synopsys’ mission to remain at the forefront of the Era of Pervasive Intelligence through breakthrough silicon solutions.\n\nWhat You’ll Need:\nBachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related discipline.\n10+ years of relevant industry experience in ASIC digital design, with a focus on protocols like DDR, PCIe, USB, or HBM.\nPast experience of leading IP deign projects, team.\nIn-depth experience with RTL coding in Verilog/SystemVerilog and simulation tools for ASIC design.\nStrong command of design flows, including lint, CDC, synthesis, static timing analysis, and formal verification.\nHands-on expertise in architecting and implementing control path-oriented designs (e.g., asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces).\nFamiliarity with scripting languages such as Perl or Shell—an advantage.\nDemonstrated ability to technically lead or mentor small teams of engineers.\n\nWho You Are:\nA collaborative team player who thrives in a multi-site, multicultural environment.\nAn effective communicator, able to translate complex technical concepts for diverse audiences.\nA proactive problem-solver with strong analytical and troubleshooting skills.\nSelf-motivated, showing high initiative and ownership of responsibilities.\nAdaptable and eager to learn, always seeking opportunities for personal and professional growth.\nCommitted to fostering a positive, inclusive, and innovative team culture.\n\nThe Team You’ll Be A Part Of:\nYou will join the R&D Solutions Group at our Bengaluru Design Center, a dynamic and diverse team dedicated to the design and development of industry-leading DesignWare IP cores. As a Technical Individual Contributor, you will collaborate with global experts in a multi-site environment, contributing to technically challenging projects that push the boundaries of silicon design. The team values innovation, continuous learning, and the sharing of knowledge, offering ample opportunities for growth and leadership.\n\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "ASIC Digital Design, Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-21", "url": "https://careers.synopsys.com/job/bengaluru/asic-digital-design-staff-engineer/44408/99541956032", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou are an engineer who gets energized when you see a complex Subsystem come together and actually work, not just pass a basic smoke test, actually work under corner cases that would make most people walk away. You have spent enough time in verification to know that the difference between a clean tapeout and a costly respin often lives in a test case no one thought to write or a coverage hole no one noticed until it was too late. That keeps you up at night in the best way.\nYou think in test plans, not checklists. When someone hands you a spec for a DDR or PCIe or UCIe interface, you are already mapping out where the edge cases hide and what kind of stimulus will actually stress the design. Debugging a waveform with thousands of signals does not intimidate you, it is where you do your best work. You ask the right questions early, whether that is clarifying an ambiguous requirement with an architect or pushing back on an RTL designer when something does not smell right.\nLeading a team does not mean having all the answers. It means knowing when to dive deep yourself and when to unblock someone else. You have mentored engineers before, or you are ready to, and you understand that the best verification environments are built by people who share what they learn. At Synopsys, you will work on Subsystems that power the chips behind AI, automotive, and cloud infrastructure, and the verification rigor you bring will directly determine whether those chips work.\nWhat You'll Be Doing\nLead verification ownership for critical Subsystem areas, driving strategy and execution alongside a team of verification engineers working on DDR, HBM, PCIe, UCIe, Ethernet, UALink, or UFS IP integration\nDefine, implement, and track detailed verification test plans that map coverage goals to real silicon risk, ensuring nothing slips through\nBuild and maintain Subsystem-level UVM testbenches in SystemVerilog, integrating RTL and behavioral models into a cohesive verification environment\nWrite complex test cases, assertions, and checkers that catch the corner cases other teams miss, and debug simulation failures down to root cause\nExtract, analyze, and drive closure on functional coverage and code coverage metrics, working with the team to close gaps before signoff\nManage regression suites and contribute to continuous improvement of verification flows, methodologies, and automation\nCollaborate directly with RTL designers and architects across global sites to ensure functional correctness and alignment on design intent\nThe Impact You Will Have\nEnable successful verification and deployment of high-performance Subsystems that ship in leading-edge SoCs powering AI, automotive, cloud, and mobile applications worldwide\nCatch critical design issues early in the verification cycle, reducing time-to-market and avoiding costly silicon respins that can delay product launches by months\nAdvance verification methodologies and AI-assisted verification flows that influence how Synopsys and the broader industry approach Subsystem-level verification\nBuild verification environments and test strategies that become reusable assets across multiple product generations and IP families\nMentor and grow verification engineers on your team, raising the technical bar and building a culture of rigor and knowledge sharing\nStrengthen Synopsys' reputation as the premier provider of high-speed connectivity IP Subsystems through engineering excellence that customers depend on\nSet industry standards for IP verification quality and methodology, contributing to Synopsys' leadership in chip design and EDA\nWhat You'll Need\nBachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related technical field\n8+ years of hands-on experience in ASIC or FPGA verification, with a track record of owning verification deliverables from planning through signoff\nProven expertise developing SystemVerilog and UVM-based testbenches for complex ASIC designs, including experience with assertions, checkers, and constrained random stimulus\nStrong ability to define verification strategies, write rigorous test plans, and drive coverage closure using functional coverage and code coverage analysis\nExperience technically leading a verification team or mentoring engineers, with demonstrated success collaborating across design, architecture, and verification teams\nDeep understanding of verification metrics, regression management, and debugging complex simulation failures in large-scale environments\nExperience with high-speed interface protocols such as DDR, HBM, PCIe, UCIe, Ethernet, UALink, or UFS is highly desirable and will set you apart\nWho You Are\nYou can look at a failing regression, pull up the waveform, and within an hour tell the team whether it is a testbench bug, an RTL issue, or a timing corner no one considered\nWhen a junior engineer brings you a stuck debug, you do not just give them the answer, you walk them through how to isolate the problem so they can solve the next one themselves\nYou push back when a test plan is too shallow or a coverage model misses an important state transition, and you do it in a way that makes the team stronger, not defensive\nYou stay current on verification techniques and tools, whether that is exploring AI-assisted verification flows or adopting new UVM patterns that improve reuse and debug speed\nYou communicate clearly across time zones and disciplines, translating verification status into terms that architects, designers, and project leads can act on\nYou take ownership seriously, if a coverage hole or test gap exists in your area, you do not wait for someone else to notice, you flag it and drive it to closure\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Physical Design Layout Engineer ICE", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-08-21", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Physical-Design-Layout-Engineer-ICE_JR0286585", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nAs a Physical Design Engineer, you will focus on creating and optimizing chip designs at the physical level. You'll be responsible for crafting elements such as cell, block-level semi-custom layouts, FUB-level floor plans, and performing schematic-to-layout verification to ensure design integrity. Your contributions will directly impact the development and execution of complex chip methodologies, enabling Intel to deliver cutting-edge technology to the marketplace.\n\nBusiness group\nThis role is part of Intel's broader semiconductor engineering organization, which is dedicated to designing, developing, and verifying innovative chip technologies. The team focuses on advancing physical design methodologies, ensuring reliability, and optimizing chip performance while supporting Intel's mission to create world-class computing solutions.\n\nKey Responsibilities\n- Develop and refine physical chip designs, including cell and block-level semi-custom layouts, FUB-level floor plans, abstract view generation, and schematic-to-layout verification.\n- Conduct reliability verification, debug issues, and apply proactive intervention strategies to optimize chip performance.\n- Utilize parasitic extraction, custom polygon editing, auto-place and route algorithms, floor planning, and full-chip assembly techniques to ensure design success.\n- Collaborate across teams to troubleshoot complex design challenges and deliver high-quality solutions.\n- Participate in the execution of project methodologies, flow developments, and verification processes.\n\nQualifications:\nMinimum Qualifications\n- Bachelor's degree in Electronics, Electrical Engineering, or a related field with 0-1 years of hands-on experience in physical design, including skills gained through internships, academic projects, coursework, or hands-on training OR a Master's degree in Electronics, Electrical Engineering, or a related field with no prior professional experience.\n- Basic understanding of layout design and verification processes.\n- Familiarity with ICC2 tools.\n- Proficiency in TCL scripting is a plus.\n\nPreferred Qualifications\n- Strong problem-solving skills and ability to troubleshoot complex design challenges effectively.\n- Excellent collaboration and communication skills to work across diverse teams.\n- Demonstrated interest in advancing semiconductor technologies and methodologies.\n\nWe're excited to see how your skills and passion for innovation can contribute to our cutting-edge team. Take the next step in shaping the future of technology by applying today.\n          \n\nJob Type:\nIntel Contract Employee\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Validation Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-20T16:32:32.714000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000144597684-validation-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "The Post-Silicon Validation team within the Performance Computing Power Division is building a world-class organization of highly skilled engineers across multiple global sites. Our mission is to push the boundaries of silicon validation for industry-leading integrated circuits enabling high-power, high-efficiency power management systems. \nWe are committed to delivering the highest level of validation quality by continuously improving test coverage, measurement accuracy, repeatability, automation, and execution efficiency while reducing overall validation time. \nAs a Validation Engineer, you will be part of a multidisciplinary global development team and play a key role in ensuring that every new product fully meets its electrical, functional, and performance specifications before release to production. You will work closely with Design, Applications, Product Engineering, Quality, and System teams to identify, debug, and resolve silicon and system-level issues while supporting aggressive product development and New Product Introduction (NPI) schedules. \nFor our office in Bangalore, we are looking for a passionate engineer who thrive on innovation, enjoy solving complex technical challenges, and is committed to delivering high-quality results in a fast-paced environment. \nPrincipal Responsibilities :\nValidate analog, digital, mixed-signal, and power management ICs against electrical, functional, and performance specifications. \n\nPrepare advanced laboratory test setups for complex silicon evaluation. \n\nContribute to the design of custom evaluation boards and supporting hardware for silicon characterization. \n\nDevelop measurement scripts using Python. \n\nPerform data acquisition, statistical analysis, result correlation, preparation of detailed technical reports and silicon evaluation summaries. \n\nEvaluate silicon performance at device, board, and system level, identifying, documenting, and tracking silicon and application issues. \n\nCollaborate closely with Design, Applications, Firmware, Product Engineering, and Quality teams to investigate and resolve silicon and system-level bugs. \n\nContribute innovative ideas that enhance validation quality, automation, productivity, and time-to-market. \n\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related discipline with about 2 years of work-related experience. \n\nGood level of expertise in lab automation, ability to propose improvements to existing measurements techniques. \n\nProficiency with Python programming with particular use for lab automation hardware environments  \n\nBasic knowledge of power management applications in consumer electronic   \n\nBoard level analog and digital circuit design expertise for PCB schematic creation  \n\nStrong analytical and debugging skills with a systematic approach to problem solving. \n\nSelf-motivated, proactive, and able to manage priorities while delivering high-quality results under demanding project schedules. \n\nGoals-oriented and able to deliver on-time results under tight schedules  \n\nExcellent communication skills and ability to collaborate effectively within international cross-functional teams. \n\nImportant \nConcise and precise communication, internal and with customers   \n\nCross cultural awareness and sensitivity within multisite and multicultural environments  \n\nFlexible to undertake occasional international travel  \n\nExcellent command of verbal and written English  \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Sr Staff, Product/Program Management - Semiconductor NPI(Analog/Power)", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-20T07:34:47.291000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000144476019-sr-staff-product-program-management-semiconductor-npi-analog-power-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Responsible for managing the development of New Products (Industrial and Automotive) and delivering on all program commitments from inception through execution to tape out and start of production. \nDevelop and maintain project schedules, budgets, and resource allocations to ensure on-time project completion within budget constraints while maintaining high quality \nDrive cross-functional teams including design, test, product engineering, validation, marketing, systems, applications, operations, planning, various factories, and vendors as Program Manager to meet project milestones and objectives. \nManage several key projects in parallel or singular large program \nContinuously reviews program progress, proactively identify risks and collaboratively develops and drives risk mitigation efforts \nCollaborate with cross-functional and peers from other business groups to drive collaboration and harvest best practices and lessons learned to keep the business group in sync with One Renesas methodologies, tools and systems \nDrive execution initiatives and process improvements at the functional, cross functional and business group level \nMonitor and report on project progress, including key performance indicators and metrics, to senior management and stakeholders. \n\n \nResponsibilities may include: \nCollaborate and work in a team environment with Design, Applications, Test, Marketing, Manufacturing, Quality and Reliability in all aspects of new product development, production release to accomplish goals and objectives \nDesign bench evaluation PCBs (printed circuit boards) and generating characterizations programs for bench evaluations \nPerform evaluation, debug and characterization of integrated circuits to ensure they meet the product requirement specifications and manufacturing requirements \nWork with failure analysis (FA) to determine root cause of any reliability and qualification failures \nKnowledge of statistics and tools (example: Spotfire) to analyze large amounts of characterization data and determine and set production test limits and predict yield data \nWork with process and package technology development to develop and qualify technologies for new product development \nWork closely with the global manufacturing facilities to address customer specific product quality, yield management and cost reductions issues on mature products. Scope of work could include product spins and derivatives \n\nBachelor’s degree in electrical engineering \n\n7+ years of hand`s on technical program/project management experience leading cross functional teams to develop broad market or custom Power/Analog/ Mixed-Signal products for commercial, industrial or automotive applications with at least 10  years of experience working in the Semiconductor domain \n\nSolid understanding of Semiconductor Manufacturing, Development and Management \n\nAbility to work in a team setup comprising of other functional groups \n\nStrong time management skills that enable on-time project delivery \n\nDemonstrated ability to build strong, influential relationships \n\nAbility to work effectively in a fast-paced and rapidly changing environment \n\nAbility to take the initiative and drive for results \n\nStrong problem solving, verbal and written communications skills \n\nAbility to multiplex between projects and be able to maintain project schedules \n\nFamiliarity with JEDEC / AEC Qualification standards \n\nFamiliarity with ATE tester platforms (Teradyne / Eagle) \n\nKnowledge of statistics and tools (example: Spotfire) to analyse large amounts of characterization data and determine and set production test limits and predict yield data \n\nKnowledge of back-end semiconductor processes like Wafer Fabrication, Bump, Packaging, Assembly and Test is an asset. \n\nWorking experience in a high-pressure environment, competing priorities and tight turnaround times. \n\nStrong communication, presentation, and leadership skills; Ability to lead technical discussions and summarize outcome for executive level status reporting. \n\nProficient with industry standard project management tools such as MS Project, Jira, SharePoint, DFMEA, Root Cause Analysis , Confluence, Microsoft OneNote \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Sr Staff Test Engineer - ATE", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-20T07:20:18.224000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000144473210-sr-staff-test-engineer-ate", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Renesas’ “India For India” is seeking an experienced Test Engineer to join our team. This role offers a unique and exciting opportunity to work on the development of state-of-the-art Power/Analog devices. You will be part of a cross-functional team, driving the product from conception to volume production. \nResponsibilities include: \nWork with design/systems teams to understand specifications \nGenerate test plan, create test and char program, design ATE hardware interface boards \nDebug characterizing silicon on ATE, correlate results with bench data \nAnalyse silicon results, supporting failure analysis tasks \nPerform statistical analysis of yield fallout, debug and fix yield issues; optimize test time \nWork with production team to release products to volume production \nTest strategy definition and implementation for new Power/Analog products \nATE (Automatic Test Equipment) test hardware and software \nSilicon qualification& characterization including qual hardware development \nComprehensive device debugging, design validation and failure analysis \nDrive for robust and cost-effective test solutions while being accountable for product quality \n\nTest Engineer with 10+ Years experience developing hardware and software at Wafer Sort and Final Test for PMIC, Temp Sensors and I3C products. \nTest Lead experience preferred. \n10+ Years of experience on mFLEX, Advantest 93K, SPEA , Cohu DiamondX, Teradyne Eagle or equivalent analog ATE (iFlex, LTX, VLCT), although Cohu experience is preferred and is a differentiator \nExperience using I2C, I3C, and SPI protocol as well as trim implementations for power IC products \nCharacterization test program and hardware development experience, Production test program and hardware development experience \nStrong technical knowledge of electronic devices and circuits, and Analog test techniques \nData analysis skills using Spotfire, dataPower or equivalent tool based on STDF \nExperienced with various lab equipment such as scopes, power supplies, sourcemeters, loads etc. \nExperience with product engineering activities such as yield improvement and test time reduction \nStrong understanding of the IC product development process, from concept to volume production \n \nPreferred qualifications: \nExperienced with test program and hardware offload to OSATs \nProficiency in programming/scripting in C++, Python, C# \nLabview, Teststand experience \nRevision control tools experience: Subversion, Git \nDemonstrated strong analytical and problem-solving skills \nStrong verbal and written communication skills \nAbility to work in teams and collaborate effectively with people in different functions \nStrong time management skills that enable on-time project delivery \nDemonstrated ability to build strong, influential relationships \nAbility to work effectively in a fast-paced and rapidly changing environment \nAbility to take the initiative and drive for results \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Staff Engineer", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-08-20T05:11:41+00:00", "url": "https://jobs.infineon.com/careers/job/563808971837081", "is_hardware": true, "platform": "eightfold", "jd_text": "Join our team as an ASIC Prototyping Engineer where your expertise in FPGAs, RTL design and prototyping will drive pre-silicon prototyping and validation of complex SoCs. In this role you will emulate cutting-edge SoC designs on FPGA prototyping platforms and Emulation platforms \n\nYour role\nKey responsibilities in your new role\n\nCollaborate proactively with cross-functional teams to verify, prototype, validate, and debug complex SoC designs while supporting multiple software development teams.\nDefine and establish FPGA prototyping environments, and drive board-level hardware development to enable comprehensive pre-silicon validation.\nPort ASIC RTL designs onto industry-leading prototyping and emulation platforms, including Synopsys HAPS, S2C FPGA platforms, Synopsys ZeBu, and Cadence Palladium.\nPerform FPGA synthesis, place-and-route (PnR), timing closure, and detailed timing analysis to ensure optimal design performance.\nDevelop FPGA-friendly prototyping models for analog blocks and hard IPs, including clock tree simplification to facilitate efficient implementation and validation.\n- \n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor's degree (B.E./B.Tech) in Electronics, VLSI Design, or a related field with 12+ years of relevant industry experience, or Master's degree (M.E./M.Tech) with 10+ years of relevant experience.\n\nStrong expertise in FPGA design methodologies, RTL development, and associated design tools, flows, and processes.\n\nProven hands-on experience in FPGA-based ASIC prototyping, including Synopsys HAPS platforms and related toolchains.\n\nPractical experience working with industry-leading emulation platforms such as Synopsys ZeBu and Cadence Palladium.\n\nSolid understanding of ASIC design flow, Design Verification (DV) methodologies, SoC architecture, and complex system-level debugging.\n\nAdvanced proficiency in hardware description languages, including Verilog, SystemVerilog, and VHDL.\n\nStrong scripting and programming skills with the ability to develop automation solutions and improve design productivity.\n\n-      \n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nAnand Rawal", "jd_status": "stored"}, {"title": "Staff Engineer, Analog Design", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-20T05:09:19.543000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000144457489-staff-engineer-analog-design", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Looking for a 8+ years experienced Engineer with good understanding of Analog concepts, experience of from scratch design of key analog blocks, integrating smaller blocks to create functional I/Ps and full ownership of those, ICs and well versed with Transistor level design flow, to join the 2.6B$ Power Business Unit. The candidate will get to work on a wide range of exciting products such as PMICs, Linear and Switching DC-DC converters powering the next generation of most sought-after phones and hand held devices. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas’s massive Power product portfolio.\nEssential Functions:\nMust be proficient in designing and owning key analog blocks including Bangdap references, Analog Buffers, Op-Amps, Comparators, High speed level shifters etc.\nMust be able to come up with architectures to meet block level performance specifications.\nMust be well versed of the standard architectures and be able to bring in innovative ideas to improve designs to meet challenging specifications.\nShould have clear understanding of analog layouts and should be able to work closely with and guide layout engineers to ensure quality layout to meet the desired performance.\nMust be conversant with the standard design, extraction and simulation flows & tools, speed, convergence, accuracy trade-offs and should be able to optimize setups based on Pre/Post (with/without) Parasitic using simulator options, debug and navigate through tool related challenges.\nShould be able to mentor Freshers and Junior engineers for upscaling their technical skills as well as other skills needed for better efficacy.\nShould be able to develop multiple blocks with minimal supervision, take full ownership to drive all aspects within committed schedule and work closely with Sr members of Design team to support them build subsystem/chip top.\nExperience of silicon validation and debug is a strong advantage.\nShould have good understanding of ESD and be able to design the I/O ring for the IC\n \n\nMinimum Requirements:\nBachelor’s or Master’s degree in Electrical Engineering\n8+ years in Analog Circuit Design, Simulation and Verification\nSolid understanding of analog designs and proven experience of block designs with full ownership.\nSchematic generation, simulation and verification using modern CAD tools\nDesign & verification experience of simple analog blocks, Monte Carlo analysis using industry standard CAD tools\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Staff NPU STA/Timing Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-20T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720515867", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nResponsibilities:\nSTA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.\n\nTiming analysis, validation and debug across multiple PVT conditions using PT/Tempus.\n\nRun Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.\n\nEvaluate multiple timing methodologies/tools on different designs and technology nodes.\n\nWork on automation scripts within STA/PD tools for methodology development.\n\nGood Technical writing and Communication skills, should be willing to work in cross-collaborative environment\n\nExperience in design automation using TCL/Perl/Python.\n\nFamiliar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus\n\nFamiliar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo.\n\nEducation : B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI.\nPreferred Qualification/Skills\n5 - 10 years of experience in STA/Timing\n\nStrong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling\n\nHands-on experience with STA tools - Prime-time, Tempus\n\nHave experience in driving timing convergence at Chip-level and Hard-Macro level\n\nIn-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,\n\nKnowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)\n\nKnowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation.\n\nProficient is scripting languages – TCL, Perl, Awk\n\nBasic knowledge of device physics\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NPU STA/Timing Engineer (Senior/Lead)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-20T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720515862", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nResponsibilities:\nSTA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.\n\nTiming analysis, validation and debug across multiple PVT conditions using PT/Tempus.\n\nRun Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.\n\nEvaluate multiple timing methodologies/tools on different designs and technology nodes.\n\nWork on automation scripts within STA/PD tools for methodology development.\n\nGood Technical writing and Communication skills, should be willing to work in cross-collaborative environment\n\nExperience in design automation using TCL/Perl/Python.\n\nFamiliar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus\n\nFamiliar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo.\n\nEducation : B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI.\nPreferred Qualification/Skills\n3 - 10 years of experience in STA/Timing\n\nStrong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling\n\nHands-on experience with STA tools - Prime-time, Tempus\n\nHave experience in driving timing convergence at Chip-level and Hard-Macro level\n\nIn-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,\n\nKnowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)\n\nKnowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation.\n\nProficient is scripting languages – TCL, Perl, Awk\n\nBasic knowledge of device physics\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Lead NSP STA/Timing Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-20T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720515865", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nResponsibilities:\nSTA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.\n\nTiming analysis, validation and debug across multiple PVT conditions using PT/Tempus.\n\nRun Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.\n\nEvaluate multiple timing methodologies/tools on different designs and technology nodes.\n\nWork on automation scripts within STA/PD tools for methodology development.\n\nGood Technical writing and Communication skills, should be willing to work in cross-collaborative environment\n\nExperience in design automation using TCL/Perl/Python.\n\nFamiliar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus\n\nFamiliar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo.\n\nEducation : B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI.\nPreferred Qualification/Skills\n7 - 14 years of experience in STA/Timing\n\nStrong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling\n\nHands-on experience with STA tools - Prime-time, Tempus\n\nHave experience in driving timing convergence at Chip-level and Hard-Macro level\n\nIn-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,\n\nKnowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)\n\nKnowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation.\n\nProficient is scripting languages – TCL, Perl, Awk\n\nBasic knowledge of device physics\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RTL Performance Analysis Architect", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-20T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720514224", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Systems Engineering\nGeneral Summary:\nJoin the Bangalore-based Infrastructure IP Performance Modeling, Verification, and Analysis team as an RTL Performance Analysis Architect. As part of the Infrastructure RTL Analysis and Optimization (I-RAO) team and a broader global performance organization, you will influence architecture and design decisions across Snapdragon-based SoCs for mobile, automotive, XR/VR, server, and AI products. The role spans early architectural exploration, microarchitectural analysis, RTL performance correlation, pre-silicon bottleneck identification, design optimization, and production-hardware tuning. You will analyze infrastructure IPs—including memory controllers, emerging compute-in-memory technologies, cache controllers, memory management units (MMUs), PCIe and CXL controllers, compression IPs, and interconnects—and have opportunities to contribute to patents and technical publications.\n\nResponsibilities\nCharacterize representative workloads and use cases to identify performance bottlenecks across CPUs, GPUs, multimedia engines, SMMUs, CXL, networks-on-chip (NoCs), cache controllers, and memory controllers.\n\nCollaborate with architecture, design, and modeling teams to evaluate enhancements for next-generation memory controllers, last-level caches, interconnects, and related infrastructure IPs.\n\nAnalyze power-and-performance (PnP) tradeoffs and propose architectural or microarchitectural improvements that increase efficiency.\n\nDefine targeted pre-silicon performance analysis strategies and test plans that expose design bottlenecks early.\n\nDevelop simulation-scale workloads, monitors, and analysis flows for SystemVerilog/UVM-based pre-silicon environments.\n\nCore Qualifications\nBachelor’s degree in Engineering, Information Systems, Computer Science, or a related field.\n\nStrong foundation in computer architecture and microarchitecture, supported by rigorous analytical and problem-solving skills.\n\nTwo to ten years of experience in digital design, performance analysis, or functional verification.\n\nExperience investigating performance and microarchitectural behavior in complex hardware blocks such as memory controllers, CPUs, GPUs, NoCs, or multimedia subsystems.\n\nAbility to identify system-level performance bottlenecks, develop evidence-based hypotheses, and communicate actionable recommendations.\n\nProficiency in SystemVerilog/UVM and scripting or automation using Python or Perl.\n\nClear communication and collaboration skills for working effectively with architects, designers, modelers, and verification engineers across global teams.\n\nPreferred Qualifications\nDemonstrated innovation or technical thought leadership through patents, peer-reviewed publications, or high-impact engineering contributions.\n\nKnowledge of memory controllers, LPDDR/DDR protocols, AMBA, Arm architectures, cache coherency, CXL, PCIe, MMUs, compression technologies, or interconnect design.\n\nExperience translating system performance use cases into targeted workloads, metrics, and pre-silicon analysis plans.\n\nA collaborative mindset, intellectual curiosity, and commitment to technical excellence in a fast-paced engineering environment.\n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.\n                                                                    OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience.\n                                                                    OR\nPhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "AMS Verification Engineer", "company": "Samsung", "location": "SSIR, Goldstone, Bangalore, India", "date_posted": "2026-08-20", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/SSIR-Goldstone-Bangalore-India/AMS-Verification-Engineer_R119757", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.\n\nPosition: AMS DV Engineer\nRole and Responsibilities\n\nRoles and Responsibilities\n• Strong knowledge of mixed signal verification fundamentals\n• Experience with behavioral modelling of analog blocks like switching converters and LDO’s using SV/Verilog/Verilog-AMS/VerilogA\n• Experience of Real model creation and model validation\n• Prior experience with verification of Power management IPs and SOCs - Desirable\n• Strong background in verification fundamentals, verification planning and environment development is must\n• Experience in PSL/SV assertions development\n• Should be process oriented and have passion for scripting and automation\n• Should have good soft skills and experience of working collaboratively in cross-site environment\n\nSkills and Qualifications\n\nExperience – 4 to 8 Years of experience\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\n        By submitting this application, I confirm that I will not disclose or use proprietary information, trade secrets or confidential materials obtained from or belonging to my current or past employers during the recruitment process or future employment with Samsung Semiconductor India Research, a division of Samsung R &D Institute India Bangalore Private Limited\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "Principal AMS Verification Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-08-20", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506068", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Principal Analog Mixed Signal Verification Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following \n\nComplete AMS verification ownership of a Product (Define and execute) \n\nHands-on verification of Analog Mixed-Signal simulations. \n\nParticipate with Design team to Enable the Behavioral Modeling requirements  \n\nCollaborate with cross-functional teams for seamless integration within the overall system \n\nCome up with methods to improve efficiency in verification processes. \n\nContribute to the overall success of the team by actively participating in debugging sessions, providing valuable insights, and maintaining effective communication within the team. \n\nWork in methodology development team to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows \n\n#L1-LK1\n\nResponsibilities\nExpert-level knowledge in Analog Mixed-Signal simulations \n\nExpert-level modeling of Analog blocks using SV Real Modeling / Verilog-AMS /Verilog-A  \n\nProficient on using design and verification languages: Verilog, System Verilog, and System Verilog Assertions (SVA). \n\n Proficient on Design Verification development process, from specification to test plan, to configurable test bench, drivers and checkers setup, to test suite building to meet functional and code coverage goals  \n\nExperience in verifying Power Management Blocks  \n\nProficiency in scripting languages such as PERL, TCL, Python \n\nExcellent communication skills with a collaborative and team-oriented mindset \n\nAbility to quickly ramp on new systems and processes  \n\n #L1-LK1\n\nQualifications\nBE in Electrical Engineering or related +10 years of experience, or MS + 8 years of experience in AMS verification \n\n \n\n#L1-LK1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Staff Digital Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-08-20", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506108", "is_hardware": true, "platform": "oracle", "jd_text": "*Description for Internal Candidates\n \n\n     \n\nResponsibilities: \n\nOnSemi is seeking a Prin Digital design engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following: \n\n \n\nThe candidate will lead the digital design architecture, digital RTL, low power design, synthesis and timing analysis, and behavioral coding teams for the power management chips as well as executing various tool flows for IP quality control\n\nThe candidate will be able to work as part of a large and focused team of engineers and will be able to collaborate successfully as needed with design architects, digital verification, project management, and digital and analog design teams in multiple worldwide geographies\n\nDrive architecture to micro-architecture to RTL implementation with the refining of features requirements throughout the design process\n\nSupport the bring-up of various features at a system level in various pre-silicon platforms like SOCV, Emulation, FPGA.\n\nKnowledge of development of digital control peripherals, MCU systems\n\nOwn technical outcome of design, verification, implementation, and execution of Power Management ICs with complexities that can span from simple regulators to complex designs, control loops, and digital interfaces \n\nIdentify, recommend, and implement new systems, tools, processes, and technologies to improve design, reuse organizational processes and decision-making\n\nSupport post-silicon validation activities for your designs.\n\nBS in Electrical Engineering or related + 10 years of experience, or MS + 8 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments\n\nThe ideal candidate should have thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status\n\nSolid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF and system Verilog (assertion)\n\nSolid understanding of Verilog, TCL and Perl/Python/XML programming languages\n\nExperience in developing ASIC/Mixed signal ICs for various Power Converters such as multiphase converter, DC-DC PMIC/POL, AC-DC converters, LED drivers \n\nGood understanding of topologies and architectures for Constant-on-time, Peak, and Valley Current/Voltage Mode control mechanism, Hysteretic, Multi-Phase Controllers, and Smart Power Stages\n\nUnderstanding of digital architecture trade-offs for power, performance, and area\n\nMust have good written and verbal cross-functional communication skills\n\nBE/BTech in Electrical Engineering or related + 10 years of experience, or MTech + 8 years of experience\n\n#LI-RT1\n\n \n\n \n\n   \n\nResponsibilities for Internal Candidates\n \n\n     \n\nQualifications:\n\nBS in Electrical Engineering or related + 10 years of experience, or MS + 8 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments\n\nThe ideal candidate should have thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status\n\nSolid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF and system Verilog (assertion)\n\nSolid understanding of Verilog, TCL and Perl/Python/XML programming languages\n\nExperience in developing ASIC/Mixed signal ICs for various Power Converters such as multiphase converter, DC-DC PMIC/POL, AC-DC converters, LED drivers \n\nGood understanding of topologies and architectures for Constant-on-time, Peak, and Valley Current/Voltage Mode control mechanism, Hysteretic, Multi-Phase Controllers, and Smart Power Stages\n\nUnderstanding of digital architecture trade-offs for power, performance, and area\n\nMust have good written and verbal cross-functional communication skills\n\nBE/BTech in Electrical Engineering or related + 10 years of experience, or MTech + 8 years of experience\n\n#LI-RT1\n\n   \n\nQualifications for Internal Candidates\n \n\n     \n\nQualifications:\n\nBS in Electrical Engineering or related &; 10 years of experience, or MS ; 8 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments\n\nThe ideal candidate should have thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status\n\nSolid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF and system Verilog (assertion)\n\nSolid understanding of Verilog, TCL and Perl/Python/XML programming languages\n\nExperience in developing ASIC/Mixed signal ICs for various Power Converters such as multiphase converter, DC-DC PMIC/POL, AC-DC converters, LED drivers \n\nGood understanding of topologies and architectures for Constant-on-time, Peak, and Valley Current/Voltage Mode control mechanism, Hysteretic, Multi-Phase Controllers, and Smart Power Stages\n\nUnderstanding of digital architecture trade-offs for power, performance, and area\n\nMust have good written and verbal cross-functional communication skills\n\nBE/BTech in Electrical Engineering or related + 10 years of experience, or MTech + 8 years of experience\n\n#LI-RT1\n\n   \n\n   Same Posting Description for Internal and External Candidates\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Staff Digital Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-08-20", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506109", "is_hardware": true, "platform": "oracle", "jd_text": "*Description for Internal Candidates\n \n\n     \n\nResponsibilities: \n\nOnSemi is seeking a Prin Digital design engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following: \n\n \n\nThe candidate will lead the digital design architecture, digital RTL, low power design, synthesis and timing analysis, and behavioral coding teams for the power management chips as well as executing various tool flows for IP quality control\n\nThe candidate will be able to work as part of a large and focused team of engineers and will be able to collaborate successfully as needed with design architects, digital verification, project management, and digital and analog design teams in multiple worldwide geographies\n\nDrive architecture to micro-architecture to RTL implementation with the refining of features requirements throughout the design process\n\nSupport the bring-up of various features at a system level in various pre-silicon platforms like SOCV, Emulation, FPGA.\n\nKnowledge of development of digital control peripherals, MCU systems\n\nOwn technical outcome of design, verification, implementation, and execution of Power Management ICs with complexities that can span from simple regulators to complex designs, control loops, and digital interfaces \n\nIdentify, recommend, and implement new systems, tools, processes, and technologies to improve design, reuse organizational processes and decision-making\n\nSupport post-silicon validation activities for your designs.\n\nBS in Electrical Engineering or related + 10 years of experience, or MS + 8 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments\n\nThe ideal candidate should have thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status\n\nSolid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF and system Verilog (assertion)\n\nSolid understanding of Verilog, TCL and Perl/Python/XML programming languages\n\nExperience in developing ASIC/Mixed signal ICs for various Power Converters such as multiphase converter, DC-DC PMIC/POL, AC-DC converters, LED drivers \n\nGood understanding of topologies and architectures for Constant-on-time, Peak, and Valley Current/Voltage Mode control mechanism, Hysteretic, Multi-Phase Controllers, and Smart Power Stages\n\nUnderstanding of digital architecture trade-offs for power, performance, and area\n\nMust have good written and verbal cross-functional communication skills\n\nBE/BTech in Electrical Engineering or related + 10 years of experience, or MTech + 8 years of experience\n\n#LI-RT1\n\n \n\n \n\n   \n\nResponsibilities for Internal Candidates\n \n\n     \n\nQualifications:\n\nBS in Electrical Engineering or related + 10 years of experience, or MS + 8 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments\n\nThe ideal candidate should have thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status\n\nSolid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF and system Verilog (assertion)\n\nSolid understanding of Verilog, TCL and Perl/Python/XML programming languages\n\nExperience in developing ASIC/Mixed signal ICs for various Power Converters such as multiphase converter, DC-DC PMIC/POL, AC-DC converters, LED drivers \n\nGood understanding of topologies and architectures for Constant-on-time, Peak, and Valley Current/Voltage Mode control mechanism, Hysteretic, Multi-Phase Controllers, and Smart Power Stages\n\nUnderstanding of digital architecture trade-offs for power, performance, and area\n\nMust have good written and verbal cross-functional communication skills\n\nBE/BTech in Electrical Engineering or related + 10 years of experience, or MTech + 8 years of experience\n\n#LI-RT1\n\n   \n\nQualifications for Internal Candidates\n \n\n     \n\nQualifications:\n\nBS in Electrical Engineering or related + 10 years of experience, or MS + 8 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments\n\nThe ideal candidate should have thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status\n\nSolid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF and system Verilog (assertion)\n\nSolid understanding of Verilog, TCL and Perl/Python/XML programming languages\n\nExperience in developing ASIC/Mixed signal ICs for various Power Converters such as multiphase converter, DC-DC PMIC/POL, AC-DC converters, LED drivers \n\nGood understanding of topologies and architectures for Constant-on-time, Peak, and Valley Current/Voltage Mode control mechanism, Hysteretic, Multi-Phase Controllers, and Smart Power Stages\n\nUnderstanding of digital architecture trade-offs for power, performance, and area\n\nMust have good written and verbal cross-functional communication skills\n\nBE/BTech in Electrical Engineering or related + 10 years of experience, or MTech + 8 years of experience\n\n#LI-RT1\n\n   \n\n   Same Posting Description for Internal and External Candidates\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Staff Digital Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-08-20", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506110", "is_hardware": true, "platform": "oracle", "jd_text": "*Description for Internal Candidates\n \n\n     \n\nResponsibilities: \n\nOnSemi is seeking a Prin Digital design engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following: \n\n \n\nThe candidate will lead the digital design architecture, digital RTL, low power design, synthesis and timing analysis, and behavioral coding teams for the power management chips as well as executing various tool flows for IP quality control\n\nThe candidate will be able to work as part of a large and focused team of engineers and will be able to collaborate successfully as needed with design architects, digital verification, project management, and digital and analog design teams in multiple worldwide geographies\n\nDrive architecture to micro-architecture to RTL implementation with the refining of features requirements throughout the design process\n\nSupport the bring-up of various features at a system level in various pre-silicon platforms like SOCV, Emulation, FPGA.\n\nKnowledge of development of digital control peripherals, MCU systems\n\nOwn technical outcome of design, verification, implementation, and execution of Power Management ICs with complexities that can span from simple regulators to complex designs, control loops, and digital interfaces \n\nIdentify, recommend, and implement new systems, tools, processes, and technologies to improve design, reuse organizational processes and decision-making\n\nSupport post-silicon validation activities for your designs.\n\nBS in Electrical Engineering or related + 10 years of experience, or MS + 8 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments\n\nThe ideal candidate should have thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status\n\nSolid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF and system Verilog (assertion)\n\nSolid understanding of Verilog, TCL and Perl/Python/XML programming languages\n\nExperience in developing ASIC/Mixed signal ICs for various Power Converters such as multiphase converter, DC-DC PMIC/POL, AC-DC converters, LED drivers \n\nGood understanding of topologies and architectures for Constant-on-time, Peak, and Valley Current/Voltage Mode control mechanism, Hysteretic, Multi-Phase Controllers, and Smart Power Stages\n\nUnderstanding of digital architecture trade-offs for power, performance, and area\n\nMust have good written and verbal cross-functional communication skills\n\nBE/BTech in Electrical Engineering or related + 10 years of experience, or MTech + 8 years of experience\n\n#LI-RT1\n\n \n\n \n\n   \n\nResponsibilities for Internal Candidates\n \n\n     \n\nQualifications:\n\nBS in Electrical Engineering or related + 10 years of experience, or MS + 8 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments\n\nThe ideal candidate should have thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status\n\nSolid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF and system Verilog (assertion)\n\nSolid understanding of Verilog, TCL and Perl/Python/XML programming languages\n\nExperience in developing ASIC/Mixed signal ICs for various Power Converters such as multiphase converter, DC-DC PMIC/POL, AC-DC converters, LED drivers \n\nGood understanding of topologies and architectures for Constant-on-time, Peak, and Valley Current/Voltage Mode control mechanism, Hysteretic, Multi-Phase Controllers, and Smart Power Stages\n\nUnderstanding of digital architecture trade-offs for power, performance, and area\n\nMust have good written and verbal cross-functional communication skills\n\nBE/BTech in Electrical Engineering or related + 10 years of experience, or MTech + 8 years of experience\n\n#LI-RT1\n\n   \n\nQualifications for Internal Candidates\n \n\n     \n\nQualifications:\n\nBS in Electrical Engineering or related + 10 years of experience, or MS + 8 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments\n\nThe ideal candidate should have thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status\n\nSolid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF and system Verilog (assertion)\n\nSolid understanding of Verilog, TCL and Perl/Python/XML programming languages\n\nExperience in developing ASIC/Mixed signal ICs for various Power Converters such as multiphase converter, DC-DC PMIC/POL, AC-DC converters, LED drivers \n\nGood understanding of topologies and architectures for Constant-on-time, Peak, and Valley Current/Voltage Mode control mechanism, Hysteretic, Multi-Phase Controllers, and Smart Power Stages\n\nUnderstanding of digital architecture trade-offs for power, performance, and area\n\nMust have good written and verbal cross-functional communication skills\n\nBE/BTech in Electrical Engineering or related + 10 years of experience, or MTech + 8 years of experience\n\n#LI-RT1\n\n   \n\n   Same Posting Description for Internal and External Candidates\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Staff Analog Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-08-20", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506111", "is_hardware": true, "platform": "oracle", "jd_text": "*Description for Internal Candidates\n \n\n   \n\n*Description for Internal Candidates\n \n\n        \n\nonsemi is seeking a Staff Analog Design Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bangalore, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications. \n\n      \n\nResponsibilities for Internal Candidates\n \n\n        \n\nIn this role, you will focus on the following:\n\nLead multiple analog IPs with IP ownership and responsibility from definition, IP execution to release to manufacturing.\n\nAble to resolve complex analog problem and propose and implement the solution.\n\nProvide design guidance as needed, developing schedules and monitoring progress throughout the project.\n\nEvaluate intermediate and results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives.\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout.\n\nCollaborate with Design Verification teams during the pre-tapeout phase of a project to ensure completion of all technical tasks before tapeout.\n\nWork with systems engineers, application engineers and marketing and assist the team in product briefs, datasheets, application notes and assisting in the definition of the product to meet customer needs as well as contributing to roadmap formulation and new concept creation.\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production.\n\nProvide technical leadership in driving architecture design and circuit design based on high-level specifications. \n\nOwn technical outcomes of design, verification, implementation, and execution of power management ICs with complexities that can span from simple regulators to complex mixed-signal designs and control loops. \n\nUnderstand project goals, create a realistic schedule and resource plan, track execution schedule to plan, monitor progress, and provide full clarity to the team on the goals and objectives. \n\n      \n\nQualifications for Internal Candidates\n \n\n        \n\nMinimum Requirements:\n\nBS in Electrical Engineering or related plus 7 years of experience, or MS plus 5 years of experience.\n\nQualification\n\nSolid track record of delivering multiple complex IPs to manufacturing.\n\nExtensive knowledge of engineering processes, principles, and methodologies. \n\nGoal and outcome-focused with the ability to handle multiple projects within the team. \n\nAbility to attract and retain key engineering talent.\n\nExperience in simplifying complex problems into smaller problems and solving them as a team. \n\nGood understanding of various Power Converters such as Buck, Boost, LDOs, gate drivers, comparators, linear regulators gm-stage and relevant Analog building blocks. \n\nGood understanding of topologies and architectures for Constant-on-time, Peak, and Valley Current Mode, Voltage Mode, Multi-Phase Controllers, and Smart Power Stages. \n\nGood understanding of DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC devices and drivers.\n\nStrong Analog IC design skills, debug of complex silicon problems using simulations and/or bench testing. \n\nFamiliarity with advanced Bipolar, CMOS, and High Voltage BCD technology, Process, Device Physics, Semiconductor Manufacturing processes, and their impact on Analog performance. \n\nUnderstanding of large power transistor (LDMOS) Design, Layout, and Robustness. \n\nProficiency in leading-edge design and verification tools such as Simplis or MATLAB for architectural simulations, Cadence Spectre for schematic capture, simulation, layout, and tape-out. \n\nStrong verbal and written communication skills. \n\nAbility to quickly ramp on new systems and processes. \n\nDemonstrated strong interpersonal, analytical and problem-solving skills. \n\nAbility to work in teams and collaborate effectively with people in different functions. \n\nAbility to take the initiative and drive for results.\n\nResponsibilities\nQualification\n\nSolid track record of delivering multiple complex IPs to manufacturing.\n\nExtensive knowledge of engineering processes, principles, and methodologies. \n\nGoal and outcome-focused with the ability to handle multiple projects within the team. \n\nAbility to attract and retain key engineering talent.\n\nExperience in simplifying complex problems into smaller problems and solving them as a team. \n\nGood understanding of various Power Converters such as Buck, Boost, LDOs, gate drivers, comparators, linear regulators gm-stage and relevant Analog building blocks. \n\nGood understanding of topologies and architectures for Constant-on-time, Peak, and Valley Current Mode, Voltage Mode, Multi-Phase Controllers, and Smart Power Stages. \n\nGood understanding of DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC devices and drivers.\n\nStrong Analog IC design skills, debug of complex silicon problems using simulations and/or bench testing. \n\nFamiliarity with advanced Bipolar, CMOS, and High Voltage BCD technology, Process, Device Physics, Semiconductor Manufacturing processes, and their impact on Analog performance. \n\nUnderstanding of large power transistor (LDMOS) Design, Layout, and Robustness. \n\nProficiency in leading-edge design and verification tools such as Simplis or MATLAB for architectural simulations, Cadence Spectre for schematic capture, simulation, layout, and tape-out. \n\nStrong verbal and written communication skills. \n\nAbility to quickly ramp on new systems and processes. \n\nDemonstrated strong interpersonal, analytical and problem-solving skills. \n\nAbility to work in teams and collaborate effectively with people in different functions. \n\nAbility to take the initiative and drive for results.\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Senior Analog Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-08-20", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506112", "is_hardware": true, "platform": "oracle", "jd_text": "*Description for Internal Candidates\n \n\n             \n\nonsemi is seeking a Staff Analog Design Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bangalore, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications. \n\n           \n\nResponsibilities for Internal Candidates\n \n\n             \n\nIn this role, you will focus on the following:\n\nLead multiple analog IPs with IP ownership and responsibility from definition, IP execution to release to manufacturing.\n\nAble to resolve complex analog problem and propose and implement the solution.\n\nProvide design guidance as needed, developing schedules and monitoring progress throughout the project.\n\nEvaluate intermediate and results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives.\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout.\n\nCollaborate with Design Verification teams during the pre-tapeout phase of a project to ensure completion of all technical tasks before tapeout.\n\nWork with systems engineers, application engineers and marketing and assist the team in product briefs, datasheets, application notes and assisting in the definition of the product to meet customer needs as well as contributing to roadmap formulation and new concept creation.\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production.\n\nProvide technical leadership in driving architecture design and circuit design based on high-level specifications. \n\nOwn technical outcomes of design, verification, implementation, and execution of power management ICs with complexities that can span from simple regulators to complex mixed-signal designs and control loops. \n\nUnderstand project goals, create a realistic schedule and resource plan, track execution schedule to plan, monitor progress, and provide full clarity to the team on the goals and objectives. \n\n           \n\nQualifications for Internal Candidates\n \n\n             \n\nMinimum Requirements:\n\nBS in Electrical Engineering or related plus 7 years of experience, or MS plus 5 years of experience.\n\n \n\n   \n\nResponsibilities for Internal Candidates\n \n\n     \n\n      \n\n   \n\nQualifications for Internal Candidates\n \n\n     \n\n      \n\n   \n\n   Same Posting Description for Internal and External Candidates\n\nResponsibilities\nQualification\n\nSolid track record of delivering multiple complex IPs to manufacturing.\n\nExtensive knowledge of engineering processes, principles, and methodologies. \n\nGoal and outcome-focused with the ability to handle multiple projects within the team. \n\nAbility to attract and retain key engineering talent.\n\nExperience in simplifying complex problems into smaller problems and solving them as a team. \n\nGood understanding of various Power Converters such as Buck, Boost, LDOs, gate drivers, comparators, linear regulators gm-stage and relevant Analog building blocks. \n\nGood understanding of topologies and architectures for Constant-on-time, Peak, and Valley Current Mode, Voltage Mode, Multi-Phase Controllers, and Smart Power Stages. \n\nGood understanding of DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC devices and drivers.\n\nStrong Analog IC design skills, debug of complex silicon problems using simulations and/or bench testing. \n\nFamiliarity with advanced Bipolar, CMOS, and High Voltage BCD technology, Process, Device Physics, Semiconductor Manufacturing processes, and their impact on Analog performance. \n\nUnderstanding of large power transistor (LDMOS) Design, Layout, and Robustness. \n\nProficiency in leading-edge design and verification tools such as Simplis or MATLAB for architectural simulations, Cadence Spectre for schematic capture, simulation, layout, and tape-out. \n\nStrong verbal and written communication skills. \n\nAbility to quickly ramp on new systems and processes. \n\nDemonstrated strong interpersonal, analytical and problem-solving skills. \n\nAbility to work in teams and collaborate effectively with people in different functions. \n\nAbility to take the initiative and drive for results.\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Staff Analog Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-08-20", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506113", "is_hardware": true, "platform": "oracle", "jd_text": "*Description for Internal Candidates\n \n\n             \n\nonsemi is seeking a Staff Analog Design Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bangalore, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications. \n\n           \n\nResponsibilities for Internal Candidates\n \n\n             \n\nIn this role, you will focus on the following:\n\nLead multiple analog IPs with IP ownership and responsibility from definition, IP execution to release to manufacturing.\n\nAble to resolve complex analog problem and propose and implement the solution.\n\nProvide design guidance as needed, developing schedules and monitoring progress throughout the project.\n\nEvaluate intermediate and results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives.\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout.\n\nCollaborate with Design Verification teams during the pre-tapeout phase of a project to ensure completion of all technical tasks before tapeout.\n\nWork with systems engineers, application engineers and marketing and assist the team in product briefs, datasheets, application notes and assisting in the definition of the product to meet customer needs as well as contributing to roadmap formulation and new concept creation.\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production.\n\nProvide technical leadership in driving architecture design and circuit design based on high-level specifications. \n\nOwn technical outcomes of design, verification, implementation, and execution of power management ICs with complexities that can span from simple regulators to complex mixed-signal designs and control loops. \n\nUnderstand project goals, create a realistic schedule and resource plan, track execution schedule to plan, monitor progress, and provide full clarity to the team on the goals and objectives. \n\n           \n\nQualifications for Internal Candidates\n \n\n             \n\nMinimum Requirements:\n\nBS in Electrical Engineering or related plus 7 years of experience, or MS plus 5 years of experience.\n\nQualification\n\nSolid track record of delivering multiple complex IPs to manufacturing.\n\nExtensive knowledge of engineering processes, principles, and methodologies. \n\nGoal and outcome-focused with the ability to handle multiple projects within the team. \n\nAbility to attract and retain key engineering talent.\n\nExperience in simplifying complex problems into smaller problems and solving them as a team. \n\nGood understanding of various Power Converters such as Buck, Boost, LDOs, gate drivers, comparators, linear regulators gm-stage and relevant Analog building blocks. \n\nGood understanding of topologies and architectures for Constant-on-time, Peak, and Valley Current Mode, Voltage Mode, Multi-Phase Controllers, and Smart Power Stages. \n\nGood understanding of DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC devices and drivers.\n\nStrong Analog IC design skills, debug of complex silicon problems using simulations and/or bench testing. \n\nFamiliarity with advanced Bipolar, CMOS, and High Voltage BCD technology, Process, Device Physics, Semiconductor Manufacturing processes, and their impact on Analog performance. \n\nUnderstanding of large power transistor (LDMOS) Design, Layout, and Robustness. \n\nProficiency in leading-edge design and verification tools such as Simplis or MATLAB for architectural simulations, Cadence Spectre for schematic capture, simulation, layout, and tape-out. \n\nStrong verbal and written communication skills. \n\nAbility to quickly ramp on new systems and processes. \n\nDemonstrated strong interpersonal, analytical and problem-solving skills. \n\nAbility to work in teams and collaborate effectively with people in different functions. \n\nAbility to take the initiative and drive for results. \n\n   \n\nResponsibilities for Internal Candidates\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Principal Analog Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-08-20", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506114", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Principal Analog design Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following\n\n \n\n#LI-RT1\n\nResponsibilities\nLead an analog IP block from definition to IP delivery\n\nEvaluate intermediate and results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout\n\nCollaborate with Design Verification teams during the pre-tapeout phase of a project to ensure completion of all technical tasks before tapeout\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nCollaborate with overseas design and systems teams on technical aspects, IP development, sharing of know-how \n\nOwn technical outcomes of design, verification, implementation, and execution of power management ICs with complexities that can span from simple regulators to complex mixed-signal designs and control loops \n\nUnderstand project goals, create a realistic schedule and resource plan, track execution schedule to plan, monitor progress, and provide full clarity to the team on the goals and objectives \n\n#LI-RT1\n\nQualifications\nMinimum Requirements\n\nBS in Electrical Engineering or related + 7 years of experience, or MS + 5 years of experience\n\n \n\n \n\nQualification\n\n \n\nSolid track record of delivering multiple complex IPs to manufacturing\n\nExtensive knowledge of engineering processes, principles, and methodologies \n\nGoal and outcome-focused with the ability to handle multiple projects within the team \n\nAbility to attract and retain key engineering talent\n\nAbility to clearly articulate issues, challenges, and concerns to all levels of management \n\nGood understanding of various Power Converters such as Buck, Boost, LDOs, gate drivers, comparators, linear regulators gm-stage and relevant Analog building blocks \n\nGood understanding of topologies and architectures for Constant-on-time, Peak, and Valley Current Mode, Voltage Mode, Multi-Phase Controllers, and Smart Power Stages \n\nUnderstanding of DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC devices and drivers is a strong plus\n\nStrong Analog IC design skills, debug of complex silicon problems using simulations and/or bench testing \n\nFamiliarity with advanced Bipolar, CMOS, and High Voltage BCD technology, Process, Device Physics, Semiconductor Manufacturing processes, and their impact on Analog performance \n\nunderstanding of large power transistor (LDMOS) Design, Layout, and Robustness \n\nProficiency in leading-edge design and verification tools such as Simplis or MATLAB for architectural simulations, Cadence Spectre for schematic capture, simulation, layout, and tape-out \n\nStrong verbal and written communication skills \n\nAbility to quickly ramp on new systems and processes \n\nDemonstrated strong interpersonal, analytical and problem-solving skills \n\nAbility to work in teams and collaborate effectively with people in different functions \n\nAbility to take the initiative and drive for results\n\n \n\n#LI-RT1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Sr Analog Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-08-20", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506250", "is_hardware": true, "platform": "oracle", "jd_text": "onSemi is seeking a Sr Analog design Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following\n\nDesign and develop an analog IP block from definition to IP delivery\n\nDesign and simulation at the block/IP level during execution phase, present the block results to review team in timely manner.\n\nWork with and provide guidance to physical designers and monitors the progress of IP block layout\n\nWork with validation, product engineering and test engineering teams to enable them to measure Si performance\n\nOwn technical outcomes of design, verification, implementation, and execution of power management IPs with complexities that can span from simple regulators to complex mixed-signal designs and control loops \n\nAble to plan and execute the work in timely manner aligning with full chip schedule. \n\n#L1-LK1\n\nResponsibilities\nOnSemi is seeking a Sr Analog design Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following\n\nDesign and develop an analog IP block from definition to IP delivery\n\nDesign and simulation at the block/IP level during execution phase, present the block results to review team in timely manner.\n\nWork with and provide guidance to physical designers and monitors the progress of IP block layout\n\nWork with validation, product engineering and test engineering teams to enable them to measure Si performance\n\nOwn technical outcomes of design, verification, implementation, and execution of power management IPs with complexities that can span from simple regulators to complex mixed-signal designs and control loops \n\nAble to plan and execute the work in timely manner aligning with full chip schedule. \n\n#L1-LK1\n\nQualifications\nSolid track record of delivering block/IP level design \n\nSound knowledge in CMOS analog design, CMOS fundamentals and related simulation tools \n\nGood communication skills to make detailed technical presentations  \n\nGood understanding of various Power Converters such as Buck, Boost, LDOs, gate drivers, comparators, linear regulators gm-stage and relevant Analog building blocks \n\nExperience in power converters like DC/DC, AC/DC, gate drivers, PMICs etc is plus\n\nStrong Analog IC design skills, debug of complex silicon problems using simulations and/or bench testing \n\nUnderstanding of large power transistor (LDMOS) Design, Layout, and Robustness \n\nExperience in system tools such as Simplis or MATLAB for architectural simulations, Cadence Spectre for schematic capture, simulation, layout, and tape-out \n\nStrong verbal and written communication skills \n\nAbility to quickly ramp on new systems and processes \n\nDemonstrated strong interpersonal, analytical and problem-solving skills \n\nAbility to work in teams \n\n#L1-LK1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Sr Principal Analog Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-08-20", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506248", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Senior Principal Analog design Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including LED drivers, SiC/MOS/IGBT/motor/GAN drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following\n\nMentor junior Analog IC design engineers  \n\nLead multiple analog IPs with IP ownership and responsibility from definition, IP execution to release to manufacturing\n\nAble to resolve complex analog problem and propose and implement the solution\n\nProvide design guidance as needed, developing schedules and monitoring progress throughout the project\n\nEvaluate intermediate and results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout\n\nCollaborate with Design Verification teams during the pre-tapeout phase of a project to ensure completion of all technical tasks before tapeout\n\nWork with systems engineers, application engineers and marketing assisting in the definition of the product to meet customer needs as well as contributing to roadmap formulation and new concept creation\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nProvide technical leadership in driving architecture design and circuit design based on high-level specifications \n\nOwn technical outcomes of design, verification, implementation, and execution of power management ICs with complexities that can span from simple regulators to complex mixed-signal designs and control loops \n\nUnderstand project goals, create a realistic schedule and resource plan, track execution schedule to plan, monitor progress, and provide full clarity to the team on the goals and objectives.\n\n#LI-RG1\n\nQualifications\nMinimum Requirements\n\nBS in Electrical Engineering or related + 14 years of experience, or MS + 12 years of experience\n\nQualification\n\nSolid track record of delivering multiple complex IPs with Si learnings\n\nExtensive knowledge of engineering processes, principles, and methodologies \n\nGoal and outcome-focused with the ability to handle multiple projects within the team \n\nAbility to provide technical mentorship\n\nExperience in simplifying complex problems into smaller problems and solving them as a team \n\nGoodunderstanding of various drivers like SiC/GAN/LED, smartFET / Efuses and relevant Analog building blocks \n\nStrong Analog IC design skills, debug of complex silicon problems using simulations and/or bench testing \n\nFamiliarity with advanced Bipolar, CMOS, and High Voltage BCD technology, Process, Device Physics, Semiconductor Manufacturing processes, and their impact on Analog performance \n\nunderstanding of power transistor Design, Layout, and Robustness \n\nProficiency in leading-edge design and verification tools such as Simplis or MATLAB for architectural simulations, Cadence Spectre for schematic capture, simulation, layout, and tape-out \n\nStrong verbal and written communication skills \n\nAbility to quickly ramp on new systems and processes \n\nDemonstrated strong interpersonal, analytical and problem-solving skills \n\nAbility to work in teams and collaborate effectively with people in different functions \n\nAbility to take the initiative and drive for results \n\n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Staff Analog Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-08-20", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506363", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Staff Analog design Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including WBG Drivers (SiC, GaN), LED drivers, Switches/efuses/Hotswap controllers, DC-DC PMIC/POL, Multiphase controllers, Dr. MOS for consumer, industrial and automotive applications. In this role, you will focus on the following.\n\nDesign and develop a complex analog IP or lead a couple of analog block from definition to IP delivery\n\nDesign and simulation at the block/IP level during execution phase, present the block results to review team in timely manner.\n\nWork with and provide guidance to physical designers and monitors the progress of IP block layout\n\nWork with validation, product engineering and test engineering teams to enable them to measure Si performance\n\nOwn technical outcomes of design, verification, implementation, and execution of power management IPs with complexities that can span from simple regulators to complex mixed-signal designs and control loops \n\nAble to plan and execute the work in timely manner aligning with full chip schedule. \n\n#LI-RG1\n\nResponsibilities\nDesign and develop a complex analog IP or lead a couple of analog block from definition to IP delivery\n\nDesign and simulation at the block/IP level during execution phase, present the block results to review team in timely manner.\n\nWork with and provide guidance to physical designers and monitors the progress of IP block layout\n\nWork with validation, product engineering and test engineering teams to enable them to measure Si performance\n\nOwn technical outcomes of design, verification, implementation, and execution of power management IPs with complexities that can span from simple regulators to complex mixed-signal designs and control loops \n\nAble to plan and execute the work in timely manner aligning with full chip schedule.\n\n#LI-RG1\n\nQualifications\nBS in Electrical Engineering or related 8+ years of experience, or MS 6+ years of experience\n\nQualification\n\nSolid track record of delivering block/IP level design \n\nSound knowledge in CMOS analog design, CMOS fundamentals and related simulation tools \n\nGood communication skills to make detailed technical presentations  \n\nGood understanding of various Power Converters such as Buck, Boost, LDOs, gate drivers, comparators, linear regulators gm-stage and relevant Analog building blocks \n\nExperience in WBG Drivers (SiC, GaN), LED drivers, Switches/efuses/Hotswap controllers will be a plus\n\nStrong Analog IC design skills, debug of complex silicon problems using simulations and/or bench testing \n\nUnderstanding of large power transistor (LDMOS) Design, Layout, and Robustness \n\nExperience in system tools such as Simplis or MATLAB for architectural simulations, Cadence Spectre for schematic capture, simulation, layout, and tape-out \n\nStrong verbal and written communication skills \n\nAbility to quickly ramp on new systems and processes \n\nDemonstrated strong interpersonal, analytical and problem-solving skills \n\nAbility to work in teams\n\n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Staff Verification Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-08-20", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506364", "is_hardware": true, "platform": "oracle", "jd_text": "We are seeking an experienced ASIC Verification Engineer to join our dynamic team. As a verification engineer, you will play a crucial role in ensuring the quality and reliability of our cutting-edge semiconductor designs. If you thrive in a collaborative environment and have a passion for solving complex challenges, this role is for you.\n\nResponsibilities:\n\nVerification Planning and Execution:\n\nDevelop and execute comprehensive verification plans.\n\nClose verification with coverage closure, ensuring high-quality results.\n\nApply standard ASIC verification techniques, including test planning, testbench creation, code and functional coverage, directed and random stimulus generation, and assertions.\n\nTestbench Development:\n\nCreate and enhance testbenches using SystemVerilog (OVM/UVM) or other standard testbench languages.\n\nImplement reusable Verification IP (VIP) components.\n\nCollaborate with third-party VIP providers.\n\nMethodology and Flows:\n\nDemonstrate a solid understanding of ASIC design and verification methodologies.\n\nApply object-oriented programming principles effectively.\n\nImplement constraint random verification methodology.\n\nTechnical Skills:\n\nProficiency in SystemVerilog (OVM/UVM) and other relevant languages (C/C++, Perl, Tcl, Python, Verilog PLI).\n\nFamiliarity with industry standards (e.g., I2C/SPI).\n\nExperience with low-power verification using UPF (Unified Power Format) is a plus.\n\nKnowledge of formal verification techniques is advantageous.\n\nCollaboration and Communication:\n\nWork effectively with internal teams and external customers.\n\nStrong written and verbal communication skills.\n\nInitiative, analytical problem-solving abilities, and adaptability within a diverse team environment.\n\n#LI-RG1\n\nQualifications\nBachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or related fields.\n\n7 Years experience in design verification using SV/UVM based test-benches\n\nProven track record in complex ASIC verification.\n\nPassion for solving challenging problems and ensuring product reliability.\n\n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "SoC Lead - Senior Principal Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-20", "url": "https://careers.arm.com/job/bengaluru/soc-lead-senior-principal-engineer/33099/99480638544", "is_hardware": true, "platform": "talentbrew", "jd_text": "Solutions Engineering is at the forefront of developing ground breaking SoC/SiP (System-on-Chip / System-in-Package) solutions across a wide range of market segments including Cloud Ai, Edge AI, and Physical AI.\nIn this critical leadership role, you will coordinate and be responsible for the development of high-performance SoCs from concept through product launch. This is a deeply technical position requiring end-to-end expertise and the ability to operate across functional and geographic boundaries. You will orchestrate multi-functional technical execution and help shape Arm’s future in advanced semiconductor technologies such as 2.5D/3D integration and sub-2nm process nodes.\nResponsibilities:\nProduct Definition: Partner with line-of-business and architecture teams to define product requirements and success criteria.\nTechnical leadership: Drive alignment across architecture, front-end development, physical implementation, packaging, software, silicon validation, test, product engineering, quality, and post-silicon operations\nExecution Ownership: Serve as the technical point of contact for the assigned product(s), both internally and externally, throughout the development lifecycle\nProgram Planning: Assess required engineering resources and competencies, propose execution timelines, and supervise program health\nChange control: Scrutinize the feature improvement requests and lead the engineering change order process\nContinuous Improvement: Conduct technical capability assessments and feed insights back into tools, methodologies, and team development plans.\nRequired Skills:\nBachelors, Masters, or Ph.D. degree or experience in Electrical Engineering or Computer Engineering, with a strong computer architecture, design and product engineering background.\nDirect experience of the full ASIC development lifecycle, from architecture to silicon bring-up and post-silicon commercialization.\nProven success in owning the architecture, and development of complex SoCs, ideally across multiple market segments\nUnderstanding of Arm-based SoC architecture, compute IPs, interconnect, low-speed and speed peripheral interfaces.\n“Nice To Have” Skills :\nExcellent interpersonal skills, strong initiative and open in engaging and learning new concepts and sharing with collaborators\nProven ability in product definition, architecture, design, system SW and silicon validation.\nFamiliarity with product lifecycle management, including early-stage concept development and go-to-market readiness.\nIn Return:\nWe are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to surpass ordinary and shape outstanding!\n \n10x Mindset at Arm\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Read more about how we bring the 10x mindset to life on the Arm blog.\n\n #LI-SC2 \nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "PDK Engineer Extraction Development", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-08-20", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/PDK-Engineer-Extraction-Development_JR0286519", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact:\n\nAs a Process Design Kit (PDK) Engineer, you will play a pivotal role in developing and ensuring the quality of PDK collateral that enables cutting-edge silicon designs. You will be responsible for maintaining and validating design environments for specific technology nodes, working on parasitic extraction, physical verification, and design methodologies to set the foundation for high-quality, efficient design flows. This role is integral to advancing Intel's product lines and ensuring seamless collaboration across design and manufacturing teams.\n\nBusiness Group:\n\nYou will join the Design Technology Platform Enablement group, which focuses on creating world-class design environments to support Intel's advanced process technologies. This group collaborates with design teams, EDA vendors, and technology development experts to deliver high-quality design tools and methodologies that drive innovation across Intel's product offerings.\n\nKey Responsibilities:\n\n- Develop and maintain PDK collateral, including Metal R and C extraction, runsets, LVS , physical design verification decks, and modeling transistors for silicon designers.\n- Perform validation for PDK libraries, ensuring compliance with design rules and correct implementations for advanced process nodes.\n- Build test structures and simulate physical verification, parasitic extraction, and device modeling to deliver high-quality design solutions.\n- Collaborate with stakeholders to resolve PDK-related issues, including debugging, root cause analysis, and error dispositioning.\n- Drive automation and scalability by developing QA methodologies and tools to enhance coverage across technology nodes.\n- Partner with EDA vendors to enable new tool functionalities and improve design workflows.\n- Document and deliver design flows, guidelines, and tutorials to optimize usability for internal and external design communities.\n- Engage with cross-functional teams to support new process development and ensure ease of use for the design ecosystem.\n\nQualifications:\nMinimum Qualifications:\n\n- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with 12+ years of experience; OR Master's degree with 10+ years of experience; OR Ph.D. with 8+ years of experience in PDK development and validation.\n- Hands-on expertise in physical verification tools such as Calibre, Pegasus, or ICV, and parasitic extraction tools such as StarRC or QRC.\n- Proficiency in scripting languages such as Python, TCL, or PERL for automation and workflow optimization.\n- Demonstrated experience with PDK enablement for advanced process nodes, including device modeling and layout verification methodologies.\n\nPreferred Qualifications:\n\n- Familiarity with reliability verification techniques, including EM/IR flows and ESD concepts.\n- Knowledge of CMOS device physics, process technology, and design rules.\n- Experience with 3DIC flow methodologies and low-power techniques.\n- Strong organizational, presentation, and communication skills to collaborate effectively with cross-functional teams and vendors.\n\nWe're looking for innovative, detail-oriented individuals who thrive in dynamic environments and are eager to make a meaningful impact on Intel's design technology platform. Join us and be part of a team that drives technological excellence and shapes the future of semiconductor innovation.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Senior Verification Engineer, PCIE", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-20", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer--PCIE_JR2023401", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science.\n\nThe GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nBe responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nExpected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.\n\nYou will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech or equivalent experience\n\n5+ years of relevant experience\n\nExperience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog\n\nExpertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)\n\nExperience in developing and working in functional coverage based constrained random verification environments\n\nBackground in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nExcellent knowledge of PCIE protocol - Gen3 and above\n\nGood understanding of the system level architecture of PCIE/CXL-based designs\n\nPerl, Python or similar scripting and SW programming language experience\n\nGood debugging and analytical skills\n\nGood interpersonal skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "IP Verification Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-20", "url": "https://careers.arm.com/job/bengaluru/ip-verification-engineer/33099/99500560928", "is_hardware": true, "platform": "talentbrew", "jd_text": "Overview\nThe ARM Solutions Engineering Technology and IP team is seeking talented IP Verification Engineers across multiple experience levels, from engineers developing their verification expertise through to experienced Staff Engineers capable of owning complex IP and subsystem verification programs.\n \nThese roles provide opportunities to work across a broad portfolio of technologies, including high-speed I/O, PCI Express (PCIe), DDR and memory interfaces, interconnect, compute and control subsystems, and security IP.\n \nDepending on experience and role level, engineers may contribute to verification environment development, test creation and debug, own verification of an IP or major feature, lead subsystem-level verification, or provide technical direction across projects and teams.\n \nYou will collaborate with architecture, design, implementation, firmware, performance, and SoC integration teams to deliver robust, reusable, and production-ready IP for next-generation SoCs.\nOpportunities Across Experience Levels\nWe are hiring for multiple individual-contributor positions and will align responsibilities with the successful candidate's experience, technical depth, and ownership capability.\nVerification Engineer\nEngineers at this level will typically:\nDevelop tests, sequences, assertions, checkers, and functional coverage.\nDebug simulation and regression failures with support from experienced team members.\nContribute to SystemVerilog/UVM verification environments.\nTranslate defined requirements and test-plan items into verification collateral.\nSupport coverage analysis, regression triage, and bug investigation.\nBuild knowledge of IP architecture, protocols, verification methodology, and product-development processes.\nMinimum of 4 years of professional experience required. \nSenior Verification Engineer\nSenior engineers will typically:\nOwn verification of significant IP features or functional areas.\nDevelop verification strategies, test plans, coverage models, and reusable verification components.\nLead complex debug involving RTL, testbench, firmware, protocol, and integration behavior.\nDrive functional, code, assertion, and scenario coverage toward closure.\nReview specifications and designs to identify verification risks, ambiguities, and corner cases.\nMentor less-experienced engineers and improve verification methodology and automation.\nCoordinate verification activities with design, architecture, firmware, and implementation teams.\nMinimum of 8 years of professional experience required.\nStaff Verification Engineer\nStaff engineers will typically:\nLead end-to-end verification of complex IPs, subsystems, or major functional areas.\nDefine verification architecture, methodology, reuse strategy, and sign-off criteria.\nIdentify technical and schedule risks early and drive mitigation across teams.\nInfluence IP architecture and design through verification insights, modeling, and early analysis.\nLead verification planning across projects, configurations, and customer use cases.\nDrive reuse of verification collateral from IP level through subsystem and SoC integration.\nProvide technical guidance, mentor engineers, and lead complex debug and coverage-closure efforts.\nCollaborate with engineering and program teams on execution strategy, dependencies, risks, and delivery commitments.\nImprove verification quality, scalability, automation, and engineering practices across the team.\nMinimum of 10 years of professional experience required. \nResponsibilities\nResponsibilities will vary by role level and may include:\nDeveloping verification strategies, test plans, and coverage plans from architecture and design specifications.\nBuilding and maintaining reusable SystemVerilog/UVM verification environments, agents, scoreboards, reference models, assertions, and coverage models.\nVerifying IP and subsystems such as high-speed interfaces, PCIe, DDR and memory controllers, interconnect, embedded processor systems, and security hardware.\nCreating constrained-random, directed, protocol-compliance, error-injection, low-power, and performance-oriented tests.\nDriving functional, code, assertion, and scenario coverage to closure.\nDebugging failures across RTL, testbench, firmware, and system-level interactions.\nVerifying multi-clock, multi-reset, and multi-power-domain behavior.\nSupporting hardware and firmware co-verification, including boot, initialization, configuration, interrupt, error-handling, and recovery flows.\nContributing to verification automation, regression infrastructure, dashboards, and continuous-integration flows.\nImproving verification methodologies, reusable components, coding practices, and sign-off criteria.\nParticipating in architecture, specification, design, test-plan, and coverage reviews.\nMentoring engineers and providing technical guidance appropriate to the role level.\nRequired Skills and Experience\nThe depth and breadth expected in each area will depend on the position level.\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.\nUnderstanding of digital design, Verilog/SystemVerilog RTL, and simulation-based verification.\nExperience with SystemVerilog, UVM, or comparable verification methodologies.\nExperience with verification planning, stimulus development, functional coverage, assertions, scoreboards, and debug.\nUnderstanding of SoC and IP architecture, including clocking, reset, interrupts, address maps, memory-mapped interfaces, and system integration.\nFamiliarity with one or more protocols or technology areas such as AXI, AHB, APB, CHI, PCIe, DDR, high-speed I/O, interconnect, processor subsystems, or security IP.\nExperience with scripting or programming languages such as Python, Perl, TCL, Bash, C, or C++.\nAbility to collaborate across teams and communicate technical information clearly.\nDemonstrated ownership and technical leadership appropriate to the experience level of the role.\nYears of experience indicated above required.\nDesirable Skills and Experience\nExperience in one or more of the following areas would be beneficial:\nPCIe controllers, transaction layers, link management, protocol compliance, and error recovery.\nDDR controllers, memory PHY interfaces, training, initialization, scheduling, and reliability features.\nHigh-speed serial interfaces, coherent or non-coherent interconnect, cache, and memory subsystems.\nSecurity IP, including hardware roots of trust, secure boot, cryptography, key management, lifecycle management, access control, and secure debug.\nEmbedded processor systems and hardware/firmware co-verification.\nLow-power verification using UPF, power-state modeling, isolation, retention, and reset sequencing.\nFormal verification, assertion-based verification, Portable Stimulus, reference models, emulation, or acceleration.\nVerification at IP, subsystem, and SoC levels.\nPerformance verification, traffic modeling, stress testing, and bottleneck analysis.\nFamiliarity with ARM-based designs and ARM system architectures.\n#LI-KS1\nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Verification Engineer - PCIE", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-20", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Verification-Engineer---PCIE_JR2023402", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n\nAt NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nResponsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nExpected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.\n\nYou will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech. with 2+ years of relevant experience\n\nExperience in verification at Unit/Sub-system/SOC level using Verilog and SystemVerilog\n\nBackground with verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)\n\nExperience in developing and working in functional coverage based constrained random verification environments\n\nExperience in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nExcellent problem solving skills\n\nKnowledge of PCIE protocol - Gen3 and above\n\nProficiency in Testbench development using SystemVerilog\n\nPerl, Python or similar scripting and SW programming language experience\n\nGood debugging and analytical skills\n\nGood interpersonal skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, Nvidia is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Post Silicon Validation Engineers", "company": "Samsung", "location": "SSIR, Goldstone, Bangalore, India", "date_posted": "2026-08-20", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/SSIR-Goldstone-Bangalore-India/Post-Silicon-Validation-Engineers_R119744", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nAbout Samsung Semiconductor India Research\nWith a wide range of industry-leading semiconductor solutions, we’re enabling innovative growth in market segments from hyperscale data centers and automotive to IoT, mobile and consumer electronics. SSIR, Bangalore is the largest R&D center outside Korea for Samsung Electronics and we take pride in our ability to work on some of the cutting edge technologies that our parent organization ventures into.\nRole and Responsibilities\n\nJob Description\nSSIR is now hiring Post-Silicon Validation Engineers with 3-19 years’ experience. You will apply your technical expertise to validate next generation mobile Exynos SoCs ensuring their functional correctness and production quality.\n\nRole and Responsibilities\nFormulate, review and execute the silicon validation test plans\n\nDevelop functional tests targeting new IP features\n\nPerform electrical characterization\n\nWork with industry standard tools and silicon/board test equipment\n\nDebug HW issues that arise during the post-silicon development phase\n\nWork closely with software and hardware design teams ensuring that the commercialisation goals are met\n\nSupport customers by debugging and root-causing issues with returned merchandise and documenting necessary corrective actions\n\nDocument and communicate results regularly with project management personnel\n\nMinimum Qualifications\nBachelors Degree in Engineering\n\nFundamentals of digital and analog electronics\n\n3-15 years experience in post-silicon validation or embedded/bare-metal programming and system debugging\n\nExcellent knowledge of modern SOC architecture and memory hierarchy\n\nExperience with ARM based embedded/firmware programming\n\nGood embedded C programming skills\n\nExperience with debugging programs during run-time using Lauterbach Trace32 or similar JTAG based debuggers\n\nGood to Have\nExperience with basic test equipment: Oscilloscopes, logic analyzers, and protocol analyzers\n\nValidation or verification experience in any of these areas: CPU, GPU, NPU, Power, Clock, Memory, Modem, High Speed and Low Speed Peripherals, Timers and Interrupts, Security\n\nCMM programming for Lauterbach Trace32\n\nSkills and Qualifications\n\nExperience: 3 – 14 years\n\nEducation: B.E / B.Tech / M.E / M.Tech\n\n        By submitting this application, I confirm that I will not disclose or use proprietary information, trade secrets or confidential materials obtained from or belonging to my current or past employers during the recruitment process or future employment with Samsung Semiconductor India Research, a division of Samsung R &D Institute India Bangalore Private Limited\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "SoC HW Systems Engineer — Packaging & IO ", "company": "Infineon", "location": "Bangalore (India)", "date_posted": "2026-08-19T11:26:48+00:00", "url": "https://jobs.infineon.com/careers/job/563808971261568", "is_hardware": true, "platform": "eightfold", "jd_text": "Our Automotive Microcontroller R&D team\nis looking for an experienced SoC HW Systems Engineer to join the Chip-Level\nArchitecture team and own the package, ballout, and IO interface strategy for\nour next-generation automotive microcontroller platform.\n\nYour role\nKey responsibilities in your new role\n\n·        \nOwn the package selection\nstrategy, ballout architecture, and IO ring planning for our next-generation uC\nplatform.\n\n·        \nAnalyze and consolidate\ncustomer PCB design constraints and system-level integration requirements to\ndrive chip-level packaging decisions.\n\n·        \nReview and maintain the\nplatform ballout map, providing technical feedback across stakeholder teams\nincluding implementation, PHY vendors, and customers.\n\n·        \nDrive the datasheet content for\nIO electrical parameters and system-level interface specifications in\ncollaboration with IP teams and customers.\n\n·        \nVerify PHY and PMIC\ncompatibility with the platform through model-based simulation and parasitic\nanalysis.\n\n·        \nAssess package performance vs.\ncost tradeoffs and maintain the holistic picture of package constraints versus\ncustomer system needs across the full product family.\n\n·        \nMaintain technical\ndocumentation in compliance with ISO 26262 requirements.\n\nYour profile\nQualifications and skills to help you succeed \n\n·         Bachelor's or Master's degree\nin Electrical Engineering or related field.\n·         At least 7 years of industry\nexperience in semiconductor product development with a background in analog\ndesign, package engineering, or SoC system-level design.\n·         Good knowledge of package types\n(LFBGA, TFBGA, QFP) and package parasitic modeling.\n·         Experience with PCB\nsystem-level design constraints and customer board integration requirements.\n·         Understanding of IO ring\narchitecture — pad types, ESD protection strategies, IO power domains.\n·         Familiarity with ballout\nplanning, signal grouping principles, and PCB routing constraints for\nautomotive microcontrollers.\n·         Familiarity with ISO 26262\ndocumentation standards.\n·         Pro-active collaborative\nattitude with strong communication skills in a global multi-cultural team.\n\n·        Fluent English required; German\nis a plus.\nYou\nare best equipped for this task if you have:\n\n·        Experience reviewing package\nroadmaps and translating customer system constraints into chip-level package\nand ballout requirements.\n·         Hands-on experience with signal\nintegrity simulation at package level and model-based PHY/PMIC compatibility\nverification.\n·         Contributed to ballout map\ncreation, reviewed platform ballout with stakeholders, and managed feedback\ncycles with package vendors.\n·         Worked on datasheet electrical\nparameter content for IO and system-level interface specifications.\n·         Experience driving BOM analysis\nfor the full system solution around the microcontroller.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "SoC High-Speed Interface Architect", "company": "Infineon", "location": "Bangalore (India)", "date_posted": "2026-08-19T11:21:31+00:00", "url": "https://jobs.infineon.com/careers/job/563808971261567", "is_hardware": true, "platform": "eightfold", "jd_text": "Our Automotive Microcontroller R&D team\nis looking for an experienced SoC High-Speed Interface Architect to join the\nChip-Level Architecture team and own the chip-level integration architecture\nfor high-speed interface PHYs on our next-generation automotive microcontroller\nplatform. This is an SoC architecture role — not an IP design role — focused on\nhow high-speed PHYs land on the chip, meet electrical constraints, and\nintegrate with the platform.\n\nYour role\nKey responsibilities in your new role\n\n·        Own the SoC-level integration\narchitecture for high-speed interface PHYs (LPDDR, Ethernet PHY, HSPHY) —\ndefining placement strategy, power delivery, reference clock assignment, and\nelectrical compliance requirements.\n·        Define and maintain the\nchip-level interface specifications that high-speed PHY IP teams must comply\nwith, including jitter budgets, termination requirements, and signal integrity\nconstraints.\n·        Serve as the primary SoC\narchitecture interface to PHY IP teams and external PHY vendors — driving\nintegration feasibility assessments and resolving chip-level signal integrity\nissues.\n·        Perform or oversee early signal\nintegrity simulation and parasitic analysis for high-speed interface regions of\nthe chip.\n·        Review and provide\narchitectural sign-off on PHY IP integration results, floorplan proposals, and\nhigh-speed IO region design decisions.\n·        Maintain technical architecture\ndocumentation in compliance with ISO 26262 requirements.\n·        Drive datasheet content for\nhigh-speed interface electrical parameters in collaboration with IP teams and\ncustomers.\n\nYour profile\nQualifications and skills to help you succeed \n\n·         Bachelor's or Master's degree\nin Electrical Engineering or related field.\n·         At least 10 years of industry\nexperience in semiconductor development with proven experience in high-speed\ninterface architecture or integration.\n·         Strong knowledge of high-speed\ninterface PHYs — LPDDR memory PHY, Ethernet PHY, and high-speed serial\ninterfaces (HSPHY/SerDes).\n·         Experience with chip-level\nsignal integrity, jitter budgets, and eye diagram analysis for high-speed\ninterfaces.\n·         Understanding of PHY placement\nconstraints, power delivery requirements, and reference clock architecture for\nhigh-speed interfaces.\n·         Familiarity with IO ring\narchitecture and ESD protection strategy at high-speed IO boundaries.\n·         Familiarity with ISO 26262\ndocumentation standards.\n·         Pro-active collaborative\nattitude with strong communication skills in a global multi-cultural team.\n·         Fluent English required; German\nis a plus.\n\nYou\nare best equipped for this task if you have:\n·         Owned chip-level integration\narchitecture for LPDDR, Ethernet PHY, or high-speed SerDes in a previous SoC\nprogram.\n·         Defined jitter budgets, power\ndelivery specs, and placement constraints for high-speed PHYs at the SoC level.\n·         Worked with PHY IP vendors to\nestablish interface specifications, simulation models, and integration\nacceptance criteria.\n·         Experience distinguishing\nSoC-level integration constraints from IP-internal design decisions — and\ndriving the former without dictating the latter.\n·         Contributed to datasheet\nelectrical parameters for high-speed interface sections.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "NOC IP Digital Design Engineer", "company": "Infineon", "location": "Bangalore (India)", "date_posted": "2026-08-19T11:06:40+00:00", "url": "https://jobs.infineon.com/careers/job/563808971169930", "is_hardware": true, "platform": "eightfold", "jd_text": "Join a high-impact team developing next-generation automotive SoCs. Contribute to NoC IP integration, RTL design, connectivity validation, and automation, while collaborating with architecture, verification, and integration teams to deliver robust, high-quality silicon solutions. Ideal for engineers passionate about digital design, debugging, and chip-level integration.\n\nYour role\nKey responsibilities in your new role\n\nSupport NoC IP microarchitecture, RTL integration, and configuration activities under the guidance of senior engineers\nContribute to NoC design implementation, connectivity checks, and quality validation for automotive SoCs\nParticipate in design reviews and work closely with architecture, integration, and verification teams\nDebug RTL and connectivity issues, support status reporting, and help close design quality gaps\nWork on automation and scripting improvements to enhance team productivity and design efficiency\nHelp define and validate chip-level connectivity and integration concepts for automotive microcontroller products\nLearn and apply best practices in digital design, integration, and design methodology across project teams\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor's/Master's degree in Electrical/ Electronic Engineering or a related discipline\n5 to 7 years of industry experience in semiconductor product development and proven execution in digital RTL/SoC design or integration\nGood understanding of NoC micro architecture, RTL integration, and SoC connectivity concepts\nWorking knowledge of AMBA protocols such as AHB/AXI/APB and experience with interconnect-related design flows\nStrong fundamentals in digital design, RTL coding, simulation, debugging, and design quality checks\nExposure to SystemVerilog/Verilog and ASIC/SoC design methodologies\nAbility to work effectively in a global, fast-paced team with good communication and collaboration skills\nExperience in UNIX/Windows environments, MS Office tools, and version control systems such as GIT Bachelor's/Master's degree in Electrical/ Electronic Engineering or a related discipline\n5 to 7 years of industry experience in semiconductor product development and proven execution in digital RTL/SoC design or integration\nGood understanding of NoC micro architecture, RTL integration, and SoC connectivity concepts\nWorking knowledge of AMBA protocols such as AHB/AXI/APB and experience with interconnect-related design flows\nStrong fundamentals in digital design, RTL coding, simulation, debugging, and design quality checks\nExposure to SystemVerilog/ Verilog and ASIC/SoC design methodologies\nAbility to work effectively in a global, fast-paced team with good communication and collaboration skills\nExperience in UNIX/Windows environments, MS Office tools, and version control systems such as GIT \nExposure to architecture feasibility analysis,\nintegration trade-offs, and design reviews\nUnderstanding of RTL implementation flows, debug\ntechniques, and connectivity clean-up activities\nFamiliarity with simulation tools such as\nVCS/Xcelium/ModelSim and design verification workflows\nA proactive attitude toward learning, problem\nsolving, and improving design automation\nBasic to intermediate experience in NoC design and\nintegration, including multi-clock and multi-power domains\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Principal Engineer Verification", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-08-19T09:34:10+00:00", "url": "https://jobs.infineon.com/careers/job/563808971792093", "is_hardware": true, "platform": "eightfold", "jd_text": "#WeAreIn to make sure that our circuits are designed to perfection. Are you in?\n\nYour role\nKey responsibilities in your new role\n\nCollaborate with Silicon Validation and Characterization teams to gather, analyze, and understand test requirements.\nDevelop comprehensive test plans, test cases, and automation frameworks, including supporting software and firmware for silicon validation.\nPerform validation activities on FPGA platforms (pre-silicon) and silicon devices, working closely with cross-functional teams to identify, debug, and resolve issues.\nDesign and implement Python and LabVIEW-based automation solutions for bench test equipment to support silicon validation and characterization activities.\nDrive project execution by managing schedules, coordinating deliverables, and collaborating with cross-functional stakeholders when serving in a Program Manager role.\nEnsure efficient test coverage, data collection, and reporting to support product quality and performance objectives.\nContribute to continuous improvement of validation methodologies, automation frameworks, and testing processes.\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor's or Master's degree in Electronics, Computer Science, or a related field.\n\n13+ years of experience with microcontrollers and SoC (System-on-Chip) products.\nStrong experience in bench characterization of Analog, Digital, and Mixed-Signal IPs.\nHands-on expertise with laboratory equipment, including SMUs, DMMs, oscilloscopes, and signal generators.\nProficiency in C, Python, and LabVIEW programming languages; LabVIEW experience is highly desirable.\nSolid understanding of voltage regulators, reference circuits, and precision measurement techniques.\nExcellent communication, collaboration, and interpersonal skills.\nStrong analytical and problem-solving abilities with a detail-oriented approach.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Sr. Staff Post Silicon Validation Apps Engineer - SOC/IP, HSIO", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-08-19T08:46:00+00:00", "url": "https://global-external-amd.icims.com/jobs/89515/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. SENIOR STAFF POST SILICON VALIDATION APPS ENGINEER THE ROLE: AMD is looking for a highly experienced Senior Member of Technical Staff (SMTS) to join the Embedded x86 Applications Engineering organization and serve as a technical leader for customer enablement, post-silicon validation, system debug, platform qualification, and technical escalation management. This role serves as the senior technical bridge between customers, FAEs, Product Management, Program Management, Silicon Engineering, Platform Engineering, BIOS/Firmware Engineering, Validation, Quality, and Customer Support organizations. The SMTS Engineer will provide technical leadership across complex customer engagements, drive resolution of high-impact escalations, influence validation and debug methodologies, and help define support and qualification strategies across AMD Embedded x86 platforms. The role requires deep platform expertise, exceptional debugging skills, strong customer engagement capabilities, and the ability to influence cross-functional engineering organizations without direct authority. THE PERSON: The ideal candidate is a recognized technical leader with extensive post-silicon validation and platform debug experience, a strong customer-first mindset, and a proven track record of driving complex technical issues to closure. This person is comfortable operating in highly ambiguous environments, leading root-cause investigations, mentoring engineers, influencing engineering priorities, and representing AMD in strategic customer engagements. Strong executive-level and customer-facing communication skills. Deep technical expertise in platform validation and system architecture. Ability to influence technical direction across engineering organizations. Recognized problem solver for complex platform and interoperability issues. Strong leadership and mentoring capabilities. Comfortable interacting with customers, engineering directors, architects, validation leads, and executive stakeholders. Ability to balance customer urgency with engineering execution discipline. Demonstrated ownership mindset and accountability. A self-starter capable of independently driving highly complex technical investigations while providing technical leadership to broader validation and applications engineering teams.   KEY RESPONSIBILITIES: Strategic Customer Technical Ownership Serve as the senior technical lead for customer escalations involving AMD Embedded x86 platforms. Act as the primary technical escalation point for high-priority and business-critical customer issues. Provide technical leadership across customer engagements, platform enablement activities, and production deployments. Influence customer adoption, platform readiness, and long-term customer success. Technical Leadership Provide technical leadership and mentoring to MTS engineers and validation teams. Drive best practices for validation, debugging, escalation management, and customer engagement. Lead cross-functional investigations involving multiple engineering organizations. Establish debug methodologies and root-cause frameworks for complex platform issues. Post Silicon Validation Leadership Define validation strategies for customer-reported issues. Lead validation activities for new platforms, features, and customer deployments. Drive interoperability, qualification, compatibility, and production-readiness efforts. Review and improve validation coverage based on field learnings and customer feedback. Advanced Platform Debug & Root Cause Analysis Lead investigations involving: PCIe Gen4/Gen5,DDR4/DDR5,Memory training and validation,USB,Networking,Storage and NVMe,Graphics and Display,RAS technologies,Platform security, Silicon-to-system interactions Escalation Management Lead engineering escalations for customer-critical issues. Partner with BIOS, Firmware, Silicon, Validation, Product, and Quality teams to drive issue resolution. Review and approve escalation strategies and debug plans. Ensure engineering teams receive complete technical analysis and reproduction data. Continuous Improvement & Innovation Drive automation initiatives for validation and debug workflows. Identify support-deflection opportunities through improved validation coverage and documentation. Influence platform quality improvements using customer and field feedback. Contribute to AMD technical strategies for product quality and customer success. PREFERRED EXPERIENCE: 13+ years of experience in Applications Engineering, Post Silicon Validation, Platform Validation, Product Validation, Embedded Systems, Customer Engineering, Silicon Validation, or related technical roles. Extensive hands-on experience debugging x86 or embedded platforms. Strong expertise in: Proven experience leading customer-facing technical engagements. Demonstrated ability to drive high-priority escalations across multiple engineering organizations. Strong platform-level debug skills spanning silicon, firmware, BIOS, operating systems, drivers, hardware, and validation domains. Experience with debug tools including protocol analyzers, logic analyzers, oscilloscopes, JTAG, firmware traces, and crash dump analysis. Strong Linux and Windows platform debugging expertise. Proficiency in Python, automation frameworks, and validation infrastructure development. Experience working with global engineering teams and executive stakeholders. Prior experience with AMD Embedded products, networking, industrial, storage, automotive, communications, AI, or compute platforms is preferred ACADEMIC CREDENTIALS: Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or a related technical field is required. Master’s degree in a relevant engineering or computer science discipline is preferred. Equivalent industry experience in platform validation, customer engineering, embedded systems, or silicon validation may be considered where applicable. Location Bangalore, India #LI-NR1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Staff Engineer ", "company": "Infineon", "location": "Bangalore", "date_posted": "2026-08-19T08:31:01+00:00", "url": "https://jobs.infineon.com/careers/job/563808971837080", "is_hardware": true, "platform": "eightfold", "jd_text": "We are seeking a highly motivated DFT Engineer to develop and deploy robust Design-for-Test solutions for complex SoC/ASIC products. The ideal candidate will work closely with Design, Verification, and Physical Design teams to ensure high test coverage, efficient manufacturability, and successful silicon bring-up.\n\nYour role\nKey responsibilities in your new role :\n\nDevelop and implement comprehensive Design-for-Test (DFT) architectures and methodologies for complex SoCs.\nCollaborate with Design, Verification, and Backend teams to seamlessly integrate DFT features into the chip design flow.\nCreate, execute, and validate test strategies to achieve high fault coverage and reliable defect detection.\nPerform scan insertion, DRC analysis, and resolution of DFT-related issues.\nDrive ATPG, MBIST, and IJTAG implementation, validation, and sign-off activities.\nAnalyze and optimize test coverage at the IP, subsystem, and SoC levels to meet quality and manufacturing targets.\nSupport silicon bring-up, characterization, and debug activities to ensure successful product ramp-up.\nDevelop and maintain automation scripts to improve the efficiency and scalability of DFT flows.\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor's degree in Electrical Engineering, Electronics & Communication Engineering (ECE), or a Master's degree with specialization in VLSI.\n6 to 9+ years of hands-on experience in DFT and ASIC/SoC design and implementation.\nStrong understanding of digital design fundamentals, RTL design concepts, simulation methodologies, and test architectures.\nExpertise in Scan Architecture, Scan Insertion, DFT DRC closure, Boundary Scan (JTAG) implementation, validation, and debug.\nProficient in ATPG generation, fault coverage analysis, MBIST insertion, verification, and debug.\nExperience in IJTAG integration, verification, and sign-off activities.\nHands on experience with industry standard DFT tools including Siemens Tessent, Synopsys TetraMAX, and Cadence Genus.\nStrong knowledge of simulation and validation tools such as Siemens Questa and Cadence Xcelium.\nProficient in hardware description languages including Verilog/VHDL.\nStrong scripting skills in Perl, TCL, and Python for automation and flow development.\nExcellent analytical, debugging, and problem-solving abilities with a proven track record of resolving complex design and test challenges.\nEffective communication and collaboration skills, with experience working across cross-functional teams including Design, Verification, Physical Design, and Test Engineering.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nKeerthini M H", "jd_status": "stored"}, {"title": "Senior Staff Engineer", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-08-19T08:04:29+00:00", "url": "https://jobs.infineon.com/careers/job/563808971837075", "is_hardware": true, "platform": "eightfold", "jd_text": "We are hiring VLSI Design Engineer with expertise in Synthesis, Logic Equivalence Checks (LEC), and UPF-based Low-Power Sign-off. Experienced in low-power implementation, timing analysis, constraints development, and advanced node technologies (40nm/28nm/22nm). Proficient in Shell, Perl, and TCL scripting, with a strong track record of problem-solving, cross-functional collaboration, and driving successful design closure\n\nYour role\nKey responsibilities in your new role\n\nResponsible for synthesis execution, timing closure, and low-power sign-off for complex low-power SoCs targeting the IoT and MCU markets.\n\nOwned synthesis implementation and timing convergence activities at both pre-DFT and post-DFT stages for large hierarchical blocks and full-chip designs.\n\nConducted low-power Logic Equivalence Checks (LEC) across RTL-to-Netlist (RTL2N) and Netlist-to-Netlist (N2N) stages to ensure design integrity.\n\nLed UPF-based low-power verification and sign-off across synthesis, post-layout, and final sign-off stages.\n\nCollaborated closely with architecture, RTL, and DFT teams to evaluate timing feasibility, assess performance targets, and drive design optimization.\n\nPartnered with Physical Design and STA teams to achieve post-layout timing closure and ensure successful design sign-off.\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor's or Master's degree with specialization in VLSI design \nHands-on technical experience in Synthesis, Logic Equivalence Checks, Low Power Sign-off \nSkilled in UPF based Low Power implementations and debugging complex low-power violations \nExperience in constraints development, sign-off timing analysis/closure will be a plus \nExperience in scripting languages (shell, perl, tcl) and Make flow \nUnderstanding of 40nm/28nm/22nm technologies and associated timing closure challenges Soft Skills: \nStrong commitment and determination in area of expertise - Must be well organized, methodical and detail oriented \nReady to accept new challenges and take necessary measures to overcome those \nCommunicates effectively and shares information comprehensively \nMust be a good team player and should have desire to learn and explore\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nAnand Rawal", "jd_status": "stored"}, {"title": "Sr Engineer, Design Verification", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-19T06:31:28.070000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000144236399-sr-engineer-design-verification", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Opportunity for a talented individual for their memory interface products.\nWe are looking for a candidate with a strong background in verifying complex integrated circuits.\nThe candidate needs to have skills that are up to date with the latest IC verification tools and flow.\nThe candidate will work closely with design, and verification engineering.\nIn addition, strong collaboration and communication skills are a must.\nDuties/Responsibilities:\nDevelop verification testbench components for chip/module level using System Verilog.\nUse high-level concepts (Object-oriented, UVM, etc) to develop an extendable environment.\nDefine and execute detailed verification plan from spec working with architects and designer engineers\nExperience in code coverage, functional coverage, assertions, cover groups, etc to achieve 100% verification completeness before tape-out.\nDebug tests, regression failures and participate in silicon debugging and analysis.\nUnderstanding or prior experience with Industry standard protocols like DDR4/DDR5/LPDDR5/DIMM (Dual In-line Memory Module) knowledge is preferred.\n\nBachelors or Masters in Electronics or Electrical Engineering with a minimum of 2-5 years of experience in design/verification management of highly complex projects.\nOrganized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required.\nMust be good in building verification environments preferably using the verification subset of high-level languages like System Verilog (UVM).\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Staff AMS Verification Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-19T04:43:45.959000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000144228959-staff-ams-verification-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Position Overview\nWe are looking for an experienced Staff AMS Verification Engineer to lead and execute verification of complex Analog/Mixed-Signal (AMS) PMIC (Power Management IC) designs. The role involves developing verification strategies, testbenches, methodologies, and automation for block-level and top-level PMIC verification.\nThe ideal candidate will have strong expertise in analog/mixed-signal verification, SystemVerilog/UVM, real-number modeling (RNM), SPICE simulations, and power-management circuits, with the ability to work closely with analog design, digital design, modeling, and product engineering teams.\nKey Responsibilities\nOwn the AMS verification strategy for PMIC blocks and full-chip/top-level designs.\nDefine verification plans, coverage goals, test scenarios, and verification methodologies.\nDevelop and maintain SystemVerilog/UVM-based verification environments for mixed-signal designs.\nDevelop and use Real Number Models (RNM), behavioral models, and mixed-signal abstractions for efficient verification.\nPerform AMS/DMS simulations for functional and corner-case verification.\nVerify PMIC functionality including:\nLDOs and voltage regulators, Buck/boost converters, Bandgap references,Oscillators, Charge pumps, Power-on-reset (POR), Brownout detection, Voltage/current monitoring, ADC/DAC interfaces, Power sequencing and state machines ,Protection features(OVP, UVP, OCP, OTP, and short-circuit protection)\nDevelop verification models for analog blocks and their interaction with digital control logic.\nDebug failures across analog, digital, RTL, behavioral models, and testbench environments.\nCollaborate closely with analog designers and digital designers, review design specifications and identify verification gaps, corner cases, and potential risks.\nMentor junior and senior verification engineers and provide technical leadership.\nDrive improvements in verification methodology, simulation efficiency, automation, and coverage closure.\nContribute to project schedules, technical reviews, sign-off criteria, and verification documentation.\n\nRequired Qualifications\nBachelor's or Master's degree in Electrical/Electronics Engineering, Microelectronics, or a related field.\nTypically 8+ years of experience in semiconductor verification, with significant experience in AMS verification.\nStrong understanding of analog and mixed-signal circuit fundamentals.\nHands-on experience with PMIC architecture and power-management circuits.\nStrong programming/scripting skills in one or more of:\nSystemVerilog\nPython\nPerl\nTcl\nC/C++\nStrong experience with SystemVerilog/UVM and constrained-random verification.\nExperience with AMS simulation and SPICE-based verification.\nExperience with Real Number Modeling (RNM) and/or behavioral modeling.\nExperience with industry-standard EDA tools such as Cadence, Synopsys, or Siemens EDA simulation and verification environments.\nStrong debugging and problem-solving skills.\nExperience defining verification plans and driving coverage closure and sign-off.\nPreferred Qualifications\nExperience verifying automotive, consumer, mobile, industrial, or server PMICs.\nKnowledge of power-management architectures, including switching regulators and linear regulators.\nExperience with AMS assertions, SVA, and functional safety concepts.\nKnowledge of formal verification or hybrid analog/digital verification methodologies.\nExperience developing reusable AMS verification IP and verification frameworks.\nExperience with silicon bring-up, characterization, or correlation between simulation and silicon measurements.\nLeadership Expectations – Staff Level\nAct as a technical owner for AMS verification methodology and execution.\nInfluence architecture and design decisions by identifying verification risks early.\nEstablish reusable verification frameworks and best practices across projects.\nLead complex debug involving interactions between analog and digital domains.\nMentor engineers and raise the overall technical capability of the verification team.\nDrive technical decisions across cross-functional teams and communicate effectively with senior engineering leadership.\nProactively identify opportunities to improve verification quality, simulation performance, and project execution.\nKey Skills\nAMS Verification | PMIC | Analog/Mixed-Signal | SystemVerilog | UVM | RNM | SPICE | Verilog-AMS | Python | Assertions | Functional Coverage | Monte Carlo | PVT | Power Management | AMS Simulation | Mixed-Signal Debug | Verification Automation\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "RTL Design(Security)-Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-19T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720217269", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    5+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Signal Integrity Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-19T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720493930", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nTitle - Staff Signal Integrity Engineer\nThis role represents individual contributor within the CHS Signal Integrity organization responsible for end-to-end SI/PI architecture, analysis, and signoff for next-generation mobile, compute, Automotive and various other connectivity platforms.\nThe engineer acts as\nSystem SI/PI owner across full platform (SoC ↔ package ↔ board ↔ connectors ↔ external systems)\nTechnical owner for high-speed interfaces and system margins\nCross-functional leader driving SIPI driven design convergence across silicon, package, and platform teams\nCore Responsibilities\nOwn end-to-end SI/PI closure for programs (pre-silicon → post-silicon → production)\nDefine design targets and layout design guidelines for all high-speed interfaces\nInfluence architecture decisions early in product lifecycle\nEnsure SI/PI alignment with product KPIs (performance, yield, power, cost)\nDrive new IP co-design across IC/IO/PHY, package, and PCB\nEnsure compliance to standards (JEDEC, PCI-SIG, MIPI, IEEE)\nInfluence PDN architecture definition at system and package level, provide related optimum cost solutions\nEnsure cross functional alignments. Partner with SoC/PHY design teams, Package engineering, Board/system teams and OEM/ODM ecosystem\nLead design reviews and signoff decisions\nRepresent SI/PI in program reviews and leadership forums\nDefine company-wide SI/PI methodologies\nDrive correlation between pre-silicon models and silicon/lab data\nLead debug of eye collapse / jitter margin issues, crosstalk and power noise and silicon-package-board interactions\nDrive best practices adoption across programs\nEstablish golden methods for system SI/PI\nMentor senior engineers across SI/PI domains\nHigh-Speed Interface Expertise\nDrive SI/PI for interfaces such as:\nMemory: LPDDR4/5/6\nHigh-speed IO: PCIe Gen4/5/6/7, USB4, UFS, 10G–112G+ PHYs\nCamera/Display: MIPI CSI/DSI\nSystem PDN\nRequired Qualifications / Experience\n12+ years in Signal Integrity / Power Integrity / High-speed systems\nProven ownership of multiple tapeouts or high-volume products\nDomain Expertise\nDeep expertise in Transmission line theory, EM fundamentals, SI/PI interactions and jitter/noise coupling. Strong hands-on experience with: Tools: HFSS, ADS, Sigrity, CST, SIwave, HSPICE; Measurement: VNA, TDR, real-time scopes\nPreferred Differentiators\nExperience with: Packaging technologies like FCBGA, 2.5D/3D; Products like Data center, Compute and Servers\nTrack record of Patents, standards contributions, or published work internal / external conferences\nyou will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Signal Integrity Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-19T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720493928", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nTitle - Staff Signal Integrity Engineer\nThis role represents individual contributor within the CHS Signal Integrity organization responsible for end-to-end SI/PI architecture, analysis, and signoff for next-generation mobile, compute, Automotive and various other connectivity platforms.\nThe engineer acts as\nSystem SI/PI owner across full platform (SoC ↔ package ↔ board ↔ connectors ↔ external systems)\nTechnical owner for high-speed interfaces and system margins\nCross-functional leader driving SIPI driven design convergence across silicon, package, and platform teams\nCore Responsibilities\nOwn end-to-end SI/PI closure for programs (pre-silicon → post-silicon → production)\nDefine design targets and layout design guidelines for all high-speed interfaces\nInfluence architecture decisions early in product lifecycle\nEnsure SI/PI alignment with product KPIs (performance, yield, power, cost)\nDrive new IP co-design across IC/IO/PHY, package, and PCB\nEnsure compliance to standards (JEDEC, PCI-SIG, MIPI, IEEE)\nInfluence PDN architecture definition at system and package level, provide related optimum cost solutions\nEnsure cross functional alignments. Partner with SoC/PHY design teams, Package engineering, Board/system teams and OEM/ODM ecosystem\nLead design reviews and signoff decisions\nRepresent SI/PI in program reviews and leadership forums\nDefine company-wide SI/PI methodologies\nDrive correlation between pre-silicon models and silicon/lab data\nLead debug of eye collapse / jitter margin issues, crosstalk and power noise and silicon-package-board interactions\nDrive best practices adoption across programs\nEstablish golden methods for system SI/PI\nMentor senior engineers across SI/PI domains\nHigh-Speed Interface Expertise\nDrive SI/PI for interfaces such as:\nMemory: LPDDR4/5/6\nHigh-speed IO: PCIe Gen4/5/6/7, USB4, UFS, 10G–112G+ PHYs\nCamera/Display: MIPI CSI/DSI\nSystem PDN\nRequired Qualifications / Experience\n12+ years in Signal Integrity / Power Integrity / High-speed systems\nProven ownership of multiple tapeouts or high-volume products\nDomain Expertise\nDeep expertise in Transmission line theory, EM fundamentals, SI/PI interactions and jitter/noise coupling. Strong hands-on experience with: Tools: HFSS, ADS, Sigrity, CST, SIwave, HSPICE; Measurement: VNA, TDR, real-time scopes\nPreferred Differentiators\nExperience with: Packaging technologies like FCBGA, 2.5D/3D; Products like Data center, Compute and Servers\nTrack record of Patents, standards contributions, or published work internal / external conferences\nyou will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "ASIC RTL Design Engineer (Automotive IP/Cores) (Sr. Engr / Sr. Lead Engr)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-19T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720366374", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Description\n\nThis role offers a position in system power management IP cores and subsystem design, targeted for variety of industry leading Snapdragon SoCs for mobile, compute, IoT and Automotive markets.\n\nKey Responsibilities\nMicro-architecture and RTL design for IP Cores / subsystems.\nWork in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence.\nEnable SW teams to use HW blocks.\nQualify designs using static tool checks including Lint, CDC, CLP etc.\nSynthesis, LEC and Netlist CLP\nReport status and communicate progress against expectations.\n\n Preferred Qualifications\n3 to 8 years of strong experience in RTL design for ASICs\nExpertise in RTL coding in Verilog/SV of complex designs with multiple clock domains and multiple power domains\nFamiliar with UPF and power domain crossing\nExperience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP\nFamiliarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI\nExperience in low power design methodology and clock domain crossing designs\nExperience in Spyglass Lint/CDC checks and waiver creation\nExperience in formal verification with Cadence LEC\nUnderstanding of full RTL to GDS flow to interact with DFT and PD teams\nExpertise in Perl/TCL/Python language\nExperienced in database management flows with Clearcase/Clearquest.\nExpertise in post-Si debug is a plus\nExcellent oral and written communications skills to ensure effective interaction with Engineering Management and team  members.\nTeam player, self-motivated, should be able to work with minimal supervision.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Field Applications Engineer", "company": "Microchip", "location": "India - Bangalore Sales", "date_posted": "2026-08-19", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore-Sales/Senior-Field-Applications-Engineer_R235-26-4", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nJob Description\nAs an Embedded Solutions Engineer (ESE/FAE) specializing in FPGAs, you will apply your engineering expertise to solve clients’ technical challenges while identifying and developing new business. You will reframe how clients approach their designs, build consensus around Microchip’s solutions, and co-create value that gives them the freedom to innovate.\nAt Microchip Technology, our values empower employees to grow and thrive in a supportive, collaborative, professional, and global work environment. We embrace change and continuous improvement for the mutual benefit of our team and our clients, and we are looking for like-minded people who share our passion for success.\n\nJob Responsibilities\nPartner with the Sales and Marketing teams to deliver pre-sales and post-sales technical support across every phase of a client’s adoption of Microchip FPGAs.\nApply Microchip’s Client Engagement Process to convert design wins into revenue at targeted strategic clients.\nLead client system-architecture discussions and design reviews, positioning Microchip to meet both the FPGA requirements and the companion ICs surrounding the FPGA.\nServe as an authority across all phases of programmable-logic design, including requirements analysis, HDL development and simulation, embedded hard- and soft-processor system design, synthesis optimization, place-and-route constraints, timing closure, FPGA hardware development, and debug tools.\nConduct architecture and board-level schematic reviews, provide design-in support, and deliver product training for customers.\nSupport clients’ development processes that incorporate Microchip FPGA solutions, advancing each design from design-in through post-production.\nCollaborate within a global team to develop and execute account strategies for assigned clients across all regions.\nCommunicate effectively with Microchip’s product divisions, providing quantifiable feedback and ROI on their investments in clients.\n\nRequirements/Qualifications:\n\nBachelor’s or Master’s degree in an engineering discipline (EEE, ECE, EIC, ETC, or VLSI) with a strong academic record.\n5–7+ years of relevant experience in FPGA-based design or applications.\nIn-depth experience with Microsemi/Microchip, Xilinx, or Altera FPGA devices, with deep knowledge of Verilog or VHDL.\nHands-on experience with Libero, Vivado, or Quartus FPGA design software, along with synthesis and simulation EDA tools.\nExperience with high-speed serial transceivers and interfaces such as PCIe, DDR3/4, LPDDR3/4, and MIPI.\nExperience with embedded soft-core or ASIC-based CPUs (RISC-V or ARM architectures).\nEmbedded processor experience with a working knowledge of C and Linux; familiarity with software debugging tools such as Keil, IAR, or Eclipse, and experience building and debugging customized Linux images, is a strong plus.\nFamiliarity with hardware security concepts — such as secure boot, encryption and authentication, key management, and physically unclonable functions (PUFs) — and with Hardware Security Module (HSM)-based key provisioning is preferred.\nCreativity and initiative to identify clients’ technical needs, provide support on RTL blocks and FPGA-based designs, and introduce other Microchip solutions when appropriate.\nAbility to create content and deliver technical overviews, seminars, and workshops for clients and fellow ESEs/FAEs.\nStrong debugging skills, with the ability to investigate system-level issues and help clients identify the root cause.\nAbility to manage multiple customer engagements simultaneously.\nStrategic and critical thinking — solve problems systematically, anticipate clients’ pain points, expectations, and implicit needs, and collaborate with team members to devise solutions to complex client challenges.\nCommunication — tailor messaging to each client’s needs with authority, deliver effective presentations, and demonstrate strong verbal and written communication skills.\nOwnership — take initiative, work independently, and drive relentlessly to complete tasks and achieve results.\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "IO and Mixed Signal Circuit Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-08-19", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/IO-and-Mixed-Signal-Circuit-Design-Engineer_R026862", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nWork as part of Mixed Signal and IO Library Development team in Central Engineering. Primary responsibilities include:\nDesign and verification of IO interfaces and mixed signal blocks such as POR, process monitors, voltage/temperature sensors, crystal oscillators etc.\nRTL coding, synthesis and verification of digital wrappers that interface with analog circuitry\nInterface with both custom and P&R layout engineers and oversee physical design and verification.\nDevelop functional models and perform timing characterization of these cells.\nDirectly interface with end customers to understand their requirements, come up with specifications and implement circuit designs that support them.\nCreate necessary infrastructure and generate test vectors to support silicon validation of these blocks on test chips.\nWork with test engineers to support silicon validation either on ATE or on the bench.\nDevelop accurate documentation in the form of datasheets, application notes and integration guides\n\nSkills and Qualifications Required:\nEducational requirements: MSEE with a minimum of 5-15 years of hands-on experience in independently designing mixed signal circuits especially in newer CMOS technologies such as 5nm or 3nm\nMust have experience in designing analog circuits such as PLLs, LDOs, Bandgap references, ADCs or DACs--knowledge of AMS methodology and analog circuit modeling will be a plus\nMust be proficient with Cadence Virtuoso Schematic Capture and ADE along with an excellent knowledge of spice based simulators such as Spectre and/or Hspice\nWorking knowledge of LVS, DRC along with EM/ESD verification tools such as Totem/Pathfinder/PER\nStrong written and oral communication skills in English to be able to work effectively across geographies as well as to be able to interface with end customers\nRequire proficiency in automation using shell scripting or any other languages such as SED, AWK, TCL or PERLˇ\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Senior Memory Circuit Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-08-19", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Senior-Memory-Circuit-Design-Engineer_R026827", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nAnalyze different memory architectures and highlight the tradeoffs\n\nDesign and build memory or circuit blocks at the gate or transistor level \n\nSimulate and analyze the circuit design using transistor level simulators \n\nExtract the layout and perform post-layout simulations and verification\n\nFloorplan physical implementation and leafcell layout integration to build the physical macro\n\nIntegrate characterization flow to extract timing and power information\n\nDevelop scripts to automate characterization flow, simulations, and verification\n\nSpecify and verify various behavioral and physical memory models\n\nDocument the design specifications, behavioral description, and timing diagrams\n\nSpecify silicon test plan and correlate silicon to simulation data\n\nHelp debug silicon issues\n\nSkillset Required\nKnowledge in development of memory compilers or custom digital circuits of all types; SRAMs, Register-files, Multi-ports, ROM, etc…\n\nGood understanding of transistor level circuit behavior and device physics\n\nGood understanding of signal integrity, EM/IR, and reliability analysis\n\nUnderstanding of memory behavioral and physical models\n\nUnderstanding of DFT schemes and chip level integration\n\nFamiliarity with test setups, silicon testing and debug is a plus\n\nProficient in running simulators, writing automation scripts, and are tools savvy\n\nGood communication, interpersonal, and leadership skills\n\nMotivated, self-driven and good at multi-tasking\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Staff Memory Circuit Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-08-19", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Staff-Memory-Circuit-Design-Engineer_R026828", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nWe are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience levels.\n \nAvailable Job Responsibilities\nDesign and build memory or circuit blocks at the gate or transistor level\n\nSimulate and analyze the circuit design using transistor level simulators\n\nExtract the layout and perform post-layout simulations and verification\n\nFloorplan physical implementation and layout integration of design components\n\nIntegrate characterization flow to extract timing and power information\n\nDevelop scripts to automate characterization flow, simulations, and verification\n\nSpecify and verify various behavioral and physical memory models\n\nDocument the design specifications, behavioral description, and timing diagrams\n\nHelp specify silicon test plan and correlate silicon to simulation data\n\n \nPreferred Skills\nGood understanding of transistor level circuit behavior and device physics\n\nGood understanding of signal integrity analysis, EM/IR analysis, and reliability analysis\n\nProficiency in running simulators, writing automation scripts, and are tools savvy\n\nUnderstanding of memory behavioral and physical models is a plus\n\nExpertise in memory circuit design is a plus\n\nUnderstanding of DFT schemes and chip level integration is a plus\n\nGood communication, interpersonal, and leadership skills\n\nMotivated, self-driven and good at multi-tasking\n\nPassion for solving complex problems and willingness to learn\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "CPU Verification Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-19", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/CPU-Verification-Engineer_JR2019900", "is_hardware": true, "platform": "workday", "jd_text": "At NVIDIA, we take pride in pushing the edge of computer graphics, PC gaming, and accelerated computing. As a Senior CPU Verification Engineer, you will be involved in development of latest ARM architecture-based CPUs that are engineered for AI execution and are a key component of the Agentic AI hardware stack. This position presents a valuable opportunity to work on pioneering CPU projects with experts in the field. If you strive for innovation and excellence, this is where you belong!\n \nWhat you'll be doing:\nResponsible for verification of ARM architecture-based CPU cores\n\nDevelop and execute thorough unit-level verification plans and create new testbench components\n\nCollaborate closely with design and architecture teams to verify architectural and microarchitectural features\n\nDevelop stimulus using external and in-house RIS tools for end-to-end verification of features\n\nAnalyze and improve existing verification strategies by incorporating AI accelerated workflows to enhance efficiency and effectiveness\n\nWhat we need to see:\nBachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.\n\nAt least 2+ years of experience in CPU verification.\n\nProven expertise in ARM architecture and/or CPU microarchitecture verification.\n\nStrong understanding of verification methodologies and tools.\n\nOutstanding problem-solving skills and attention to detail.\n\nExcellent communication and teamwork abilities.\n\nWays to stand out from the crowd:\nDetailed understanding of ARM v9 architecture and/or cache coherency concepts \n\nExposure to unit level (Branch-Predictor/Frontend/Load-Store) verification of high-performance CPU cores\n\nExposure to stimulus generation using RIS tools\n\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status.\n\nWith competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and passionate people in the world working for us and, due to unprecedented growth, our elite engineering teams are rapidly growing. If you're a creative and independent engineer with a real passion for technology, we want to hear from you.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Engineering Manager 2", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-08-19", "url": "https://careers.skyworksinc.com/job-invite/77301/", "is_hardware": true, "platform": "successfactors", "jd_text": "Division: RMI Engineering \n\nEmployment Status: Exempt\n\nSalary Grade: 111\n\nShift: \n\nRequisition ID: 77301 \n\nPlease be aware that if you are selected to formally interview for an internal position you will be required to notify your current manager.  Please refer to the Employee Transfers Guidelines posted on Skylink.\n\nAbout the role\n\nWe are seeking an experienced Engineering Manager II to lead one or more Analog and Mixed‑Signal IC Design teams. This role combines deep technical leadership with people management and execution ownership. You will be responsible for delivering high‑quality silicon while growing talent, shaping design direction, and partnering across the organization to bring complex products to market.\n\nThis position is ideal for a seasoned analog IC designer who has successfully transitioned into people leadership and thrives at the intersection of technical depth, execution, and team development.\n\nResponsibilities\n\nWhat You’ll Do\n\nLead and manage teams of senior analog and mixed‑signal IC designers\n\nOwn technical direction, design quality, and execution for complex IC programs\n\nGuide teams through architecture definition, design reviews, verification, and silicon bring‑up\n\nTranslate system and product requirements into robust analog architectures\n\nDrive delivery across multiple milestones while balancing schedule, quality, and silicon risk\n\nMentor engineers and managers, supporting both technical excellence and career growth\n\nPartner closely with product, systems, digital design, physical design, validation, and manufacturing teams\n\nInfluence longer‑term technology and IP roadmaps\n\nWhat You’ll Bring\n\nTechnical Expertise\n\nDeep experience in analog IC design, with multiple successful production tape‑outs\n\nStrong knowledge of analog building blocks such as:\n\nVoltage/current references, regulators, LDOs\n\nLNA's, Mixers, Amplifiers, comparators, and data converters\n\nPLLs, clocking, or interface‑adjacent analog circuits\n\nProven ability to define and evaluate analog and mixed‑signal architectures\n\nSolid understanding of mixed‑signal integration challenges (noise, isolation, power integrity)\n\nFamiliarity with layout tradeoffs and analog verification methodologies (corners, Monte Carlo, aging)\n\nLeadership & Execution\n\nExperience managing senior IC designers and/or first‑line managers\n\nDemonstrated success in:\n\nHiring, coaching, and retaining top engineering talent\n\nPerformance management and career development\n\nDriving accountability and engineering rigor\n\nStrong program ownership skills, including planning, risk management, and cross‑team coordination\n\nAbility to communicate clearly with both technical teams and leadership\n\nRequired Experience and Skills\n\nBachelor’s degree in Electrical Engineering or related field\n(Master’s or PhD preferred)\n\nTypically 10–15+ years of IC design experience\n\n8+ years focused on analog or mixed‑signal design\n\n3+ years in engineering leadership or people management roles\n\nTrack record of delivering high‑quality silicon into production\n\nDesired Experience and Skills\n\nReferral Bonus Program Reward (if eligible): Rs200,000.00", "jd_status": "stored"}, {"title": "Principal Electrical Engineer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-08-19", "url": "https://careers.skyworksinc.com/job-invite/77302/", "is_hardware": true, "platform": "successfactors", "jd_text": "Division: RMI Engineering \n\nEmployment Status: Exempt\n\nSalary Grade: 111\n\nShift: \n\nRequisition ID: 77302 \n\nPlease be aware that if you are selected to formally interview for an internal position you will be required to notify your current manager.  Please refer to the Employee Transfers Guidelines posted on Skylink.\n\nDescription\n\nAbout the Role\n\nWe are seeking a Principal Analog Design Engineer to design, integrate, and characterize high‑performance, high speed analog circuits for next‑generation products. This role requires deep hands‑on expertise, strong system‑level understanding, and the ability to technically lead complex mixed‑signal designs from concept through silicon qualification and production.\n\nYou will work closely with digital, layout, validation, firmware, and product teams to deliver robust, manufacturable solutions for demanding high speed analog applications\n\nResponsibilities\n\nAnalog Design\n\nArchitect, design, and simulate Analog circuit blocks, including:\n\nVCOs/PLLs, XOSC\n\nHigh Speed Data converters (ADCs/DACs)\n\nBias generation, bandgap references, LDOs\n\nAmplifiers and filters\n\nLNAs, mixers\n\nTranslate system‑level requirements (noise, gain, linearity, power, phase noise) into robust circuit implementations\n\nPerform detailed schematic design, simulation, and optimization across PVT corners\n\nSystem & Architecture Contribution\n\nCollaborate with system architects to define RF signal chains and analog subsystems\n\nDrive tradeoff analysis between performance, power, area, and cost\n\nSupport RF budgeting (NF, IP3, phase noise, jitter, spur analysis)\n\nSilicon Implementation & Signoff\n\nWork closely with layout engineers on:\n\nFloor planning\n\nSensitive routing and matching\n\nEM, IR, and substrate coupling considerations\n\nOwn or support block‑level and top‑level signoff:\n\nAC/DC performance\n\nNoise and linearity\n\nStability and yield margin\n\nValidation & Debug\n\nLead silicon bring‑up, lab characterization, and debug\n\nCorrelate measurement results with simulation\n\nIdentify root causes and drive fixes for silicon issues\n\nSupport yield improvement and production ramp\n\nTechnical Leadership\n\nDefine best practices for RF/analog design and verification\n\nMentor Junior engineers and help refine circuits and architectures\n\nInfluence roadmap and architectural decisions\n\nServe as a technical point of contact across cross‑functional teams\n\nRequired Experience and Skills\n\nBachelor’s, Master’s, or PhD in Electrical Engineering or related field\n\nTypically 10+ years of hands‑on Analog IC design experience\n\nProven track record of tape‑out ownership and silicon success\n\nStrong understanding of:\n\nAnalog circuit design techniques with CMOS\n\nRF fundamentals (noise, linearity, matching, phase noise)\n\nExperience with industry tools:\n\nCadence Virtuoso, SpectreRF, EMX or equivalent\n\nComfortable working across process nodes and foundries\n\nDesired Experience and Skills\n\n \n\nMixed‑signal integration experience (Analog + digital SoC)\n\nHigh‑speed or precision analog experience\n\nFamiliarity with packaging, test, and manufacturing constraints\n\nExperience supporting volume production\n\nSoft Skills & Mindset\n\nStrong problem‑solving and debugging skills\n\nAbility to communicate complex technical concepts clearly\n\nOwnership mindset with attention to detail\n\nComfortable influencing without formal authority\n\nCollaborative and pragmatic approach to engineering tradeoffs\n\n \n\n#LI-CB1\n\nReferral Bonus Program Reward (if eligible): Rs200,000.00", "jd_status": "stored"}, {"title": "ASIC Digital Design , Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-19", "url": "https://careers.synopsys.com/job/bengaluru/asic-digital-design-staff-engineer/44408/99481075424", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years building RTL that ships in silicon, not just passes simulation. When you read a protocol specification, you see the corner cases that will break three months into verification, and you architect around them before anyone else notices. You are comfortable taking a huge page Ethernet spec and walking out with a micro-architecture that balances latency, power, and area without needing someone to hold your hand. You write Verilog that other engineers can actually read and maintain. Debugging asynchronous FIFO issues and CDC violations has taught you what good design discipline looks like, and you hold yourself to it even when schedules get tight. Multi-site collaboration does not slow you down. You can review someone's RTL in a different timezone, leave clear feedback, and move the design forward without waiting for a meeting. At Synopsys, you will work on IP cores that power everything from AI accelerators to automotive systems, and the designs you own will matter.\nWhat You'll Be Doing\nDesign and code RTL for high-speed Ethernet IP cores ranging from 100G to 1.6T, focusing on low latency and timing closure in complex datapath and control logic\nTranslate protocol specifications and functional requirements into micro-architecture and detailed design documents for DesignWare IP in Ethernet, AMBA AXI, CHI, PCIe, USB, MIPI, or memory controller domains\nBuild and refine directed Verilog testbenches to improve functional and code coverage, analyzing metrics and defining targeted test cases that catch real bugs\nPerform technical reviews of functional specs, micro-architecture documents, and RTL code from peers across global design teams\nDrive timing analysis and closure for high-speed designs using synthesis, STA, lint, CDC, and formal verification flows\nApply low power design methodologies and automotive safety requirements to IP development\nCollaborate with verification, integration, and product teams across Bangalore, the US, and other global sites to deliver production-quality IP on schedule\nThe Impact You Will Have\nYour RTL will ship in customer SoCs powering data center infrastructure, automotive platforms, and AI systems used by millions of people\nThe micro-architecture decisions you make today will determine whether a customer's chip meets their performance and power targets six months from now\nYour coverage improvements and directed tests will catch silicon bugs before tapeout, saving customers months of respins and lost revenue\nThe design quality and documentation you deliver will set the standard for how the rest of the IP team approaches complex protocol implementations\nYour timing closure work on multi-gigabit interfaces will enable Synopsys to stay ahead in the race toward higher-speed Ethernet and interconnect IP\nThe technical reviews you provide will level up junior engineers and prevent architectural mistakes from becoming costly late-stage fixes\nYour ability to work across sites will keep globally distributed projects on track and reduce friction in cross-functional handoffs\nWhat You'll Need\nBachelor's in Electrical Engineering with 6+ years of hands-on ASIC or IP design experience, or Master's with 4+ years\nDeep RTL design experience on IP cores or SoC subsystems that have taped out or shipped to customers\nStrong working knowledge of at least one protocol from this list: AMBA (AHB, AXI, CHI), SD, eMMC, DDR, PCIe, USB, MIPI. High-speed Ethernet (100G and above) experience is a strong plus\nProven ability to create micro-architecture and detailed design documents from functional specs for small to medium complexity blocks, especially control-path designs like async FIFOs, DMA engines, or SRAM/DPRAM interfaces\nHands-on experience with Verilog or SystemVerilog, simulation tools, synthesis flows, static timing analysis, lint, CDC, and formal verification tools\nSolid understanding of high-speed, low-latency design techniques and timing closure challenges. Experience with datapath designs or arithmetic algorithms like FEC is a plus\nFamiliarity with Perforce or similar version control systems, and scripting in Perl or shell for automation\nWho You Are\nYou can take a vague feature request and turn it into a clean, implementable design without needing three rounds of clarification meetings\nWhen you review RTL, you catch the subtle issues that would have caused problems in integration, and you explain them clearly enough that the engineer learns something\nYou know how to prioritize when you are juggling timing closure, coverage improvements, and a design review scheduled for tomorrow, and nothing falls through the cracks\nYou communicate technical tradeoffs in writing and in review meetings with enough clarity that engineers in other timezones can act on your feedback without a follow-up call\nYou push back when a spec is ambiguous or a schedule does not account for real design complexity, and you do it in a way that moves the conversation forward\nYou treat documentation as part of the design, not an afterthought, because you know the next person reading your micro-arch doc might be you in six months\nThe Team You'll Be Part Of\nYou will join the IPG Group at the Bangalore Design Center as a technical individual contributor working on DesignWare IP cores. This is a multi-site team spread across global locations, focused on delivering high-speed protocol IP in areas like Ethernet, AMBA, PCIe, USB, MIPI, and memory controllers. The work is technically challenging, the designs are complex, and the team expects you to own your deliverables with minimal supervision while collaborating across timezones to hit shared milestones.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "ASIC Digital Design , Sr Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-19", "url": "https://careers.synopsys.com/job/bengaluru/asic-digital-design-sr-staff-engineer/44408/99446435280", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years building RTL that ships in silicon, not just passes simulation. When you read a protocol specification, you see the corner cases that will break three months into verification, and you architect around them before anyone else notices. You are comfortable taking a huge page Ethernet spec and walking out with a micro-architecture that balances latency, power, and area without needing someone to hold your hand. You write Verilog that other engineers can actually read and maintain. Debugging asynchronous FIFO issues and CDC violations has taught you what good design discipline looks like, and you hold yourself to it even when schedules get tight. Multi-site collaboration does not slow you down. You can review someone's RTL in a different timezone, leave clear feedback, and move the design forward without waiting for a meeting. At Synopsys, you will work on IP cores that power everything from AI accelerators to automotive systems, and the designs you own will matter.\nWhat You'll Be Doing\nDesign and code RTL for high-speed Ethernet IP cores ranging from 100G to 1.6T, focusing on low latency and timing closure in complex datapath and control logic\nTranslate protocol specifications and functional requirements into micro-architecture and detailed design documents for DesignWare IP in Ethernet, AMBA AXI, CHI, PCIe, USB, MIPI, or memory controller domains\nBuild and refine directed Verilog testbenches to improve functional and code coverage, analyzing metrics and defining targeted test cases that catch real bugs\nPerform technical reviews of functional specs, micro-architecture documents, and RTL code from peers across global design teams\nDrive timing analysis and closure for high-speed designs using synthesis, STA, lint, CDC, and formal verification flows\nApply low power design methodologies and automotive safety requirements to IP development\nCollaborate with verification, integration, and product teams across Bangalore, the US, and other global sites to deliver production-quality IP on schedule\nThe Impact You Will Have\nYour RTL will ship in customer SoCs powering data center infrastructure, automotive platforms, and AI systems used by millions of people\nThe micro-architecture decisions you make today will determine whether a customer's chip meets their performance and power targets six months from now\nYour coverage improvements and directed tests will catch silicon bugs before tapeout, saving customers months of respins and lost revenue\nThe design quality and documentation you deliver will set the standard for how the rest of the IP team approaches complex protocol implementations\nYour timing closure work on multi-gigabit interfaces will enable Synopsys to stay ahead in the race toward higher-speed Ethernet and interconnect IP\nThe technical reviews you provide will level up junior engineers and prevent architectural mistakes from becoming costly late-stage fixes\nYour ability to work across sites will keep globally distributed projects on track and reduce friction in cross-functional handoffs\nWhat You'll Need\nBachelor's in Electrical Engineering with 8+ years of hands-on ASIC or IP design experience, or Master's with 6+ years\nDeep RTL design experience on IP cores or SoC subsystems that have taped out or shipped to customers\nStrong working knowledge of at least one protocol from this list: AMBA (AHB, AXI, CHI), SD, eMMC, DDR, PCIe, USB, MIPI. High-speed Ethernet (100G and above) experience is a strong plus\nProven ability to create micro-architecture and detailed design documents from functional specs for small to medium complexity blocks, especially control-path designs like async FIFOs, DMA engines, or SRAM/DPRAM interfaces\nHands-on experience with Verilog or SystemVerilog, simulation tools, synthesis flows, static timing analysis, lint, CDC, and formal verification tools\nSolid understanding of high-speed, low-latency design techniques and timing closure challenges. Experience with datapath designs or arithmetic algorithms like FEC is a plus\nFamiliarity with Perforce or similar version control systems, and scripting in Perl or shell for automation\nWho You Are\nYou can take a vague feature request and turn it into a clean, implementable design without needing three rounds of clarification meetings\nWhen you review RTL, you catch the subtle issues that would have caused problems in integration, and you explain them clearly enough that the engineer learns something\nYou know how to prioritize when you are juggling timing closure, coverage improvements, and a design review scheduled for tomorrow, and nothing falls through the cracks\nYou communicate technical tradeoffs in writing and in review meetings with enough clarity that engineers in other timezones can act on your feedback without a follow-up call\nYou push back when a spec is ambiguous or a schedule does not account for real design complexity, and you do it in a way that moves the conversation forward\nYou treat documentation as part of the design, not an afterthought, because you know the next person reading your micro-arch doc might be you in six months\nThe Team You'll Be Part Of\nYou will join the IPG Group at the Bangalore Design Center as a technical individual contributor working on DesignWare IP cores. This is a multi-site team spread across global locations, focused on delivering high-speed protocol IP in areas like Ethernet, AMBA, PCIe, USB, MIPI, and memory controllers. The work is technically challenging, the designs are complex, and the team expects you to own your deliverables with minimal supervision while collaborating across timezones to hit shared milestones.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Lead Analog Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-08-19", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25011652", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n  Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\n  This is a great opportunity to be part of an established team that's continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electronics, mobile computing and communications.\n\nIn this role, responsibilities may include:\n\nLead an Analog IC design team with product ownership and responsibility from definition to release to manufacturing\n\nDirect, guide and participate in activities of a research or technical design function responsible for designing, developing, modifying and evaluating electronic parts, components, integrated circuits for a variety of applications\n\nMake assignments for team members, providing design guidance as needed, developing schedules and monitoring progress throughout the project\n\nEvaluate intermediate and final results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout\n\nCollaborate with Design Verification teams during the pre-PG phase of a project to ensure completion of all technical tasks before PG\n\nWork with systems engineers, application engineers and marketing to prepare product briefs, datasheets, application notes and assisting in the definition of the product to meet customer needs as well as contributing to roadmap formulation and new concept creation\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nInterface and lead discussions with the customer and/or TI field sales/field applications teams to understand customer designs, problems and support as required\n\nActively participate in hiring, developing and evaluating personnel to ensure efficient operation of the organization and growth of the individuals into leader\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in Electrical Engineering\n\nXX years of relevant experience\n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Senior Technology Engineer", "company": "Lattice", "location": "San Jose, CA", "date_posted": "2026-08-19", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/San-Jose-CA/Senior-Technology-Engineer_R-101002-1", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\n\nJob Description:\nWe are looking for a Senior Technology Engineer.  This person will be responsible for the interface between Lattice engineering and external foundries to enable successful process adoption and on-time tape-out. Ensure PDK readiness, and ensure alignment between internal EDA, design teams, and foundry requirements.\n\nKey responsibilities:\nServe as the primary technical interface to foundries, driving technical alignment, issue resolution, and escalations\n\nPartner with EDA teams on procurement, validation, and rollout of PDKs, models, and technology collateral\n\nEnsure design and signoff flows align with foundry requirements (DRC/LVS, EM/IR, ESD, SI/PI, reliability, etc.)\n\nOwn device test structure definition and support silicon characterization to validate process assumptions\n\nEstablish and scale processes for managing technology collateral, documentation, and design methodology consistency across programs\n\nQualifications:\n\nBS/MS/PhD in Electrical Engineering or related field\n\n10+ years in semiconductor technology and foundry interfacing roles\n\nDeep understanding of advanced process nodes and device physics\n\nProven ability to work with external partners (foundry, EDA, and IP vendors)\n\nStrong cross-functional collaboration and communication skills\n\nPreferred\nDirect experience with TSMC and Samsung foundry ecosystems\n\nStrong understanding of CAD/EDA flows (PDK, reliability, ESD, EM/IR, SI/PI, etc.)\n\nExperience supporting tape-out and silicon validation across multiple nodes\n\nPay & Benefits\n\nConsistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. \n\nFor candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.  The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.\n\nBase Pay Range\n211200\nIn addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! \n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in the United States.\n\nLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.\n \nAs an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.", "jd_status": "stored"}, {"title": "ASIC Digital Design, Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-19", "url": "https://careers.synopsys.com/job/bengaluru/asic-digital-design-staff-engineer/44408/99446435344", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years building RTL that ships in silicon, not just passes simulation. When you read a protocol specification, you see the corner cases that will break three months into verification, and you architect around them before anyone else notices. You are comfortable taking a huge page Ethernet spec and walking out with a micro-architecture that balances latency, power, and area without needing someone to hold your hand. You write Verilog that other engineers can actually read and maintain. Debugging asynchronous FIFO issues and CDC violations has taught you what good design discipline looks like, and you hold yourself to it even when schedules get tight. Multi-site collaboration does not slow you down. You can review someone's RTL in a different timezone, leave clear feedback, and move the design forward without waiting for a meeting. At Synopsys, you will work on IP cores that power everything from AI accelerators to automotive systems, and the designs you own will matter.\nWhat You'll Be Doing\nDesign and code RTL for high-speed Ethernet IP cores ranging from 100G to 1.6T, focusing on low latency and timing closure in complex datapath and control logic\nTranslate protocol specifications and functional requirements into micro-architecture and detailed design documents for DesignWare IP in Ethernet, AMBA AXI, CHI, PCIe, USB, MIPI, or memory controller domains\nBuild and refine directed Verilog testbenches to improve functional and code coverage, analyzing metrics and defining targeted test cases that catch real bugs\nPerform technical reviews of functional specs, micro-architecture documents, and RTL code from peers across global design teams\nDrive timing analysis and closure for high-speed designs using synthesis, STA, lint, CDC, and formal verification flows\nApply low power design methodologies and automotive safety requirements to IP development\nCollaborate with verification, integration, and product teams across Bangalore, the US, and other global sites to deliver production-quality IP on schedule\nThe Impact You Will Have\nYour RTL will ship in customer SoCs powering data center infrastructure, automotive platforms, and AI systems used by millions of people\nThe micro-architecture decisions you make today will determine whether a customer's chip meets their performance and power targets six months from now\nYour coverage improvements and directed tests will catch silicon bugs before tapeout, saving customers months of respins and lost revenue\nThe design quality and documentation you deliver will set the standard for how the rest of the IP team approaches complex protocol implementations\nYour timing closure work on multi-gigabit interfaces will enable Synopsys to stay ahead in the race toward higher-speed Ethernet and interconnect IP\nThe technical reviews you provide will level up junior engineers and prevent architectural mistakes from becoming costly late-stage fixes\nYour ability to work across sites will keep globally distributed projects on track and reduce friction in cross-functional handoffs\nWhat You'll Need\nBachelor's in Electrical Engineering with 6+ years of hands-on ASIC or IP design experience, or Master's with 4+ years\nDeep RTL design experience on IP cores or SoC subsystems that have taped out or shipped to customers\nStrong working knowledge of at least one protocol from this list: AMBA (AHB, AXI, CHI), SD, eMMC, DDR, PCIe, USB, MIPI. High-speed Ethernet (100G and above) experience is a strong plus\nProven ability to create micro-architecture and detailed design documents from functional specs for small to medium complexity blocks, especially control-path designs like async FIFOs, DMA engines, or SRAM/DPRAM interfaces\nHands-on experience with Verilog or SystemVerilog, simulation tools, synthesis flows, static timing analysis, lint, CDC, and formal verification tools\nSolid understanding of high-speed, low-latency design techniques and timing closure challenges. Experience with datapath designs or arithmetic algorithms like FEC is a plus\nFamiliarity with Perforce or similar version control systems, and scripting in Perl or shell for automation\nWho You Are\nYou can take a vague feature request and turn it into a clean, implementable design without needing three rounds of clarification meetings\nWhen you review RTL, you catch the subtle issues that would have caused problems in integration, and you explain them clearly enough that the engineer learns something\nYou know how to prioritize when you are juggling timing closure, coverage improvements, and a design review scheduled for tomorrow, and nothing falls through the cracks\nYou communicate technical tradeoffs in writing and in review meetings with enough clarity that engineers in other timezones can act on your feedback without a follow-up call\nYou push back when a spec is ambiguous or a schedule does not account for real design complexity, and you do it in a way that moves the conversation forward\nYou treat documentation as part of the design, not an afterthought, because you know the next person reading your micro-arch doc might be you in six months\nThe Team You'll Be Part Of\nYou will join the IPG Group at the Bangalore Design Center as a technical individual contributor working on DesignWare IP cores. This is a multi-site team spread across global locations, focused on delivering high-speed protocol IP in areas like Ethernet, AMBA, PCIe, USB, MIPI, and memory controllers. The work is technically challenging, the designs are complex, and the team expects you to own your deliverables with minimal supervision while collaborating across timezones to hit shared milestones.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "ASIC Digital Design , Sr Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-19", "url": "https://careers.synopsys.com/job/bengaluru/asic-digital-design-sr-staff-engineer/44408/99446435328", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years building RTL that ships in silicon, not just passes simulation. When you read a protocol specification, you see the corner cases that will break three months into verification, and you architect around them before anyone else notices. You are comfortable taking a huge page Ethernet spec and walking out with a micro-architecture that balances latency, power, and area without needing someone to hold your hand. You write Verilog that other engineers can actually read and maintain. Debugging asynchronous FIFO issues and CDC violations has taught you what good design discipline looks like, and you hold yourself to it even when schedules get tight. Multi-site collaboration does not slow you down. You can review someone's RTL in a different timezone, leave clear feedback, and move the design forward without waiting for a meeting. At Synopsys, you will work on IP cores that power everything from AI accelerators to automotive systems, and the designs you own will matter.\nWhat You'll Be Doing\nDesign and code RTL for high-speed Ethernet IP cores ranging from 100G to 1.6T, focusing on low latency and timing closure in complex datapath and control logic\nTranslate protocol specifications and functional requirements into micro-architecture and detailed design documents for DesignWare IP in Ethernet, AMBA AXI, CHI, PCIe, USB, MIPI, or memory controller domains\nBuild and refine directed Verilog testbenches to improve functional and code coverage, analyzing metrics and defining targeted test cases that catch real bugs\nPerform technical reviews of functional specs, micro-architecture documents, and RTL code from peers across global design teams\nDrive timing analysis and closure for high-speed designs using synthesis, STA, lint, CDC, and formal verification flows\nApply low power design methodologies and automotive safety requirements to IP development\nCollaborate with verification, integration, and product teams across Bangalore, the US, and other global sites to deliver production-quality IP on schedule\nThe Impact You Will Have\nYour RTL will ship in customer SoCs powering data center infrastructure, automotive platforms, and AI systems used by millions of people\nThe micro-architecture decisions you make today will determine whether a customer's chip meets their performance and power targets six months from now\nYour coverage improvements and directed tests will catch silicon bugs before tapeout, saving customers months of respins and lost revenue\nThe design quality and documentation you deliver will set the standard for how the rest of the IP team approaches complex protocol implementations\nYour timing closure work on multi-gigabit interfaces will enable Synopsys to stay ahead in the race toward higher-speed Ethernet and interconnect IP\nThe technical reviews you provide will level up junior engineers and prevent architectural mistakes from becoming costly late-stage fixes\nYour ability to work across sites will keep globally distributed projects on track and reduce friction in cross-functional handoffs\nWhat You'll Need\nBachelor's in Electrical Engineering with 8+ years of hands-on ASIC or IP design experience, or Master's with 6+ years\nDeep RTL design experience on IP cores or SoC subsystems that have taped out or shipped to customers\nStrong working knowledge of at least one protocol from this list: AMBA (AHB, AXI, CHI), SD, eMMC, DDR, PCIe, USB, MIPI. High-speed Ethernet (100G and above) experience is a strong plus\nProven ability to create micro-architecture and detailed design documents from functional specs for small to medium complexity blocks, especially control-path designs like async FIFOs, DMA engines, or SRAM/DPRAM interfaces\nHands-on experience with Verilog or SystemVerilog, simulation tools, synthesis flows, static timing analysis, lint, CDC, and formal verification tools\nSolid understanding of high-speed, low-latency design techniques and timing closure challenges. Experience with datapath designs or arithmetic algorithms like FEC is a plus\nFamiliarity with Perforce or similar version control systems, and scripting in Perl or shell for automation\nWho You Are\nYou can take a vague feature request and turn it into a clean, implementable design without needing three rounds of clarification meetings\nWhen you review RTL, you catch the subtle issues that would have caused problems in integration, and you explain them clearly enough that the engineer learns something\nYou know how to prioritize when you are juggling timing closure, coverage improvements, and a design review scheduled for tomorrow, and nothing falls through the cracks\nYou communicate technical tradeoffs in writing and in review meetings with enough clarity that engineers in other timezones can act on your feedback without a follow-up call\nYou push back when a spec is ambiguous or a schedule does not account for real design complexity, and you do it in a way that moves the conversation forward\nYou treat documentation as part of the design, not an afterthought, because you know the next person reading your micro-arch doc might be you in six months\nThe Team You'll Be Part Of\nYou will join the IPG Group at the Bangalore Design Center as a technical individual contributor working on DesignWare IP cores. This is a multi-site team spread across global locations, focused on delivering high-speed protocol IP in areas like Ethernet, AMBA, PCIe, USB, MIPI, and memory controllers. The work is technically challenging, the designs are complex, and the team expects you to own your deliverables with minimal supervision while collaborating across timezones to hit shared milestones.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Verification Engineer - PCIE", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-19", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Verification-Engineer---PCIE_JR2019559", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science.\nThe GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nYou will be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.\nYou will build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\nYou are expected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.\nYou will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech. with 2+ years of relevant experience\nExperience in verification at Unit/Sub-system/SOC level using Verilog and SystemVerilog\nExperience with verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)\nExperience in developing and working in functional coverage based constrained random verification environments\nExperience in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nExcellent problem solving skills\nKnowledge of PCIE protocol - Gen3 and above\nProficiency in Testbench development using SystemVerilog\nPerl, Python or similar scripting and SW programming language experience\nGood debugging and analytical skills\nGood interpersonal skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, Nvidia is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "IO and Mixed Signal Circuit Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-08-19", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/IO-and-Mixed-Signal-Circuit-Design-Engineer_R026863", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nWork as part of Mixed Signal and IO Library Development team in Central Engineering. Primary responsibilities include:\nDesign and verification of IO interfaces and mixed signal blocks such as POR, process monitors, voltage/temperature sensors, crystal oscillators etc.\nRTL coding, synthesis and verification of digital wrappers that interface with analog circuitry\nInterface with both custom and P&R layout engineers and oversee physical design and verification.\nDevelop functional models and perform timing characterization of these cells.\nDirectly interface with end customers to understand their requirements, come up with specifications and implement circuit designs that support them.\nCreate necessary infrastructure and generate test vectors to support silicon validation of these blocks on test chips.\nWork with test engineers to support silicon validation either on ATE or on the bench.\nDevelop accurate documentation in the form of datasheets, application notes and integration guides\n\nSkills and Qualifications Required:\nEducational requirements: MSEE with a minimum of 5-15 years of hands-on experience in independently designing mixed signal circuits especially in newer CMOS technologies such as 5nm or 3nm\nMust have experience in designing analog circuits such as PLLs, LDOs, Bandgap references, ADCs or DACs--knowledge of AMS methodology and analog circuit modeling will be a plus\nMust be proficient with Cadence Virtuoso Schematic Capture and ADE along with an excellent knowledge of spice based simulators such as Spectre and/or Hspice\nWorking knowledge of LVS, DRC along with EM/ESD verification tools such as Totem/Pathfinder/PER\nStrong written and oral communication skills in English to be able to work effectively across geographies as well as to be able to interface with end customers\nRequire proficiency in automation using shell scripting or any other languages such as SED, AWK, TCL or PERLˇ\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "CPU Physical Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-08-19", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/CPU-Physical-Design-Engineer_JR0285673-1", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nAs a CPU Physical Design Engineer, you will play a pivotal role in implementing high-performance, low-power CPU designs from RTL to GDSII. You will focus on detailed processes such as synthesis, placement, routing, timing analysis, and power optimization, enabling designs that meet stringent performance and efficiency targets. Your work will directly influence the success of Intel's next-generation CPUs and their manufacturing readiness, contributing to innovative advancements in computing technology.\n\nBusiness Group\nYou will join the Advanced Computing and Engineering (ACE) group, a dynamic team dedicated to designing Intel's latest high-performance CPUs using cutting-edge technologies. This group focuses on delivering innovative solutions that propel Intel's leadership in the semiconductor industry. Collaborating across multiple domains, the team drives groundbreaking designs that support Intel's mission of creating world-changing technologies to enrich the lives of every person on Earth.\n\nKey Responsibilities\n- Perform physical design implementation from RTL to GDSII, including synthesis, placement, routing, clock tree synthesis, and optimization.\n- Conduct static timing analysis, power distribution analysis, and reliability verification to ensure design convergence and high manufacturability.\n- Collaborate with logic, circuit, architecture, and automation teams to improve CPU microarchitectures and design methodologies.\n- Work closely with industry-leading EDA vendors to enhance tool capabilities for high-speed, low-power CPU development.\n- Optimize designs for power, frequency, and area, ensuring product-level parameter excellence.\n- Participate in developing and improving physical design methodologies and flow automation for future projects.\n\nQualifications:\nMinimum Qualifications\n- Bachelor's degree in Electrical, Electronics, or Computer Engineering with 6+ years of physical design experience, or a Master's degree with 4+ years of relevant experience, or a PhD with 2+ years of experience.\n- Technical expertise in synthesis, placement, clock tree synthesis (CTS), and routing tools, particularly using Synopsys and Cadence platforms.\n- Proficiency in timing signoff, formal verification, and low-power design techniques.\n- Solid understanding of submicron process node technologies and layout verification methods such as LVS/DRC.\n- Skilled in power estimation, power optimization, and power delivery methodologies.\n\nPreferred Qualifications\n- Familiarity with scripting languages like Tcl, Perl, and Python for automating physical design workflows.\n- Experience with Verilog or VHDL for hardware description and design execution.\n- Strong communication skills, both verbal and written, for collaborative problem-solving.\n- Demonstrated ability to work effectively in dynamic environments across geographies.\n- Knowledge of innovative feature feasibility studies and SD flow methodologies.\n\nBe part of a world-class team driving innovation in CPU design. Apply today to contribute to Intel's mission of shaping the future of technology.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Staff Engineer", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-08-18T06:04:24+00:00", "url": "https://jobs.infineon.com/careers/job/563808971773331", "is_hardware": true, "platform": "eightfold", "jd_text": "We are seeking an experienced Senior RF IC Test Development Engineer to lead Automated Test Equipment (ATE) hardware and software development for complex RF integrated circuits on the Teradyne UltraFLEX platform. The successful candidate will collaborate with cross-functional teams to develop robust test solutions, optimize test coverage and cost, drive characterization activities, and enhance manufacturing test efficiency and yield.\n\nYour role\nKey responsibilities in your new role\n\nLead ATE hardware and software development for complex RF IC products using the Teradyne UltraFLEX platform.\nCollaborate with design, product, validation, and manufacturing teams to develop comprehensive test plans that maximize test coverage while minimizing test cost.\nLead RF IC characterization activities on ATE and analyze test results to ensure product quality and performance.\nWork closely with development teams to define Design-for-Test (DFT) requirements and implement effective test strategies.\nDevelop innovative test methodologies and debug silicon-related issues during product development and production.\nDrive continuous improvements in test time reduction, multisite optimization, throughput enhancement, and yield improvement.\nProvide regular project updates and technical status reports to core team members and stakeholders.\nSupport new product introduction (NPI) activities and production test readiness.\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Semiconductor Engineering, or a related field.\n5+ years of experience in semiconductor test development with a proven track record in RF IC test solutions.\nStrong expertise in Automated Test Equipment (ATE) development, including both hardware and software.\nHands-on experience with the Teradyne UltraFLEX platform.\nDeep understanding of DFT methodologies, including MBIST, JTAG, SCAN, and IDDQ.\nExperience in silicon debug, failure analysis, and vector translation from standard formats to ATE environments.\nStrong knowledge of RF measurements, characterization, and production test optimization.\nProven ability to drive yield enhancement, test cost reduction, and throughput/site-count optimization.\nExpertise in RF IC testing, characterization, and semiconductor product development.\nExperience supporting New Product Introduction (NPI) and production test readiness.\nExcellent communication, stakeholder management, and cross-functional collaboration skills.\nAbility to develop robust, scalable, and high-quality test solutions for complex semiconductor products.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nAnand Rawal", "jd_status": "stored"}, {"title": "PD Architect", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-08-18T05:39:00+00:00", "url": "https://global-external-amd.icims.com/jobs/89233/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. THE ROLE: As a member of the S3 India physical design team, you will help bring to life cutting-edge designs. As a member and lead of the Physical design implementation team, you will work closely with the SOC architects, Fellows/Sr Fellows, Cross functional leads, Customers, Design leads, IP teams, Physical Design leads and PD/STA engineers to achieve first-pass silicon success. You will be expected to innovate and lead, design implementation and convergence activities in the RTL2GDSII SOC implementation perspective. In this position as a Physical Design Expert, you will be part of a world-class team developing groundbreaking high-performance SOCs/ASICS for DPU/APU/GPU/Others designs. These products are targeted for AI Data Centre, Game Consoles, High-end Discrete Graphics, Thin and Light Laptops, Artificial Intelligence solutions for Inference/Training, Telecommunication, Automotive applications and more. This is a great opportunity to join a talented team that is well-invested in the implementation of futuristic designs in advanced process nodes. THE PERSON: As a PD (Physical Design) Architect, we are seeking a highly experienced and innovative person, who will be responsible for driving Physical Design, Timing closure, Power Optimization and Signoff strategies, methodologies, setting industry standards flows along with spearheading multiple SOC/ASICs execution for the successful delivery of project tape-outs from RTL2GDSII. You will use your knowledge of Physical design and timing closure to lead a complete set of activities, specifically Synthesis, Constraints, PnR, Timing, Physical Verification and Signoff, including IP integration and full-chip signoff aspects. Your leadership and strategic vision will guide the development of methodologies that optimize SOC development cycle. Additionally, you will mentor team members and effectively communicate complex technical concepts to align stakeholders and drive successful implementation. This position requires a detail-oriented candidate who possesses good communication skills and can handle/work with teams. KEY RESPONSIBILITIES: Go to person for multiple SOC/ASICs in RTL2GDSII domain comprising of physical design implementation, timing closure and various signoff (timing, physical verification, IREM, Power etc) activities Provide leadership and mentoring towards convergence of highly complex tiles/partitions/blocks spanning across multiple Subsystems and IPs , not limited to PCIE, DDR, CPUs, GPUs, Gfx, ETH, UCIE etc. Cross-Functional Leadership - Collaborate with various teams, including architecture, design, verification, DFT and product management, to ensure PPA goals are met. Strategic Planning: Provide strategic direction to SOC/Subsystem and Tile/Partition level execution, that align with industry trends and company goals. Foster a culture of innovation by encouraging research and experimentation in RTL2GDSII activities. Identify opportunities for patents and publications. Good understanding of horizontal sign-off flows like VCLP, Formal Equivalence, Low Power Checks with expert level understanding of timing convergence (both tile-level and full chip timing), and full chip integration flows. Understanding of design requirements, timelines and various milestones of a project and tracking project convergence status accordingly covering all aspects of the design cycle. Drive methodology development ideas and drive internal forums towards adoption of latest flow/methodologies and AI technologies. Collaborate with CAD and EDA vendors to further strengthen AMD and S3 PD closure methodology. Provide technical direction, guidance, mentorship and support to the engineering team. Stay abreast of the latest advancements in RTL2GDSII and represent the company in industry forums, conferences, and collaborations to influence and adopt best practices. Define and track key performance indicators (KPIs) related RTL2GDSII . Report on progress and impact to senior leadership and executives. Possess good understanding of foundry DRM and must have collaborated with DTCO and FTO in the past PREFERRED EXPERIENCE: Experienced PD/Timing professional with a minimum of 15 years of industry experience in the Physical design domain (RTL to GDS, STA, Physical verification, timing signoff, tapeout). SOC and Block-level implementation (Place and Route), which includes Floorplanning, Timing Closure and Physical Verification. Well-versed with Physical Design verification signoff techniques such as Formal Equivalence, IR&EM, Timing Closure (STA), Physical verification, VSI, Formal Equivalence Check or LEC, etc. Expert level understanding of Power, Performance and Area (PPA) optimisation techniques. Hands on experience with Perl/TCL/Shell/Python scripting, and Verilog/VHDL RTL design and latest use of AI technologies Expert level understanding of EDA tools across Synopsys and Cadence Excellent presentation and inter-communication skills. Qualifications: B.Tech/M.Tech/MS/Ph.D. in Computer/Electronics/Electrical Engineering. Candidate must have the ability to drive/manage projects from RTL to GDS, with a minimum experience of managing more than 5-10 tape-outs. Proficient in physical design industry-standard EDA tools like Fusion compiler/ICC2/Primetime/Redhawk/PTPX, low power and physical verification tools. #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Power Modelling Engineer, Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-18T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719961930", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Systems Engineering\nGeneral Summary:\n\nJob Summary:          \n8 to 12 years of experience in Front end Power modeling, power estimation and power analysis of complex Qualcomm propriety DSP IP\n\nDSP design team is responsible for delivering high-performance DSP cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space\n\nQualcomm is the largest fabless design company in the world, generating over $35 Billion in annual revenues from chipsets and royalties from intellectual property. Qualcomm provides hardware, software and related services to nearly every mobile device maker and operator in the global wireless marketplace\n\n Job Responsibilities: \nIn this highly visible and interactive role, your primary responsibility will be to drive performance verification/correlation of DSP IP by working with global DSP design team involving architecture, implementation, post silicon and back-end teams\n\nResponsible for analyzing power and performance efficiency across cores/chipsets.\n\nResponsible for building infrastructure for performance verification and verifying performance of processors\n\nWork with front end power and backend teams to build power models, estimate power for AI/ML workloads.\n\nWriting specific targeted tests to measure power and performance of the processor.\n\nInvolves having a deep understanding of processor micro-architecture and triaging performance issues in RTL and simulator\n\nSkillset/Experience:          \n8-12 years’ experience in processor/ASIC power modelling, power estimation and analysis.\n\nExperience in micro-architecture testing for modern high-performance, low power processors\n\nExperience in writing tests and building infrastructure that tests power and performance of modern processors.\n\nExperience in application-level power and performance analysis\n\nProgramming/Scripting Skills — C, C++, Perl, Python, Shell, Make file TCI\n\nSolid background and understanding of Digital Design, RTL design, improving model performance and Processor Architecture\n\nStrong troubleshooting, analytical and debug skills\n\nPrior experience is performance correlation of Processor subsystems (ARM/DSP) is preferred\n\nShould have excellent inter-personal, communication skills and ability to work in a fast-paced exciting environment\n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.\n                                                                    OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience.\n                                                                    OR\nPhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Data Converters Mixed Signal Lead, Sr. Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-18T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718893361", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > ASICS Engineering\nGeneral Summary:\nJob Description\n\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nSenior Staff – MSIP Design (RFA Connectivity IP) – Bangalore\nAbout the Team\nQualcomm’s RFA Connectivity team is a global organization responsible for delivering high-performance, power-efficient, and cost-optimized Connectivity IP solutions—including PMU, Transceivers, and MSIP—for Mobile, Compute, AR/VR, Automotive, and IoT products.\nOur portfolio spans key connectivity technologies such as Wi-Fi, Bluetooth, GNSS, and UWB, driving innovation across a wide range of devices and use cases.\n\nRole Overview\nWe are seeking a Senior Engineer (10+ years of experience) to join the MSIP Bangalore Design Team. This team works closely with RF Transceiver teams to develop cutting-edge IPs for Cellular and Connectivity systems, as well as high-performance RF front-end components across advanced process nodes.\n\nKey Responsibilities\nLead and contribute to MSIP circuit design, with strong ownership from system definition and specification through silicon validation and debug\nOversee layout, verification, and documentation of MSIP blocks supporting radio transceivers and SoCs\nDrive design excellence across the full lifecycle:System architecture and design trade-offs\nCircuit design and simulation\nPost-silicon validation and debug\n\nCollaborate closely with cross-functional teams including RF, digital, and system teams\nStay up to date on industry trends, competitor products, and emerging MSIP technologies using publicly available information\nProvide technical leadership, including mentoring junior engineers and managing small project teams (where applicable)\n\nRequired Technical Expertise\nStrong experience in one or more of the following areas:\nHigh-speed / high-performance MSIPs, such as:ADCs (≥320 MHz bandwidth)\nDACs\nPLLs\n\nTools & Skills\nProficiency in Cadence ADE, Virtuoso XL, Spectre and other analog design flows\nWorking knowledge of MATLAB, Verilog / Verilog-AMS, and related tools\nExperience with high-speed interfaces between MSIP and digital subsystems\nStrong debugging and silicon validation experience\n\nPreferred Qualifications\nExperience with high sampling rate SAR ADCs\nPrior experience in leading small teams and managing multiple projects\nExposure to advanced technology nodes and multi-domain integration (RF, analog, digital)\n\nWhat We Value\nStrong analytical and problem-solving skills\nOwnership and end-to-end accountability\nCollaborative mindset across global teams\nAbility to balance performance, power, and cost trade-offs in complex systems\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Performance Validation Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-18T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446717773559", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Software Engineering\nGeneral Summary:\nPerformance Benchmark\nLocation: Bangalore\nRole Type: Engineer\nDomain: ARMv9 Server Platforms, CPU Performance\nRole Summary\nLead Qualcomm’s server CPU performance benchmarking and optimization efforts for next-generation ARMv9 platforms. Own performance strategy, guide a team of performance engineers, and drive end-to-end analysis across silicon, firmware, kernel, and workloads.\nKey Responsibilities\nLeadership & Strategy\nLead and mentor a team of performance engineers.\n\nDefine performance KPIs, benchmarking strategy, and roadmap.\n\nDrive alignment across architecture, silicon, firmware, kernel, compiler, and workload teams.\n\nBenchmarking & Characterization\nLead SPEC CPU, SPECjbb, SPECrate, cloud workload analysis.\n\nCharacterize CPU, memory, I/O, NUMA, ARMv9 features.\n\nRegression & Monitoring\nOwn regression detection and CI/CD automation.\n\nTrack KPIs across firmware, software, and hardware.\n\nRoot Cause & Optimization\nLead investigations using PMU counters, perf, VTune, Streamline.\n\nGuide kernel, BIOS/UEFI, compiler, SVE/SVE2 optimizations.\n\nCustomer & Partner Engagement\nValidate workloads for hyperscalers, Kubernetes, enterprise.\n\nSupport OEM/ODM benchmarking and field issues.\n\nMinimum Qualifications\n1+ years in CPU performance engineering/system software.\n\nStrong Python, Bash, C/C++.\n\nDeep microarchitecture, memory, NUMA, PCIe/CXL understanding.\n\nARMv9/SVE/SVE2, virtualization, firmware experience.\n\nHands-on with SPEC suites, cloud-native benchmarks.\n\nLeadership experience.\n\nIdeal Attributes\nAnalytical, data-driven, strong debugging.\n\nEffective cross-functional collaboration.\n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SoC Silicon Validation - Embedded Firmware Infra development Engineer, Sr. Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-18T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718306806", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nMinimum Qualifications :\nBachelor’s / master’s degree in Electronics/Electrical Engineering, Computer Science, Information Systems, or related field.\n\n6+ years of Embedded Hardware Engineering experience or related work experience.\n\nResponsibilities :\nYou will be part of Qualcomm Snapdragon SoC - Silicon Validation team, particularly in the bring up of SVE infra framework for the enablement of VI content in production testing.\n\nYou will be working with IP validation teams and Systems validation Lead/systemcontent engineer for bring up the framework.\n\nOwn SoC frequent regression and execute end-to-end regression suite by considering SoC design corner cases w.r.t power and performance. Executing these releases on bench in lab and supporting the DFT, SLT teams in Debug and enabling different features in the framework.\n\nWork with a relevant team member for regular reporting of issues and failure debugs.\n\nMandatory Skills :\nBasics of ARM SoC architecture, Multicore/Multiprocessor with SMP/MTE/heterogeneous cores.\n\nC language expertise for low level programming, Assembly language for any processor, C-assembly interworking.\n\nHands on python programming, test automation programming will be an added advantage.\n\nPreferrable having hands on experience with remote debugging using JTAG tool debuggers, customization of compiler/linker tool chain.\n\nExposure to boot process, MMU/SMMU page tables configurations. Operating systems/RTOS/Linux kernel internals. Bash scripting, SW application development.\n\nExposure to working on programming for DFT and Modem characterization environment is added advantage.\n\nExposure to working on emulation/pre-si environment is added advantage\n\nShould have good exposure to software development life cycle\n\nDesired Skills:\nExposure to SoC architecture paradigms – interconnects, power management,\n\nSoftware development for silicon enablement, silicon validation\n\nBring-up of hardware-software solution on FPGA/emulation platforms and on fresh SOC designs\n\nSoftware for power/performance KPIs\n\nGood knowledge of ARM Cortex-A7/A8) / x86 / PowerPC CPU and memory system architecture\n\nWeakly ordered memory model/pipelining of memory systems/memory barriers\n\nSoftware development towards higher performance of multi-threaded applications using lower power\n\nTop level of ASIC design methodology is an added skill\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Design Evaluation Engineer", "company": "Analog Devices", "location": "India, Bangalore, Nova", "date_posted": "2026-08-18", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-Nova/Staff-Design-Evaluation-Engineer_R261958", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nJob Title: Staff Design Evaluation Engineer\nAs part of the Post‑Silicon Engineering organization, you will be responsible for bench evaluation (validation) activities for new SoC product developments within the Digital Business Unit at Analog Devices. This role involves working closely with Design, Product Test Engineering (PTE), and Applications teams to drive the post‑silicon phase of product development, from first‑silicon bring‑up through full validation across Process, Voltage, and Temperature (PVT) corners.\nThe ideal candidate is technically strong, has hands‑on experience in digital and mixed‑signal validation, and demonstrates the ability to collaborate effectively with cross‑functional, global teams to ensure robust silicon validation, characterization, and production readiness.\n\nKey Responsibilities\nDesign and develop innovative, reliable, and efficient bench hardware and software solutions for complex digital and mixed‑signal SoCs.\nDrive the post‑silicon evaluation lifecycle, including hardware bring‑up, silicon bring‑up, functional validation, debug, and PVT characterization.\nDevelop, execute, and automate test scripts to support validation, debug, and characterization activities.\nEngage early with Design teams to contribute to DFT definition and development, improving debug capability and overall testability.\nWork in close collaboration with Product Engineering and Test Engineering teams to define, execute, and align on a comprehensive Silicon Characterization and Measurement (SCM) plan.\nPartner with Applications teams to define system‑level use cases for bench validation and customer‑focused testing.\nSupport correlation between bench evaluation results and production test data to enable smooth product ramp and release.\n\nQualifications & Experience\nB.Tech/M.Tech degree in Electronics or Electrical Engineering.\n4–8 years of hands‑on experience in high‑speed digital validation and Firmware development of MCUs (ARM Cortex), DSPs, and NPUs.\nStrong experience in MCU/Processor Test Firmware development\nStrong experience in electrical compliance characterization and system validation of high‑speed interfaces such as DDR3, PCIe, CSI, USB, and HDMI.\nExperience in characterization of precision analogue IPs including ADCs, DACs, and voltage references.\nWorking knowledge of validating communication protocols such as I²C, SPI, USB, and other serial interfaces.\nExperience running system‑level performance benchmarks for power and speed across MCUs, DSPs, and NPUs.\nFamiliarity with embedded toolchains such as IAR, Keil, and similar development environments.\nStrong programming skills in Python, C, C#, and VHDL/Verilog for automation, debug, and validation.\nHands‑on experience with bench instruments including oscilloscopes, Audio Precision systems, signal generators, and analyzers.\nProven ability to work closely with Design, Product Engineering, and Test Engineering teams to align evaluation, characterization, and production test strategies.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Senior DFT Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-18", "url": "https://careers.arm.com/job/bengaluru/senior-dft-engineer/33099/99391140016", "is_hardware": true, "platform": "talentbrew", "jd_text": "Experience: 10+ Years of experience\nRole: Mixed Signal DFT lead/engineer\n\n \nRole Overview\n\n \nWe are looking for an experienced DFT Engineer with 10+ years of semiconductor industry experience and strong hands-on expertise in DFT verification of mixed-signal blocks, Pattern debug on ATE, and Tessent-based pattern generation.\nThe ideal candidate will have a strong understanding of mixed signal IP like SERDES, Sensors, non-volatile memory (effuse/otp/),  JTAG/iJTAG architectures, PDL development for Pattern development, in-depth understanding on ATE and  The candidate should be capable of independently debugging complex DFT and production-test issues and driving them to closure.\n\n \nKey Responsibilities\n\n•    Perform DFT verification of mixed-signal IP blocks in complex SoC\n•    Own verification and debug of DFT features across block and SoC levels.\n•    Develop, verify, and debug ATE test patterns and drive pattern bring-up on silicon.\n•    Perform ATE pattern debug and stabilization, including root-cause analysis of simulation-to-silicon and tester-related failures.\n•    Work extensively with JTAG (IEEE 1149.1) and iJTAG (IEEE 1687) architectures and associated verification flows.\n•    Develop and maintain PDL (Procedural Description Language) for embedded instruments and iJTAG networks.\n•    Generate, validate, and debug DFT patterns using Siemens Tessent tools.\n•    Debug complex pattern, timing, protocol, and DFT infrastructure issues across simulation and ATE environments.\n•    Collaborate closely with DFT, design, verification, physical design, product engineering, and test engineering teams during pre-silicon and post-silicon phases.\n•    Drive technical issues independently from initial investigation through root-cause identification and final resolution.\n\nRequired Skills & Experience\n\n•    10+ years of hands-on experience in DFT, DFT verification.\n•    Strong hands-on experience with verification of mixed-signal blocks from a DFT perspective.\n•    In-depth understanding of ATE architecture, test programs, pattern formats, and pattern execution/debug flows.\n•    Proven experience in:\no    Loopback test verification for high speed SERDES blocks (like UCIe, DDR PHY, PCIE/Ethernet, USB) based on BIST\no    Sensors and calibration procedures\no    Lane repair schemes\no    ATE pattern bring-up and debug\no    Pattern stabilization\no    Failure analysis and root-cause debugging\no    Test-time reduction and optimization \no    Know-how on SCAN & MBIST is plus\n•    In-depth understanding of JTAG and iJTAG protocols, including IEEE 1149.1 and IEEE 1687.\n•    Strong experience in developing pattern specifications, PDL development and debug using Siemens Tessent tools.\n•    Good understanding of DFT concepts such as test access mechanisms, embedded instruments\n•    Excellent analytical and problem-solving skills, with the ability to debug complex cross-domain issues.\n•    Ability to work independently and take complete ownership of technical deliverables.\n•    Strong communication skills and ability to collaborate effectively with geographically distributed engineering teams.\n \n \n \n#LI-BB1\n \nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Staff Foundation IP Engineer (Arithmetic/DSP)", "company": "Lattice", "location": "Pune, India", "date_posted": "2026-08-18", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Pune-India/Senior-Staff-Foundation-IP-Engineer--Arithmetic-DSP-_R-102890", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\n\nA successful candidate will join a team designing and developing Lattice FPGA software tools at Penang. The candidate will contribute to research, design and development of FPGA Foundation IP and IP Catalog tooling. The candidate is expected to work closely with cross-functional teams to plan and execute Lattice FPGA software release cycle including requirement analysis, feature scoping, development, testing and validation. The candidate also will be responsible for maintaining existing software product tools and develop improvement plan to increase the test coverage to achieve high product quality.\n\nKey Responsibilities:\nDesign and implement DSP-centric foundation IP blocks, including multipliers, accumulators, FIR/IIR filter primitives, and arithmetic units targeted for integration into FPGA fabric.\n\nDevelop RTL (VHDL/Verilog/SystemVerilog) for DSP hard macros and programmable DSP slices.\n\nPerform functional simulation and timing analysis to ensure correctness and performance targets are met.\n\nEngage with software and tools teams to ensure DSP IP is correctly modeled in simulation libraries and synthesis flows.\n\nRequired Qualifications:\nBachelor's or Master's degree in Electronics/Electrical Engineering, Computer Engineering, or a related discipline.\n\n8 or more years of experience in IP design or ASIC/FPGA engineering.\n\nStrong proficiency in RTL design using Verilog, VHDL, or SystemVerilog.\n\nWorking experience in DSP theory and algorithms: filtering, FFT, fixed-point arithmetic, sample-rate conversion.\n\nPreferred Qualifications:\nExperience with functional verification methodologies (SystemVerilog Assertions, formal verification).\n\nFamiliarity with synthesis and static timing analysis tools (Synopsys Design Compiler, PrimeTime, Radiant, Quartus or equivalent).\n\nWorking knowledge of FPGA architectures and programmable DSP slice design.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Junior Verification Engineer", "company": "Nokia", "location": "Bangalore, Karnataka, IN", "date_posted": "2026-08-18", "url": "https://fa-evmr-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/38750", "is_hardware": true, "platform": "oracle", "jd_text": "As a Junior Verification Engineer, conducts target-oriented research to support the design, development, integration, verification, testing, and maintenance of hardware, software, and systems. Contributes to the continuous improvement of products and processes, supports customer-specific feature development, and performs integration, verification, and testing (IVT) to ensure system components meet defined requirements and specifications. Maintains laboratory equipment, tools, and test environments.\n\nResponsibilities\nDeveloped comprehensive test plans and test cases for optical system features to ensure high product quality.\nExecuted functional and system-level tests, identified defects, and reported bugs using defect tracking tools.\nCollaborated with architects and developers to analyze issues, verify fixes, and ensure successful resolution.\nDeveloped and maintained automated test scripts to improve test efficiency and coverage.\nBuilt and enhanced AI-assisted verification frameworks for intelligent test execution and validation.\nCreated data pipelines and analytics dashboards to convert test results into actionable quality insights.\nDesigned, validated, and optimized optical networking test scenarios for platform and service assurance.\nApplied machine learning techniques to predict potential failures, identify quality risks, and support continuous quality improvement.\n\nQualifications\nYou have:\nBachelor's degree with 3-5 years of relevant experience. \nApplied strong knowledge of communication and networking systems to support verification and testing activities.\nDeveloped and maintained Python-based automation scripts to improve test efficiency and coverage.\nWorked with test automation frameworks to streamline validation and regression testing.\nPerformed data analysis to identify trends, defects, and opportunities for quality improvement.\nIt would be nice if you also had:\nLeveraged AI/ML fundamentals and AI-assisted tools, including LLMs, Copilot, and Cursor, to enhance test generation and troubleshooting.\nTroubleshot complex networking scenarios to identify root causes and validate solutions.\nCollaborated with cross-functional teams to resolve technical issues and ensure product quality.\nDemonstrated a strong learning mindset and adapted quickly to fast-paced, high-technology development environments.\n\nAbout the company\nAdvancing connectivity to secure a brighter world.\n\nNokia is a global leader in connectivity for the AI era. With expertise across fixed, mobile and transport networks, powered by the innovation of Nokia Bell Labs, we’re advancing connectivity to secure a brighter world. \n\nLearn more about life at Nokia.\n\nOur recruitment process\n\nWe act inclusively and respect the uniqueness of people. Our employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.\n\nIf you’re interested in this role but don’t meet every listed requirement, we still encourage you to apply. Unique backgrounds, perspectives, and experiences enrich our teams, and you may be just the right candidate for this or another opportunity.\n\nThe length of the recruitment process may vary depending on the specific role's requirements. We strive to ensure a smooth and inclusive experience for all candidates. Discover more about the recruitment process at Nokia.\n\nAbout the organization\nSome of our benefits in India:\n\nFlexible and hybrid working arrangements to support work–life balance\n\nHealth and well-being support – medical insurance for you and your family, health check-ups, life and accident insurance, well-being programs, and employee resource groups \n\nA minimum of 90 days of Maternity and Paternity Leave based on eligibility\n\nPersonal Support Service 24/7 – a confidential support channel open to all Nokia employees and their families in challenging situations\n\nCareer growth & mobility – technical career paths, job rotations, international assignments, and relocation support\n\nContinuous learning – technical certifications, mentoring programs, coaching, and digital learning platforms\n\nOpportunities to innovate and contribute through Nokia’s research and development environment\n\nRecognition programs that celebrate outstanding contributions\n\nWorkplace support – ergonomic working support and mobile device programs based on eligibility", "jd_status": "stored"}, {"title": "Senior DFT Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-18", "url": "https://careers.arm.com/job/bengaluru/senior-dft-engineer/33099/99657738400", "is_hardware": true, "platform": "talentbrew", "jd_text": "Responsibilities:\nArchitect, implement, and validate innovative DFT techniques on ARM SoCs. Insert DFT logic into SoC style designs at the RTL level and at the Synthesis gate level, validate all features, and generate ATE targeted test patterns to be run on silicon. Work closely with front-end design and verification teams on DFT RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation.\nRequired Skills and Experience :\nCore DFT skills considered for this position should include some of the following: Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics\nExperience ranges from 3- 20 Years.\nExperience coding Verilog RTL, TCL and/or Perl\nProficient in Unix/Linux environments\nBachelors or Master’s degree or equivalent experience in Electronic Engineering, Computer Engineering, or a related field\n“Nice To Have” Skills and Experience :\nFamiliarity with IEEE 1149, 1500, 1687, 1838\nSynthesis & Static Timing Analysis\nFamiliarity with SoC style architectures including multi-clock domain and low power design practices.\nValidated understanding of Siemens DFT tools\nFamiliarity with Arm IP like the following: Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, CoreSight debug\nExperience with 2.5D and 3D test\nAbility to work both collaboratively on a team and independently\nHard-working and excellent time management skills with an ability to multi-task\nAn upbeat demeanor to working on exciting projects on the cutting edge of technology\nExperience with Siemens, Cadence, and/or Synopsys DFT and simulation tools\nIn Return:\n\nOur offices are outstanding places to collaborate. If you are interested, but unsure whether you tick all the boxes, we still would love you to reach out! We are keen to welcome versatile people into Arm!\n \n#LI-PS2\n \nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Verification Engineer -  ARM Fabric Unit Level", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-18", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Verification-Engineer----ARM-Fabric-Unit-Level_JR2023540", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.\n\nWe are seeking hardworking, determined, and imaginative individuals to join our automotive verification group. As the owner of HSIO IP's unit level verification, you will contribute to projects crafting the future of automotive chips and systems. You will gain direct experience of chip working with high-performance CPU and memory sub-systems, NOC-based interconnect fabric, high-speed I/Os, and various advanced technologies used in our Tegra chips.\n \nWhat you'll be doing:\nYou will develop UVM-based verification test benches and methodologies. These will verify our in house ARM architecture based distributed fabric needed to transport control, sidebands and data as needed. During the course of a project, you will drive the following aspects of verification for your unit:\nArchitect the testbenches and craft verification environment using SV and UVM methodology\nDefine test plans, tests and verification infrastructure for modules, clusters and systems\nBuild efficient and reusable bus functional models, monitors, checkers, and scoreboards\nImplement functional coverage and coordinate the verification closure process for the unit\nWork with architects, designers, FPGA, and post-silicon teams to ensure that your unit is robust\n\nWhat we need to see:\nBTech or MTech in ECE, EE, CSE, or an equivalent degree is required. Candidates should have 2+ years of demonstrated ability in verification closure of complex units, sub-systems, or SOC level verification.\nProven experience in ARM architecture and protocols (AXI, AHB and APB)\nExperience in the latest verification methodologies like SV and UVM\nGood debugging and analytical skills with exposure to industry-standard verification tools for simulation and debug\nGood interpersonal skills, ability to work as a diligent teammate, and excellent communication skills to collaborate with cross-cultural global teams and work in a matrix organization\n\nWays to stand out from the crowd:\nExposure on using AI (like Claude or Cursor) extensively for code development would be a big plus\nA mentality towards constant improvement and looking to build a multiplier effect through your work and automation\nExposure to Formal verification would be excellent\n\nWe have some of the most experienced and dedicated people in the world working at NVIDIA. If you're creative and independent, with a genuine passion for adopting the newest technology, we want to hear from you. Join us and be part of something outstanding!\n\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior Staff Engineer Design ", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-08-17T14:25:57+00:00", "url": "https://jobs.infineon.com/careers/job/563808971855121", "is_hardware": true, "platform": "eightfold", "jd_text": "#WeAreIn to draw on our creativity to develop analog and mixed-signal circuit solutions. Are you in?\n\nYour role\nKey responsibilities in your new role\n\nOwn end-to-end I/O library design and development, from specification to delivery.\nCollaborate with system architects to define and finalize I/O requirements and specifications.\nDrive I/O integration into SoCs/subsystems and resolve technical challenges.\nEnsure I/O quality sign-off and milestone compliance through robust review processes.\nMentor and guide design/layout teams to improve design quality, performance, power, and area efficiency.\nProvide hands-on circuit design support based on project needs.\nEnhance design and verification methodologies to improve quality and development efficiency.\nEnsure adherence to Infineon quality standards and library development processes.\n\nYour profile\nQualifications and skills to help you succeed \n\nBE/BTech/MTech in ECE/VLSI with 8+ years of experience in I/O design and development.\nStrong expertise in I/O interfaces including LVTTL, LVCMOS, DDR, SPI, xSPI, Oscillators, LVDS, and voltage-tolerant circuits.\nGood understanding of ESD, Latch-Up (LU), and I/O reliability concepts.\nHands-on experience with I/O library characterization methodologies and development flows.\nProven ability to technically lead small design and layout teams and drive project execution.\nTrack record of delivering silicon-proven designs from specification through implementation and validation.\nStrong analytical, debugging, and problem-solving skills.\nExcellent verbal and written communication skills.\nEffective team player with the ability to collaborate across cross-functional teams.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "ATE Test Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-17T12:50:15.507000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000143821595-ate-test-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "This role requires moderate hands-on expertise in ATE test development, product validation, and debugging. The candidate will contribute to the development of reliable and cost-effective test solutions, working closely with more senior engineers while progressively increasing autonomy on complex tasks. For this role you are expected to work to a provided schedule on problems of a moderate scope, with regular guidance and judgement. You are also expected to build and maintain stable work relationships for exchanging information with colleagues and leadership to collaboratively solve problems. \nRenesas Electronics, a leading global semiconductor company, is rapidly scaling investing in  power delivery business. Products include Point of loads (POL), Hotswap/Efuse, drivers. \nKey Responsibilities \nAs a Test Engineer you will play a crucial role in delivering world class test solutions with high quality and low cost of test for a fast growing business. Your responsibilities will include: \nImplementing ATE test solutions for final test, characterization, WT in both engineering and production \n\nDeliver test programs in languages such as C, or C++ to automate test processes \n\nCollaborating with cross-functional teams including design engineers, manufacturing teams, and quality assurance (QA) teams to address technical issues and optimize testing processes. \n\nAnalyzing test results, identifying trends, troubleshooting issues, and generating detailed test reports and documentation. \n\nStaying updated with industry trends, advancements, and best practices in semiconductor testing methodologies. \n\nBachelor’s degree in Electrical/Computer Engineering  \n2+ years of experience in test engineering or related field \n\nExperience with ATE platforms (COHU DMDX, STS8300 is a plus) \n\nBasic understanding of DFT concepts and production test flows \n\nExperience in debugging analog and mixed-signal circuits \n\nFamiliarity with lab equipment (oscilloscope, multimeter, spectrum analyzer) \n\nProgramming skills in C/C++, Python, or similar \n\nBasic knowledge of data analysis and statistical methods \n\nStrong understanding of analog parameters and a demonstrates and understanding of how to use lab equipment. \n\nFundamental understanding of using I2C, I3C, and SPI protocols \n\nKey Competencies \nStrong execution and hands-on approach \n\nGood problem-solving and debugging capability \n\nAbility to work in team environments with increasing autonomy \n\nAttention to detail and quality focus \n\nWillingness to learn and grow technically \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Staff Engineer, Analog Design", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-17T08:17:01.283000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000143768819-staff-engineer-analog-design", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "AI/ML driven ASIC Design and Implementation Automation Lead Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-08-17", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/AI-ML-driven-ASIC-Design-and-Implementation-Automation-Engineer_R-10063275", "is_hardware": true, "platform": "workday", "jd_text": "Job Description\n\nAs an “AI/ML driven ASIC Design and Implementation Automation Engineer”, you will work in a dynamic environment to explore methodology, flows and tools to improve efficiency and quality of results (power, performance, area, and verification) for SoC and IP development teams across the organization. You'll be working and connecting with AI/ML and automation experts in the industry to explore state-of-the-art AI/ML CAD techniques as a part of VLSI CAD SW, prescribe key methods and requirements for tools & features to leverage for ASIC design.\n\nIn this role, you will work & develop prototype solutions to evaluate various state-of-the-art AI/ML techniques to identify the best solutions in close collaboration with Architecture, IP design, SoC Design, Verification, Implementation and Design Enablement teams to drive new ways of working, improvements to current ways of working, addressing design quality challenges and continuously improve NXP Semiconductors design, verification and implementation flows. While developing these new ways of working, successful candidates will be working on actual designs and implementation to pilot and develop the automation.\n\nThis opportunity is to enable Digital Transformation to leverage state-of-the-art AI/ML ideas to improve NXP designs for the Edge-AI, Automotive Processors and Advanced microcontrollers in NXP.\nSuccessful candidate will be working in a fast-paced engineering environment, on a leading-edge advanced node technologies enabling automated building of exciting and complex SoCs.\n\nJob Summary\n\nExplore research ideas and solutions that bring AI/ML applications to VLSI design\nWork closely with Academic research communities in AI/ML for VLSI design, Architecture teams, IP and SoC designers and SoC Implementation teams from multiple sites to explore and evaluate for leading edge SoC technologies serving multiple industries\nThese automation applications include use of GenAI, Reinforcement Learning, Graph Neural Networks, and convolutional Networks\nStrong AI/ML expertise and software background required\n\nJob Qualifications\n\nBS or MS in Computer Science, Electrical Engineering, Computer Engineering or related disciplines with strong background in SW development\n5 years of experience in developing complex SW projects, and hands-on expertise in programming using Python & C++\nHands on experience in Unix/Linux, revision control (Git, BitBucket), SW development and debug tools\nExcellent analytical problem solving skills\nStrong verbal and written communication skills\n\nDesirable skills/experience:\n\nData structures, algorithms and SW development for optimization problems.\nPrior experience in VLSI CAD methodology and tool development\nUnderstanding or prior experience with EDA tools for design, verification, DFT and implementation\nStrong understanding of design, layout, constraints (SDC, Clocks, CDC, RDC), Static timing analysis, Low-power and Power-aware flows (UPF)\nExperience with Design revision control (GIT, DesignSync) and Make Splunk, Jenkins, LSF and CI/CD process\n\nMore information about NXP in India...\n\n#LI-29f4", "jd_status": "stored"}, {"title": "AI/ML driven ASIC Design and Implementation Automation Lead Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-08-17", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/AI-ML-driven-ASIC-Design-and-Implementation-Automation-Engineer_R-10063274", "is_hardware": true, "platform": "workday", "jd_text": "Job Description\n\nAs an “AI/ML driven ASIC Design and Implementation Automation Engineer”, you will work in a dynamic environment to explore methodology, flows and tools to improve efficiency and quality of results (power, performance, area, and verification) for SoC and IP development teams across the organization. You'll be working and connecting with AI/ML and automation experts in the industry to explore state-of-the-art AI/ML CAD techniques as a part of VLSI CAD SW, prescribe key methods and requirements for tools & features to leverage for ASIC design.\n\nIn this role, you will work & develop prototype solutions to evaluate various state-of-the-art AI/ML techniques to identify the best solutions in close collaboration with Architecture, IP design, SoC Design, Verification, Implementation and Design Enablement teams to drive new ways of working, improvements to current ways of working, addressing design quality challenges and continuously improve NXP Semiconductors design, verification and implementation flows. While developing these new ways of working, successful candidates will be working on actual designs and implementation to pilot and develop the automation.\n\nThis opportunity is to enable Digital Transformation to leverage state-of-the-art AI/ML ideas to improve NXP designs for the Edge-AI, Automotive Processors and Advanced microcontrollers in NXP.\nSuccessful candidate will be working in a fast-paced engineering environment, on a leading-edge advanced node technologies enabling automated building of exciting and complex SoCs.\n\nJob Summary\n\nExplore research ideas and solutions that bring AI/ML applications to VLSI design\nWork closely with Academic research communities in AI/ML for VLSI design, Architecture teams, IP and SoC designers and SoC Implementation teams from multiple sites to explore and evaluate for leading edge SoC technologies serving multiple industries\nThese automation applications include use of GenAI, Reinforcement Learning, Graph Neural Networks, and convolutional Networks\nStrong AI/ML expertise and software background required\n\nJob Qualifications\n\nBS or MS in Computer Science, Electrical Engineering, Computer Engineering or related disciplines with strong background in SW development\n5 years of experience in developing complex SW projects, and hands-on expertise in programming using Python & C++\nHands on experience in Unix/Linux, revision control (Git, BitBucket), SW development and debug tools\nExcellent analytical problem solving skills\nStrong verbal and written communication skills\n\nDesirable skills/experience:\n\nData structures, algorithms and SW development for optimization problems.\nPrior experience in VLSI CAD methodology and tool development\nUnderstanding or prior experience with EDA tools for design, verification, DFT and implementation\nStrong understanding of design, layout, constraints (SDC, Clocks, CDC, RDC), Static timing analysis, Low-power and Power-aware flows (UPF)\nExperience with Design revision control (GIT, DesignSync) and Make Splunk, Jenkins, LSF and CI/CD process\n\nMore information about NXP in India...\n\n#LI-29f4", "jd_status": "stored"}, {"title": "AI/ML driven ASIC Design and Implementation Principal Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-08-17", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/AI-ML-driven-ASIC-Design-and-Implementation-Lead-Engineer_R-10065113", "is_hardware": true, "platform": "workday", "jd_text": "As an “AI/ML driven ASIC Design and Implementation Lead Engineer”, you will work in a dynamic environment to explore methodology, flows and tools to improve efficiency and quality of results (power, performance, area, and verification) for SoC and IP development teams across the organization. You'll be working and connecting with AI/ML and automation experts in the industry to explore state-of-the-art AI/ML CAD techniques as a part of VLSI CAD SW, prescribe key methods and requirements for tools & features to leverage for ASIC design.\n \nIn this role, you will work & develop prototype solutions to evaluate various state-of-the-art AI/ML techniques to identify the best solutions in close collaboration with Architecture, IP design, SoC Design, Verification, Implementation and Design Enablement teams to drive new ways of working, improvements to current ways of working, addressing design quality challenges and continuously improve NXP Semiconductors design, verification and implementation flows. While developing these new ways of working, successful candidates will be working on actual designs and implementation to pilot and develop the automation.\n \nThis opportunity is to enable Digital Transformation to leverage state-of-the-art AI/ML ideas to improve NXP designs for the Edge-AI, Automotive Processors and Advanced microcontrollers in NXP.\nSuccessful candidate will be working in a fast-paced engineering environment, on a leading-edge advanced node technologies enabling automated building of exciting and complex SoCs.\n \nJob Summary\n \nExplore research ideas and solutions that bring AI/ML applications to VLSI design\nWork closely with Academic research communities in AI/ML for VLSI design, Architecture teams, IP and SoC designers and SoC Implementation teams from multiple sites to explore and evaluate for leading edge SoC technologies serving multiple industries\nThese automation applications include use of GenAI, Reinforcement Learning, Graph Neural Networks, and convolutional Networks\nStrong AI/ML expertise and software background required\n \nJob Qualifications\n \nBS or MS in Computer Science, Electrical Engineering, Computer Engineering or related disciplines with strong background in SW development\n10+ years of experience in developing complex SW projects, and hands-on expertise in programming using Python & C++\nHands on experience in Unix/Linux, revision control (Git, BitBucket), SW development and debug tools\nExcellent analytical problem solving skills\nStrong verbal and written communication skills\n \nDesirable skills/experience:\n \nData structures, algorithms and SW development for optimization problems.\nPrior experience in VLSI CAD methodology and tool development\nUnderstanding or prior experience with EDA tools for design, verification, DFT and implementation\nStrong understanding of design, layout, constraints (SDC, Clocks, CDC, RDC), Static timing analysis, Low-power and Power-aware flows (UPF)\nExperience with Design revision control (GIT, DesignSync) and Make Splunk, Jenkins, LSF and CI/CD process\n\nMore information about NXP in India...\n\n#LI-29f4", "jd_status": "stored"}, {"title": "Lead I/O Design Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-08-17", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Lead-I-O-Design-Engineer_R-10065863", "is_hardware": true, "platform": "workday", "jd_text": "Job Summary:\nWe are seeking an experienced IO Circuit Design Engineer with 5-8 years of expertise in designing and validating high-performance I/O circuits for advanced semiconductor SoCs. The role involves developing GPIO, LVDS, DDR, SerDes support circuits, ESD protection, level shifters, buffers, and termination circuits using advanced CMOS technologies. The candidate will be responsible for transistor-level design, signal integrity analysis, layout reviews, silicon bring-up, and cross-functional collaboration to deliver robust, production-ready IO IP solutions. Strong hands-on experience with Cadence Virtuoso, SPICE simulation, ESD methodologies, and high-speed interface standards is essential.\n\nKey Responsibilities\nDesign and develop custom IO circuits including:GPIO\nLVDS\nLVCMOS\nSSTL\nHSTL\nDDR Interfaces\nHigh-speed SerDes support circuits\n\nPerform transistor-level design and simulation using advanced CMOS technology nodes.\nDevelop and optimize:ESD protection circuits\nLevel shifters\nInput buffers\nOutput drivers\nOn-chip termination circuits\n\nConduct pre-layout and post-layout simulations for functionality, timing, power, noise, and reliability.\nPerform signal integrity analysis including:IBIS model generation\nPackage-aware simulations\nCrosstalk and reflection analysis\n\nDrive layout reviews and work closely with physical design teams to ensure design quality and performance targets.\nSupport silicon bring-up, characterization, debugging, and production ramp activities.\nCollaborate with system, package, reliability, and product engineering teams.\nDevelop and maintain design documentation, specifications, and verification reports.\n\nRequired Qualifications\nBachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, or related field.\n5-8 years of experience in Analog/Mixed-Signal or IO Circuit Design.\nStrong understanding of:CMOS device physics\nAnalog circuit design fundamentals\nIO architectures and standards\nESD design methodologies\n\nHands-on experience in custom circuit design using Cadence Virtuoso.\nExpertise in SPICE-based simulators such as Spectre, HSPICE, or FineSim.\nExperience with advanced technology nodes (16nm/7nm/5nm preferred).\nGood knowledge of LVS, DRC, EMIR, and reliability checks.\nFamiliarity with process corners, Monte Carlo analysis, and yield optimization techniques.\n\nPreferred Skills\nExperience with DDR4/DDR5, LPDDR, USB, PCIe, MIPI, or Ethernet interfaces.\nKnowledge of package modeling and SI/PI analysis tools.\nUnderstanding of ESD standards such as HBM, CDM, and IEC.\nExperience in silicon validation and lab characterization.\nScripting skills in Python, Perl, Tcl, or SKILL.\nFamiliarity with IBIS and IBIS-AMI model generation.\n\nDesired Competencies\nStrong analytical and debugging skills.\nExcellent communication and cross-functional collaboration.\nAbility to lead technical discussions and mentor junior engineers.\nProven track record of delivering silicon successfully from specification to production.\nSelf-driven with strong problem-solving abilities.\n\nNice to Have\nExperience in automotive, AI/ML, networking, mobile, or data center SoCs.\nExposure to functional safety and reliability requirements.\nPrior ownership of complete IO IP development cycle.\nThis role is ideal for an engineer who has hands-on experience in IO circuit design, ESD, signal integrity, and silicon validation, and is looking to contribute to next-generation semiconductor products.\n\nMore information about NXP in India...\n\n#LI-7013", "jd_status": "stored"}, {"title": "Staff Engineer - Memory Design", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-17", "url": "https://careers.synopsys.com/job/bengaluru/staff-engineer-memory-design/44408/99353319200", "is_hardware": true, "platform": "talentbrew", "jd_text": "Staff Memory Design EngineerWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in the analog and mixed-signal trenches, designing memory circuits that have to work across voltage corners, temperature extremes, and process variations without a second chance. You know that an SRAM bitcell is not just six transistors on a page, it is a tradeoff between read stability, write margin, leakage, and area, and you have made those calls enough times to know which knob to turn when a design is not closing.\nYou think in terms of transistor-level behavior, not just simulation results. When a memory fails at a corner, you do not just re-run SPICE, you go back to the schematic, check your layout parasitics, and figure out what actually broke. You have worked closely with layout teams, and you understand that a good floorplan saves you three weeks of iteration later.\nYou are comfortable owning a memory block from architecture through tapeout. You can sit with a compiler team and explain why your bitcell needs a specific routing constraint, then turn around and review a layout with a physical design engineer without losing context. At Synopsys, you will design embedded memories that ship in our IP portfolio and power chips across the industry.\nWhat You'll Be Doing\nDesign and develop embedded CMOS memories including single-port SRAM, dual-port SRAM, register files, and ROM for Synopsys IP products\nOwn circuit architecture and transistor-level implementation for ultra-high-speed, ultra-low-power, or high-density memory configurations\nPerform schematic entry, SPICE simulation, layout planning, and supervise physical layout execution through to final verification\nDevelop and verify bitcells, define layout rules, and drive layout design and parasitic extraction closure with the physical design team\nInterface with CAD teams to integrate memory designs into compiler automation flows and generate EDA models for customer use\nCollaborate with frontend engineers to define and validate full verification flows including timing, power, and functional models\nMentor junior engineers and lead technical aspects of memory design projects from concept to delivery\nThe Impact You Will Have\nYour memory designs will ship as part of Synopsys IP offerings used by semiconductor companies worldwide in high-volume production chips\nThe bitcells and architectures you develop will define performance, power, and area benchmarks for next-generation embedded memory IP\nYour layout planning and verification rigor will reduce tapeout risk and speed time to market for memory compiler releases\nThe automation flows you help define will enable faster, more reliable memory generation for customers across process nodes\nYour technical mentorship will build design capability within the team and raise the quality bar for future memory products\nThe tradeoffs you make between speed, power, and density will directly influence customer adoption and competitiveness in the IP market\nYour collaboration with CAD and frontend teams will improve tooling, models, and verification coverage across the memory IP portfolio\nWhat You'll Need\nBachelor's or Master's degree in Electrical Engineering, Electronics, or a related technical field\nDeep hands-on experience with CMOS memory circuit design including SRAM, register files, or ROM\nProficiency with circuit simulation tools such as HSPICE, Spectre, or similar SPICE-based simulators\nStrong understanding of memory layout design, parasitic extraction, and layout verification tools like Calibre or Assura\nScripting capability in C-Shell, Perl, or similar languages; experience with C++ or JavaScript is a plus\nDemonstrated ability to lead technical projects and mentor junior engineers through complex design challenges\nExperience working with memory compiler flows, EDA model generation, or design automation is a strong plus\nWho You Are\nYou can look at a bitcell schematic and immediately spot a read stability issue or a leakage path without running a full simulation\nYou know how to work with layout designers, not just hand off a schematic and hope for the best, you review floorplans, flag routing issues, and iterate together\nYou are comfortable making technical tradeoffs in ambiguity, choosing between a faster access time and lower leakage when the spec does not give you both\nYou can explain a circuit-level design decision to a compiler engineer or a product manager in terms they understand without oversimplifying the engineering\nYou stay organized across multiple design blocks, verification runs, and layout reviews without losing track of what is blocking tapeout\nYou take ownership, if a memory fails characterization, you do not wait for someone else to debug it, you dig in and figure out what went wrong\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Analog Design, Sr Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-17", "url": "https://careers.synopsys.com/job/bengaluru/analog-design-sr-staff-engineer/44408/95856495984", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\n\n Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You Are\n\n You have spent years in the trenches of analog design, working on circuits that move data at speeds most people cannot fathom. SerDes is not just a buzzword to you, it is the domain where you have built voltage-mode drivers, tuned PLLs until they locked cleanly, and debugged equalization schemes that looked perfect in simulation but needed three more iterations in layout. You know that a well-designed CDR is the difference between a link that works and one that fails margin at the customer site.\n\n You do not wait for a reference design to be handed to you. When you see a spec, you already start sketching topologies and thinking through tradeoffs between power, area, and performance. Layout is not something that happens after you finish the schematic, it is part of your design process from day one. A long metal run or poor device placement catches your eye in a floorplan review because you know exactly how it will show up in post-layout simulation.\n\n At Synopsys, you will work on SerDes IP that ships in AI accelerators, data center switches, automotive SoCs, and consumer electronics. The circuits you design will be measured in gigabits per second, and the decisions you make will matter in millions of devices.\n\nWhat You'll Be Doing\n\n * Design and optimize analog front-end building blocks for SerDes IP, including voltage and current-mode drivers, equalizers (CTLE, FFE, DFE), CDR circuits, PLLs, DLLs, VCOs, phase interpolators, bandgaps, and regulators\n * Run SPICE simulations across PVT corners and create verification test benches that validate performance against PCIe 6.0, PCIe 7.0, PAM4, Ethernet, USB, HDMI, or other high-speed protocol specifications\n * Collaborate closely with layout engineers to minimize parasitic resistance and capacitance, reduce mismatch, and account for proximity effects in sub-micron CMOS processes\n * Work with digital RTL engineers to verify calibration loops, adaptation algorithms, and control logic that tune your analog circuits in real time\n * Present simulation results, design tradeoffs, and performance data in peer reviews and customer-facing technical discussions\n * Document circuit architecture, design features, verification strategies, and test plans for integration into larger SerDes products\n * Own the full lifecycle of your blocks from spec to silicon, including post-layout verification, characterization support, and design-for-reliability checks for electromigration, IR drop, aging, and ESD\n\nThe Impact You Will Have\n\n * Your circuits will enable multi-gigabit data transfer in AI accelerators, data center switches, automotive SoCs, and consumer electronics shipping in millions of units\n * You will help Synopsys deliver SerDes IP that meets the performance and power targets our customers depend on to win in competitive markets\n * Your layout optimization and simulation rigor will reduce respins, saving months of schedule and significant engineering cost\n * The verification strategies you define will catch corner-case failures before tapeout, improving first-pass silicon success rates\n * Your collaboration with digital and system teams will ensure analog-digital co-design works seamlessly, not just in theory but in real integrated test chips\n * You will contribute to the technical foundation of next-generation high-speed standards, influencing how the industry builds faster, more efficient links\n * Your documentation and knowledge sharing will raise the design quality and speed of the entire analog team\n\nWhat You'll Need\n\n * PhD with 2+ years of hands-on SerDes or high-speed analog design experience, or BTech/MTech with 5 to 10 years in the same domain\n * Silicon-proven experience designing and bringing up analog or mixed-signal blocks in production chips, you have seen your circuits work in real silicon\n * Deep expertise in at least several of these building blocks: analog front-end transceivers, voltage/current-mode drivers, PLLs, DLLs, VCOs, CDR circuits, bandgaps, regulators, CTLE, FFE, DFE, impedance calibrators, serializers, deserializers, or phase interpolators\n * Strong proficiency with SPICE simulation tools and sub-micron CMOS design methodologies, you know how to set up corners, sweep parameters, and interpret results that matter\n * Experience optimizing layout for performance, including parasitic extraction, device matching, stress effects, and design-for-reliability considerations like electromigration, IR drop, and aging\n * Familiarity with scripting languages such as TCL or Perl for automation and simulation flow setup is a strong plus\n * Working knowledge of high-speed serial standards like PAM4, PCIe 6.0, PCIe 7.0, Ethernet, USB, SATA, HDMI, or MIPI is highly valued\n\nWho You Are\n\n * You can take a specification document and translate it into a circuit architecture without waiting for someone to hand you a reference design\n * You catch layout issues early, you review floorplans and flag where a long metal run or poor device placement will degrade performance before it becomes a post-layout surprise\n * You are comfortable presenting technical data to peers and customers, you can walk someone through a Bode plot or an eye diagram and explain what it means for margin and yield\n * You push back when a requirement does not make sense or when a verification plan has gaps, you care about getting it right more than checking a box\n * You work well across teams, coordinating with digital designers on control loops, with layout on physical implementation, and with characterization engineers on test plans\n * You stay current on process technology and circuit techniques, not because it is trendy but because it helps you design better blocks\n\nThe Team You'll Be Part Of\n\n Your recruiter will share more about the team structure and mission during the interview process.\n\nRewards and Benefits\n\n We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "R&D Engineering, Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-17", "url": "https://careers.synopsys.com/job/bengaluru/r-and-d-engineering-staff-engineer/44408/99353319136", "is_hardware": true, "platform": "talentbrew", "jd_text": "Alternate Job Titles\nMemory Circuit Design Engineer\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent the last few years deep in memory circuit design, the kind of work where a 10mV margin shift can mean the difference between a product that ships and one that doesn't. You understand CMOS fundamentals not as theory but as something you use every day to explain why a bitcell behaves the way it does under corner conditions. You have run enough SPICE simulations to know when a result smells wrong before you even look at the waveform.\nYou are comfortable sitting with a characterization dataset, spotting the outlier, and tracing it back to a setup issue or a real circuit behavior that matters. Working across time zones doesn't faze you. You ask questions when something is unclear, you share what you learn, and you don't wait for perfect documentation to move forward. You want to build memory IP that works, not just in simulation but in silicon, and you care about the details that make that happen.\nWhat You'll Be Doing\nDesign and optimize memory circuits including SRAM bitcells, sense amplifiers, decoders, and peripheral blocks for advanced process nodes\nRun SPICE simulations using tools like HSPICE or Spectre to validate circuit performance across PVT corners and operating conditions\nPerform margin analysis and characterization to ensure robustness of memory designs under voltage, temperature, and process variation\nDebug circuit-level issues by analyzing simulation results, identifying failure modes, and proposing design fixes\nCollaborate with verification, layout, and product teams across Bengaluru and global sites to close design and characterization loops\nDocument design decisions, characterization results, and analysis flows for use by the broader memory IP team\nSupport silicon bring-up and post-silicon debug by correlating measured data with simulation predictions\nThe Impact You Will Have\nYour circuit designs will directly enable memory compilers used in SoCs across automotive, mobile, and AI applications\nThe margin analysis you perform will determine whether a memory IP meets yield and reliability targets in production silicon\nYour characterization flows will become the foundation for how the team validates new memory architectures\nThe bugs you catch in simulation will save months of silicon respins and customer escalations\nYour collaboration across sites will accelerate design closure and reduce iteration cycles on critical IP deliverables\nThe documentation you create will help onboard new engineers and scale the team's design capacity\nYour work will contribute to memory IP that ships in millions of devices worldwide\nWhat You'll Need\nBTech or MTech in Electronics Engineering, VLSI Engineering, or equivalent from a recognized institution\n4 to 6 years of hands-on experience in memory circuit design, characterization, or verification\nStrong understanding of SRAM, register file, or embedded memory architectures and circuit topologies\nProficiency in SPICE simulation tools such as HSPICE, Spectre, or similar for circuit analysis and debug\nSolid foundation in CMOS fundamentals, device physics, and digital circuit design principles\nExperience with margin analysis, Monte Carlo simulation, or statistical characterization methods is a strong plus\nFamiliarity with scripting languages like Python, Perl, or TCL for automating simulation and analysis flows is helpful\nWho You Are\nYou can look at a SPICE deck, spot a setup error, and fix it without needing someone to walk you through it\nYou communicate clearly in written and verbal form, whether you are explaining a circuit tradeoff to a peer or summarizing characterization results in a review\nYou work well with distributed teams and are comfortable coordinating across time zones without losing momentum\nYou are motivated by learning, whether that means understanding a new process node or digging into a failure mode you have not seen before\nYou do not get stuck when documentation is thin or requirements are evolving, you ask the right questions and keep moving\nYou take ownership of your work, from simulation setup through final characterization sign-off\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "R&D Engineer, Sr Engineer (C/C++, Data structures, Algorithm, FPGA)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-17", "url": "https://careers.synopsys.com/job/bengaluru/r-and-d-engineer-sr-engineer-c-c-data-structures-algorithm-fpga/44408/92439874704", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nYou are a passionate and driven engineering professional with a deep curiosity about how things work and a relentless desire to solve complex problems. You thrive in a collaborative environment, working alongside talented peers to deliver robust, high-performance solutions that make a tangible impact. You bring a strong foundation in computer science or electrical engineering, coupled with hands-on experience in developing and maintaining large-scale EDA software. Your expertise in C/C++, data structures, and graph algorithms is complemented by your understanding of digital logic design and hardware description languages. You are proactive, detail-oriented, and eager to continuously learn new technologies and methodologies. Whether you’re designing innovative algorithms or troubleshooting intricate system issues, you approach every challenge with analytical rigor and creativity. You are committed to quality, enjoy working with cross-functional teams, and are motivated by the opportunity to influence the future of chip design and prototyping. If you value diversity, inclusion, and believe in the power of technology to change the world, Synopsys is the place where your ambitions can thrive.\nWhat You’ll Be Doing:\nDesigning, developing, troubleshooting, debugging, and maintaining large-scale, efficient software systems for the HAPS® ProtoCompiler partition flow.\nImplementing and optimizing advanced data structures and algorithms in C/C++ to meet challenging performance and scalability requirements.\nCollaborating with product validation (PV) teams to plan, execute, and automate comprehensive testing strategies.\nWorking on logic optimization, clock inference, and marking, as well as preparing designs for partitioning and estimating area and other critical design metrics.\nMaintaining and supporting existing features and products, ensuring robustness and quality across releases.\nEngaging with digital logic design, and applying your knowledge of Verilog/VHDL at the RTL level to enhance hardware/software co-design workflows.\nParticipating in code reviews, design discussions, and knowledge-sharing sessions within the team and broader engineering organization.\nThe Impact You Will Have:\nAccelerate time-to-market for cutting-edge silicon designs by enabling early embedded software development and hardware/software co-design.\nHelp customers avoid costly device re-spins through robust prototyping solutions that support rapid iteration and validation.\nDrive improvements in software quality, performance, and reliability for ProtoCompiler and HAPS solutions.\nSupport the creation of innovative verification and validation methodologies for processor subsystems and full SoC designs.\nContribute to the evolution of Synopsys’ industry-leading EDA tools, shaping future product capabilities and features.\nEmpower teams across the globe to build high-performance, energy-efficient chips for applications ranging from AI and automotive to IoT and beyond.\nWhat You’ll Need:\nB.Tech/M.Tech in Computer Science or Electrical Engineering from a reputed institute.\n2+ years of experience designing, developing, and maintaining large-scale EDA or system software solutions.\nStrong programming skills in C and C++ across Windows and Unix platforms.\nSolid understanding of data structures, graph algorithms, and software optimization techniques.\nFamiliarity with digital logic design, Verilog/VHDL at RTL level, and logic optimization concepts.\nExperience with FPGA design tools and flows is a plus.\nWho You Are:\nInnovative thinker with a passion for technology and problem-solving.\nEffective communicator, comfortable working in cross-functional and global teams.\nAnalytical, detail-oriented, and committed to delivering high-quality results.\nAdaptable and open to learning new tools, methodologies, and technologies.\nCollaborative team player who values diversity and inclusion.\nResilient, proactive, and able to thrive in a fast-paced, dynamic environment.\nThe Team You’ll Be A Part Of:\nYou will join the ProtoCompiler R&D team in Bangalore, a group of talented engineers dedicated to developing world-class partitioning flows for the Synopsys HAPS® Prototyping Solution. Our team thrives on innovation, collaboration, and technical excellence, working closely with global engineering, validation, and product management groups to deliver industry-leading tools that power the next generation of silicon design.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\n#TPG", "jd_status": "stored"}, {"title": "Verification Engineer - Media IP", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-17", "url": "https://careers.arm.com/job/bengaluru/verification-engineer-media-ip/33099/94742302528", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview\n \nThis position is an excellent opportunity for an experienced and highly motivated verification engineer to join the Arm Systems Media IP team! The team is responsible for the development of Image Signal Processors (ISPs), Display Processors, and Video codecs for deploying within Arm Compute Subsystems for various end markets, including automotive, IoT, and client market segments. Our intellectual property encompasses RTL, reference drivers, tools, and libraries, enabling our customers to build upon our work to create innovative products!\n \nYou will specify and develop new hardware verification testbenches for future generation hardware IP. You will improve existing testbenches to increase performance, quality and efficiency. You will also identify areas for improvement in processes and methodologies, then implement those changes to advance our best-practices for hardware verification. This is a new team with plenty of opportunities to shape its future, and your own growth and career progression.\nResponsibilities\nDepending on prior experience, the responsibilities of the role can include:\nVerification ownership of unit level or multi-unit hierarchy or alternatively verification lead of an overall IP (ISP, Display, Video).\nArchitecting verification IP and full verification environments.\nReviewing and assessing proposed design changes from a verification complexity point of view.\nAnalysis of data from simulation runs using machine learning and data science techniques to drive efficient bug discovery and debug.\nIdentify cross Media IP process or methodology improvement opportunities, implementing changes to advance hardware verification efficiency.\nClose collaboration with other Arm engineering teams leading to high quality IP that works well in a complete system.\nMentor & support other members of the team.\nRequired skills and experience:\n6+ years of experience in working with constrained-random verification including ownership of a suitably complex verification environment and creating testbenches.\nExperience developing reusable and scalable code whilst having in-depth knowledge of SV-UVM.\nStrong scripting skills – being able to develop scripts to support new and existing flows.\nSolid software engineering skills including understanding of object-oriented programming, data structures, and algorithms.\nFamiliar with the tools and processes for developing testbenches and finishing all aspects of the verification process.\nPrior technical and/or team leadership skills required for more senior positions.\n'Nice to Have' skills and Experience:\nTeam leadership and mentoring experience.\nMultiprocessing microarchitecture experience including knowledge of bus protocols (e.g. AMBA APB/AHB/AXI).\nPast experience in Formal Verification testbenches.\nExperience in video codec, ISP, or display projects, including knowledge of advanced image processing algorithms, such as local tone mapping, noise reduction, motion estimation, transform coding, etc.\nExperience of Functional Safety product development for the Automotive market (applying standards such as ISO 26262 and/or IEC 61508).\nExperience with Continuous Integration flows.\nIn Return:\nYou will get to utilise your engineering skills to build support for the technologies and influence millions of devices for years to come. You will be able to drive and bring your ideas to a wider audience, while building your technical leadership and influencing skills.\nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\n \n \n#LI-SA3\nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Memory Layout Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-08-17", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Memory-Layout-Design-Engineer_R026842", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nJob Requirements:\n  - Minimum 3 years of experience with strong layout knowledge.\n  - Bachelor's degree required.\n  - Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - CALIBRE & Hercules).\n  - Strong layout knowledge in submicron processes (e.g., A14, 2nm, 3nm, 5nm, 7nm).\n  - Experience in digital layout (Standard cell, Memory, I/O); analog layout experience is a plus.\n\nJob Description:\n  - Understand and apply layout guidelines, new process rules, and technical requirements for good quality layout.\n  - Manage scheduling, timelines, and layout floor-planning.\n  - Responsible for start-to-end deliverables with quality within the planned schedule.\n  - Adapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the SOC/library team.\n\nSkill Set (Memory):\n  - Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes.\n  - Experience with Cadence Layout tools (VIRTUOSO XL, VXL, or EXL) and CALIBRE verification tools.\n  - Proficiency in floor-planning, hierarchy layout, and chip integration.\n  - Understanding of memory architecture, RC requirements, and the ability to plan signal and power based on layout guidelines.\n  - Knowledge of AI, automation in layout, Script Programming, and SKILL Programming is a plus.\n  - Ability to lead, train junior engineers, and manage projects effectively.\n  - Good knowledge of memory layout topology; experience with memory compilers is a plus.\n  - Ability to lead new technology reviews to document layout methodologies, flows, and guidelines.\n  - Self-reliant with the ability to work both independently and collaboratively.\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Memory Layout Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-08-17", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Memory-Layout-Design-Engineer_R026849", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nJob Requirements:\n- Minimum 3 years of experience with strong layout knowledge\n- Bachelor's degree required.\n- Proficiency in using Cadence tools (virtuotso layout, layotu XL, Cadence schematic capture, and verification tools - CALIBRE & Hercules).\n- Strong layout knowledge in submicron processes (e.g. 7nm, 5nm, 3nm, 2nm).\n- Experience in digital layout (Standard cell, Memory, I/O); analog layout experience is a plus.\n\nJob Description:\n- Understand and apply layout guidelines, new process rules, and technical requirements for good quality layout.\n- Manage scheduling, timelines, and layout floor-planning.\n- Responsible for start to end deliverables with quality within the planned schedule.\n- Adapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the SOC/library team.\n\nSkill Set (Memory):\n- Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes.\n- Experience with Cadence Layout tools (VIRTUOSO XL, VXL, or EXL) and CALIBRE verification tools.\n- Proficiency in floor-planning, hierarchy layout, and chip integration.\n- Understanding of memory architecture, RC requirement, ability to plan signal and power, based on the layout guidelines\n- Knowledge of AI, automation in layout, Script Programming and SKILL Programming is a plus.\n- Ability to lead, train junior engineers, and manage projects effectively.\n- Good knowledge of memory layout topology; experience with memory compilers is a plus.\n- Ability to lead new technology reviews to document layout methodologies, flows, and guidelines.\n- Self-reliant with the ability to work both independently and collaboratively.\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "ASIC VERIFICATION ENGINEER", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-08-16", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/ASIC-VERIFICATION-ENGINEER_R026799-6", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nJob Description\n\nWhat You can Expect -\n- Work on Latest cutting edge CSG Switches.\n- To be part of the team working on defining many Firsts for the AI Network Infrastructure Ecosystem.\n- Develop and maintain verification Environment in Mix of SV/UVM.\n- Understanding of the End to End spec along with Network & System topology.\n- Closely working with Arch/uArch/Design team for Test Plan development and closure of the feature set across Blocks/Top level.\n- Coverage Closures, Gate Level Simulations along with end to end verification cycle.\n\nWhat we are looking for -\n- Bachelor's/Masters/PhD with Verification experience of 8+ years\n- Wide exposure to chip level (SoC) verification and SystemVerilog/UVM methodology a MUST\n- Exposure to any one of the scripting languages - Perl or Python or SED/Awk\n- Expertise in Co-Simulations (HW/SW) Flow and debugs\n- Knowledge of networking protocols(L2/L3/L4, 1588TS, UEC) desired but not necessary.\n- Expertise in the High Speed bus protocols desired - PCIe, Ethernet, AXI4.0 \n- Exposure the Chip level Interconnect/Testability Functions - JTAG, I2C, PLLs etc\n- Experience in GLS, Coverage Driven Methodology, ATE\n- Good exposure in Simulation tool usage for simulation (VCS) and waveform debug(Verdi) and formal tools like Jasper.\n- Exposure to Test Bench Accelerators /Emulation Platforms.\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Principal Engineer Design", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-08-15T07:59:02+00:00", "url": "https://jobs.infineon.com/careers/job/563808971837074", "is_hardware": true, "platform": "eightfold", "jd_text": "We are seeking a highly motivated Principal Engineer Design to lead the physical implementation and timing closure of advanced low-power SoCs targeting the IoT and MCU markets. This role offers the opportunity to drive end-to-end physical design execution, optimize power, performance, and area (PPA), and influence methodology improvements that enable successful silicon delivery.\n\nThe ideal candidate will possess deep expertise in physical design, timing convergence, low-power implementation methodologies, and signoff processes while demonstrating strong technical leadership and cross-functional collaboration skills.\n\nYour role\nKey responsibilities in your new role\n\nLead physical design and timing closure for complex low-power SoCs targeting IoT and MCU applications.\nManage end-to-end physical implementation from floor planning to final signoff while meeting Power, Performance, and Area (PPA) objectives.\nDrive and optimize die area, timing, power, and performance for both hierarchical block-level and full-chip designs.\nOwn critical physical design activities, including package co-design, floor planning, power planning, power grid design, place-and-route (P&R), clock tree synthesis (CTS), timing closure, and physical signoff.\nEnsure successful timing convergence across multiple operating modes and process, voltage, and temperature (PVT) corners.\nPerform and oversee physical verification, signoff validation, and design readiness reviews.\nCollaborate closely with Architecture, RTL Design, DFT, Verification, Packaging, Product Engineering, Foundry, and other cross-functional teams to resolve implementation challenges.\nDrive improvements in EDA tools, design methodologies, automation, and implementation flows to enhance Quality of Results (QoR), productivity, and design efficiency.\nProvide technical leadership in defining physical implementation strategies, risk mitigation plans, and signoff methodologies.\nMentor and guide engineers, promote technical excellence, and drive adoption of industry best practices across the organization.\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Computer Engineering, or a related discipline.\n12+ years of hands-on experience in Physical Design and Timing Closure for complex SoC products.\nProven success in driving chip implementation from floor planning through tape out and silicon delivery.\nStrong understanding of advanced semiconductor process technologies and associated physical design challenges.\nExperience delivering low-power SoCs for IoT, MCU, consumer, mobile, automotive, or related applications.\nTechnical Skills & Expertise\nDeep expertise in hierarchical SoC physical design, implementation, and timing convergence.\nStrong proficiency with industry-standard Physical Design, Signoff, and EDA automation tools.\nHands-on experience in:Floor planning and physical partitioning\nPower planning and power grid design\nPlace and Route (P&R)\nClock Tree Synthesis (CTS)\nStatic Timing Analysis (STA)\nMulti-mode, multi-corner (MMMC) timing closure\nPhysical verification and signoff\nEM/IR and power integrity analysis\n\nIn-depth knowledge of low-power design methodologies and implementation techniques.\nStrong understanding of process technology trade-offs affecting Power, Performance, and Area (PPA).\nAbility to analyze and solve complex implementation challenges through data-driven decision-making and technical collaboration.\nLeadership & Collaboration\nDrive technical decisions and take ownership of implementation quality, schedule, and deliverables.\nCollaborate effectively with cross-functional teams across Architecture, RTL, Verification, DFT, Packaging, and Foundry organizations.\nLead technical discussions, design reviews, and implementation strategy planning.\nMentor and develop junior engineers while fostering a culture of technical excellence.\nPromote knowledge sharing, best practices, and continuous learning across teams.\nChampion innovation in methodologies, design flows, automation, and tool usage.\nDemonstrate strong communication, stakeholder management, and problem-solving capabilities.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nKeerthini M H", "jd_status": "stored"}, {"title": "Senior Staff Engineer Design ", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-08-15T07:36:09+00:00", "url": "https://jobs.infineon.com/careers/job/563808971837077", "is_hardware": true, "platform": "eightfold", "jd_text": "We are seeking an experienced Senior Staff Engineer with 8+ years of expertise in SoC architecture, microarchitecture development, RTL design, low-power methodologies, and post-silicon debug. The candidate will drive end-to-end SoC design activities, collaborate with cross-functional teams, and provide technical leadership to ensure successful silicon development and product delivery.\n\nYour role\nKey responsibilities in your new role\n\nDefine and develop SoC architecture and microarchitecture for complex semiconductor products.\nDesign and implement RTL using Verilog/System Verilog.\nArchitect and optimize low-power solutions utilizing UPF methodologies.\nDevelop and review clock, reset, power, DMA, and interconnect architectures.\nPerform and analyze CDC (Clock Domain Crossing), Lint, CLP (Convergence Low Power), and PTPX power analysis.\nEnsure compliance with AMBA protocols and industry-standard design practices.\nCollaborate closely with Verification, Software, Validation, DFT, Physical Design, PSVP, and System teams throughout the product lifecycle.\nLead silicon bring-up, post-silicon validation, debugging, and root-cause analysis.\nDrive design reviews, architecture reviews, and technical decision-making.\nMentor junior engineers and provide technical guidance across the design team.\nSupport implementation teams in achieving performance, power, and area (PPA) targets.\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.\n8+ years of hands-on experience in SoC Architecture, Microarchitecture, RTL Design, and SoC Development using Verilog/SystemVerilog.\nStrong expertise in SoC Architecture & Microarchitecture, including clock, reset, power, DMA, and interconnect architecture.\nDeep understanding of AMBA protocols (AXI, AHB, APB) and complex SoC integration.\nProven experience in Low-Power Design Methodologies, including UPF, CLP, power intent definition, and low-power architecture implementation.\nProficiency in CDC, Lint, CLP, and Prime Time PX (PTPX) Power Analysis with strong design quality and signoff understanding.\nExtensive experience in RTL Design, Debug, Silicon Bring-up, Post-Silicon Validation, and Root Cause Analysis.\nKnowledge of DFT methodologies, physical design constraints, and performance, power, and area (PPA) optimization techniques.\nExposure to Emulation, FPGA Prototyping, Pre-Silicon Validation Platforms (PSVP), and system-level validation environments.\nStrong understanding of Design Review, Quality Assurance, and Design Verification processes.\nDemonstrated ability to collaborate effectively with cross-functional teams including Verification, Software, Validation, DFT, Physical Design, and System Engineering.\nProven Technical Leadership and Project Execution experience, including mentoring junior engineers, driving architecture and design reviews, and leading complex SoC development programs.\nExcellent analytical, problem-solving, communication, and stakeholder management skills\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nKeerthini M H", "jd_status": "stored"}, {"title": "Senior Principal Engineer, Physical Design Engineering", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-08-15", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Senior-Principal-Engineer--Physical-Design-Engineering_R264577", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nAbout the Role:\n\nAs an SoC Chip Lead, you will lead SoC execution from spec to silicon across domains. You will be responsible to drive technical strategy and execution for complex SoCs and digital systems, drive product and technology roadmaps, architecture for mission-critical projects and serve as a technical authority within the organization. This position requires exceptional expertise across multiple domains and the ability to influence business direction while delivering on the product actualization.\n\nKey Responsibilities:\n\nTechnical Strategy & Architecture\nDrive Product Strategy: Define long-term product and technology roadmaps for complex SoCs and systems.\n\nSelect IP & Nodes: Lead technical IP assessments, vendor selection, and foundry technology node evaluations.\n\nDefine Architecture: Author and drive top-level SoC definitions alongside business and architecture teams, including fabric interconnects (NoC), memory hierarchies, power management, and micro-architecture.\n\nSilicon Execution & Sign-off\nOwn the Lifecycle: Lead SoC execution from initial concept through definition, tape-out, and final productization.\n\nOptimize PPA: Ensure all silicon milestones meet strict Power, Performance, Area, and Cost (PPA) requirements.\n\nGovern Silicon Sign-off: Drive final sign-off reviews for synthesis, DFT, constraints, timing closure, and physical design tape-out.\n\nCross-Functional Leadership & Collaboration\nUnify Engineering Domains: Direct and collaborate closely with all core hardware engineering functions, including Design (RTL), Verification (DV), DFT, Physical Design (PD), Power, and Silicon Validation (SiVal).\n\nBridge Hardware and Software: Partner with software, systems, manufacturing, and program management to guarantee high-quality, first-time-right silicon success.\n\nManage Stakeholders: Lead executive decision-making, mitigate program risks, and manage communications across business units, product marketing, and customers.\n\nMust Have Skills:\n\nTechnical Strategy: Visionary capability to define and drive technical strategy for digital design\n\nInnovation Leadership: Exceptional ability to drive innovation in digital design approaches and solutions\n\nSoC Architecture: Authority in complex SoC architecture design and implementation\n\nMulti-Domain Expertise: Comprehensive mastery across multiple technical domains\n\nBusiness Acumen: Strong understanding of business context and ability to align technical strategy with business goals\n\nIndustry Thought Leadership: Recognized expertise with ability to influence industry direction\n\nPreferred Education and Experience:\n\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent experience\n15+ years of relevant experience in semiconductors design roles\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Senior Staff Engineer Verification", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-08-14T08:27:33+00:00", "url": "https://jobs.infineon.com/careers/job/563808971791763", "is_hardware": true, "platform": "eightfold", "jd_text": "Drive cutting-edge silicon innovation by building\nvalidation frameworks, automating test solutions, and collaborating across\nteams to bring next-generation semiconductor products from FPGA to silicon.\n\nYour role\nKey responsibilities in your new role\n\nInterfacing with the silicon validation, char teams to understand the requirements.  \nDevelop and build test list, automation suite including software and firmware for the silicon.  \nValidation on FPGA (pre-silicon) and Silicon, working with the cross functional teams for debugging \nPython/LabVIEW based bench test equipment automation to support silicon Val and Char testing. \nManage schedules and liaison with cross functional teams, when associated as a program manager. \n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor's/Master's degree in Electronics, Computer Science, or related field of study. \n5-8 years of experience and understanding of microcontroller and SoC products.  \nExperience in Bench Characterization with Analog, Digital, and Mixed signal IPs.  \nHands-on experience in using lab equipment such as SMUs, DMM Oscilloscopes and signal generators. \nGood understanding of C ,Python, LabVIEW language. LabVIEW knowledge will be a great plus.  \nGood knowledge about regulators and reference measurements.  \nExcellent communication and interpersonal skills \n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Senior Staff Engineer Analog Mixed Signal Design", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-08-14T06:22:41+00:00", "url": "https://jobs.infineon.com/careers/job/563808971836304", "is_hardware": true, "platform": "eightfold", "jd_text": "The selected candidate will provide technical leadership in the architecture, design, development, and delivery of complex analog and mixed-signal IPs. The role requires strong expertise in power management solutions, excellent stakeholder management skills, and the ability to drive IP development from specification through silicon validation.\n\nYour role\nKey responsibilities in your new role\n\nLead the design and development of analog and mixed-signal IPs, ensuring high-quality execution and timely delivery.\nDrive architecture definition, circuit design, verification, and silicon bring-up activities for medium-complexity mixed-signal IPs.\nProvide technical leadership and mentorship to design teams, guiding implementation strategies and resolving critical design challenges.\nCollaborate with cross-functional teams including digital design, verification, layout, product engineering, and system architects.\n\nYour profile\nQualifications and skills to help you succeed \n\nStrong expertise in analog IC design with proven technical leadership capabilities.\nExtensive experience in Power Management Unit (PMU) design and development, including low-power architectures and power sequencing functions.\nHands-on experience in Switch-Mode Power Converter (SMPS/DC-DC Converter) design and implementation.\nDemonstrated ability to independently drive medium-complexity mixed-signal IP development from concept to production.\nStrong understanding of analog design fundamentals, including amplifiers, references, regulators, bias circuits, and feedback control systems.\nExcellent problem-solving, technical communication, and stakeholder management skills.\nAbility to lead design reviews, influence technical decisions, and coordinate across global teams.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nVidhi Thakkar", "jd_status": "stored"}, {"title": "Lead Board Design Engineer (X86 processors)", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-08-14T05:54:00+00:00", "url": "https://global-external-amd.icims.com/jobs/89068/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. Join AMD as an Hardware Development Engineer within the AECG-FPD-BOARD-BLR (Board Design team, AMD). In this role, you will lead the development and delivery of next-generation embedded computing system boards from concept through production. You will work closely with silicon architects, platform engineers, ODM partners, validation teams, firmware teams, and manufacturing organizations to ensure successful execution of complex embedded hardware programs. You will be responsible for driving board architecture reviews, schematic and layout oversight, design validation, system integration, and debugging of high-performance embedded platforms utilizing AMD processors, FPGAs, ASICs, and advanced embedded technologies. The role requires balancing technical excellence, schedule execution, quality, manufacturability, and cost objectives while working across global cross-functional teams. AMD's platform engineering organization develops world-class embedded and AI infrastructure solutions enabling industrial, networking, edge computing, telecommunications, aerospace, automotive, and intelligent infrastructure applications. We collaborate across engineering, manufacturing, and supply-chain organizations to deliver innovative embedded platforms that power the next generation of connected and intelligent systems. KEY RESPONSIBILITIES Lead hardware development and technical execution of AMD embedded platform programs. Drive schematic reviews, board architecture reviews, and design signoff activities. Collaborate with different teams on schematic capture, PCB design, manufacturing readiness, and product delivery. Define and review high-speed PCB layout guidelines for DDR, PCIe, Ethernet, USB, storage, management interfaces, and power delivery networks. Provide technical leadership during board bring-up, validation, root-cause analysis, and issue resolution. Review and approve component selection, BOM, risk assessments, and design changes. Partner with SI/PI engineers to ensure signal integrity, power integrity, and timing requirements are met. Work with firmware, software, validation, and manufacturing teams to ensure successful platform integration. Drive DFM, DFT, reliability, compliance, safety, and quality requirements throughout the product lifecycle. Manage technical interactions with suppliers and external partners to support schedule, quality, and cost objectives. Mentor engineers and contribute to hardware design best practices across the organization. PREFERRED EXPERIENCE 13+ yrs of experience in server, networking, industrial control, telecommunications, edge computing, aerospace, automotive, or enterprise hardware development. Bachelor's or Master's Degree in Electrical/Electronics Engineering. Strong knowledge of processor architectures, DDR memory subsystems, PCIe, Ethernet, USB, storage interfaces, and embedded power architectures. Expertise in high-layer-count PCB design and high-speed routing methodologies. Strong schematic review and board-level debugging skills. Experience with SI/PI analysis and interpretation of simulation results. Deep understanding of embedded board bring-up, validation, reliability testing, and failure analysis. Experience working with ODM/JDM design partners and contract manufacturers. Knowledge of safety, regulatory compliance, reliability, and manufacturing requirements. Strong project leadership, technical communication, and stakeholder management skills. #LI-SR4 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Staff Engineer Design", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-08-14T05:49:48+00:00", "url": "https://jobs.infineon.com/careers/job/563808971836305", "is_hardware": true, "platform": "eightfold", "jd_text": "The selected candidate will play a critical role in the architecture, design, verification, and implementation of RTL solutions for mixed-signal subsystems and standalone IPs. The role involves developing robust digital designs that interface with complex analog and mixed-signal circuits while ensuring power, performance, and area (PPA) targets are achieved.\n\nYour role\nKey responsibilities in your new role\n\nDefine, develop, verify, and implement RTL designs for mixed-signal subsystems and standalone IPs from concept through silicon realization.\n\nCollaborate closely with analog, verification, and physical design teams to deliver high-quality mixed-signal solutions.\nArchitect and implement digital control logic for complex mixed-signal IPs, ensuring seamless integration and functionality.\n\nYour profile\nQualifications and skills to help you succeed \n\nStrong expertise in RTL design and development for mixed-signal IPs such as PLLs, ADCs, SerDes, PMUs, and complex signal-chain architectures.\nHands-on experience in designing and implementing Finite State Machines (FSMs) and digital control logic for Power Management Units (PMUs) and related low-power applications.\nProficiency in developing and maintaining synthesis constraints (SDC), timing constraints, and implementing coverage-driven design methodologies.\nStrong understanding and practical experience in low-power design techniques, including creation and maintenance of UPF (Unified Power Format) for designs spanning multiple power domains.\nExperience with RTL coding in Verilog/System Verilog, linting, CDC/RDC analysis, synthesis, and timing closure methodologies.\nGood understanding of mixed-signal design flows and digital-analog interface requirements.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nVidhi Thakkar", "jd_status": "stored"}, {"title": "Layout Engineer, DPG IP DEV Layout", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-08-14T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/43750808", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nJob Description\n For more than 45 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.\n   We are looking for Layout Design engineer at our Micron Technology’s DPG-IPDEV Team in Bangalore, India.  DPG-IPDEV team is responsible for developing world-class analog and mixed signal IPs used in every modern DRAM chip produced in Micron. As a Layout Design engineer, you will be working for intensive applications such as artificial intelligence and high-performance computing solution, High Bandwidth Memory. As a Layout Design Engineer you will be collaborating with peer teams crossing Micron global footprint, in a multiple projects-based environment.\n \n \nRole and Responsibilities\n \n•        Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support.\n•        Perform layout verification like LVS/DRC/Antenna, quality check and support documentation.\n•        Responsible for on-time delivery of block-level layouts with acceptable quality.\n•        Demonstrate leadership qualities in planning, area/time estimation, scheduling, and execution to meet project schedule/milestones in multiple project environment.\n•        Contribute to effective project-management.\n•        Effectively communicating with Global engineering teams to assure the success of layout project.\n \nQualification/Requirements\n•        3 to 5 years' experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET )\n•        Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.\n•        Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,\n•        Good understanding of Analog Layout fundamentals (e.cg., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive static device parasitics etc.)\n•        Understanding layout effects on the circuit such as speed, capacitance, power and area etc.\n•        Ability to understand design constraints and implement high-quality layouts\n•        Ability to understand design hierarchy and different architectures for Memory designs.\n•        Excellent problem-solving skills in physical verification of custom layout.\n•        Multiple Tape out support experience will be an added advantage.\n•        Excellent verbal and written communication skills.\nShould be proactive in exploring AI-related tools in day-to-day tasks.\n \nEducation\n \nBE or MTech in Electronic/VLSI Engineering\n \nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "SOC Verification Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-14", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/SOC-Verification-Engineer_JR2023239", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to seek, which only we can pursue, and which matter to the world. This is our life’s work: to amplify human inventiveness and intelligence. NVIDIA is now driving innovation at the intersection of visual processing, high-performance computing, and artificial intelligence.\n\nWe are currently seeking an expert Verification Engineer with strong verification fundamentals to work in NVIDIA's SOC verification team.\n\nWhat you’ll be doing:\nWork on NVIDIA's next generation SOC\n\nVerify CPU, GPU, high speed interfaces, Design for Debug (DFD) and horizontal functions like Boot and Power management at subsystem or full chip testbenches including FPGA/Silicon\n\nDevelop and implement testplans collaborating with SOC architects\n\nWork on developing verification testbenches, flows and automation, explore and implement new methodologies to support verification of groundbreaking architecture\n\nWhat we need to see:\nExperience with full stack development - from verifying scenarios at SW simulator level, to getting the overall end-to-end test working on silicon with a full sw stack.\n\nStrong verification fundamentals and able to juggle working on SW simulators, full chip testbenches and on FPGA/Silicon\n\nExperience with Verilog, SystemVerilog, C/C++ and possess strong debugging skills\n\nExperience in creating test benches grounds up, build flows, verification infrastructure\n\nBachelors/Masters, or equivalent experience, in Computer Science or electrical engineering with 3+ years of industry experience\n\nWays to stand out from the crowd:\nExperience with doing complex verification projects at subsystem and/or SOC integration levels\n\nKnowledge of SOC integration and verification methodologies\n\nExperience of collaborating with geographically diverse multi-functional teams\n\nWith competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us and, due to unprecedented growth, our elite engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you.\n\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.", "jd_status": "stored"}, {"title": "Senior Verification Engineer -  ARM Fabric Unit Level", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-14", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer----ARM-Fabric-Unit-Level_JR2020600", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people.\nToday, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.\nWe are seeking hardworking, determined, and imaginative individuals to join our automotive verification group. As the owner of HSIO IP's unit level verification, you will contribute to projects crafting the future of automotive chips and systems. You will gain direct experience of chip working with high-performance CPU and memory sub-systems, NOC-based interconnect fabric, high-speed I/Os, and various advanced technologies used in our Tegra chips.\n \nWhat you'll be doing:\nYou will develop UVM-based verification test benches and methodologies. These will verify our in house ARM architecture based distributed fabric needed to transport control, sidebands and data as needed.\nDuring the course of a project, you will drive the following aspects of verification for your unit:\nArchitect the testbenches and craft verification environment using SV and UVM methodology\n\nDefine test plans, tests and verification infrastructure for modules, clusters and systems\n\nBuild efficient and reusable bus functional models, monitors, checkers, and scoreboards\n\nImplement functional coverage and coordinate the verification closure process for the unit\n\nWork with architects, designers, FPGA, and post-silicon teams to ensure that your unit is robust\n\nWhat we need to see:\nBTech or MTech in ECE, EE, CSE, or an equivalent degree is required. Candidates should have 4+ years of demonstrated ability in verification closure of complex units, sub-systems, or SOC level verification.\n\nProven experience in ARM architecture and protocols (AXI, AHB and APB)\n\nExperience in the latest verification methodologies like SV and UVM\n\nGood debugging and analytical skills with exposure to industry-standard verification tools for simulation and debug\n\nGood interpersonal skills, ability to work as a diligent teammate, and excellent communication skills to collaborate with cross-cultural global teams and work in a matrix organization\n\nWays to stand out from the crowd:\nExposure on using AI (like Claude or Cursor) extensively for code development would be a big plus\n\nA mentality towards constant improvement and looking to build a multiplier effect through your work and automation\n\nExposure to Formal verification would be excellent\n\nWe have some of the most experienced and dedicated people in the world working at NVIDIA. If you're creative and independent, with a genuine passion for adopting the newest technology, we want to hear from you. Join us and be part of something outstanding!\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.\nWidely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior Verification Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-14", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer_JR2017971", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nNVIDIA is seeking best-in-class Senior SoC/CPU Verification Engineer to verify the world's most powerful CPUs/Socswith AI capabilities for self-driving cars, gaming consoles & other automated machines (see NVIDIA Grace CPU and Arm Architecture | NVIDIA). NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to pursue, that only we can take on, and that matter to the world. We have crafted a team of excellent people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n\nWhat you’ll be doing:\nWork alongside brilliant engineers on NVIDIA's next generation CPU\n\nVerify micro-architecture/architecture features at unit level or subsystem or full chip testbenches including FPGA/Silicon\n\nPartner with CPU architects in crafting verifiable designs.\n\nWorking on full stack development - from verifying sequences at SW simulator level, to getting the overall end-to-end sequence working on silicon with a full SW stack.\n\nWhat we need to see:\nStrong verification fundamentals and are able to juggle working on SW simulators vs Silicon\n\nProficiency in CPU architecture (ARM knowledge is desirable), Coherent fabric designs, Verilog, System Verilog and possess strong debugging skills.\n\n3+ years of experience with Bachelors/Masters in Computer Science or Electronics Engineering or equivalent experience\n\nWays to stand out from the crowd:\nWorked on various pieces of CPU unit/microarchitecture verification, Interconnect, system memory coherency\n\nYou have worked on complex coverage driven verification projects\n\nExperience of collaborating with geographically diverse multi-functional teams\n\nWith competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most resourceful and versatile people in the world working for us and, due to outstanding growth, our best-in-class engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior Verification Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-14", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer_JR2017972", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nNVIDIA is seeking best-in-class Senior SoC/CPU Verification Engineer to verify the world's most powerful CPUs/Socswith AI capabilities for self-driving cars, gaming consoles & other automated machines (see NVIDIA Grace CPU and Arm Architecture | NVIDIA). NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to pursue, that only we can take on, and that matter to the world. We have crafted a team of excellent people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n\nWhat you’ll be doing:\nWork alongside brilliant engineers on NVIDIA's next generation CPU\n\nVerify micro-architecture/architecture features at unit level or subsystem or full chip testbenches including FPGA/Silicon\n\nPartner with CPU architects in crafting verifiable designs.\n\nWorking on full stack development - from verifying sequences at SW simulator level, to getting the overall end-to-end sequence working on silicon with a full SW stack.\n\nWhat we need to see:\nStrong verification fundamentals and are able to juggle working on SW simulators vs Silicon\n\nProficiency in CPU architecture (ARM knowledge is desirable), Coherent fabric designs, Verilog, System Verilog and possess strong debugging skills.\n\n3+ years of experience with Bachelors/Masters in Computer Science or Electronics Engineering or equivalent experience\n\nWays to stand out from the crowd:\nWorked on various pieces of CPU unit/microarchitecture verification, Interconnect, system memory coherency\n\nYou have worked on complex coverage driven verification projects\n\nExperience of collaborating with geographically diverse multi-functional teams\n\nWith competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most resourceful and versatile people in the world working for us and, due to outstanding growth, our best-in-class engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.", "jd_status": "stored"}, {"title": "ASIC Verification Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-14", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/ASIC-Verification-Engineer_JR2018695", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.\n\nNVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! In this position, you will be expected to plan and implement IP/Cluster/SOC functional verification of designs that constitute our Graphics Processors and Tegra SOCs. You would work on creating regression plans for code as well as functional coverage closure. You would perform pre-silicon validation activities such as XPROP simulations and GLS.\n\nWhat you’ll be doing:\nOwn ASIC verification of IP/Cluster for complicated designs in RTL.\n\nWork with HW architects and designers to make the right implementation choices.\n\nInteract with the Performance verification teams to augment verification through dynamic simulations and/or Formal verification techniques.\n\nYou will work with the specifications and ensure functional and code coverage of all the RTL which you will verify.\n\nPartner with and enable FPGA and S/W teams to ensure that S/W is tested.\n\nBe involved with post-silicon verification and debug.\n\nWhat we need to see:\nBS / MS or equivalent experience.\n\n1+ years of design experience.\n\nExperience in ASIC verification of complex design units for at least one or two projects.\n\nBackground with design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).\n\nExposure to System Verilog and UVM based methodology for ASIC verification is highly desired.\n\nWays to stand out from the crowd:\nKnowledge of Memory controllers or prior experience with verification of IP/clusters involving access to Memory.\n\nGood debugging and problem solving skills.\n\nScripting knowledge (Python/Perl/shell).\n\nGood interpersonal skills and ability & desire to work as a part of a team.\n\nNVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior IP Design Verification Engineer - XBAR IP", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-14", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-IP-Design-Verification-Engineer---XBAR-IP_JR2019350", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of memory subsystem units for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n\nThe GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nYou will be responsible for verifying the ASIC design, architecture and micro-architecture of memory sub-systems/units using advanced verification methodologies.\n\nUnderstand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.\n\nComing up come up with test plans, tests and verification infrastructure for complex IPs/sub-systems.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nWork on advanced verification methodologies like SV/UVM.\n\nPerform functional coverage driven verification closure.\n\nWorking with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech., or equivalent experience.\n\n4+ years of relevant experience.\n\nExperience in verification of complex IPs/units and sub-systems.\n\nBackground in verification using random stimulus along with functional coverage and assertion-based verification methodologies.\n\nExpertise in Verilog.\n\nKnowledge in SystemVerilog or similar HVL / UVM or VMM.\n\nWays to stand out from the crowd:\nExperience in memory subsystem or network interconnect IP verification.\n\nDebugging and analytical skills with sound scripting knowledge.\n\nGood communication and excellent team player.\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior IP Design Verification Engineer - XBAR IP", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-14", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-IP-Design-Verification-Engineer---XBAR-IP_JR2022804", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of memory subsystem units for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n\nThe GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nYou will be responsible for verifying the ASIC design, architecture and micro-architecture of memory sub-systems/units using advanced verification methodologies.\n\nUnderstand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.\n\nComing up come up with test plans, tests and verification infrastructure for complex IPs/sub-systems.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nWork on advanced verification methodologies like SV/UVM.\n\nPerform functional coverage driven verification closure.\n\nWorking with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech., or equivalent experience.\n\n4+ years of relevant experience.\n\nExperience in verification of complex IPs/units and sub-systems.\n\nBackground in verification using random stimulus along with functional coverage and assertion-based verification methodologies.\n\nExpertise in Verilog.\n\nKnowledge in SystemVerilog or similar HVL / UVM or VMM.\n\nWays to stand out from the crowd:\nExperience in memory subsystem or network interconnect IP verification.\n\nDebugging and analytical skills with sound scripting knowledge.\n\nGood communication and excellent team player.\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior Verification Engineer - HSIO Cluster and SOC", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-14", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer---HSIO-Cluster-and-SOC_JR2020603-1", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people.\nToday, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.\nWe are seeking enthusiastic, driven, and imaginative individuals to join our automotive verification group. As the owner of HSIO IP's cluster and SOCV level verification, you will contribute to projects crafting the future of automotive chips and systems. You will gain direct experience of chip working with high-performance CPU and memory sub-systems, NOC-based interconnect fabric, high-speed I/Os, and various advanced technologies used in our Tegra chips.\n \nWhat you'll be doing:\nYou will develop verification components and API's for cluster and system level test benches. These will verify complex rapid data transfer IO IPs and sub-systems such as USB, UFS, MPHY, Ethernet, and MACSEC.\nDuring the course of a project, you will drive the following aspects of verification for your unit:\nArchitect the testbenches and craft verification environment using SV, C/C++ methodology\n\nDefine test plans, tests and verification infrastructure for clusters and systems\n\nBuild efficient and reusable bus functional models, monitors, checkers, and scoreboards\n\nImplement functional coverage and own SOC level verification closure\n\nWork with architects, designers, FPGA, and post-silicon teams to ensure that your unit is robust\n\nWhat we need to see:\nBTech or MTech in ECE, EE, CSE, or an equivalent degree is required. Candidates should have over 4 years of experience in verification closure of complex units, sub-systems, or SOC level verification.\n\nProven experience in High Speed IO verification (UFS/PCIE/XUSB), knowledge of 10G/1G Ethernet MAC and Switch\n\nExperience in the latest verification methodologies like SV and UVM\n\nGood debugging and analytical skills with exposure to industry-standard verification tools for simulation and debug\n\nGood interpersonal skills, ability to work as a diligent teammate, and excellent communication skills to collaborate with cross-cultural global teams and work in a matrix organization\n\nWays to stand out from the crowd:\nExposure on using AI (like Claude or Cursor) extensively for code development would be a big plus\n\nA mentality towards constant improvement and looking to build a multiplier effect through your work and automation\n\nExposure to Formal verification would be excellent\n\nWe have some of the most experienced and dedicated people in the world working at NVIDIA. If you're creative and independent, with a genuine passion for adopting newest technology, we want to hear from you. Join us and be part of something outstanding!\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.\nRecognized as one of the most sought-after employers in the technology sector, NVIDIA provides highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "ASIC Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-14", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/ASIC-Engineer_JR2023232", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA builds accelerated computing platforms that are redefining AI, data centers, autonomous systems, and scientific computing. The Global Flows Team advances RTL quality and sign-off methodologies used across NVIDIA CPU programs. This position connects digital implementation and microarchitecture with CDC, RDC, RTL-NA/DA, PSI and lint. The work spans methodology development, technical analysis, tool deployment, and coordination across development and CAD organizations. Results improve RTL quality, project predictability, and readiness for silicon.\n\nWhat you’ll be doing\nAs an ASIC Engineer, you will embark on an ambitious journey to develop and deploy innovative RTL design-quality methodologies. These include CDC, RDC, Netlist/Design Auditors, Power Insertion, lint, and related structural checks. Your role will involve: \nAnalyzing flow results in the context of design intent and identifying root causes across RTL, constraints, tools, and methodology.\n\nEstablishing quality requirements and readiness criteria for project achievements while monitoring regressions, violation trends, and sign-off status.\n\nCollaborating across RTL build, DFT, clocks, reset, low-power, physical-design, verification, and CAD teams to resolve technical issues.\n\nAssessing new tool releases and methodology capabilities, coordinating their integration into project environments.\n\nImproving runtime, debug efficiency, waiver management, reporting, and training through automation, reusable scripts, and engineering guidelines.\n\nWhat we need to see\nWe are seeking a professional with:\nA Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.\n\n3+ years of proven experience in ASIC or SoC RTL design or design-methodology.\n\nPractical experience with Verilog or SystemVerilog build, analysis, and debugging.\n\nKnowledge of digital design and microarchitecture, including pipelines, finite-state machines, clock/reset architectures, synchronizers, handshakes, asynchronous FIFOs, metastability, and power-domain crossings.\n\nExperience with front-end methodologies such as lint, CDC/RDC, structural RTL analysis, low-power verification, synthesis, or timing constraints.\n\nThe ability to relate methodology results to RTL behavior and perform detailed root-cause analysis.\n\nExperience with Linux development environments and scripting in Python, Tcl, Perl, shell, or a comparable language.\n\nWays to stand out from the crowd\nTo shine in this role, you may possess:\nExperience with RTL integration, design bring-up, or multi-team debugging at the unit, subsystem, chiplet, or SoC level.\n\nFamiliarity with tools such as Meridian, SpyGlass, VC CDC, Questa CDC, Design Auditor, Power insertion, or equivalent.\n\nKnowledge of UPF and low-power RTL implementation or verification.\n\nExperience with SDC, synthesis, static timing analysis, formal verification, or equivalence checking.\n\nJoin NVIDIA and help build the future of technology. Your efforts will drive us toward our demanding targets and build a meaningful legacy in the world. This is your chance to be part of a world-class team and compete at the highest level!\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.", "jd_status": "stored"}, {"title": "Senior Verification Engineer - Hardware", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-14", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer---Hardware_JR2020604", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nWe are now looking for passionate, highly motivated and creative individuals to be part of our automotive verification team. As a verification owner, you will work on projects that will define the next generation of automotive chips and systems. You will get firsthand exposure to high performance CPU and Memory sub-systems, NOC based Interconnect Fabric, High speed IO's and many other leading technologies deployed in our Tegra chips.\n\nWhat you will be doing:\nYou will be responsible for creation of \"state of the art\" UVM based verification test benches and methodologies to verify complex IP's and Sub-systems. You will also get to work on System level verification using C/C++. During the course of a project you would end up driving the following aspects of verification for your unit:\nArchitect the testbenches and craft verification environment using UVM methodology\n\nDefine test plans, tests and verification infrastructure for modules, clusters and system\n\nBuild efficient and reusable bus functional models, monitors, checkers and scoreboards\n\nImplement functional coverage and own verification closure\n\nWork with architects, designers, FPGA and post-silicon teams to ensure that your unit is robust\n\nWhat we need to see:\nYou should be BTech/MTech with 4+ years of experience in verification closure of complex Unit, Sub-system or SOC level verification. If you have experience in at least a few of the following domains, we will have an excellent match for our needs:\nCPU verification, Memory controller verification, Interconnect verification\n\nHigh Speed IO verification (UFS/PCIE/XUSB)\n\n10G/1G Ethernet MAC and Switch\n\nBus protocols (AXI/APB)\n\nSystem functions like Safety, Security, Virtualization and sensor processing\n\nExperience in the latest verification methodologies like UVM/VMM\n\nExposure to industry standard verification tools for simulation and debug is a requirement\n\nExposure to Formal verification would be excellent\n\nGood debugging and analytical skills.\n\nGood interpersonal skills, ability to work as an excellent teammate with excellent communication skills to collaborate with cross-cultural teams and work in a matrix organization\n\nWith highly competitive salaries and a comprehensive benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you're creative and independent, with a genuine real passion for technology, we want to hear from you.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior Staff Analog Design Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-13T15:14:56.731000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000143343829-senior-staff-analog-design-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Looking for a 10+ years + Masters experienced Engineer with in-depth understanding of Analog concepts, experience of from scratch design of complex Analog I/Ps & sub-blocks, integrating I/Ps and sub systems and ownership, experienced of fully owning smaller ICs (Point of loads, Single Converters) and owning major I/Ps in large PMICs, to join the 2.6B$ Power Business Unit. The candidate will get to work on a wide range of exciting products such as PMICs, Linear and Switching DC-DC converters powering the next generation of most sought-after phones and handheld devices. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas’s massive Power product portfolio.\nEssential Functions:\nMust be proficient in designing and owning complex I/Ps like +ve/-ve Charge Pumps, Source-Sink LDOs, Ultra-low power Oscillators (including Relaxation type), Temperature Sensor, Current Sense, SAR ADCs, House Keeping blocks, Protection (Thermal, Under-Voltage, Over-Voltage, Over Current etc) and analog blocks including Bandgap references, V2I, Analog Buffers, Op-Amps, Comparators, High speed level shifters etc. Thorough understanding of Switch Cap circuits will be advantageous.\nMust have in-depth Understanding of and should be able to Implement & Compensate the Control Loops, Analog feedback loops and should know trade-offs between various compensation strategies.\nShould be able to build/support Block level spec break down from Top level chip requirements and independently own, design complete switching converter e.g. Buck, Boost, Buck-Boost etc and LDOs. Must be able to do block level error budgeting depending on the block requirements.\nMust be aware of relative differences of various control loop architectures (Constant Freq, Constant ON/OFF Time, Current mode etc) and decide/implement the best option to meet converter level performance specifications and other system requirements.\nMust be able to bring in innovative ideas to improve designs to meet challenging specifications.\nShould have in-depth knowledge of Analog layouts and be able to work closely with layout lead from floor planning till Chip Top completion and verification and do trade-offs based on desired performance\nMust be conversant with the standard design, extraction and simulation flows & tools, speed, convergence, accuracy trade-offs and should be able to optimize setups based on Pre/Post (with/without) Parasitic using simulator options, debug and navigate through tool related challenges.\nShould be able to setup design flows and methodologies including checklists, reviews to ensure quality designs and take them all the way to Silicon success.\nShould be able to mentor Freshers and Junior engineers for upscaling their technical skills as well as other skills needed for better efficacy.\nShould have experience of end-to-end IC development flow, Silicon debugs, and taking ICs to production\nShould be able to lead a small group of Engineers and navigate through all stages of IC development while handling and mitigating challenges, ensuring high quality silicon while adhering to the schedules based on business needs.\nShould have in-depth understanding of ESD, LU and other IC level issues and be able to define protection for the I/O ring for the IC\n\nMinimum Requirements:\nBachelor’s or master’s degree in electrical engineering\n10+ years in Analog Circuit Design, Simulation and Verification\nSolid understanding and design experience of complex analog designs with full ownership.\nChip design, Verification, Silicon validation, debugs, Qual support and taking ICs to production.\nMust be a natural team player, mentor and strive towards fostering a highly creative and productive working environment\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Principal Engineer", "company": "Infineon", "location": "Bangalore", "date_posted": "2026-08-13T13:42:13+00:00", "url": "https://jobs.infineon.com/careers/job/563808971773333", "is_hardware": true, "platform": "eightfold", "jd_text": "Join our team as a Principal Engineer and lead New Product Introduction (NPI) and production engineering for cutting-edge IoT products. In this role, you will own product characterization from design through production, drive post-silicon debug and validation, and collaborate with design, test, reliability, process, and manufacturing teams to resolve yield, quality, and production challenges. You will also lead process improvement initiatives, enhance data analytics capabilities, and ensure the successful delivery of high-quality, cost-effective products to production.\n\nYour role\nKey responsibilities in your new role\n\nLead New Product Introduction (NPI) and production support engineering activities for IoT products.\nDrive product bring-up, characterization, post-silicon debug, and validation from design phase through production release.\nCollaborate with Design, Test, Reliability, Process, and Manufacturing teams to resolve product and production issues related to yield, quality, and stability.\nOwn and deliver characterization (Char) milestones, ensuring high-quality and timely execution.\nIdentify and implement process improvements to enhance manufacturing efficiency, improve yields, and reduce production costs.\nAnalyze production and characterization data to identify trends, risks, and opportunities for optimization.\nLead planning, prioritization, stakeholder coordination, and execution of engineering deliverables.\nEnsure compliance with internal engineering processes, quality standards, and project requirements.\nDevelop and enhance data analytics capabilities by consolidating data sources and enabling faster, automated analysis and reporting.\nDrive continuous improvement initiatives to support successful product ramp-up and sustained production performance.\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor’s or Master’s degree in Electrical/Electronics Engineering or a related discipline.\n9+ years of product engineering experience in digital, mixed-signal, RF, or SoC semiconductor products.\nStrong understanding of semiconductor manufacturing and production flows, including wafer processing, assembly, and production testing.\nHands-on experience with product characterization, yield analysis, failure analysis, and production support.\nProficiency in statistical analysis techniques and data analysis tools for product and manufacturing optimization.\nExperience working with complex semiconductor products and driving issue resolution across multiple engineering disciplines.\nStrong analytical and problem-solving skills with the ability to address high-complexity technical challenges.\nExcellent communication, stakeholder management, and technical leadership skills.\nProven ability to collaborate effectively with cross-functional and global teams.\nRF product experience is highly desirable.\nHands-on experience with Automated Test Equipment (ATE), preferably Teradyne UltraFLEX and/or Advantest V93000 (93K), is an added advantage.\nDemonstrated ability to lead initiatives, drive continuous improvement, and deliver results in a fast-paced product engineering environment.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nAnand Rawal", "jd_status": "stored"}, {"title": "Experienced Engineer - FPGA CAD", "company": "Ericsson", "location": "Bangalore,Karnataka,India", "date_posted": "2026-08-13T13:24:34+00:00", "url": "https://jobs.ericsson.com/careers/job/563121777008688", "is_hardware": true, "platform": "eightfold", "jd_text": "Join our Team\n\nAbout this opportunity:\n \nYou will join the FPGA CAD team to support design and verification teams which focuses on legacy, current, and next-generation Radio/RAN compute products within Ericsson. The new hire will play a critical role in strengthening Ericsson’s silicon strategy by supporting automation and FPGA CAD methodology to enhance the efficiency of a new site in Bangalore. \n \nYou will do:\n \nDevelop, test, and deploy FPGA CAD tools and automation flows to support FPGA product development.\nAssist in defining design specifications, implementation strategies, CAD methodologies and debugging for FPGA tools and automation flows.Develop and maintain automation scripts for FPGA design and simulation flow and support engineers in resolving tool, environment, and runtime issues by engaging AE teams from suppliers.\nThe automation scripts to include but not be limited to synthesis, place & route, bitstream generation, timing closure, QoR analysis and performance assessment - power estimation, timing analysis for design flow/ compile, elaboration, run, debug, regression and performance assessment – runtime, memory, licenses for simulation flow.\nSupport FPGA design and verification engineers by automating the performance assessment of new tool versions and features.\n\nBuild and maintain relationships with FPGA project teams to ensure alignment on goals and support timelines.\nContribute to the continuous improvement of products, tools, and processes.\nFollow and contribute to the team’s CAD guidelines, best practices, processes, and documentation standards.\n \nYou must have:\n \n3 to 5 years of experience in Python software development.\nStrong understanding of Python idioms, data structures, and object-oriented design.\nExperience with automated testing (unit, integration) and TDD practices.\nAbility to understand, reuse existing code effectively and/or write reusable, modular, and well-documented code.\nStrong experience with scripting languages such as Tcl, Bash, Perl, etc\nFamiliarity with version control systems such as Git.\nA problem-solving attitude, self-motivation, and eagerness to learn and contribute.\nExcellent English verbal and written communication skills.\nBachelor’s or Master’s degree in Electronics or Computer Engineering or equivalent\n\nNice to have:\n\nKnowledge of CI/CD tooling such as Jenkins.\nFamiliarity with REST APIs.\nExperience with relational databases and SQL.\nFamiliarity with FPGA/ASIC development, including ability to read and debug SystemVerilog/Verilog designs.\nExposure/Hands-on with FPGA design and RTL simulation tools.\nUnderstanding of FPGA design/simulation flow and automation experience.\nExposure with FPGA timing constraints (XDC/SDC), QoR analysis, and regression flows.\nExposure with FPGA tools (Vivado, Quartus, Radiant)\n\n*\n\n“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”\n\nWhy join Ericsson?At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.\n \nWhat happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.\n \nPrimary country and city: India (IN) || Bangalore\nReq ID: 788877", "jd_status": "stored"}, {"title": "Staff Engineer ", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-08-13T11:56:58+00:00", "url": "https://jobs.infineon.com/careers/job/563808971837078", "is_hardware": true, "platform": "eightfold", "jd_text": "Responsible for Physical Verification, Reliability Sign-off, EM/IR Analysis, Power Grid Design, Analog/Mixed-Signal Integration, and methodology development for complex low-power SoCs targeting IoT and MCU applications\n\nYour role\nKey responsibilities in your new role\n\nDrive Physical Verification (PV), ESD, and Reliability Sign-off activities for complex low-power SoCs targeting IoT and MCU applications.\nPerform Physical Design and Timing Closure for ICW SoCs. Execute and own Physical Verification and Reliability Checks to ensure design quality and manufacturability. \nConduct Power Grid Design, including power switch estimation and optimization.\nPerform Static and Dynamic EM/IR Analysis for multi-voltage and multi-power domain designs. \nLead I/O Planning and Package Co-design activities for SoC implementation.\nDrive Analog and Mixed-Signal IP Integration into SoC designs.\nDevelop and improve design flows, methodologies, QoR (Quality of Results), and sign-off processes.\nCollaborate closely with Physical Design, STA, DFT, RTL, DV Engineers, and Chip Architects to ensure successful project execution. \nSupport implementation of SoCs with multiple voltage islands, power islands, and low-power design techniques\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor’s or Master’s degree in VLSI Design with 5 -8 years of relevant industry experience. \nHands-on experience in Physical Verification (PV), ESD, and Reliability Sign-off for complex SoCs.\nStrong expertise in Power Grid Design, Power Switch Estimation, and Static/Dynamic EMIR Analysis for multi-voltage and multi-power domain designs.\nDeep understanding of low-power SoC implementation, including multiple voltage islands, power islands, and power reduction techniques.\nExperience with industry-standard Physical Verification and Power Grid Sign-off tools.\nKnowledge of semiconductor technologies including 40nm, 28nm, and 22nm nodes, along with WireBond and FlipChip packaging methodologies.\nProficiency in scripting and automation using Shell, Perl, Tcl, and Make-based flows. \nExperience in I/O Planning, Package Co-design, and Analog/Mixed Signal IP Integration for SoC designs.\nProven ability to drive flow and methodology improvements to enhance QoR and Sign-off efficiency. \nStrong ownership, technical commitment, and a results-oriented mindset. \nHighly organized, detail-oriented, and methodical in problem-solving and execution. \nDemonstrated ability to take initiative, drive innovation, and overcome technical challenges. \nEffective collaborator with the ability to work across Physical Design, STA, DFT, RTL, DV, and Architecture teams. \nExcellent communication skills with a track record of knowledge sharing and cross-functional partnership\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nKeerthini M H", "jd_status": "stored"}, {"title": "Principal Engineer Design", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-08-13T11:26:33+00:00", "url": "https://jobs.infineon.com/careers/job/563808971849146", "is_hardware": true, "platform": "eightfold", "jd_text": "#WeAreIn to draw on our creativity to develop analog and mixed-signal circuit solutions. Are you in?\n\nYour role\nKey responsibilities in your new role\n\nOwn end-to-end IO library design and development.\n\nCollaborate with system architects to define and finalize IO specifications.\nLead IO integration into subsystems and provide expert guidance on IO selection, implementation, and qualification.\nDrive IO quality sign-offs and ensure compliance with milestone deliverables.\nDefine IO architectures and align designs with product requirements.\nMentor and review team members' work to improve design quality, performance, power, and area optimization.\nProvide hands-on support for Front-End (FE) and Back-End (BE) development activities.\nEnhance design and verification methodologies to improve efficiency and quality.\nEnsure adherence to quality standards and development processes for library design.\n\nYour profile\nQualifications and skills to help you succeed \n\nBE/BTech/MTech in ECE, VLSI, or related field with 12+ years of IO design and development experience.\n\nStrong expertise in IO design for LVTTL, LVCMOS, DDR, SPI, xSPI, Oscillator, LVDS, and voltage-tolerant circuits.\nGood understanding of ESD (Electrostatic Discharge) and Latch-Up concepts.\nExperience with IO library characterization methodologies.\nProven ability to lead small design/layout teams and drive architecture development and project planning.\nTrack record of delivering chip designs from specification to silicon.\nStrong process management, problem-solving, multitasking, and attention to detail.\nExcellent analytical, communication, and cross-functional collaboration skills.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Principal Engineer", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-08-13T11:04:37+00:00", "url": "https://jobs.infineon.com/careers/job/563808971811663", "is_hardware": true, "platform": "eightfold", "jd_text": "We are looking for an experienced SoC/IP Verification Engineer to lead and drive the verification of complex semiconductor designs. The role involves defining verification strategies, architecting and developing scalable constraint-random verification environments, and driving verification closure at both subsystem and SoC levels. The ideal candidate will possess strong expertise in System Verilog/UVM-based verification methodologies and hands-on experience across functional, power-aware, and gate-level verification flows.\n\nYour role\nKey responsibilities in your new role\n\nLead and contribute to the definition of verification architecture and strategy for IPs, subsystems, and SoCs.\nDevelop robust constraint-random verification environments from scratch using SystemVerilog and UVM methodologies.\nBuild reusable verification components, assertions, coverage models, and testbenches to ensure comprehensive design validation.\nVerify ARM-based IPs and SoCs with strong understanding of AHB, AXI, and serial communication protocols.\nPerform RTL verification, power-aware simulations, Gate-Level Simulations (GLS), boot verification, and drive end-to-end verification closure.\nDevelop C-based tests, debug complex functional issues using Tarmac, and collaborate closely with design and software teams.\nDrive automation initiatives to improve verification productivity, coverage, and quality.\nMentor and guide junior engineers while promoting verification best practices across the team.\n\nYour profile\nQualifications and skills to help you succeed \n\nStrong expertise in Verilog/SystemVerilog, UVM, C programming, and Tarmac debugging.\nProven experience in IP and SoC verification, including verification planning, component development, assertion coding, and constrained-random verification.\nExperience leading or contributing to the development of verification architectures and UVM environments from scratch at subsystem and SoC levels.\nHands-on experience in RTL verification, Power-Aware Verification, Gate-Level Simulation (GLS), and Boot Verification.\nStrong knowledge of ARM-based architectures, AHB/AXI protocols, and industry-standard serial interfaces.\nExperience with verification automation, coverage closure, regression management, and verification signoff activities.\nStrong analytical, debugging, leadership, and stakeholder management skills.\nAbility to mentor engineers and drive verification excellence on complex SoC programs.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nAnand Rawal", "jd_status": "stored"}, {"title": "RTL Design Lead - IP Design", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-08-13T09:56:00+00:00", "url": "https://global-external-amd.icims.com/jobs/86881/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. SMTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Computing and Graphics Group, you will help bring to life cutting-edge designs. You will lead a front-end design and integration team, working closely with architecture, design verification, physical design, and product engineers to achieve first pass silicon success. THE PERSON: The ideal candidate will have experience leading teams and developing RTL for SoC subsystems from architectural specification to silicon. Responsibilities include IP and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC team. KEY RESPONSIBLITIES: Design of IP and subsystems with integration of AMD and other 3rd party IPs Perform quality checks (lint, CDC, and power rule checks) of power-gated digital designs Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up PREFERRED EXPERIENCE: 10+ years full-time experience in IP hardware design Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs Verilog lint tools (Spyglass) and verilog simulation tools (VCS) Clock domain crossing (CDC) tools Detailed understanding of SoC design flows Understanding of IP/SS/SoC Power Management techniques – Power Gating, Clock Gating Experience with embedded processors and data fabric architectures (NoC) Outstanding interaction skills while communicating both written and verbally Ability to work with multi-level functional teams across various geographies Outstanding problem-solving and analytical skills  ACADEMIC CREDENTIALS: Bachelors degree in Computer Engineering/Electrical Engineering plus 12 years full-time experience in IP hardware design, or Masters degree plus 8 years experience in same. #LI-NS1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Staff Engineer, Physical Design", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-13T09:40:55.482000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000143271539-senior-staff-engineer-physical-design", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Renesas India is seeking an experienced Senior Staff Physical Design Engineer to lead subsystem- and block-level physical implementation and closure for complex hierarchical SoCs at advanced technology nodes. This role requires deep expertise in timing, congestion, power integrity, and clocking methodologies, along with strong cross-functional collaboration skills. While this role does not own SoC-level physical design, it plays a critical role in aligning subsystem implementation with overarching SoC strategies.\nKey Responsibilities\nLead block- and subsystem-level physical design closure, including timing closure, congestion mitigation, power integrity, and overall physical implementation quality\nCollaborate closely with SoC-level physical design teams to align on clocking strategies, floorplanning intent, and integration requirements, without direct ownership of SoC-level execution\nApply deep understanding of clocking methodologies to ensure subsystem-level clock domains integrate cleanly into the broader SoC clock architecture\nDevelop, refine, and scale subsystem closure methodologies, flows, and automation, improving predictability, quality, and execution efficiency\nMentor and guide physical design engineers within subsystem teams, promoting best practices, technical rigor, and methodology adoption\nWork cross-functionally with RTL design, STA, power, verification, and backend teams to ensure smooth handoffs and robust closure\nProactively identify, assess, and mitigate physical design risks, coordinating closely with SoC teams to manage impacts and drive solutions\n\n10+ years of experience in physical design, with a strong focus on subsystem-level closure for complex hierarchical SoCs\nStrong expertise in:Timing closure and constraint management\nCongestion analysis and resolution\nPower integrity and power-aware physical implementation\nBlock and subsystem-level physical design flows\n\nSolid understanding of SoC-level floorplanning and clocking methodologies, including:Clock domain partitioning\nClock tree architecture\nSkew management\nClock gating\n\n(Candidate is expected to collaborate effectively at the SoC level, not lead these activities.)\n\nHands-on experience with industry-standard tools such as:Synopsys ICC2, Fusion Compiler, PrimeTime\nCadence Innovus, Tempus, Certus\nSignoff and analysis platforms\n\nProficiency in scripting and automation using Tcl, Python, and/or Perl\nDeep knowledge of end-to-end SoC design flows, with strong collaboration experience across timing, power, clocking, verification, and backend teams\nStrong understanding of low-power design techniques and power-aware implementation methodologies\nEducation\nB.Tech or M.Tech in Electronics and Communication, Electrical Engineering, Computer Science, or a related field\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "RTL Synthesis Methodology Principal/ Sr Staff Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-13T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446717261607", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs the Principal Engineer, RTL Synthesis Methodology Lead  you will drive the technical direction and deployment of next-generation RTL-to-Gate implementation flows for Qualcomm’s industry-leading SoCs (Snapdragon Mobile, Automotive, Compute, and IoT). You will lead the definition and optimization of synthesis methodologies to maximize Power, Performance, and Area (PPA) while ensuring robust Signoff closure for Synthesis, Low Power, STA, and LEC.\nYou will partner closely with Design teams (CPU, GPU, Modem, DSP), Physical Design (PD) teams, and major EDA vendors (Synopsys, Cadence) to benchmark, certify, and deploy advanced features like Physical Synthesis, Machine Learning-based optimization, and Unified Low Power flows.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n\nKey Responsibilities\nMethodology Leadership: Lead the definition, development, and deployment of the global RTL Synthesis Reference Flow (Fusion Compiler, Genus) across multiple technology nodes (5nm, 3nm, 2nm and beyond).\nPPA Optimization: Drive \"RTL2GDS\" co-optimization initiatives. collaborate with RTL and PD teams to deliver measurable PPA improvements through advanced synthesis techniques\nLow Power Synthesis: Architect and maintain the Low Power (UPF/IEEE 1801) implementation methodology. Drive  the flow for Static Low Power checking (CLP/VCLP) and power intent verification from RTL to Netlist.\nSignoff Convergence (STA & LEC): Ownership of Logic Equivalence Checking (LEC) flows (Conformal/Formality) for complex data paths, retiming, and functional ECOs. Drive constraints management and early STA signoff quality (Fishtail, PrimeTime).\nTool Roadmap & Vendor Engagement: Act as the primary technical interface with EDA vendors (Synopsys, Cadence). Drive tool roadmaps, manage beta evaluations, and file critical enhancements to close gaps between foundry claims and actual product PPA.\nFlow Automation: Oversee the development of scalable, robust automation (Python/Tcl) to integrate synthesis with DFT insertion and Netlist Signoff.\nMentorship: Mentor a team of CAD engineers, providing technical guidance on complex debugs, flow architecture, and best practices.\nMinimum Qualifications\nExperience: 15+ years of solid experience in ASIC CAD flow development, Physical Design, or Synthesis Methodology.\nEducation: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.\nSynthesis Expertise: Deep expertise in industry-standard Synthesis tools (Synopsys Fusion Compiler (FC)/Design Compiler (DC-NXT) and Cadence Genus). Proven track record of solving complex PPA challenges.\nSignoff Expertise: Hands-on mastery of Logic Equivalence Checking (LEC) tools (Cadence Conformal LEC, Synopsys Formality) including debug of difficult non-equivalent points in datapath-heavy designs.\nTiming & Constraints: Strong understanding of Static Timing Analysis (STA), SDC constraints generation, and validation (PrimeTime, GCA/Fishtail).\nScripting: Advanced proficiency in Tcl and Python for flow development and data analysis.\nPreferred Qualifications\nLow Power Synthesis: Deep knowledge of UPF/CPF flows, multi-voltage domains, power gating, retention\nPhysical Awareness: Experience with Physical Synthesis technologies (Def-based flow, iSpatial, Physical guidance) and correlation with P&R tools (Innovus/ICC2).\nDFT Integration: Familiarity with RTL-integrated DFT flows (Scan stitching, MBIST insertion) and their impact on timing/congestion.\nLeadership: Demonstrated ability to lead cross-site projects, influence design methodologies, and manage stakeholder expectations in a fast-paced environment.\nInnovation: Experience with AI/ML-driven CAD tools (e.g., Fusion.ai, Cerebrus) for design space exploration is a strong plus.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SoC Verification Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-08-13", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/SoC-Verification-Engineer_JR0286326", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nAbout the Team:\nYou will be joining Intel's cutting-edge product development group, a team focused on designing and verifying advanced semiconductor solutions. This group is at the forefront of innovation, delivering high-quality, scalable products that drive Intel's leadership in technology and performance. By contributing your skills here, you will help shape the future of computing and enable groundbreaking advancements in the industry.\n\nPosition Overview:\nAs a SoC Design Verification Engineer, you will play a pivotal role in ensuring that Intel's complex System-on-Chip (SoC) designs meet functional specifications and deliver high-quality performance. You will design scalable and reusable verification plans, develop test environments, and execute tests to uncover issues and improve functionality. Your contributions will directly enhance Intel's product quality and ensure optimal performance in presilicon development.\n\nKey Responsibilities:\nCreate and update UVM-based test bench generation and test case creation\n\nDefine and develop scalable and reusable block, subsystem, and SoC verification plans\n\nCreate test benches and verification environments that align with microarchitecture specifications\n\nExecute verification plans, including emulation and system simulation models, to ensure design functionality and uncover bugs\n\nDebug and root cause issues in presilicon environments, implementing corrective measures to address failures\n\nCollaborate with architects, RTL developers, postsilicon teams, and physical design teams to improve verification of complex architectural features\n\nDocument and maintain test plans, driving technical reviews with design and architecture teams\n\nIntegrate security coverage activities within test plans, including regression and debug tests\n\nMaintain and improve existing functional verification infrastructure and methodologies\n\nAbsorb learnings from postsilicon development and incorporate feedback into improved verification strategies.\n\nTo Be Successful, You Should Demonstrate the Following:\nAbility to work collaboratively across interdisciplinary teams\n\nStrong communication skills with the ability to work across interdisciplinary teams\n\nPassion for tackling complex problems and delivering innovative solutions\n\nQualifications:\nMinimum Qualifications:\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 7+ years of hands-on experience in SoC design verification, including demonstrated expertise in OVM/UVM methodologies, debugging, and test planning\nOR\n\nMaster's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 6+ years of hands-on experience in SoC design verification, including demonstrated expertise in OVM/UVM methodologies, debugging, and test planning.\n\nThe experience must include:\nAMBA protocols such as CHI, AXI, AHB, and APB with industry-standard VIP from various EDA vendors\n\nCreation and updating of UVM-based test benches and test case creation\n\nPreferred Qualifications:\nExperience with postsilicon validation and incorporating feedback into presilicon test plans\n\nFamiliarity with emulation models and system simulation tools for performance analysis\n\nWe invite you to bring your expertise and creativity to Intel, where your contributions will make a lasting impact on future technology. Join us and shape the future of computing with your skills and dedication.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Sr. Electrical Engineer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-08-13", "url": "https://careers.skyworksinc.com/job-invite/77785/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 77785\n\nDescription\n\nExperienced PD designer working on multiple technology nodes. 40/22nm analog, RF, and mixed/signal circuits will be an added advantage. \n\nPerform physical design from scratch, modify existing layouts. Create block level floorplans and work within the constraints of higher-level floorplans. Participate in peer and engineering reviews\n\nResponsibilities\n\nStrong experience across synthesis, physical design, STA, DRC/LVS verification, and power analysis. \n\nProvide accurate area, power, and schedule estimates for assigned blocks, with a focus on optimizing PPA (Power, Performance, Area). \n\nWork closely with both design engineers and other layout engineers. \n\nRequired Experience and Skills\n\nWe are looking for an experienced person (~7-10 years) who has overall knowledge of PD and takes care of all the flows associated with it. \n\nApart from PnR & Synthesis: Experience with work closer to the front end such as digital modeling, gate level simulations, CDC, LEC, and STA/synthesis if possible. \n\nFloor planning: Strategically planning the placement of functional blocks on the chip.  \n\nPlacement and Routing: Optimizing the placement of components and connecting them with wires (routing). \n\nDesired Experience and Skills\n\nTiming Closure: Ensuring the chip meets timing requirements (ensuring signals arrive at the correct time).  \n\nPower Integrity: Managing power distribution and ensuring the chip operates reliably.  \n\nVerification: Checking the layout for errors and ensuring it meets design rules.  \n\nECOs: Implementing design changes (ECOs) to fix issues identified during verification.\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Analog Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-08-13", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25017170", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\n This is a great opportunity to be part of an established team that's continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electronics, mobile computing and communications.\n\nWho are we and what do we do?\n\nThe advanced circuits and power solution business is known for delivering industry leading custom IC system solutions including display and touch power products, charger power products, camera PMICs, power path devices, sensing devices and high-performance communication interface products. Our products integrate precision signal-chain and highly efficient power components in ultra-small form factors that enable TI’s best-in-class customer to translate their ideas to high value products that revolutionize the personal electronics market. \n\n In this team, you will get to work with, and learn from incredibly talented technical leaders, who have influenced TI technology, productivity and way of working in a creative and impactful way. You will get to directly interact with one of TI’s valued and high-volume customers, by way of intense technical reviews and architecture discussions! \n\n By enabling designs that are highly impactful to TI revenue and working with a critical customer on a versatile set of products, you will find yourself on an accelerated career path. \n\n  \n\nAbout the job If you are looking to join an ingenious, vigorous & ambitious team that consistently delivers groundbreaking technologies into the custom mobile electronics world, here is an opportunity for you!   \n\nAnalog Design Engineer\n\nLocation: Bangalore, India\n\nExperience: 2+ Years\n\nWhat will you be doing in this role?\n\nAnalog Chip/Sub-section/IP architect and design with complete ownership and responsibility from definition to release to manufacturing.\n\nDirect, guide and participate in activities of a research or technical design function responsible for designing, developing, modifying and evaluating electronic parts, components, integrated circuits for a variety of applications.\n\nEvaluate intermediate and final results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives.\n\nCollaborate with Design Verification teams during the pre-PG phase of a project to ensure completion of all technical tasks before PG.\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production.\n\nQualifications\nBasic Requirements (Must-Haves)\n\nBachelor’s & Master’s degree in Electrical Engineering or related field of study\n\n2+ years of analog circuit design.\n\n  Preferred Skills & \"Good to Have\" \n\nActive involvement with a customer. Candidate would be expected to interact and collaborate with a sense of ownership with customers and all product development team members including design, layout, systems, verification, validation, test and program management\n\nIC system partitioning and architectural tradeoff analysis\n\nBlock level topology selection, hand analysis, and IC transistor level implementation\n\nSchematic generation and simulation on modern CAD tools (Cadence tool set)\n\nWorst case identification, top level simulation, Monte Carlo analysis, and simulation data analysis\n\nExpertise in tools e.g. Spectre, Simplis, Matlab and AMS\n\n  System level understanding and analysis; and the ability to translate requirements to an IC spec level\n\nPhysical layout management, signal grounding and routing tradeoffs, die area optimization\n\nPost layout parasitic extraction and simulation, verification of all IC level performance metrics\n\nTop level verification, block level modelling, top level simulation\n\nKnowledge of device physics and process technologies tradeoffs that are applicable to Power IC design\n\nMust budget time, manage schedule and complete complex IC design tasks on time\n\nMust have depth of experience and meticulous approach to assure high quality results\n\nMust account for limitations of system level specifications, testability, debug, characterization, production and yield targets in the IC design phase.\n\nMust work well with colleagues and customers to foster a highly creative, interesting, productive and fun working environment.\n\nOrganizational Skills: Ability to work well with internal cross functional teams. Must successfully and appropriately interface with external customers. Project management, time management, multi-tasking, problem solving and communication (written and oral) are important skills in this role. Must be able to manage assigned tasks with minimal supervision.\n\nTeam and People Skills: Candidate must be team oriented and must be able to work with TI-internal and external groups (systems, test, sales, marketing, customers, etc.) to resolve issues and generate business success. The ability to work well with others and to perform in a team environment is essential.\n\nProjects and Deliverables: The main deliverable is the timely release of meticulously analysed and simulated IC designs or sub-sections of designs for custom designs with tight schedules. These designs should lead to cost-effective, high quality, bug-free products that fully meet our customer’s end-system requirements.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Firmware Design and Validation Engineer – Sr Staff", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-13", "url": "https://careers.synopsys.com/job/bengaluru/firmware-design-and-validation-engineer-sr-staff/44408/99150952432", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years moving between RTL and bare metal firmware, and you know that the hardest problems show up where those two worlds meet. SerDes IP does not forgive sloppy handoffs or assumptions that worked on the last project, and you have learned to design with that reality baked in from day one. You understand that silicon bring-up is where theory meets the bench, and you are the kind of engineer who stays calm when the prototype does not behave like the simulation said it would.\nYou do not wait for perfect specs. You ask the right questions, align with mixed-signal teams, and find a path through ambiguity without creating more downstream. When a junior engineer gets stuck on a timing closure issue or a register map conflict, you can walk them through it without taking over, because you have been there and you remember what actually helped.\nYou care about documentation and process, not because someone told you to, but because you have seen what happens when firmware gets handed off without it. At Synopsys, you will work on SerDes products that ship into real customer SoCs, and the decisions you make during development will matter long after tapeout.\nWhat You'll Be Doing\nDesign, develop, and validate bare metal firmware for NRZ and PAM-based SerDes IP targeting high-speed data recovery and serialization circuits\nWork directly with mixed-signal design and verification teams to integrate firmware with analog and digital subsystems from spec through silicon bring-up\nExecute silicon bring-up on prototype test chips, diagnosing and resolving functional and performance issues between RTL behavior and actual hardware\nMentor junior firmware and digital design engineers on structured development flows, RTL debugging, and bring-up best practices\nDrive firmware development using structured processes including documentation, version control, and verification handoffs\nCollaborate with customer support and design groups to resolve integration issues and support SerDes IP deployment into customer SoCs\nLeverage AI tools like Cursor to accelerate development, debugging, and code quality without sacrificing rigor\nThe Impact You Will Have\nYour firmware will enable SerDes IP that powers high-speed interfaces in AI, automotive, and 5G applications shipping to customers globally\nThe bring-up work you lead will directly determine whether prototype test chips meet performance targets and move to production on schedule\nYour mentorship will shape how junior engineers approach firmware design, RTL integration, and silicon debugging across the team\nThe structured processes you help establish will reduce handoff friction between design, verification, and customer support teams\nYour ability to navigate ambiguity will keep projects moving even when specs evolve or silicon behaves unexpectedly\nThe documentation and design decisions you make will carry forward into next-generation SerDes products and customer deployments\nYour work will help Synopsys maintain its position as the broadest silicon IP provider in the industry\nWhat You'll Need\nBachelor's or Master's in Electrical Engineering or equivalent practical experience\n5+ years of hands-on experience in bare metal firmware development and silicon bring-up\nStrong digital design skills with deep understanding of RTL, synthesis, and timing closure\nDemonstrated ability to mentor engineers and provide technical leadership on complex projects\nExperience executing firmware projects from specification through silicon validation using structured development and verification processes\nAbility to work across design groups and customer support teams with clear, effective communication\nKnowledge of SerDes, Ethernet, or PCIe standards is a strong plus\nProficiency with AI tools like Cursor for accelerating development workflows is a plus\nWho You Are\nYou can explain a register map conflict to a mixed-signal designer in two sentences without losing the technical nuance\nWhen a prototype does not match simulation, you methodically isolate the issue rather than guessing or escalating prematurely\nYou balance design quality with deadlines, knowing when to push back and when to ship with documented trade-offs\nYou treat documentation as part of the deliverable, not an afterthought, because you have inherited undocumented firmware before\nYou are comfortable diving into unfamiliar territory, whether that is a new SerDes standard or a silicon bug that does not match any known pattern\nYou stay current with tooling and methods, including AI-assisted development, and apply them where they genuinely improve outcomes\n\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior Verification Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-13", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer_JR2023223", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nNVIDIA is seeking best-in-class Senior SoC/CPU Verification Engineer to verify the world's most powerful CPUs/Socswith AI capabilities for self-driving cars, gaming consoles & other automated machines (see NVIDIA Vera CPU and Arm Architecture | NVIDIA). NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to pursue, that only we can take on, and that matter to the world. We have crafted a team of excellent people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n\nWhat you’ll be doing:\nWork alongside brilliant engineers on NVIDIA's next generation CPU\n\nVerify micro-architecture/architecture features at unit level or subsystem or full chip testbenches including FPGA/Silicon\n\nPartner with CPU architects in crafting verifiable designs.\n\nWorking on full stack development - from verifying sequences at SW simulator level, to getting the overall end-to-end sequence working on silicon with a full SW stack.\n\nWhat we need to see:\nStrong verification fundamentals and are able to juggle working on SW simulators vs Silicon\n\nProficiency in CPU architecture (ARM knowledge is desirable), Coherent fabric designs, Verilog, System Verilog and possess strong debugging skills.\n\n3+ years of experience with Bachelors/Masters in Computer Science or Electronics Engineering or equivalent experience\n\nWays to stand out from the crowd:\nWorked on various pieces of CPU unit/microarchitecture verification, Interconnect, system memory coherency\n\nYou have worked on complex coverage driven verification projects\n\nExperience of collaborating with geographically diverse multi-functional teams\n\nWith competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most resourceful and versatile people in the world working for us and, due to outstanding growth, our best-in-class engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.", "jd_status": "stored"}, {"title": "Principal Digital Engineer (DFT Design)", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-12T14:43:58.135000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000143124658-principal-digital-engineer-dft-design-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "This is an opportunity to join a top-notch Power Management IC Team with Renesas leading Automotive Business Unit. You will be part of a very skilled group of engineers who are helping build world-class automotive PMIC products that will power tomorrow’s automobiles. You will design complex chips that includes various analog and digital control circuitry and work very closely with all aspects of chip design – from writing specifications to developing tests for mass production. You will be a key contributor to the digital DFT design team and work closely with the digital design team for meeting TEST requirements for Automobile and work closely with test engineering teams for validating the test patterns and meeting ASIL-B/D requirements. You will have an opportunity to work on new designs, insert Lbist and shape the company’s pathway for success. Your responsibilities, depending on your level of experience and skill level, will be a mix of the following:\nInserting DFT/Scan on digital logic, ATPG, validating test patterns on pre and post layout gate level netlist.\nDelivering test patterns to TEST engineering team and validating them on silicon.\nInserting Logicbist with industry standard tools.\nImproving scan coverage and modifying RTL for scan.\nReduce ATE tester time by reducing scan patterns while achieving the required coverage.\nParticipate in all aspects of digital design flow - Micro-architecture, Design partitioning, RTL Verilog / System Verilog coding, DFT insertion, generating Timing Constraints, Synthesis, Interaction with P&R Team, Timing Analysis, LINT, CDC.\nWorking closely with Architects, Design, P&R, Test and Silicon validation teams.\nAssisting with top level test-bench creation for scan and running gate level simulations.\nDebug scan pattern fails on ATE and fix the scan patterns.\nWriting detailed design documents and help writing DFT specifications, reviewing the specs with different stake holders and own the design to meet the spec.\nOrganizing and participating in key design reviews and completion of various checklists.\nWorking on-site for 3 days a week is a must.\n\nFollowing are rough guidelines for the qualifications (if you feel you have much more or somewhat less, let that not stop you from applying):\nRequired\nMasters plus 12+ years or Bachelors plus 15+ years experience in digital design and DFT implementation.\nMust be a team player and yet be an independent thinker with strong digital design and DFT fundamentals\nHands on experience in Scan insertion, improving scan coverage, ATPG, experience in Logicbist insertion during synthesis or rtl.\nGate level simulations with test patterns, delivering test patterns to Test engineering team and work closely with them to get the patterns validated. \nMust have basic digital RTL coding experience besides synthesis exposure.\nMust have experience with at least 8 tapeouts with hands on experience with DFT/Scan.  \nIdeal candidate will have solid understanding of synthesizable design, timing constraints and exceptions.\nMust have experience with industry standard Synopsys, Cadence, Mentor, Siemens for scan, Lbist insertion and ATPG. Tetramax experience is a huge plus.\nAttention to detail, accuracy and expertise in DFT required.\nMust have good written and verbal cross-functional communication skills\nHave an analytical mind - be open to new ideas and have capability to persuade others in convincing and implementing better flows and processes.\nDesirable\nMixed signal experience highly preferred.\nExposure to automotive test requirements, ASIL, is highly preferred.\nEducation\n• BSEE required (MSEE preferred) \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nRenesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.", "jd_status": "stored"}, {"title": "Principal Engineer , SOC Architect", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-12T10:47:15.107000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000143075919-principal-engineer-soc-architect", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "About Renesas India (India for India – IFI)\nRenesas continues to significantly expand its presence in India, with headcount approaching 1,000 and strong engagement across government, academia, and the broader semiconductor ecosystem. As India emerges as a strategic semiconductor market and a global talent hub, Renesas’ India for India (IFI) initiative is focused on creating differentiated products that address local market needs, while remaining globally competitive.\nThis role represents a rare opportunity to shape future silicon platforms from India—directly influencing product architecture, execution methodologies, and portfolio direction for a fast‑growing, strategically important market. The individual will play a pivotal role in defining end‑to‑end SoC solutions that serve India’s unique applications across automotive, industrial, infrastructure, and emerging domains.\nKey Responsibilities\nProduct & Portfolio Architecture\nWork closely with Business, Product Management, Sales, and Customers to define product portfolio strategy and translate market needs into clear SoC/MCU requirements.\nArchitect scalable SoC/MCU platforms, including detailed technical specifications and cost–benefit trade‑offs across architecture options, process nodes, IP reuse, and integration strategies.\nDefine–Own–Deliver SoC implementations that meet product KPIs, quality, cost, and schedule targets.\nEnsure end‑to‑end specification compliance across verification, validation, characterization, and production test, with rigorous review of outcomes prior to release.\nDrive paradigm shifts in SoC/MCU execution—covering team structures, tools, design methodologies, and processes—to enable high‑quality, first‑pass silicon.\nLead IP selection strategies, including make/buy decisions, third‑party IP evaluation, and long‑term platform reuse.\nCollaborate deeply with RTL design, Design Verification, Firmware/Software, Pre‑ and Post‑Silicon Validation, Test, and Program Management teams.\nEnable delivery of first‑pass functional silicon on aggressive and aspirational schedules through architectural rigor and execution discipline.\nEngage with external stakeholders, including IP vendors, EDA partners, foundries, and OSATs.\nRepresent Renesas at technical conferences, standards bodies, and ecosystem forums, contributing to thought leadership and technology direction.\nContribute to training program definition and rollout, mentor senior engineers, and drive systematic lessons‑learned and best‑practice sharing across teams and programs.\n\nQualifications & Experience\nStrong can‑do attitude, adaptability, and openness to diverse people, cultures, and working environments.\nEducational background in Electrical Engineering, Electronics Engineering, Computer Engineering, or Computer Science.\nHands‑on experience across key portions of the SoC development lifecycle, including:Front‑end architecture and RTL design\nVerification\nRTL‑to‑GDSII flow\nEmbedded software and system‑level integration\n\nBroad technical exposure across multiple domains such as Automotive, Multimedia, Networking, Compute, Computer Vision, and Software‑defined systems.\nProven ability to influence and coordinate across highly experienced, globally distributed cross‑functional teams.\nExcellent communication, problem‑solving, and technical leadership skills with a strong focus on quality and execution.\nM.Tech / B.Tech in Electrical Engineering or Computer Science with 12+ years of experience in SoC/MCU architecture and RTL design, including leadership across the full NPI lifecycle.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Staff Engineer ", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-08-12T09:35:13+00:00", "url": "https://jobs.infineon.com/careers/job/563808971831658", "is_hardware": true, "platform": "eightfold", "jd_text": "We are seeking a highly motivated Physical Design Engineer to drive the physical implementation and timing closure of complex, low-power SoCs targeted for the IoT and MCU markets. The ideal candidate will play a key role in achieving design objectives related to area, performance, and power while ensuring high-quality silicon implementation.\n\nYour role\nKey responsibilities in your new role :\n\nDrive physical design and timing closure activities for hierarchical blocks and full-chip SoC designs, meeting aggressive area, performance, and power (PPA) targets.\nOwn and execute various stages of the physical design flow, including:Floorplanning and I/O planning\nPackage co-design\nPower grid design\nPlacement and routing\nClock Tree Synthesis (CTS)\nTiming optimization and closure\nStatic and Dynamic IR drop analysis\nPhysical verification and signoff checks\n\nImplement and optimize low-power design methodologies, including designs with multiple voltage domains, power islands, and advanced power-reduction techniques.\nCollaborate closely with cross-functional teams to ensure seamless integration of package, design, and implementation requirements.\nDevelop, enhance, and drive physical design methodologies and automation flows to continuously improve Quality of Results (QoR), productivity, and design efficiency.\nAnalyze and resolve complex implementation challenges while ensuring design robustness, scalability, and manufacturability.\nContribute to best practices, technical innovations, and continuous improvements within the physical design organization.\nIdeal Candidate Profile\nStrong hands-on experience in end-to-end physical design and timing closure for advanced SoCs.\nDeep understanding of low-power implementation techniques, including multiple voltage and power domains.\nGood knowledge of I/O planning and package co-design considerations.\nProven ability to drive design closure and improve QoR through methodology and flow enhancements.\nSelf-driven, detail-oriented, and capable of working effectively in a collaborative team environment.\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor’s or Master’s degree in Electronics Engineering, Microelectronics, VLSI Design, or a related field.\nHands-on experience in SoC physical design, including floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure.\nStrong experience with industry-standard EDA tools for physical design, verification, and signoff.\nProficiency in scripting and automation using Shell, Perl, Tcl, and Make-based flows.\nSolid understanding of advanced semiconductor technology nodes (40nm, 28nm, and 22nm) and the associated physical design challenges.\nStrong analytical and problem-solving skills with the ability to identify, debug, and resolve complex design issues.\nDemonstrated commitment, ownership, and determination in delivering high-quality results within the area of expertise.\nWell-organized, methodical, and detail-oriented approach to work.\nProactive mindset with the ability to take initiative and overcome challenges through creativity and innovation.\nStrong team player with excellent collaboration and interpersonal skills.\nAbility to effectively coordinate with cross-functional teams and actively share knowledge and expertise with colleagues.\nExcellent communication skills with the ability to share information comprehensively, accurately, and effectively.\nPassion for continuous learning, professional development, and exploring new technologies and methodologies.\nExposure to low-power design methodologies and physical verification flows.\nExperience working in a fast-paced, collaborative semiconductor product development environment.\nAbility to drive design closure while meeting performance, power, area (PPA), quality, and schedule targets.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nAnand Rawal", "jd_status": "stored"}, {"title": "Senior Engineer - Low Power Design", "company": "Ericsson", "location": "Bangalore,Karnataka,India", "date_posted": "2026-08-12T08:17:24+00:00", "url": "https://jobs.ericsson.com/careers/job/563121776308109", "is_hardware": true, "platform": "eightfold", "jd_text": "Grow with us\n\nAbout this Opportunity\nJoin Ericsson's cutting-edge journey to shape the future of 5G networks! As a Low-Power Physical Design Engineer, you'll work on pioneering digital ASIC designs vital to Ericsson's mobile network infrastructure. Our team, responsible for the final critical stage of chip design before fabrication, thrives on Lean and Agile principles, promoting close collaboration, daily progress-sharing, and continuous improvement. If you're passionate about advanced technology and ready to make a meaningful impact in telecom, this role is crafted just for you.\nAt Ericsson, we support your growth, offering opportunities to advance your skills while contributing to game-changing 5G/6G technologies. Here, you'll find a supportive, innovative environment focused on quality, teamwork, and career development. Join us and help shape the future of telecom!\n\nWe are hiring a Low-Power Physical Design Engineer to own chip-level power estimation, analysis, and signoff using Synopsys PrimePower (PTPX) on high-performance, power-constrained SoC designs at advanced process nodes. You will define and drive power closure methodology, coordinate with RTL, physical design, and architecture teams to meet power budgets, and contribute to synthesis and STA flows as a secondary responsibility. This role is critical to the chip's power-performance story from early RTL through tape-out.\n\nWhat you will do:\n\nDynamic Power Analysis\n•    Own dynamic power analysis using Synopsys PrimePower (PTPX) across all design modes, workloads, and PVT corners.\n•    Generate, annotate, and validate switching activity files (SAIF / VCD) from RTL and gate-level simulations for accurate power estimation.\n•    Define representative workload scenarios and activity vectors for meaningful power measurement across use cases (active, idle, burst).\n•    Perform clock-domain-level, block-level, and full-chip dynamic power breakdowns; identify high-power contributors and drive optimization.\n•    Collaborate with RTL designers to implement low-power techniques — clock gating, operand isolation, fine-grained power gating — and verify their effectiveness in PTPX.\nStatic & Leakage Power Analysis\n•    Perform leakage power analysis across process corners and temperatures; validate multi-Vt cell usage and leakage reduction strategies.\n•    Analyze static power contribution from individual blocks and guide Vt optimization decisions in partnership with synthesis teams.\n•    Validate UPF/CPF power intent implementation — isolation cells, level shifters, retention registers — for correctness and power impact.\nPower Integrity & IR Drop\n•    Coordinate with physical design and package teams on static and dynamic IR drop analysis using Ansys RedHawk or Synopsys VoltageStorm.\n•    Analyze electromigration (EM) violations on power and signal nets; provide constraints and guidance to P&R for power grid fixes.\n•    Define power delivery network (PDN) requirements and validate against IR drop targets throughout the design cycle.\n•    Cross-correlate PTPX switching activity maps with IR drop hotspots to identify and resolve power integrity risks.\nPower Signoff & Methodology\n•    Define and own the power signoff checklist and sign-off criteria; lead power-related tape-out readiness reviews.\n•    Build and maintain power estimation flows for early-stage RTL power budgeting and architecture trade-off studies.\n•    Track power metrics across design milestones; produce detailed power reports for program management and architecture teams.\n•    Develop and document power analysis methodology, scripts, and best practices for reuse across projects and technology nodes.\n•    Engage with EDA vendors (Synopsys) to evaluate new PTPX features, resolve tool issues, and optimize flow runtime.\nSynthesis Support\n•    Assist synthesis team in reviewing QoR results from Design Compiler or Genus with a focus on power-aware optimization — multi-Vt assignment, clock gating inference, and operand isolation.\n•    Provide power-driven feedback on synthesis constraints and strategies; validate that low-power RTL coding practices translate correctly through synthesis.\n•    Review DFT-aware synthesis output to ensure scan and BIST insertion does not introduce unexpected switching activity or power overhead.\nStatic Timing Analysis Support\n•    Contribute to STA reviews using PrimeTime — specifically for timing paths affected by power optimization changes (clock gating, Vt swaps, buffer insertion).\n•    Validate that power-saving ECOs (gate sizing, Vt swaps) do not introduce timing regressions; flag and coordinate fixes with the STA team.\n•    Support MMMC corner coverage for power-vs-timing trade-off analysis at critical operating points.\n\nThe skills you bring:\n\n•    B.Tech / M.Tech / M.S. in Electronics Engineering, VLSI Design, Computer Engineering, or a related field with 10+ years in power analysis or low-power design roles\n•    Expert-level PTPX / PrimePower proficiency\n•    SAIF/VCD generation, annotation, and validation\n•    Strong understanding of dynamic, static, and leakage power dissipation mechanisms\n•    Experience with UPF/CPF multi-voltage design flows\n•    Familiarity with IR drop tools (RedHawk, VoltageStorm)\n•    Working knowledge of synthesis (Fusion Compiler)\n•    Basic STA familiarity (PrimeTime)\n•    Proficiency in Tcl; Python scripting a strong plus\n•    At least one tape-out on 7nm or below\n\nNice to Have\n\n•    Experience with architectural power modeling and early RTL estimation flows\n•    Familiarity with P&R tools (Innovus, ICC2) for power-driven implementation\n•    Knowledge of memory compiler power models and SRAM power characterization\n•    Background in package-level power delivery and PDN co-design\n•    Exposure to thermal analysis and junction temperature estimation\n•    Familiarity with power-aware formal verification flows\n•    Strong foundation in CMOS circuit theory, digital design, and power dissipation mechanisms (dynamic, short-circuit, leakage).\n•    Analytical mindset with a track record of identifying and resolving complex power issues across large, multi-million gate designs.\nEDA Tools & Environment\nSynopsys PTPX / PrimePower, Ansys RedHawk, VC-LP, Synopsys VoltageStorm, VCS / Questa (SAIF/VCD), Fusion Compiler, Design Compiler, PrimeTime, Tcl / Python\n\n.\n\n“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”\n\nWhy join Ericsson?At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.\n \nWhat happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.\n \nPrimary country and city: India (IN) || Bangalore\nReq ID: 786040", "jd_status": "stored"}, {"title": "Principal Engineer- Custom Layout (High-Speed Interface IP)", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-12T07:29:33.137000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000143040140-principal-engineer-custom-layout-high-speed-interface-ip-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Job Summary:\nWe are seeking an experienced Principal Custom Layout Engineer to lead the physical implementation of advanced high-speed analog and mixed-signal circuits for next-generation interface IPs. The successful candidate will be responsible for the layout design, floorplanning, optimization, and signoff of critical analog and mixed-signal blocks including DFE, CTLE, PLLs, CDRs, Transmitters, Receivers, DLLs, and SerDes subsystems. \nThe ideal candidate will have 15+ years of custom layout experience after completing a Master’s or Bachelor’s degree from a reputed university, with a proven record of delivering silicon-proven designs in advanced process nodes such as 5nm and 3nm. The candidate should be able to independently drive complex projects and mentor a team of 3–4 junior layout engineers. \nKey Responsibilities:\nLead the custom layout development of high-performance analog and mixed-signal IPs for advanced semiconductor products. \nIndependently drive complex custom layout projects from floorplanning through tapeout. \nOwn physical implementation for critical building blocks such as rCTLE, DFE, PLL, etc. \nDefine floorplanning strategies to achieve aggressive performance, area, power, and yield targets. \nPerform transistor-level and device matching-aware layouts using industry best practices. \nDrive physical verification and signoff activities, including DRC, LVS, ERC, PERC, density verification, and EMIR analysis. \nWork closely with Analog Design, Digital Design, SI, Packaging, and Product Engineering teams to ensure successful product execution. \nSupport silicon bring-up, debug, characterization, and production qualification activities. \nDevelop and institutionalize layout methodologies and best practices across the organization. \n\nB.Tech/M.Tech in Electrical Engineering, Electronics Engineering, VLSI Design, or related discipline from a reputed university. \n15+ years of industry experience in custom layout design. \nExtensive experience in custom layout of analog and mixed-signal circuits in advanced CMOS technologies. \nStrong understanding of:  \nAnalog layout fundamentals \nDevice matching techniques \nHigh-speed signal routing \nNoise coupling mechanisms \nParasitic extraction and optimization \nManufacturing process variations \nDemonstrated track record of delivering successful silicon in advanced technology nodes. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Staff Application Engineer - AMS Design", "company": "Infineon", "location": "Bangalore", "date_posted": "2026-08-12T06:44:05+00:00", "url": "https://jobs.infineon.com/careers/job/563808971829823", "is_hardware": true, "platform": "eightfold", "jd_text": "#WeAreIn to enable successful customer designs on the application level. Are you in?\n\nYour role\nKey responsibilities in your new role\nAs\na Senior Staff Engineer Analog Mixed Signal DAE, you will play a pivotal role\nin collaborating with team on next-generation automotive products, working\nclosely with cross-functional and international teams to deliver innovative\nsolutions.\n\nEnable project setup requirement for Design and systems for a wide range of applications such as configurations, design system, system clocking, data management along with tool licensing.\nApply engineering judgment and analysis methods to arrive at optimized solutions with a temporary work-around to ungate  the ongoing developments.\nDevelop block and product definitions, integration requirements, and verification requirements in collaboration  with cross-functional teams\nProvide support for test planning, silicon bring-up, characterization, and testing activities\nSupervise tool utilities,  layout activities related to block and chip design\nDeliver integration support into the design flow and cooperate with top-level integration\nPlay a role in the development of mixed signal     solutions for the next generation of automotive products\n\n \n\nYour profile\nQualifications and skills to help you succeed \n\nYou are a collaborative team player with\nexcellent communication skills who thrives in multicultural environments.\n\nBachelor's or Master's degree in Electrical Engineering, Computer Science, Physics, or in a related field\nAt least 8 years of relevant work experience in  mixed signal design support on architectures and application engineering  in these topics would be an advantage\nExperience with standard I/O interfaces (single ended and differential) is a plus\nGood understanding of custom layout techniques/ definitions for mixed-signal circuits, together with knowledge of ESD, latch-up, packaging, and PCB concepts and requirements, would be a plus\nGood understanding of Spectre simulation, mixed  signal design concepts in integration.\nBasic knowledge of safety standards like FUSA and applications such as ISO 26262 is a plus\nStrong intuitive and analytical understanding of transistor-level  design\nExperience designing most of the following blocks: ADCs, DACs, AFEs. \nExperience with an AFE+ADC subsystem is a plus\nTeam player with excellent listening, communication, and  organizational skills\nAbility to organize and prioritize work for yourself and others\nStrong tools knowledge  on Virtuoso,Spectre,Cadence Xcelium ,ADE\nVerifier, vManager\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nGowri Shenoy\nGowri.Shenoy@infineon.com\n\nhttps://www.linkedin.com/in/gowri-shenoy-33894217/", "jd_status": "stored"}, {"title": "Senior Staff Engineer – Analog/Mixed-Signal Design ", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-12T06:28:06.479000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000143032679-senior-staff-engineer-analog-mixed-signal-design-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking an experienced Senior Staff Engineer – Analog/Mixed-Signal Design with 10+ years of expertise in transistor-level analog IC design and a strong foundation in analog circuit design fundamentals. The ideal candidate has a proven track record of architecting, designing, integrating, and delivering complex analog IPs and mixed-signal subsystems from concept through production. Experience developing power management ICs is a plus.\nAs part of Renesas' $2.6B Power Business Unit, you will help develop next-generation analog and mixed-signal solutions for multi-phase controllers and power management products that enable AI infrastructure and hyperscale computing platforms.\nKey Responsibilities\nArchitect, design, own, and deliver high-performance analog and mixed-signal IPs, including:Source/sink LDOs\nPositive and negative charge pumps\nRelaxation and other oscillator architectures\nTemperature sensors\nCurrent-sense circuits\nSAR ADCs\nProtection circuits (UVLO, OVLO, OCP, thermal protection, etc.)\nCore analog building blocks, including bandgap references, operational amplifiers, comparators, analog buffers, V-to-I converters, and high-speed level shifters\n\nDrive innovative circuit architectures and design optimizations to meet challenging performance, power, area, yield, and reliability targets.\nLead analog IP development through the complete product lifecycle—from architecture and transistor-level implementation through silicon validation, production qualification, and manufacturing support.\nCollaborate closely with layout engineers from floorplanning through chip-level integration, ensuring optimal analog layout, parasitic-aware design, and performance trade-offs.\nDevelop and optimize simulation methodologies across pre- and post-layout verification, balancing simulation accuracy, convergence, runtime, and debugging efficiency.\nEstablish and drive robust analog design methodologies, review processes, and quality checklists to maximize first-pass silicon success.\nDefine and review chip-level ESD, latch-up, and I/O protection strategies to ensure product robustness and reliability.\nMentor junior engineers and foster a culture of technical excellence across the team.\nLead or manage a small team of engineers, driving execution, mitigating technical risks, and delivering high-quality silicon on schedule.\n\nMinimum Qualifications\nBachelor's or Master's degree in Electrical Engineering or a related discipline.\n10+ years of hands-on experience in analog and mixed-signal IC design.\nDemonstrated ownership of complex transistor-level analog IP from specification through silicon validation.\nStrong understanding of:Analog circuit design fundamentals\nSemiconductor device physics and transistor-level design\nProcess corners, Monte Carlo analysis, mismatch, and noise\nExtraction, post-layout simulation, and parasitic optimization\nAnalog layout techniques and layout-dependent effects (LDE)\nESD, latch-up, and chip-level reliability considerations\n\nProven experience across the complete IC development lifecycle, including architecture, design, verification, silicon bring-up, debugging, qualification, and production support.\nStrong technical leadership, mentoring, communication, and cross-functional collaboration skills, with a passion for building high-performing engineering teams.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Analog/Mixed-Signal Layout Engineer - SERDES", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-08-12T03:51:00+00:00", "url": "https://global-external-amd.icims.com/jobs/90066/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. THE ROLE: As a member of SERDES Group, you will help develop layout designs. As a member of the team, you will work closely with the architecture, IP design, Physical Design teams to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Implementation Layout of blocks and macros Own and deliver the high-quality macros with help of team Mentor and groom the juniors in the team Work with contractor team and the planned work done as per aligned schedule Enable release flows as required PREFERRED EXPERIENCE: 15+ yrs of hands-on experience in layout design Experience with Cadence virtuoso, Caliber and other verification tools as required for layout development Preferrable experience in high speed SERDES blocks ACADEMIC CREDENTIALS: Bachelors or Masters degree in Electrical Engineering or equivalent #LI-PK2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "CPU RTL Power Engineer (Sr Staff/Principal)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-12T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720255539", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nWe are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for mobile space.\n\nJob Description:\nParticipate on a project involved in the development of ASICs, low power concepts, .\n\nlow Power checks, timing and power analysis.\n\nCreate design of experiments and do detailed comparison analysis to improve quality of results.\n\nWork closely with RTL design, physical design, low power and automation teams to optimize performance and power\n\nTabulate metrics results for analysis comparison\n\nBachelor's/Master’s degree in Science, Engineering, or related field.\n\nRequirements:\n12+ years Low power design understanding and low power checks working knowledge,Primetime/Primepowe,Synthesis/Constraints, Signoff STA, or related work experience.\n\nExtensive experience in Primetime/ptpx, PowerArtist, Synthesis with DCT/DCG or RC/RCP..\n\nComplete ASIC flow with low power, performance and area optimization techniques\n\nExperience with STA using Primetime and PTPX required\n\nExperience of multiple power domain understanding with complex UPF/CPF definition required\n\nPerl/Tcl scripting is required\n\nStrong problem solving and ASIC development/debugging skills\n\nExperience with CPU micro-architecture and their critical path\n\nHigh speed CPU implementation\n\nPlace and route tool understanding\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RTL Design Engineer, Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-12T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720358909", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Description - 5+ year RTL designer\n\nWe are looking for a highly motivated RTL Design Engineer with 5+ years of experience in front-end ASIC/SoC design. The candidate will be responsible for micro-architecture development, RTL implementation, and quality signoff activities including Lint and CDC analysis. Experience with synthesis and timing constraints development is highly desirable. The role involves close collaboration with architecture, verification, DFT, and physical design teams to deliver high-quality silicon.\n\nKey Responsibilities\n·                     Develop detailed micro-architecture specifications from high-level architectural requirements.\nDesign and implement synthesizable RTL using Verilog/SystemVerilog.\nParticipate in design reviews and ensure design quality and compliance with coding guidelines.\nPerform RTL quality checks including:\no        Lint analysis and cleanup\nCDC/RDC analysis and closure\nFSM and structural checks\n\nDevelop and maintain design documentation including micro-architecture and interface specifications.\nWork closely with verification teams to define verification plans and resolve functional issues.\nSupport synthesis, timing analysis, and timing closure activities.\nDevelop and review SDC constraints for block-level and subsystem-level designs.\nAnalyze and debug issues across simulation, synthesis, and implementation stages.\nCollaborate with DFT and physical design teams for successful integration and tapeout.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nRequired Qualifications\n·                     Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field.\n5+ years of experience in ASIC/SoC front-end design.\nStrong knowledge of digital design fundamentals.\nHands-on expertise in:\no        RTL design using Verilog/SystemVerilog\nMicro-architecture definition and documentation\nLint tools (SpyGlass, Questa Lint, or equivalent)\nCDC/RDC tools (SpyGlass CDC, Questa CDC, or equivalent)\n\nGood understanding of clocking architectures, reset strategies, and low-power design concepts.\nExperience debugging RTL and simulation issues.\nPreferred Qualifications\n·                     Experience with synthesis flows using Design Compiler, Genus, or equivalent tools.\nExperience creating and reviewing timing constraints (SDC).\nUnderstanding of timing analysis concepts including setup/hold, clock domain crossings, and timing closure.\nExposure to DFT methodologies and integration.\nKnowledge of low-power design techniques (UPF/CPF).\nExperience with complex SoC/IP development and integration.\nDesired Skills\n·                     Strong analytical and debugging skills.\nExcellent written and verbal communication.\nAbility to work independently and drive block ownership.\nStrong collaboration skills across architecture, verification, and physical design teams.\nNice to Have\n·                     Experience working on high-performance CPU, DSP, AI/ML, networking, multimedia, or connectivity IPs.\nScripting knowledge in Python, Perl, or TCL for automation and flow enhancement.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU RTL Power Engineer (Senior/Lead/Staff)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-12T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720255529", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nWe are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for mobile space.\n\nJob Description:\nParticipate on a project involved in the development of ASICs, low power concepts, .\n\nlow Power checks, timing and power analysis.\n\nCreate design of experiments and do detailed comparison analysis to improve quality of results.\n\nWork closely with RTL design, physical design, low power and automation teams to optimize performance and power\n\nTabulate metrics results for analysis comparison\n\nBachelor's/Master’s degree in Science, Engineering, or related field.\n\nNote : References to a particular number of years’ experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfil the principal duties of the role and possesses the required competencies.\n\nRequirements:\n3 - 10years Low power design understanding and low power checks working knowledge, Primetime/Primepower , Synthesis/Constraints, Signoff STA, or related work experience.\n\nExtensive experience in Primetime/ptpx, PowerArtist, Synthesis with DCT/DCG or RC/RCP..\n\nComplete ASIC flow with low power, performance and area optimization techniques\n\nExperience with STA using Primetime and PTPX required\n\nExperience of multiple power domain understanding with complex UPF/CPF definition required\n\nPerl/Tcl scripting is required\n\nStrong problem solving and ASIC development/debugging skills\n\nExperience with CPU micro-architecture and their critical path\n\nHigh speed CPU implementation\n\nPlace and route tool understanding\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RTL Design Engineer, Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-12T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720358940", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Description - 5+ year RTL designer\n\nWe are looking for a highly motivated RTL Design Engineer with 5+ years of experience in front-end ASIC/SoC design. The candidate will be responsible for micro-architecture development, RTL implementation, and quality signoff activities including Lint and CDC analysis. Experience with synthesis and timing constraints development is highly desirable. The role involves close collaboration with architecture, verification, DFT, and physical design teams to deliver high-quality silicon.\n\nKey Responsibilities\n·                     Develop detailed micro-architecture specifications from high-level architectural requirements.\nDesign and implement synthesizable RTL using Verilog/SystemVerilog.\nParticipate in design reviews and ensure design quality and compliance with coding guidelines.\nPerform RTL quality checks including:\no        Lint analysis and cleanup\nCDC/RDC analysis and closure\nFSM and structural checks\n\nDevelop and maintain design documentation including micro-architecture and interface specifications.\nWork closely with verification teams to define verification plans and resolve functional issues.\nSupport synthesis, timing analysis, and timing closure activities.\nDevelop and review SDC constraints for block-level and subsystem-level designs.\nAnalyze and debug issues across simulation, synthesis, and implementation stages.\nCollaborate with DFT and physical design teams for successful integration and tapeout.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nRequired Qualifications\n·                     Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field.\n5+ years of experience in ASIC/SoC front-end design.\nStrong knowledge of digital design fundamentals.\nHands-on expertise in:\no        RTL design using Verilog/SystemVerilog\nMicro-architecture definition and documentation\nLint tools (SpyGlass, Questa Lint, or equivalent)\nCDC/RDC tools (SpyGlass CDC, Questa CDC, or equivalent)\n\nGood understanding of clocking architectures, reset strategies, and low-power design concepts.\nExperience debugging RTL and simulation issues.\nPreferred Qualifications\n·                     Experience with synthesis flows using Design Compiler, Genus, or equivalent tools.\nExperience creating and reviewing timing constraints (SDC).\nUnderstanding of timing analysis concepts including setup/hold, clock domain crossings, and timing closure.\nExposure to DFT methodologies and integration.\nKnowledge of low-power design techniques (UPF/CPF).\nExperience with complex SoC/IP development and integration.\nDesired Skills\n·                     Strong analytical and debugging skills.\nExcellent written and verbal communication.\nAbility to work independently and drive block ownership.\nStrong collaboration skills across architecture, verification, and physical design teams.\nNice to Have\n·                     Experience working on high-performance CPU, DSP, AI/ML, networking, multimedia, or connectivity IPs.\nScripting knowledge in Python, Perl, or TCL for automation and flow enhancement.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Physical Design Engineer, Sr Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-12T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720367724", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nExperience:\n12+ years of experience in Physical Design, including floorplanning, Place & Route (PNR), Clock Tree Synthesis (CTS), and STA signoff checks\nHands-on experience owning end-to-end Physical Design from netlist to GDSII, including HM-level PV, LEC, low-power checks, PDN design, and STA closure\nExperience with voltage islands and low-power design methodologies, flows, and implementation\nStrong focus on achieving optimal PPA (Power, Performance, Area)\nStrong familiarity with industry-standard tools such as Fusion Compiler (FC), Genus, Innovus, , PrimeTime (PT), Tempus, Voltus, and RedHawk\nSolid understanding of the full Physical Design flow from floorplanning to post-route optimization and timing signoff, including IR drop analysis and physical verification\nExperience in implementing complex ECOs for timing convergence across multiple corners using Tweaker, Tempus, and physical ECO flows in PrimeTime\nKnowledge of power optimization techniques and methods to minimize power consumption\nExperience in deep submicron technology nodes (preferred)\nUnderstanding of high-performance and low-power implementation techniques (preferred)\nStrong fundamentals in Physical Design and VLSI concepts\nProficiency in scripting languages such as Perl, Python and TCL\nRoles and Responsibilities\nCollaborate with cross-functional teams (Design, CAD) to address critical physical design challenges in Camera PNR Implementation.\nDevelop innovative techniques within Physical Design and optimization space to meet stringent PPA targets.\nEngage with external CAD tool vendors and internal CAD teams to identify and enhance optimization issues related to Camera designs.\nPartner with all block-level implementation teams to analyze, implement, and improve optimization methods relevant to the designs.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "HSIO Characterization Engineer, Senior", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-12T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718165543", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nThe BDC HSIO Post Silicon Engineering group has an opening for a Digital Bench Characterization Engineer.\nAs part of the HSIO Post Silicon Engineering group, you will be responsible for bench characterization of leading-edge LPDDR & PCDDR subsystem components (DRAM, DRAM Controller, DRAM PHY, IOs, PLL/DLL, Clocking architecture, Delay circuits, Power Distribution Network) and high-speed IO interfaces (PCIe, USB2/3/4, DisplayPort, HDMI, MIPI-CSI/DSI, UFS & PLL).\nYou will:\nEvaluate parametric performance of DDR & High-Speed IO IPs\nPerform failure analysis to root-cause design problems\nYou’ll work closely with IC design engineering, system engineering, and hardware applications teams across the globe in a time-critical environment.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nQualifications\nM.Tech, B.Tech, or equivalent in Electronics or Electrical Engineering\n3 years of related work experience\nSkills & Knowledge\nFamiliarity with test and characterization of DDR and High-Speed IO interfaces\nIn-depth understanding of:\nMobile & PC DDR protocols (DDR2/3/4), timing diagrams\nHSIO IPs at PHY level\nElectrical parametric compliance specs (eye diagram, differential signaling, jitter analysis, Receiver-Jitter-Tolerance, signal integrity, transmission line considerations, de-embedding)\nDecent understanding of VLSI technologies, analog/digital ICs, and semiconductor physics\nHands-on experience with bench instruments (oscilloscopes, BERT, network/spectrum analyzers, signal generators, logic analyzers) is a plus\nProgramming skills: Python, C, C# (or equivalent)\nSoft Skills\nStrong interpersonal, problem-solving, and debugging skills\nAbility to work effectively in a fast-paced environment\nExcellent verbal and written communication skills\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "AV&V Manager", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-08-12", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25017068", "is_hardware": true, "platform": "oracle", "jd_text": "We are at a pivotal moment where technology is rapidly evolving, and we have some exciting opportunities within our MCU organization that place us right at the center of this transformation.\n\n Our current work is focused on developing solutions for high-growth markets such as AI-driven data centers and emerging domains like humanoid systems. These areas are shaping the future of computing, automation, and intelligent systems, and offer a unique chance to work on cutting-edge technologies with real-world impact.\n\n If you are passionate about solving complex technical challenges and want to contribute to innovations in these fast-growing segments, I encourage you to come forward and apply. This is an opportunity to be part of a journey that is not only technically rewarding but also strategically significant.\n\n Looking forward to seeing many of you take this step.\n\nRole Title: AV&V Manager\n\nRole Summary: Own end-to-end functional validation activities of the first T28 industrial ASIC for the ASM Industrial business. This role combines AV&V team ownership with functional team leadership, flawless post-silicon execution, FPGA prototyping, and hardware emulation to ensure our highly differentiated products meet the highest quality standards.\n\nWhat you will gain from this role:\n\n• Lead SoC Validation, FPGA & Emulation for cutting-edge wireless connectivity devices.\n\n• Global Exposure: Opportunity to interact with world-wide teams for FPGA prototyping, emulation, post-silicon validation, and system integration.\n\n• Strategic Impact: Identify, define, and drive advanced methodologies to improve the quality, coverage, and efficiency of FPGA prototypes, hardware emulation, and post-silicon validation.\n\n \n\nKey Responsibilities:\n\nTeam Leadership: Drive results, manage execution timelines, and own the career growth and mentorship of the complete AVnV ( Functional Validation), FPGA, and Post-Silicon Validation team.\n\nFPGA Prototyping & Emulation: Drive SoC prototyping and validation strategies using high-performance platforms, specifically FPGA (e.g., Xilinx/AMD, Intel) and Palladium hardware emulation environments.\n\nSilicon Bring-up: Lead the planning and execution of post-silicon bring-up, functional validation, and characterization activities across temperature and voltage corners.\n\nBoard-Level Concepts: Architect, review, and oversee the development of complex validation boards, custom FPGA prototyping boards, reference platforms, and test fixtures required for silicon evaluation.\n\nCross-Functional Debug: Interact heavily with Test, Software/ROM, Application Engineering, and Analog Design teams to isolate, root-cause, and debug complex silicon bugs using both lab equipment and FPGA/Emulation trace environments.\n\nInfluence & Governance: Participate in and conduct rigorous hardware design reviews, board schematic reviews, and post-silicon/FPGA readiness gates.\n\nMethodology Innovation: Innovate and drive improved validation methodologies and automation frameworks, collaborating with EDA and instrument vendors to upgrade lab tools, FPGA synthesis/mapping tools, and emulation flows.\n\nQualifications\nMinimum Qualifications:\n\nEducation: Bachelor’s or Master’s degree in Electrical / Electronics Engineering.\n\nExperience: Minimum of 8+ years of experience in semiconductor validation and prototyping, with a proven track record of managing or leading engineering teams.\n\nTechnical Depth: Strong understanding of board-level hardware concepts, high-speed signal integrity, lab equipment (oscilloscopes, logic analyzers), FPGA prototyping workflows, and emulation platforms (Palladium).\n\nLeadership Skills: Ability to drive results from the team even without having complete command of a specific domain.\n\nStakeholder Management: Ability to establish strong relationships with key stakeholders critical to success, both internally and externally.\n\nSoft Skills: Strong verbal/written communication, time management, analytical problem-solving, and a result-driven attitude to handle dynamically evolving requirements.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Layout Design Manager", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-08-12", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25017063", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\nTexas Instruments is seeking Analog Layout Design Manager. In this role, you will direct the activities of the layout design function involving the layout of complex integrated circuits. You may also ensure circuits conform to design rules and circuit schematics. You will also be responsible for the storage of circuit documentation and developing computer design rule checks. An additional job function may involve the selection of mask vendors. As a Layout Design Manager, you may also select, develop and evaluate personnel to ensure the efficient operation of the function.  Switching Regulators and high voltage combination, challenges the layout skills/problem solving and is extremely important for the 1st pass silicon success.\n\nQualifications\nMinimum requirements:\n\nMinimum education - Bachelor's degree in electrical/electronic/related engineering\n\nMinimum of 8 years of experience\n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Project Manager Design", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-08-11T06:45:20+00:00", "url": "https://jobs.infineon.com/careers/job/563808971792095", "is_hardware": true, "platform": "eightfold", "jd_text": "Must have experience in SoC/ASIC product cycles and understanding of architecture, integration, validation, and silicon bring-up phases. \n\nYour role\nKey responsibilities in your new role\n\nBring\nstrong execution discipline, structured project management, and\ncross-functional leadership. \n\nPartner with Chip Lead, Analog Designers, IP owners, RTL, PD, DFT, firmware, Testing, validation, and Product \n\nEngineering to drive convergence, resolve dependencies, and maintain schedule integrity. \nUnderstand system-level architecture, Chip integration challenges, milestones (e.g., architecture, Analog & Digital design, physical design readiness, validation readiness, Pre silicon Verification, and tape out) and the full lifecycle of complex Power IC program, with the ability to drive alignment across geographically distributed teams. \nEnsure execution is on time, within cost, meet Infineon Quality Standards and manage scope changes.\n\nYour profile\nQualifications and skills to help you succeed \n\nMust\nhave experience in SoC/ASIC product cycles and understanding of architecture,\nintegration, validation, and silicon bring-up phases. \nStrong\nfamiliarity with SoC / IP execution flows: \nArchitecture\nto tape out and Fab to Production Release \nIP\nintegration and dependency management \nPre-silicon\nand post-silicon execution flows \nSystem-level\nbring-up and platform readiness\nDetail-oriented,\nself-driven with a strong sense of pride and ownership. \nProficiency\nin project management tools (JIRA, Confluence, Excel, MS Project, AI tools). \nStrong\norganizational, problem-solving, interpersonal, presentation, written and\nverbal communication skills. \nAbility\nto build relationships and work effectively as a self-starter and as part of a\nteam. \nPrior\nexperience driving large multi-site or multi-vendor engagements is desirable. \nExcellent\nverbal and written communication skills to handle all levels of interaction,\nincluding executive level. \nHorizontal\nleadership/Matrix management experience. \nQualification : Engineering\ndegree in Electronics, master’s degree is preferred \nTotal\n10-15 Years of Semiconductor Industry experience \n5+\nYears of Soc/ASIC Project manager experience, managing the multisite , multi-million\ndollar project execution \n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nVidhi Thakkar", "jd_status": "stored"}, {"title": "STA Engineer - CPU Team", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-08-11T05:46:00+00:00", "url": "https://global-external-amd.icims.com/jobs/88434/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Senior SILICON DESIGN ENGINEER    THE ROLE: AMD is seeking an experienced **Static Timing Analysis (STA) Engineer** to join our high-performance Cores team. This role will be responsible for ensuring timing closure and optimization of next-generation CPU/APU designs operating at industry-leading frequencies. The ideal candidate will have deep expertise in STA methodologies, timing marginings, and yield analysis for advanced process nodes. THE PERSON:  As an STA Engineer in the AMD Cores team, you will play a critical role in delivering high-frequency, power-efficient processor designs that push the boundaries of performance. You will work closely with RTL design, physical design, and verification teams to ensure robust timing closure across multiple process corners and operating conditions.   KEY RESPONSIBILITIES:  2+ years of experience in Static Timing Analysis for high-performance digital designs 2+ years** working on CPU, GPU, or high-frequency ASIC designs Proven track record of leading timing closure for complex SoCs through multiple tapeouts Timing Closure & Analysis Lead static timing analysis for high-frequency CPU/APU cores running at 4+ GHz Perform comprehensive timing signoff across all PVT corners (SS, TT, FF, FS, SF) and voltage/temperature combinations Drive timing closure from RTL freeze through tapeout, ensuring all setup, hold, and transition violations are resolved Develop and maintain timing constraints (SDC) for complex clocking architectures including multi-mode, multi-corner scenarios Analyze and optimize critical paths to achieve frequency targets while minimizing power impact Perform timing ECO (Engineering Change Orders) and coordinate with physical design teams for implementation Timing Marginings & Variability Analysis Define and implement timing margins for process variation, voltage droop, aging, temperature gradients, and OCV (On-Chip Variation) Conduct **statistical timing analysis (STA/SSTA)** to account for process variation and ensure robust yield Perform **AOCV/POCV/SOCV** analysis for advanced nodes (5nm, 3nm and beyond) Develop methodologies for **IR drop analysis** and voltage-aware timing closure Analyze **aging effects** (NBTI, HCI, EM) and define appropriate timing guardbands Work with characterization teams to define **derating factors** and timing models Yield Analysis & Optimization Collaborate with yield engineering teams to analyze timing yield and identify sensitivities Perform path-based analysis (PBA) and graph-based analysis (GBA) to reduce pessimism Conduct Monte Carlo simulations and corner analysis to ensure robust timing across process spread Identify and optimize timing-critical structures to improve manufacturability Drive binning strategies based on frequency and voltage guardband analysis   PREFERRED EXPERIENCE:  Physical Design Exposure Physical design experience (synthesis, place & route, or timing closure) Understanding of placement optimization for timing improvement Knowledge of routing impacts on timing (via count, metal layer selection, wire models) Experience with floorplanning and its impact on timing Familiarity with physical design tools: Synopsys Fusion Compiler, Cadence Innovus/Genus Understanding of buffer insertion and gate sizing strategies Knowledge of pin assignment and I/O timing closure Clock Tree Synthesis (CTS) Recipes Experience **defining CTS recipes** and specifications for clock tree builders Deep understanding of **CTS algorithms**: H-tree, X-tree, fishbone, mesh Knowledge of **clock buffer selection** and sizing for skew/latency optimization Experience with **useful skew** implementation and optimization Understanding of **clock concurrent optimization (CCOpt)** Familiarity with **clock tree QoR metrics**: insertion delay, skew, transition, power Additional Preferred Skills Experience with **Synopsys tools**: Design Compiler, IC Compiler II, PrimeTime SI/PX Knowledge of **machine learning** applications in timing prediction and optimization Familiarity with **FinFET** and **Gate-All-Around (GAA)** transistor timing characteristics Understanding of **3D IC** and chiplet-based timing analysis Experience with **timing correlation** studies between STA and SPICE Knowledge of **standard cell characterization** and timing library generation   ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-RR1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Product Applications Engineer", "company": "Analog Devices", "location": "India, Bangalore, Nova", "date_posted": "2026-08-11", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-Nova/Senior-Product-Applications-Engineer_R264605-1", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nSenior Engineer, Product Applications (P3)\nJob Summary\nThe Product Applications Engineer will support the evaluation, characterization, validation, and customer enablement of Analog Devices' mixed-signal semiconductor solutions. Working closely with Design, Systems, Product Marketing, and Customer teams, the engineer will develop reference designs, create technical collateral, investigate product and customer issues, and deliver system-level application support.\n\nAt Analog Devices, we are accelerating innovation across energy infrastructure and next-generation data centres through industry-leading sensing, power monitoring, connectivity, and edge intelligence solutions. Our technologies enable smarter energy meters, intelligent circuit breakers, power distribution units (PDUs), data centre power delivery networks, and grid modernisation systems, helping customers improve energy efficiency, reliability, and sustainability.\nLearn more:\n•https://www.analog.com/en/markets/energy.html\n•https://www.analog.com/en/markets/data-center.html\n•https://www.analog.com/en/about-adi.html\n\nThe ideal candidate combines strong hardware and software skills with hands-on laboratory experience and the ability to independently solve complex technical challenges while contributing to product success and customer satisfaction.\nKey Responsibilities\n•Evaluate, characterize, and validate semiconductor products, reference platforms, and system-level solutions.\n•Develop customer-facing application collateral, software tools, reference designs, and demonstration platforms.\n•Support customers and field application teams in resolving technical issues and driving successful product adoption.\n•Collaborate with cross-functional teams throughout the product development lifecycle, including Design, Systems Engineering, Product Marketing, Quality, and Manufacturing.\n•Drive root-cause analysis, debugging, characterization, and performance optimisation activities.\n•Develop automated test and validation solutions using scripting and software tools.\n•Contribute to technical reviews, documentation, and knowledge-sharing initiatives.\n•Support new product introduction activities, silicon bring-up, and validation efforts.\n\nKey Qualifications\n•M.S./M.Tech./B.E./B.Tech. in Electrical Engineering, Electronics Engineering, Electronics & Communication Engineering, or a related engineering discipline with 5+ years of industry experience.\n•Hands-on experience in one or more of the following application domains:\n •Smart Energy Meters\n •Intelligent Circuit Breakers\n •Power Distribution Units (PDUs)\n •Data Centre Power Delivery Networks\n •Power Monitoring and Energy Management Systems\n•Strong understanding of mixed-signal systems, embedded systems, power electronics, energy metering, or industrial measurement applications.\n•Proficiency in C and Python.\n•Hands-on experience in hardware design, development, debugging, validation, and system bring-up.\n•Familiarity with standard laboratory test and measurement equipment, including oscilloscopes, logic analyzers, spectrum analyzers, signal generators, source measurement units (SMUs), power analyzers, electronic loads, and digital multimeters.\n•Experience in product characterization, performance evaluation, and root-cause analysis.\n•Knowledge of communication interfaces such as SPI, I²C, UART, and other embedded peripherals.\n•Strong analytical, troubleshooting, and problem-solving skills.\n•Excellent verbal and written communication skills.\n•Proficient in English.\n\nPreferred Qualifications\n•Experience with energy metering, power quality monitoring, grid modernisation, or utility automation systems.\n•Familiarity with metrology algorithms, ADC signal chains, calibration techniques, and sensor interfaces.\n•Experience with ARM-based processors, microcontrollers, and embedded firmware development.\n•Knowledge of power monitoring architectures used in hyperscale and enterprise data centres.\n•Experience developing customer-facing reference designs, evaluation platforms, and technical documentation.\n•Familiarity with IEC, ANSI, and other industry standards related to measurement, metering, and power quality.\n\nWhy Join ADI?\nAt Analog Devices, you will work with world-class engineers developing technologies that power the future of energy infrastructure and AI-driven data centres. From enabling accurate energy measurement and intelligent power distribution to improving power efficiency at scale, you will help create innovative solutions that have a meaningful impact on how the world generates, distributes, and consumes energy.\nThis role offers the opportunity to work across hardware, software, systems, and customer applications while contributing directly to products deployed in millions of devices worldwide.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Senior Post Silicon HSIO Bringup Lead", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-11", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Post-Silicon-HSIO-Bringup-Lead_JR2016435", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people.\nToday, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.\nWe seek hardworking, motivated, and imaginative individuals to join our High Speed IO (HSIO) post silicon validation team. As the lead engineer, you will own post-silicon validation and support new hardware bring-up. This role offers firsthand experience in developing and productizing reliable HSIO interfaces for GPU accelerated computing platforms, next generation client and automotive systems.\n \nWhat you'll be doing:\nOwn HSIO (PCIe, CXL, and NVLink) validation on FPGA/Emulator and Silicon, including test plan development, board building for validation requirements, resource planning, automation, test execution, coverage metrics, bug resolution, and release to production.\n\nCoordinate with internal and external logic, circuit, boards, simulation, diagnostics, firmware, driver, and marketing teams across different time zones. Ensure our products are tested against and meet specifications, are tuned for efficient workload performance. Drive the system into production.\n\nParticipate in reviewing board schematics, PCB layouts, and making build and component suggestions. Ensure interoperability with connected devices and system components in sophisticated interconnect topologies.\n\nProvide engineering support during manufacturing in both NPI and MP stages of production.\n\nInfluence pre-silicon development and verification methodologies, workflows based on issues observed and debugged on silicon to achieve outstanding HSIO products.\n\nWhat we need to see:\nBS or B.Tech or MS or M.Tech in EE, ECE, CS, or equivalent degree with 7+ years or more experience in HSIO validation.\n\nComprehensive understanding of the HSIO protocols (including PCI Express, Infiniband, Ethernet), its specifications, and its operation at a system level.\n\nStrong knowledge of lab instruments (DSOs, BERT, Protocol/Logic analyzers) and hands-on experience in Post-Si bring-up, functional validation, troubleshooting, and tuning of HSIO interfaces. Proficient with logic and protocol analyzers, along with protocol exercisers.\n\nOutstanding verbal and written communication skills. Proficient in collaborating across geographically distributed teams and suppliers to deliver quality products on tight schedules.\n\nHands-on experience of developing workflows and coding in scripting languages like Python would be helpful.\n\nWays to stand out from the crowd:\nProven leadership experience in PCI Express physical layer and debugging LTSSM failures; familiarity with data link layer, transaction layer and CXL.\n\nExtensive knowledge of characterization techniques in post-silicon settings. Excellent knowledge of signal integrity concepts, silicon characteristics, and high-speed/SERDES functional validation.\n\nFamiliarity with x86/Arm server architectures and latest accelerated computing server architecture is required. Experience with datacenter products including system management, security, networking, and storage would be a plus.\n\nWorking exposure on working with AI tools (like Claude or Cursor) would be highly desirable\n\nWe have some of the most experienced and dedicated people in the world working at NVIDIA. If you're creative and independent, with a genuine passion for technology, we want to hear from you. Join us and be part of something outstanding!\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.\nWidely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "ASIC Digital Design, Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-11", "url": "https://careers.synopsys.com/job/bengaluru/asic-digital-design-staff-engineer/44408/95703467168", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:\n At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\n \nYou Are:\n You are a passionate and detail-oriented ASIC Digital Design professional who thrives in high-tech, fast-paced environments. With a strong foundation in Design-for-Testability (DFT) methodologies, you enjoy taking ownership of complex challenges and delivering reliable, high-quality results. You are eager to collaborate with diverse, global teams and are driven by a desire to continuously learn and grow within the semiconductor industry. Your expertise in scan insertion, ATPG, and scan STA is matched by your ability to adapt to new tools and technologies. You value open communication, inclusivity, and knowledge sharing, and you excel at translating intricate technical concepts into actionable solutions. As a proactive problem solver, you are comfortable navigating ambiguity and take pride in mentoring junior engineers while contributing to collective team success. You are committed to upholding Synopsys' culture of innovation, integrity, and excellence, and you are excited about building next-generation semiconductor products that fuel advances in AI, automotive, and beyond.\n \n What You'll Be Doing:\n  \nLead and execute scan insertion and ATPG (Automatic Test Pattern Generation) flows for complex ASIC designs.\nWork closely with RTL and Verification teams to ensure DFT requirements are integrated early in the design cycle.\nAnalyze and resolve DFT-related issues using tools such as Spyglass DFT, ensuring robust test coverage and manufacturability.\nPerform scan STA (Static Timing Analysis) to validate timing closure and optimize testability paths.\nCollaborate with cross-functional teams to define and implement best practices for DFT methodologies and flows.\nContribute to the continuous improvement of automation scripts and design flows to boost efficiency and reduce turnaround time.\n \nThe Impact You Will Have:\n \nEnhance the testability and reliability of cutting-edge ASIC products, reducing defect rates and improving time-to-market.\nDrive innovation in DFT flows, setting new standards for quality and efficiency within the organization.\nEnable successful silicon validation and ramp-up, directly contributing to customer satisfaction and business growth.\nRepresent Synopsys as a technical leader in the industry, influencing best practices and future technology directions.\nEmpower cross-functional teams by sharing expertise, fostering a culture of continuous improvement and collaboration.\nContribute to the development of next-generation technologies in AI, automotive, and other high-impact sectors.\n \nWhat You'll Need:\n \nExtensive hands-on experience with 3-6yrs in DFT methodologies, including scan insertion and ATPG for complex ASIC designs.\nProficiency with industry-standard EDA tools such as Spyglass DFT and scan STA analysis suites.\nStrong understanding of digital logic design, RTL coding, and verification principles.\nDemonstrated ability to debug and resolve DFT-related issues across multiple project phases.\nSolid scripting skills (e.g., TCL, Perl, Python) to automate design and test flows.\n \nWho You Are:\n \nCollaborative team player who communicates effectively across functions and cultures.\nProactive problem solver, comfortable with ambiguity and rapid change.\nDetail-oriented and highly organized, with a commitment to delivering high-quality results.\nInclusive and open-minded, eager to share knowledge and mentor others.\nSelf-motivated and driven by curiosity, with a continuous learning mindset.\n \nThe Team You'll Be A Part Of:\n You will join a dynamic and innovative DFT team within Synopsys' Engineering organization in Bangalore. The team is dedicated to advancing ASIC testability and reliability, working collaboratively with design, verification, and software groups across the globe. Our culture values technical excellence, mentorship, and cross-disciplinary innovation, providing opportunities to work on industry-leading products that power the next wave of intelligent systems.\n \nRewards and Benefits:\n We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Architect", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-08-11", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506031", "is_hardware": true, "platform": "oracle", "jd_text": "Platform Architect – Digital Compute, Analog & Mixed Signal Products\n\nAbout Us\n\nAt onsemi, we help improve lives through silicon solutions every day. Our intelligent power and sensing technologies solve the world’s most complex challenges and lead the way in creating a safer, cleaner, and smarter world. Our group develops compute subsystems containing MCUs, DSPs, and accelerators, for a large variety of different products and markets.\n\nThe Role\n\nThis role presents an exciting opportunity to define the design architecture and methodologies for a new platform of digital compute and analog/mixed-signal products. As Senior Principal Engineer, you will define the design platform, targeting a large variety of different products. Your responsibilities will include architecture definition, design specification, RTL modeling and performance analysis. Also, you will get to define the design methodologies spanning the entire scope of chip design. You will have a central role within the organization, and you have the opportunity to interact with many product and design teams.\n\nWhy Join Us\n\nWe create a diverse set of world-class products in a friendly and team-oriented atmosphere. We provide an environment of continual learning and growth opportunities and support volunteer & charitable programs. We offer a competitive benefit package and a great place to work to build a career.\n\nWhat You’ll Do\n\nTechnical leadership: Define the architecture and methodology for a new design platform targeting a broad spectrum of products, covering elements of hardware and software\n\nProblem solving: Identify novel solutions when architecting product functionality and/or with design methodologies\n\nTechnical guidance & mentoring: Guide world-wide teams in technical areas, from microarchitecture to productization\n\nInnovation: Define and create design methodology and design flow improvements for efficiency and robustness\n\n  #LI-MK1\n\nResponsibilities\nWhat Else You May Bring (Experience in some of the following areas is a plus)\nExperience in the design of CPU/MCU (sub)systems, compute functions and accelerators\nDevelopment of signal processing components or processing systems\nProgramming in Python for automation and C/C++ for embedded software\nDefinition of design intent: one or more of specification, microarchitecture, structural / functional assessments (CDC, test readiness), verification methods (formal / simulation), physical design (synthesis, timing/power optimisation), process technology aspects, etc.\nExperience in FPGA prototyping\nAwareness in mixed-signal design and verification\nOur commitment to you\nAs part of the onsemi team, you will have an opportunity to transform your tomorrow and operate in a diverse, inclusive, and socially responsible environment. If you’re passionate about shaping a better future, join us!\n\n#LI-MK1\n\nQualifications\nWhat You’ll Need\nB.Tech / M.Tech in Electrical Engineering or related technical field\nAt least 15 years of strong technical experience across any domain of VLSI design \nAn extensive technical background within the development of semiconductor products or sub-components (IPs)\nExperience with embedded CPUs, from a hardware and software/firmware perspective\nStrong communication skills\nAbility to define strategic actions, with appropriate design trade-off analyses\n\n#LI-MK1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Staff SOC Verification Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-11", "url": "https://careers.arm.com/job/bengaluru/staff-soc-verification-engineer/33099/99055494912", "is_hardware": true, "platform": "talentbrew", "jd_text": "Staff SoC Design Verification Engineer\nAbout Solutions SoC Engineering\nJoin the Solutions SoC Engineering organization and help shape the future of silicon. We are building a world-class engineering organization focused on delivering innovative, high-performance, and energy-efficient SoC solutions that power next-generation computing across diverse markets.\n\nAs a rapidly growing global team, we bring together expertise across architecture, design, verification, emulation, FPGA, software, and post-silicon validation to deliver first-time-right silicon. Our engineers solve some of the industry's most challenging engineering problems using advanced verification methodologies, automation, and AI-driven tools while maintaining the highest standards of quality and execution.\n\nOur culture is built on technical excellence, ownership, collaboration, and continuous learning. We invest in our people, encourage innovation, and provide opportunities to influence engineering methodologies, contribute across the product lifecycle, and grow alongside an organization that is defining the future of SoC engineering.\nRole Overview\nAs a Design Verification Engineer, you will verify complex Arm-based IPs, subsystems, and SoCs powering next-generation computing platforms. You will develop scalable verification solutions, own end-to-end verification execution, and contribute to advanced SoC methodologies.\nKey Responsibilities\nDevelop and execute verification strategies for IP, subsystem, and SoC designs.\nVerify CPU, PCIe, DDR, Security, coherency, memory subsystem, and interconnect functionality.\nPerform power-aware verification and system scenario/performance validation.\nOwn verification deliverables from planning through verification closure while ensuring quality, schedule, and execution commitments are met.\nArchitect, develop, and maintain reusable verification environments, verification IPs, methodologies, and automation.\nDevelop verification plans, test methodologies, test cases, and coverage closure strategies.\nDrive functional, code, toggle, assertion, and coverage closure.\nDebug RTL, testbench, integration, and system-level issues.\nCollaborate with architecture, design, firmware, emulation, FPGA, validation, and post-silicon teams.\nLeverage automation, scripting, and AI-assisted workflows to improve verification productivity.\nContribute to methodology improvements, documentation, and engineering best practices.\nRequired Skills and Qualifications\nBachelor's or Master's degree in a relevant engineering discipline.\n10+ years of IP, subsystem, or SoC verification experience.\nStrong Verilog, SystemVerilog, UVM, and modern verification methodologies.\nExperience with Arm-based SoC architecture, coherency, interconnects, memory hierarchy, and UPF.\nExperience with C/C++, scripting, coverage closure, and strong RTL/testbench debug.\nExcellent analytical, communication, and collaboration skills.\nDesired Skills and Qualifications\nExperience with CHI, ACE, AMBA, PCIe, DDR, or Security IP.\nArm System Architecture knowledge.\nAssembly programming.\nFormal verification, emulation, FPGA, gate-level simulation, or post-silicon validation.\nAI-assisted verification and globally distributed engineering experience.\n#LI-KR2\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "SOC Verification Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-11", "url": "https://careers.arm.com/job/bengaluru/soc-verification-engineer/33099/99052020496", "is_hardware": true, "platform": "talentbrew", "jd_text": "About Solutions SoC Engineering\nJoin the Solutions SoC Engineering organization and help shape the future of silicon. We are building a world-class engineering organization focused on delivering innovative, high-performance, and energy-efficient SoC solutions that power next-generation computing across diverse markets.\n\nAs a rapidly growing global team, we bring together expertise across architecture, design, verification, emulation, FPGA, software, and post-silicon validation to deliver first-time-right silicon. Our engineers solve some of the industry's most challenging engineering problems using advanced verification methodologies, automation, and AI-driven tools while maintaining the highest standards of quality and execution.\n\nOur culture is built on technical excellence, ownership, collaboration, and continuous learning. We invest in our people, encourage innovation, and provide opportunities to influence engineering methodologies, contribute across the product lifecycle, and grow alongside an organization that is defining the future of SoC engineering.\nRole Overview\nAs a Design Verification Engineer, you will verify complex Arm-based IPs, subsystems, and SoCs powering next-generation computing platforms. You will develop scalable verification solutions, own end-to-end verification execution, and contribute to advanced SoC methodologies.\nKey Responsibilities\nDevelop and execute verification strategies for IP, subsystem, and SoC designs.\nVerify CPU, PCIe, DDR, Security, coherency, memory subsystem, and interconnect functionality.\nPerform power-aware verification and system scenario/performance validation.\nOwn verification deliverables from planning through verification closure while ensuring quality, schedule, and execution commitments are met.\nArchitect, develop, and maintain reusable verification environments, verification IPs, methodologies, and automation.\nDevelop verification plans, test methodologies, test cases, and coverage closure strategies.\nDrive functional, code, toggle, assertion, and coverage closure.\nDebug RTL, testbench, integration, and system-level issues.\nCollaborate with architecture, design, firmware, emulation, FPGA, validation, and post-silicon teams.\nLeverage automation, scripting, and AI-assisted workflows to improve verification productivity.\nContribute to methodology improvements, documentation, and engineering best practices.\nRequired Skills and Qualifications\nBachelor's or Master's degree in a relevant engineering discipline.\n2-5 years of IP, subsystem, or SoC verification experience.\nStrong Verilog, SystemVerilog, UVM, and modern verification methodologies.\nExperience with Arm-based SoC architecture, coherency, interconnects, memory hierarchy, and UPF.\nExperience with C/C++, scripting, coverage closure, and strong RTL/testbench debug.\nExcellent analytical, communication, and collaboration skills.\nDesired Skills and Qualifications\nExperience with CHI, ACE, AMBA, PCIe, DDR, or Security IP.\nArm System Architecture knowledge.\nAssembly programming.\nFormal verification, emulation, FPGA, gate-level simulation, or post-silicon validation.\n \n#LI-PS1\nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\n \nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior CPU SubSystem Verification Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-11", "url": "https://careers.arm.com/job/bengaluru/senior-cpu-subsystem-verification-engineer/33099/99052020240", "is_hardware": true, "platform": "talentbrew", "jd_text": "Senior CPU Subsystem Design Verification Engineer\nAbout Solutions SoC Engineering\nJoin the Solutions SoC Engineering organization and help shape the future of silicon. We are building a world-class engineering organization focused on delivering innovative, high-performance, and energy-efficient silicon solutions. As a rapidly growing global team, we bring together expertise across architecture, design, verification, emulation, FPGA, software, and post-silicon validation to deliver first-time-right silicon using advanced methodologies, automation, and AI-driven tools. Our culture is built on technical excellence, ownership, collaboration, and continuous learning.\nRole Overview\nAs a CPU Subsystem Design Verification Engineer, you will verify complex CPU subsystems and their integration within next-generation Arm-based platforms. You will develop scalable verification solutions, own end-to-end verification execution, and collaborate across global engineering teams to deliver first-time-right silicon.\nKey Responsibilities\nDevelop and execute verification strategies for CPU subsystems and associated IP.\nVerify processor subsystems including cache hierarchy, coherency, interrupt controllers, debug, trace, memory interfaces, and subsystem integration.\nValidate functional correctness, coherency, performance scenarios, and power management across CPU subsystems.\nOwn verification deliverables from planning through verification closure while ensuring quality, schedule, and execution commitments are met.\nArchitect, develop, and maintain reusable verification environments, verification IPs, methodologies, and automation.\nDevelop verification plans, test methodologies, test cases, and coverage closure strategies.\nDrive functional, code, toggle, assertion, and coverage closure.\nDebug RTL, testbench, integration, and system-level issues.\nCollaborate with architecture, design, firmware, emulation, FPGA, validation, and post-silicon teams.\nLeverage automation, scripting, and AI-assisted workflows to improve verification productivity.\nContribute to methodology improvements, documentation, and engineering best practices.\nRequired Skills and Qualifications\nBachelor's or Master's degree in a relevant engineering discipline.\n4–9 years of experience in CPU, subsystem, or SoC verification.\nStrong knowledge of Verilog, SystemVerilog, UVM, and modern verification methodologies.\nUnderstanding of Arm CPU architecture, memory hierarchy, coherency protocols, interrupts, and subsystem integration.\nExperience with C/C++, scripting, coverage closure, and RTL/testbench debugging.\nExcellent analytical, communication, and collaboration skills.\nDesired Skills and Qualifications\nExperience with CHI, ACE, AMBA, GIC, RAS, or debug/trace.\nExperience with performance and power-aware verification (UPF).\nExperience with emulation, FPGA, gate-level simulation, or post-silicon validation.\nKnowledge of Arm System Architecture.\nAI-assisted verification experience.\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior SoC Formal verification Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-11", "url": "https://careers.arm.com/job/bengaluru/senior-soc-formal-verification-engineer/33099/99055494944", "is_hardware": true, "platform": "talentbrew", "jd_text": "Formal Verification Engineer\nAbout Solutions SoC Engineering\nJoin the Solutions SoC Engineering organization and help shape the future of silicon. We are building a world-class engineering organization focused on delivering innovative, high-performance, and energy-efficient SoC solutions that power next-generation computing across diverse markets.\n\nAs a rapidly growing global team, we bring together expertise across architecture, design, verification, emulation, FPGA, software, and post-silicon validation to deliver first-time-right silicon. Our engineers solve some of the industry's most challenging engineering problems using advanced verification methodologies, automation, and AI-driven tools while maintaining the highest standards of quality and execution.\n\nOur culture is built on technical excellence, ownership, collaboration, and continuous learning. We invest in our people, encourage innovation, and provide opportunities to influence engineering methodologies, contribute across the product lifecycle, and grow alongside an organization that is defining the future of SoC engineering.\nRole Overview\nAs a Formal Verification Engineer, you will apply state-of-the-art formal verification methodologies to complex IPs, subsystems, and SoCs. You will develop proof strategies, assertions, and scalable methodologies that improve design quality and accelerate verification closure.\nKey Responsibilities\nDevelop and execute formal verification strategies for IP, subsystem, and SoC designs.\nDevelop SystemVerilog Assertions (SVA) and formal properties.\nApply property checking, protocol verification, equivalence checking, and formal analysis.\nOwn verification deliverables from planning through verification closure while ensuring quality, schedule, and execution commitments are met.\nArchitect, develop, and maintain reusable verification environments, verification IPs, methodologies, and automation.\nDevelop verification plans, test methodologies, test cases, and coverage closure strategies.\nDrive functional, code, toggle, assertion, and coverage closure.\nDebug RTL, testbench, integration, and system-level issues.\nCollaborate with architecture, design, firmware, emulation, FPGA, validation, and post-silicon teams.\nLeverage automation, scripting, and AI-assisted workflows to improve verification productivity.\nContribute to methodology improvements, documentation, and engineering best practices.\nRequired Skills and Qualifications\nBachelor's or Master's degree in a relevant engineering discipline.\n4+ years of formal verification experience.\nStrong understanding of formal verification methodologies and abstraction techniques.\nHands-on experience with Verilog, SystemVerilog, and SVA.\nUnderstanding of temporal logic, protocol verification, and RTL analysis.\nStrong analytical, debugging, communication, and collaboration skills.\nDesired Skills and Qualifications\nExperience with JasperGold, VC Formal, Questa Formal, or equivalent.\nKnowledge of Arm architecture and AMBA protocols.\nExperience with CDC/RDC, low-power, security, or equivalence verification.\nScripting and automation using Python, Tcl, Perl, or Shell.\nAI-assisted verification and globally distributed engineering experience.\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Mask Design Engineer – Hardware", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-11", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Mask-Design-Engineer---Hardware_JR2022881", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA’s GPUs and SOCs are the world leaders in power, performance, and efficiency. We are continually innovating to deliver new and creative, unusual solutions to extraordinary problems in a wide range of sectors. To this purpose, we are now seeking a hard-working Senior Mask Design Engineer who is committed to making a difference in the world through their contributions!\nThis position will collaborate with Package Technical Lead and different design teams in designing and developing sophisticated, detailed layout of silicon interposers for NVIDIA products. In addition, work with design teams to plan scheules, resolve costs, manufacturing, and electrical design issues.\n\nWhat you'll be doing:\nYou'll collaborate cross functionally with package technical lead (PTL) and I/O signal integrity and technology engineers to deliver solution for product packages in tight schedule.\n\nPerforming physical layout for silicon interposer using Cadence tools.\n\nConduct design feasibility studies to evaluate the package design goals for size, cost, and system performance.\n\nTake part in studying layout floorplan and perform custom layout and verification against design rules and netlists.\n\nPropose layout design trade-offs to the PTL for resolution and implementation.\n\nWhat we need to see:\nHold a B.S. Electrical Engineering or equivalent experience\n\nMinimum of 5+ years proven experience in Mask and Layout Design.\n\nDeep understanding of layout concepts in submicron CMOS technologies.\n\nYou are an authority with Cadence layout tools - particularly Virtuoso.\n\nKnowledge of Integrity auto-routing is a plus.\n\nExperience running and debugging with verification tools such as Calibre, ICV, Thunder, etc.\n\nProficient in scripting languages like Perl, Python, Skill, etc.\n\nShould have knowledge of DRC and LVS checking flows, ability to customize decks.\n\nKnowledge of APD package layout tool is a plus.\n\nGood understanding of packaging technology is useful.\n\nYou can work optimally in a team, good interpersonal skills, passion and positive energy.\n\nNVIDIA is widely considered to be one of the technology world’s most desirable employers! We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative and autonomous, we want to hear from you", "jd_status": "stored"}, {"title": "Staff Subsystem verification engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-11", "url": "https://careers.arm.com/job/bengaluru/staff-subsystem-verification-engineer/33099/99055494672", "is_hardware": true, "platform": "talentbrew", "jd_text": "Staff Subsystem Design Verification Engineer\nAbout Solutions SoC Engineering\nJoin the Solutions SoC Engineering organization and help shape the future of silicon. We are building a world-class engineering organization focused on delivering innovative, high-performance, and energy-efficient silicon solutions. As a rapidly growing global team, we bring together expertise across architecture, design, verification, emulation, FPGA, software, and post-silicon validation to deliver first-time-right silicon using advanced methodologies, automation, and AI-driven tools. Our culture is built on technical excellence, ownership, collaboration, and continuous learning.\nRole Overview\nAs a Subsystem Design Verification Staff engineer you will drive verification of complex subsystems that form the foundation of next-generation Arm-based platforms. You will develop reusable verification solutions and drive verification from planning through closure.\nKey Responsibilities\nDevelop and execute verification strategies for subsystem-level designs and IP integration.\nVerify subsystem functionality including interconnects, memory interfaces, peripherals, power management, and software-visible features.\nValidate subsystem functionality under functional, integration, stress, and performance scenarios.\nOwn verification deliverables from planning through verification closure while ensuring quality, schedule, and execution commitments are met.\nArchitect, develop, and maintain reusable verification environments, verification IPs, methodologies, and automation.\nDevelop verification plans, test methodologies, test cases, and coverage closure strategies.\nDrive functional, code, toggle, assertion, and coverage closure.\nDebug RTL, testbench, integration, and system-level issues.\nCollaborate with architecture, design, firmware, emulation, FPGA, validation, and post-silicon teams.\nLeverage automation, scripting, and AI-assisted workflows to improve verification productivity.\nContribute to methodology improvements, documentation, and engineering best practices.\nRequired Skills and Qualifications\nBachelor's or Master's degree in a relevant engineering discipline.\n10+ years of experience in IP or subsystem verification.\nStrong knowledge of Verilog, SystemVerilog, UVM, and modern verification methodologies.\nUnderstanding of subsystem architecture, integration, AMBA protocols, memory hierarchy, and verification flows.\nExperience with C/C++, scripting, coverage closure, and RTL/testbench debugging.\nExcellent analytical, communication, and collaboration skills.\nDesired Skills and Qualifications\nExperience verifying multimedia, security, PCIe, networking, storage, or memory subsystems.\nKnowledge of Arm architecture and AMBA protocols.\nExperience with UPF, formal verification, emulation, FPGA, or gate-level simulation.\nExperience developing reusable verification IPs and automation frameworks.\nAI-assisted verification experience.\nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Subsystem Design Verification Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-11", "url": "https://careers.arm.com/job/bengaluru/subsystem-design-verification-engineer/33099/99055494752", "is_hardware": true, "platform": "talentbrew", "jd_text": "Senior Subsystem Design Verification Engineer\nAbout Solutions SoC Engineering\nJoin the Solutions SoC Engineering organization and help shape the future of silicon. We are building a world-class engineering organization focused on delivering innovative, high-performance, and energy-efficient silicon solutions. As a rapidly growing global team, we bring together expertise across architecture, design, verification, emulation, FPGA, software, and post-silicon validation to deliver first-time-right silicon using advanced methodologies, automation, and AI-driven tools. Our culture is built on technical excellence, ownership, collaboration, and continuous learning.\nRole Overview\nAs a Subsystem Design Verification Engineer, you will verify complex subsystems that form the foundation of next-generation Arm-based platforms. You will develop reusable verification solutions and drive verification from planning through closure.\nKey Responsibilities\nDevelop and execute verification strategies for subsystem-level designs and IP integration.\nVerify subsystem functionality including interconnects, memory interfaces, peripherals, power management, and software-visible features.\nValidate subsystem functionality under functional, integration, stress, and performance scenarios.\nOwn verification deliverables from planning through verification closure while ensuring quality, schedule, and execution commitments are met.\nArchitect, develop, and maintain reusable verification environments, verification IPs, methodologies, and automation.\nDevelop verification plans, test methodologies, test cases, and coverage closure strategies.\nDrive functional, code, toggle, assertion, and coverage closure.\nDebug RTL, testbench, integration, and system-level issues.\nCollaborate with architecture, design, firmware, emulation, FPGA, validation, and post-silicon teams.\nLeverage automation, scripting, and AI-assisted workflows to improve verification productivity.\nContribute to methodology improvements, documentation, and engineering best practices.\nRequired Skills and Qualifications\nBachelor's or Master's degree in a relevant engineering discipline.\n4–9 years of experience in IP or subsystem verification.\nStrong knowledge of Verilog, SystemVerilog, UVM, and modern verification methodologies.\nUnderstanding of subsystem architecture, integration, AMBA protocols, memory hierarchy, and verification flows.\nExperience with C/C++, scripting, coverage closure, and RTL/testbench debugging.\nExcellent analytical, communication, and collaboration skills.\nDesired Skills and Qualifications\nExperience verifying multimedia, security, PCIe, networking, storage, or memory subsystems.\nKnowledge of Arm architecture and AMBA protocols.\nExperience with UPF, formal verification, emulation, FPGA, or gate-level simulation.\nExperience developing reusable verification IPs and automation frameworks.\nAI-assisted verification experience.\n \nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Staff SoC verification Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-11", "url": "https://careers.arm.com/job/bengaluru/staff-soc-verification-engineer/33099/99055494848", "is_hardware": true, "platform": "talentbrew", "jd_text": "Staff SoC Design Verification Engineer\nAbout Solutions SoC Engineering\nJoin the Solutions SoC Engineering organization and help shape the future of silicon. We are building a world-class engineering organization focused on delivering innovative, high-performance, and energy-efficient SoC solutions that power next-generation computing across diverse markets.\n\nAs a rapidly growing global team, we bring together expertise across architecture, design, verification, emulation, FPGA, software, and post-silicon validation to deliver first-time-right silicon. Our engineers solve some of the industry's most challenging engineering problems using advanced verification methodologies, automation, and AI-driven tools while maintaining the highest standards of quality and execution.\n\nOur culture is built on technical excellence, ownership, collaboration, and continuous learning. We invest in our people, encourage innovation, and provide opportunities to influence engineering methodologies, contribute across the product lifecycle, and grow alongside an organization that is defining the future of SoC engineering.\nRole Overview\nAs a Design Verification Engineer, you will verify complex Arm-based IPs, subsystems, and SoCs powering next-generation computing platforms. You will develop scalable verification solutions, own end-to-end verification execution, and contribute to advanced SoC methodologies.\nKey Responsibilities\nDevelop and execute verification strategies for IP, subsystem, and SoC designs.\nVerify CPU, PCIe, DDR, Security, coherency, memory subsystem, and interconnect functionality.\nPerform power-aware verification and system scenario/performance validation.\nOwn verification deliverables from planning through verification closure while ensuring quality, schedule, and execution commitments are met.\nArchitect, develop, and maintain reusable verification environments, verification IPs, methodologies, and automation.\nDevelop verification plans, test methodologies, test cases, and coverage closure strategies.\nDrive functional, code, toggle, assertion, and coverage closure.\nDebug RTL, testbench, integration, and system-level issues.\nCollaborate with architecture, design, firmware, emulation, FPGA, validation, and post-silicon teams.\nLeverage automation, scripting, and AI-assisted workflows to improve verification productivity.\nContribute to methodology improvements, documentation, and engineering best practices.\nRequired Skills and Qualifications\nBachelor's or Master's degree in a relevant engineering discipline.\n10+ years of IP, subsystem, or SoC verification experience.\nStrong Verilog, SystemVerilog, UVM, and modern verification methodologies.\nExperience with Arm-based SoC architecture, coherency, interconnects, memory hierarchy, and UPF.\nExperience with C/C++, scripting, coverage closure, and strong RTL/testbench debug.\nExcellent analytical, communication, and collaboration skills.\nDesired Skills and Qualifications\nExperience with CHI, ACE, AMBA, PCIe, DDR, or Security IP.\nArm System Architecture knowledge.\nAssembly programming.\nFormal verification, emulation, FPGA, gate-level simulation, or post-silicon validation.\nAI-assisted verification and globally distributed engineering experience.\nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Engineer, Design Automation Methodologies", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-11", "url": "https://careers.arm.com/job/bengaluru/senior-engineer-design-automation-methodologies/33099/99055524544", "is_hardware": true, "platform": "talentbrew", "jd_text": "We are seeking a highly skilled and technically proficient Engineer with experience in ASIC front-end methodologies across IP and SoC design domains. The ideal candidate will bring over 5+ years of VLSI experience, having successfully handled and deployed sophisticated automation flows, design checks and collaborated effectively to deliver innovative solutions in the semiconductor domain. The role includes working with global design teams and internal collaborators to deploy IP/SoC design checks, integration methodologies and improve them continuously.\nResponsibilities:\nDefine the deployment of sophisticated front-end methodologies for ASIC design, including SoC Integration, LEC, CDC/RDC, SDC, linting processes for ASIC project.\nApply automation in design check flows to improve the operating efficiencies.\nCollaborate closely with other design engineers in resolving all the design checks violations and sign-off the design check reports\nCollaborate closely with worldwide team on design methodology, define and evaluate the flows. Actively involve in defining the improvements in the methodology.\nRepresent the company in technical conferences, working groups, and internal award forums.\nRequired Skills and Experience:\n5+ years of experience in VLSI ASIC design and methodology development and deployment.\nDemonstrated experience in executing and driving design check activities for complex SoC projects.\nExpertise in EDA tools such as SpyGlass, VC RDC, LEC, Design Compilers, and formal verification tools.\nProficiency in scripting and automation using Python, Perl, TCL.\nStrong understanding of Verilog/System Verilog and front-end design verification techniques (CDC, RDC, Lint, FV, Synthesis).\n'Nice to Have' Skills and Experience :\nExperience in leveraging AI-driven techniques to optimize and automate workflows within EDA environments.\nSDC and Timing Constraint knowledge, experience working with tools like TimeVision and Fishtail.\nFamiliarity with automotive and compute SoC programs and compliance processes.\nAwards or accolades demonstrating innovation, execution excellence, and peer recognition.\nIn Return:\nWe are proud to have a set of behaviors that reflects who we are and guides our decisions, defining how we work together to surpass ordinary and shape outstanding!\nPartner and dedication towards or customers\nCollaborate and communication\nOriginality and resourcefulness\nTeam and personal development\nImpact and influence\nDeliver on your promises\n10x Mindset at Arm\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Read more about how we bring the 10x mindset to life on the Arm blog.\n\n #LI-SC2 \nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior/Staff ATE Test Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-11", "url": "https://careers.arm.com/job/bengaluru/senior-staff-ate-test-engineer/33099/99055547408", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview: \n \nThis is a great opportunity to join Arm's  Solutions Test Team working with emerging process technologies and the latest offerings across Cloud, Infra, IoT, Auto segments! The test team works closely with IP, SoC Design, Product and Systems teams throughout the company, to represent test engineering and drive test capability development within Arm. You will play a key role in preparing Arm and our partners for how to address production, Characterization challenges in areas like 2.5D/3DIC and sub-3nm nodes. The role requires execution oriented engineering focus across areas such as: Test Strategy, ATE SW/HW planning/execution,  bring-up/characterization/production, and test data capture/correctness/reporting!\nResponsibilities:\nDrive test strategy development for upcoming projects\nDevelop/implement ATE production/characterization plan\nOwns ATE test program development, including:\nTest method source code for test types (ATPG/Scan, MBIST, HSIO, Sensors, Functional, etc)\nTest flow development, including implementation of binning strategy\nTest program revision control framework (ie SVN, git, etc)\nPattern conversion flow\nGuide ATE test HW development (in collaboration with vendors), including wafer probe card, loadboard/socket, and thermal control interface\nRequired Skills and Experience:\nDemonstrated knowledge of ATE (Advantest EXAScale-SMT8) test program development, including areas of test method/flow development, test bring-up, characterization, debug, and production\nKnowledge in areas of DFT (Scan, MBIST, PHY BIST, etc), fabrication process, product qualification.\nExperience in end-to-end project execution, from architecture to production release\nStrong project ownership and ability to lead external vendors and drive multi-functional teams\n6+ years of demonstrated experience in semiconductor product development, including bring-up, characterization, and production\nDegree or equivalent experience with experience in Electronic Engineering or Computer Engineering\n“Nice To Have” Experience:\nUnix, C++, Python, SmarTest, SmartRDI\nData analysis techniques and tools, such as excel, Tableau, JMP, YieldExplorer, etc\nExperience with:\nIEEE 1149, 1500, 1687, 1838\nStreaming Scan Network (SSN), scan diagnostics, failure analysis techniques\nSTIL pattern conversion techiques/tools\nKnowledge of active thermal management\nPersonal Skills:\nAbility to work both collaboratively on a team and independently\nInnovative mentality\nResults-driven mindset and excellent time management skills with an ability to multi-task\nAn upbeat approach to working on exciting projects on the forefront of technology\nCommunicate effectively across teams and sites in different geographies and time zones\nGood analytical and debug skills with a “figure it out” mentality\n10x Mindset at Arm\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Read more about how we bring the 10x mindset to life on the Arm blog.\n\n #LI-SC2 \nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Staff Engineer, Physical Design", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-10T13:59:15.712000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000142651541-staff-engineer-physical-design", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.\nRenesas India is seeking an experienced Staff / Senior Staff Physical Design Engineer to lead subsystem- and block-level physical implementation and closure for complex hierarchical SoCs at advanced technology nodes. This role requires deep expertise in timing, congestion, power integrity, and clocking methodologies, along with strong cross-functional collaboration skills. While this role does not own SoC-level physical design, it plays a critical role in aligning subsystem implementation with overarching SoC strategies.\nKey Responsibilities\nLead block- and subsystem-level physical design closure, including timing closure, congestion mitigation, power integrity, and overall physical implementation quality\nCollaborate closely with SoC-level physical design teams to align on clocking strategies, floorplanning intent, and integration requirements, without direct ownership of SoC-level execution\nApply deep understanding of clocking methodologies to ensure subsystem-level clock domains integrate cleanly into the broader SoC clock architecture\nDevelop, refine, and scale subsystem closure methodologies, flows, and automation, improving predictability, quality, and execution efficiency\nMentor and guide physical design engineers within subsystem teams, promoting best practices, technical rigor, and methodology adoption\nWork cross-functionally with RTL design, STA, power, verification, and backend teams to ensure smooth handoffs and robust closure\nProactively identify, assess, and mitigate physical design risks, coordinating closely with SoC teams to manage impacts and drive solutions\n\n7+ years of experience in physical design, with a strong focus on subsystem-level closure for complex hierarchical SoCs\nStrong expertise in:Timing closure and constraint management\nCongestion analysis and resolution\nPower integrity and power-aware physical implementation\nBlock and subsystem-level physical design flows\n\nSolid understanding of SoC-level floorplanning and clocking methodologies, including:Clock domain partitioning\nClock tree architecture\nSkew management\nClock gating\n\n(Candidate is expected to collaborate effectively at the SoC level, not lead these activities.)\n\nHands-on experience with industry-standard tools such as:Synopsys ICC2, Fusion Compiler, PrimeTime\nCadence Innovus, Tempus, Certus\nSignoff and analysis platforms\n\nProficiency in scripting and automation using Tcl, Python, and/or Perl\nDeep knowledge of end-to-end SoC design flows, with strong collaboration experience across timing, power, clocking, verification, and backend teams\nStrong understanding of low-power design techniques and power-aware implementation methodologies\nEducation\nBTech or MTech in Electronics and Communication, Electrical Engineering, Computer Science, or a related field\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Staff Engineer Design - STA Synthesis", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-08-10T12:00:35+00:00", "url": "https://jobs.infineon.com/careers/job/private?pid=563808971831657", "is_hardware": true, "platform": "eightfold", "jd_text": "#WeAreIn\nfor jobs that impact everyone's life.\nBuild\nthe future nobody’s dreamed of yet... are you ready to rethink the impossible?\n\n As an STA Engineer, you will drive timing analysis and\nclosure for complex low-power SoCs, ensuring designs meet performance and power\ntargets across multiple modes and operating conditions. You will develop and\nvalidate timing constraints, perform pre- and post-layout timing signoff, and\nresolve critical timing challenges.\n \nAre\nyou in?\n\nYour role\nKey responsibilities in your new role\n\nResponsible for STA and Timing Closure of complex, low power SoCs targeted for IOT and MCU markets.\n\nOwnership of constraints development for functional/test modes at pre and post layout stage.\n\nOpportunity to work on IO timing closure for critical interfaces like Serial Peripherals and External Memory Interfaces.\n\nTiming analysis and convergence of large hierarchical design across multiple modes and corners.\n\nInteract with RTL and DFT teams on timing feasibility and performance assessment. \n\nWork closely with physical design team for timing/SI closure. \n\nYour profile\nQualifications and skills to help you succeed \n\nEntrepreneurial\nKnowledge: B.Tech or M.Tech relevant work experience and specialization in VLSI design.\nStrong hands-on technical experience in constraints development, timing\nanalysis/closure of SoCs.\nExperience in low-power synthesis and equivalence checks will be a plus.\nExpert user of industry standard tools for timing signoff. \nExperience in scripting languages (shell, perl, tcl) and Make flow.\nMust be well organized, methodical and detail oriented.\n\nSoft Skills: - \nStrong commitment and determination in area of expertise.\n\nTakes initiatives and overcomes challenges through creativity and innovation.\n\nCoordinates with colleagues and actively shares expertise with others.\n\nShares information comprehensively and effectively.\n\nCooperates across boundaries and appreciates the contributions of other people.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Sr Staff Engineer, Design Verification", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-10T10:42:22.745000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000142609529-sr-staff-engineer-design-verification", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Job Responsibilities\nCoding of simulation infrastructure using SystemVerilog (UVM) & C/(ARM,RISC-V Assembly)  \nSoC Level verification is a must.\nActively involve in all stages of product development including specification, circuit design, circuit modeling, verification, design for test, and silicon debug.\nSet up UVM verification environment, develop, and verify self-tested test benches for Mixed Signal chips and sub-circuits.\nUse and Development of Advanced UVM/mixed-signal simulation techniques to enhance simulation efficiency.\nGenerate Verification Plan from the Specifications using vManager\nDetermine Coverage and design completeness requirements\nGenerate random-constraint tests to cover all customer-use-models\nCreate Assertions, cover-groups, checkers, monitors and automatic reporting\nSet-up and run regression reports\nWorks diligently to accomplish project goals and meet schedule requirements\n\nJob Requirements\nBSEE (MSEE pref.) or equivalent with 10+ years professional industry experience in Digital multi core SoC verification.\nExperience in digital Verification.\nMixed-signal Verification is plus.\nUVM testbench creation, writing and implementation is a plus.\nProficient developing scripts (Shell, Perl, Python etc.), and Cadence SKILL language is plus\nExperience with RN(Real Number)/Digital top-level modeling and verification methodology to speed up simulation (understanding accuracy/speed tradeoff and interfaces)\nMust be able to work independently with limited supervision and work closely with team.\nWork from office.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Principal Engineer- SoC/Chip Lead", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-10T09:40:36.319000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000142596339-senior-principal-engineer-soc-chip-lead", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Own end-to-end technical leadership and execution of complex SoC programs from architecture through silicon production.\nDrive SoC planning, integration strategy, execution schedules, risk management, and tape-out readiness.\nLead cross-functional teams across digital design, verification, physical design, DFT, firmware, validation, packaging, and product engineering.\nDefine chip-level architecture, integration requirements, performance targets, and power/area objectives.\nDrive technical decision-making and trade-off analysis across architecture, implementation, and product requirements.\nOversee subsystem and IP integration, ensuring successful deployment of complex multi-domain SoCs.\nPartner with analog and SerDes teams to integrate high-speed interfaces and mixed-signal subsystems into the overall chip architecture.\nLead design reviews, execution reviews, silicon readiness assessments, and post-silicon debug activities.\nDrive issue resolution across the development lifecycle and ensure successful first-pass silicon execution.\nMentor senior engineers and provide technical leadership across multiple engineering organizations.\n\nBachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or related discipline.\n20+ years of semiconductor industry experience with substantial leadership responsibility.\nProven experience as a Chip Lead, SoC Lead, Technical Program Lead, or equivalent role for large-scale ASIC/SoC products.\nDemonstrated success leading advanced-node SoCs, preferably at 3nm and/or 5nm technology nodes.\nDeep understanding of SoC architecture, integration methodologies, and full-chip development flows.\nStrong experience working across:RTL Design, Design Verification, Physical Design, DFT, Static Timing Analysis, Low-Power Design Methodologies and Silicon Bring-up and Productization.\n\nExperience managing complex schedules, technical dependencies, and cross-functional execution across global teams.\nStrong communication, stakeholder management, and engineering leadership skills.\nPreferred Qualifications: \nPrior experience with:High-performance switching silicon\nNetwork-on-Chip (NoC) architectures\nData movement and interconnect fabrics\nHigh-bandwidth memory-centric systems\nComplex multi-die or chiplet-based architectures\n\nHands-on experience integrating:High-speed SerDes interfaces, Analog front-end (AFE) subsystems, Mixed-signal IPs and Advanced PHY technologies.\n\nExperience with high-bandwidth and low-latency interconnect technologies.\nKnowledge of packaging technologies and signal integrity considerations for high-speed systems.\nExperience in AI, HPC, networking, connectivity, data-center, or memory infrastructure products.\nPrior exposure to UALink, Ethernet switching, switch fabrics, or similar high-performance interconnect technologies is highly desirable.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "CPU Physical Design Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-10T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720238160", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\n7-14  yrs experience in Physical Design and timing signoff for high speed cores.\n\nShould have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology.\n\nMasters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design.\n\nExperience in leading block level or chip level Physical Design, STA and PDN activities.\n\nWork independently in the areas of RTL to GDSII implementation.\n\nAbility to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc.\n\nKnowledge of low power flow (power gating, multi-Vt flow, power supply management etc.)\n\nCircuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.)\n\nTcl/Perl scripting Willing to handle technical deliveries with a small team of engineers.\n\nStrong problem-solving skills.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU STA/Timing Engineer (Lead/Staff/Sr Staff)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-10T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720238162", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nAs a CPU Physical Design Timing (STA) Engineer, you will be a key contributor to high‑performance CPU core and uncore designs, working closely with CPU microarchitecture, RTL, CAD, and physical design teams.\nYou will drive timing analysis and closure for complex, multi‑GHz CPU designs across block, cluster, and full‑chip hierarchies, ensuring aggressive frequency and power targets are met.\n\nRoles and Responsibilities\nWork closely with CPU microarchitecture, RTL, and DFT teams to understand CPU pipelines, critical paths, and performance goals, and to define, implement, and validate timing constraints.\n\nPerform STA for high‑performance CPU designs at block, cluster, and SoC/top‑level hierarchies across multiple modes, corners, and scenarios.\n\nAnalyze timing on frequency‑critical CPU paths (core, cache, interconnect, clocking) and collaborate with RTL and DFT teams to drive logic and micro‑architectural fixes.\n\nProvide actionable timing feedback to block‑level and top‑level physical design engineers to enable CPU frequency and timing closure.\n\nPartner with CAD and methodology teams to develop, deploy, and enhance CPU‑specific timing flows and infrastructure.\n\nGenerate and review timing ECOs (logic and physical) to close setup, hold, noise, and cross‑talk violations in CPU designs.\n\nContribute to CPU timing methodology definition, best practices, and documentation for consistent signoff quality.\n\nPreferred Qualifications\nMS degree in Electrical Engineering with 3+ years of hands‑on experience in STA and timing closure.\n\nStrong experience with STA and timing closure for high‑performance CPU or processor‑class SoCs.\n\nExpertise in multi‑clock, multi‑domain CPU designs with aggressive frequency targets.\n\nExperience in deep sub‑micron technology nodes and advanced process technologies.\n\nProven experience performing STA on large CPU/SoC designs with multi‑scenario and signoff‑quality closure.\n\nHands‑on knowledge of timing ECO techniques and their implementation for CPU frequency closure.\n\nSolid understanding of standard cell libraries, CPU‑critical path optimization, and timing trade‑offs.\n\nFamiliarity with circuit modeling, transistor fundamentals, and worst‑case corner selection for CPU timing signoff.\n\nStrong understanding of industry‑standard synthesis, place & route, and tape‑out flows.\n\nExcellent communication skills to work effectively with CPU architects, RTL designers, PD, and CAD teams.\n\nIn‑depth knowledge of timing effects such as noise, cross‑talk, OCV/variation, and their impact on CPU designs.\n\nWorking knowledge of CPU/SoC architecture and HDL languages such as Verilog.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU STA CAD Engineer (Lead/Staff/Sr Staff)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-10T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720319622", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\n​As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nAs CPU STA CAD engineer, you will build and support the world’s best analysis tools and flows. Your tools and flows will ensure our custom CPUs have industry-leading power, performance and area.\n\nRoles and Responsibilities\n5 to 15 years of relavant experience is mandatory for this role\n\nArchitect and recommend methodology improvements to ensure our silicon has the best power, performance and area\n\nMaintain, support and debug STA and timing closure (ECO) flows, and resolve project-specific issues\n\nWork closely with worldwide CPU physical design teams, and provide methodology guidance and tools/flows support.\n\nWork with EDA vendors to define roadmap and to resolve tool issues.\n\n \n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU Integration/Physical Verification CAD engineer (Lead/Staff/Sr Staff)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-10T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720319625", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\n​As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nAs CPU Integration CAD engineer, you will enable the floor-planning, physical design (PD), physical design verification (PDV), and signoff of Qualcomm’s class-leading Oryon CPU cores.\n\nQualifications:\n6+ years of hands-on experience in development of high-performance chips - either in a design or CAD role\n\nHigh level of programming proficiency (Python and Tcl). Knowledge of data structures and algorithms\n\nExperience with automation\n\nExperience with a broad variety of Physical Design tasks - ranging all the way from place-and-route, analysis, timing sign-off and PDV\n\nExperience with advanced technology nodes (5nm or lower)\n\nStrong user of industry-standard PDV tools such as Siemens/Mentor Calibre\n\nStrong user of industry-standard place-and-route tools such as Cadence Innovus\n\nProven track record of managing and regressing place-and-route flows\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU EM/IR CAD Engineer (Lead/Staff/Sr Staff)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-10T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720319645", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\n​As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nJob Description:\n6 to 15 years of experience in EM/IR and PDN domain is mandatory for this role\n\nExpert user of  Synopsys Redhawk SC/ Cadence Voltus power integrity analysis tool and have exposure to PNR/STA and extraction industry standard tools and  flow\n\nSupport and enhance static IR, dynamic IR, and electromigration flows at the block-level and  subsystem levels\n\nProvide guidance and feedback to PDN  analysis engineers on EMIR best practices, rules, and methodologies.\n\nTroubleshoot and debug EMIR issues and provide solutions to improve accuracy and efficiency.\n\nDevelop, support, enhance scripts that can postprocess EMIR results to dashboard and summarize actionable results for design team\n\nMaintain and release qualified flow releases for large and complex SoCs design implementation and analysis work.\n\nMaximize design productivity with strong/efficient python/tcl/perl scripting skills and customization of tool flows\n\nQualify EMIR tools with regression management systems and create tests.\n\nEngage with EDA vendors in providing cutting edge out of box solutions for new features and flows.\n\nCollaborate with EDA partners to determine/drive optimal and cutting-edge solutions for effective & efficient CAD solutions\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Design Verification Engineer, SSG", "company": "Amazon", "location": "Bengaluru, Karnataka, IND", "date_posted": "2026-08-10", "url": "https://www.amazon.jobs/en/jobs/10497414/senior-design-verification-engineer-ssg", "is_hardware": true, "platform": "amazon", "jd_text": "As a Senior Design Verification Engineer, you will contribute to exploring innovative hardware designs to enhance our devices. You will define verification methodology and implement test plans for advanced functional blocks while collaborating with cross-functional teams to develop world-class hardware devices.  You will participate in the bringup of such blocks on Simulation and Emulation platforms.\n\nYou will work closely with multi-disciplinary groups including Architecture, RTL Design, PD, Validation, Software and Product Design to architect and implement verification environments for complex functional block that enable development of world-class hardware devices. In this role, you will:\n\n• Architect and implement verification environments for complex functional blocks\n• Create and enhance verification environments using SystemVerilog and UVM\n• Develop comprehensive test plans through collaboration with design engineers, SW and architects\n• Implement coverage measures for stimulus and corner-case scenarios\n• Participate in test plan and coverage reviews\n• Drive complex RTL and TB debugs\n• Drive UPF based low power verification\n• Contribute to verification activities across simulation and emulation platforms\n• Work on creating the automation scripts to support DV methodologies\n• Create infrastructure to performs system level performance analysis\n\nBasic qualifications\n- Bachelor's degree in Electrical Engineering or a related field\n- Experience using multiple verification platforms: UVM test bench, FPGA, emulator, software environments, and system testing\n- Experience with test plan development, building the necessary test bench infrastructure, developing tests and verifying the design\n- Experience with industry standard tools and scripting languages (Python or Perl) for automation\n- Experience in object-oriented design skills\n- 10+ years or more of practical semiconductor ASIC experience including owning end to end DV of major SOC blocks\n- Experience with RTL development environments\n\nPreferred qualifications\n- Master's degree or Ph.D. degree in Electrical Engineering or related field\n- Experience with transaction level modeling\n- Strong programming skills in SV, UVM and C Knowledge of AMBA bus protocols\n- Experience with formal verification methods Experience with Low power verification methods\n- Experience with Baremetal processor environments\n- Familiarity with industry standard I/O interfaces\n- FPGA and emulation platform knowledge\n\nOur inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "jd_status": "stored"}, {"title": "Senior Board Design Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-10", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Board-Design-Engineer_JR2014247", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an outstanding Platform Design Engineer to join our Circuit Solutions Group team. In this role, you will collaborate with other key design teams to develop evaluation boards for different Nvidia products and test chips. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of AI computing. Are you passionate about technology enabling growth in AI markets and want to change the world? Then apply now to join NVIDIA!\n\nWhat you will be doing:\nDesign responsibility for the design of evaluation boards for Nvidia products, including GPUs, CPUs, test chips, etc.\n\nDrive every aspect of design execution, electrical schematics, component selection, and provide layout guidance.  \n\nManage the documentation required to release the product to manufacturing and partners, and serve as the primary interface to the Silicon/Thermal/Mechanical/SI/EMC engineers.\n\nCollaborate with Platform Architects and Chip Leads to create the platform specification and ensure the design meets the performance and testing requirements.\n\nHands-on development and testing in a lab environment, validation plans and bring-up, accompanying production and qualification processes.\n\nWhat we need to see:\nBS/MSEE and 5+ years of board/System design experience\n\nProficiency in digital/analog circuit simulation and fault diagnosis.\n\nProven ability to deliver complex projects from specification through to production.\n\nStrong communication and interpersonal skills, critical thinking, problem solving, and project management skills.\n\nWays to stand out from the crowd:\nDeep knowledge in analog and digital electrical circuits.\n\nExperience with SoC platform design, including high current power delivery and high speed signals.\n\nProven industry experience with board design and fabrication including schematics, layout, and familiarity with thermal and mechanical design processes.\n\nWe are dedicated to solving some of the world's most complex problems, from healthcare to robotics, self-driving cars to blockbuster movies, and beyond. Our work in AI and digital twins is transforming industries and profoundly impacting society. We thrive on seamless collaboration, shared success, and a commitment to diversity and individuality. Everyone at NVIDIA contributes, and everyone belongs. Join us at NVIDIA, where you will be part of an eclectic, passionate group of professionals dedicated to making a lasting impact on the world. Together, we will continue to push the frontiers of technology and create a better tomorrow.", "jd_status": "stored"}, {"title": "Senior Engineer, Test Engineering - Product Development", "company": "Analog Devices", "location": "India, Bangalore, Nova", "date_posted": "2026-08-10", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-Nova/Staff-Engineer--Test-Engineering---Product-Development_R255457", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nStaff Test Development Engineer\nADI’s Automotive Wireless Battery Monitoring Systems (wBMS) team in Bangalore works on building Wireless Battery Management Systems products for worldwide automotive customers. We are looking for a highly motivated and experienced candidate to join our team. You will have an opportunity to work directly with cross functional team from product definition through silicon & system development until production release and post-production support.\n\nKey Responsibilities\nWork as part of the development team establishing hardware and software test capability on new designs of high performance digital, mixed-signal and RF SOC’s\nDisplay technical innovation in test development work on new products to improve test efficiency and test development cycle time ensuring success in fast-growing markets\nPlay a key role in DFT/BIST definition & development, through direct involvement with Design early in the New Product Development to improve testability & Full Factory Cost\nDevelop ATE test hardware and software for Final Test and Wafer Probe, understanding the problems/limitations and providing solutions for the same\nAnalyze tester data to debug and optimize the test solution and set parametric test limits for production using statistical methods\nWork with Reliability on device qualification\nWork with manufacturing to release robust, multi-site, high-performance, low-cost test solutions and sustaining released solutions\nProvide technical guidance and mentorship to junior engineers, fostering skill development and knowledge sharing across the test development team\nCollaborate with global teams to align test strategies and share best practices across sites\nDrive continuous improvement in test methodologies and infrastructure to support evolving product requirements and manufacturing capabilities\nQualifications and other requirements\nHold a graduate degree in electrical or Electronics engineering, Masters will be a plus, with 7 to 15 years of relevant experience\nKnowledgeable in Digital, Analog, and Mixed signal IC test methods\nGood hands-on experience on ATE, experience on Teradyne Ultraflex is preferred\nExperience in performing test calibration and knowledge of best practices used in test for coding and hardware design provide an added advantage\nExperience in developing test hardware by creating schematic and overseeing layout\nKnowledge and experience in industry standard best practices for test product development and mass production release process\nGood analytical skills and strong decision making\nPositive attitude and proactive / self-motivated / willing to accept responsibility\nGood team player and ability to work with teams at different sites\nPossess strong interpersonal and communication skills\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Senior Design Engineer - Memory Subsystem", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-09", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Design-Engineer---Memory-Subsystem_JR2020816", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking passionate, highly motivated, and creative senior design engineers to be part of a team working on the design of state of the art memory sub-system components used in their industry-leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nIn this position, you will be encouraged to make architectural trade-offs based on features, performance requirements and system limitations, come up with micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. You will work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and backend teams to accomplish your tasks.\n\nWhat you’ll be doing:\nOwn micro-architecture and RTL development of design modules.\n\nMicro-architect features to meet performance, power and area requirements.\n\nWork with HW architects to define critical features.\n\nCollaborate with verification teams to verify the correctness of implemented features.\n\nInteract with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable.\n\nCo-operate with FPGA and S/W teams to prototype the design and ensure that S/W is tested.\n\nWork on post-silicon verification and debug.\n\nWhat we need to see:\nBS / MS or equivalent experience.\n\n4+ years of design experience.\n\nExperience in micro-architecture and RTL development of complex designs.\n\nExposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).\n\nDeep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping,, timing analysis, floor-planning, ECO, bring-up & lab debug.\n\nExpertise in Verilog.\n\nWays to stand out from the crowd:\nDesign experience in memory subsystem or network interconnect IP.\n\nGood debugging and problem solving skills.\n\nScripting knowledge (Python/Perl/shell).\n\nGood interpersonal skills and ability & desire to work as a part of a team.\n\nNVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "ASIC Design Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-09", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/ASIC-Design-Engineer_JR2019598", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fuelled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world.\n\nNVIDIA is seeking outstanding ASIC Design Engineers to design and implement world’s leading SoC's. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.\n\nWhat you will be doing:\nWork with system architects to understand the functional and performance requirements of a unit or feature.\n\nDefine micro-architecture and develop RTL for owned unit and/or feature.\n\nWork with verification and physical design teams to ensure that the unit or feature is accurately verified and implemented.\n\nOwn silicon bring-up in conjunction with post silicon validation and SW teams.\n\nMentor junior engineers and guide them in their work.\n\nWhat we need to see:\nBS / MS or equivalent experience.\n\n2+ years of experience.\n\nProven knowledge in implementation of complex features or units.\n\nExpertise in micro architecture definition, RTL coding using Verilog or System Verilog.\n\nExpertise in using design and verification tools (Synthesis, lint, VCS or equivalent simulation tools, debug tools like Debussy, GDB).\n\nExperience in memory controller, memory management unit, interconnect design and cache controller design desirable.\n\nGood debugging and problem solving skills. Scripting knowledge.\n\nGood interpersonal skills and ability & desire to work as a teammate are a huge plus.\n\nNVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative, autonomous and love a challenge, we want to hear from you.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior SOC Design Engineer - Networking Group", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-09", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-SOC-Design-Engineer---Networking-Group_JR2019824-1", "is_hardware": true, "platform": "workday", "jd_text": "We are currently seeking an expert SOC Design and Integration Engineers with strong design fundamentals to work in Networking chip design group. You'll join a group of hardworking engineers to craft and implement the next generation innovative DPUs and Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing best high-speed communication devices, delivering the highest efficiency and lowest latency! The Networking Chip Design team in India is a new team which is growing at a fast pace.\n\nWhat you'll be doing:\nYou are encouraged to understand all features of a given project and define project milestones based on internal roadmaps, assign them and track them through agile framework\n\nDefine and develop system-level methodologies, tools, and IPs to build subsytems in an efficient and scalable manner.\n\nWork with SOC Assembly team and drive cross-functional teams towards SOC milestone execution.\n\nBe responsible for integrating all the pieces for a given defined project milestone and deliver the model to relevant teams for further verification at cluster/sub-system/SOC/emulation levels.\n\nWhat we need to see:\nBS (or equivalent experience) / MS with 4+ years of practical semiconductor design and architecture experience building complex SoC’s.\n\nMust have firsthand experience & solid understanding of all phases of SOC development in multiple ASIC projects including ASIC architecture, Micro-Architecture, RTL design, verification, timing closure & Physical design.\n\nExposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.).\n\nC/C++ programming or python or any other industry-standard scripting language experience desirable.\n\nExperience working with software teams to tightly define the HW/SW interface including control/status registers, interrupt and error handling.\n\nHands on experience in successful tape outs of multiple sophisticated, high-volume SoCs in advanced process nodes.\n\nExposure to various Chip Design Functions to be able to collaborate and tackle sophisticated cross functional problems.\n\nExcellent verbal and written communication skills to interact with cross functional teams to build consensus.\n\nExperience in synthesis, physical design and DFT is a plus.\n\nExperience in RTL Build and Design Automation is a plus.\n\nWays to Stand out from the crowd:\nChip lead type of technical leadership experience on delivering complex SOCs for enterprise and/or HPC applications.\n\nExperience in RTL coding and debug, as well as performance/power/area analysis and trade-offs\n\nExperience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area.\n\nPrior experience of smartNIC and/or high-speed interconnects.\n\nStrong coding skills in Perl, Python, or other industry-standard scripting languages.\n\nKnown throughout the technology industry as a top employer, NVIDIA delivers highly competitive salaries and a thorough benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/\n\nNVIDIA is committed to encouraging a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Staff DFT Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-08-09", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Staff-DFT-Engineer_R026775", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nStrong knowledge and experience in Scan Insertion, Compression, ATPG, Memory BIST and JTAG at IC level for mixed signal designs\nLooking for Expert at IJTAG, SSN, ATPG Verification\nExperience in Mentor DfT tools, Synopsys DC and simulator tools.\nDefine DfT Strategy and Requirement Specification for the design\nDfT verification for gate-level and timing simulations\nWork cross sites with design team to define and implement DfT.\nHands on experience in solving DfT problems, simulation failures, ATPG coverage and DRC improvements.\nWork with STA engineer to define timing constraints for DfT modes. Hands on experience on Primetime will be required.\nWork with Layout engineer to see DFT logic is getting implemented without any issues.\nSupport Test engineer in silicon debug and pattern delivery for ATE.\nExperience in RTL coding, shell/Perl scripting.\nKnowledge of System Verilog Interfaces and Lint checks preferred.\nExperienced in handling analog IP DfT simulations.\nBe fluent with all common concepts of DfT and DfT tools.\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Verification Engineer - HWPM", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-08", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Verification-Engineer---HWPM_JR2000528", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been redefining computer graphics, PC Gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s motivated by phenomenal technology – and outstanding people. Today, we are tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work.\n\nThe HWPM Team at NVIDIA is seeking an excellent ASIC Verification Engineer to drive high-quality, robust verification of system-level IP across unit, subsystem, and SoC levels. This role is ideal for someone passionate about ground-breaking hardware, sophisticated verification methodologies, and crafting the future of computing. Come join the team and see how you can make a lasting impact on the world.\n\nWhat You’ll Be Doing:\nPlay a key role in the Hardware Performance Monitor (HWPM) team, helping define and develop system-level RTL and performance measurement methodologies for NVIDIA’s industry-leading SoCs and GPUs.\n\nDevelop comprehensive test plans, implement tests, and apply robust verification strategies to validate microarchitecture and design functionality.\n\nDesign and implement reusable, scalable testbenches and testbench components using System Verilog and UVM.\n\nCollaborate with architects, RTL designers, and software engineers to drive feature completeness, performance visibility, and verification closure.\n\nWhat we need to see:\nM.Tech. (or equivalent) in VLSI or Electronics Engineering OR B.Tech with 2+ years of experience in a similar domain\n\nHands-on experience in unit and/or system level verification\n\nAbility to contribute to testbench development and maintenance, preferably using System Verilog and standard methodologies\n\nProficiency in Python or industry-standard scripting languages for automation and test development\n\nProven debugging fundamentals — ability to read waveforms, analyze logs, and isolate issues effectively\n\nFamiliarity with industry-standard tools such as VCS, Xcelium, Verdi, or similar simulation/debug environments\n\nGood understanding of RTL design concepts and experience working with Verilog or SystemVerilog\n\nExperience with UVM (Universal Verification Methodology) is a strong plus\n\nClear communication skills and collaborative attitude, with ability to work alongside design, DV, and automation teams\n\nWidely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. Also, e have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our outstanding engineering teams are growing fast. If you are creative, curious, and motivated with a real passion for technology, we want to hear from you!\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Verification Engineer - GPU Fullchip", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-08", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Verification-Engineer---GPU-Fullchip_JR2019165", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nThe GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nAs a key member of our ASIC Verification team, you will verify the design and implementation of the industry's leading GPUs.\n\nResponsible for verification of the ASIC design, architecture, golden models and micro-architecture of the GPUs and full-chip level using advanced verification tools and methodologies.\n\nBuild reusable bus functional models, traffic generators, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nYou are expected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.\n\nWorking with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech or equivalent experience with 2+ years of relevant experience\n\nProficiency in Verilog and C\n\nFamiliarity with OOPs concepts\n\nHands-on experience in verification at Unit/Sub-system/SOC level\n\nGood understanding of computer architecture concepts\n\nStrong technical fundamentals with superior analytical skills and problem-solving skills\n\nKnowledge of SystemVerilog or similar HVL is highly desirable\n\nExperience in verification methodologies like UVM/VMM is highly desirable\n\nExposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nPrior experience in 3D graphics processing or processor verification\n\nC/C++ programming language experience\n\nExperience in scripting and tool development using Perl and Python\n\nExcellent debugging skills\n\nGood interpersonal and communication skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Verification Engineer - PCIE", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-08", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Verification-Engineer---PCIE_JR2019560", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n\nAt NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nResponsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nExpected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.\n\nYou will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech. with 2+ years of relevant experience\n\nExperience in verification at Unit/Sub-system/SOC level using Verilog and SystemVerilog\n\nBackground with verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)\n\nExperience in developing and working in functional coverage based constrained random verification environments\n\nExperience in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nExcellent problem solving skills\n\nKnowledge of PCIE protocol - Gen3 and above\n\nProficiency in Testbench development using SystemVerilog\n\nPerl, Python or similar scripting and SW programming language experience\n\nGood debugging and analytical skills\n\nGood interpersonal skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, Nvidia is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Assistant Engineer", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-08-07T12:28:11+00:00", "url": "https://jobs.infineon.com/careers/job/563808971782823", "is_hardware": true, "platform": "eightfold", "jd_text": "#WeAreIn to make sure that our circuits are designed to perfection. Are you in?\nDrive silicon validation and characterization by developing automated test solutions, performing FPGA and post-silicon validation, collaborating on debugging, and streamlining bench testing using Python and LabVIEW. Coordinate with cross-functional teams to ensure successful project execution.\n\nYour role\nKey responsibilities in your new role\n\nInterfacing with the silicon validation, char teams to understand the requirements.\nDevelop and build test list, automation suite including software and firmware for revisions of the silicon.\nValidation on FPGA (pre-silicon) and Silicon (post-silicon), working with the cross functional teams for debugging.\nPython/LabVIEW based bench test equipment automation to support silicon validation and characterization testing.\nManage schedules and liaison with cross functional teams, when associated as a program manager.\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor's/Master's degree in Electronics, Electrical related field of study.\n0 - 3 years of experience and understanding of Microcontroller and SoC products.\nExperience in Bench Characterization with Analog, Digital and Mixed signal IPs.\n Hands-on experience in using equipment such as SMUs, DMM, Oscilloscopes and Signal generators.\nGood understanding of C ,Python, LabVIEW. LabVIEW knowledge will be a great plus.\nGood knowledge about electronic circuits, regulators and reference measurements.\nExcellent communication and interpersonal skills.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nSwati Gupta", "jd_status": "stored"}, {"title": "Sr Staff Mask Design Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-07T07:22:47.591000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000142062214-sr-staff-mask-design-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are looking for an experienced Sr Staff Mask Design Engineer to join a highly skilled layout organization working on Analog and Mixed‑Signal ICs for Automotive applications.\n\nThe role involves defining, developing, and delivering high‑quality, manufacturable IC layouts using industry‑standard technologies and tools.\nThe successful candidate will contribute at block and top level, support or lead layout activities, collaborate closely with design and cross‑functional teams, and ensure robust physical implementation that meets performance, reliability, and quality requirements.\nJob Purpose\nThe purpose of this role is to deliver robust, high‑quality physical layouts for complex analog and mixed‑signal ICs, ensuring manufacturability, reliability, and on‑time delivery, while contributing to layout methodology, team capability, and continuous improvement.\nKey Responsibilities\nAs a Sr Staff Mask Design Engineer, you will be responsible for:\nImplementing physical layouts for Automotive Business Line products at IP, block, and/or SoC level\nDriving and delivering floorplanning activities for blocks and top‑level designs\nParticipating in power supply strategy definition and signal distribution between blocks\nDelivering analog and mixed‑signal layout blocks and contributing to top‑level floorplan strategy\nApplying state‑of‑the‑art layout techniques for device matching, parasitic reduction, ESD protection, latch‑up prevention, and yield optimization\nExecuting and signing off physical verification flows, including DRC, LVS, ERC, DFM, and parasitic extraction (PEX)\nWorking according to Analog‑on‑Top and Mixed‑Signal‑on‑Top layout methodologies\nAttending relevant project and design reviews, reporting progress, risks, and schedule impacts\nCollaborating closely with design, verification, CAD, and technology teams to minimize rework and resolve physical implementation issues\nIdentifying root causes and proposing solutions for issues observed during first silicon or prototype evaluation\nContributing to design‑for‑quality, ensuring layouts are verified, validated, and suitable for long‑term reliability and zero‑defect goals\nSupporting or leading layout team activities, including task planning, execution, and knowledge sharing\nParticipating in and contributing to training activities, technical documentation, and layout guidelines\nTaking a proactive role in personal development, continuous learning, and methodology improvement\n\nEducation & Experience\nBachelor’s or Master’s degree in Electrical, Electronics, or Microelectronics Engineering\n8+ years of experience in Analog and Mixed‑Signal IC layout design\nProven experience delivering complex layouts at IP, block, and/or SoC level\nExperience in automotive or safety‑critical semiconductor products is highly desirable\nTechnical Skills\nStrong expertise in analog layout techniques, including:Floorplanning and top‑level integration\nDevice matching and symmetry\nParasitic management\nLatch‑up prevention and ESD protection\n\nSolid understanding of electronics, semiconductor physics, and fabrication processes\nHands‑on expertise with layout and verification tools, including:Cadence Virtuoso / Virtuoso XL (OA, PVS)\nMentor Graphics Calibre (DRC, LVS, PEX, DFM)\nR3D and related parasitic extraction tools\n\nExperience with advanced CMOS BCD technologies\nExperience using Mixed‑Signal‑on‑Top (MSoT) flows\nAbility to define and execute advanced floorplan strategies\nSoft Skills & Ways of Working\nStrong team player, self‑motivated, and results‑oriented\nAbility to work independently and collaboratively in a multisite, multicultural environment\nExcellent verbal and written English communication skills\nClear, concise communication and presentation skills\nAbility to propose innovative and pragmatic solutions\nStrong focus on quality, reliability, and on‑time delivery\nWillingness to undertake occasional international travel if required\nComfortable collaborating with cross‑functional teams including design, test, program management, and quality\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Staff Engineer - ATE Hardware", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-08-07T06:00:16+00:00", "url": "https://jobs.infineon.com/careers/job/563808971815216", "is_hardware": true, "platform": "eightfold", "jd_text": "Join our team as a ATE Hardware Design & Validation Engineer and play a key role in the development of cutting-edge wireless and test hardware solutions. In this role, you will drive hardware specification reviews, PCB design validation, RF compliance, and ATE test hardware development while collaborating with external design partners, manufacturing vendors, and cross-functional teams. If you have expertise in high-speed hardware design, Bluetooth/Wi-Fi RF systems, SI/PI analysis, and product validation, this is an exciting opportunity to influence products from concept through production.\n\nYour role\nKey responsibilities in your new role\n\nDefine hardware requirements and design specifications for external design vendors. \nReview schematics, PCB layouts, stack ups, and manufacturing outputs to ensure compliance with electrical, RF, mechanical, and reliability requirements. \nEnsure Bluetooth (BT) and Wi-Fi RF test requirements are fully met. \nReview signal integrity (SI), power integrity (PI), and RF simulation results. \nSupport development, validation, and production release of load boards and probe card hardware for ATE-based testing. \nSelect and qualify board-level components including sockets, connectors, cables, relays, and RF components. \nReview board materials, layer stack ups, and fabrication requirements with manufacturing partners. \nWork with external vendors, manufacturing partners, and internal company teams to support fabrication, assembly, validation, delivery, and debug activities. Drive technical issue resolution throughout the hardware development lifecycle.\n\nYour profile\nQualifications and skills to help you succeed \n\nExperience with ATE hardware development, load boards, probe cards, or RF test hardware. \nStrong understanding of Bluetooth and Wi-Fi RF testing requirements. \nExperience reviewing PCB layouts, stack ups, manufacturing outputs, and simulation results. \nKnowledge of PCB fabrication processes, controlled impedance design, and manufacturing constraints. \nExcellent analytical, troubleshooting, and problem-solving skills. \nStrong understanding of electronic components, circuit theory, and board-level hardware design principles. \nHands-on experience with Teradyne Ultra FLEX, Ultra FLEX Plus Advantest 93K, or similar test platforms.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nAnand Rawal", "jd_status": "stored"}, {"title": "USB-Design Verification Senior Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-07T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446715108203", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nJob Description:\nWe are seeking a highly motivated and skilled Design Verification Engineer with 3–6 years of experience to join our team. The ideal candidate will contribute to the verification of high Speed interface  controllers, ensuring compliance with industry standards.\nKey Responsibilities:\nDevelop and execute test plans for USB controller IPs (USB3.2 Gen 2x2, eUSB2V2, USB 2.0).\n\nBuild and maintain UVM-based verification environments for block and system-level DV.\n\nPerform functional coverage analysis, debug failures, and drive closure of verification metrics.\n\nCollaborate with architecture, design, and firmware teams to ensure comprehensive verification.\n\n \n\nRequired Qualifications:\nB.E./B.Tech or M.E./M.Tech in Electrical/Electronics/Computer Engineering.\n\n3–6 years of hands-on experience in digital design verification, preferably in USB or high-speed serial interfaces.\n\nStrong expertise in SystemVerilog, UVM, and scripting languages (Python, Perl, TCL).\n\nExperience with simulation tools (VCS, Questa, Incisive) and debugging tools (Verdi, DVE).\n\nFamiliarity with USB protocols, including USB3.x, USB2.0, and Type-C.\n\nExposure to Synopsys VIPs/IP integration and Qualcomm DV flows is a plus.\n\nPreferred Skills:\nKnowledge of low-power verification, clock domain crossing, and assertion-based verification.\n\nExperience with formal verification and  coverage-driven methodologies.\n\nStrong analytical and communication skills with a proactive attitude.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-08-07", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Senior-Engineer_R026381-6", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nCandidate would be required to work on various phases of SOC physical design activities. The job will include but not limited to  block level – floor-planning, partitioning, placement, clock tree synthesis, route, physical verification (LVS/DRC/ERC/Antenna etc).\nShould be able to meet congestion, timing and area metrics.  Candidate would be required to do equivalence checks, STA, Crosstalk delay analysis ,noise analysis, power optimization. Should be able to implement timing and functional ECOs.\n \nShould have excellent problem solving skill to help through congestion resolution and timing closure. Should have experience formal verification and timing analysis and ECO implementation.\nExperience with tools such as Innovus/Encounter, ICC, Caliber, LEC, Primetime etc is highly desirable.\n \nCandidate should be able to work independently and guide other team members. Should be experienced in working in a global team and dynamic environment.\nShould possess ability to learn and adapt to new tools and methodologies.\nExcellent communication skill is a must. \n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Senior Memory Subsystem Architect", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-08-07", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Memory-Subsystem-Architect_JR2022648", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nNVIDIA is seeking a motivated memory subsystem architects to work with a team to solve complex problems while optimizing performance, area, complexity, and power on leading-edge SoC systems . This team helps build new and innovative products tailored to NVIDIA’s world changing solutions for Data center, Autonomous vehicles, deep-learning, and gaming.\n\nWhat you will be doing:\nDeveloping architecture and micro-architecture to improve the state-of-the-art in memory system optimizing along the axes of performance, power efficiency, complexity, area, effort, and schedule.\n\nPerformance modeling and simulation of features to improve memory system efficiency.\n\nImplementing and maintaining high-level performance and functional models.\n\nAnalyzing benchmarks, application workloads, and performance simulation results to identify tradeoffs in areas of micro-architectural optimizations.\n\nDebugging performance and functional issues with high-level models, RTL simulation, and silicon.\n\nWorking with various cross functional teams like ASIC design and verification, software, product development team, marketing in developing the comprehensive solution.\n\nWhat we need to see:\nMaster degree or equivalent experience in Electrical Engineering, Computer Science, Computer Engineering or related field (or the equivalent experience).\n\n4+ years of meaningful work experience in SoC Architecture and development specifically in one or more domains of MMU and address translation, memory caching, interconnects, and DRAM controllers.\n\nStrong communication and interpersonal skills are required along with the ability to work in a dynamic, product oriented, distributed team.\n\nWays to stand out from the crowd:\nSignificant understanding of Performance (Bandwidth and Latency), Quality of Service and its impact on the overall system performance\n\nPractical experience in developing and using Performance model for early Architecture analysis\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "CAD-DFT Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-07", "url": "https://careers.arm.com/job/bengaluru/cad-dft-engineer/33099/98893963888", "is_hardware": true, "platform": "talentbrew", "jd_text": "Overview\n \nJoin the proactive Chip Methodology & Automation (CMA) team within Arm's Solutions Engineering organization! As a CAD-DFT Engineer, you will develop and apply scalable strategies, sequences, and automation to optimize Arm-based SoC implementation. This role gives you the chance to work across IP, architecture, and product engineering areas. You will contribute to producing production-ready solutions that improve quality, efficiency, and time to market.\nResponsibilities:\nDevelop and maintain DFT methodologies, flows, automation, and reference solutions for Arm-based SoCs.\nDrive alignment and integration of DFT flows within end-to-end RTL-to-GDS and silicon enablement methodologies.\nCollaborate with architecture, implementation, CAD, product engineering, customers, and ecosystem partners to ensure successful deployment.\nEvaluate and enable new capabilities with EDA vendors and technology partners.\nLead technical reviews, resolve complex integration challenges, and drive methodology improvements.\nGuide engineers and contribute to the DFT and automation roadmap within CMA.\nNecessary Skills and Experience:\nMinimum 3+ years of industry experience in DFT implementation, methodology development, and flow integration for complex SoCs.\nDeep understanding of scan, compression, ATPG, MBIST/LBIST, JTAG/IEEE 1149.x, IEEE 1687, and hierarchical DFT methodologies.\nExperience integrating DFT into implementation, verification, and signoff flows.\nHands-on expertise with industry-standard DFT EDA tools.\nStrong automation and scripting skills (Python, Tcl, Shell, or similar).\nExcellent debugging, communication, and collaborator management skills.\nProven ability to influence technical direction across cross-functional teams.\nPreferred Skills and Background:\nExperience with advanced-node SoC development.\nFamiliarity with chiplet or multi-die architectures.\nExperience developing CAD, methodology, or automation infrastructure.\nIn Return:\nAt Arm, we believe in promoting an inclusive and united environment where every team member can thrive. You will be given the opportunity to join a group of highly skilled engineers working on groundbreaking technology. We offer competitive compensation, comprehensive benefits, and a culture that values work-life balance. Join us and contribute to the future of computing!\n10x Mindset at Arm\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Read more about how we bring the 10x mindset to life on the Arm blog.\n \n#LI-SC2\n\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Principal Engineer", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-08-07", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Principal-Engineer_R2739-26-5", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nThe Wireless Solutions Group is seeking an experienced Verification Engineer  candidate with an AI/ML background and verification lead capabilities.\n\nThe successful candidate will be responsible for Digital Verification for future generations of microcontrollers and wireless products.\n\nRequirements/Qualifications:\n\n10+ years in functional verification of complex SoC designs\n\nExpertise in System Verilog, C testcases , UVM and formal verification methodologies\n\nFamiliarity with AI/ML-driven EDA tools and scripting for flow integration.\n\nExperience working with global cross functional teams\n\nProven experience building IP-level and SoC-level verification environments using UVM and/or formal verification Testbenches.\n\nExcellent understanding of digital design, RTL fundamentals, and ARM/RISC SoC architectures.\n\nStrong communication, teamwork, and problem-solving skills.\n\nHighly motivated, detail-oriented, and committed to delivering quality results on time.\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Signal & Power Integrity Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-08-07", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Signal---Power-Integrity-Engineer_JR0286240", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nDelivers signal integrity solutions for large, complex highspeed platforms, boards, and packages. Develops a viable space for all interconnects including 2D and 3D models extracts of electrical structures for the entire dietodie interconnect. Defines signal integrity rules, reviews implementation, documents characterization and measurement reports, and improves and optimizes design margins. Applies knowledge of signal integrity design and tradeoffs to perform simulations of interconnect and guide package and platform physical implementation, and designs and characterizes test structures to correlate simulations and measurements for interconnects using intricate highspeed equipment and debugs challenges. Develops electrical specifications and new industry standard interconnect specifications to guide consortiums for nextgeneration interfaces. Documents and provides implementation guidelines to the end customers as part of the platform design guide. Collaborates with IP design teams and silicon integration teams to ensure the IP and SoC designs maximize the platform level solution space to meet targeted product landing zone requirements and minimize quality degradation (e.g., attenuation, crosstalk, jitter, power noise) and cost.\n\nQualifications:\nMinimum Qualifications:\n- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.\n- 8+ years of experience with a Bachelor's degree, 6+ years with a Master's degree, or 4 years with a PhD.\n- Proficiency in signal integrity analysis, including simulations and validation techniques.\n- Hands-on experience with 3D EM solvers and 3D modeling tools.\n- Strong understanding of PCB and package design principles.\n- Expertise in electrical validation and debug practices.\n- Technical proficiency in noise glitch and signal/power integrity analysis.\n\nPreferred Qualifications:\n- Advanced knowledge of systems engineering fundamentals related to signal delivery design and evaluation.\n- Familiarity with DDR and SERDES interfaces, such as LPDDR5x/6, GDDR6/7, PCIe Gen5/6/7, PAM-4 SerDes, UCIe, UAL, I3C, SVID, etc.\n- Experience developing electrical interface specifications and collaborating with industry consortiums.\n- Ability to demonstrate strong problem-solving skills and strategic thinking in design optimization.\n- Proven ability to work collaboratively across multidisciplinary teams.\n\nWe are looking for passionate individuals eager to make an impact and drive innovation. If you are ready to redefine signal integrity engineering and be part of a team shaping the future of technology, we encourage you to apply today.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Post-Silicon Debug Tools Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-07", "url": "https://careers.arm.com/job/bengaluru/post-silicon-debug-tools-engineer/33099/98893963344", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview:\nWe are seeking a Post-Silicon Debug Tools Engineer to define and drive implementation of the next generation of silicon debug tools! In this role you will lead architecture and development of tracing tools for system debug environment. The ideal candidate combines proven experience in developing command-line and graphical user interfaces, excellent Python software-development skills and proficiency in modern design-for-debug (DFD) architectures.\n\nResponsibilities:\nLead the architecture and development of post-silicon debug tools for configuring and decoding hardware traces, as a part of a larger SoC debug portfolio.\nActively collaborate with DFD architecture and design teams to deliver debug tools that communicate with innovative DFD hardware for system debug use cases.\nWork closely with other members of the silicon debug tools to create consistent user experience across the entire debug toolkit.\nPartner with silicon verification teams for end-to-end debug flow validation of tracing tools in simulation and emulation environments.\nProvide training and support to post-silicon debug teams employing debug tools for issue root-cause and analysis.\nChampion automation, reuse, and scalable debug methodologies that reduce time-to-root-cause.\nInfluence next-generation silicon architecture to ensure debug features are designed for observability and diagnosability.\nRequired Skills and Experience :\nBS/MS in Electrical Engineering, Computer Engineering, or related field with 5+ years of experience.\nExcellent proficiency with Python language for tool and automation development.\nCompetency in software development concepts including unit testing, code coverage collection, release processes and CI/CD pipelines.\nProven experience in development of command-line and graphical user interfaces.\nFamiliarity with Git, Gerrit, Artifactory and CloudBees platform.\nFamiliarity with SoC debug ecosystems (CoreSight, IJTAG, ELA, telemetry frameworks, etc.).\nProven track record in teamwork across hardware, software, and validation teams in a fast-paced environment.\nUnderstanding of JTAG and on-chip debug architectures.\nExperience with silicon bring-up, failure triage and analysis.\n“Nice To Have” Skills and Experience :\nStrong communication skills and consistent record of collaboration with multi-functional and multi-site teams\nIn Return:\nTo join a newly forming Solution Engineering SoC architecture team with significant opportunities to impact the shape, definition, and culture of the team and help build our future success! This will be a fast paced and exciting environment with opportunities to demonstrate your strategic and innovative thinking while directly chipping in to current projects.\nPartner and customer focus\nCollaboration and communication\nCreativity and innovation\nTeam and personal development\n10x Mindset at Arm\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Read more about how we bring the 10x mindset to life on the Arm blog.\n \n#LI-SC2\nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Staff Engineer, Analog Design", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-06T11:02:41.895000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000141893949-senior-staff-engineer-analog-design", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Looking for a 12+ years experienced Engineering Manager with in-depth understanding of Analog concepts, experience of design of complex Analog I/Ps & sub-blocks, integrating I/Ps and sub systems and ownership, experience of fully owning smaller ICs (Point of loads, Single Converters) and owning major I/Ps in large PMICs, to join the 2.6B$ Power Business Unit. The candidate will get to work on a wide range of exciting products such as PMICs, Linear and Switching DC-DC converters powering the next generation of Renesas processors. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas’s massive Power product portfolio. \nEssential Functions: \nMust be proficient in designing and owning complex I/Ps like +ve/-ve Charge Pumps, Buck Converters, Source-Sink LDOs, Ultra-low power Oscillators (including Relaxation type), Temperature Sensor, Current Sense, SAR ADCs, Protection (Thermal, Under-Voltage, Over-Voltage, Over Current etc) and analog blocks including Bandgap references, V2I, Analog Buffers, Op-Amps, Comparators, High speed level shifters etc.  \n\nMust have in-depth Understanding of and should be able to implement & compensate the Control Loops, Analog feedback loops and should know trade-offs between various compensation strategies. \n\nShould be able to build/support Block level spec break down from Top level chip requirements and independently own, design complete switching converter e.g. Buck, Boost, Buck-Boost etc and LDOs. Must be able to do block level error budgeting depending on the block requirements. \n\nMust be aware of relative differences of various control loop architectures (Constant Freq, Constant ON/OFF Time, Current mode etc) and decide/implement the best option to meet converter level performance specifications and other system requirements. \n\nMust be able to bring in innovative ideas to improve designs to meet challenging specifications. \n\nShould have in-depth knowledge of Analog layouts and be able to work closely with layout lead from floor planning till Chip Top completion and verification and do trade-offs based on desired performance \n\nMust be conversant with the standard design, extraction and simulation flows & tools, speed, convergence, accuracy trade-offs and should be able to optimize setups based on Pre/Post (with/without) Parasitic using simulator options, debug and navigate through tool related challenges. \n\nShould be able to setup design flows and methodologies including checklists, reviews to ensure quality designs and take them all the way to Silicon success. \n\nShould be able to mentor Freshers and Junior engineers for upscaling their technical skills as well as other skills needed for better efficacy. \n\nShould have experience of end-to-end IC development flow, Silicon debugs, and taking ICs to production \n\nShould be able to lead/manage a small group of Engineers and navigate through all stages of IC development while handling and mitigating challenges, ensuring high quality silicon while adhering to the schedules based on business needs. \n\nShould have in-depth understanding of ESD, LU and other IC level issues and be able to define protection for the I/O ring for the IC \n\n \n \n\nMinimum Requirements:  \nBachelor’s or master’s degree in electrical engineering  \n\n12+ years in Analog Circuit Design experience  \n\nSolid understanding and design experience of complex analog designs with full ownership.  \n\nChip design, Verification, Silicon validation, debugs, Qual support and taking ICs to production.  \n\nMust be a technical leader and natural team player, mentor and should strive towards fostering a highly creative and productive working environment  \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "DFT- SCAN/ATPG", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-08-06T10:31:00+00:00", "url": "https://global-external-amd.icims.com/jobs/88977/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. MTS SILICON DESIGN ENGINEER    We are seeking a motivated DFx engineer to join our CDFX team. In this role, you will contribute to the next generation of AMD’s silicon innovation while developing your expertise in DFx methodologies and advanced design practices. You will be part of a forward-thinking engineering organization that values learning, encourages fresh ideas, and empowers emerging talent to grow into impactful contributors who help shape the future of semiconductor technology. KEY RESPONSIBILITIES: The successful candidate will own/lead the DFX Design Architect, Develop and implement cutting edge DFX features including SCAN, ATPG, MBIST, BSCAN, etc. Work closely with the DFX Architecture and the various IP Design teams to align on the DFX requirements and successfully implement the DFX design Design and develop correct by construction DFX design and support DFX verification Work closely with the RTL designers, Verification Engineers, and PD team to find creative ways to accelerate the identification of functional defects. Work with the Synthesis and PD team to ensure correct DFT implementation in Scan/ATPG. PREFERRED EXPERIENCE: Experience and understanding of ASIC DFX, Scan synthesis, Integration flow using Fusion Compiler, ATPG experience in tile and SoC level experience. Applicant should be familiar with scan hardware compressions, failure mechanisms and debug processes. Familiar in ICl Extraction, SSN, IJTAG,EDT, TestKompress, simulation and verification flow and experience of working in DFX architecture of complex SOC. Implement and deploy automated design flows to implement DFT features in a complex SOC ASIC design or IP subsystem Experience in End-to-End DFX flow development/creation. DC/AC scan (at-speed) development, debug and test. Expert in at least one of the scripting tool (Perl, Python, TCL) and ability to create complex flows/scripts that provide scalable solutions to DFX implementation. Strong EDA tools experience Tessent - Testkompress, SSN, IJTAG, Synopsys - Fusion compiler, Design Compiler, Spyglass Experience with RTL quality check tools/methodologies such as Spyglass, Lint is required. Exposure to Static timing analysis & Timing closure is required. Scan/ATPG patterns & test flows development, debug, test, and characterization Excellent hands-on debug skills and scripting skills are critical. Strong communication skills and the ability to collaborate effectively within a global team environment are essential. Strong problem-solving skills Knowledge & experience of low power concepts, clock gating, power gating is a plus ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering how it integrates into SoC. #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Systems Design Engineer - Memory Enablement", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-08-06T08:45:00+00:00", "url": "https://global-external-amd.icims.com/jobs/84874/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE:  We are looking for a dynamic, energetic and a strong Enablement Engineer for Memory Enablement in Post silicon x86 environment, join our growing team. The successful candidate will work as part of the post-silicon validation group, enablement of memory features including training/margining and memory subsystem implementation, working with engineering teams across AMD and with the vendor eco-system. Candidate will be immersed in challenging work, developing and executing enablement and feature test plans and reports throughout the execution to meet project milestones at POR quality. The candidate should be able to work in a global environment while maintaining a synergetic culture.   THE PERSON:  As a key contribution to the success of AMD’s product, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry-leading technologies to market. In this role you will facilitate the enablement efforts of a program to ensure timely and qualitative completion of the milestones and adhere to the program commitments. KEY RESPONSIBILITIES: Owning memory sub system implementation based on the Product requirements Conducting day-to-day experiments for Memory enablement Maintaining Test plans and reports and scrubbing the JIRA tickets on a periodic basis Developing required test scripts for small tasks Problem solving - the successful candidate loves debugging complex problems and has a track record of doing so  Work with the Memory Lead and senior members in refining the processes, and demonstrate keen interest to learn and explore new methods/ideas pertaining to memory subsystem PREFERRED EXPERIENCE:  8+ years of Memory enablement experience for any type of SoCs especially x86 containing multi core CPU/GPU subsystems with focus on memory technologies like DDR5/LPDDDR5 Strong understanding of Memory Subsystem including the Memory PHY and Controller understanding, various DDR/LPDDr topologies and configurations, and ecosystem collaboration Expertise in CPU subsystem in x86 / any SoC environment with Strong and Proven expertise in conducting tests and experiments towards enabling memory during Boot and Post -boot enablement Good understanding of x86 HW, FW and BIOS Architecture Strong communication and cross-functional collaboration abilities Exposure to certain stages of Silicon Validation will be crucial, including use-case validation. Practical experience of working on Processor based system designs is a plus Knowledge of shell programming/scripting (e.g. Tcl Perl, Python etc.) Hands-on experience dealing with Memory Analyzers   ACADEMIC CREDENTIALS:  Bachelors or Masters degree in electrical or computer engineering #LI-SK3 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Core CPU Physical Design Engineer (Lead/Staff/Sr Staff)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-06T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720255540", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\n7-14  yrs experience in Physical Design and timing signoff for high speed cores.\n\nShould have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology.\n\nMasters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design.\n\nExperience in leading block level or chip level Physical Design, STA and PDN activities.\n\nWork independently in the areas of RTL to GDSII implementation.\n\nAbility to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc.\n\nKnowledge of low power flow (power gating, multi-Vt flow, power supply management etc.)\n\nCircuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.)\n\nTcl/Perl scripting Willing to handle technical deliveries with a small team of engineers.\n\nStrong problem-solving skills.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Design Implementation Synthesis Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-06T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720259143", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    1+ year of experience with circuit design (e.g., digital, analog, RF).\n•    1+ year of experience utilizing schematic capture and circuit simulation software.\n•    1+ year of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n\nPrincipal Duties and Responsibilities:\n•    Applies Hardware knowledge to assist in the planning, optimization, verification, and testing of electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Provides support for the integration of features and functionality into hardware designs in line with proposals or roadmaps.\n•    Assists in conducting simulations and analyses of designs as well as with the implementation of designs with the best power, performance, and area.\n•    Collaborates with team members to assist in the implementation of new requirements and incorporation of the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Assists in the evaluation, characterization, and development of manufacturing solutions for leading edge products in processes and bring up product to meet customer expectations and schedules.\n•    Assists in the evaluation of reliability for materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Assists in the assessment of common design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works under supervision.\n•    Decision-making affects direct area of work and/or work group.\n•    Requires verbal and written communication skills to convey basic, routine factual information.\n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Technical Lead - Jira Workflow & Automation Engineering", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-06", "url": "https://careers.arm.com/job/bengaluru/technical-lead-jira-workflow-and-automation-engineering/33099/98849319936", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Description:\nWe are looking for an expert Technical Lead to define and drive the engineering JIRA ecosystem across the semiconductor development lifecycle. This role will partner with engineering and program teams to standardize workflows, improve defect management, develop automation, and build data-driven solutions that provide end-to-end execution transparency.\nThe successful candidate will combine strong software engineering expertise with an understanding of engineering execution processes to improve planning, governance, and delivery across multiple organizations.\nResponsibilities:\nEngineering Process & Partner Leadership\nLead the definition and deployment of standardized JIRA workflows, defect tracking processes, issue taxonomy, and engineering governance across Front-End Design, Verification, Physical Implementation, Validation, Power, Performance, Post-Silicon, Software, and Program Management teams. Work closely with partners to harmonize engineering processes and drive adoption across projects.\nAtlassian Platform & Automation\nDesign, develop, and enhance solutions on the Atlassian platform, including JIRA and Confluence. Develop custom workflows, automation, integrations, and extensions using Atlassian APIs, database architecture, and scripting frameworks to improve engineering productivity and scalability.\nEngineering Analytics & Dashboard Development\nDevelop web applications and executive dashboards that provide real-time clarity into project health, milestone readiness, defect trends, execution metrics, dependencies, and engineering targets. Build data pipelines and reporting solutions using Atlassian data and enterprise engineering databases.\nTechnical Leadership\nDrive architectural decisions for workflow automation, mentor engineers, collaborate across organizations, and find opportunities to simplify engineering execution through automation, analytics, and process improvements.\nRequired Skills and Experience:\nBachelor’s or Master’s degree or equivalent with 8years+ experience in Computer Science, Electronics, Information Technology, or a related field.\nStrong experience administering and developing solutions on the Atlassian platform.\nGood understanding of Atlassian architecture, database schema, REST APIs, workflows, permissions, and automation.\nProficiency in Python and SQL, with experience in scripting, API development, and database querying.\nExperience developing modern web applications and dashboards using technologies such as React, Angular, Flask, or similar frameworks.\nStrong partner leadership skills with experience working across multiple engineering teams.\nExcellent problem-solving, communication, and technical leadership skills.\n“Nice To Have” Skills and Experience:\nExperience within semiconductor or EDA environments.\nKnowledge of the SoC development lifecycle, including Design, Verification, Implementation, Validation, Power, Performance, Software, and Program Management.\nExperience integrating JIRA with enterprise engineering tools, CI/CD pipelines, and analytics platforms.\nFamiliarity with Atlassian ecosystem applications such as ScriptRunner, Assets, Structure, or EazyBI.\nIn Return:\nJoining Arm means becoming part of a collaborative engineering community where you’ll be supported throughout your career. We invest in learning, mentoring, and professional development so you can continue building your technical expertise while working on technology that powers billions of devices worldwide.\nYou’ll have opportunities to:\nLearn from extraordinary engineers across hardware and software.\nWork on latest SoC and low-power technologies.\nBuild software, automation, and data solutions used across Arm engineering.\nGain experience across the complete silicon development lifecycle.\nGrow your career through technical mentoring, training, and multi-functional collaboration.\n10x Mindset at Arm\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Read more about how we bring the 10x mindset to life on the Arm blog.\n \n#LI-SC2\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "SOC Design Verification Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-08-06", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/SOC-Design-Verification-Engineer_JR0285533", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nIntel is seeking a Design Verification Engineer for the Hard IP Division. In this technical role, you will define end-to-end verification strategy and execution for multiple Testchips from planning through signoff.\nYou will partner closely with architecture, design, structural design, and IP teams to make early technical calls, unblock cross-team issues, and drive predictable high-quality delivery.\nThis role requires deep DV expertise, strong protocol and memory subsystem knowledge, and enough breadth in RTL, physical design to contribute across traditional discipline boundaries.\nAI-assisted workflows are part of everyday development here. Consistent execution against schedule and quality goals is expected.\n \nResponsibilities\n- Define verification strategy, technical standards, and execution model for critical blocks and ensure on-time quality test collateral delivery to enable post-si team.\n- Lead development of reusable environments, tools, and targeted testplans, including complex testbenches, checkers, VIPs, and behavioural models\n- Collaborate closely with architecture, design, SD, Post-SI and methodology teams from specification through bring up; contribute across role boundaries when needed to unblock execution and maintain delivery quality\n- Drive ownership of multiple critical blocks and verification components; take full responsibility for functional signoffs , Coverage closure, and GLS signoff\n- Drive convergence of simulation and formal verification into unified bug hunting and coverage closure strategies; evaluate and adopt emerging methodologies including AI-driven verification flows\n- Mentor and develop junior verification engineers; establish verification best practices and raise team-level execution quality.\n\nQualifications:\nMinimum Qualifications\n- BS/MS in Electrical Engineering, Computer Science, or related field, with 5+ years of relevant experience in design verification; extensive background in subsystem and SoC-level verification.\n- Demonstrated experience in verification of global functions including debug, trace, clock and power management.\n- Strong background in simulation and formal verification methodologies including UVM, SVA, ABV, and co-simulation; proficiency in low-power verification techniques, HDL/verification languages, and industry-standard EDA tools\n- Advanced hands-on coding proficiency across SystemVerilog/UVM, C/C++, Python, and build systems; comfort using AI-assisted development tools as part of everyday workflow; track record of developing and delivering highly configurable and reusable verification collateral\n- Working familiarity with RTL, physical design constraints, and tool flows; enough to read, review, and contribute outside core DV responsibilities\n- Excellent communication and organizational skills with a track record of delivering high-quality silicon on schedule and establishing technical standards; able to adapt as tools, methodologies, and role definitions evolve.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Principal Firmware/Middleware Architect", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-05T06:46:04.621000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000141645081-principal-firmware-middleware-architect", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Job Summay:\nAs the Principal Firmware Architect for UALink Switch Products, you will serve as the technical visionary responsible for defining, designing, and driving the end-to-end embedded software and firmware architecture for our next-generation AI cluster scale-up switches. \nIn this high-impact role, you will bridge the gap between cutting-edge silicon (ASICs) and upper-layer cluster orchestration software. You will define how firmware manages complex scale-up topologies, ensures raw hardware performance (maximizing bandwidth and minimizing latency), and maintains absolute reliability across thousands of connected AI accelerators. \nKey Responsibilities:\n1. Architectural Definition & Design \nFabric Firmware Architecture: Architect and specify the low-level firmware running on internal microcontrollers within the UALink Switch ASIC. \nHardware-Software Co-Design: Collaborate heavily with ASIC design, logic design (RTL), and verification teams to define hardware-software interfaces, registers, scratchpads, and memory maps. \nProtocol Implementation: Define the firmware stack to support UALink physical, link, and transport layers, managing credits, routing tables, and flow control.\n2. Initialization, Boot, & Fabric Management \nLink Initialization & Training: Design deterministic, fast link-training state machines to bring up ultra-high-speed die-to-die and chassis-to-chassis UALink connections. \nTopology Discovery & Routing: Architect efficient algorithms for runtime topology discovery, dynamic routing, and credit management to prevent fabric congestion. \nPlatform Orchestration: Lead the design of SDKs and APIs that expose switch functionality to baseboard management controllers (BMCs) using OpenBMC and Redfish APIs.\n3. Performance, RAS, & Security:\nLatency & Bandwidth Optimization: Fine-tune bare-metal execution paths to guarantee deterministic low latency for collective communication primitives (e.g., All-Reduce, All-to-All). \nAdvanced RAS (Reliability, Availability, Serviceability): Design robust error-handling, telemetry, and fault-isolation micro-architectures (e.g., link degradation fallback, FEC, and error containment). \nSecurity & Root of Trust: Implement secure boot, cryptographic firmware authentication, and runtime attestation to ensure fabric integrity. \n\nEducation & Experience:\nDegree: Bachelor’s or Master’s/Ph.D. in Computer Engineering, Electrical Engineering, Computer Science, or a related discipline. \n\nExperience: 15+ years of hands-on experience in embedded systems, server platform architecture, or low-level silicon firmware development. \n\nTechnical Skill Set:\nLanguage Masteries: Expert-level proficiency in C for bare-metal and RTOS environments (e.g., ThreadX, FreeRTOS, Zephyr) and Python for hardware automation and modeling. \n\nProtocol Expertise: Deep technical understanding of high-speed scale-up/scale-out interconnect protocols (UALink, NVLink, CXL, or PCIe Gen5/Gen6). \n\nNetwork Switching Concepts: Comprehensive knowledge of credit-based flow control, packet routing, physical layer (PHY) equalization, and SerDes management. \n\nTooling: Strong familiarity with hardware debuggers (JTAG, Lauterbach Lauterbach/TRACE32) and lab equipment (Oscilloscopes, PCIe/Protocol Analyzers). \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nRenesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.", "jd_status": "stored"}, {"title": "Lead DFT Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-08-05T06:41:00+00:00", "url": "https://global-external-amd.icims.com/jobs/88741/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. Lead DFT Engineer:   THE ROLE: As a member of the AMD, you will help bring to life cutting-edge designs. As a member of the DFT team, you will work closely with the DFT Architecture, IP design, Physical Design teams, and Product Engineers to achieve first pass silicon success. THE PERSON: The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Experience with 7+ Years of Strong understanding on Scan Architecture and Scan features Scan insertion and ATPG pattern generation for Stuck at, Transition ATPG, IDDQ Pattern Generation GLS, Timing and Power Aware Simulations Test coverage and test cost reduction analysis Yield Analysis & Debug for Design root cause & Recovery Post Silicon Bring Up: Planning, Co-ordination, and Execution DFT Silicon bring up expertise from across tech various nodes Extensive Silicon Debug for Phasing closure and production enablement Experience of multiple SOC Tape-Outs and Post Silicon Bring-ups PREFERRED EXPERIENCE: Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design   ACADEMIC CREDENTIALS:  Bachelor’s or master’s degree in Electronics/VLSI/Electrical Engineering #LI-SR5 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Principal Engineer- Digital Design", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-05T05:54:37.151000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000141640319-principal-engineer-digital-design", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Job Summary:\nWe are seeking an experienced Principal Engineer / Senior Manager - Digital Design to lead the micro-architecture, design, and execution of next-generation UA Link Switch solutions within the Memory Interface Division (MID). The ideal candidate will bring deep expertise in high-speed digital system design and SoC development, with a proven track record delivering complex silicon products from architecture through production. \nThis role requires strong technical leadership in defining and implementing scalable switching and interconnect architectures that enable high-bandwidth, low-latency connectivity for AI, HPC, and memory-centric systems.\nKey Responsibilities:\nLead digital architecture and design activities for UA Link Switch products. \nDefine and drive microarchitecture, RTL design, integration, and performance optimization of high-speed switching fabrics and interconnect subsystems. \nCollaborate with architecture, verification, firmware, physical design, signal integrity, and system teams to ensure successful product execution. \nDrive end-to-end development from requirements definition through silicon bring-up and product qualification. \nProvide technical leadership across multiple engineering teams and mentor senior engineers. \nAnalyze performance, power, area, and scalability trade-offs to meet aggressive product goals. \nParticipate in architectural reviews, design audits, and technical roadmap planning. \nWork closely with ecosystem and standards teams to align product implementation with evolving industry standards. \n\nBachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or related discipline. \n15+ years of experience in digital ASIC/SoC development. \nStrong experience in one or more of the following areas:  \nHigh-speed digital design \nSoC architecture and integration \nSwitching fabric design \nNetwork-on-Chip (NoC) \nHigh-speed interconnects \nMemory subsystem design \nMicrocontroller-based systems \nHigh-bandwidth data movement architectures \nDeep understanding of RTL design using Verilog/SystemVerilog. \nExperience with modern ASIC development flows including synthesis, STA, low-power methodologies, and silicon bring-up. \nStrong debugging and performance analysis skills. \nDemonstrated ability to lead complex technical programs and influence cross-functional teams. \nPreferred Qualifications:\nPrior experience in: High-speed SerDes-based systems, Switching fabrics and packet processing architectures, Memory interface technologies, AI/HPC interconnect solutions, PCIe, CXL, Ethernet, UCIe, or related high-speed protocols. \nExperience developing large-scale SoCs for networking, compute, storage, or memory applications. \nUnderstanding of system-level architecture and board-level considerations for high-speed designs. \nExperience leading geographically distributed engineering teams. \nStrong communication and stakeholder management skills. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Principal Engineer-Physical Design", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-05T05:44:45.312000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000141639689-principal-engineer-physical-design", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Job Summary:\nWe are seeking an experienced Senior Principal Engineer / Senior Manager – Physical Design Lead to lead the implementation and delivery of next-generation, high-performance SoC products built on advanced process technologies. This role will be responsible for driving the complete physical design execution of large-scale SoCs, from floorplanning through tape-out, while achieving aggressive performance, power, area, and schedule targets. \nThe ideal candidate will have a proven track record delivering complex 3nm and/or 5nm SoCs, with deep expertise in physical implementation of extremely high-speed designs incorporating large digital subsystems, high-speed SerDes interfaces, mixed-signal blocks, and advanced power management architectures. \nKey Responsibilities:\nLead the end-to-end physical design execution of large and complex SoCs from floorplanning through GDS signoff. \nOwn implementation strategy, execution planning, risk management, and tape-out readiness. \nDrive floorplanning, power planning, placement, clock tree synthesis, routing, timing closure, signal integrity, IR/EM closure, and physical verification. \nCollaborate closely with architecture, RTL, verification, DFT, package, analog, and product engineering teams to optimize implementation quality and schedule. \nDefine chip-level implementation methodologies and best practices to achieve challenging frequency, power, and area goals. \nLead timing closure for complex multi-clock, high-frequency designs. \nPartner with package and system teams to optimize overall product performance and signal integrity. \nDrive implementation of advanced low-power architectures and ensure successful power-performance-area (PPA) optimization. \nLead physical design reviews, signoff reviews, and tape-out milestones. \nMentor senior physical design engineers and establish implementation excellence across the organization. \n\nBachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or related discipline. \n15-20+ years of experience in ASIC/SoC physical design. \nProven experience leading physical design teams for large-scale, high-performance SoCs. \nDemonstrated success delivering advanced-node products, preferably at 3nm and/or 5nm technology nodes. \nExtensive experience across:  Floor planning and Partitioning, Power Planning, Placement and Optimization, Clock Tree Synthesis (CTS), Routing and Congestion Analysis, Timing Closure, Signal Integrity Analysis, IR Drop and Electromigration (EM) Closure, Physical Verification and Signoff.\nDeep understanding of advanced-node implementation challenges including variation management, power integrity, and manufacturability. \nStrong knowledge of industry-standard physical design and signoff flows. \nProven ability to lead large cross-functional teams and manage complex execution schedules.\nPreferred Qualifications\nExperience implementing:  \n\nHigh-performance SoCs operating at aggressive frequency targets \nLarge-scale switching and interconnect architectures \nNetwork-on-Chip (NoC) based designs \nHigh-bandwidth data movement fabrics \nMulti-billion transistor designs \nExperience integrating and closing timing on:  \nHigh-speed SerDes subsystems \nMixed-signal and analog IPs \nAdvanced PHY technologies \nMemory controller and high-speed interface designs \nStrong understanding of package-level and system-level impacts on physical implementation and timing closure. \nExperience with advanced packaging and multi-die/chiplet architectures. \nExposure to AI, HPC, networking, data-center, connectivity, or memory infrastructure products. \nPrior experience with high-performance switch fabrics, Ethernet switching, UALink, or similar interconnect technologies is desirable. \nAdvanced Low-Power Expertise (Must Have) \nThe successful candidate must have hands-on experience architecting and implementing advanced power optimization techniques in advanced-node SoCs, including: \nMulti-voltage and multi-power domain designs \nDynamic Voltage and Frequency Scaling (DVFS) \nPower gating and retention strategies \nClock gating methodologies \nAdaptive power management techniques \nUPF/CPF-based low-power implementation flows \nLeakage optimization and dynamic power reduction \nLow-power verification and signoff methodologies \nPower-aware physical design and implementation closure. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Principal Engineer- Design Verification ", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-08-05T05:32:58.267000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000141638869-principal-engineer-design-verification-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Job Summary:\nWe are seeking a highly experienced Verification Lead to drive the verification strategy and execution for next-generation UA Link Switch products within the Memory Interface Division (MID). The candidate will be responsible for leading verification efforts across complex digital subsystems and SoCs, ensuring first-silicon success for high-performance, high-bandwidth interconnect and switching solutions.\nThe ideal candidate will possess deep expertise in modern verification methodologies and extensive experience verifying large-scale, high-speed digital designs involving switching fabrics, SerDes-based interfaces, memory subsystems, and complex SoC architectures.\nKey Responsibilities\nDefine and own the verification strategy, methodology, and execution plan for UA Link Switch products.\nLead verification architecture, testbench development, coverage planning, and verification closure activities.\nBuild and drive scalable UVM/ System Verilog-based verification environments for complex SoC and subsystem designs.\nCollaborate closely with architecture, design, firmware, system validation, and silicon bring-up teams to ensure comprehensive verification coverage.\nDevelop verification plans covering functionality, performance, reliability, error handling, and corner-case scenarios.\nDrive debug and root-cause analysis of design and verification issues.\nDefine and track verification metrics including functional coverage, code coverage, assertions, and regression quality.\nLead verification reviews, sign-off activities, and silicon readiness assessments.\nMentor verification engineers and establish best practices across the organization.\n\nBachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or related field.\n18+ years of experience in ASIC/SoC verification.\nProven leadership experience delivering complex SoC or subsystem verification programs from architecture through tape-out.\nStrong expertise in:System Verilog, UVM, Assertion-Based Verification (SVA), Functional and Code Coverage Methodologies, Simulation and Regression Infrastructure and Verification Closure Techniques.\n\nExperience verifying large-scale digital systems involving:High-speed digital designs, SoCs and subsystem integration, Switching fabrics and interconnect architectures, Memory controllers and memory subsystems and Microcontroller-based systems.\n\nStrong understanding of RTL design concepts and hardware architecture.\nDemonstrated ability to drive cross-functional technical teams and influence architecture and design decisions.\nPreferred Qualifications\nPrior verification experience in one or more of the following:High-speed SerDes-based systems\nSwitching fabrics and packet-based architectures\nMemory interface technologies\nAI/HPC interconnect solutions\nPCIe, CXL, Ethernet, UALink, UCIe, or similar protocols\n\nExperience with formal verification, emulation, and FPGA prototyping.\nFamiliarity with performance verification and system-level validation methodologies.\nExperience debugging silicon issues and supporting post-silicon validation.\nHands-on experience with mixed hardware/firmware verification environments.\nExperience leading geographically distributed verification teams.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "System IP MicroArchitect", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-05T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718352941", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Systems Engineering\nGeneral Summary:\nSkills/Experience:\nTechnical/hands on role for IP Architecture/micro-architecture development\n\nBuilding Design prototypes & commercializing advanced IPs in system infrastructure domain, creating experiments to test proof of concept for algo efficiency, analysis on perf, power, area benefits\n\nlearning various facets of SOC architecture from High-speed Interconnect, Bus Protocols, Memory Technologies, Power Architecture to support different segments of infra solutions\n\nWorking with Performance modelling team to prototype new IP ideas, and with Silicon team to analyze prior products and competition\n\nGuiding Design/DV and engineering teams on high quality IP implementation and successful commercialization, work with SW team for Post Silicon tuning for superior Perf & Power\n\nPreferred Qualifications:\n8+ years of experience in IP architecture, micro-architecture and design.\n\nGood understanding of SOC. Possesses expertise in any one of the following technical areas is a plus: DDR, Interconnects, memory management, SOC power management, clock/reset, Compression, Encryption, ECC, PCIe, CXL\n\nUnderstanding of ARM architecture (Coherency, bus interconnects, Security, arch evolution)\n\nGood communication and ability to work with minimal supervision\n\nCollaborate with Perf, Design and System team stakeholders in developing IP solutions\n\nExperience with Verilog, logic design principles with timing, area and power implications.\n\nExperience in test-plan development, UVM, will be a great asset\n\nUnderstanding interconnect protocols like AHB/AXI/ACE/ACE-Lite/CHI.\n\nGood Understanding of system concurrency, Quality of service, bandwidth, latency and system level analysis\n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Systems Engineering or related work experience.\n                                                                    OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Systems Engineering or related work experience.\n                                                                    OR\nPhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RTL Design (Infra/NOC/SMMU/DDR/Peripherals)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-05T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446717303056", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nWe are seeking a highly skilled and experienced IP Design Engineer to join our dynamic team. The ideal candidate will have a strong background in microarchitecture design, RTL design for complex IPs, and a deep understanding of AMBA or PCIe protocols. This role requires a hands-on approach and a commitment to delivering high-quality, reliable designs.\n\nKey Responsibilities:\nLead the design and development of ground-up IP solutions, focusing on microarchitecture and RTL design.\n\nCollaborate with cross-functional teams to define and implement design specifications and requirements.\n\nEnsure the quality and performance of designs through rigorous PLDRC and synthesis processes.\n\nDevelop and maintain detailed documentation for design processes and methodologies.\n\nTroubleshoot and resolve complex design issues, ensuring timely and effective solutions.\n\nStay current with industry trends and best practices in IP design and related technologies.\n\nQualifications:\n3-15 years of experience in IP design, with a strong focus on microarchitecture and RTL design for complex IPs.\n\nExtensive hands-on experience with AMBA protocol or PCIe protocol.\n\nProficiency in PLDRC and synthesis tools to ensure high-quality design outputs.\n\nStrong understanding of digital design principles and methodologies.\n\nExperience with design verification and validation processes.\n\nExcellent problem-solving skills and the ability to work independently and in a team environment.\n\nStrong communication and interpersonal skills.\n\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.\n\nPreferred Skills:\nExperience with industry standard design flow tools.\n\nKnowledge of ASIC design flows.\n\nFamiliarity with scripting languages such as Python for automation.\n\nExperience with version control systems like Git, clearcase.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    12+ years of Hardware Engineering or related work experience.\n•    3+ years of experience with circuit/logic design/validation (e.g., digital, analog, RF).\n•    3+ years of experience utilizing schematic capture and circuit stimulation software.\n•    3+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test highly critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Participates in or leads the implementation of advanced design rules and processes for electronic hardware, equipment, and/or integrated circuitry.\n•    Conducts highly complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops novel manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of highly critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Advises and leads engineers in the development of complex hardware designs, evaluating various design features to identify potential flaws or issues.\n•    Writes detailed technical documentation for highly complex Hardware projects; reviews technical documentation for junior engineers.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making is significant in nature and affects work beyond immediate work group.\n•    Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. \n•    Has a moderate amount of influence over key organizational decisions.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Physical Design , Principal Engineer/Director, (Custom Silicon Group)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-05T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720216201", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next generation experiences and drives digital transformation to help create a smarter, connected future for all. As an ASIC Design Manager (Principal / Director-Level) in the Custom Silicon Group, you will lead the development and delivery of next-generation, high-performance SoCs from concept to tapeout. You will be responsible for driving the complete silicon development lifecycle, spanning architecture, RTL design, integration, physical design, verification, silicon bring-up, and production readiness. In addition to providing technical and organizational leadership, you will serve as a key customer-facing engineering leader, partnering with strategic customers and stakeholders to translate business requirements into successful silicon solutions.\n\nYou will lead a team of engineers and work closely with cross-functional groups across geographies -- including RTL design, verification, CAD, and integration teams. Your role will be pivotal in shaping the physical design strategy, ensuring design convergence, and maintaining signoff integrity across timing, power, and area metrics.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n\nPrincipal Duties and responsibilities:\nDemonstrate proven experience in executing responsibilities across multiple sites.\n\nLead and manage a team across multiple functions.\n\nDesign closure and tapeout expertise in advanced technology nodes.\n\nComplete ownership of PnR implementation, including Floor planning, Placement, CTS, and post-route activities on the cutting-edge nodes.\n\nPossess mandatory signoff knowledge, including STA, Power Analysis, FV, Low Power Verification and PV.\n\nCollaborate effectively to resolve issues related to constraints validation, verification, STA, Physical Design and tapeout\n\nUnderstand deep sub-micron design challenges, including leakage power, signal integrity, and DFM.\n\nSupport pre-sales and business development activities by evaluating technical feasibility and providing design expertise.\n\nProvide technical leadership during design reviews and executive-level customer engagements.\n\nDrive resolution of customer-reported issues by coordinating across design, verification, firmware, software, and validation teams.\n\nMinimum Qualifications\n• Bachelor's or Master’s degree in Electrical/Electronics Engineering and 17- 25 years of Hardware/VLSI Engineering specializing in Physical Design and timing signoff for high-speed SoCs.\n \nPreferred Qualifications:\nExcellent hands-on experience on Floor planning, PnR and STA flows\n\nGood knowledge of Placement/Clock Tree Synthesis (CTS), Low Power/High Performance optimization etc.\n\nThorough understanding of signoff domains– LEC/CLP/PDN etc.\n\n18+ years of experience with Physical Design and timing signoff expertise in latest tech nodes (e.g., 2nm/3nm/4nm/5nm)\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Engineer EM/IR", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-05T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720216365", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nWe are looking for an experienced EM/IR Engineer to lead power integrity and reliability signoff activities for advanced-node SoC designs. In this role, you will drive IR drop and electromigration (EM) analysis, define signoff methodologies, and collaborate with cross-functional teams to achieve robust and reliable silicon implementation. The ideal candidate should possess deep expertise in power integrity analysis, a strong understanding of advanced-node challenges, and proven experience in leading signoff closure for complex chip designs.\n\nWhat You’ll Do\n \nLead full-chip and block-level IR drop and electromigration (EM) analysis for advanced-node SoC designs\n\nDrive power integrity signoff closure by identifying, debugging, and resolving IR/EM violations\n\nCollaborate with Physical Design, Power, Package, and Foundry teams to optimize power delivery networks\n\nDefine and improve EM/IR methodologies, automation flows, and signoff strategies\n\nPerform static and dynamic IR analysis across multiple operating conditions and scenarios\n\nAnalyze power grid robustness, current density, and thermal impacts to ensure design reliability\n\nSupport tapeout activities and ensure high-quality signoff delivery within project timelines\n \n\nWhat We’re Looking For\n \nBachelor’s or Master’s degree in Electronics, Electrical Engineering, or VLSI-related discipline\n\n10+ years of experience in IR/EM analysis, power integrity, or Physical Design signoff\n\nStrong understanding of power integrity concepts including static/dynamic IR drop, EM analysis, and power grid optimization\n\nHands-on experience with industry-standard tools such as Cadence Voltus, Ansys RedHawk, or equivalent\n\nGood understanding of Physical Design flow including floorplanning, placement, CTS, routing, and extraction\n\nStrong scripting skills in Tcl, Python, Perl, or Shell for automation and flow development\n \n\nGood to Have\n \nExperience with advanced technology nodes such as 7nm, 5nm, 3nm, or below\n\nExposure to package-aware analysis, thermal analysis, and low-power methodologies\n\nExperience in leading signoff closure for large-scale SoC or high-performance compute designs\n \n\nSuccess in This Role Looks Like\n \nAchieving robust IR/EM signoff with minimal iterations and successful tapeout execution\n\nEarly identification and resolution of power integrity risks impacting performance and reliability\n\nImproved signoff productivity through methodology enhancements and automation initiatives\n\nStrong technical leadership and collaboration across implementation and signoff teams\n \n\nLocation\n\nOn-site – Bengaluru\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SOC Architect / uArchitect", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-05T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720273305", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Systems Engineering\nGeneral Summary:\nSkills/Experience:\nBachelor’s Degree required, Master or PhD degree in related field highly desired\n\nSOC Architecture / micro-architecture Background\n\nExcellent communication and interpersonal skills\n\nDemonstrated ability to collaborate on projects with multiple teams and disciplines\n\nAbility to develop and improve methodologies for experiments and analysis in the specific area of expertise\n\nExperience or Education involving hardware, System architecture and software\n\nAreas of Expertise (the more the better):\nCandidates should have one or more of the following areas of knowledge and/or expertise:\n6-11 years in SOC Architecture/Systems Engineering or related work experience\n\nSOC Architecture: Mobile, IOT, XR, Servers\n\nExperience in architecture / Micro-architecture / Design\n\nPreferred domain experience in DDR, Interconnect, System Cache, Coherency, QOS, Modem, DSPs, CPUs (ARM preferred), High and Low Speed peripherals, PCIe / CXL Ips, RISV-V\n\nExpertise in one or more from these Skills: Power Arch, Boot, Debug, Security, Access Control\n\nComputer architecture, understanding of ARM Architecture and related concepts such as ARM TrustZone, Virtualization\n\nUnderstanding of VLSI flow from spec to tape out with proficiency in digital design, HDL languages, Scripting languages\n\nPower and/or performance analysis, simulation, and modelling\n\nLanguages (Not Mandatory): C/C++, Python, Perl, SystemVerilog, VHDL, Verilog, SystemC - FPGA/ASIC design\n\nExposure to HW/SW working model\n\nDesired: Profiles with both VLSI Design and Systems is a plus\n\nDesired: hands on experience with SoC design, integration for complex SoCs and strong understanding in SoC Area, Performance and Power Analysis/tradeoffs.\n\nAnalyzing Complex Information, ability to gather, integrate, and interpret high level information from multiple sources\n\nGood Communication skills, ability to convey information clearly and accurately,\n\nGetting Work Done:  Working independently with little supervision, ability to be organized, resourceful, and planful\n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.\n                                                                    OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience.\n                                                                    OR\nPhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "STA/Timing Methodology Engineer (Lead/Staff)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-05T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446717732133", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nOverview:\nExperienced STA/Timing Engineer with 6-10 Years of hands-on experience on timing sign off/convergence for complex SOCs. Ability to start immediately on timing analysis/sign-off with PD/Methodology teams across multiple sites and different technology nodes.\n\nJob Description:\nSTA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.\n\nTiming analysis, validation and debug across multiple PVT conditions using PT/Tempus.\n\nRun Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.\n\nEvaluate multiple timing methodologies/tools on different designs and technology nodes.\n\nWork on automation scripts within STA/PD tools for methodology development.\n\nGood Technical writing and Communication skills. Willing to work in cross-collaborative environment.\n\nExperience in design automation using TCL/Perl/Python.\n\nFamiliar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus\n\nFamiliar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo.\n\nEducation : B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI.\nPreferred Qualification/Skills\nStrong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling.\n\nHands-on experience with STA tools - Prime-time, Tempus\n\nHave experience working on timing convergence at Chip-level and Hard-Macro level.\n\nIn-depth knowledge crosstalk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,\n\nKnowledge of ASIC back-end design flows, methods, and tools (ICC2, Innovus)\n\nKnowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation.\n\nProficient is scripting languages – TCL, Perl, Python\n\nBasic knowledge of device physics\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Analog/Mixed Signal PLL Analog Designers", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-05T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719650320", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nJob Function\nQualcomm Mixed-Signal IP team is actively seeking analog circuit designers with 6–12 years of experience to join our growing team in Bangalore, India (BDC). You will be directly involved in delivering analog and mixed-signal integrated circuits for high-speed PLL/DLL/LDO/Data Converter IPs for SoCs and supporting their integration into Qualcomm's Mobile, Auto, IoT, and Compute products on leading-edge FinFET and advanced process nodes. Design goals include low-power and low-voltage analog designs for Qualcomm's low-power wireless products.\n\nResponsibilities\nHands-on experience - Analog circuit design \nOwn the architecture, design, and development of analog and mixed-signal hard macros for the PLL IP design team.\nDesign multiple analog building blocks, including bias circuits, references, op-amps, LDOs, VCOs/DCOs, and high-speed custom digital blocks such as dividers and clock distribution.\nPerform custom circuit design in the latest FinFET CMOS process technologies, deliver hard macros, and support customer integration and testing.\nSet up, run, and analyze SPICE circuit simulations, and create behavioral models.\nCollaborate closely with layout, digital design, physical design, and HSIO Bench/ATE teams.\nParticipate in internal customer requirement discussions to create clear design specifications.\n\nSkills & Experience\nMinimum 6 years of transistor-level analog/mixed-signal design experience, preferably in PLL design, data converters (ADC/DAC), or other high-speed applications.\nExperience using SPICE simulators, ADEXL, and Virtuoso.\nFamiliarity with custom analog layout, parasitic optimization, post-layout extraction, verification, and design review closure.\nUnderstanding of signal integrity in high-speed wireline design is preferred.\nScripting experience to automate circuit design and verification workflows.\nAbility to collaborate effectively with global cross-functional teams and communicate technical concepts clearly through documentation and presentations.\n\nPreferred  \nMixed-signal design experience, especially in PLL/DLL clocking architectures, high-speed interfaces, SoC integration, advanced CMOS/FinFET nodes, and scripting\n\nKeywords\nAnalog Circuit Design, Mixed-Signal IP, PLL, DLL, LDO, Bias, Reference, VCO, DCO, Clock Distribution, ADC, DAC, SPICE, Virtuoso, ADEXL, FinFET, Analog Layout, Post-Layout Simulation\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Principal Engineer - Analog Design", "company": "Microchip", "location": "India - Hyderabad", "date_posted": "2026-08-05", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Hyderabad/Principal-IO-Mixed-Signal-Design-Engineer_R1700-25-7", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nAbout the Company:\nMicrochip FPGA Product Group is the leading supplier of low-power programmable technologies. Our mission is to manage power consumption at both the chip and the system level, leveraging the industry's lowest power and unique mixed-signal FPGAs and SoC’s to offer system designers a competitive edge. Our Design Center in Hyderabad, India is a growing and vital member of the group.\nAbout this Position:\nYou will join the custom design team to design analog IP’s for FPGA products. You will work closely with architects, technology development and software engineers to ensure that the company deploys new products with the highest quality and shortest time to market. This position will provide the opportunity to work on multiple projects supporting key functions within the organization.\n\nRequirements/Qualifications:\n\nPrimary Job Responsibilities:\nWork with analog design lead and architects to design specific analog IP blocks\nSimulate analog circuits across process corners and operating conditions, including Montecarlo analysis\nModel design blocks to be included in top level mixed signal simulations\nPost-silicon validation of design at block and system level\nRequired Skills and Experience:\nBSEE or MSEE or PhD in Electrical Engineering\n10+ years of direct experience working on analog and mixed-signal circuits\nExperience in high-speed and analog circuit design including the following: ADCs, DACs, Filters, bandgap, POR circuits, high accuracy comparators etc.\nStrong fundamentals of circuit theory, design, and layout\nHands-on experience in scripting and automation (Skill, Python, Perl, Tcl, etc.)\nStrong knowledge in Cadence IC design flow and tools\nExpertise in the system design of mixed signal circuits is preferred\nHands-on experience with lab testing of analog blocks\nInitiative (self-motivated, self-confident, self-driven, self-learning, always striving for excellence)\nCommitment (responsible, responsive, committed to winning)\nSolid functional and technical skills\nWork quality (\"do it right the first time\", attention to detail, good documentation)\nStrong analytical and problem-solving skills\nExcellent communication, documentation and presentation skills\nMust have strong self-learning ability, leadership, and enjoy working in teams\n\nPreferred Skills:\nExperience in board design fundamentals, signal and power integrity\nExperience with Verilog or VHDL\nWorking knowledge of SOC and/or FPGA Architectures\nKnowledge of FPGA design generation flow associated with Microchip (Libero), or any other FPGA\n\nTravel Time:\n\nNo Travel\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "SoC Verification- Principal Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-05", "url": "https://careers.synopsys.com/job/bengaluru/soc-verification-principal-engineer/44408/98800793072", "is_hardware": true, "platform": "talentbrew", "jd_text": "Alternate Job Title:SoC Verification- Principal Engineer\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in the trenches of SoC verification, where the difference between a chip that tapes out on schedule and one that slips six months often comes down to a verification plan you wrote in week two. You know that verification is not just about coverage numbers, it is about understanding what can actually break in silicon and making sure it does not.\nLeading a team does not mean delegating and disappearing. You are in the waveform debugger alongside your engineers when a protocol violation shows up at 2am, and you can spot a gap in a testbench architecture during a design review without needing to see the code. You have learned to read a customer's SoC spec and immediately know where the risk lives, whether it is in the interconnect, the power domain crossings, or that custom accelerator block nobody wants to talk about yet.\nYou do not wait for perfect requirements. You ask the right questions, build a verification plan that actually maps to what can go wrong, and adjust as the design evolves. At Synopsys, you will work directly with customers building chips for AI, automotive, aerospace, and high-performance computing, and the verification strategies you build will determine whether their silicon works.\nWhat You'll Be Doing\nLead verification execution for customer SoC, subsystem, and IP projects, from verification planning through signoff, working directly with customer engineering teams to define scope and deliverables\nLead verification teams of 3-4 engineers, assigning tasks, reviewing testbenches and coverage reports, and mentoring engineers through complex debug scenarios\nDevelop verification plans that map customer requirements to testbench architecture, coverage goals, and resource allocation, then track execution and adjust as designs evolve\nIntegrate and deploy Synopsys VCS, Verdi, and third-party VIP for protocols like PCIe, Ethernet, USB, and DDR into customer verification environments\nDebug complex multi-protocol and multi-domain SoC issues using waveform analysis, coverage analysis, and cross-functional collaboration with design, architecture, and post-silicon teams\nIdentify project risks early, propose mitigation strategies, and communicate status and blockers to Synopsys management and customer stakeholders\nDrive methodology improvements across the SSG verification team, whether that is UVM reuse strategies, regression optimization, or new tool adoption\nThe Impact You Will Have\nYour verification plans and execution will directly determine whether customer chips tape out on schedule or slip quarters, affecting product launch timelines for AI accelerators, automotive SoCs, and aerospace systems\nThe engineers you mentor will grow into technical leads themselves, building verification capability across Synopsys that scales to future customer engagements\nYour early identification of design risks and verification gaps will prevent costly respins and post-silicon surprises for customers building chips in 5nm and below\nThe methodology improvements you drive will reduce verification cycle time and improve coverage quality across dozens of SSG projects annually\nYour direct customer engagement will shape how leading semiconductor companies adopt and deploy Synopsys EDA tools and IP in their verification flows\nThe testbench architectures and VIP integration strategies you build will become reusable assets for future projects, compressing ramp time for new customer engagements\nYour technical leadership will help Synopsys win and retain customer relationships in high-performance computing, automotive, and aerospace markets where verification complexity is a competitive differentiator\nWhat You'll Need\nBachelor's or Master's in Electronics Engineering, Computer Engineering, or related field with 12+ years of hands-on SoC, subsystem, or IP verification experience\nDeep technical expertise in UVM testbench development, coverage analysis, verification planning, and complex multi-domain debug\nProven experience leading verification teams through full project cycles, including resource planning, task assignment, and delivery against customer schedules\nStrong working knowledge of industry-standard protocols such as PCIe, Ethernet, USB, or DDR, and how they interact in real SoC architectures\nHands-on proficiency with Synopsys VCS, Verdi or equivalent waveform analysis tools, and integration of third-party VIP into verification environments\nExperience with ARM-based technologies including Coresight debug infrastructure, processor architecture, or AMBA protocols is a strong plus\nSolid understanding of ASIC design flows, RTL design concepts, and how verification fits into the broader chip development process\nWho You Are\nYou can walk into a customer meeting, hear a high-level SoC architecture description, and walk out with a verification plan that identifies the three highest-risk areas before anyone else in the room sees them\nWhen a regression fails at 3am and your team is stuck, you can look at the waveform, the coverage report, and the testbench code and know within 15 minutes whether it is a real bug or a testbench issue\nYou give feedback that makes engineers better, not just feedback that makes you feel heard, and your team knows the difference\nYou do not let a project drift. If a customer requirement is vague or a timeline is unrealistic, you say so early and propose a path forward that actually works\nYou can explain a complex protocol violation to a customer architect, a verification coverage gap to your manager, and a UVM sequence bug to a junior engineer, and all three conversations will be clear and useful\nYou stay current on verification methodology and tooling not because it is required but because you care about doing this work well, and you bring that knowledge back to your team\nThe Team You'll Be Part Of\nYou will join the System Solutions Group (SSG), a team that delivers end-to-end SoC design and verification services to Synopsys customers across automotive, high-performance computing, aerospace, and defense. SSG works on everything from individual IP blocks to full turnkey SoCs, partnering with customers ranging from startups to industry leaders and government agencies. Your verification work will span subsystems and full chips, and you will collaborate closely with Synopsys architecture, design, EDA application engineering, and sales teams to deploy tool and IP solutions that solve real customer problems.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Analog Circuit Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-08-05", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Analog-Circuit-Design-Engineer_JR0283513", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact:\nAs an Analog Circuit Design Engineer, you will be at the forefront of cutting-edge technology, transforming innovative concepts into high-performance analog circuits. Your expertise will drive the development of advanced process nodes for analog and mixed-signal IPs, enabling Intel's next-generation products to achieve exceptional performance and efficiency. You will collaborate with cross-functional teams to design, simulate, and verify circuits that optimize power, performance, area, and yield goals. This role presents an exciting opportunity to shape the future of analog design, tackle complex challenges, and contribute to Intel's mission of delivering world-class solutions.\n\nKey Responsibilities:\n- Design, develop, and implement analog circuits for advanced process nodes focused on high-speed 112/224Gbps SerDes Design, including TX, RX and PHY clocking circuits.\n- Perform circuit design, parameter extraction, and analog behavior modeling to meet circuit and block microarchitecture specifications.\n- Create and execute test plans to validate functionality, reliability, and performance of designs, ensuring compliance with specifications.\n- Optimize circuits for power, performance, area, timing, and leakage while addressing trade-offs in circuit design.\n- Collaborate with architecture and layout teams to design circuits that deliver robust functionality and superior electrical capabilities.\n- Conduct detailed validation, including post-silicon testing and debug, and support high-volume production readiness.\n- Utilize industry-standard tools such as Cadence Virtuoso, SPICE simulators, and extraction tools for design and verification.\n- Continuously improve design methodologies and contribute to enhancing processes for greater efficiency and innovation.\n- Drive technical discussions, report progress, and resolve performance and design issues through collaboration with cross-functional teams.\n\nQualifications:\nMinimum Qualifications:\n- Bachelor's or Master's degree in Electrical Engineering or a related specialized field.\n- Minimum 6 years of hands-on experience with a Bachelor's degree or 4 years with a Master's degree in analog circuit design.\n- Proficiency in designing Analog/Mixed-signal circuits for 224Gbps/112Gbps SerDes PHY.\n- Demonstrated capability in using EDA tools such as Cadence Virtuoso, SPICE simulators, and extraction tools like DRC, LVS, and post-layout verification.\n- Expertise in CMOS technologies and I/O fundamentals.\n- Experience with circuit simulation methodologies and tools.\n- Ability to develop circuits optimized for performance, power, area, and yield.\n\nPreferred Qualifications:\n- Strong fundamentals in circuit trade-offs, including power optimization and reliability-aware design.\n- Experience in post-silicon validation and debugging of pre/post-silicon issues.\n- Familiarity with scripting languages such as Python, Perl, or TCL for design automation.\n- Knowledge of industry standards and compliance requirements related to high-speed I/O interfaces.\n- Proven ability to work in fast-paced environments, solve complex technical challenges, and lead innovative design initiatives.\n\nBe part of a team that transforms ideas into reality and shapes the future of analog and mixed-signal design. Apply today to join Intel and help drive innovation that impacts the world.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Mixed Signal Logic Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-08-05", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Mixed-Signal-Logic-Design-Engineer_JR0285540", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nAs a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of industry-leading technologies by contributing to the development of high-speed, low-power IPs for next-generation products. You will work in a dynamic, innovative environment, collaborating with cross-functional teams to deliver robust and efficient mixed signal designs. By owning and delivering the logic design of Mixed Signal IPs, you will directly influence Intel's mission to create world-changing technology that enables global progress and enriches lives.\n\nKey Responsibilities\n- Define and implement microarchitecture and RTL designs for mixed signal and high-speed IP blocks using System Verilog.\n- Collaborate closely with architecture and system teams to optimize power, performance, and area for IP designs.\n- Develop and utilize automation flows for IP logic design, ensuring high-quality RTL through tools such as Lint, CDC, and synthesis QA checks.\n- Conduct power and performance analysis, driving improvements in area and power efficiency across designs.\n- Review verification plans and resolve RTL issues to ensure feature correctness and design integrity.\n- Support SoC teams, ensuring seamless integration and high-quality delivery of IP modules.\n- Innovate and implement automated solutions to streamline coverage closure and timing convergence.\n\nQualifications:\nMinimum Qualifications\n- Bachelor's or Master's degree in Electrical or Computer Engineering, or a closely related field.\n- 4-12 years of experience with a Bachelor's degree or 3-10 years of experience with a Master's degree.\n- Strong expertise in RTL development using System Verilog.\n- Proficiency in low-power design techniques, including UPF, clock gating, and multiple clock domain design.\n- Hands-on experience with front-end design tools such as Spyglass, VC Lint, CDC, and synthesis tools.\n- Solid understanding of state machine design, simulation, and debugging using tools like VCS and Verdi.\n- Scripting proficiency in Perl, Python, or TCL for design automation and workflow optimization.\n\nPreferred Qualifications\n- Familiarity with DFI, DDR, or LPDDR protocols and DDR PHY/Memory Controller designs.\n- Basic understanding of analog design to facilitate optimal integration of analog and digital components.\n- Pre-silicon and post-silicon validation experience is an advantage.\n- Knowledge of area and power optimization techniques for IP designs.\n- Strong problem-solving skills with the ability to make critical technical decisions in complex situations.\n\nJoin us in redefining the boundaries of technology and innovation. Apply today to be part of a team that drives transformative solutions for tomorrow's challenges.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Lead  Hardware Development Engineer - Signal & Power Integrity", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-08-04T11:17:00+00:00", "url": "https://global-external-amd.icims.com/jobs/89136/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. THE ROLE: We are looking for an SI/PI Analyst – Signal & Power Integrity Engineer to architect, analyze, and optimize high-speed electronic systems across PCB, Package, Module, and System-level designs. In this role, you will leverage first-principles engineering, simulation, measurement, and correlation to deliver robust, cost-effective, and high-performance solutions. You will work on challenging electrical problems involving memory interfaces, high-speed serial links, power delivery networks, package design, and advanced embedded computing platforms. THE PERSON: Engineers who are passionate about signals, power delivery, transmission lines, measurements, circuits, and system behavior. We value individuals who combine deep technical expertise with humility, innovation, mentorship, and a relentless desire to elevate both technology and the people around them. KEY RESPONSIBILITIES: Architect robust Signal Integrity and Power Integrity solutions using strong engineering fundamentals and first-principles thinking. Perform pre-layout and post-layout SI/PI analysis using time-domain and frequency-domain methodologies. Balance Performance, Power, Cost, and Design Margin without unnecessary over-design. Develop practical design guidelines and best practices that enable successful platform execution. Correlate simulations with measurements and continuously improve modeling accuracy and methodology. Identify opportunities to innovate, automate, simplify workflows, and improve engineering productivity. PREFERRED EXPERIENCE: Strong understanding of electromagnetic theory, transmission lines, return current behavior, crosstalk, S-parameters, jitter, channel analysis, and power delivery networks. Ability to perform hand calculations, estimations, and engineering sanity checks before relying on simulations. Deep passion for signals, waveforms, circuits, networks, measurements, and solving challenging SI/PI problems. Hands-on experience with industry-standard Signal Integrity tools including: Ansys Sigrity Keysight Equivalent SI/PI simulation environments Strong knowledge of high-speed interfaces including high-speed Memory and SERDES. Challenges conventional approaches and continuously seeks better ways to improve design quality, prediction accuracy, and customer success. We value engineers who reason from physics and first principles, using tools to validate their understanding—not to replace it. ACADEMIC CREDENTIALS: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline. #LI-NS2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Lead  Hardware Development Engineer - Signal & Power Integrity", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-08-04T11:05:00+00:00", "url": "https://global-external-amd.icims.com/jobs/89162/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. THE ROLE: We are looking for an I/PI Analyst – Signal & Power Integrity Engineer to be part of the Commercial sales team. This role is customer-facing and will be responsible for building AMD's commercial systems channel business in support of our customers' commercial PCs, servers, and professional graphics. You will be responsible for driving a team that will be building business development with Distribution, NSP and VAR partners by evangelizing AMD technology, building sales programs, enabling sales teams through training, and managing executive relationships. THE PERSON: Engineers who are passionate about signals, power delivery, transmission lines, measurements, circuits, and system behavior. We value individuals who combine deep technical expertise with humility, innovation, mentorship, and a relentless desire to elevate both technology and the people around them. KEY RESPONSIBILITIES: Architect robust Signal Integrity and Power Integrity solutions using strong engineering fundamentals and first-principles thinking. Perform pre-layout and post-layout SI/PI analysis using time-domain and frequency-domain methodologies. Balance Performance, Power, Cost, and Design Margin without unnecessary over-design. Develop practical design guidelines and best practices that enable successful platform execution. Correlate simulations with measurements and continuously improve modeling accuracy and methodology. Identify opportunities to innovate, automate, simplify workflows, and improve engineering productivity. PREFERRED EXPERIENCE: Strong understanding of electromagnetic theory, transmission lines, return current behavior, crosstalk, S-parameters, jitter, channel analysis, and power delivery networks. Ability to perform hand calculations, estimations, and engineering sanity checks before relying on simulations. Deep passion for signals, waveforms, circuits, networks, measurements, and solving challenging SI/PI problems. Hands-on experience with industry-standard Signal integrity tools from: Ansys, Sigrity, Keysight and Equivalent SI/PI simulation environments Strong knowledge of high-speed interfaces including: high speed Memory and SERDES Challenges conventional approaches and continuously seeks better ways to improve design quality, prediction accuracy, and customer success. Expertise in Cadence Allegro PCB design tools, particularly for advanced routing optimization and pathfinding studies, would be a valuable addition. We value engineers who reason from physics and first principles, using tools to validate their understanding—not to replace it. #LI-NS2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Physical Design Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-08-04T05:07:00+00:00", "url": "https://global-external-amd.icims.com/jobs/88012/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. MTS SILICON DESIGN ENGINEER    THE ROLE: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. THE PERSON: AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanning and physical design flows for best in class ASIC solutions. KEY RESPONSIBLITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Deft at Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus. Tasks to include Full Chip Level Floor planning, Bus / Pin Planning, feed-thru planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, Physical Verification and Sign Off Identify complex technical problems, break them down, summarize multiple possible solutions, Drive and hands-on flow development and scripting PREFERRED EXPERIENCE: 8+years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-AB1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Engineer Verification", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-08-04T04:00:20+00:00", "url": "https://jobs.infineon.com/careers/job/563808971791766", "is_hardware": true, "platform": "eightfold", "jd_text": "Looking for an experienced Validation Engineer to drive silicon validation, characterization, and test automation for next-generation SoC products. Work with cross-functional teams, advanced lab equipment, and Python/LabVIEW-based automation in a highly innovative environment.\n\nYour role\nKey responsibilities in your new role\n\nDefine and develop test plans, test lists, and automation solutions for silicon validation and characterization.\nPerform validation on FPGA (pre-silicon) and silicon platforms, including debugging and issue resolution.\nDevelop software, firmware, and Python/LabVIEW-based automation frameworks for bench testing.\nCollaborate with validation, characterization, design, and firmware teams to ensure comprehensive test coverage.\nSupport silicon bring-up, characterization, and product qualification activities.\nCoordinate project schedules, track deliverables, and work with cross-functional stakeholders to achieve program milestones.\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor's or Master's degree in Electronics, Computer Science, or a related field.\n3-6 years of experience in silicon validation, bench characterization, or product engineering for Microcontroller and SoC products.\nHands-on experience in characterization and validation of Analog, Digital, and Mixed-Signal IPs.\nStrong expertise in using lab equipment such as SMUs, DMMs, oscilloscopes, and signal generators.\nGood programming skills in C and Python; LabVIEW experience is a strong advantage.\nSolid understanding of power management circuits, regulators, and reference voltage measurements.\nStrong analytical, debugging, and problem-solving skills.\nExcellent communication and interpersonal skills with the ability to collaborate effectively across global teams.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Staff Engineer Verification", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-08-04T04:00:11+00:00", "url": "https://jobs.infineon.com/careers/job/563808971791762", "is_hardware": true, "platform": "eightfold", "jd_text": "We're hiring a Silicon Validation Engineer with minimum 5 years of experience to work on FPGA and silicon validation, characterization, and test automation for advanced SoC and microcontroller products. The role requires hands-on experience with analog, digital, and mixed-signal validation, lab equipment, and programming in Python/C (LabVIEW is a plus). If you're passionate about debugging complex hardware-software interactions and collaborating with cross-functional teams.\n\nYour role\nKey responsibilities in your new role\n\nInterfacing with the silicon validation, char teams to understand the requirements. \nDevelop and build test list, automation suite including software and firmware for the silicon. \nValidation on FPGA (pre-silicon) and Silicon, working with the cross functional teams for debugging. \nPython/LabVIEW based bench test equipment automation to support silicon Val and Char testing. \nManage schedules and liaison with cross functional teams, when associated as a program manager.\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor's/Master's degree in Electronics, Computer Science, or related field of study. \n5-8 years of experience and understanding of microcontroller and SoC products. \nExperience in Bench Characterization with Analog, Digital, and Mixed signal IPs. \nHands-on experience in using lab equipment such as SMUs, DMMoscillo scopes and signal generators. \nGood understanding of C ,Python, LabVIEW language. LabVIEW knowledge will be a great plus. \nGood knowledge about regulators and reference measurements. \nExcellent communication and interpersonal skills\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nAnand Rawal", "jd_status": "stored"}, {"title": "Senior Engineer Verification", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-08-04T04:00:09+00:00", "url": "https://jobs.infineon.com/careers/job/private?pid=563808971791761", "is_hardware": true, "platform": "eightfold", "jd_text": "Passionate about silicon validation and test automation? We are seeking a skilled engineer with expertise in FPGA validation, lab instrumentation, Python/LabVIEW automation, and mixed-signal characterization to help bring next-generation products to life.\n\nYour role\nKey responsibilities in your new role\n\nCollaborate with Silicon Validation and Characterization teams to understand test requirements and project objectives.\n\nDevelop and maintain test plans, test suites, automation frameworks, software, and firmware for silicon validation activities.\nPerform validation on FPGA (pre-silicon) and silicon platforms, working closely with cross-functional teams to troubleshoot and resolve issues.\nDesign and implement Python/LabVIEW-based automation solutions for bench test equipment to support silicon validation and characterization testing.\nCoordinate project schedules and effectively collaborate with cross-functional stakeholders, including program management responsibilities when required.\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor's or Master's degree in Electronics, Computer Science, or a related field.\n\n3 to 6 years of experience with microcontrollers and SoC (System-on-Chip) products.\nExperience in bench characterization of Analog, Digital, and Mixed-Signal IPs.\nHands-on expertise with laboratory equipment, including SMUs, DMMs, oscilloscopes, and signal generators.\nProficiency in C, Python, and LabVIEW programming languages; LabVIEW experience is an added advantage.\nStrong knowledge of voltage regulators and reference measurement techniques.\nExcellent communication, collaboration, and interpersonal skills.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "DFT DV Engineer, AI Hardware", "company": "Tesla", "location": "Bengaluru, India ; India", "date_posted": "2026-08-04T02:30:00", "url": "https://hire-r1.mokahr.com/social-recruitment/tesla/100004142?#/job/41461324-2fa0-4f66-9129-a49a049961e2", "is_hardware": true, "platform": "mokahr", "jd_text": "Position Description\nThe Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life. \n\nTesla's AI hardware team is seeking a highly motivated ASIC RTL Design Engineer with a specialization in the mathematical and computational aspects of custom AI accelerators. You will focus on designing high-performance, power-efficient RTL for math-intensive components that power our AI training and inference systems. This role emphasizes expertise in tensor operations, matrix computations, and optimized data paths for advanced AI workloads.  This role is located in Bengaluru, India. If you are passionate about pushing the boundaries of low-precision arithmetic, quantization techniques, and hardware acceleration for machine learning, this is your opportunity to contribute to revolutionary AI hardware.  \n\nOur Silicon Engineering team validates DFT features from RTL through silicon bring-up — ensuring test structures work correctly before the chip reaches the tester. As a Staff DFT DV Engineer, you will own functional verification of all DFT structures at block and SoC level, delivering pre-Si testcases that directly enable silicon debug and ATE correlation. \n\nResponsibilities\nDevelop SystemVerilog/UVM testbenches to verify DFT features — SSN, compressed scan, memory BIST, JTAG, and boundary scan at block and SoC level \nVerify top-level DFT features — power-on self-test, clock observation, clock stop, and scan dump \nRun DV regressions, analyze coverage, triage and debug failures to closure \nIdentify design fixes and validate DFT RTL corrections \nDeliver pre-Si DV testcases for silicon bring-up and ATE correlation \nOwn post-silicon ATE test correlation — root cause discrepancies between pre-Si and silicon behavior \nLeverage agentic AI flows to automate regression execution, coverage analysis, and failure triage \n\nRequirements\nDegree in Electrical Engineering, Computer Engineering, or related field, or equivalent experience \n3+ years of DFT DV experience at block and SoC level \nExpert-level SystemVerilog and UVM testbench development \nHands-on verification of SSN, compressed scan, MBIST, JTAG, and boundary scan \nExperience delivering pre-Si testcases through silicon bring-up and ATE correlation \nAbility to use agentic AI flows to automate DV regression and debug workflows \nPost-silicon debug and ATE correlation experience on server-class SoCs \nFamiliarity with formal verification methods for DFT structural checks \nExperience with power-on self-test and clock control verification", "jd_status": "stored"}, {"title": "Staff EM & IR Engineer, Power Integrity, AI Hardware", "company": "Tesla", "location": "Bengaluru, India ; India", "date_posted": "2026-08-04T02:30:00", "url": "https://hire-r1.mokahr.com/social-recruitment/tesla/100004142?#/job/cf75be14-df60-4950-bd06-5bca2e51c256", "is_hardware": true, "platform": "mokahr", "jd_text": "Position Description\nThe Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life. Tesla's AI Hardware Team is looking for experienced, highly skilled VLSI engineers who enjoy working across the logic, circuit, methodology, and physical design levels. Our physical design team is growing to tackle a wider range of projects, building on our in-house SOC design expertise. This position entails the design, construction and integration of SOCs, IP, circuits, tool flows, and methodologies into systems using advanced technologies - from definition through characterization. \nOur AI Hardware engineering team is building some of the most complex SoCs. As a Staff EM/IR Engineer, you will own power grid architecture, EMIR signoff, and IR budget strategy across full-chip and multi-die designs. Your work directly determines whether silicon performs reliably at the power and frequency targets that matter — from individual compute blocks through the complete 3D stack. \n\nResponsibilities\nDesign and validate power grids for large SoCs — set IR budgets per compute block and enforce targets through implementation \nOwn signal EM and power EM analysis flows end-to-end, from block-level through full-chip signoff \nManage EMIR analysis across complex SoC hierarchies — triage violations, drive fixes, and own signoff closure \nPerform EM/IR analysis for 3D IC architectures including hybrid bonded and die-stacked designs — account for TSV current density, bond interface parasitics, and cross-die power delivery \nSet and validate IR drop budgets across the die stack including package and interposer contributions \nAnalyze package power integrity and signal integrity interactions — partner with packaging teams to align on PDN strategy \nDefine EMIR targets for compute blocks and validate convergence through tapeout \nLeverage AI agents to automate power grid analysis, violation triage, and EMIR reporting workflows \n\nRequirements\nDegree in Electrical Engineering, Computer Engineering, or related field, or equivalent work experience \n20+ years of EM/IR analysis and power grid design experience on high-performance SoCs \nDeep expertise in static and dynamic IR drop, electromigration (signal and power), and power grid validation \nHands-on proficiency with industry EMIR tools (RedHawk, Voltus, or equivalent) \nProven experience setting and managing IR budgets across large, multi-block SoC designs \nExperience with 3D IC EMIR analysis — hybrid bonding, die stacking, and TSV current density modeling \nUnderstanding of package PI/SI concepts and their impact on on-die power delivery \nAbility to use AI agents to automate and scale EMIR flows across complex design hierarchies", "jd_status": "stored"}, {"title": "Staff SoC Product & Test Engineer, AI Hardware", "company": "Tesla", "location": "Bengaluru, India ; India", "date_posted": "2026-08-04T02:30:00", "url": "https://hire-r1.mokahr.com/social-recruitment/tesla/100004142?#/job/442484be-69d6-4361-8592-1bac9bb6b02f", "is_hardware": true, "platform": "mokahr", "jd_text": "Position Description\nThe Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life. \n\nTesla's AI hardware team is seeking a highly motivated ASIC RTL Design Engineer with a specialization in the mathematical and computational aspects of custom AI accelerators. You will focus on designing high-performance, power-efficient RTL for math-intensive components that power our AI training and inference systems. This role emphasizes expertise in tensor operations, matrix computations, and optimized data paths for advanced AI workloads.  This role is located in Bengaluru, India. If you are passionate about pushing the boundaries of low-precision arithmetic, quantization techniques, and hardware acceleration for machine learning, this is your opportunity to contribute to revolutionary AI hardware. \n\nOur Silicon Engineering team takes chips from first silicon through volume production — owning characterization, yield, diagnostics, and IP test. As a Staff SoC Product and Test Engineer, you will own the full arc from NPI bring-up and performance characterization through production yield optimization and IP-level test content, ensuring every product ships at validated quality and performance. \n\nResponsibilities\nDefine characterization plans for processor cores and IPs — develop NPI performance stress tests across process, voltage, and temperature \nPerform and correlate measurements across ATE and SLT platforms over volume — define guard bands and drive corrective actions for test platform alignment \nDevelop solutions to set optimal system voltage and frequency operating points — align from manufacturing screen through system operation \nOwn silicon bring-up — execute structural, functional, and parametric tests; debug failures and quantify performance shifts using accelerated stress \nAnalyze volume production data — identify and implement solutions to improve yield and throughput \nArchitect and deploy volume diagnostic data processing pipelines for SoC logic and memory \nIntegrate AI-based deep learning techniques to improve diagnostics convergence, fault isolation, and failure analysis success rates \nDrive defect reduction with foundry partners — build defect paretos, recommend FA candidates, and validate improvements from process changes \nDevelop models to predict yield trends, detect anomalies, and drive corrective actions \nRoot cause qualification fails and field returns — develop new test content targeting identified fault types \n\nRequirements\nDegree in Electrical Engineering, Computer Engineering, or related field, or equivalent experience \n10+ years across SoC characterization, yield, diagnostics, and IP test engineering \nHands-on experience across ATE, SLT, and bench platforms \nDeep expertise in PVT characterization, guard band definition, and ATE/SLT correlation \nExperience with diagnostic data pipelines and AI/ML-based fault isolation techniques \nIP test development experience for High-Speed IO and Mixed Signal IPs \nAbility to use agentic AI flows to automate yield analysis, diagnostics, and test optimization", "jd_status": "stored"}, {"title": "Sr. Clock Distribution Engineer, AI Hardware", "company": "Tesla", "location": "Bengaluru, India ; India", "date_posted": "2026-08-04T02:30:00", "url": "https://hire-r1.mokahr.com/social-recruitment/tesla/100004142?#/job/51226d09-99b3-44a8-8e2a-0e88835be0be", "is_hardware": true, "platform": "mokahr", "jd_text": "Position Description\nThe Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life. Tesla's AI Hardware Team is looking for experienced, highly skilled VLSI engineers who enjoy working across the logic, circuit, methodology, and physical design levels. Our physical design team is growing to tackle a wider range of projects, building on our in-house SOC design expertise. This position entails the design, construction and integration of SOCs, IP, circuits, tool flows, and methodologies into systems using advanced technologies - from definition through characterization. \nOur AI Hardware engineering team implements world-class clocking for high-performance SoCs where skew directly impacts chip performance. As a Sr. Clock Distribution Engineer, you will own the physical implementation of clock distribution networks — designing H-trees, driving floorplan-stage clock planning in Innovus, and pushing skew to the limits of what the process allows. Your work bridges clock architecture intent and physical reality. \n\nResponsibilities\nDesign and implement H-tree clock distribution networks — plan topology, trunk routing, and branch balancing to minimize skew across the full clock domain \nOwn clock planning at the floorplan stage in Innovus — place clock roots, define clock trunk paths, and establish pre-CTS constraints that guide downstream implementation \nDrive skew optimization from floorplan through CTS closure — iterate on H-tree structure, buffer placement, and load balancing to meet skew targets \nSize clock drivers and buffers — analyze drive strength requirements and validate EMIR compliance for large clock drivers under peak switching current conditions \nEvaluate EM and IR impact of high-fanout clock networks — ensure clock trunk and driver sizing meets electromigration current density limits and IR drop budgets \nDevelop CTS constraints and guidelines — define skew groups, clock latency targets, and insertion delay budgets for the CTS engine \nValidate clock distribution against post-route parasitics — analyze skew degradation and drive ECO fixes to recover timing \nImplement clock shielding strategies to protect clock trunks from aggressor coupling and noise \nAnalyze and optimize clock power — balance transition times, driver strengths, and switching activity for power efficiency \nLeverage agentic AI flows to automate H-tree generation, skew analysis, and EMIR validation across clock domains \n\nRequirements\nDegree in Electrical Engineering, Computer Engineering, or related field, or equivalent work experience \n7+ years of clock distribution implementation experience on high-performance SoCs \nDeep expertise in H-tree clock topology design and skew optimization \nHands-on proficiency with Innovus for floorplan-stage clock planning and CTS implementation \nStrong understanding of EMIR concepts as applied to large clock drivers and high-fanout clock networks \nExperience sizing clock drivers for EM compliance under peak switching conditions \nSolid grasp of pre-CTS planning, CTS constraints, and post-route skew validation \nAbility to use agentic AI flows to automate clock distribution analysis and optimization", "jd_status": "stored"}, {"title": "Staff CAD Flow Engineer, Physical Implementation & Sign Off, AI Hardware", "company": "Tesla", "location": "Bengaluru, India ; India", "date_posted": "2026-08-04T02:30:00", "url": "https://hire-r1.mokahr.com/social-recruitment/tesla/100004142?#/job/14cbb961-fbc1-4102-b3f6-ec5377643c26", "is_hardware": true, "platform": "mokahr", "jd_text": "Position Description\nThe Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life. Tesla's AI Hardware Team is looking for experienced, highly skilled VLSI engineers who enjoy working across the logic, circuit, methodology, and physical design levels. Our physical design team is growing to tackle a wider range of projects, building on our in-house SOC design expertise. This position entails the design, construction and integration of SOCs, IP, circuits, tool flows, and methodologies into systems using advanced technologies - from definition through characterization. \nOur AI Hardware engineering team builds and maintains the end-to-end CAD infrastructure that powers tapeout for complex SoC and 3D IC designs. As a Staff CAD Flow Engineer, you will own the development, deployment, and continuous improvement of implementation and signoff flows — from RTL to GDS. You will be at the center of how we scale design productivity and PPA optimization using agentic AI-driven flows. \n\nResponsibilities\nBuild and maintain RTL-to-GDS implementation flows including synthesis, placement, routing, and signoff integration \nOwn CTS flow development and optimization — tune clock tree strategies to achieve PPA targets across frequency, power, and area \nDevelop and manage ECO flows — functional ECOs, timing ECOs, and metal-only ECOs — with robust LEC validation at each stage \nSet up and validate electrical analysis flows including static/dynamic IR drop, EM, and power analysis integration within the implementation flow \nDevelop power intent flows — implement and validate UPF/CPF-driven multi-voltage domain strategies through synthesis and P&R \nMaintain parasitic extraction flows and ensure correlation between implementation and signoff tools \nBuild MMMC timing flows — manage corner and mode configuration for setup, hold, and signoff convergence \nIntegrate physical verification (DRC/LVS) and formal equivalence checking (LEC) as continuous checkpoints within the flow \nDevelop and deploy agentic AI flows to automate flow execution, detect bottlenecks, triage violations, and drive closure decisions without manual intervention \nEvaluate and adopt new EDA tool capabilities — drive tool bring-up, qualification, and regression benchmarking \n\nRequirements\nDegree in Electrical Engineering, Computer Engineering, or related field, or equivalent work experience \n5+ years of CAD flow development and physical implementation experience on complex SoCs \nDeep expertise in CTS methodologies and clock architecture optimization for PPA \nHands-on experience with industry P&R and synthesis tools (Innovus, Genus, Fusion Compiler, or equivalent) \nStrong command of ECO methodologies — timing, functional, and metal ECO flows through tapeout \nExperience building power analysis and power intent flows (UPF/CPF, multi-voltage) \nProficiency with signoff integration — STA, EMIR, DRC/LVS, and parasitic extraction within a unified flow \nAbility to develop, deploy, and scale agentic AI flows for design automation and autonomous closure", "jd_status": "stored"}, {"title": "Staff STA Engineer, Timing Sign Off, AI Hardware", "company": "Tesla", "location": "Bengaluru, India ; India", "date_posted": "2026-08-04T02:30:00", "url": "https://hire-r1.mokahr.com/social-recruitment/tesla/100004142?#/job/6c554ada-4e42-4a13-a0f2-57b623f92c8f", "is_hardware": true, "platform": "mokahr", "jd_text": "Position Description\nThe Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life. Tesla's AI Hardware Team is looking for experienced, highly skilled VLSI engineers who enjoy working across the logic, circuit, methodology, and physical design levels. Our physical design team is growing to tackle a wider range of projects, building on our in-house SOC design expertise. This position entails the design, construction and integration of SOCs, IP, circuits, tool flows, and methodologies into systems using advanced technologies - from definition through characterization. \nOur AI Hardware engineering team is pushing the boundaries of advanced SoC design at 3nm and below. As a STA Engineer, you will own timing signoff from block-level through full-chip tapeout — including die-to-die interfaces across TSV-based 3D stacks. This is a high-impact role where timing convergence directly determines product readiness. \n\nResponsibilities\nDrive full-chip and block-level STA across all PVT corners and modes (MMMC) \nOwn timing closure — identify and resolve setup/hold violations, clock skew, crosstalk, IR drop, and process variation impacts \nDevelop, maintain, and validate timing constraints for complex SoC/ASIC designs \nLead signoff timing analysis using industry-standard EDA tools \nExecute and support ECO implementation for timing fixes through tapeout \nPerform timing analysis for 3D IC architectures across TSV interconnects — model parasitics (RC delay, coupling), validate cross-die clock distribution, and address latency and synchronization across dies \nAnalyze thermal and voltage impacts on TSV timing paths \nValidate timing across interposer and multi-die communication paths (DDR, PCIe, SerDes) \nLeverage AI agents to automate timing debug, constraint validation, and signoff workflows\n\nRequirements\nDegree in Electrical Engineering, Computer Engineering, or related field, or equivalent work experience \n7+ years in STA and timing signoff \nDeep expertise in timing fundamentals: setup/hold, skew, jitter, latency, MMMC methodology \nHands-on experience with industry STA signoff tools \nExperience at advanced nodes (5nm and below) \nAbility to use AI agents to automate and accelerate timing analysis workflows", "jd_status": "stored"}, {"title": "Staff Physical Verification Engineer", "company": "Tesla", "location": "Bengaluru, India ; India", "date_posted": "2026-08-04T02:30:00", "url": "https://hire-r1.mokahr.com/social-recruitment/tesla/100004142?#/job/cc1b7c8d-9354-4a71-822e-867829cb1c93", "is_hardware": true, "platform": "mokahr", "jd_text": "Position Description\nThe Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life. Tesla's AI Hardware Team is looking for experienced, highly skilled VLSI engineers who enjoy working across the logic, circuit, methodology, and physical design levels. Our physical design team is growing to tackle a wider range of projects, building on our in-house SOC design expertise. This position entails the design, construction and integration of SOCs, IP, circuits, tool flows, and methodologies into systems using advanced technologies - from definition through characterization. \n\nOur AI Hardware engineering team is taping out complex SoCs at advanced nodes. As a Staff Physical Verification Engineer, you will own the physical verification signoff flow end-to-end — from DRC and LVS through ESD and antenna — ensuring every design meets foundry requirements before tapeout. This role sits at the critical intersection of design correctness and manufacturability. \n\nResponsibilities\nOwn and execute full-chip DRC, LVS, ESD, and antenna signoff using Calibre, ICV, or Pegasus \nDevelop, maintain, and optimize physical verification flows for advanced node SoC and 3D IC designs \nInterpret and implement foundry Design Rule Manuals (DRM) — translate rule updates into verified flow changes \nDebug and resolve complex DRC/LVS violations across hierarchical full-chip designs \nPerform ESD verification — validate protection strategies, current paths, and CDM/HBM compliance \nDrive tapeout readiness by coordinating signoff across block and top-level design teams \nEngage directly with foundry teams to resolve DRM ambiguities and waiver requests \nLeverage AI agents to automate rule deck validation, violation triage, and signoff reporting workflows \n\nRequirements\nDegree in Electrical Engineering, Computer Engineering, or related field, or equivalent work experience \n7+ years in physical verification with full signoff ownership \nDeep expertise in DRC, LVS, and ESD verification methodologies \nHands-on proficiency with Calibre, ICV (IC Validator), or Pegasus \nDirect foundry DRM experience — able to read, interpret, and implement complex rule decks \nExperience at advanced nodes (4nm and below) \nAbility to use AI agents to drive automation across verification flows and tapeout signoff", "jd_status": "stored"}, {"title": "RTL Design(Audio) - Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-04T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720185992", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    5+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Engineer - Analog Design", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-08-04T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/43363930", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nResponsibilities will include, but are not limited to:\nDesign, implementation and integration of complex analog circuits such as CMOS Amplifiers, Comparators, Bandgap References, LDOs, Charge Pumps, Oscillators, DLL, IO Buffers, Analog Test Mux, Process Monitor, and Temperature sensors for advanced DRAM products.\nDesign, implementation and integration of synchronous and asynchronous custom digital block\nContributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Analog/Memory/Logic circuits.\nParasitic modeling and design validation, reticle experiments and required tape-out revisions.\nOverseeing and managing the layout process including floor-planning, placement, and routing\nPerforming verification processes with modeling and simulation using industry standard simulators\nContributing to cross group communication to work towards standardization and group success.\nWorking with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product.\nProactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality.\nMentor and lead young designers.\nStrong AI proficiency, a solid understanding of agentic AI models, and effective use of tools such as Claude are expected to significantly improve engineering efficiency, enhance PPA (Power, Performance, Area) optimization, and accelerate overall delivery timelines.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "SOC Design Verification Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-04", "url": "https://careers.arm.com/job/bengaluru/soc-design-verification-engineer/33099/98735647568", "is_hardware": true, "platform": "talentbrew", "jd_text": "SoC Design Verification Engineer\nAbout Solutions SoC Engineering\nJoin the Solutions SoC Engineering organization and help shape the future of silicon. We are building a world-class engineering organization focused on delivering innovative, high-performance, and energy-efficient SoC solutions that power next-generation computing across diverse markets.\n\nAs a rapidly growing global team, we bring together expertise across architecture, design, verification, emulation, FPGA, software, and post-silicon validation to deliver first-time-right silicon. Our engineers solve some of the industry's most challenging engineering problems using advanced verification methodologies, automation, and AI-driven tools while maintaining the highest standards of quality and execution.\n\nOur culture is built on technical excellence, ownership, collaboration, and continuous learning. We invest in our people, encourage innovation, and provide opportunities to influence engineering methodologies, contribute across the product lifecycle, and grow alongside an organization that is defining the future of SoC engineering.\nRole Overview\nAs a Design Verification Engineer, you will verify complex Arm-based IPs, subsystems, and SoCs powering next-generation computing platforms. You will develop scalable verification solutions, own end-to-end verification execution, and contribute to advanced SoC methodologies.\nKey Responsibilities\nDevelop and execute verification strategies for IP, subsystem, and SoC designs.\nVerify CPU, PCIe, DDR, Security, coherency, memory subsystem, and interconnect functionality.\nPerform power-aware verification and system scenario/performance validation.\nOwn verification deliverables from planning through verification closure while ensuring quality, schedule, and execution commitments are met.\nArchitect, develop, and maintain reusable verification environments, verification IPs, methodologies, and automation.\nDevelop verification plans, test methodologies, test cases, and coverage closure strategies.\nDrive functional, code, toggle, assertion, and coverage closure.\nDebug RTL, testbench, integration, and system-level issues.\nCollaborate with architecture, design, firmware, emulation, FPGA, validation, and post-silicon teams.\nLeverage automation, scripting, and AI-assisted workflows to improve verification productivity. \nContribute to methodology improvements, documentation, and engineering best practices\n\nRequired Skills and Qualifications\nBachelor's or Master's degree in a relevant engineering discipline.\n2–4 years of IP, subsystem, or SoC verification experience.\nStrong Verilog, SystemVerilog, UVM, and modern verification methodologies.\nExperience with Arm-based SoC architecture, coherency, interconnects, memory hierarchy, and UPF.\nExperience with C/C++, scripting, coverage closure, and strong RTL/testbench debug.\nExcellent analytical, communication, and collaboration skills.\nDesired Skills and Qualifications\nExperience with CHI, ACE, AMBA, PCIe, DDR, or Security IP.\nArm System Architecture knowledge.\nAssembly programming.\nFormal verification, emulation, FPGA, gate-level simulation, or post-silicon validation.\nAI-assisted verification and globally distributed engineering experience.\n\n \n \n \n#LI-PS1\nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Physical Design Engineer, Staff", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-04", "url": "https://careers.synopsys.com/job/bengaluru/physical-design-engineer-staff/44408/96302724416", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in physical design and timing closure, and you know that the difference between a chip that tapes out clean and one that comes back with yield issues is usually a decision made during floorplanning or a timing corner someone didn't validate hard enough. You are the engineer who catches those decisions before they become expensive problems. Working across advanced nodes like 5nm, 3nm, and beyond doesn't intimidate you because you have been there, debugged the DRC violations at 2am, closed timing on a block everyone said was impossible, and learned what actually matters versus what just looks good in a review slide. You do not wait for perfect specs. When the RTL drops and the constraints are half-baked, you start asking the right questions, build your SDC from first principles, and move forward. At Synopsys, you will work on silicon lifecycle monitors that actually ship in automotive and consumer products.\nWhat You'll Be Doing\nDesign and implement RTL to GDS flows for on-chip silicon lifecycle monitors including process, voltage, temperature, glitch, and droop sensors\nOwn digital backend from synthesis through tapeout: floorplanning, power planning, multivoltage design with UPF and VCLP, placement, CTS, and routing\nDevelop and close pre-layout and post-layout STA across multiple corners using PrimeTime and PrimeTime PX, including SDC creation and timing ECO generation\nExecute physical verification and signoff: DRC, LVS, PERC, ERC, antenna checks, EMIR, and power signoff using ICV and RedHawk\nBuild and refine design flows in collaboration with architecture and circuit teams, scripting automation in TCL and Perl\nGenerate timing and DRV ECOs for closure, working iteratively to meet PPA targets on advanced FinFET and GAA nodes\nThe Impact You Will Have\nEnable next-generation intelligent sensors that monitor silicon health in real time, improving product reliability in automotive and consumer markets\nDrive tapeout success on advanced nodes by delivering clean, timing-closed designs that meet aggressive PPA and yield targets\nBuild reusable methodologies that accelerate physical design execution across multiple product teams at Synopsys\nReduce risk and schedule slip by catching design issues early through rigorous analysis and signoff discipline\nContribute to the differentiation of Synopsys IP products by embedding best-in-class physical design practices\nInfluence tooling and flow improvements that benefit the broader Synopsys design community\nWhat You'll Need\nBachelor's or Master's in Electrical Engineering with 5+ years in physical design, physical verification, and STA at IP, block, or full-chip level\nProven tapeout success on advanced nodes: 14nm, 10nm, 7nm, 5nm, 3nm, or 2nm\nStrong experience with DRC, LVS, DFM cleaning, and generating ECOs for DRV and timing closure\nProficiency with Synopsys tools: Fusion Compiler, VCLP, PrimeTime, PrimeTime PX, ICV, and RedHawk\nSolid understanding of multivoltage design, UPF, SDC constraints, OCV, POCV, derates, and crosstalk\nExperience scripting in TCL and Perl to automate flows and customize methodologies\nWho You Are\nYou can spot a floorplan that will fail timing in two weeks and explain exactly why in terms the team can act on immediately\nDetail-oriented enough to catch a single missing mode in an SDC file, but pragmatic enough to know when a 2ps margin is good enough\nComfortable working independently to debug a tricky LVS issue, but quick to pull in the right people when the problem is bigger than one domain\nYou push back when a constraint set doesn't match the actual use case because you care about the quality of what ships\nAble to context-switch between synthesis strategy, post-route timing debug, and power grid analysis without losing momentum\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Electrical Engineer 2", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-08-04", "url": "https://careers.skyworksinc.com/job/Electrical-Engineer-2/78030", "is_hardware": true, "platform": "successfactors", "jd_text": null, "jd_status": "source_unavailable"}, {"title": "Senior Director Design Manager", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-08-04", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Senior-Director-Design-Manager_R264571", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nSoC Design Manager / Product Lead\n\nRole Overview\n\nADI is seeking a highly experienced SoC Design Manager / Product Lead to lead the end-to-end execution of complex SoC and processor programs from concept to commercialization.\n\nThis role combines the responsibilities of a Chip Lead, Technical Program Leader, and Business Stakeholder Manager, owning overall product execution across architecture, silicon, software, validation, and business teams. The ideal candidate will drive cross-functional alignment, manage technical and program risk, engage with customers, and ensure successful product delivery.\n\nKey Responsibilities\nOwn complete SoC development from architecture through tape-out, silicon bring-up, production ramp, and commercialization.\nProvide technical leadership across architecture, RTL design, verification, DFT, physical design, software, and post-silicon activities.\nDrive program execution, schedules, staffing plans, risk management, and milestone delivery.\nLead critical trade-off decisions involving performance, power, area, cost, quality, features, and schedule.\nPartner with software, systems, product, and business teams to ensure strong hardware-software co-design.\nServe as the primary interface for customers, business units, and senior leadership on execution-related matters.\nSupport customer engagements and product vertical customer visits as needed.\nInfluence and align globally distributed teams across engineering, software, operations, product management, and business functions.\nDrive production readiness, go-to-market planning, and successful product commercialization.\n\nQualifications\nBS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field.\n20+ years of semiconductor industry experience, including leadership of complex SoC/ASIC/Processor development programs.\nProven track record of multiple successful silicon tape-outs and product commercialization.\nStrong expertise in SoC architecture, digital design, verification, DFT, physical design, silicon validation, and manufacturing.\nExperience leading large cross-functional teams and influencing without direct authority.\nStrong customer-facing, stakeholder management, communication, and problem-solving skills.\n\nSuccess Criteria\nSuccessful first-time tape-out and commercialization of complex SoCs.\nPredictable program execution with effective risk management.\nStrong hardware-software alignment throughout the development lifecycle.\nSuccessful delivery of customer, product, and business objectives.\nExecutive confidence through clear communication and stakeholder leadership.\nAlignment of diverse teams around a common product vision and execution strategy.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Controls Engineer", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2026-08-04", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/Controls-Engineer_R2624590", "is_hardware": true, "platform": "workday", "jd_text": "Who We Are\n\nApplied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips – the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world – like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world. \n\nWhat We Offer\n\nLocation:\nBangalore,IND\nYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. \n\nAt Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. \n \n \nAs an Electrical Engineer, you are responsible for designing, modifying, and troubleshooting electrical or electronic engineering assemblies, layouts, schematics, and drawings to advance the equipment that supports our technology. Using your technical experience and critical thinking skills, you will perform engineering analysis, generate test reports, develop innovative solutions, and create documentation for product releases. You will also coordinate the procurement and assembly of components, identify sources of critical parts, and resolve technical issues to ensure peak performance. \n \nRole Responsibilities: \nDesign or modify electrical or electronic engineering assemblies, layouts, schematics, drawings or specifications of moderate scope under general supervision \n\nPerform basic engineering analysis under general supervision \n\nPerform and generate basic engineering test reports; generate related alpha/gamma documentation for product releases \n\nCoordinate the procurement and assembly of electrical or electronic components and equipment, and identify sources of critical parts and subsystems to resolve technical issues \n\nTroubleshoot a variety of moderately complex electrical problems \n\nImplement concepts for product issues and electrical solutions of moderate difficulty \n\nAssist in the development of electrical product specifications \n\nClearly communicate complex information in straightforward situations\n\nMinimum Qualifications:\nBachelor’s degree\n\n2-4 years of related experience\n\nPreferred Qualifications:\nA solid understanding of the industry’s key business drivers  \n\nGood communication/interpersonal skills to explain complex information to others   \n\nAnalog & Digital circuit design using ADC, DAC, Op-amps, Transistors, MOSFETS, Sensors, Signal Conditioning circuits, microcontroller/ Microprocessor, Memories, Various communication interfaces (I2C,SPI, RS485,Ethernet), IOT platforms\nObsolescence process, Customer support for field issues, Interact with suppliers\nHand on experience on testing tools (DSO, DMM,FG, electronic loads etc.) circuit validation,  board bring up, functional testing , trouble shooting, Failure analysis\n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nAssignee / Regular\nTravel:\nYes, 10% of the Time\nRelocation Eligible:\nYes\n\nApplied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "Application Engineering Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-04", "url": "https://careers.synopsys.com/job/bengaluru/application-engineering-staff-engineer/44408/98783835168", "is_hardware": true, "platform": "talentbrew", "jd_text": "Alternate Job Titles:\nStaff Implementation Application Engineer\nPhysical Design Application Engineer\nSenior EDA Solutions Engineer\nRTL-to-GDS Application Specialist\nWe Are:\nAt Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules.\nYou Are:\nYou are a highly skilled and passionate engineer with a strong background in physical implementation, particularly RTL-to-GDS flows. With over six years of hands-on experience, you have developed deep expertise in autonomously diagnosing and resolving synthesis and place-and-route (PnR) challenges. Your command of scripting languages such as Tcl, Unix, and Perl, along with your in-depth knowledge of Synopsys implementation tools, sets you apart as a technical leader in the field. You are adept at collaborating with both customers and internal teams, leveraging your exceptional communication skills to ensure precise and attentive fulfillment of complex requirements. \n \n Driven by curiosity and a self-starting attitude, you thrive in dynamic environments where you can advocate for customers and represent innovative products. You are known for your collaborative approach, working seamlessly with colleagues across functions to deliver best-in-class solutions. Your ability to translate technical insights into actionable requirements for R&D teams is crucial to advancing Synopsys’ solution capabilities and driving continuous innovation. \n \n You value inclusion and diversity, recognizing that a wide range of perspectives leads to better problem-solving and more impactful results. Your experience spans multiple chip tape-outs, preferably at advanced nodes such as 7nm or below, across various foundries. You are eager to contribute to flagship customer projects, participate in technical campaigns, and expand your expertise as part of a world-class engineering team committed to shaping the future of silicon design.\nWhat You’ll Be Doing:\nDriving global customer adoption of Synopsys Implementation products by providing expert guidance on RTL-to-GDS flows.\nDelivering comprehensive technical support and solutions for premium customer projects, including hands-on debugging and on-site expert visits when required.\nParticipating in technical campaigns such as benchmarks, deployments, and flow enablement to improve usability and adoption of new solutions.\nAdvocating for customers by communicating their needs and feedback to product development teams, influencing product roadmaps and future technologies.\nContributing to Synopsys’ Knowledge Base with technical articles that provide self-help guidance and front-line support to customers.\nRolling out new product methodologies through training sessions and ongoing technical support to ensure customer success.\nCollaborating with R&D teams to translate customer challenges into innovative solutions that advance Synopsys’ technology leadership.\nThe Impact You Will Have:\nDelivering comprehensive support and effective technical solutions in key customer flagship projects to ensure project success and satisfaction.\nDriving deployment of new flows to achieve better power, performance, and area (PPA) while taking ownership of block-level activities to improve quality of results (QoR).\nEnabling seamless EDA transitions for customers, optimizing their outcomes and strengthening long-term partnerships.\nPromoting Synopsys tools and solutions to grow market presence and fuel adoption of next-generation technologies.\nAddressing and overcoming complex design challenges, supporting innovation, and improving product performance based on real-world feedback.\nEnhancing internal knowledge sharing by developing technical resources and mentoring team members.\nWhat You’ll Need:\nB-Tech or equivalent with a minimum of 6+ years of experience, or M-Tech or equivalent with a minimum of 4+ years of experience in physical implementation.\nDeep expertise in implementation methodologies, physical design, and Synopsys tools such as Fusion Compiler or ICC-II (or equivalent).\nThorough understanding of RTL-to-GDS flows, methodologies, and challenges.\nProficiency in scripting languages including Tcl, Perl, and Unix; knowledge of Python is a strong advantage.\nExperience in static timing analysis (STA), low power flows, and design planning.\nProven track record of participating in multiple chip tape-outs, ideally at 7nm or lower nodes across various foundries.\nExcellent verbal and written communication skills; prior customer-facing experience is a plus.\nWho You Are:\nPassionate about delivering world-class customer service and technical excellence.\nAn effective communicator, able to engage with stakeholders at all levels and translate complex technical concepts into actionable insights.\nCollaborative and inclusive, thriving in diverse teams and valuing different perspectives.\nSelf-motivated, detail-oriented, and able to work independently on complex challenges.\nCurious, innovative, and eager to drive technological advancement in the field of silicon design.\nThe Team You’ll Be A Part Of:\nYou will join Synopsys’ Silicon Design & Verification team—a group of passionate, high-performing engineers dedicated to delivering cutting-edge solutions and world-class support. Our team partners closely with R&D, product management, and sales to drive customer success, innovate on next-generation chip design methodologies, and ensure Synopsys remains the industry leader. We foster a collaborative, inclusive environment where knowledge sharing and continuous learning are fundamental, and where every team member’s contributions are valued.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Tech Lead, Formal Verification", "company": "Astera Labs", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-08-03T14:23:59-04:00", "url": "https://job-boards.greenhouse.io/asteralabs/jobs/4720768005", "is_hardware": true, "platform": "greenhouse", "jd_text": "Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\n\nWe are looking for a Tech Lead, Formal Verification Engineer with 5–10 years of experience to lead formal verification efforts for complex IP and SoC designs. The ideal candidate will have deep expertise in assertion-based verification, property checking, formal proof methodologies, and advanced verification tools. This role requires close collaboration with Architecture, RTL Design, and Design Verification teams to ensure first-pass silicon success for Astera Labs' next-generation connectivity and AI infrastructure products.\n\n \n\nKey Responsibilities \n\nDevelop comprehensive formal verification plans from architecture and design specifications by identifying critical design properties, protocol requirements, and micro-architectural invariants.\n\nDevelop and execute formal verification environments, assertions, properties, and checkers.\n\nDrive proof convergence through advanced abstraction and complexity reduction techniques.\n\nCollaborate with RTL designers, architects, and verification teams to understand design intent and verification requirements.\n\nEvaluate, deploy, and scale formal verification methodologies, flows, and tools across projects.\n\nImprove verification productivity through reusable methodologies, automation, and best practices.\n\nEnsure comprehensive design correctness and provide technical leadership and mentorship across multiple projects.\n\nDrive bug triage, root-cause analysis, and resolution in collaboration with cross-functional teams.\n\nSupport project planning by estimating verification effort, tracking execution progress, identifying risks, and driving mitigation plans.\n\nParticipate in design reviews and contribute to verification sign-off strategies and quality metrics.\n\nPromote assertion-driven design practices and formal verification adoption across engineering teams.\n\n \n\nRequired Qualifications \n\nBachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field. \n\n5-10 experience in semiconductor verification, including significant formal verification experience.\n\nExpert knowledge of SystemVerilog, SVA,Verification planning & closure and ABV verification techniques. \n\nHands-on experience with one or more formal verification tools – JG, VCF preferably. \n\nExperience verifying complex protocols, control logic, and SoC or subsystem-level designs. \n\nStrong scripting skills in Python, Perl, Tcl, or Shell.\n\nExcellent analytical, debugging, and problem-solving capabilities\n\nExperience leading technical efforts or mentoring team members. \n\nStrong communication and cross-functional collaboration skills. \n\n \n\nPreferred Qualifications\n\nExperience with industry-standard formal verification tools such as JasperGold, VC Formal, or equivalent solutions.\n\nExperience verifying high-speed protocols and interfaces including PCIe®, UALink™, CXL®, Ethernet, SerDes, or related technologies.\n\nKnowledge of NoC architectures, cache coherency protocols, memory subsystems, and interconnect fabrics.\n\nExperience with formal bug hunting, proof-based verification, and coverage-driven verification methodologies.\n\nPrior experience leading technical teams and mentoring engineers.\n\nExposure to simulation, emulation, and the broader verification lifecycle is a plus.\n\nTrack record of contributing to successful silicon tape-outs.\n\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.", "jd_status": "stored"}, {"title": "IP Verification Lead", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-08-03T08:55:00+00:00", "url": "https://global-external-amd.icims.com/jobs/86228/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. MTS SILICON DESIGN ENGINEER    THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.     THE PERSON:  You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.   KEY RESPONSIBILITIES:  Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues  Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements   PREFERRED EXPERIENCE:  Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools  Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++   Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment.   Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience.   Scripting language experience: Perl, Ruby, Makefile, shell preferred.   Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions.     ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-NS1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Hardware Security Architect – Staff / Senior Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-08-03T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720243267", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Systems Engineering\nGeneral Summary:\nJob Description\n\nIn this position you will join the team responsible for the security architecture of Qualcomm Snapdragon processors. The team works at a system level spanning across hardware, software and infrastructure while striving for industry-leading solutions. This team interacts with product management, customers (e.g., OEMs), partners, HW/SW engineering, and Services engineering teams to find the optimal Security solution. Snapdragon processors are utilized in a variety of devices, including mobile phones, laptops, automotive systems, and data centers, each with distinct security needs. These processors are engineered to address most of these requirements, encompassing a wide range of security technologies found in consumer electronics, such as Root of Trust, Integrated Secure Element, Virtualization, and Confidential Compute.\n\nMinimum Qualifications\n10+ years industry experience in SoC Security encompassing both architecture and design\n\n5+ years industry experience in Compute and/or Data Centre SoC Architecture\n\nDemonstrated expertise in Security Technologies (Root of Trust, TEE, Access Control, I/O Security)\n\nProficient in Confidential Compute Architecture (RME, TDX, SEV-SNP, TDISP)\n\nStrong understanding of Security Software Architecture for Compute and Data Centers, with a focus on Secure Boot.\n\nSkilled in HW/SW threat analysis\n\nStrong capabilities in creating and presenting architecture-level documentation.\n\nPreferred Qualifications\nProficient in isolation-related extensions, including TrustZone, Virtualization, and RME.\n\nExtensive knowledge of Server Platform security architecture covering lifecycle/debug management, provisioning, attestation/measurement.\n\nExpertise in Applied Cryptography and Protocols.\n\nKnowledgeable about Security Certification Processes and Requirements (such as OCP)\n\nExcellent communication and teamwork skills.\n\nLeadership and management experience at the project level\n\nKey Responsibilities\nEstablish system security requirements (both hardware and software) for Server SoC focusing on functionality, performance, and security levels.\n\nSpecify and review the architecture and implementation of System/SoC level security mechanisms.\n\nConduct platform security threat analysis.\n\nPerform competitive analysis of security systems and features\n\nExplore future and roadmap server security-related technologies.\n\nServe as the technical interface to product management and standards teams.\n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.\n                                                                    OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience.\n                                                                    OR\nPhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Memory Layout Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-08-03", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Memory-Layout-Design-Engineer_R026735", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nJob Requirements:\nMinimum 8+ years of experience with a Bachelor's degree or 6+ years of experience with a Master's degree, strong layout knowledge.\nProficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - Calibre & Hercules).\nStrong layout knowledge in advanced submicron FinFET processes, including  TSMC 5nm, 3nm, 2nm, A14 or Samsung lower FinFET nodes.\n\nKey Responsibilities:\nUnderstand and apply layout guidelines, new process rules, and technical requirements for high-quality layouts.\nManage scheduling, timelines, and layout floor-planning.\nEnsure end-to-end deliverables are completed with high quality and within the planned schedule.\nAdapt quickly to new methodologies and communicate effectively with the SOC and library teams.\n\nSkill Set(Memory):\nProven ability to manage schedules, timelines, and end-to-end deliverables.\nExperienced in leading teams, training junior engineers, and documenting layout methodologies and guidelines.\nProficient in Cadence tools, including Virtuoso Layout, Layout XL, VXL, EXL, and Cadence Schematic Capture.\nStrong experience in memory layout design and physical verification (LVS, DRC, ERC, Antenna, Electro Migration) in CMOS processes.\nExtensive experience with physical verification tools such as Calibre and Hercules (DRC, LVS, ERC, Antenna, and Softcheck Errors).\nProficiency in floor-planning, hierarchy layout, and chip integration.\nSolid understanding of memory architecture and RC requirements, with the ability to plan signal and power routing.\nAbility to lead teams, train junior engineers, and manage projects effectively.\nStrong knowledge of memory layout topology; experience with memory compilers is preferred.\nKnowledge of AI, layout automation, and script/SKILL programming is preferred.\nAbility to lead new technology reviews to document layout methodologies, flows, and guidelines.\nSelf-reliant with the ability to work both independently and collaboratively.\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Engineer, Design Evaluation Engineering", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-08-03", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Engineer--Design-Evaluation-Engineering_R264346", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nAnalog Devices Inc. is seeking an intelligent and versatile product engineer to join our agile advanced data converters group. You will join a team of digital, analog and mixed signal CMOS designers, algorithm and software developers implementing state of the art RF and signal processing chips.  As a member of the focused team, you will be responsible for a specific product or group of products from product definition through production and release and may participate in the design, simulation, and verification of the product prior to tapeout.\nKey responsibilities include:\n►Interface as the central resource with design, test, application, software and marketing teams as the product(s) move from design to completion and distribution.\n► Work with design, systems, software, and applications engineering to gather the data needed for hardware release and supporting datasheet.\n► Develop verification and characterization test plans and develop the software required to automate the data collection process.\n►Perform lab analysis and evaluation of new systems, working with a multi-functional team to identify, simulate, and correct functional and parametric problems.\n► Characterization of pre-release silicon encompassing the total solution including analog, digital, and firmware algorithms.\n►Verification & release of embedded software for products.\n►Responsible for taking silicon and ARM software from early development stage to full production release.\n►Responsible for developing and operating software verification test bench.\n►Responsible for developing and operating RF-centric characterization bench\n►Direct interaction with field sales/applications as well as customers to resolve product issues.\n►May participate in customer visits\nRequirements:\nMinimum BE/B Tech in Electrical/Electronics/Communication Engineering\n1-4 years’ experience working in wireless transceiver or telecommunications industry\nKnowledgeable in RF measurements and signal processing \nExperience performing circuit evaluation and characterization using bench test equipment including spectrum analyzers, oscilloscopes, signal generators, network analyzers, vector signal analyzers.\nWorking experience with transceivers and different sub-blocks. (Plls, Mixers, LNAs, ADCs\\DACs, JESD)\nKnowledge of programming languages. (Labview, C#, python and Teststand are preferred)\nFamiliarity with embedded software and verification practices. \nFamiliar with simulation tools such as ADS, Cadence\nStrong communication and problem-solving skills\nIntelligence, enthusiasm, and a solid work ethic are extremely valuable for this position.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "CAD-DFT Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-03", "url": "https://careers.arm.com/job/bengaluru/cad-dft-engineer/33099/98426141520", "is_hardware": true, "platform": "talentbrew", "jd_text": "Join the proactive Chip Methodology & Automation (CMA) team within Arm's Solutions Engineering organization! As a CAD-DFT Engineer, you will develop and apply scalable strategies, sequences, and automation to optimize Arm-based SoC implementation. This role gives you the chance to work across IP, architecture, and product engineering areas. You will contribute to producing production-ready solutions that improve quality, efficiency, and time to market.\nResponsibilities:\nDevelop and maintain DFT methodologies, flows, automation, and reference solutions for Arm-based SoCs.\nDrive alignment and integration of DFT flows within end-to-end RTL-to-GDS and silicon enablement methodologies.\nCollaborate with architecture, implementation, CAD, product engineering, customers, and ecosystem partners to ensure successful deployment.\nEvaluate and enable new capabilities with EDA vendors and technology partners.\nLead technical reviews, resolve complex integration challenges, and drive methodology improvements.\nGuide engineers and contribute to the DFT and automation roadmap within CMA.\nNecessary Skills and Experience:\nMinimum 3+ years of industry experience in DFT implementation, methodology development, and flow integration for complex SoCs.\nDeep understanding of scan, compression, ATPG, MBIST/LBIST, JTAG/IEEE 1149.x, IEEE 1687, and hierarchical DFT methodologies.\nExperience integrating DFT into implementation, verification, and signoff flows.\nHands-on expertise with industry-standard DFT EDA tools.\nStrong automation and scripting skills (Python, Tcl, Shell, or similar).\nExcellent debugging, communication, and collaborator management skills.\nProven ability to influence technical direction across cross-functional teams.\nPreferred Skills and Background:\nExperience with advanced-node SoC development.\nFamiliarity with chiplet or multi-die architectures.\nExperience developing CAD, methodology, or automation infrastructure.\nIn Return:\nAt Arm, we believe in promoting an inclusive and united environment where every team member can thrive. You will be given the opportunity to join a group of highly skilled engineers working on groundbreaking technology. We offer competitive compensation, comprehensive benefits, and a culture that values work-life balance. Join us and contribute to the future of computing!\n10x Mindset at Arm\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Read more about how we bring the 10x mindset to life on the Arm blog.\n\n #LI-SC2 \nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "IO and Mixed Signal Layout Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-08-03", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/IO-and-Mixed-Signal-Layout-Design-Engineer_R026725", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nDesign full custom layouts of I/O libraries and Analog Mixed Signal IP's in planar and FinFET technologies.\n\nDrive critical floor-planning decisions to ensure optimal placement and routing that meets design requirements and performance metric.\n\nPerform comprehensive layout verification to ensure high quality and compliance\n\nComplete ownership from end to end deliverables with quality within the schedule.\n\nAdapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the teams across all sites.\n\nSkills and Qualifications Required:\nB.Tech/M.Tech in Electronics/Electrical engineering with 8-12 years of experience\n\nHands-on experience in I/O Library and Analog Mixed-signal IP development and verification \n\nSolid understanding of Planar and FinFET layouts and process technology\n\nGood understanding of Full-chip concepts, IO frame and pitch requirements, power planning, IO segment rules and requirements\n\nIn-Depth knowledge of ESD and Latch-up principles for I/O and Analog layouts\n\nProficiency in using Cadence Virtuoso Layout suite and Siemens CALIBRE verification tools.\n\nExpertise in Layout verifications and debugging: DRC/LVS/ANT/ERC/DFM, LPE, PERC, EM and IR etc\n\nFamiliar with the Physical Design flow: LEF generation and PnR\n\nKnowledge of AI, automation in layout, Script Programming and SKILL Programming is a plus.\n\nExcellent written and verbal communication skills to collaborate with circuit designers and teams across all sites\n\nAble to lead, train junior engineers, and manage projects effectively.\n\nSelf-motivated, capable of working independently, and a strong collaborative team player.\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "IO and Mixed Signal Layout Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-08-03", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/IO-and-Mixed-Signal-Layout-Design-Engineer_R026724", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nDesign full custom layouts of I/O libraries and Analog Mixed Signal IP's in planar and FinFET technologies.\n\nDrive critical floor-planning decisions to ensure optimal placement and routing that meets design requirements and performance metric.\n\nPerform comprehensive layout verification to ensure high quality and compliance\n\nComplete ownership from end to end deliverables with quality within the schedule.\n\nAdapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the teams across all sites.\n\nSkills and Qualifications Required:\nB.Tech/M.Tech in Electronics/Electrical engineering with 5-8 years of experience\n\nHands-on experience in I/O Library and Analog Mixed-signal IP development and verification \n\nSolid understanding of Planar and FinFET layouts and process technology\n\nGood understanding of Full-chip concepts, IO frame and pitch requirements, power planning, IO segment rules and requirements\n\nIn-Depth knowledge of ESD and Latch-up principles for I/O and Analog layouts\n\nProficiency in using Cadence Virtuoso Layout suite and Siemens CALIBRE verification tools.\n\nExpertise in Layout verifications and debugging: DRC/LVS/ANT/ERC/DFM, LPE, PERC, EM and IR etc\n\nFamiliar with the Physical Design flow: LEF generation and PnR\n\nKnowledge of AI, automation in layout, Script Programming and SKILL Programming is a plus.\n\nExcellent written and verbal communication skills to collaborate with circuit designers and teams across all sites\n\nAble to lead, train junior engineers, and manage projects effectively.\n\nSelf-motivated, capable of working independently, and a strong collaborative team player.\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Applications Engineering, Director-Physical Design", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-08-03", "url": "https://careers.synopsys.com/job/bengaluru/applications-engineering-director-physical-design/44408/100768195872", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in the trenches of digital design, working synthesis flows, closing timing on advanced nodes, and debugging why a place-and-route run just blew past its power budget at 3am. More than that, you have learned how to take that hard-won knowledge and turn it into something a customer team can actually use. You do not just solve problems, you teach people how to solve them, and you know the difference between a one-time fix and a methodology that scales across an entire design organization.\nLeading a team comes naturally to you because you have been the engineer who needed clear direction, the one who hit a wall and needed air cover, and the one who wanted to grow but did not know how. You set priorities without overthinking them. You protect your team's time while keeping customers moving. You escalate when it matters and resolve when you can.\nYou are comfortable sitting across from a customer architect who is frustrated that their block will not converge and walking out with a plan that involves three engineers, two R&D escalations, and a revised timeline everyone believes in. At Synopsys, you will lead a team that does this work every day, for customers building the chips that matter.\nWhat You'll Be Doing\nLead customer engagements to deploy digital design methodologies including synthesis, place-and-route, timing closure, and power optimization for advanced node designs\nSolve complex technical challenges alongside customer engineering teams, diagnosing bottlenecks in their flows and tuning tool configurations to hit PPA targets\nDeliver technical training and hands-on guidance to customer teams on tool usage, methodology best practices, and advanced implementation techniques\nManage and mentor a team of applications engineers, balancing project delivery, technical growth, and customer relationship ownership across multiple engagements\nOwn customer escalations, driving debug and resolution plans in partnership with R&D, Product, and Program teams when issues block tapeout or deployment\nServe as the voice of the customer to Synopsys R&D teams, translating field issues and feature requests into actionable product feedback that shapes tool development\nDrive AI initiatives and work with cross-functional and global AE teams to scale adoption of new capabilities within customer organizations and internal workflows\nThe Impact You Will Have\nYour team will enable customers to tape out advanced node designs on time by solving the hard methodology and tooling problems that would otherwise derail schedules\nCustomer engineering teams will adopt Synopsys flows more broadly and deeply because you made the tools understandable and the methodology repeatable\nR&D priorities will shift based on the field intelligence you surface, turning customer pain points into product improvements that benefit the entire user base\nYour engineers will grow into stronger technical leaders and customer partners because you gave them the coaching, context, and autonomy they needed\nEscalations will resolve faster and with better outcomes because you built the cross-functional relationships and processes that turn chaos into coordinated action\nAI-driven capabilities will move from pilot to production in customer environments because you led the enablement and proved the value\nSynopsys will retain and expand relationships with strategic accounts because your team consistently delivers technical wins that matter to their business\nWhat You'll Need\n16+ years of hands-on experience in digital design implementation, including synthesis, place-and-route, timing closure, and power optimization on advanced process nodes\nDeep working knowledge of Synopsys digital design tools or equivalent EDA platforms, with the ability to debug flows, tune configurations, and teach methodologies\nProven experience leading technical teams, including hiring, mentoring, performance management, and resource allocation across multiple customer engagements\nTrack record of managing customer escalations and driving resolution through cross-functional collaboration with R&D, Product, and Support organizations\nStrong technical judgment to prioritize competing demands, allocate resources effectively, and make tradeoff decisions under pressure\nWillingness to travel occasionally to support strategic customer engagements, executive reviews, and critical project milestones\nExperience with AI/ML tooling or methodologies in the context of EDA workflows is a plus\nWho You Are\nYou can walk into a tense customer meeting where a design is stuck and leave with a clear action plan that everyone believes in, not because you overpromised but because you broke the problem down honestly\nYou know when to let your team run with something and when to step in, and you do not confuse oversight with micromanagement\nYou can explain a complex tool limitation to a customer VP in two sentences without losing the technical nuance or making excuses\nYou track metrics that matter, like milestone health and issue resolution time, not because someone asked for a report but because you use them to make better decisions\nYou push back on R&D when a workaround is not good enough and push back on customers when their expectations are not grounded in reality, and you do both without burning relationships\nYou treat mentoring as part of the job, not an extra, and your team knows you care about their growth because you make time for it even when things are busy", "jd_status": "stored"}, {"title": "Design Engineer -PNR", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-08-03", "url": "https://careers.arm.com/job/bengaluru/design-engineer-pnr/33099/97596415088", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview :\n\nAs a part of Arm's Solutions Engineering group we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance, and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is the development of comprehensive implementation and analysis methodologies.\n \nResponsibilities:\n· Synthesis, Physical implementation, Timing closure and Physical signoff of CPU cores, system interconnect, and other ARM Designs.\n· Analyze design timing, area and power to help improve the quality of ARM Design.\n· Optimize design, flow and methodologies to achieve best in class PPAT working with various internal and external teams.\n· Develop and deploy new methodologies to improve implementation efficiency and results\n· Support and develop detailed implementation analysis and data-mining methodologies.\n· Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP.\n· Converting R&D concepts into real implementation solutions.\n· Enable our partners to achieve the best possible quality of results\n\nRequired Skills and Experience :\n· Bachelor’s or master’s degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields.\n· 3-5 years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification\n· Strong Communication and Problem-Solving Skills.\n· Experience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams\n \n \n \n#LI-PS2\n \nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Design Verification Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-08-01", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505953", "is_hardware": true, "platform": "oracle", "jd_text": "We are looking to expand our team with a Senior Digital IC Verification Engineer. You will help us develop IP for next generation Automotive, Industrial & Medical products. The successful candidate will participate in the design of complex mix-signal IPs and have familiarity with analog blocks such as DACs, ADCs, PLL and wireless interface etc. \n\nResponsibilities:\n\nWhat You’ll Do\n\nDefine the verification strategy and the detailed verification plans for blocks and systems\n\nCoordinate/lead the verification activities in the project teams\n\nDevelop System Verilog/UVM environments for blocks and top-level SoCs\n\nDebug functional errors in RTL\n\nParticipate to verification methodology improvement activities\n\n#LI-RG1\n\nResponsibilities\nResponsibilities:\n\nWhat You’ll Do\n\nDefine the verification strategy and the detailed verification plans for blocks and systems\n\nCoordinate/lead the verification activities in the project teams\n\nDevelop System Verilog/UVM environments for blocks and top-level SoCs\n\nDebug functional errors in RTL\n\nParticipate to verification methodology improvement activities\n\n#LI-RG1\n\nQualifications\nQualifications \n\nWhat You’ll Need\n\nMinimum BS/MS in Electrical Engineering or related technical field\n\nMinimum 3 years of digital verification experience\n\nSolid understanding of verification best practices such as verification planning, requirements tracking, and functional coverage\n\nIn-depth knowledge and some years of proven experience in state-of-the-art verification methodologies (e.g. UVM), constrained random driven verification, assertion based verification, test environment architecture & creation, regression management, coverage collection\n\nExcellent English written and verbal communication skills\n\nWhat Else You May Bring \n\nExperience with Project/task leadership\n\nVerification of signal processing components\n\n3rd party verification IP deployment\n\nProgramming skills – Python, Tcl, embedded software\n\n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Senior Design Verification Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-08-01", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505954", "is_hardware": true, "platform": "oracle", "jd_text": "We are looking to expand our team with a Senior Digital IC Verification Engineer. You will help us develop IP for next generation Automotive, Industrial & Medical products. The successful candidate will participate in the design of complex mix-signal IPs and have familiarity with analog blocks such as DACs, ADCs, PLL and wireless interface etc. \n\nResponsibilities:\n\nWhat You’ll Do\n\nDefine the verification strategy and the detailed verification plans for blocks and systems\n\nCoordinate/lead the verification activities in the project teams\n\nDevelop System Verilog/UVM environments for blocks and top-level SoCs\n\nDebug functional errors in RTL\n\nParticipate to verification methodology improvement activities\n\n#LI-RG1\n\nQualifications\nWhat You’ll Need\n\nMinimum BS/MS in Electrical Engineering or related technical field\n\nMinimum 3 years of digital verification experience\n\nSolid understanding of verification best practices such as verification planning, requirements tracking, and functional coverage\n\nIn-depth knowledge and some years of proven experience in state-of-the-art verification methodologies (e.g. UVM), constrained random driven verification, assertion based verification, test environment architecture & creation, regression management, coverage collection\n\nExcellent English written and verbal communication skills\n\nWhat Else You May Bring \n\nExperience with Project/task leadership\n\nVerification of signal processing components\n\n3rd party verification IP deployment\n\nProgramming skills – Python, Tcl, embedded software\n\n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Senior Design Verification Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-08-01", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505955", "is_hardware": true, "platform": "oracle", "jd_text": "We are looking to expand our team with a Senior Digital IC Verification Engineer. You will help us develop IP for next generation Automotive, Industrial & Medical products. The successful candidate will participate in the design of complex mix-signal IPs and have familiarity with analog blocks such as DACs, ADCs, PLL and wireless interface etc. \n\nResponsibilities:\n\nWhat You’ll Do\n\nDefine the verification strategy and the detailed verification plans for blocks and systems\n\nCoordinate/lead the verification activities in the project teams\n\nDevelop System Verilog/UVM environments for blocks and top-level SoCs\n\nDebug functional errors in RTL\n\nParticipate to verification methodology improvement activities\n\n#LI-RG1\n\nQualifications\nWhat You’ll Need\n\nMinimum BS/MS in Electrical Engineering or related technical field\n\nMinimum 3 years of digital verification experience\n\nSolid understanding of verification best practices such as verification planning, requirements tracking, and functional coverage\n\nIn-depth knowledge and some years of proven experience in state-of-the-art verification methodologies (e.g. UVM), constrained random driven verification, assertion based verification, test environment architecture & creation, regression management, coverage collection\n\nExcellent English written and verbal communication skills\n\nWhat Else You May Bring \n\nExperience with Project/task leadership\n\nVerification of signal processing components\n\n3rd party verification IP deployment\n\nProgramming skills – Python, Tcl, embedded software\n\n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Senior Design Verification Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-08-01", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505956", "is_hardware": true, "platform": "oracle", "jd_text": "We are looking to expand our team with a Senior Digital IC Verification Engineer. You will help us develop IP for next generation Automotive, Industrial & Medical products. The successful candidate will participate in the design of complex mix-signal IPs and have familiarity with analog blocks such as DACs, ADCs, PLL and wireless interface etc. \n\nResponsibilities:\n\nWhat You’ll Do\n\nDefine the verification strategy and the detailed verification plans for blocks and systems\n\nCoordinate/lead the verification activities in the project teams\n\nDevelop System Verilog/UVM environments for blocks and top-level SoCs\n\nDebug functional errors in RTL\n\nParticipate to verification methodology improvement activities\n\n#LI-RG1\n\nQualifications\nWhat You’ll Need\n\nMinimum BS/MS in Electrical Engineering or related technical field\n\nMinimum 3 years of digital verification experience\n\nSolid understanding of verification best practices such as verification planning, requirements tracking, and functional coverage\n\nIn-depth knowledge and some years of proven experience in state-of-the-art verification methodologies (e.g. UVM), constrained random driven verification, assertion based verification, test environment architecture & creation, regression management, coverage collection\n\nExcellent English written and verbal communication skills\n\nWhat Else You May Bring \n\nExperience with Project/task leadership\n\nVerification of signal processing components\n\n3rd party verification IP deployment\n\nProgramming skills – Python, Tcl, embedded software\n\n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Senior Director,  Hardware Engineering", "company": "Lumilens", "location": "Bengaluru, India", "date_posted": "2026-07-31T13:17:55.528000+00:00", "url": "https://jobs.ashbyhq.com/lumilens/b732a547-6303-464b-9fec-b721e1cd6f4e", "is_hardware": true, "platform": "ashby", "jd_text": "ABOUT LUMILENS\nAt Lumilens we are building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new era of computing - faster, cooler, and massively more efficient.\n\nWe’re a well-funded startup backed by Mayfield and led by veterans who’ve built and scaled some of the most transformative technologies in the industry. At Lumilens, we’re developing high-speed photonics products purpose-built to power the future of AI infrastructure and high-performance computing.\n\nThis isn’t incremental innovation, it’s a ground-floor opportunity to rethink the optical layer from the silicon up. You’ll work alongside a team of world-class engineers solving some of the hardest challenges in scaling optical systems. Every line of code, every design decision, every breakthrough you help deliver will shape the infrastructure of tomorrow.\n\nIf you're looking for mission, momentum, and the chance to make an outsized impact, jump on the rocket ship. We’re just getting started.\nPOSITION OVERVIEW\nWe are looking for a Senior Hardware Manager who combines strategic leadership with hands‑on technical expertise. This role is ideal for someone who thrives in fast‑paced environments, is comfortable rolling up their sleeves to solve engineering challenges, and is willing to travel frequently on short notice to support global teams, vendors, and customers.\nDUTIES/RESPONSIBILITIES\nLead a team of hardware engineers across design, validation, and deployment.\n\nDrive project execution, ensuring milestones are met with high quality and efficiency.\n\nFoster a culture of accountability, innovation, and continuous improvement.\n\nHands‑On Technical Contribution\n\nActively participate in board bring‑up, debugging and system integration.\n\nSupport prototype builds, lab validation, High volume manufacturing and field issue resolution.\n\nCollaborate with cross‑functional teams (mechanical, firmware, SI/PI, manufacturing) to ensure robust designs.\n\nVendor & Customer Engagement\n\nTravel on short notice to vendor sites, manufacturing partners, and customer locations for troubleshooting, audits, and design reviews.\n\nBuild strong relationships with suppliers to ensure quality, cost, and delivery targets are met.\n\nProgram, Project & Process Management\n\nOversee hardware development lifecycle from concept to production\n\nImplement best practices for DFM/DFT, reliability testing, and compliance.\n\nTrack deliverables, tasks, action items, project milestones and report progress to senior leadership.\n\nRequired Qualifications\nBachelor’s or Master’s degree in Electrical Engineering.\n\n15+ years of experience in hardware design and development, with Significant years in a leadership role.\n\nProven ability to debug hardware at the board/system level using lab equipment (oscilloscopes, logic analyzers, etc.).\n\nStrong knowledge of high‑speed interfaces, power delivery, and system integration.\n\nWillingness and ability to travel frequently (international) on short notice.Preferred Skills\n\nExperience with data center hardware, networking equipment, or photonic/electrical interconnects.\n\nFamiliarity with compliance standards (FCC, CE, UL, RoHS, etc.).\n\nStrong vendor management and cross‑cultural communication skills.\n\nTrack record of leading teams through NPI (New Product Introduction) and scaling to volume production.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.", "jd_status": "stored"}, {"title": "DFT Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-31T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719583776", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a DFT engineer, you will be working on end-to-end Custom Silicon Design cycle, from DFT-architecture planning to delivering qualified Si parts to our customers. You will be using some the best industry-standard tools and specific workflows to implement full chip level advanced Scan and MBIST insertion, verification, and pattern generation. Your role will involve collaborating closely with customers, working hand-in-hand with RTL/PD teams and supporting Test/Product Engineering teams.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nWhat you'll do: \nDevelop and implement comprehensive DFT architectures, collaborating on early planning stages.\n\nImplement scan and MBIST using industry-standard EDA tools.\n\nDevelop and execute DFT verification plans (pattern generation, fault simulation).\n\nCollaborate with cross-functional teams to resolve DFT-related issues.\n\nDocument DFT architecture and verification results.\n\nServe as the primary point of contact for DFT-related inquiries and lead the implementation efforts, ensuring alignment with customer requirements.\n\nWhat you'll need:  \nBTech/MTech in EE or related field, 3-12 years DFT experience.\n\nProven leadership in complete DFT implementation and team guidance.\n\nDeep understanding of advanced DFT techniques.\n\nNice to have  \nExperience driving DFT implementation on large designs.\n\nFamiliarity with advanced DFT techniques (e.g. In-system test, SSN, multi-die testing).\n\nSilicon debug experience related to DFT.\n\nTool and methodology development related to DFT.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "PCIe / CXL Validation Engineer - Sr. Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-31T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718281544", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nRole Summary:\n\nLead and own end‑to‑end validation of PCIe (Gen4/Gen5/Gen6/Gen7) and CXL (2.x/3.x) subsystems across pre‑silicon and post‑silicon platforms for server‑class SoCs. Drive validation strategy, execution, debug, and cross‑functional alignment to ensure high‑quality, on‑schedule delivery.\n\nKey Responsibilities:\nDefine and own validation strategy, test plans, and coverage for PCIe/CXL controllers, PHY, and system‑level use cases.\n\nLead pre‑silicon (RUMI, Veloce, FPGA) and post‑silicon bring‑up and validation activities.\n\nValidate protocol compliance, performance, reliability, power management (ASPM, L1SS, LTR), and advanced features including P2P, IDE/DOE, error handling, and reset flows.\n\nDrive complex root‑cause analysis using protocol analyzers (e.g., LeCroy), and silicon debug.\n\nPartner closely with architecture, Design, PHY, software, platform, and power teams to root-cause and resolve issues.\n\nProvide technical leadership and mentorship to validation engineers..\n\nRequired Skills & Experience:\nCandidate needs 12 to 15 years of experience of relevant experience (A Must).\n\nStrong expertise in PCIe and CXL architecture, protocol, and system integration.\n\nHands‑on experience with server platforms, analyzers, emulation platforms, and SoC bring‑up.\n\nProven ability to lead cross‑functional debug and deliver under aggressive schedules.\n\nExcellent technical communication and stakeholder‑management skills.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Principal Engineer , ASIC Analog Design", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-31T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/40780352", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nJob Description\n\nOur vision is to transform how the world uses information to enrich life.\nJoin an inclusive team focused on one thing: using their expertise in the steadfast pursuit of innovation for customers and partners. The solution we create help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing!\nPosition Description:\nTo be part of a highly skilled and challenging high speed PHY build team working on the newest technology nodes (12nm and below).\n\nTake ownership of analog sub-blocks inside the PHY and drive the specification and implementation. It includes transistor and block level design, simulation, reliability and mixed mode simulations etc.\n\nLeverage AI-enabled tools to improve productivity and decision making.\n\nDrive layout of sophisticated blocks through mask designers. Conform to complex process rules as well as DFM or equivalent experience.\n\nParticipate in design reviews both internally and potentially with customers to explain design choices and robustness. Work with people across multiple sites including overseas.\n\nHelp with creating IP EDA views: Behavioral/Verilog-A, timing views, abstract etc.\n\nParticipate in silicon bring up, characterization, & perform correlations against models & simulations.\n\nMentor and supervise entry-level engineers.\n\nEqual opportunity position with excellent pay package!\n\nSKILLS required:\nCircuit design experience in analog/mixed signal CMOS circuits in deep sub-micron technologies (2 – 28 nm) in High speed Memory interfaces (DDR3/4/5, LPDDR5/6, GDDR5/6/7) or SerDes Interfaces (PCIe, MIPI, HDMI, USB, SATA etc).\n\nPrior experience in taking full ownership of at least on of the sub-blocks like PLL, DLL, CDR, high speed receiver with equalization, transmitter front end and high speed data path.\n\nThe candidate is encouraged to possess a deep understanding of analog and mixed signal circuits along with experience in high speed link.\n\nCandidate must have experience in Serdes/Parallel Interface.\n\nExperience with TX RX Equalization (FFE/CTLE/DFE) is must\n\nExperience with various CDR and Clocking architecture.\n\nCandidate should have experience in finfet 10nm and below.\n\nAble to create block level specification based on link budget.\n\nAble to create system level modeling using VerilogA/Python.\n\nShould be able to work with Packaging/Board team.\n\nShould have knowledge of ESD.\n\nExperience in lab testing and work with validation team to analysis data.\n\nHigh speed I/O cell designs such as DDR, LVDS, HSTL, CML.\n\nPower Delivery circuits such as Bandgap, LDO, Bias circuits.\n\nStrong fundamental knowledge for AMS design, Advanced CMOS and FinFet technologies.\n\nUnderstanding of Mismatch analysis & Monte-Carlo methodology/sims, transistor level Circuit level noise analysis. Understanding of device physics & deep-sub micron issues.\n\nSupervision of complex and/or critical analog layout and defining IP floorplan\n\nExperience with industry standard tools such as Cadence ADE, Spectre, AMS verification, EM/IR flows, MATLAB, Calibre etc.\n\nWorking knowledge of Mixed mode simulation, Signal Integrity and ESD desired.\n\nM.S./M.Tech, BS/BE (Electronics)\n\nExperience Required : 5+ Years\n\nAdditional Job Description\n\nLeads all aspects of definition, design, verification, and documentation for ASIC development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. May also review vendor capability to support development.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Senior DFT Engineer", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-07-31", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Senior-DFT-Engineer_R263574", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nSenior DFT Engineer Responsibilities\nDFT architecture definitionUnderstand SoC architecture and test requirements.\nWork very closely with the lead Product/Test engineering throughout the DFT definition phase to determine efficient ways to optimize test cost and achieve high test coverage.\nDrive and optimize DFT architecture for high performance and efficiency:SCAN – scan partition, compression, at-speed, IR and low power\nMBIST for memories\nJTAG boundary scan insertion\n\nHandle responsibilities pertaining to both block and top-level activities in Hierarchical Scan.\n\nImplementationDevelop / Upgrade SCAN & MBIST Insertion flows\nDevelop appropriate timing constraints for SCAN/MBIST modes and debug timing violations\nATPG flow implementation catering to various fault models, test pattern generation\nSCAN , MBIST & BSCAN Pattern Simulation\nSolutions to test analog macros\n\nPost-Silicon bring-up/supportWork with Evaluation/Test Engineering team to bring-up patterns on ATE\nWork on failure analysis as required\nWork with the Operation team on test cost and yield improvement\n\nImprove DFT methodology to be in sync with latest best practices and technology in the industry\nWork closely with physical design team throughout the development cycle.\nShould be able to guide newly inducted team members on their bring-up on flow, methodology and execution methods in all aspects of DFT.\nRequirements\n4-8 years of industry experience in DFT domain.\nMust have experience in bringing atleast one or two products to successful production from architecture phase, scan implementation and simulations.\nMust have hands-on experience working on post-silicon activities.\nHaving working experience with tessent DFT (SCAN, Mbist, Lbist, OCC, EDT, SSN, Boundary Scan) will be preferred.\nExceptional interpersonal and communication skills are critical for working, influencing and collaborating with product development groups and CAD tool teams spread across the globe.\nScripting skills in Perl/Python/TCL and a good command over HDLs.\nCandidates with exposure to deep submicron effects and low power implementation using UPF/CPF will be at an advantage. Candidates with experience using Cadence digital implementation tools (Genus, Tempus) would be preferred.\nPrior experience of timing closure/physical design will be an added plus.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Engineer /Senior Engineer (Verification)", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-07-31", "url": "https://careers.arm.com/job/bengaluru/engineer-senior-engineer-verification/33099/98567425360", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job overview:\nExperience : 2-8 years\n \nResponsibilities:\n \nYou’ll be part of a team that builds complete reference systems around Arm IPs and use it for and Arm IP stress verification, giving you exposure far beyond traditional DV roles.\n· Integrate Arm CPU and system IPs into full reference platforms\n· Bring up systems across simulation and emulation\n· Debug real system issues spanning hardware + low-level software\n· Develop system-level tests (C/C++/Assembly driven)\n· Work closely with design, architecture, and global teams\n· Contribute to improving verification flows, tools, and efficiency\n \nWhy This Role Stands Out\n· 🔧 Early System-level exposure – go beyond UVM/testbench work\n· 🧠 Strong learning curve – CPU architecture, AMBA, memory systems\n· 🚀 High ownership – own IP integration, features, debug, and bring-up\n· 🌍 Global collaboration – work with teams across UK, US, and Europe\n· ⚡ Real impact – your work directly influences quality of Arm IPs.\n \nRequired skills and experience:\n \n· 2–8 years of experience in SoC/IP development or verification\n· Solid understanding of verification fundamentals & debug\n· Experience with C/C++ or Assembly-based testing\n· Exposure to pre-silicon environments (simulation/emulation)\n· Basic understanding of CPU or SoC architecture\n \nGood to Have\n· Knowledge of Arm architecture / AMBA protocols\n· Experience in embedded software or firmware bring-up\n· Exposure to SoC integration or system-level validation\n· Scripting in Python/Perl\n· Familiarity with Verilog/SystemVerilog\n \nWho You’ll Fit In Best As\n· You enjoy debugging and figuring out system integration problems\n· You want to work close to real hardware and full systems\n· You’re looking to move beyond pure DV into system understanding\n· You take ownership and can drive tasks end-to-end\n \nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Principal - Analog Design", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-07-31", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506194", "is_hardware": true, "platform": "oracle", "jd_text": "onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world. \n\nonsemi’s Core-Analog IP Center of Excellence is hiring an experienced Analog IC design engineer to help us develop IP for next generation Automotive, Industrial & Medical products. The successful candidate will participate in the design of complex CMOS integrated circuits and have familiarity with analog blocks such as bandgaps, amplifiers, filters, precision comparators, LDOs, oscillators, PLLs etc. Experience with signal chain optimization is highly desired.\n\n #L1-MK1\n\nResponsibilities\nDrive the development, verification, and characterization of advanced analog and mixed-signal CMOS circuit blocks, ensuring optimal performance, power efficiency, reliability, and reusability across product platforms.\nDrive analog circuit requirements discussions, technical issues and other design aspects with internal teams and marketing to arrive at agreed upon product specifications. \nBuild/develop circuits based on an IP specification, drive the layout design and final IP characterization.\nExecute state-of-the-art analog designs while following the best design practices with on time quality design releases.\nPropose innovative and creative solutions where necessary to meet customer & product needs.\nWork diligently with the analog team members and others to accomplish project goals and meet schedule requirements.\nDebug of complex integrated circuit problems in the laboratory. Support team debug efforts as needed.\nPerform bench characterization and support application engineering bench evaluation efforts.Analyze design aspects related to DFT and collaborate with other teams to develop DFT strategy for block designs.\nDocument designs including architecture and circuit descriptions, testing procedures, and safety mechanisms.\nInterface with test, product, and applications engineering to drive the design to a successful production release.\nProvide technical leadership through IC specification definition, project planning, design reviews, team coordination, layout oversight, and mentoring of junior engineers.\n\n#L1-MK1\n\nQualifications\nMaster’s degree in electrical engineering with 12+ years of relevant experience or Ph.D. in Electrical Engineering with 14+ years of relevant experience in analog circuit designal \nAnalog design experience and proficiency in verification, documentation, and post-silicon validation. Includes broad understanding of integrated circuit design such as amplifiers, filters, BGAP circuits, oscillators etc.\nIn-depth knowledge of semiconductor devices like MOS transistors, BJTs etc.\nKnowledge with behavioral top-level modeling and mixed signal verification methodology.\nKnowledge of UNIX/Linux working environment \nKnowledge of multiple semiconductor design tools like Matlab, Spectre, Spice, Cadence design environment. AMS simulation experience is a plus.\nExcellent written and oral communication.\nProven ability to work independently and in teams.\nHands-on experience in a lab environment working with sensitive measurement equipment and data acquisition.\nVery good debugging ability in circuit operation, and device function\n\n#L1-MK1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Director - Analog Design", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-07-31", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506193", "is_hardware": true, "platform": "oracle", "jd_text": "ON Semiconductor is seeking a self-driven and motivated professional & leaders to join the Center-Of-Excellence in Advanced Solution Group located in  Bangalore (Whitefield), India.  As a design manager you will lead and drive a team that impacts the next generation analog/mixed signal innovations across the whole of the Advanced Solutions Group. You will be working with a world-class team of professionals focusing on developing the power-management and clock management systems that will be used by all product lines across multiple business units and also as standalone discrete products. \n\n#LI-MK1\n\nResponsibilities\nMust have a working knowledge of Cadence Circuit design tools.\nAnalytical approach to problem solving is required. \nCMOS designs provide challenging learning opportunities where performance, power and reliability are all pushed to the limit while maintaining product execution schedule.\nDrive development and verification of state-of-the-art analog blocks and mixed signal CMOS designs which can be reused across different market segments.\nDrive analog circuit requirements discussions, technical issues and other design aspects with internal teams and marketing to arrive at agreed upon product specifications. \nBuild/develop circuits based on an IP specification, drive the layout design and final IP characterization.\nExecute state-of-the-art analog designs while following the best design practices with on time quality design releases.\nPropose innovative and creative solutions where necessary to meet customer & product needs.\nWork diligently with the analog team members and others to accomplish project goals and meet schedule requirements.\nDebug of complex integrated circuit problems in the laboratory. Support team debug efforts as needed.\nWork with Validation engineers and support debug activities and engineering bench evaluation efforts.\nAnalyze design aspects related to DFT and collaborate with other teams to develop DFT strategy for block designs.\nDocument designs including architecture and circuit descriptions, testing procedures, and safety mechanisms.\nInterface with test, product, and applications engineering to drive the design to a successful production release.\nProvide technical leadership including IC specification, project planning, design team management, and layout supervision.\nClose collaboration with system architects and product definers.\nMentor junior engineers \n#LI-MK1\n\nQualifications\nQualifications\nMasters in VLSI design from reputed universities like IIT/NIT with a background in Bachelors in Electronics and Communication, or a related field.\n15 to 25 years of experience in the field of semiconductor chip design.\nProven experience in project management, with a specialization in analog semiconductor chip design.\nStrong technical background in high-performance analog and mixed-signal circuit design.\nExcellent leadership and communication skills.\nFamiliarity with project management tools and methodologies.\n#LI-MK1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Senior Packaging Technical Engineer - Hardware", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-07-31", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Packaging-Technical-Engineer---Hardware_JR2022406", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nWe are now looking for a Senior Packaging Technical Engineer. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing.\n\nWhat you’ll be doing:\nYour responsibilities include defining the chip pad ring, substrate interconnect scheme, and lead the package layout design process.\n\nWe collaborate with large teams consisting of Circuit, Signal Integrity, RTL, Place and Route, substrate layout and system design Engineers and Managers.\n\nWork to define a chip floor plan, pad ring, substrate, and ball out implementing a robust world-class electrical package!\n\nCommunicate effectively with various teams throughout the company\n\nWhat we need to see:\nBSEE or equivalent experience.\n\nMinimum of 8+ years in board/system design. Experience with package design is preferred.\n\nGood understanding of transmission line theory, power delivery and signal integrity is desired.\n\nStrong programming and scripting skills in Perl, Python, Tcl desired, Cadence Skill and EXCEL familiarity are helpful.\n\nEnthusiastic and able to work with a minimum of supervision.\n\nYou seek to solve complex technical problems.\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We welcome you join our team with some of the most hard-working people in the world working together to promote rapid growth. Are you passionate about becoming a part of a best-in-class team supporting the latest in GPU and AI technology? If so, we want to hear from you.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "DFT Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-07-31", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/DFT-Design-Engineer_JR0286042", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nDesign, implement, validate, and debug Design-for-Test (DFT) solutions to ensure manufacturability, test coverage, and silicon quality across IP and SoC programs.\nResponsibilities include development and validation of TAP/JTAG and IJTAG infrastructures, Boundary Scan (BSCAN), MBIST, Scan/ATPG methodologies, and associated test collateral such as ICL, PDL, BSDL, and ATPG patterns. The role requires driving test access, pattern generation, coverage optimization, memory test validation, and debug of scan, at-speed, and silicon bring-up issues while ensuring robust DFT integration across the product lifecycle.\nThe engineer collaborates closely with Design, Verification, Physical Design, Product Engineering, Manufacturing Test, and IP teams to ensure DFT readiness and signoff.\nKey responsibilities include RTL and Gate-Level Simulation (GLS) validation, root-cause analysis and resolution of DFT-related failures, adoption of DFT methodologies and best practices, and leadership of technical reviews and continuous process improvements.\nRequired expertise includes TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, Scan Compression, ATPG, Verilog/System Verilog, Tcl/Perl/Python scripting, DFT verification, silicon debug, and strong communication and technical leadership skills.\n\nQualifications:\nCandidate must have a Bachelor's Degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or related field with 10+ years of experience Or\nMaster's Degree in Electrical Engineering, Microelectronics, VLSI or related field with 8+ years of experience.\nScan Insertion, DFT features, RTL design for DFT and verification.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Applications Engineering, Sr Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-07-31", "url": "https://careers.synopsys.com/job/bengaluru/applications-engineering-sr-staff-engineer/44408/98572441680", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent a decade building, verifying, or supporting silicon that ships, and you know the difference between a clean integration and one that costs your customer three months of debug. You understand that a protocol spec is just the starting point. The real work begins when someone tries to configure PCIe Gen5 in a power-constrained automotive SoC or bring up DDR5 on a board that was not quite laid out the way the datasheet suggested.\nYou have been in the room when things go wrong during tape-out or bring-up, and you are the person who stays calm, asks the right questions, and finds the path through. You can read Verilog, trace a timing violation back to its root cause, and explain what went wrong to a customer engineer who is three time zones away and under pressure. You do not need perfect documentation to move forward. You work with what you have, fill in the gaps, and keep the project on track.\nAt Synopsys, you will work directly with customers integrating our Interface IP into their most critical designs. The problems are real, the stakes are high, and the work you do will directly determine whether their silicon works on the first pass.\nWhat You'll Be Doing\nServe as the technical point of contact for customers integrating Synopsys Interface IP, including Ethernet, PCIe, and DDR, into complex SoC designs\nGuide customers through IP configuration, feature selection, and integration into their RTL and verification environments\nDebug critical issues across simulation, synthesis, static timing analysis, and physical design flows using tools like VCS, Design Compiler, and PrimeTime\nSupport silicon and system bring-up activities, working with customers to diagnose and resolve hardware-level issues in lab environments\nCollaborate with Synopsys R&D, product engineering, and field teams to deliver tailored solutions and escalate complex technical problems\nStay current with evolving protocol specifications for Ethernet, PCIe, DDR, and emerging standards relevant to automotive, AI, and data center applications\nTravel occasionally to customer sites for on-site integration support, training, and bring-up assistance\nThe Impact You Will Have\nEnable successful first-pass silicon for customers by catching integration issues early and providing expert guidance through tape-out\nReduce customer time-to-market by resolving technical blockers quickly and accurately during critical project phases\nStrengthen customer relationships and drive repeat business by becoming a trusted technical advisor they rely on for complex integrations\nInfluence future IP product roadmaps by feeding real-world customer requirements and pain points back to Synopsys R&D teams\nExpand adoption of Synopsys Interface IP across high-growth markets including automotive, AI accelerators, and hyperscale data centers\nContribute to the success of next-generation products that depend on high-speed, low-latency connectivity in increasingly complex system architectures\nBuild internal knowledge and best practices that improve how Synopsys supports customers across the entire applications engineering organization\nWhat You'll Need\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field with focus on VLSI or digital design\n10+ years of hands-on experience in ASIC/SoC design, verification, or applications engineering with exposure to full tape-out cycles\nDeep working knowledge of at least one high-speed protocol: Ethernet (10G/25G/50G/100G/400G), PCIe (Gen3/Gen4/Gen5), or DDR (DDR4/DDR5/LPDDR5)\nStrong RTL coding skills in Verilog or VHDL, with ability to read, debug, and modify customer design code\nPractical experience with simulation (VCS, ModelSim, Xcelium), synthesis (Design Compiler, Genus), and static timing analysis (PrimeTime, Tempus) in a UNIX/Linux environment\nFamiliarity with clock domain crossing (CDC), reset domain crossing (RDC), lint, DFT, and logical equivalence checking (LEC) is a strong plus\nExcellent written and verbal communication skills in English, with ability to explain complex technical concepts clearly to diverse audiences\nWho You Are\nYou can take a vague customer problem description, ask three clarifying questions, and walk away with a clear action plan that actually solves the issue\nYou are comfortable working across time zones and cultures, adapting your communication style to meet customers where they are technically and operationally\nYou manage multiple customer engagements at once without dropping threads, keeping stakeholders informed and issues moving toward resolution\nYou know when to dig in and solve a problem yourself and when to pull in specialists from R&D, and you do both without ego\nYou are willing to travel occasionally for customer visits, training sessions, and on-site bring-up support when the situation calls for it\nYou stay current with industry trends and protocol evolution because you understand that what you learned five years ago is not enough for what customers are building today\n                                                                                                                                                                                                          The Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.", "jd_status": "stored"}, {"title": "Power Architecture Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-07-31", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Power-Architecture-Engineer_JR2005131", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. \n\nNVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! \n\nWhat you’ll be doing:  \n\nBe part of NVIDIA Power Architecture Group that owns end-to-end power aspects such as - ASIC power analysis, power architecture, low power design, power-aware verification, advanced power methodologies, UPF methodologies, power feature bring-up on silicon, and post-Si power correlation for NVIDIA's family of products. \n\nContributing to power analysis by helping to architect, develop, verify & correlate power estimation models/tools for NVIDIA's products \n\nBe part of the team that architects & designs system-level power features for optimizing the dynamic and leakage power dissipation for different usecases.  \n\nWork on power verification which includes structural, functional & power aware verification of power features of NVIDIA products by coming up with test plans, write testcases, build test bench components like Monitors, assertions and coverage points & own verification convergence across RTL, Gates and Silicon.  \n\nValidate the effectiveness of the power features on silicon, conduct studies and contribute to the Performance/Watt improvement ideas.  \n\nHelp build power management solutions and drive innovation in energy efficiency across NVIDIA’s product portfolio.  \n\nWhat we need to see:  \n\nB.Tech./M.Tech with 1+ years of experience related to Power such as Power analysis, Power Design, Power Aware Verification, UPF methodologies and Power Correlation \n\nStrong fundamentals in power including transistor-level leakage/dynamic characteristics of VLSI circuits  \n\nStrong fundamentals in digital design and verilog \n\nFamiliarity with low power design techniques such as multi-VT, Clock gating, Power gating, Voltage Islands and Dynamic Voltage-Frequency Scaling (DVFS)  \n\nGood background in power estimation techniques, flows and algorithms  \n\nKnowledge of power intent formats - UPF/CPF or similar \n\nExperience in Static Power check tools like VCLP/CLP or similar & Dynamic Power verification tools like VCS-NLP or equivalent \n\nWays to stand out from the crowd:  \n\nGood debugging and problem-solving skills \n\nStrong communication skills and ability & desire to work as a great teammate \n\nGood programming skills - Python preferred (Good skills with object-oriented programming & design) preferred.  \n\nExposure to Power analysis tools (such as PTPX, EPS) or exposure to lab setups for power measurements like scope/DAQ with ability to analyze board level power issues is a plus  \n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.  \n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Power Architecture Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-07-31", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Power-Architecture-Engineer_JR2019980", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. \n\nNVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! \n\nWhat you’ll be doing:  \n\nBe part of NVIDIA Power Architecture Group that owns end-to-end power aspects such as - ASIC power analysis, power architecture, low power design, power-aware verification, advanced power methodologies, UPF methodologies, power feature bring-up on silicon, and post-Si power correlation for NVIDIA's family of products. \n\nContributing to power analysis by helping to architect, develop, verify & correlate power estimation models/tools for NVIDIA's products \n\nBe part of the team that architects & designs system-level power features for optimizing the dynamic and leakage power dissipation for different usecases.  \n\nWork on power verification which includes structural, functional & power aware verification of power features of NVIDIA products by coming up with test plans, write testcases, build test bench components like Monitors, assertions and coverage points & own verification convergence across RTL, Gates and Silicon.  \n\nValidate the effectiveness of the power features on silicon, conduct studies and contribute to the Performance/Watt improvement ideas.  \n\nHelp build power management solutions and drive innovation in energy efficiency across NVIDIA’s product portfolio.  \n\nWhat we need to see:  \n\nB.Tech./M.Tech with 1+ years of experience related to Power such as Power analysis, Power Design, Power Aware Verification, UPF methodologies and Power Correlation \n\nStrong fundamentals in power including transistor-level leakage/dynamic characteristics of VLSI circuits  \n\nStrong fundamentals in digital design and verilog \n\nFamiliarity with low power design techniques such as multi-VT, Clock gating, Power gating, Voltage Islands and Dynamic Voltage-Frequency Scaling (DVFS)  \n\nGood background in power estimation techniques, flows and algorithms  \n\nKnowledge of power intent formats - UPF/CPF or similar \n\nExperience in Static Power check tools like VCLP/CLP or similar & Dynamic Power verification tools like VCS-NLP or equivalent \n\nWays to stand out from the crowd:  \n\nGood debugging and problem-solving skills \n\nStrong communication skills and ability & desire to work as a great teammate \n\nGood programming skills - Python preferred (Good skills with object-oriented programming & design) preferred.  \n\nExposure to Power analysis tools (such as PTPX, EPS) or exposure to lab setups for power measurements like scope/DAQ with ability to analyze board level power issues is a plus  \n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.  \n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Power Architecture Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-07-31", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Power-Architecture-Engineer_JR2010141-1", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. \n\nNVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! \n\nWhat you’ll be doing:  \n\nBe part of NVIDIA Power Architecture Group that owns end-to-end power aspects such as - ASIC power analysis, power architecture, low power design, power-aware verification, advanced power methodologies, UPF methodologies, power feature bring-up on silicon, and post-Si power correlation for NVIDIA's family of products. \n\nContributing to power analysis by helping to architect, develop, verify & correlate power estimation models/tools for NVIDIA's products \n\nBe part of the team that architects & designs system-level power features for optimizing the dynamic and leakage power dissipation for different usecases.  \n\nWork on power verification which includes structural, functional & power aware verification of power features of NVIDIA products by coming up with test plans, write testcases, build test bench components like Monitors, assertions and coverage points & own verification convergence across RTL, Gates and Silicon.  \n\nValidate the effectiveness of the power features on silicon, conduct studies and contribute to the Performance/Watt improvement ideas.  \n\nHelp build power management solutions and drive innovation in energy efficiency across NVIDIA’s product portfolio.  \n\nWhat we need to see:  \n\nB.Tech./M.Tech with 1+ years of experience related to Power such as Power analysis, Power Design, Power Aware Verification, UPF methodologies and Power Correlation \n\nStrong fundamentals in power including transistor-level leakage/dynamic characteristics of VLSI circuits  \n\nStrong fundamentals in digital design and verilog \n\nFamiliarity with low power design techniques such as multi-VT, Clock gating, Power gating, Voltage Islands and Dynamic Voltage-Frequency Scaling (DVFS)  \n\nGood background in power estimation techniques, flows and algorithms  \n\nKnowledge of power intent formats - UPF/CPF or similar \n\nExperience in Static Power check tools like VCLP/CLP or similar & Dynamic Power verification tools like VCS-NLP or equivalent \n\nWays to stand out from the crowd:  \n\nGood debugging and problem-solving skills \n\nStrong communication skills and ability & desire to work as a great teammate \n\nGood programming skills - Python preferred (Good skills with object-oriented programming & design) preferred.  \n\nExposure to Power analysis tools (such as PTPX, EPS) or exposure to lab setups for power measurements like scope/DAQ with ability to analyze board level power issues is a plus  \n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.  \n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Tech Lead ASIC Design Engineer", "company": "Astera Labs", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-30T11:45:27-04:00", "url": "https://job-boards.greenhouse.io/asteralabs/jobs/4719812005", "is_hardware": true, "platform": "greenhouse", "jd_text": "Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\n\nJob Description: Lead Digital Design Engineer\n\nLocation: Bengaluru, India (Hybrid)\n\nAbout Astera Labs\n\nAstera Labs is a global leader in purpose-built semiconductor connectivity solutions for AI and cloud infrastructure. Our intelligent connectivity platform enables hyperscalers and system OEMs to maximize the performance and scalability of accelerated computing through industry-leading technologies such as Compute Express Link (CXL), PCI Express (PCIe), and Ethernet.\n\nAs AI and cloud workloads continue to evolve, Astera Labs is developing innovative silicon solutions that enable the next generation of high-performance computing. We are looking for a talented Lead Digital Design Engineer to join our Silicon Engineering team and contribute to the development of cutting-edge connectivity products.\n\nPosition Summary\n\nAs a Lead Digital Design Engineer, you will be responsible for the design and implementation of complex digital IPs and SoC subsystems for next-generation AI infrastructure products. You will drive RTL development from architecture through implementation, collaborate closely with cross-functional teams, and provide technical leadership to ensure high-quality, first-pass silicon.\n\nThis role requires strong expertise in RTL design, SoC integration, and high-speed interfaces, along with the ability to mentor engineers and lead technical execution.\n\nKey Responsibilities\n\nLead the architecture, microarchitecture, RTL design, and implementation of complex digital IPs and SoC subsystems for high-performance connectivity products.\n\nDrive end-to-end ownership of design modules from specification through RTL development, integration, and silicon bring-up.\n\nDesign high-quality, synthesizable RTL using Verilog/System Verilog, ensuring optimal performance, power, area (PPA), and scalability.\n\nDevelop complex data paths, control logic, finite state machines, arbitration mechanisms, and protocol engines.\n\nDesign and implement solutions for high-speed interfaces and protocols, including CXL, PCIe, Ethernet, and AXI-based interconnects.\n\nCollaborate with Architecture teams to define microarchitecture and review functional specifications.\n\nPartner closely with Design Verification teams to develop verification strategies, debug design issues, and achieve functional closure.\n\nWork with Physical Design teams to resolve timing, power, congestion, and implementation challenges through RTL optimization.\n\nSupport synthesis, lint, CDC/RDC, STA, DFT, and design sign-off activities.\n\nParticipate in design reviews and ensure compliance with RTL coding guidelines and design best practices.\n\nDrive debug and resolution of RTL, integration, and post-silicon issues in collaboration with firmware, validation, and system engineering teams.\n\nRequired Qualifications\n\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.\n\n6–12 years of experience in digital design for complex semiconductor products.\n\nStrong expertise in Verilog/System Verilog RTL design.\n\nExperience with complete ASIC design cycles from microarchitecture through RTL implementation and silicon bring-up.\n\nStrong understanding of digital design fundamentals, computer architecture, and SoC integration.\n\nExperience with synthesis, lint, CDC/RDC, STA, and RTL sign-off methodologies.\n\nExcellent debugging and analytical skills.\n\nPreferred Technical Skills\n\nExperience in one or more of the following:\n\nCompute Express Link (CXL)\n\nPCI Express (PCIe)\n\nEthernet MAC/PCS\n\nHigh-speed networking or connectivity IP\n\nAXI-based SoC architecture\n\nDMA engines\n\nPacket processing pipelines\n\nCache coherency protocols\n\nMemory controllers\n\nHigh-speed interconnects\n\nTools & Methodologies\n\nVerilog/System Verilog\n\nSynopsys Design Compiler\n\nCadence Genus\n\nSpyGlass (Lint/CDC/RDC)\n\nStatic Timing Analysis (STA)\n\nGit or other version control systems\n\nPython, Tcl, Perl, or Shell scripting\n\nPreferred Experience\n\nExperience designing connectivity, networking, storage, or AI accelerator silicon.\n\nProven track record of delivering successful ASIC or SoC tape-outs.\n\nFamiliarity with high-speed protocols and data center technologies.\n\nExperience working in cross-functional global engineering teams.\n\nExposure to low-power design methodologies and Design for Test (DFT) is a plus.\n\nWhy Join Astera Labs?\n\nAstera Labs is redefining connectivity for AI and cloud infrastructure. As a Lead Digital Design Engineer, you'll work on industry-leading technologies that power next-generation data centers and accelerated computing platforms. You'll collaborate with world-class engineers, solve complex design challenges, and play a key role in delivering innovative semiconductor solutions that shape the future of AI.\n\n \nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.", "jd_status": "stored"}, {"title": "Lead Power and Performance Attainment Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-07-30T11:43:00+00:00", "url": "https://global-external-amd.icims.com/jobs/86700/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Power and Performance Attainment Engineer AMD’s Datacenter Performance Group is seeking a senior Power & Performance Architect for driving the Power Constrained Performance of our industry-leading AI/ML/HPC GPUs. The role will involve owning the Perf@Power attainment of a leading generation of our Instinct accelerators, providing cross-functional leadership for a virtual team that drives all aspects of Perf@Power attainment, including pre-Si modeling, post-Si correlation, workload analysis, setting PPA targets and driving attainment, power/perf roll-ups and reporting, methodology innovations and development. Being passionate about performance and power efficiency, influence without authority and excellent communication skills are key ingredients for success in this role. KEY RESPONSIBILITIES: • Own power-constrained performance modeling, projections, implementation target setting and attainment tracking from Concept-exit (pre-si) to Product launch (post-si) for AMD Instinct AI/ML/HPC accelerators • Work with business unit and product architecture to define product configurations, capabilities and P&P targets • Cross functionally lead P&P attainment by working with various engineering functions including SOC architecture, System Design, IP Design, Circuit Design, Foundry team, CAD, Physical Design, Software, Power Management, Post-si validation • Roll-up Power/Performance readouts, present in executive forums, motivate cross-functional teams on power efficiency improvements • Mentor junior engineers and develop skillsets and methodologies in the team for important PPA domains like Power Modeling at various stages of SoC development, Cdyn/Leakage/STA/Area trade-offs and attainment, Silicon Power/Performance debug, Post Si calibration of models, Work-load power analysis KEY QUALIFICATIONS: • Background in Computer Architecture, Processor/Accelerator development • Experience in Power/Performance projections, modeling and optimization at SoC or System level • Familiarity with digital logic physical design and power management techniques (clock gating, power gating, V-F curves, p-states, on-die voltage regulation, clock integrity, etc..) • Familiarity with post-silicon power/performance debug, model correlation • Fluency in communicating with various engineering teams, business leads and executive management • Knowledge of DL/ML/LLM/MoE workloads will be a bonus EDUCATION: • Bachelor’s or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or related #DC-GPU #LI-SG2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Package Design Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-07-30T08:23:50.731000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000140625950-senior-package-design-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are looking for a Package Design Engineer to join our advanced silicon packaging design and simulation team and contribute to the design and delivery of high‑performance 2.5D/3D, chiplet‑based, FCBGA, SiP, wire bond and QFP/QFN packages used in industry‑leading products. The role requires strong technical depth in package layout execution, manufacturability, and cross‑domain co‑design with silicon, SI/PI, thermal, and reliability teams.\nKey Responsibilities\nPerform package layout design and development for advanced packages including 2.5D/3D IC, FCBGA, SiP, and multi‑chip modules.\nDevelop and maintain package CAD databases, ensuring accuracy and adherence to design guidelines, Design for Manufacturing (DFM), and Design for Assembly (DFA) requirements to ensure producibility.\nManage end-to-end design cycle, including schematic creation, netlist import, footprint assignment, and generation of manufacturing outputs (Gerbers, drill data, fabrication/assembly drawings).\nCreate and modify substrate/RDL layouts, bump maps, escape routing, and power/ground structures.\nWork closely with SI/PI, thermal, reliability, and DFT teams to support co‑design and optimization and participate in design reviews.\nEnsure designs comply with foundry, OSAT, and manufacturing design rules (DRC, LVS).\nSupport ECO cycles, design updates, and version control throughout the project lifecycle.\n\nMinimum Qualifications\n6+ years of hands‑on experience in package CAD layout and development.\nStrong experience with 2.5D / 3D IC packaging, FCBGA and advanced substrate‑based packages, multi‑die and chiplet‑based designs.\nProficiency in industry‑standard tools such as: Cadence Allegro Package Designer (APD / SiP), Siemens Xpedition / Innovator 3D IC, or equivalent.\nExperience working with advanced manufacturing design rules and interface with OSATs.\nGood understanding of Signal Integrity (SI) and Power Integrity (PI) fundamentals and High‑Speed Design concepts.\nStrong communication, presentation, and documentation skills with the ability to work effectively in a team environment.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Staff Engineer – RV (EM/IR)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-30T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719763569", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n\nWe are looking for an experienced EM/IR Engineer to lead power integrity and reliability signoff activities for advanced-node SoC designs. In this role, you will drive IR drop and electromigration (EM) analysis, define signoff methodologies, and collaborate with cross-functional teams to achieve robust and reliable silicon implementation. The ideal candidate should possess deep expertise in power integrity analysis, a strong understanding of advanced-node challenges, and proven experience in leading signoff closure for complex chip designs.\n\nWhat You’ll Do\n \nLead full-chip and block-level IR drop and electromigration (EM) analysis for advanced-node SoC designs\nDrive power integrity signoff closure by identifying, debugging, and resolving IR/EM violations\nCollaborate with Physical Design, Power, Package, and Foundry teams to optimize power delivery networks\nDefine and improve EM/IR methodologies, automation flows, and signoff strategies\nPerform static and dynamic IR analysis across multiple operating conditions and scenarios\nAnalyze power grid robustness, current density, and thermal impacts to ensure design reliability\nSupport tapeout activities and ensure high-quality signoff delivery within project timelines\n \nWhat We’re Looking For\n \nBachelor’s or Master’s degree in Electronics, Electrical Engineering, or VLSI-related discipline\n10+ years of experience in IR/EM analysis, power integrity, or Physical Design signoff\nStrong understanding of power integrity concepts including static/dynamic IR drop, EM analysis, and power grid optimization\nHands-on experience with industry-standard tools such as Cadence Voltus, Ansys RedHawk, or equivalent\nGood understanding of Physical Design flow including floorplanning, placement, CTS, routing, and extraction\nStrong scripting skills in Tcl, Python, Perl, or Shell for automation and flow development\n \nGood to Have\n \nExperience with advanced technology nodes such as 7nm, 5nm, 3nm, or below\nExposure to package-aware analysis, thermal analysis, and low-power methodologies\nExperience in leading signoff closure for large-scale SoC or high-performance compute designs\n \nSuccess in This Role Looks Like\n \nAchieving robust IR/EM signoff with minimal iterations and successful tapeout execution\nEarly identification and resolution of power integrity risks impacting performance and reliability\nImproved signoff productivity through methodology enhancements and automation initiatives\nStrong technical leadership and collaboration across implementation and signoff teams\n \nLocation\n\nOn-site – Bengaluru\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "PDK Extraction Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-30T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719771994", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nMinimum 5 years’ experience in a hands-on PDK role\n\nExpertise in Calibre/ICV runset coding for DRC/LVS/ERC/PERC/ESD/Latch-up/Antenna….\nExperience with developing and customization of the StarRC/Calibre-xACT/QRC parasitic extraction flows\nAs a member of the Physical Verification CAD team, you will maintain and improve all aspects of physical verification flow and methodology  \nCode custom checks such as Layout/Programmable ERCs, addition of custom devices in LVS, implementation of custom design rules(DRCs), etc to meet the needs of the design teams\nYou will need to have a deep understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, writing from scratch and/or modify existing ones.\nProficiency in integration and tech setup of Calibre LVS with StarRC/QRC and other Extraction tools\nUtilizing your hands-on skills to revamp/rewrite and streamline the PEX flow\nUnderstanding of Digital/Custom/Analog requirements for various post layout electrical flows\nDevelopment of custom extraction solutions for transistor level to meet the needs of the design teams\nHands on experience with the Field solvers and RC reduction tools\nSupport design teams with solving their PEX challenges\nSupport the design teams with solving their PV challenges to facilitate the IP release and Chip tapeouts\nCollaborate with tool vendor and foundries for tools and flow improvements\nKnowledge of deep sub-micron FINFET, Planar, SOI and PMIC process technologies and mask layout design\nProficiency in one or more of the programming/scripting languages – SKILL, Python, Unix, Perl and TCL.\nGood communication skills and ability to work collaboratively in a team environment\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Engineer- DEG Layout", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-30T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/43365113", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nRole and Responsibilities\nResponsible for layout design and development of critical analog, mixed-signal, custom digital block, standard cells  and full chip level.\nPerform layout verification like LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem checks,  quality check and documentation.\nResponsible for development of digital block layouts using auto placement and route tools\nResponsible for basic understanding of skill coding and automation\nResponsible for on-time delivery of block-level layouts with acceptable quality.\nDemonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/achievements in multiple project environment.\nGuide developing team members in their execution of Sub block-level layouts & review their work\nContribute to effective project-management.\nEffectively communicating with Global engineering teams to assure the success of layout project.\nResponsible for the reducing the layout effort by using AI tools\n\nQualification/Requirements\n5 to 8-year experience in analog/custom layout design in advanced CMOS process.\nExpertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.\nShould have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,\nGood understanding of Analog Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc.)\nUnderstanding layout effects on the circuit such as speed, capacitance, power and area etc.,\nAbility to understand design constraints and implement high-quality layouts.\nExcellent command and problem-solving skills in physical verification of custom layout.\nMultiple Tape out support experience will be an added advantage.\nExcellent verbal and written communication skills.\nExcellent verbal and written communication skills.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Senior Design Verification Engineer", "company": "Lattice", "location": "Hyderabad, India", "date_posted": "2026-07-30", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Hyderabad-India/Senior-Design-Verification-Engineer_R-102415", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nResponsibilities:\nDraft DV scope, strategy & feasibility in response to marketing requirements\nDevelop test plans based on Design Specifications\nDesign & Implement constrained-random testbenches & metrics\nCode & Execute tests, Debug encountered issues\nCollate & Analyze test results to closure\nRequirements:\nBS or MS in Computer/Electronics/Electrical Engineering with a minimum of 5 years of relevant design verification experience.\nGood communication, collaboration & documentation skills.\nGood grasp of & Hands-on experience with SystemVerilog/UVM, with solid understanding of different available SV/UVM constructs. Experience with languages like Python, make, C, C++ is an advantage.\nGood analysis & debugging skills. Understanding of HDL & FPGA concepts is an advantage.\nExperience with industry standard digital design simulators & debugging tools. Experience with Siemens EDA tools specifically is an advantage. Experience with Perforce, Git, Jenkins, & generative AI is also an advantage.\nExperience in the following technology areas is an advantage: Cryptography, Security, AMBA protocols, SPI, I2C/I3C\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Staff Digital Design Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-07-30", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Staff-Digital-Design-Engineer_R-10062734", "is_hardware": true, "platform": "workday", "jd_text": "Job Description\n\nRole Summary\nWe are seeking a Senior Lead Digital Designer to lead the architecture, implementation, and integration of digital subsystems for Automotive Ethernet PHY products (10BASE‑T1S, 100BASE‑T1, 1000BASE‑T1, and multi‑gig automotive SerDes technologies).\nThe role involves driving digital micro-architecture, state machines, PCS functionality, safety mechanisms, and end‑to‑end digital design across the PHY.\n\nKey Responsibilities\n1. Architecture & Technical Leadership\nDefine and own digital subsystem micro‑architecture for Automotive Ethernet PHYs, including:\nPCS pipelines and encoding/decoding logic\n\nScramblers/descramblers, CRC engines, alignment & framing\n\nPacket processing, link monitoring, error handling\n\nInterface logic (MII, RMII, RGMII, GMII, XGMII depending on product line)\n\nProcessor based SoC design\n\nPerform system‑level partitioning between digital, analog/mixed-signal, and firmware components.\n\nLead feasibility studies, power/performance trade-offs, and digital architecture exploration.\n\n2. RTL Design & Implementation\nDevelop high-quality RTL (Verilog/SystemVerilog) for control, datapath, and protocol logic.\n\nDrive digital front-end flows including:\nLint, CDC/RDC, reset architecture, synthesis guidance\n\nTiming constraints and logic optimization\n\nWork with DV to define coverage goals, corner cases, and feature verification plans.\n\n3. System‑Level Ownership\nTranslate system requirements, IEEE 802.3 specifications, and architecture documents into robust digital designs.\n\nWork with mixed-signal teams to define:\nControl interfaces to analog front‑end blocks\n\nCalibration engines, register programming flows, and digital‑analog interaction models\n\nContribute to bring‑up sequences, compliance testing, and system validation.\n\n4. Automotive Quality & Functional Safety\nEnsure compliance with Automotive Ethernet standards, ISO 26262, and AEC‑Q100 expectations.\n\nDefine and implement:\nSafety mechanisms (BIST, LBIST/MBIST, error detection schemes)\n\nDiagnostic monitors, timeout recovery logic, watchdogs, and fault reporting\n\nParticipate in FMEDA, DFA, and functional safety analysis.\n\nRequired Qualifications\nMasters in Electrical Engineering, Computer Engineering, or related discipline.\n\n7+ years experience in digital design for PHY, SerDes, networking ASICs, or communication ICs.\n\nStrong expertise in:\nVerilog/SystemVerilog RTL design\n\nHigh‑speed digital logic, state machines, control logic\n\nIEEE 802.3 Ethernet PCS, link training, and system control flows\n\nSynthesis, STA, CDC/RDC methodology\n\nProven track record across multiple production tape-outs.\n\nPreferred Qualifications\nExperience with Automotive Ethernet standards: 10BASE‑T1S, 100BASE‑T1, 1000BASE‑T1, 10GBASE‑T1.\n\nFamiliarity with PHY firmware-driven initialization and configuration flows.\n\nStrong debugging skills with logic analyzers, protocol analyzers, and post-silicon validation.\n\nBackground in safety‑critical digital logic designs.\n\nMore information about NXP in India...\n\n#LI-7013", "jd_status": "stored"}, {"title": "Senior Design Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-07-30", "url": "https://careers.arm.com/job/bengaluru/senior-design-engineer/33099/98510713136", "is_hardware": true, "platform": "talentbrew", "jd_text": "We are looking for a motivated and innovative Senior Design Engineer to develop innovative IPs and technologies for next-generation SoCs. If you enjoy solving complex design challenges, collaborating across teams, and influencing future architectures, this role is for you.\nResponsibilities:\nDevelop high-quality IP and technology components for advanced SoCs.\nWorking with Architects to refine and translate architecture specifications and translate them into detailed design specs.\nOwn micro-architecture, RTL coding, bug fixing, and design quality checks.\nCollaborate with verification teams on test plan reviews and debug activities.\nImprove and evolve design methodologies, flows, and guidelines.\nMentor and support junior team members to ensure successful project execution.\nRequired Skills and Experience:\nBachelor’s/Master’s degree in CS, EE, or CE\nSkilled in design for IPs/Sub systems with 5+ years of experience\nSynthesis & timing analysis\nPower management and low-power design techniques\nClock & power domain implementations\nDigital hardware design and Verilog HDL.\nStatic checks (Lint, CDC, RDC, Power checks)\nExperience writing design & micro-architecture specifications.\nHands-on RTL development expertise.\nProficiency with scripting (Perl, Python, etc.).\n“Nice To Have” Skills and Experience:\nExperience with ARM-based designs or ARM System Architectures.\nExposure to:\nAdvanced synthesis checks\nFunctional verification, X-propagation, GLS etc\nDFT and physical implementation flows\n10x Mindset at Arm\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Read more about how we bring the 10x mindset to life on the Arm blog.\n \n#LI-SC2\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Program Management Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-07-30", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010510", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n Texas Instruments (TI) is looking for an energetic, service minded leader, who enjoys helping others to succeed by providing team members and clients with motivation and support in a positive and professional work environment as a Program Management Engineer. We are seeking a highly motivated individual who will challenge teammates to achieve flawless execution goals, while maintaining strong working relationships. Success in this role is measured by the ability to grow the number of new products and drive the forecasted return on investment.\n\nResponsibilities include:\n\nLead a cross functional team on the execution of releasing new products and ensuring successful return on investment for every development; the team consists of Design, Marketing, Systems& Applications, Validation, Product& Test Engineering, Firmware/Software Engineering, Manufacturing, Field, and Quality\n\nWork with wafer fabrication, assembly& test sites to guarantee schedule, cost and quality\n\nPlan the project using MS Project from Assess Opportunity Phase to Release to Market and is responsible to make sure the project comes in on budget\n\nProvide clear direction to both, team and external support organizations like device fabrication and assembly and test sites\n\nDrive and motivate all team members critical to the flawless execution of each product and project\n\nProvide weekly and monthly updates to senior management on status of projects, explaining the issues facing a project\n\nInteract with customers in support of project status, key milestones, and deliveries. This includes samples deliveries, special work requests, wafer lot starts and reliability tests\n\nPerform product reliability and characterization of integrated circuits to ensure they meet the product requirement specifications and manufacturing requirements\n\nWork with failure analysis (FA) to determine root cause of any reliability and qualification failures\n\nMaintain thorough and up-to-date project schedules with all related milestones\n\nDevelop and implement Qualification plans\n\nCommunicate weekly to management on status of each project\n\nEffectively coordinate material logistics and shipment/assembly/test prioritization\n\nSuccess will be measured by the ability to grow the number of new products and drive the forecasted return on investment.\n\nQualifications\nMinimum requirements:\n\nBachelor's in electrical engineering or related engineering degree\n\nExperience with project engineering/management experience on highly complex products/projects\n\nProven leadership capabilities in leading multifaceted global organizations\n\nSuccessful proven track record in indirect management and influence\n\nPreferred qualifications:\n\nAbility to manage multiple projects simultaneously, and set realistic plans based on required tasks with available resources\n\nAbility to effectively coordinate and lead global development teams on projects that include design, silicon fabrications, production test development, qualification and production ramp; Programs will be driven out of multiple global locations\n\nAbility to provide clear direction to both internal teams and external support organizations like device fabrication and assembly sites\n\nKnowledge of device packaging and wafer fabrication process\n\nKnowledge of reliability requirements and tri-temp characterization methodology using statistical analysis\n\nAbility to work in a team environment and understand cross-functional team dynamics\n\nDemonstrated strong analytical and problem solving skills\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nStrong time management skills that enable on-time project delivery\n\nDemonstrated ability to build strong, influential relationships\n\nAbility to work effectively in a fast-paced and rapidly changing environment\n\nAbility to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Sr Staff Engineer, Physical Design", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-07-30", "url": "https://careers.synopsys.com/job/bengaluru/sr-staff-engineer-physical-design/44408/98689551776", "is_hardware": true, "platform": "talentbrew", "jd_text": "Sr Staff - Physical Implementation Flow (experience - 8+ Years)\n\nWe Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nYou are a highly skilled and experienced ASIC Digital Design Engineer passionate about working on the latest processes for physical implementation flows and cutting-edge technology nodes. You thrive in dynamic environments and excel in collaborating with functional teams to optimize and develop Next Gen PCI/CXL/IDE Controller IPs. You have a strong focus on Timing Closure and are adept at defining signoff criteria. Your background includes extensive experience with ASIC design flow, hierarchical physical design strategies, and a deep understanding of sub-micron technology issues. You possess a strong knowledge of timing analysis, constraints management, and various verification strategies, including Primepower-based power analysis. Your scripting skills are excellent, and you are innovative, self-motivated, and able to work both independently and as part of a team. Your communication skills, both verbal and written, are outstanding, and you have a desire to understand RTL/Timing signoff criteria.\nWhat You’ll Be Doing:\nWorking on new processes for physical implementation flows and cutting-edge technology nodes.\nCollaborating with functional teams to optimize and develop Next Gen PCI/CXL/IDE Controller IPs.\nDefining signoff criteria with a strong focus on Timing Closure.\nMaturing the physical implementation guide used for customers and internal hardening teams.\nParticipating in next-generation physical design methodology and flow development.\nPerforming physical design implementation, including synthesis, floor planning, PG Grid design, PnR, CTS, STA, and power/signal integrity signoff.\nEvaluating PPA targets (Area/Speed/Power) and collaborating with the design team to improve design and constraints.\nThe Impact You Will Have:\nDriving the development of next-generation physical design methodologies and flows.\nEnsuring the optimization and successful implementation of cutting-edge technology nodes.\nContributing to the development of high-performance silicon chips and software content.\nEnhancing the efficiency and performance of Synopsys’ IPs through rigorous timing closure and signoff criteria.\nImproving customer satisfaction by maturing physical implementation guides.\nSupporting the achievement of Synopsys' operational goals through innovative design solutions.\nWhat You’ll Need:\nExtensive experience with ASIC design flow and hierarchical physical design strategies.\nStrong background in timing analysis, constraints management, and frontend synthesis.\nExperience with physical-aware synthesis, formality, and various verification strategies.\nKnowledge of Primepower-based power analysis and clock gating for power reduction.\nFair knowledge of FC design planning methodologies, floor planning, and PG Grid creation using Synopsys Tools.\nStrong physical implementation flow debugging skills and scripting abilities.\nWho You Are:\nInnovative, self-motivated, and able to work independently or as a team player. Excellent verbal and written communication skills. Strong analytical and problem-solving abilities. Passionate about continuous learning and staying updated with the latest technological advancements in ASIC digital design.\nThe Team You’ll Be A Part Of:\nYou will join a highly skilled and collaborative team focused on developing and optimizing physical design flows for cutting-edge technology nodes. The team is dedicated to innovation, continuous improvement, and delivering high-performance solutions that meet the evolving needs of our customers.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior Engineer, Test Engineering", "company": "Analog Devices", "location": "India, Bangalore, Nova", "date_posted": "2026-07-30", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-Nova/Senior-Engineer--Test-Engineering_R264104-1", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nSenior Test Engineer - Product Development\n\nJob Description\nADI’s Hearables and Audible Solutions Business Unit is looking for a Senior engineer in test product development at our Bangalore location. The candidate will become an integral part of the Product & Test Engineering (PTE) activities for the development of mixed signal audio edge processors and battery management power products. The candidate will also be part of pre & post-silicon phase of the silicon development from DFT to silicon bring up / characterization to high volume production. The ideal candidate will be technically strong and will have demonstrated experience in testing both Digital and Analog/Mixed-Signal (AMS) Products, working with cross functional teams like Design, Bench Eval, PD, etc., with ability to collaborate with ADI global teams and off-shore subcons. \nJob Responsibilities:\nDesign of innovative, reliable, and efficient Probe and Test solutions with highly parallel multi-site test capability using mixed signal/Digital ATE platforms (primarily ultra-flex or NI)\nDevelopment of the ATE software solutions as per the specifications.\nPlay a role in DFT/BIST definition & development, through direct involvement with the Design Team early in the New Product Development, to reduce FFC and improve testability.\nExecution of the Test development phases of the projects including Silicon functionality, Characterization, Yield Analysis, Correlation & Offshore Production release.\n\nQualifications:\nHave a degree in Electrical/Electronic Engineering\nHave 5-7years’ of hands-on experience in mixed signal or digital test.\nHave knowledge of the ATE software development and working knowledge of Teradyne Flex and/or 93K ATE systems.\nHave good analytical & statistical skills and knowledge of the Perl/C++ programming.\nBe experienced in ATE highly parallel multi-site test digital h/w design & layout, with lead skills in understanding the problems/limitations in hardware development.\nBe experienced in releasing multi-site test programs to offshore production test houses.\nBe well versed with the usage of bench equipment such as Oscilloscope, VI-meter, Signal generator and analyzers.\nBe capable of working with the reliability engineers on the product qual\nBe proactive and work under own supervision.\nBe self-motivated, and willing to accept responsibility.\nPossess strong interpersonal, teamwork & communication skills.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Audio System Development Engineer, Silicon and Systems Group", "company": "Amazon", "location": "Bengaluru, Karnataka, IND", "date_posted": "2026-07-30", "url": "https://www.amazon.jobs/en/jobs/10488198/audio-system-development-engineer-silicon-and-systems-group", "is_hardware": true, "platform": "amazon", "jd_text": "Amazon Lab126 is an inventive research and development company that designs and engineer’s high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced ground-breaking devices like Fire tablets, Fire TV and Amazon Echo.\n\nWork hard. Have fun. Make history.\n\nWe are looking for an Embedded System Development Engineer- to help design, develop, integrate our next generation devices.\nIn this role you will work with customers, system architects, program managers and hardware engineers to design, implement, troubleshoot, fix  kernel drivers, Audio SW, BSP for our next generation devices.\n\nYou will be responsible for the development of real-time embedded firmware and embedded Linux software that implements audio features.\n\nKey job responsibilities\nIf you have one or more of the below skills, then this job is for you:\n- Exposure to ALSA / Pulse Audio\n- Exposure to Audio software stack on Android/QNX/proprietary OS including Audio Flinger, Audio HAL\n- Exposure to ARM, DSP architectures\n- Exposure to Dolby MS12 / DTS/ MPEG-TS\n- Exposure to Audio/Video Sync\n- Exposure to STB / DTV audio systems\n- Working knowledge of Oscilloscope, Logic Analyzer, and Audio Tools including Audio Precision\n\nKey job responsibilities\nIn this role, you will:\n- Develop audio software that runs on ARM/DSP using Bare metal, Linux and other high level OSes\n- Optimization and porting audio and speech processing algorithms\n- Integration of vendor hardware and software stacks\n- Tune hardware for highest audio performance and lowest noise\n\nAbout the team\nAmazon Lab126 is an inventive research and development company that designs and engineer’s high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced ground-breaking devices like Fire tablets, Fire TV and Amazon Echo.\n\nBasic qualifications\n- 2+ years of systems development experience\n- Experience with embedded systems\n- Bachelor's degree", "jd_status": "source_unavailable"}, {"title": "Sr. Memory Layout Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-07-30", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Sr-Memory-Layout-Design-Engineer_R026710", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nJob Requirements:\n- Bachelor's degree with 12 years of experience or a Master's degree with over 10 years of experience.\n- Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - Calibre & Hercules).\n- Strong layout knowledge in submicron processes (e.g., 7nm, 5nm, 3nm, 2nm).\n\nKey Responsibilities:\n- Understand and apply layout guidelines, new process rules, and technical requirements for high-quality layouts.\n- Manage scheduling, timelines, and layout floor-planning.\n- Ensure end-to-end deliverables are completed with high quality and within the planned schedule.\n- Adapt quickly to new methodologies and communicate effectively with the SOC and library teams.\n\nSkill Set(Memory):\n- Strong experience in memory layout design and physical verification (LVS, DRC, ERC, Antenna, Electro Migration).\n- Experience with Cadence Layout tools (Virtuoso XL, VXL, or EXL) and Calibre verification tools.\n- Proficiency in floor-planning, hierarchy layout, and chip integration.\n- Solid understanding of memory architecture and RC requirements, with the ability to plan signal and power routing.\n- Ability to lead teams, train junior engineers, and manage projects effectively.\n- Strong knowledge of memory layout topology; experience with memory compilers is preferred.\n- Knowledge of AI, layout automation, and script/SKILL programming is preferred.\n- Ability to lead new technology reviews to document layout methodologies, flows, and guidelines.\n- Self-reliant with the ability to work both independently and collaboratively.\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Senior Staff Engineer, Product Definer (IC Architect)", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-07-29T17:30:05.751000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000140522229-senior-staff-engineer-product-definer-ic-architect-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking a talented and motivated person to join as a manager of system and application team to own and define next generation products and support customer for India for India business division with focus on power products. \nA successful candidate will have strong desire and ability to work in a technically challenging and entrepreneurial environment. To succeed, candidate will need to combine deep technical understanding of power management, Renesas products and customer systems. You will engage in product definition as well as customer support activities. Your ability to work across functional groups through formal communication and direct interaction is critical to success. The position requires significant technical experience in power management as well as understanding of firmware-enabled and embedded system (attach to SoC) products. The candidate will work closely with management, sales and engineers based in India while coordinating efforts with a global team. \nResponsibilities :\nIdentify market opportunities and collaborate with Marketing team, Business Division management, and Sales to exploit these opportunities \n\nSupport marketing/Sales/FAEs to facilitate the design-in of our products as well as providing technical assistance to address customer technical questions such as customer circuit design review, debug, troubleshooting and field return analysis. \n\nUse knowledge gained to support marketing business plan including TAM/ SAM / SOM) activities by providing analysis demonstrating technical merit of Renesas solutions vs competing solutions. \n\nProvide deep technical support and training to advance Renesas’s commercial success. Requires ability to translate complex ideas or implementations to a level suitable for less experienced audiences such as customers or field sales staff. \n\nWork with the broader marketing team and design team to develop customer collateral that raises the company's profile \n\nUnderstand market and customer requirements and define product requirements and improve product roadmaps \n\nDefine product family roadmap \n\n·Produce technically detailed Product Requirements and / or design specifications documents. \n\nWork with design engineering when conflicts arise between requirements, capabilities and business expectations. \n\nInterpret device level system use cases and requirements and translate to product specifications while ensuring specifications meet customer needs by working with customers and internal teams \n\nCompare of design trade-offs and IP choices to achieve competitive product specifications \n\nParticipate in FPGA based design prototyping to verify key features and functions will meet expectations. Work with design and other staff to find solutions when targets are not met. \n\nGuide staff in creation of Applications Validation Plans by using experience to ensure corner cases are covered \n\nPerform physical silicon device evaluation at board level based on defined evaluation plans, including understanding the silicon behavior and functionality in detail. \n\nDrive system modelling requirement \n\nSupport hiring and managing the necessary team as per business need over time \n\n \n\nComfort and ability to collaborate and be effective in an entrepreneurial (fast-paced and ambiguous) environment \n\nExcellent interpersonal, communication and presentation skills and comfort in presenting to a wide range of audiences. Capable to communicate issues in a concise and effective way. \n\nDesire and drive to interact with, as well as ability to build and maintain excellent relationships with internal and external stakeholders. \n\n Product ownership mentality \n\n12+ years of experience in power management space, ideally including product definition, with semiconductor companies \n\nTravel will be required \n\nBachelor or Masters of Electronics Engineering or related discipline \n\nAbility to build a strong team and motivate individuals to work out of their comfort zone \n\nSelf-driven, strongly motivated individual capable to take full ownership of their activities, and to involve other functions in the company or management when needed to bring them to a successful outcome. \n\nUnderstanding of power management applications and products. \n\nTechnical proficiency: \nHands-on experience and ability in lab debugging, probing and characterizing circuit and silicon using a mixture of custom-made and standard equipment such as power supplies, e-load, digital oscilloscopes, spectrum analyzers, etc. \n\nBoard level analog and digital circuit design expertise and PCB schematic design \n\nSIMPLIS or similar ckt simulator \n\nUnderstanding of control loop theory and its application in power converters \n\nExperience using FEA tools for various thermal, electrical and magnetic investigations \n\nProgramming proficiency in C and Python \n\nPCB CAD tools for both schematic and layout. \n\nProficiency with a full complement of lab equipment including network analysers, oscilloscopes and waveform generators. Experience with automation of lab testing. \n\nData analysis using Excel or JMP \n\nUnderstanding of AECQ / IATF /ISO26262 (FuSa) (At least basic level) \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "RTL(NOC)Design-Sr Lead/Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-29T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719901848", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    8+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates complex features and functionality into hardware designs in line with proposals or roadmaps for complex products.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the novel manufacturing of solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for complex Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making is significant in nature and affects work beyond immediate work group.\n•    Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. \n•    Has a moderate amount of influence over key organizational decisions.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Signal Integrity Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-29T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720179222", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer,\n\nTitle - Staff Signal Integrity Engineer\n\nThis role represents individual contributor within the CHS Signal Integrity organization responsible for end-to-end SI/PI architecture, analysis, and signoff for next-generation mobile, compute, Automotive and various other connectivity platforms.\n\nThe engineer acts as\nSystem SI/PI owner across full platform (SoC ↔ package ↔ board ↔ connectors ↔ external systems)\n\nTechnical owner for high-speed interfaces and system margins\n\nCross-functional leader driving SIPI driven design convergence across silicon, package, and platform teams\n\nCore Responsibilities\nOwn end-to-end SI/PI closure for programs (pre-silicon → post-silicon → production)\n\nDefine design targets and layout design guidelines for all high-speed interfaces\n\nInfluence architecture decisions early in product lifecycle\n\nEnsure SI/PI alignment with product KPIs (performance, yield, power, cost)\n\nDrive new IP co-design across IC/IO/PHY, package, and PCB\n\nEnsure compliance to standards (JEDEC, PCI-SIG, MIPI, IEEE)\n\nInfluence PDN architecture definition at system and package level, provide related optimum cost solutions\n\nEnsure cross functional alignments. Partner with SoC/PHY design teams, Package engineering, Board/system teams and OEM/ODM ecosystem\n\nLead design reviews and signoff decisions\n\nRepresent SI/PI in program reviews and leadership forums\n\nDefine company-wide SI/PI methodologies\n\nDrive correlation between pre-silicon models and silicon/lab data\n\nLead debug of eye collapse / jitter margin issues, crosstalk and power noise and silicon-package-board interactions\n\nDrive best practices adoption across programs\n\nEstablish golden methods for system SI/PI\n\nMentor senior engineers across SI/PI domains\n\nHigh-Speed Interface Expertise\nDrive SI/PI for interfaces such as:\nMemory: LPDDR4/5/6\n\nHigh-speed IO: PCIe Gen4/5/6/7, USB4, UFS, 10G–112G+ PHYs\n\nCamera/Display: MIPI CSI/DSI\n\nSystem PDN\n\nRequired Qualifications / Experience\n12+ years in Signal Integrity / Power Integrity / High-speed systems\n\nProven ownership of multiple tapeouts or high-volume products\n\nDomain Expertise\nDeep expertise in Transmission line theory, EM fundamentals, SI/PI interactions and jitter/noise coupling. Strong hands-on experience with: Tools: HFSS, ADS, Sigrity, CST, SIwave, HSPICE; Measurement: VNA, TDR, real-time scopes\n\nPreferred Differentiators\nExperience with: Packaging technologies like FCBGA, 2.5D/3D; Products like Data center, Compute and Servers\n\nTrack record of Patents, standards contributions, or published work internal / external conferences\n\nyou will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "AI Automation Engineer, Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-29T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718784040", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nWe are looking for an engineer to build AI-driven solutions that improve and automate RTL front-end design and implementation flows. The focus is on using agentic AI frameworks and modern open-source tooling to streamline common RTL-to-GDS workflow tasks and reduce manual effort. \n \nKey Responsibilities\nDevelop AI-based tools/agents to optimize RTL design/DV and front-end flow execution, including automation around analysis, checks, and flow tasks. \nBuild and maintain agentic workflows using modern open-source ecosystems (e.g., LangChain/CrewAI or similar frameworks). \nCreate and improve automation and scripting that integrates with design tools and existing engineering workflows. \nWrite, review, and maintain Python code with good engineering practices (readability, testability, maintainability). \nQuickly learn and adopt new AI packages and evolving best practices, as the ecosystem changes rapidly. \n \nRequired Qualifications\nStrong hands-on experience with Python scripting/automation (comfort writing + reviewing code). \nBasic understanding of VLSI RTL → GDS flow and common front-end stages (RTL/design checks/synthesis/STA/CDC/formal/DV, etc.). \nPractical familiarity with agentic AI frameworks and tooling (LangChain, CrewAI, LangGraph, or similar open-source stacks). \nAbility to work independently, iterate quickly, and learn new tools/packages fast. \n \nNice to Have\nHands-on experience applying LLM-driven techniques and solutions on large, production-quality SystemVerilog codebases \nExposure to building multi-agent systems (supervisor/worker patterns, tool-calling, memory/context, RAG).\nExperience integrating automation with engineering infrastructure and reference flows\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Principal Engineer - Design for Test", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-07-29", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Principal-Engineer---Design-for-Test_R2292-26-6", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nMicrochip AES Design team in Bangalore is looking for an experienced and motivated Design-For-Test Principal Engineer to provide test\nhardware solution for various microchip Business units. As a member of test development team, you will be responsible for understanding the\nexisting DFT test structures and clock strategy used across multiple business units and provide architectural improvements to improve test\ncoverage. The candidate should have experience with ATPG and MBIST. The candidate should have in depth knowledge of Tessent/Modus\ntool execution.\n\nRequirements/Qualifications:\n\nHands on expertise on handling DFT on hierarchical designs.\nHands on expertise on Tessent/Modus ATPG tool for DFT setup and pattern generations.\nHands on expertise on Tessent/Modus MBIST tool for MBIST hardware generation.\nHands on expertise on Tessent/Modus diagnosis tool for on-silicon debug.\nHands on expertise SCAN pattern simulations and debug.\nATPG with the pattern delivery to the test engineering team.\nSound knowledge of Scan Stitching, Scan Compression, MBIST & JTAG Techniques.\nShould have good post silicon DFT bring-up and debug experience.\nShould have a good knowledge of simulation debug and prior experience at SoC level.\nExcellent written and verbal communication skills.\nSelf-motivated team player with strong problem-solving skills to collaborate with various teams to achieve desired goals.\nExperience:\nBachelors/Masters in Electronics or equivalent degree with 9+ years of experience\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Staff Design Verification Engineer", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-07-29", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Staff-Design-Verification-Engineer_R262915", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nAnalog Devices is seeking Digital Design Staff verification Engineer, who will be responsible for design verification of highly integrated solutions and products in a multifunctional team. You will be working on driving real revenue growth on the next generation of Intelligence at the Edge products across multiple products and business units.\n\nAbout ADI:\nAnalog Devices, Inc. is a leading global high-performance analog technology company dedicated to solving our customers' most complex engineering challenges. We play a critical role at the intersection of the physical and digital world by providing the building blocks to sense, measure, interpret, connect, and power devices and systems. We design, manufacture, test, and market a broad portfolio of solutions, including integrated circuits (ICs), software and subsystems that leverage high-performance analog, mixed-signal and digital signal processing technologies. We embrace a culture of innovation and collaboration to push the state of the art.\n\nAbout the Role\nKey member of design verification team  for SOC or subsystem design pre silicon verification.  The candidate will be responsible for formulating verification strategies, Define verification architecture, Flow, Methodology and leading, driving and completing verification of large integrated products. As a senior team member, it is expected that he/she will lead and influence verification methodologies within both DBU and ADI.   The candidate is also encouraged to participate in cross company technical initiatives as well as patent and publish work where possible.\n\nResponsibilities\nLead pre-silicon verification for complex SoC or subsystem designs, driving execution from planning to closure.\n\nVerify microprocessor-based systems, AI/ML accelerators, and high-speed peripherals using advanced methodologies.\n\nArchitect and implement UVM-based testbenches, DV flows, and scalable verification methodologies.\n\nDefine and execute test plans; drive functional and code coverage closure in collaboration with design teams.\n\nWork cross-functionally with emulation, FPGA, and firmware teams to ensure end-to-end system correctness.\n\nApply formal verification techniques for IP and subsystem-level validation.\n\nLead NoC/interconnect verification and ensure robust data flow across the system.\n\nPerform system-level use case validation, including performance verification and analysis.\n\nDevelop and validate end-to-end scenarios to ensure real-world functionality.\n\nDrive innovative verification strategies to meet quality and schedule goals.\n\nDefine overall verification strategy based on product requirements and design specifications, leveraging modern techniques such as formal, emulation, portable stimulus, and virtual platforms.\n\nRequirements\nB.Tech/M.Tech with 8+ years of experience in digital pre-silicon verification.\n\nStrong understanding of SoC/subsystem architectures with hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development and debugging.\n\nProven experience in verification closure using functional and code coverage metrics at block and subsystem levels.\n\nExpertise in NoC, bus, and interconnect verification, including coverage analysis and optimization.\n\nExperience in architecting testbench environments and implementing scalable DV flows and methodologies.\n\nHands-on experience in power-aware verification using UPF, including power analysis and optimization.\n\nExposure to formal verification, including flow setup, connectivity, and functional checks.\n\nFamiliarity with gate-level simulations (GLS) with timing annotation.\n\nStrong knowledge of test planning, constrained-random verification, assertions, and transaction-level modeling using SystemVerilog.\n\nUnderstanding of processor-based systems (ARM, RISC-V, Tensilica), AI/ML or GPU-based architectures is a plus.\n\nProficiency in C/C++, SystemC, and scripting (Python/TCL/Shell).\n\nExcellent communication and collaboration skills with the ability to work across global teams.\n\nStrong problem-solving ability with a mindset to quickly learn and adopt new technologies.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Principal Design Engineer ( Layout Design )", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-07-29", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Design-Engineer---Layout-Design--_R53821", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\n\nCadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.\n\nThe Cadence Advantage\nThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.\nCadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.\nThe unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success.\nMultiple avenues of learning and development available for employees to explore as per their specific requirement and interests.\nYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.\n\nJob responsibilities:\n\nJob Description: Layout Design\nWork Location : Bangalore\nWork Experience : 8 - 11 Years or equivalent relevant experience.\n\nResponsibilities:\n\nCustom layout design for NextGen, high-speed IPs like SerDes/DDR/GDDR/LPDDR/ Pcie/D2D/HBM/Ucie/Chiplets and much more which are yet on the horizon…\nUnderstanding requirements from different teams and stake-holders be it circuit-design, digital, packaging or foundry and work with a co-creation mindset to successfully deliver Analog Macros *(depending upon level of exp).\nPerform physical verificationsFull Spectrum Verifications as per foundry.\nFlavors of DRC\nVarious Electrical check / LVS / Ageing and Reliability Compliance. \n\nBased on expertise level, would be required to not just contribute as an individual contributor, but wear a hat of a leader to lead a team of engineers towards a successful IP delivery. \nTo be agile enough and adapt-with-ease with changing market, client, technology and foundry needs. \n\nRequirements\n\n•                 It’s expected to have ownership and hands on to high-speed products, classical analog products.\n•                 Hands on layout experience in various analog IP like High-speed Analog (Serdes), Data converters, power management and PLL etc.\n•                 Having worked on latest technology nodes like 18a, 2nm, 3nm, 5nm, 7nm and below, is desired.\n•                 Knowledge of various analog layout techniques, floorplan constraints and IP integration at chip level scenario.\n•                 Hands on layout experience in various analog modules like Opamps, Bandgaps, Dataconverters, LDO and PLL etc.\n•                 Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,\n•                 Knowledge of various analog layout techniques like matching, shielding etc.,\n•                 Must have good communication skills and should be team player.\n•                 Scripting and automation experience is a plus.\n•                 Good communication skills, documentation, and presentation skills.\n•                 Strong analytical and problem-solving skills.\n\n********************************************************************************************************************************************\n\nQualifications\n\nBE/BTech/ME/MS/MTech in Electrical/Electronic or equivalent\n\nBehavioral skills required.\nMust possess strong written, verbal and presentation skills.\nAbility to establish a close working relationship with both customer peers and management.\nExplore what’s possible to get the job done, including creative use of unconventional solutions.\nWork effectively across functions and geographies\nPush to raise the bar while always operating with integrity.\n\nRegards\nMadhu\nkmadhup@cadence.com\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "High Speed IO Validation Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-07-29", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/High-Speed-IO-Validation-Engineer_JR2020227", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. Today, we are tapping into the unlimited potential of AI to define the next era of computing — an era in which our GPUs act as the brains of computers, robots, and self-driving cars that understand the world. Doing what has never been done before takes vision, innovation, and the world’s best talent.\n\nNVIDIA’s Silicon Co-Design Group is the team that gets every GPU, SoC, and CPU silicon program from first power-on to high-volume production. We are hiring an HSIO Validation Engineer to own characterization and qualification of high-speed I/Os — PCIe, NVLink, NVLink-C2C, UCIe, USB, UFS, and Ethernet — on brand-new silicon serving datacenter, AI, and client markets. Your bench is where silicon meets the signal — where every link train, jitter sweep, eye diagram, and protocol corner gets exercised before the part ships. You drive characterization and debug for IO interconnects across silicon, board, firmware, and driver — designing tests that anticipate rack-scale deployment so marginality surfaces at die-and-board scale, never in a rack. Your decisions show up in link margin, BER, power per lane, and the go/no-go calls that gate samples and production.\n\nWhat you will be doing:\nOwn end-to-end characterization and validation of high-speed IO — PCIe, NVLink, NVLink-C2C, UCIe, USB, UFS, Ethernet — from silicon die through package and board, on NVIDIA GPUs, CPUs, and SoCs.\n\nDevelop and execute validation test plans for silicon and SoC-level HSIO features — bring-up, corner qualification, stress, productization, and structured DOE across PVT, board, cable/connector, thermal, and firmware variables — left-shifting silicon failures before deployment.\n\nDrive power characterization and optimization across IO interconnects under workload-representative stimuli (MLPerf-class patterns at silicon/board level) — analyze trade-offs across V/F, lane config, and protocol state — and feed back into design, firmware, and binning.\n\nDrive systematic root-cause analysis for complex HSIO bugs — isolating contributions across silicon, package, board, firmware, and driver, with platform/thermal/mechanical partners when system context matters. Convert rack-observed failures into silicon/board reproducers so future spins fix the root cause upstream.\n\nAssess manufacturing and yield implications of HSIO margin distributions — identify gaps in scaling from chip to product, and feed back into binning and design.\n\nDevelop and improve validation methodologies, automation frameworks, and margin-tracking infrastructure — increase efficiency and coverage as platform complexity grows.\n\nWhat we need to see:\nBS or MS in Electrical or Computer Engineering (or equivalent), with 8+ years in post-silicon HSIO validation, characterization, or a closely related discipline.\n\nDeep understanding of high-speed serial link protocols (PCIe Gen5+, NVLink, NVLink-C2C, UCIe, CXL) and the underlying SERDES architecture — equalization, link training, electrical characterization — with strong signal integrity and jitter knowledge.\n\nStrong SI and PI fundamentals — S-parameters, eye diagrams, channel margin, crosstalk, return loss, PDN noise, jitter decomposition — and validation experience across silicon and platform boundaries (CoWoS/interposer/substrate, board), translating rack-environment effects into silicon/board characterization.\n\nHands-on with lab instrumentation (DSOs, BERTs, VNAs, protocol/logic analyzers, TDR), DOE/shmoo/margin-trending, and Python-based test automation — with a track record of driving cross-functional debug across chip, package, board, firmware, driver, and system teams.\n\nWays to stand out from the crowd:\nHands-on experience with PCIe Gen5/Gen6 or NVLink validation on production silicon — link training, equalization tuning, BER margining, or compliance debug.\n\nPrior SERDES, mixed-signal, or analog circuit design experience — sufficient to independently form hypotheses, design Sim-to-Si correlation experiments, and propose silicon/system-side fixes during debug.\n\nTrack record of translating rack-environment conditions (thermal, connector reliability, neighbor noise) into silicon/board characterization — finding marginality at die-and-board scale before it appears in the field.\n\nComfortable using AI productivity tools (Claude, Copilot, or equivalent) to compress log triage, regression analysis, scripting, and reporting workflows.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Staff Engineer, Design Verification Engineering", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-07-29", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Staff-Engineer--Design-Verification-Engineering_R254028", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nStaff Design Verification Engineer\n\nAbout the Role\nAs a Staff Design Verification Engineer at Analog Devices, you will provide technical leadership in developing verification strategies for our most complex analog and mixed-signal designs. You'll architect sophisticated verification environments, mentor junior engineers, and collaborate across organizational boundaries to ensure product quality and reliability.\nWorking with limited direction, you'll apply your deep technical expertise to solve critical verification challenges while representing ADI in interactions with key customers and industry partners. This senior position involves significant influence on verification methodology adoption and technical decisions that impact crucial organizational objectives.\n\nKey Responsibilities\nStrategic Leadership: Architect and lead verification strategy for complex digital and mixed-signal designs, acting as a key contributor in critical verification environments\nVerification Architecture: Design and implement sophisticated UVM-based verification environments that ensure comprehensive test coverage and design quality\nTechnical Mentorship: Guide and develop junior engineers, serving as a resource for colleagues with less experience while modeling professional behaviors\nCross-Functional Direction: Coordinate work across organizational lines, collaborating with design teams on verification requirements and sign-off criteria\nProblem Resolution: Lead complex debugging efforts across RTL and gate-level simulations with minimal direction, developing resolutions that require in-depth analysis\nCoverage Closure: Drive functional and code coverage closure using advanced verification methodologies to ensure design accuracy\nPost-Silicon Support: Lead post-silicon validation activities, contributing expertise to address critical issues\nCustomer Representation: Serve as principal customer contact on projects, representing ADI's technical excellence and customer commitment\n\nMust Have Skills\nSystemVerilog and UVM Expertise: Expert-level knowledge of SystemVerilog and Universal Verification Methodology for architecting advanced verification environments for complex designs\nTest Planning and Strategy: Demonstrated ability to develop comprehensive verification plans that drive coverage-driven methodologies and verification closure\nMixed-Signal Verification: Deep understanding of mixed-signal design principles and verification methodologies, with experience implementing sophisticated verification approaches\nDebugging Mastery: Advanced debugging skills across multiple design abstractions, with proven ability to resolve complex verification issues with minimal direction\nEDA Tool Proficiency: Extensive experience with electronic design automation tools (Cadence/Synopsys) and formal verification techniques\nScripting and Automation: Advanced proficiency in Python, Perl, TCL, or Shell scripting for creating sophisticated verification automation frameworks\nTechnical Leadership: Demonstrated ability to influence verification direction, mentor junior engineers, and drive methodology adoption across teams\n\nPreferred Education and Experience\nMS/PhD in Electrical Engineering, Computer Engineering, or related field\n7-10+ years of relevant digital design verification experience, with particular emphasis on mixed-signal verification\n\nWhy You'll Love Working Here\nAt Analog Devices, you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on professional growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world.\nYour expertise will shape the future of technology, and you'll be supported by a culture that values continuous advancement and professional growth. Join us and help create the technologies that bridge the physical and digital worlds, making a tangible difference in how people live, work, and connect.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Physical Design, Principal Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-07-29", "url": "https://careers.synopsys.com/job/bengaluru/physical-design-principal-engineer/44408/91539646624", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Title:Principal ASIC Physical Design Engineer\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou are the person teams turn to when timing closure looks impossible and the clock tree feels like a puzzle with missing pieces. You know the difference between a design that passes signoff and one that ships with margin to spare, because you have spent years making those calls at 7nm and below. You do not just push buttons in ICC2 or PrimeTime—you know why a constraint matters, and you catch issues before they ripple downstream. When someone asks about integrating a tricky mixed-signal macro, you have a mental toolkit of what can go wrong and how to make it work. You thrive on the hard problems: GHz-level timing, power optimization, and the reality of silicon bring-up. You want your work to show up in real products, not just in a tapeout report. Sharing what you know is second nature—mentoring junior engineers, reviewing a teammate’s floorplan, or explaining a tradeoff to a colleague in the US. You care about getting the details right, but you do not get stuck in them. You move projects forward, ask the right questions, and always look for a better way to do things.\nWhat You'll Be Doing\nImplement and integrate Physical Design for ASICs at advanced nodes (10nm, 7nm, 6nm and below) using tools like Synopsys ICC2, PrimeTime, and StarRC.\nDrive timing closure for high-frequency designs above 4GHz, handling constraint management, analysis, and optimization.\nWork hands-on with clock tree synthesis, skew balancing, and robust clock distribution for complex SoCs and IPs.\nCollaborate closely with teams in Bangalore and the US, joining technical discussions, design reviews, and troubleshooting sessions.\nIntegrate mixed-signal hard macro IPs, solving unique interface and floorplan challenges as they arise.\nMentor junior engineers, sharing best practices and elevating the team’s technical capability.\nDevelop and optimize automation scripts in Tcl, Perl, or Python to streamline physical design flows and improve productivity.\nSupport and improve methodologies for floorplanning, placement, routing, and power optimization.\nThe Impact You Will Have\nDeliver HPC Controller IPs that will power the next wave of consumer and enterprise devices.\nPush Synopsys’ reputation for silicon-proven, high-performance IP at the most advanced process nodes.\nRaise the bar for quality and innovation in timing closure, clock tree synthesis, and mixed-signal integration.\nHelp global teams align and execute, ensuring projects hit milestones and customers get what they need, on time.\nEnable faster, more robust tapeouts by improving design flows and mentoring the next generation of engineers.\nInfluence product differentiation through hands-on technical contributions and creative problem solving.\nShorten time-to-market for customers by anticipating and solving critical design challenges early.\nWhat You'll Need\nBachelor’s or Master’s degree in Electronics, Electrical Engineering, or related field.\n10+ years of hands-on experience in ASIC physical design at 10nm, 7nm, 6nm or below.\nDeep proficiency with Synopsys ICC2, PrimeTime, StarRC, and similar industry tools.\nDemonstrated success in timing closure for high-frequency designs (4GHz and above), including constraint management and analysis.\nPractical experience integrating HPC Controller interface IPs and mixed-signal macros.\nSolid knowledge of scripting (Tcl, Perl, Python) for automating physical design tasks.\nStrong skills in debugging complex design and integration issues.\nWho You Are\nYou explain why a timing violation matters, not just how to fix it, and adapt your message for a peer or a VP.\nWhen a design review gets stuck, you break down the complexity and help the team move forward.\nYou spot risk early and act, rather than waiting for issues to escalate.\nSharing knowledge is second nature—you mentor, document, and help others level up.\nYou keep an eye on quality, even under pressure, and push for continuous improvement in tools and process.\nYou are comfortable switching context between deep technical work and cross-site collaboration, always keeping the larger goal in view.\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Principal, IC Package Engineer", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-07-29", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Principal--IC-Package-Engineer_R2891-26-1", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nThe Mixed Signal Development Group is responsible for delivering high-speed analog and mixed-signal IP to divisions within Microchip. We work with leading edge CMOS processes to produce analog integrated circuits for wireline applications.  From PCIe to 128+Gb/s SERDES, we enable technology that allows Microchip’s products to interface to the outside world.\n\nAs a member of the Mixed-Signal Development Group, the candidate will be supervised by a team manager, and be engaged in the package design and layout.\n\nResponsibilities:\nConduct package routing feasibility and substrate layouts for Microchip high-speed products, including MCM packages\nPerform simple PCB breakout studies for ball map feasibility\nIdentify key issues for proposed designs based on silicon floor plans and desired package sizes\nWork with signal integrity engineers to implement high speed signal routes and quiet power routes\nWork with reliability engineers and external vendors to ensure manufacturability of package designs\nCreate package routing constraints based on signal integrity routing rules\nInteract with and oversee work of external and internal package designers\nProduce package routing reports and diagrams for review by external teams\nCreate and track package design schedules\nGuide and assist external design teams on creation of input data for package design flow.\n\nRequirements/Qualifications:\n\nApplicable Bachelor’s or Master’s Degree\n10+ years of industry experience\nExpert in package design using Cadence APD\nExpert in authoring APD design rules\nScripting in PERL or SKILL is an asset\nFamiliarity with flip chip and wire bond package designs\nFamiliarity with PCB design and BGA fanout issues\nUnderstanding of high speed and power routing rules/issues\nCapable of handling multiple tasks at once\nCustomer oriented, with attention to detail\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Digital Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-07-29", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25000479", "is_hardware": true, "platform": "oracle", "jd_text": "About ASM Auto:\n\nWe are seeking talented and motivated individuals to join our team in developing cutting-edge solutions with Application-Specific Microcontrollers (MCUs) for the rapidly evolving automotive industry. Our MCUs power a wide range of critical vehicle functions, including traction control, onboard charging (OBC) and DC-DC converters, advanced lighting systems, body control modules, engine management, and braking systems. Additionally, we are at the forefront of innovation with zonal microcontrollers designed to enable software-defined vehicles, paving the way for greater functionality, scalability, and efficiency. Our products shape the future of automotive technology and create impactful solutions for modern mobility challenges.\n\nhttps://www.ti.com/applications/automotive/overview.html\n\nRole: Senior Design Engineer (RTL)\n\nWe are looking for an experienced Senior RTL Design Engineer to join our team in developing cutting-edge automotive microcontroller solutions. The ideal candidate will have deep understanding of RTL design and SoC integration, particularly in the context of ARM-based architectures, and a proven ability to collaborate across multiple engineering disciplines to deliver high-quality solutions for complex systems.\n\n \n\nKey Responsibilities:\n\n•Define and develop microarchitecture for various subsystems, including CPU subsystems, low-power subsystems, and Reset & Clock Management modules.\n\n•Own SoC integration for automotive MCUs, ensuring efficient, scalable designs.\n\n•Collaborate with IP teams, Systems, and Architecture teams to derive requirements, co-develop microarchitecture, and align on design goals for IPs, subsystems, and SoC.\n\n•Work closely with cross-functional teams such as Design Verification (DV), Design for Testability (DFT), Emulation, and Physical Implementation to ensure quality deliverables.\n\n•Participate in debug sessions, design reviews, and ensure design robustness and compliance with industry standards.", "jd_status": "source_unavailable"}, {"title": "Staff Applications Engineer – Power Management", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-07-28T11:35:57.881000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000140214569-staff-applications-engineer-power-management", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Role Purpose\nThe Staff Applications Engineer will support Renesas input protection products for enterprise, data center, AI server, telecom, and industrial power systems. This is a hands-on hardware role focused on customer support, board debug, validation, reference designs, and practical design guidance and requires strong power electronics experience. The engineer will work with systems, design, validation, product marketing, field teams, and customers to solve real application issues and help customers adopt Renesas power products successfully.\nPrincipal Accountabilities\nProvide applications support for input protection devices used in 48 V and emerging 800 V / ±400 V power systems.\nSupport customers and field teams through schematic reviews, PCB layout reviews, component selection, bench debug, issue reproduction, root cause analysis, and clear design recommendations.\nDevelop and validate evaluation boards, demo boards, proof of concept hardware, and reference designs for high current and high voltage applications.\nDebug hardware, register configuration, PMBus/I²C communication, gate drive behavior, isolation interfaces, system transients, and customer board failures.\nUse lab equipment such as oscilloscopes, high voltage supplies, electronic loads, power analyzers, thermal tools, differential probes, and automated test setups.\nCreate scripts, calculators, GUI utilities, and data analysis tools to support validation, characterization, and customer debug.\nSupport new silicon bring up, identify application gaps early, and work with design and systems teams to improve product robustness.\nReview and write customer documentation such as datasheets, application notes, user guides, design guides, test reports, troubleshooting notes, and training material.\nWork closely with marketing, systems, design, validation, quality, sales, and field teams to support product launch, customer design in, and issue closure.\nMinimum Qualifications\nMaster’s degree in Electrical Engineering, Electronics Engineering, Power Electronics, or a related field; bachelor’s degree with strong relevant experience may also be considered.\n3+ years of experience in applications engineering, field applications, validation, product engineering, or hardware development for analog or power semiconductor products.\nStrong hands-on board and system debug experience, including issue reproduction, waveform analysis, fault isolation, root cause troubleshooting, and corrective action recommendations.\nGood understanding of power electronics, input protection, MOSFETs  gate drive, current sensing, thermal behavior, and protection concepts.\nExperience with schematic capture, PCB layout review, board bring up, high current routing, grounding, noise coupling, isolation, and measurement best practices.\nFamiliarity with simulation tools such as PSpice, SIMPLIS, MATLAB/Simulink, or similar tools for power, transient, thermal, or signal/power integrity analysis.\nComfortable using common lab equipment, including oscilloscopes, power supplies, electronic loads, power analyzers, thermal cameras, probes, and solder/rework tools.\nAble to write clear customer facing documents and work directly with customers and cross-functional engineering teams.\n\nPreferred Qualifications / Desired Experience\nExperience with high voltage products, 800 V or ±400 V HVDC systems, solid state relays, eFuses, live insertion, or high power data center systems.\nKnowledge of PMBus/I²C telemetry, register configuration, fault logging, GUI tools, and lab automation using Python, C/C++, MATLAB, LabVIEW, or similar tools.\nExperience validating startup into large capacitance, short circuit behavior, load transients, retry/latch off behavior, and safe operating area limits.\nFamiliarity with isolation concepts, isolated interfaces, bias supplies, HV lab safety, EMI, and ESD considerations.\nExperience creating EVMs, reference designs, demo platforms, user guides, application notes, design calculators, and training material.\nCustomer facing experience with enterprise or data center customers, server OEMs/ODMs, hyperscalers, telecom customers, or field applications teams.\nAble to manage ambiguity, prioritize customer issues, and drive practical solutions with limited day to day direction.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Staff Systems Engineer – Power Management", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-07-28T11:22:01.801000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000140212019-senior-staff-systems-engineer-power-management", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Role Purpose\nThis Hardware Sr. Staff Systems Engineer will define and validate solutions for protection devices used in enterprise, data center, AI server, telecom, and industrial power systems. This is a hardware systems role that connects customer needs, market trends, competitive analysis, and IC development. The engineer will turn customer and application needs into clear product specifications, validation plans, reference designs, and technical material that help the product succeed from definition to customer ramp. The role requires strong power electronics knowledge, good customer engagement skills, and the ability to work across teams from concept to production release.\nKey Responsibilities\nOwn product definition at the system level for next generation input protection devices targeting 48 V and emerging high voltage power distribution in enterprise and data center platforms.\nWork directly with customers, field teams, product marketing, applications, design, validation, test, product engineering, and program management to capture needs, align on tradeoffs, and define differentiated product specifications.\nAnalyze target applications, end-equipment trends, customer RFQs, system pain points, and competitive solutions to identify product gaps and roadmap opportunities.\nDevelop product requirement documents, system architecture proposals, specification tables, datasheet content, validation plans, verification matrices, and risk/tradeoff summaries for new product initiatives.\nDrive the system validation strategy, including corner case testing, fault response validation, thermal characterization, transient load behavior, power integrity, telemetry accuracy, and customer use case coverage.\nDesign, review, and debug evaluation boards, proof of concept platforms, and reference designs that show product capability in realistic server, accelerator, switch/router, storage, and telecom power systems.\nPerform lab bring up, bench characterization, silicon evaluation, schematic and layout review, failure analysis, and system troubleshooting to support product development and early customer adoption.\nDevelop calculators, simulation models, design tools, application notes, user guides, training material, and reference design collateral for customers, field teams, and internal stakeholders.\nLead technical discussions during customer engagements, design reviews, RFQ responses, roadmap reviews, and product launch activities; provide clear recommendations on architecture, features, and product positioning.\nPartner with applications engineering to support early design ins, resolve customer application issues, and help accelerate product ramp in strategic enterprise and data center accounts.\nSupport NPI execution by communicating market and customer requirements, tracking technical closure, and ensuring product readiness from concept through release to market.\nMinimum Qualifications\nMaster’s degree in Electrical Engineering, Electronics Engineering, Power Electronics, or a related discipline; bachelor’s degree with equivalent depth of relevant experience may be considered.\n6+ years of experience in systems engineering, applications engineering, product definition, validation, or IC development for power management or analog semiconductor products.\nStrong foundation in power electronics, protection devices, high current board design, analog control loops, MOSFET/SOA behavior, and thermal design.\nHands-on experience with lab debug and validation using oscilloscopes, power supplies, electronic loads, thermal measurement equipment, data acquisition tools, and solder/rework equipment.\nExperience reviewing schematics and layouts and working with PCB design constraints for high current, high power density power systems.\nFamiliarity with simulation and analysis tools such as SPICE/PSpice, SIMPLIS, MATLAB/Simulink, or equivalent tools for system modeling, power integrity, and control loop analysis.\nAbility to create high quality technical documentation, including specifications, validation plans, datasheet content, application notes, evaluation board user guides, and customer facing technical material.\nStrong written and verbal communication skills, with the ability to explain complex technical tradeoffs to customers and cross-functional stakeholders.\n \n\nPreferred Qualifications / Desired Experience\nPractical knowledge of PMBus/I²C based control and telemetry, digital configuration, fault reporting, NVM based settings, and register map definition for power management devices.\nExposure to safety, reliability, and layout considerations relevant to high-voltage or high-current power systems, including creepage/clearance, surge/transient behavior, EMI/EMC, ESD, and thermal derating.\nProgramming or scripting experience for test automation, data analysis, model generation, or customer design tools using Python, MATLAB, LabVIEW, or similar environments.\nDemonstrated ability to influence product roadmaps, bring ambiguity to closure, align on specification tradeoffs, and build technical agreement across customers and internal product development teams.\nCustomer-facing experience with hyperscalers, server OEMs/ODMs, telecom customers, or field applications teams is highly desirable.\nProven track record of taking semiconductor products from concept/product definition through validation, launch, and customer ramp.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Sr.DFT Verification Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-07-28T11:18:00+00:00", "url": "https://global-external-amd.icims.com/jobs/88461/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. MTS SILICON DESIGN ENGINEER    THE ROLE: The focus of this role is to plan, build, and execute the DFT verification of new and existing features for AMD’s Chiplets , resulting in no bugs in the final design.     THE PERSON:  As a DFx Verification Engineer, you will be primarily responsible for verification of architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products and will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference.   KEY RESPONSIBILITIES:  Collaborate with architects, design engineers, and firmware engineers to understand the new DFT features to be verified Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random DFT verification tests Debug test failures to determine the root cause; work with RTL/DFT and firmware engineers to resolve design defects and correct any test issues  Analyze and enhance legacy DFT test plans to accommodate new Design for Debug feature developments Write complex Perl scripts to update simulation files in a deterministic manner Recreate post-silicon failures in pre-silicon environment Conduct silicon debug and root cause analysis with minimal logging support Utilize JTAG protocols for debugging and validation   PREFERRED EXPERIENCE:  8+ years of experience in DFT Design Verification with strong debug capabilities Experienced with SystemVerilog/UVM testbench development for complex SoCs Including GLS & SDF verifications Advanced scripting skills (Python, Perl, etc.) for automation and testbench infrastructure Deep knowledge of digital design, RTL design, and verification flows Strong troubleshooting and analytical debugging skills with ability to debug without logs Ability to quickly adapt to complex infrastructure environments Excellent hands-on debug skills and attention to detail Proficient in debugging firmware and RTL code using simulation tools  Exposure to leadership or mentorship is an asset ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-PM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "MTS - Analog Design", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-28T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/43364000", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nResponsibilities will include, but are not limited to:\nDesign, implementation and integration of complex analog circuits such as CMOS Amplifiers, Comparators, Bandgap References, LDOs, Charge Pumps, Oscillators, DLL, IO Buffers, Analog Test Mux, Process Monitor, and Temperature sensors for advanced DRAM products.\nDesign, implementation and integration of synchronous and asynchronous custom digital block\nContributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Analog/Memory/Logic circuits.\nParasitic modeling and design validation, reticle experiments and required tape-out revisions.\nOverseeing and managing the layout process including floor-planning, placement, and routing\nPerforming verification processes with modeling and simulation using industry standard simulators\nContributing to cross group communication to work towards standardization and group success.\nWorking with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product.\nProactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality.\nMentor and lead young designers.\nAlso, strong AI proficiency, a solid understanding of agentic AI models, and effective use of tools such as Claude are expected to significantly improve engineering efficiency, enhance PPA (Power, Performance, Area) optimization, and accelerate overall delivery timelines.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Principal Engineer - Analog Design", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-28T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/43489613", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nWhat’s Encouraged Daily:\nContribute to the development of new HBM products by assisting with the overall design, and layout.\n·       Interpret product specifications and design circuits to meet the required functionality.\n·       Design, implementation, and improvement of Complex Analog Mixed Circuits such as CMOS Amplifiers, Comparators, Bandgap references, V2I converters, LDOs, charge pumps, Oscillators, DLL, IO circuits (DDR/LPDDR), Delays, Process and temperature sensors in advanced semiconductor process nodes for advanced High Bandwidth Memory (HBM) products\n·       Integration of modules with Power delivery network and propose design solution for optimum performance\n·       Deep understanding of Array and its peripheral circuits.\n·       Driving innovation into the future Memory generations within a dynamic work environment\n·       Validate & optimize design for reliability (Device stress, Aging effect)\n·       EM/IR simulation, optimize layout to achieve best circuit performance\n·       Custom digital circuit design & validation\n·       Parasitic modeling and assisting in design validation, reticle experiments and required tape-out revisions\n·       Overseeing and managing the layout process including floor-planning, placement, and routing\n·       Performing verification processes with modeling and simulation using industry standard simulators\n·       Contributing to cross group communication to work towards standardization and group success\n·       Working with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product\n·       Proactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality\n·       Participate in new circuit conception and design as needed\n·       Perform circuit simulations using standard industry simulators such as FINESIM, HSPICE, and VERILOG\n·       Responsible for reliability and degradation verification.\n·       Assist in design validation, reticle experiments, and required tape-out revisions\n·       Contributes expert technical knowledge to advance innovative technical solutions\n·       Provides advice and counsel to senior management on significant technical issues\n \nOversee the layout process\n·       Help floor-planning process, including placement and routing optimization\n·       Optimize design rules for cost, performance, and functionality\n·       Import layout parasitic information into the circuit simulation environment\n \nMaintain Technical Expertise and Provide Training\n·       Contribute to cross-group communication to work towards standardization and group success\n·       Aid in design documentation and communicating best-known practices to the entire department\n·       Participate in continuing education and competitor analysis\n·       Proactively solicit feedback from Standards, CAD, modeling, and verification groups to ensure the design quality\n·       Drive innovation into the future Memory generations within a dynamic work environment\n\nAI Usage\nStrong AI proficiency, a solid understanding of agentic AI models, and effective use of tools such as Claude are expected to significantly improve engineering efficiency, enhance PPA (Power, Performance, Area) optimization, and accelerate overall delivery timelines.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Staff Engineer - HBM Analog Design", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-28T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/43489824", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nResponsibilities will include, but are not limited to:\nDesign, implementation and integration of complex analog circuits such as CMOS Amplifiers, Comparators, Bandgap References, LDOs, Charge Pumps, Oscillators, DLL, IO Buffers, Analog Test Mux, Process Monitor, and Temperature sensors for advanced DRAM products.\nDesign, implementation and integration of synchronous and asynchronous custom digital block\nContributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Analog/Memory/Logic circuits.\nParasitic modeling and design validation, reticle experiments and required tape-out revisions.\nOverseeing and managing the layout process including floor-planning, placement, and routing\nPerforming verification processes with modeling and simulation using industry standard simulators\nContributing to cross group communication to work towards standardization and group success.\nWorking with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product.\nProactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality.\nMentor and lead young designers.\nUsage & working with AI Skills is must\nStrong AI proficiency, a solid understanding of agentic AI models, and effective use of tools such as Claude are expected to significantly improve engineering efficiency, enhance PPA (Power, Performance, Area) optimization, and accelerate overall delivery timelines.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Staff Engineer - HBM Analog Design", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-28T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/43489618", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nWhat’s Encouraged Daily:\nContribute to the development of new HBM products by assisting with the overall design, and layout.\n·       Interpret product specifications and design circuits to meet the required functionality.\n·       Design, implementation, and improvement of Complex Analog Mixed Circuits such as CMOS Amplifiers, Comparators, Bandgap references, V2I converters, LDOs, charge pumps, Oscillators, DLL, IO circuits (DDR/LPDDR), Delays, Process and temperature sensors in advanced semiconductor process nodes for advanced High Bandwidth Memory (HBM) products\n·       Integration of modules with Power delivery network and propose design solution for optimum performance\n·       Deep understanding of Array and its peripheral circuits.\n·       Driving innovation into the future Memory generations within a dynamic work environment\n·       Validate & optimize design for reliability (Device stress, Aging effect)\n·       EM/IR simulation, optimize layout to achieve best circuit performance\n·       Custom digital circuit design & validation\n·       Parasitic modeling and assisting in design validation, reticle experiments and required tape-out revisions\n·       Overseeing and managing the layout process including floor-planning, placement, and routing\n·       Performing verification processes with modeling and simulation using industry standard simulators\n·       Contributing to cross group communication to work towards standardization and group success\n·       Working with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product\n·       Proactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality\n·       Participate in new circuit conception and design as needed\n·       Perform circuit simulations using standard industry simulators such as FINESIM, HSPICE, and VERILOG\n·       Responsible for reliability and degradation verification.\n·       Assist in design validation, reticle experiments, and required tape-out revisions\n·       Contributes expert technical knowledge to advance innovative technical solutions\n·       Provides advice and counsel to senior management on significant technical issues\n\nAI Usage\nAlso, strong AI proficiency, a solid understanding of agentic AI models, and effective use of tools such as Claude are expected to significantly improve engineering efficiency, enhance PPA (Power, Performance, Area) optimization, and accelerate overall delivery timelines.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Staff Engineer - HBM Analog Design", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-28T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/43470894", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nResponsibilities will include, but are not limited to:\nDesign, implementation and integration of complex analog circuits such as CMOS Amplifiers, Comparators, Bandgap References, LDOs, Charge Pumps, Oscillators, DLL, IO Buffers, Analog Test Mux, Process Monitor, and Temperature sensors for advanced DRAM products.\nDesign, implementation and integration of synchronous and asynchronous custom digital block\nContributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Analog/Memory/Logic circuits.\nParasitic modeling and design validation, reticle experiments and required tape-out revisions.\nOverseeing and managing the layout process including floor-planning, placement, and routing\nPerforming verification processes with modeling and simulation using industry standard simulators\nContributing to cross group communication to work towards standardization and group success.\nWorking with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product.\nProactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality.\nMentor and lead young designers.\nUsage & working with AI Skills is must\nStrong AI proficiency, a solid understanding of agentic AI models, and effective use of tools such as Claude are expected to significantly improve engineering efficiency, enhance PPA (Power, Performance, Area) optimization, and accelerate overall delivery timelines.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Staff Engineer - HBM Analog Design", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-28T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/43489702", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nResponsibilities will include, but are not limited to:\nDesign, implementation and integration of complex analog circuits such as CMOS Amplifiers, Comparators, Bandgap References, LDOs, Charge Pumps, Oscillators, DLL, IO Buffers, Analog Test Mux, Process Monitor, and Temperature sensors for advanced DRAM products.\nDesign, implementation and integration of synchronous and asynchronous custom digital block\nContributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Analog/Memory/Logic circuits.\nParasitic modeling and design validation, reticle experiments and required tape-out revisions.\nOverseeing and managing the layout process including floor-planning, placement, and routing\nPerforming verification processes with modeling and simulation using industry standard simulators\nContributing to cross group communication to work towards standardization and group success.\nWorking with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product.\nProactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality.\nMentor and lead young designers.\nUsage & working with AI Skills is must\nStrong AI proficiency, a solid understanding of agentic AI models, and effective use of tools such as Claude are expected to significantly improve engineering efficiency, enhance PPA (Power, Performance, Area) optimization, and accelerate overall delivery timelines.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "RTL (NOC) Design - Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-28T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719912551", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nNoC design lead and is part of BDC infrastructure (NoC/Interconnect) core team\n\nResponsible for specification, design and implementation of interconnect and related IP’s\n\nActively work with SoC team, verification team, physical design team, SoC Floorplan, core teams and various other interconnect teams in various other sites\n\nPartner with SoC performance team ensuring Interconnect meeting all performance requirement, and with silicon validation team to co-relate pre-silicon and post silicon design assumptions\n\nResponsible for micro-architecting all relevant debug hooks in NoC Infrastructure to help root cause silicon issues\n\nLooks beyond existing methodologies and own discipline to define and resolve complex problems\n\nManages large, potentially diverse teams of managers and/or senior professionals\n\nProvides input to functional or departmental strategy\n\nCreate an impact on product competitiveness, roadmap and business objectives through Design/DV/Problem Solving\n\nLead by example on customer problem solving related to NoC/Interconnect\n\nMinimum Qualifications:\n8+ years of solid experience in IP/SoC design and micro-architecture\n\nUnderstanding of interconnect protocols like CHI/AHB/AXI/ACE/ACE-Lite/NoC concepts\n\nGood knowledge of Digital Design and RTL development\n\nHands-on experience with SoC Design, Verilog RTL coding\n\nUnderstanding of multi-core ARMv8/v9 CPU architecture, coherency protocols and virtualization.\n\nWorking knowledge of Synthesis, DC/DCG synthesis with Synopsys design complier, DFT, verification, formal verification, silicon debug\n\nWorking knowledge of Lint, CDC, PLDRC, CLP etc\n\nGood understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification\n\nManage SoC dependencies, planning and tracking of all front-end design related tasks\n\nDriving project milestones across the design, verification and physical implementations\n\nShould possess effective communication and leadership skills\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Sr. Principal Digital Designer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-07-28", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Sr-Principal-Digital-Designer_R-10062152", "is_hardware": true, "platform": "workday", "jd_text": "Role Summary\nWe are seeking a Sr. Principal Digital Designer to lead the architecture, implementation, and integration of digital subsystems for Automotive Ethernet PHY products (10BASE‑T1S, 100BASE‑T1, 1000BASE‑T1, and multi‑gig automotive SerDes technologies).\nThe role involves driving digital micro-architecture, state machines, PCS functionality, safety mechanisms, and end‑to‑end digital design across the PHY.\n\nKey Responsibilities\n1. Architecture & Technical Leadership\nDefine and own digital subsystem micro‑architecture for Automotive Ethernet PHYs, including: PCS pipelines and encoding/decoding logic\nScramblers/descramblers, CRC engines, alignment & framing\nPacket processing, link monitoring, error handling\nInterface logic (MII, RMII, RGMII, GMII, XGMII depending on product line)\nProcessor based SoC design\n\nPerform system‑level partitioning between digital, analog/mixed-signal, and firmware components.\nLead feasibility studies, power/performance trade-offs, and digital architecture exploration.\n2. RTL Design & Implementation\nDevelop high-quality RTL (Verilog/SystemVerilog) for control, datapath, and protocol logic.\nDrive digital front-end flows including: Lint, CDC/RDC, reset architecture, synthesis guidance\nTiming constraints and logic optimization\n\nWork with DV to define coverage goals, corner cases, and feature verification plans.\n3. System‑Level Ownership\nTranslate system requirements, IEEE 802.3 specifications, and architecture documents into robust digital designs.\nWork with mixed-signal teams to define: Control interfaces to analog front‑end blocks\nCalibration engines, register programming flows, and digital‑analog interaction models\n\nContribute to bring‑up sequences, compliance testing, and system validation.\n4. Automotive Quality & Functional Safety\nEnsure compliance with Automotive Ethernet standards, ISO 26262, and AEC‑Q100 expectations.\nDefine and implement: Safety mechanisms (BIST, LBIST/MBIST, error detection schemes)\nDiagnostic monitors, timeout recovery logic, watchdogs, and fault reporting\n\nParticipate in FMEDA, DFA, and functional safety analysis.\n5. Cross‑Functional Collaboration\nPartner with: Firmware/software teams for register maps, boot flows, diagnostics\nPD teams to ensure implementation‑friendly architecture\nValidation and compliance teams for pre‑ and post‑silicon debug\n\nMentor junior engineers and guide technical decision‑making across the digital team.\n\nRequired Qualifications\nMasters in Electrical Engineering, Computer Engineering, or related discipline.\n12+ years experience in digital design for PHY, SerDes, networking ASICs, or communication ICs.\nStrong expertise in: Verilog/SystemVerilog RTL design\nHigh‑speed digital logic, state machines, control logic\nIEEE 802.3 Ethernet PCS, link training, and system control flows\nSynthesis, STA, CDC/RDC methodology\n\nProven track record across multiple production tape-outs.\n\nPreferred Qualifications\nExperience with Automotive Ethernet standards: 10BASE‑T1S, 100BASE‑T1, 1000BASE‑T1, 10GBASE‑T1.\nFamiliarity with PHY firmware-driven initialization and configuration flows.\nStrong debugging skills with logic analyzers, protocol analyzers, and post-silicon validation.\nBackground in safety‑critical digital logic designs.\n\nSoft Skills\nStrong leadership, technical decision-making, and mentoring capabilities.\nAbility to communicate complex architectural topics to multidisciplinary teams.\nExcellent documentation and cross-functional collaboration skills.\n\nMore information about NXP in India...\n\n#LI-7013", "jd_status": "stored"}, {"title": "Senior Architect, GPU and SoC Modelling", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-07-28", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Architect--GPU-and-SoC-Modelling_JR2021971", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nThe NVIDIA Architecture Modelling group is looking for architects and software developers to join our various architecture efforts. A key part of NVIDIA's strength is to innovate in the graphics and parallel computing fields, delivering the highest performance in the world for high-performance computing. We are constantly looking for ways to improve our GPU architecture and maintain our leadership. In this position, you will be working with other world-class architects on modeling, analysis and validation of chip architectures and features that advance the state of art in performance and efficiency.\n\nWhat you'll be doing:\nModeling and analysis of graphics and / or SOC algorithms and features\n\nWork in a matrixed environment, across the different modelling teams, to document, design, develop tools to analyze and simulate, validate, and verify models\n\nFamiliarize with the different models (functional and performance) that are used at Nvidia and help with feature implementation as required.\n\nDevelop tests, test plans, and testing infrastructure for new architectures/features.\n\nCode coverage analysis and reporting\n\nMentor younger engineers and help sustain good coding practices.\n\nLearn about newer modelling techniques and frameworks, evaluate the best solution for our needs and work with your manager to drive the change\n\nHelp develop AI based tools to increase efficiency.\n\nWhat we need to see:\nBachelors Degree (or equivalent experience) in a relevant discipline (Computer Science, Electrical Engineering or Computer Engineering)\n\n8+ years of relevant work experience or MS with 5+ years of experience or PhD with 3+ years of experience\n\nStrong programming ability: C++, C along with a good understanding of build systems (CMAKE, make), toolchains (GCC, MSVC) and libraries (STL, BOOST)\n\nComputer Architecture background with experience in modeling with SystemC & TLM preferred\n\nFamiliarity with Docker, Jenkins, Python, Perl\n\nExcellent communication and interpersonal skills and ability to work in a distributed team environment.\n\nNVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. Do you love the challenge of crafting the highest-performance silicon GPUs and SoCs possible? If so, we want to hear from you! Come, join our Architecture Simulation and Modelling team and help build the real-time, cost-effective computing platform driving our success in this exciting and quickly growing field.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Program Management Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-07-28", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25016605", "is_hardware": true, "platform": "oracle", "jd_text": "Custom Team at Texas Instruments is looking for an experienced, highly driven Program Manager to lead complex, cross-functional custom development programs that bring innovative semiconductor products from concept to production. \n\nIn this role, you will work closely with systems, design, operations, marketing & sales, post-silicon validation, test, quality, and very demanding customer teams to ensure successful execution of schedules, deliverables, and business goals.\n\nKey Responsibilities\n\nProgram Ownership\n\nBeing in custom development for demanding customers, execution efficacy, timeline adherence, quality control and stakeholder management need to be ensured by the Program Manager.\n\nLead end-to-end program planning, execution, and delivery for analog/mixed-signal/embedded semiconductor products. \n\nDrive program scope, timelines, risk assessment, budgeting, and resource planning.\n\nCross-Functional Leadership\n\nCoordinate with design, DV, layout, post-Si validation, test engineering, quality, packaging, manufacturing, supply chain, marketing and operations teams across global sites.\n\nFacilitate program reviews, technical checkpoints, and decision gates.\n\nSchedule & Risk Management\n\nCreate and maintain detailed program schedules using appropriate tools.\n\nIdentify risks early, develop mitigation plans, and ensure teams stay aligned to program objectives.\n\nCustomer & Stakeholder Communication\n\nAct as the primary point of contact for internal and external stakeholders.\n\nPresent program status, key metrics, and critical issues to leadership and customers.\n\nQuality & Compliance\n\nEnsure programs meet TI’s quality, reliability, and regulatory standards along with customer mandated quality checks. Coordinate root cause analysis and corrective actions when needed.\n\nOperational & Business Support\n\nCollaborate with product line management on go-to-market strategies.\n\nMonitor cost, yield, and performance targets throughout the product lifecycle.\n\nQualifications\nPreferred Qualifications\n\n5–10+ years of program/project management experience in semiconductors, electronics, or high-tech manufacturing.\n\nExperience managing SoC/ASIC/analog/mixed-signal or embedded product development programs (depending on team).\n\nStrong understanding (experience preferred) of semiconductor development flows: architecture → design → validation → test → quality checks → release to production.\n\nProficiency with program management tools (Jira, MS Project, Confluence, etc.).\n\nExcellent leadership, communication, negotiation, and problem-solving skills.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Principal / Senior Manager, Digital Design Engineering", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-07-28", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/SoC-Chip-Lead_R262928", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nAbout the Role:\n\nAs an SoC Chip Lead, you will lead SoC execution from spec to silicon across domains. You will be responsible to drive technical strategy and execution for complex SoCs and digital systems, drive product and technology roadmaps, architecture for mission-critical projects and serve as a technical authority within the organization. This position requires exceptional expertise across multiple domains and the ability to influence business direction while delivering on the product actualization.\n\nKey Responsibilities:\n\nTechnical Strategy & Architecture\nDrive Product Strategy: Define long-term product and technology roadmaps for complex SoCs and systems.\nSelect IP & Nodes: Lead technical IP assessments, vendor selection, and foundry technology node evaluations.\nDefine Architecture: Author and drive top-level SoC definitions alongside business and architecture teams, including fabric interconnects (NoC), memory hierarchies, power management, and micro-architecture.\nSilicon Execution & Sign-off\nOwn the Lifecycle: Lead SoC execution from initial concept through definition, tape-out, and final productization.\nOptimize PPA: Ensure all silicon milestones meet strict Power, Performance, Area, and Cost (PPA) requirements.\nGovern Silicon Sign-off: Drive final sign-off reviews for synthesis, DFT, constraints, timing closure, and physical design tape-out.\nCross-Functional Leadership & Collaboration\nUnify Engineering Domains: Direct and collaborate closely with all core hardware engineering functions, including Design (RTL), Verification (DV), DFT, Physical Design (PD), Power, and Silicon Validation (SiVal).\nBridge Hardware and Software: Partner with software, systems, manufacturing, and program management to guarantee high-quality, first-time-right silicon success.\nManage Stakeholders: Lead executive decision-making, mitigate program risks, and manage communications across business units, product marketing, and customers.\n\nMust Have Skills:\n\nTechnical Strategy: Visionary capability to define and drive technical strategy for digital design\nInnovation Leadership: Exceptional ability to drive innovation in digital design approaches and solutions\nSoC Architecture: Authority in complex SoC architecture design and implementation\nMulti-Domain Expertise: Comprehensive mastery across multiple technical domains\nBusiness Acumen: Strong understanding of business context and ability to align technical strategy with business goals\nIndustry Thought Leadership: Recognized expertise with ability to influence industry direction\n\nPreferred Education and Experience:\n\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent experience\n12+ years of relevant experience in semiconductors design roles\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Software Applications Manager", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-07-28", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010047", "is_hardware": true, "platform": "oracle", "jd_text": "Applications engineers for Sitara MPU serve as technical experts on TI’s Sitara family of Processors and its use cases. This function is organized by end equipment and sector to drive a deeper understanding of key Automotive & Industrial markets and enable them to best support our sales team and customers in designing Sitara Processors into their products. Applications engineers will partner with Systems and Marketing teams to deliver system solutions, software, collateral, documentation and tools that accelerate customers' development time and drive design WINs. They also play an important role in ramping new target end-equipment (EE) by showcasing the features of Sitara Processor portfolio in a new context or application.\n\nQualifications\nJob Description: As a Software Applications Engineering Lead/Manager (Linux focused), you will be responsible for:\n\n• Supporting & developing Linux on TI’s latest Arm based SoCs – Understanding of Linux boot flow (SPL, u-boot), BSP, device drivers like (DMA, Flash, serial peripherals, ethernet etc.), good to have an understanding of middleware & frameworks (V4L2, GStreamer, Networking, Graphics etc.) & filesystem distributions (primarily Yocto).\n• Defining & developing demos to showcase silicon capability & differentiation that helps drive customer engagements.\n• Working with leading customers for TI Processors in Industrial (HMI, Industrial Automation, Grid Infrastructure, etc.) & Automotive ADAS (DOMS, CMS, Front/Rear/Surround View Camera & Radar, IVI, Cluster and Cockpit) market segments.\n• Supporting and engaging with customer on TI’s E2E (Engineer to Engineer) forum, online & face to face discussions.\n• Key point of contact for TI sales and customers, interacting with Systems, Architecture, Software Development, SoC Design and Verification teams to facilitate efficient and scalable system architectures for customer use-cases.\n• Creating collateral like Application Notes, White Papers, Academies and Webinars for enabling a broad customer base.\n \nBasic Qualifications\n\n• Bachelor’s/Master’s degree in ECE or Computer Science.\n• Minimum 7+ years industry experience in software development on embedded systems.\n• Deep expertise in developing and supporting Linux on Arm based SoCs with expertise in Industrial or Automotive EEs.\n• Exposure to leadership roles – Technical Lead or Manager.\n\nSkills Required\n\n• Strong technical, communication, leadership & management skills along with high level of accountability and curiosity.\n• Strong background in software, firmware development & experience in programming languages like C, C++ & Python.\n• Deep expertise in developing and supporting Linux on Arm based SoCs along with experience on heterogeneous SoCs systems – Arm Application & Real time cores, DSP, HW Accelerators etc.\n• Knowledge of Embedded Systems (MCU, MPU, ARM), Computer Architecture (Cache, DMA, Interconnect) and Operating Systems along with basic communication peripherals (I2C, SPI, UART), Serial Flash and optionally on Camera, Display and High Speed Interfaces like Ethernet, USB, PCIe.\n• Ability to clearly communicate (via presentations, email, virtual & in-person meetings, etc.) with customers to understand technical requirements and issues.\n• Strong problem-solving abilities by breaking down complex problems into individual components to debug and correct.\n• Strongly oriented toward process improvements and agile in achieving success within a constantly evolving environment.\n• Ability to leverage generative AI to optimize daily workflows.\n\nPrimary Responsibilities\n\n• Technical contribution driven by customer requirement: Develop expertise for key software architecture components to enable product success as measured by time to market.\n• Team Management (if hired as a manager): Managing a team of 2-5 people; responsible for mentoring, development, planning & execution along with efficient escalation management for key customer projects.\n• Customer’s technical point of contact: Expert on customer system; voice of customer to drive requirements, schedules, and market direction back into Product’s Software Development.\n• Ahead of customer requirements in key industrial & automotive segments for TI Sitara Processors: Create benchmarks, software demos, reference designs and self-serve collateral.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Sr Staff Engineer, Formal Verification", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-07-28", "url": "https://careers.synopsys.com/job/bengaluru/sr-staff-engineer-formal-verification/44408/98407187136", "is_hardware": true, "platform": "talentbrew", "jd_text": "Senior Staff Formal Verification EngineerWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent the better part of a decade proving that digital designs actually work, not just that they pass testbenches. Formal verification is where you live because you know that simulation can only show the presence of bugs, while formal methods can prove their absence. You have seen what happens when a corner case slips through, and you are the engineer who makes sure it does not.\nYou understand RTL at a level that lets you read a design and immediately spot the edge cases that will break it. Temporal logic is not abstract theory to you, it is the language you use to describe what correct behavior actually means. You have worked with tools like Jasper or VC-Formal enough to know their strengths, their quirks, and when to push back on a proof that looks complete but is not.\nMentoring comes naturally because you remember what it was like to debug your first failed assertion at 2am, and you would rather teach someone to set up a clean proof than fix their setup later. You can sit with a design team in Bangalore, walk through a formal verification plan, and leave them understanding not just what you are checking but why it matters.\nWhat You'll Be Doing\nBuild and maintain an end-to-end formal verification flow that integrates cleanly into the broader verification process, not a standalone tool that lives in a corner\nCreate formal verification plans that identify the key behaviors worth proving, then develop the assertions, assumptions, and cover properties that actually close on those behaviors\nGuide design and verification engineers on effective use of formal tools, reviewing setups and proofs to catch issues before they become blockers\nMaintain and extend assertion libraries that work for both simulation and formal contexts, ensuring consistency across verification approaches\nApply formal techniques like bounded model checking, induction, and abstraction to prove correctness of complex RTL designs\nDebug RTL when proofs fail, tracing back from a counterexample to the root cause in the design or the verification environment\nTrain team members and mentor junior engineers on formal methods, assertion-based verification, and debugging strategies\nThe Impact You Will Have\nCatch design bugs that simulation would miss, preventing costly respins and schedule slips downstream\nRaise the quality bar for digital designs across Synopsys products by making formal verification a standard part of the process, not an afterthought\nAccelerate verification closure by proving corner cases formally instead of writing thousands of directed tests hoping to hit them\nBuild verification infrastructure that other engineers can use effectively, multiplying your impact across the team\nImprove design quality at the source by working closely with RTL designers to identify and fix issues early\nContribute to the silicon and IP solutions that power everything from AI accelerators to automotive systems\nStrengthen the formal verification capability of the Bangalore team through knowledge sharing and hands-on mentorship\nWhat You'll Need\n8+ years of industry experience in digital design or verification, with at least 5 years focused on formal verification techniques\nDeep understanding of digital logic, RTL design patterns, and the synthesis and timing flows that turn RTL into gates\nHands-on experience with Verilog or SystemVerilog and the ability to read and debug complex RTL quickly\nSolid grasp of temporal logic and assertion-based verification, including SVA or PSL\nExperience with at least one formal verification tool such as Jasper or VC-Formal, including setup, proof strategies, and debug\nTrack record of using formal methods to close verification on complex projects, not just toy examples\nBachelor's or master's in computer science or electrical engineering; experience with Python, Perl, or Shell scripting is a plus\nWho You Are\nYou can look at a failed proof, trace the counterexample back through the design, and figure out whether the bug is in the RTL, the assumptions, or the assertion itself\nYou explain formal verification concepts to someone who has only done simulation-based verification in a way that makes them want to try it, not run away from it\nYou push back when a verification plan is too vague or when assumptions are hiding real design issues instead of simplifying the problem space\nYou stay organized across multiple verification tasks, keeping track of which proofs are complete, which are bounded, and which need more work\nYou collaborate effectively with geographically distributed teams, whether that means a design review over video or a detailed written explanation of a proof strategy\nYou mentor junior engineers by showing them how to think about formal verification, not just how to run a tool\nThe Team You'll Be Part Of\nYou will be part of the Solutions Group at the Bangalore Design Center, working with a team focused on delivering high-quality digital designs and verification solutions. The team values learning and growth, and you will have opportunities to work with talented engineers across different geographies and disciplines.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior/ Staff Signal and Power Integrity Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-07-27T11:42:16.577000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000139982192-senior-staff-signal-and-power-integrity-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Role Overview\nWe are seeking a highly skilled Signal and Power Integrity Engineer to support the design, analysis, and validation of high‑speed package and board designs. The ideal candidate will have strong fundamentals in electromagnetics and high‑speed signalling, hands‑on experience with industry‑standard simulation tools, and an ability to collaborate across silicon and systems teams to deliver robust, manufacturable products.\nKey Responsibilities\nPerform signal integrity (SI) and power integrity (PI) analysis for high‑speed package, PCB and system level designs.\nConduct 2D and 3D EM simulations to evaluate interconnect performance to mitigate crosstalk, impedance, and loss.\nAnalyse and optimize power distribution networks (PDN) including power plane design, decoupling strategies, and IR drop analysis.\nExecute frequency‑domain and time‑domain simulations for high‑speed interfaces.\nPerform channel simulations and system‑level analysis using tools such as ADS and HSpice.\nSupport design reviews, layout guidance, and ECO cycles with SI/PI recommendations.\nWork with validation teams to correlate simulation results with lab measurements and debug signal and power integrity issues.\nDevelop and maintain technical documentation, reports, and presentations.\nCollaborate closely with PCB layout, hardware, packaging, and validation teams.\nRequired Qualifications\nStrong fundamentals in electromagnetics, transmission lines, and microwave theory.\nHands‑on experience with EM simulation tools such as: ANSYS HFSS, SI-Wave, Cadence Power-SI.\nExperience with circuit analysis and simulation tools: ADS, HSpice. Proficiency in handling and analysing IBIS/Spice models.\nExperience in power plane modelling and analysis using tools such as Power-SI, Power DC or SI-wave.\nWorking knowledge of package and PCB technologies including stack‑up analysis, DFM, material behaviour etc.\nSolid understanding of high‑speed signalling in both time and frequency domains.\nNice to have: hands‑on experience with lab measurement equipment including VNA, oscilloscopes, TDR and spectrum analysers.\nExperience in test case development and automation using scripting languages (Python, MATLAB, or similar).\nStrong communication, presentation, and documentation skills with the ability to work effectively in a team environment.\n\nExperience Level\nBachelor’s degree in electrical / Electronic Engineering with 5+ years of relevant industry experience\n\nor\nMaster’s degree in electrical engineering with 3+ years of relevant experience.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Lead RTL design Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-07-27T08:19:00+00:00", "url": "https://global-external-amd.icims.com/jobs/88802/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. Lead RTL Design Engineer Role As part of the SoC Design team, the engineer has technical responsibility for SoC design and integration efforts involving both AMD and third-party IPs. The role works closely with IP development, verification, front-end integration, and physical design teams throughout the SoC development cycle. Key Responsibilities SoC-level design and integration. Integration of IPs, SoC fabric, voltage crossings, clock crossings, resets, fuses, and I/O. RTL design and coding for SoC logic and features. SoC power design and power implementation activities. Static verification including: RTL Lint CDC (Clock Domain Crossing) RDC (Reset Domain Crossing) Power checks Connectivity checks Debugging simulation and integration issues spanning multiple IPs in collaboration with verification teams. Supporting top-level synthesis and collaborating with physical design teams for full-chip implementation. Leading one of the design domains (integration, power, CDC/RDC, connectivity, etc.). ] Required Skills Verilog RTL development in CPU, SoC, or ASIC environments. Strong understanding of: SoC integration SoC architecture System interconnect protocols such as AXI and PCIe Experience with: UPF and low-power methodologies Static timing analysis (STA) Physical design interaction and implementation requirements Familiarity with scripting languages such as Tcl, Perl, Ruby, or Shell. Knowledge of formal verification techniques and tools. Personal Attributes Self-driven and able to work independently. Strong written and verbal communication skills. Strong problem-solving capability. Experience & Education 8+ years of SoC Design and Verilog RTL development experience. BE/B.Tech/ME/M.Tech (ECE/EEE or equivalent). . #LI-SR5 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Physical Design Lead(High Speed IP's)", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-07-27T06:48:00+00:00", "url": "https://global-external-amd.icims.com/jobs/88494/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. PMTS SILICON DESIGN ENGINEER THE ROLE AMD is looking for an experienced and highly motivated Principal Member of Technical Staff (PMTS) to join the CT Physical Design team. In this role, you will drive the physical implementation of industry-leading high-speed interface IPs including DDR, LPDDR, GDDR, PCIe, and other next-generation mixed-signal PHY solutions used across client, server, and graphics products. As a technical leader, you will work closely with architects, circuit designers, RTL, package, power integrity, signal integrity, SoC, and methodology teams to define and implement innovative physical design solutions that achieve aggressive PPA, frequency, power, and schedule goals on advanced process nodes. The ideal candidate combines deep physical design expertise with strong leadership capabilities and a proven track record of delivering complex, high-performance IPs to production. THE PERSON You are passionate about solving complex physical design challenges in advanced semiconductor technologies. You thrive in fast-paced environments, influence technical direction beyond your immediate team, and enjoy mentoring engineers while driving innovation in implementation methodologies. You possess deep understanding of high-speed digital and mixed-signal design implementation and have successfully delivered multiple tape-outs in advanced technology nodes. KEY RESPONSIBILITIES Lead physical design implementation of complex high-speed IPs such as DDR/LPDDR/GDDR PHYs, PCIe, SerDes, and related subsystems. Drive architecture and physical design co-optimization to achieve industry-leading Power, Performance, and Area (PPA). Own end-to-end implementation activities including: Floorplanning Power planning Placement Clock architecture CTS Timing closure Signal integrity closure Physical verification Tapeout signoff Drive high-frequency timing closure for challenging datapaths and clock distribution networks. Partner with architects and circuit designers to optimize PHY architectures for performance, power, and implementation efficiency. Develop and deploy innovative implementation methodologies to improve design quality, productivity, and scalability. Collaborate with cross-functional teams including Architecture, RTL, AMS, Package, SI/PI, Product Engineering, SoC, CAD, and EDA vendors. Debug and resolve complex implementation, silicon correlation, and post-silicon issues. Provide technical leadership for multiple projects and influence implementation strategies across organizational boundaries. Mentor SMTS/MTS engineers and help grow the technical capability of the organization. Drive continuous improvement initiatives in automation, AI-assisted design methodologies, and signoff flows. PREFERRED EXPERIENCE 15+ years of industry experience in Physical Design for advanced semiconductor products. Proven track record delivering multiple successful tape-outs on advanced technology nodes (N3/N4/N5 or equivalent). Extensive experience with high-performance and high-speed interface IPs such as: DDR4/DDR5/LPDDR5/LPDDR6 GDDR PCIe Mixed-signal PHYs Deep expertise in: Timing closure Clock design Physical implementation Power optimization Signal integrity Multi-voltage design methodologies Strong understanding of: Package interactions RDL ESD considerations Analog integration challenges Power integrity Experience closing timing at aggressive frequencies and implementing complex clocking structures. Expertise with industry-standard EDA tools including Cadence and Synopsys implementation/signoff flows. Experience driving methodology development and automation. Demonstrated leadership across cross-functional teams and geographies. TECHNICAL SKILLS Physical Design and Signoff STA and Timing Closure Clock Architecture and CTS Floorplanning and Power Planning IR/EM Analysis Physical Verification SI/PI Analysis Low Power Design (UPF/CPF) Advanced Node Design Methodologies Tcl/Python/Scripting AI-assisted Design Flows (preferred) LEADERSHIP EXPECTATIONS Recognized technical expert in physical design and implementation. Influences technical direction beyond immediate project boundaries. Leads strategic technical initiatives across multiple IP programs. Mentors and develops engineering talent. Drives innovation that improves product competitiveness, engineering productivity, and design quality. EDUCATION BS/MS in Electrical Engineering, Computer Engineering, VLSI Design, or related field. PhD preferred but not required. #LI-PM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Physical Design Engineer - Bengaluru, Multiple Vacancies", "company": "Graphcore", "location": "Bengaluru, India", "date_posted": "2026-07-27T01:19:29-04:00", "url": "https://job-boards.greenhouse.io/graphcore/jobs/8648270002", "is_hardware": true, "platform": "greenhouse", "jd_text": "Silicon Physical Design Engineer\n\nMultiple roles across different levels\n\nGraphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. \n\nAs part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing.  \n\nThe physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). \n\nWe are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge  designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to take ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. \n\nResponsibilities and Duties \n\nApplicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, focusing on achieving robust, high-performance and power-efficient designs in leading-edge process technologies while meeting ambitious development schedules\n\nContributions are expected to span multiple areas and involve: \n\nusing state-of-the-art EDA tools and in-house Graphcore flows to deliver final designs that are of sign-off quality \n\nenhancing existing flows and in-house tools/APIs to support new features and/or methodologies \n\nanalysis and/or debugging of complex engineering problems leading to workable solutions \n\ndeveloping an understanding of emerging technical issues and applying that knowledge to optimise in-house flows and methodologies \n\nCandidates will be expected to work closely both with other teams within Graphcore and with 3rd party support engineers/contractors, ensuring good communication between all parties, and to contribute meaningfully to the overall efficiency and success of the Physical Team\n\nEssential skills: \n\n A Degree in Electronic/Electrical Engineering, Computer Science or related subject with 3+ years of Industry experience \n\n Be highly motivated, a self-starter, and a team player\n\n Excellent problem-solving skills for debugging issues seen and finding root causes\n\n Ability to program/script (required to solve design issues, typically in Tcl and Python)\n\n Experience in 7nm or smaller technologies\n\n A good breadth of experience with physical design flows including: \n\nFloorplanning/Budgeting\n\nSynthesis\n\nPlace and Route\n\nClock CTS\n\nLogical Equivalence\n\nTiming Analysis\n\nPhysical Verification (DRC/LVS/ERC) \n\n Desirable skills: \n\n In depth expertise in one or more aspects of physical design flows\n\n Structuring of builds to maximise PPA\n\n Silicon transistor knowledge including std cell libraries and/or memories\n\n2D and 3D design (CoWoS, UCIe etc.)\n\n High speed, high power and/or full reticle chip design\n\n Ethernet, PCIe, LPDDR, HBM interfaces\n\n Power integrity and optimization\n\n 2nm or 3nm technologies\n\n Chip finishing (pad rings, chip level LVS/DRC/ERC)\n\n Design for test\n\n Team management\n\n Project Planning\n\nIn addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.", "jd_status": "stored"}, {"title": "Senior Staff Verification Engineer - Video", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-27T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446720114541", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nWe are looking for a highly experienced Senior Staff Verification Engineer with 13+ years of industry experience in IP, subsystem verification. The candidate will be expected to provide technical leadership, drive verification strategy, mentor engineers, and ensure first-pass silicon quality through robust verification methodologies and best practices.\n\nKey Responsibilities\nDefine and drive verification architecture, methodology, and execution strategy for complex IPs, subsystems.\nLead verification planning, testbench architecture, coverage closure, regression strategy, and sign-off activities.\nOwn end-to-end verification delivery including:Verification plan development\nTestbench architecture and implementation\nTest and stimulus development\nCoverage analysis and closure\nDebug and root-cause analysis\n\nCollaborate closely with architecture, design, firmware, and system teams to ensure comprehensive verification coverage.\nDrive adoption of verification best practices, automation, and productivity improvements across teams.\nMentor and technically guide junior and senior verification engineers.\nInfluence project execution through technical leadership and risk management.\n\nRequired Qualifications\n13+ years of experience in ASIC/SoC/IP verification.\nStrong expertise in SystemVerilog and UVM with proven experience architecting large-scale reusable verification environments.\nExtensive experience in coverage-driven verification methodologies and coverage closure.\nProven experience integrating and validating C/C++ reference models within UVM/SystemVerilog environments.\nStrong debugging skills\nHands-on experience with Assertion-Based Verification (ABV) and SystemVerilog Assertions (SVA).\nGood scripting skills in Python, Perl, Shell/TCL, with experience in automation and productivity enhancement.\n\nPreferred Technical Experience\nGood understanding of video and multimedia architectures, including one or more of:Video codecs (H.264, H.265/HEVC, AV1, VP9)\nVideo processing pipelines\nDMA frameworks\n\nExperience with industry-standard interfaces and protocols:AXI/AHB/APB\nNoC architectures\n\nExposure to firmware-hardware co-verification and system-level validation.\n\nAdditional Desired Experience\nHands-on experience in one or more of the following:\nsubsystem verification\nFirmware verification\nGate-Level Simulation (GLS)\nPower-Aware Verification (UPF)\nFormal Verification\nEmulation\nPerformance verification and validation\nSilicon bring-up support and post-silicon debug\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CAD RTL/DV Infrastructure Engineer, Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-27T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446716236335", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nJob Description\n\nWe are seeking a highly motivated CAD RTL/DV Infrastructure Engineer to join our Qualcomm Oryon CPU team. In this role, you will work closely with RTL, DV, and DFT teams to maintain and enhance our CI/CD infrastructure, driving continuous improvement in verification flows. You will collaborate with multiple teams across geographies to ensure robust and efficient design and verification processes.\nKey Responsibilities\nMaintain and enhance CI/CD infrastructure for CPU design and verification workflows.\n\nPartner with RTL, DV, and DFT teams to optimize verification flows and methodologies.\n\nDrive automation and continuous improvement initiatives across the CPU team.\n\nCollaborate with global teams to ensure alignment and scalability of infrastructure.\n\nWork with EDA tool vendors to drive bug fixes and resolve tool-related issues.\n\nTroubleshoot and resolve issues in design and verification environments.\n\nRequired Skills & Experience\nStrong experience with Git, GitHub, Python, and Shell scripting.\n\nHands-on experience with LSF (Load Sharing Facility) for job scheduling.\n\nFamiliarity with CI/CD tools such as Jenkins and workflow orchestration tools like Airflow.\n\nSolid understanding of CI/CD principles and infrastructure management.\n\nExcellent problem-solving and communication skills for cross-team collaboration.\n\nPreferred Qualifications\nExperience in RTL design using Verilog/SystemVerilog.\n\nUnderstanding of CPU microarchitecture concepts.\n\nFamiliarity with verification methodologies and flows.\n\nNice to have:\nExperience with Perforce for source control.\n\nAbility to create and maintain Splunk dashboards for monitoring and analytics.\n\nTools & Technologies\nGit, GitHub, Jenkins, Airflow, LSF, Python, Shell scripting, Perforce (optional), Splunk (optional).\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Engineer - HBM Analog Design", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-27T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/43470896", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nResponsibilities will include, but are not limited to:\nDesign, implementation and integration of complex analog circuits such as CMOS Amplifiers, Comparators, Bandgap References, LDOs, Charge Pumps, Oscillators, DLL, IO Buffers, Analog Test Mux, Process Monitor, and Temperature sensors for advanced DRAM products.\nDesign, implementation and integration of synchronous and asynchronous custom digital block\nContributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Analog/Memory/Logic circuits.\nParasitic modeling and design validation, reticle experiments and required tape-out revisions.\nOverseeing and managing the layout process including floor-planning, placement, and routing\nPerforming verification processes with modeling and simulation using industry standard simulators\nContributing to cross group communication to work towards standardization and group success.\nWorking with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product.\nProactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality.\nMentor and lead young designers.\nUsage & working with AI Skills is must\nStrong AI proficiency, a solid understanding of agentic AI models, and effective use of tools such as Claude are expected to significantly improve engineering efficiency, enhance PPA (Power, Performance, Area) optimization, and accelerate overall delivery timelines.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Senior Engineer - Analog Design", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-27T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/43472031", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nResponsibilities will include, but are not limited to:\nDesign, implementation and integration of complex analog circuits such as CMOS Amplifiers, Comparators, Bandgap References, LDOs, Charge Pumps, Oscillators, DLL, IO Buffers, Analog Test Mux, Process Monitor, and Temperature sensors for advanced DRAM products.\nDesign, implementation and integration of synchronous and asynchronous custom digital block\nContributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Analog/Memory/Logic circuits.\nParasitic modeling and design validation, reticle experiments and required tape-out revisions.\nOverseeing and managing the layout process including floor-planning, placement, and routing\nPerforming verification processes with modeling and simulation using industry standard simulators\nContributing to cross group communication to work towards standardization and group success.\nWorking with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product.\nProactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality.\nMentor and lead young designers.\nStrong AI proficiency, a solid understanding of agentic AI models, and effective use of tools such as Claude are expected to significantly improve engineering efficiency, enhance PPA (Power, Performance, Area) optimization, and accelerate overall delivery timelines.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Senior Engineer - Analog Design", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-27T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/43489714", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nResponsibilities will include, but are not limited to:\nDesign, implementation and integration of complex analog circuits such as CMOS Amplifiers, Comparators, Bandgap References, LDOs, Charge Pumps, Oscillators, DLL, IO Buffers, Analog Test Mux, Process Monitor, and Temperature sensors for advanced DRAM products.\nDesign, implementation and integration of synchronous and asynchronous custom digital block\nContributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Analog/Memory/Logic circuits.\nParasitic modeling and design validation, reticle experiments and required tape-out revisions.\nOverseeing and managing the layout process including floor-planning, placement, and routing\nPerforming verification processes with modeling and simulation using industry standard simulators\nContributing to cross group communication to work towards standardization and group success.\nWorking with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product.\nProactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality.\nMentor and lead young designers.\nStrong AI proficiency, a solid understanding of agentic AI models, and effective use of tools such as Claude are expected to significantly improve engineering efficiency, enhance PPA (Power, Performance, Area) optimization, and accelerate overall delivery timelines.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Senior Engineer - Analog Design", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-27T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/43472000", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nResponsibilities will include, but are not limited to:\nDesign, implementation and integration of complex analog circuits such as CMOS Amplifiers, Comparators, Bandgap References, LDOs, Charge Pumps, Oscillators, DLL, IO Buffers, Analog Test Mux, Process Monitor, and Temperature sensors for advanced DRAM products.\nDesign, implementation and integration of synchronous and asynchronous custom digital block\nContributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Analog/Memory/Logic circuits.\nParasitic modeling and design validation, reticle experiments and required tape-out revisions.\nOverseeing and managing the layout process including floor-planning, placement, and routing\nPerforming verification processes with modeling and simulation using industry standard simulators\nContributing to cross group communication to work towards standardization and group success.\nWorking with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product.\nProactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality.\nMentor and lead young designers.\nStrong AI proficiency, a solid understanding of agentic AI models, and effective use of tools such as Claude are expected to significantly improve engineering efficiency, enhance PPA (Power, Performance, Area) optimization, and accelerate overall delivery timelines.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Senior Engineer - Analog Design", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-27T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/43471758", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nResponsibilities will include, but are not limited to:\nDesign, implementation and integration of complex analog circuits such as CMOS Amplifiers, Comparators, Bandgap References, LDOs, Charge Pumps, Oscillators, DLL, IO Buffers, Analog Test Mux, Process Monitor, and Temperature sensors for advanced DRAM products.\nDesign, implementation and integration of synchronous and asynchronous custom digital block\nContributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Analog/Memory/Logic circuits.\nParasitic modeling and design validation, reticle experiments and required tape-out revisions.\nOverseeing and managing the layout process including floor-planning, placement, and routing\nPerforming verification processes with modeling and simulation using industry standard simulators\nContributing to cross group communication to work towards standardization and group success.\nWorking with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product.\nProactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality.\nMentor and lead young designers.\nStrong AI proficiency, a solid understanding of agentic AI models, and effective use of tools such as Claude are expected to significantly improve engineering efficiency, enhance PPA (Power, Performance, Area) optimization, and accelerate overall delivery timelines.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "SoC Modelling Architect", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-07-27", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/SoC-Modelling-Architect_JR2021696-1", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nThe NVIDIA Architecture Modelling group is looking for architects and software developers to join our various architecture efforts. A key part of NVIDIA's strength is to innovate in the graphics and parallel computing fields, delivering the highest performance in the world for high-performance computing. We are constantly looking for ways to improve our GPU architecture and maintain our leadership. In this position, you will be working with other world-class architects on modelling, analysis and validation of chip architectures and features that advance the state of art in performance and efficiency.\n\nWhat you'll be doing:\nModelling and analysis of graphics, LPU, SOC algorithms and features\n\nLead cmodel chip execution end to end working with various stakeholder both internal and external\n\nDrive the next generation Infra initiatives\n\nWork in a team to document, design, develop tools to analyze and simulate, validate, and verify models\n\nDevelop tests, test plans, and testing infrastructure for new architectures/features\n\nCode coverage analysis and reporting\n\nWhat we need to see:\nBachelors Degree (or equivalent experience) in a relevant discipline (Computer Science, Electrical Engineering or Computer Engineering) with 2+ years of relevant work experience.\n\nStrong programming ability: C++, C along with a good understanding of build systems (CMAKE, make) , toolchains (GCC, MSVC) and libraries (STL, BOOST)\n\nComputer Architecture background with experience in modelling with SystemC & TLM preferred\n\nFamiliarity with Docker, Jenkins, Python, Perl\n\nExcellent communication and interpersonal skills and ability to work in a distributed team environment\n\nNVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. Do you love the challenge of crafting the highest-performance silicon GPUs and SoCs possible? If so, we want to hear from you! Come, join our Architecture Simulation and Modelling team and help build the real-time, cost-effective computing platform driving our success in this exciting and quickly growing field.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior Verification Engineer, Emulation and Prototyping", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-07-27", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Emulation-and-Prototyping-Engineer_JR2020636", "is_hardware": true, "platform": "workday", "jd_text": "aNVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. Are you passionate about how ASIC @ NVIDIA is validated ? Have you wondered how we create close to real workloads to make sure chips @ NVIDIA remain reliable. Emulation and Prototyping plays an important role in achieving this.\n \nAre you interested in pushing the boundaries of innovation to make emulation & FPGA platforms faster, more scalable, and more efficient? Can you work in a fast-paced environment that requires coordination between many teams across geographies and solving sophisticated problems daily? If so, we are looking for hardworking systems engineers who will craft DV/Verification knowledge and extend to emulation & FPGA environments for our next generation GPUs, SOCs, NICs, and Switches on industry-standard FPGA prototyping and emulation platforms. We are now looking for a Emulation & Prototyping Engineer to join our Emulation team.\n\nWhat you’ll be doing:\nBuild emulation and FPGA environments by making RTL FPGA/emulation-friendly, partitioning the design, and taking it through synthesis, place-and-route, and emulator compilation flows.\n\nImprove performance of emulation and FPGA platforms, analyze timing/performance bottlenecks, and generate bitstreams/images.\n\nBring new DV Test benches that can provide high-level abstraction of C/SV TB, running at FPGA speeds.\n\nBring up designs on hardware emulation & FPGA platforms and drive complex debug and problem-solving activities.\n\nScale emulation/FPGA verification methodology in order to cater extensive test-plans\n\nWork closely with architects, designers, verification engineers, validation teams, and software teams to accomplish project goals.\n\nEnable pre-silicon software development, validation, and performance analysis using hardware emulation & FPGA environments.\n\nDevelop and optimize emulation-friendly validation infrastructures, including high-performance software interfaces and scalable debug methodologies.\n\nWhat we need to see:\nBS/MS (or equivalent experience) in Electrical Engineering, Computer Engineering, or related fields with 5+ years of proven experience in FPGA prototyping and/or hardware emulation.\n\nStrong understanding of FPGA prototyping and hardware emulation architectures, devices, flows, and tools.\n\nHands-on experience with Simulators or Emulators across vendors\n\nHands-on experience with emulation platforms such as Synopsys ZeBu, Siemens Veloce Synopsys or Cadence Z3. Familiarity with ProtoCompiler or Synplify Premier, Xilinx Vivado,\n\nExtensive knowledge of writing SV/Verilog code for TB-Emulator , high speed integrations\n\nUnderstanding of industry-standard protocols such as PCIe, CXL, NVLINK, USB, CHI, and CPU-GPU coherency.\n\nStrong expertise in developing and optimizing emulation-friendly C/C++ testbenches and transactors that can operate efficiently at emulation speeds is a critical skill for this role and experience minimizing host-emulator communication bottlenecks, improving transaction throughput, and architecting scalable software-driven validation environments for high-performance SoCs and multi-ASIC systems.\n\nAbility to develop efficient DPI/PLI/SystemC-based interfaces and software infrastructures that enable high-speed validation, debug, and bring-up on hardware emulation platforms.\n\nWays to stand out from the crowd:\nAbility to actively code in C/C++ , Python and perl \n\nPrior experience with hardware emulation or prototyping platforms (Synopsys HAPS, ZeBu, Siemens Veloce) of a high-performance processor or SOC is highly desirable.\n\nUnderstanding of performance-sensitive validation methodologies for large-scale emulation environments, including efficient logging, synchronization, memory handling, and protocol traffic generation and experience enabling pre-silicon software validation, firmware bring-up, or system-level debug on emulation platforms is a plus!\n\nBackground of QEMU/KVM and ability to script/scale the solution\n\nUnderstanding of Cadence/Synopsys/Siemens transactor solutions.\n\n \n#LI-Hybrid", "jd_status": "stored"}, {"title": "Principal Validation Engineer", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-07-27", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Principal-Validation-Engineer_2601100", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nMarvell is a leading provider of innovative storage technologies, including ultra-fast read channels, high-performance processors, leading edge transceivers, highly efficient analog designs, and powerful cryptographic engines.  These solutions address all segments of the hard disk drive (HDD) and solid-state drive (SSD) electronics markets.  Many of the same technologies have been utilized in Marvell Storage systems solutions products, power PCs, servers, cloud and enterprise systems.\nWhat You Can Expect\nDevelopment, porting, execution, and debug of bare metal SW on multiple SSD blocks to validate proper functionality\nCreate, maintain and improve code to support new features and standards\nWork with Design, FW, and Validation teams to debug any issues found and find root cause on failure cases\nCreate and review tests plans and prepare test result documents to be shared internally/externally\nCreate tests to measure performance, throughput, and power of multiple SoC blocks.\n\nWhat We're Looking For\nBachelor's degree in Software, Computer or Electrical Engineering, and at least 5-10 years professional experience and/or Master's degree in Software, Computer or Electrical Engineering, and at least 3-5 years professional experience, in following domains – Pre-Si Validation, Post-Si Validation, Stress & PVT testing\nOverall GPA of 3.5 or higher\nExcellent C/C++ SW development skills, a good understanding of embedded SW development, Linux and basic knowledge of ARM/RISC micro-processor or SOC architecture\nIn depth knowledge of DDR, SPI, PCIe, NVMe, is a plus\nExperience with NAND testing and debug, both from a SW and a HW perspective is a plus\nExpertise with embedded SW development and proven debug abilities and skills\nExpertise with typical lab tools:  Emulators, Oscilloscopes, Logic Analyzers\nAble to work across disciplines and manage time across several demands\nExcellent written and oral communication skills (English)\n​ #L1-LK1\n\nAdditional Compensation and Benefit Elements\nWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\n\nInterview Integrity \nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\n\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\n\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n\n#LI-TT1", "jd_status": "stored"}, {"title": "Sr. System Validation Manager", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-07-25T18:53:23.055000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000139829069-sr-system-validation-manager", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking a highly experienced and strategic System Validation Manager to lead multiple, concurrent product and system validation projects globally.  You will be the technical driver to lead   a multi-disciplinary team of system design, hardware and software engineers to deliver on validation of solutions and products.\nThis role requires an individual with deep embedded design experience and leadership skills with a proven track record of delivering and managing complex projects from concept to deployment Your primary mission is to ensure flawless execution, mitigate risks proactively, and drive decisions that align with our strategic business objectives of performance, cost, and time-to-market.\nKey Responsibilities:\nLead User Experience validation of Embedded Products & Solutions comprising of Renesas’s wide product portfolio of MCUs, MPUs, Power and Connectivity families\nDevelop end-to-end system validation plans for solutions targeting applications in Robotics, AI Infrastructure, Medical and Consumer for broad-market customers\nLead a team of system design,  hardware and software engineers to deliver on validation of solutions and products\nDrive customer use-case and scenario validation.\nCreate a center of excellence for developing value-added assets – HW, SW , Tools, Documents - enabling a superior designer experience\nStakeholder Management: Serve as the primary point of contact for executive leadership, providing clear, concise, and data-driven updates on project status, risks, and key performance indicators (KPIs). Manage expectations and secure buy-in for critical decisions.\nCross-Functional Collaboration : Work closely with leaders across Marketing, Product development, Application Engineering and Sales/FAE teams to create cohesive project development plans.\n\n \nBachelor’s or master’s degree in Electronics & Communication Engineering, Computer Engineering, or a related technical field.\nMinimum of 12-15 years of direct embedded product development and program management experience within the semiconductor industry or at a product development firm.\nDirect working knowledge of MCUs, Power Management, Connectivity products\nDeep technical knowledge of Embedded design including firmware, hardware and software\nProven experience managing multiple complex semiconductor projects concurrently, from definition to production ramp.\nExpertise with advanced project management tools (e.g., JIRA, MS Project, Confluence) and methodologies (Waterfall, Agile, Critical Chain).\nExceptional communication, negotiation, and influencing skills, with the ability to present complex issues clearly to both technical and non-technical audiences.\nRequired Skills & Experience\nSoC Validation ExpertiseSoC bring-up and silicon debug\nFunctional and system validation\nUse-case and scenario validation\nSubsystem validation\nCoverage planning and closure\n\nProtocol & Interface ValidationI3C, I2C, SPI, UART\nEthernet, PCIe, USB\nDDR, LPDDR\nMIPI CSI/DSI\n\nDebug & Lab EquipmentJTAG / Lauterbach\nOscilloscope\nLogic Analyzer\nProtocol Analyzers\nPower Analyzers\nHigh-speed measurement equipment\n\nSoftware & AutomationPython\nC/C++\nShell scripting\nTest automation frameworks\nData analytics and visualization tools\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "ASIC Design and STA Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-07-25", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/ASIC-Design-and-STA-Engineer_JR2021789-1", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nNVIDIA is looking for a best-in-class ASIC STA Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency for today's AI platforms! Come and take a part in designing our groundbreaking large scale and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.\n\nWhat you will be doing:\nBe in charge of full chip and/or chiplet level STA convergence from early stages to signoff.\n\nTake part in top level floor plan and clock planning.\n\nOptimize, together with CAD signoff flows and methodologies.\n\nDigital Partitions' and analog IPs' timing integration, giving feedback to PD/RTL and driving convergence.\n\nWork closely with logic design and DFT engineers to define and implement constraints for the various work modes, including their optimization for runtime and efficiency.\n\nWhat we need to see:\nB.SC./ M.SC. in Electrical Engineering/Computer Engineering.\n\n3+ years of experience in physical design and STA\n\nProven experience in RTL2GDS and STA design and convergence\n\nFamiliarity with physical design EDA tools (such as Synopsys, Cadence, etc.)\n\nHands on STA experience from early stages to signoff using Synopsis Primetime. Deep knowledge in timing concepts required.\n\nGreat teammate.\n\nNVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior CAD Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-07-25", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-CAD-Engineer_JR2021804-1", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been redefining computer graphics, PC gaming, and accelerated computing for more than 25 years. Today, we're tapping into the unlimited potential of AI to define the next era of computing — an era in which our GPUs act as the brains of computers, robots, and self-driving cars. Doing what's never been done before takes vision, innovation, and the world's best talent. Come join our diverse team and see how you can make a lasting impact on the world.\n\nWe are now looking for a Physical Design Methodology and Operations Engineer! You'll join a small team that owns the infrastructure powering NVIDIA's semiconductor design flows — coordinating hundreds of thousands of jobs per day across datacenters with 10,000+ hosts, serving over 1,000 chip designers worldwide. Our platform spans job orchestration, event-driven trigger systems, global service interconnection, web interfaces to tools, and a Jenkins-like CI/CD backbone — a production system with direct stakes in GPU, CPU, SoC and networking tapeouts. You'll own a functional area within the team while contributing across broader operations. Our stack includes mature Perl and Python services alongside modern React frontends and Elasticsearch-based telemetry. We're actively modernizing, and we need someone who can think architecturally — evaluating what we have, identifying what needs to change, and driving that evolution in a way the team can execute and maintain. If you want to own something critical at scale and shape how it grows, this role is for you.\n\nWhat you'll be doing:\n Designing and supporting mechanisms for coordinating and maintaining large-scale semiconductor design tasks across multiple global datacenters.\n\nOwning the architecture of one or more platform components — defining interfaces, data models, and service boundaries that can scale and evolve.\n\nLeading the modernization of legacy services — evaluating existing Perl and Python backends, proposing migration strategies, and driving execution with the team.\n\nDebugging and improving production services spanning web browsers, containerized microservices, and bare-metal Linux hosts.\n\nBuilding and improving web interfaces to configure, launch, and analyze EDA tools and design flows.\n\nMining and analyzing large datasets of job execution telemetry and tool quality-of-results data to improve flows and catch regressions.\n\nMentoring junior engineers and contributing to design reviews and technical standards across the team.\n\nHelping invent next-generation semiconductor design methodology.\n\nOptionally, contributing directly to the physical design of GPU, CPU, SoC, and networking products — a rare opportunity for an infrastructure engineer.\n\nWhat we want to see:\nBachelor's or master's degree in computer science or computer systems engineering (or equivalent experience).\n\n5+ years of software engineering experience, with a track record of designing and delivering production systems.\n\nStrong software architecture and design skills — experience defining service boundaries, APIs, data models, and system interfaces.\n\nProficiency in Python and/or Perl; comfort with JavaScript and web technologies.\n\nExperience with distributed systems at meaningful scale.\n\nProven ability to lead a project through its full lifecycle, from requirement solicitation to architecture design, to implementation, to maintenance and support. \n\nComfort owning and debugging Linux-based production services.\n\nWays to stand out from the crowd:\nExperience with workflow orchestration systems (Airflow, Argo, Temporal, Luigi, or similar).\n\nExperience with containerization technologies such as Docker or Kubernetes.\n\nFamiliarity with Elasticsearch / Kibana / Vega for telemetry and dashboarding.\n\nExperience with MSSQL/Mysql/SQLite or other relational and NoSQL datastores.\n\nExposure to Static Timing Analysis or VLSI physical design.\n\nNVIDIA is widely considered one of the technology world's most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. If you're an engineer who thinks in systems, takes pride in designing things that last, and wants to see the silicon your work helps produce — we want to hear from you.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "DFT RTL Design Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-07-24T10:38:00+00:00", "url": "https://global-external-amd.icims.com/jobs/88459/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. DFT RTL Lead   THE ROLE: It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. THE PERSON: As a DFx Silicon Design Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team! KEY RESPONSIBILITIES: Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications. Perform DFT RTL design integration, insertion, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS, ATPG and Scan GLS. Work with multi-functional teams and handling schedules Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design. Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis. PREFERRED EXPERIENCE: Knowledge of DFT techniques such as JTAG/IEEE standards, SSN, Scan and ATPG, memory BIST/repair or Logic BIST Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential. Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl) Familiar with Verilog design language, Verilog simulator and waveform debugging tools Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus. Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc. is a plus Strong problem-solving skills. Team player with strong communication skills. ACADEMIC CREDENTIALS: Bachelor’s or Master’s degree in electrical/Electronic Engineering with 7+Yrs #LI-SS1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Staff Engineer - Design Verification ", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-07-24T08:52:39.775000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000139544875-staff-engineer-design-verification-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are looking for a motivated and talented Design Verification Engineer to join our team in creating next-generation Power management solutions. \n\nJob Responsibilities\nDefine and own verification plans, methodologies, and coverage strategies for complex SoC designs\nArchitect and implement verification environments from scratch and enhance existing frameworks\nDrive block-level, subsystem-level, and full-chip verification\nBuild Agents, sequences, drivers, monitors, and scoreboards as part of automation.\nIntegrate industry-standard VIPs, create custom transactor.\nLead end2end verification, including: Gate level simulations and debugs,  coverage analysis and closure, regression, triage failures, and ensure quality sign-off\nMentor junior and mid-level verification engineers\nAct as technical lead or owner for key verification deliverables\n\nBachelor's degree in Electrical Engineering or equivalent practical experience.\nOverall 12+ years of experience with verification methodology such as universal verification methodology (UVM).\nExperience with industry-standard simulators, revision control systems, and regression systems.\nExperience with Architecting block the full verification lifecycle.\nExcellent problem solving and communication skills.\nConstruct testbenches components like scoreboard, agents, sequencers, and monitors\nDebugging RTL and Gate simulations and working with cross functionals team to verify fixes\nConverting verification tests to test patterns and assisting Test Engineers on ATE vector bring up\nExperience developing and maintaining verification testbenches, test cases, and test environments.\nUnderstanding of SoC architecture and functionality, Mixed signal designs.\nGood knowledge of analog components :  ADC, DAC, PLL, Oscilators and PI controllers. \nPassion for learning and engineering great solutions\nProven written and verbal communication skills that demonstrate clarity of thought and conviction\nWorking knowledge of one or more scripting languages (Perl, Python) and ability to use them to automate/accelerate verification and analysis tasks\nExperience of directed and constrained random verification methodology Good knowledge in UVM, Verilog, SV, C/C++, Shell, Python\nStrong debug, logical thinking and analytical skills\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "DFT-DV Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-07-24T06:19:00+00:00", "url": "https://global-external-amd.icims.com/jobs/84984/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. SMTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning PREFERRED EXPERIENCE: Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.) Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior/Staff/Sr Staff Engineer, Validation", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-07-24T03:02:47.460000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000139466509-senior-staff-sr-staff-engineer-validation", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Senior Engineer Validation position is an IC role which requires 7+ years of experience of Bench Validation and Debug of Power Management ICs as part of 2.6B$ Power Business Unit at Renesas. Primary responsibilities include fully own Bench Validation, Silicon Debugs, Automation of Equipment and Tests of PMICs. Will also be responsible for analysing the data, documenting and reporting findings to the Systems team and work closely with Design & Systems experts to ensure quality ICs. The role also involves opportunity to technically lead a small team with ownership of doing end to end IC validation.\nThe candidate should be able to develop and automate industry standard tests which are done for switching converters. In addition, the candidate should be able to define the equipment requirements for testing Power Management ICs and help setup lab from scratch. Ability to debug setups, equipment related issues and identify solutions is a must. The candidate needs to minimize Bench Testing cost while ensuring high quality in testing by employing standardization, reuse and automation.\n \nResponsibilities\nMaximise utilisation of Benches, equipment and resources through automation and industry best practices.\nWrite bench test programs in Python, C, Labview and be able to debug ATE programs. Work with a mindset of smart work, collaboration with rest of the team\nIn this technical role, candidate must be very strong hands on and should also be able to technically coach/mentor/ramp up new college graduates and freshers.\nProject the schedule for bench test program development, testing and debug based on the infrastructure and resource availability and identify gaps/risks for execution.\nOwnership and Accountability for accuracy, quality and presentation of all deliverables (waveforms, reports, documentation, results etc).\nTechnically lead bench validation and debug of multiple PMICs out of Bengaluru, while working with design/systems teams which located at different geographies and in different time zones.\nExpertise of using Validation related equipment including various types of Power Supplies, Load Slammer, Scopes and probes, Multi-meters, Analog switches, Relays, Computer to IC board communications etc.\nMust have experience of defining and driving Bench Validation plan for Power Management ICs and Evaluation Boards.\nMust be fluent with using FPGAs for testing Digital and emulating system behaviour.\nMust have experience with ATE-Bench correlation and should be able to drive that independently.\nShould be well versed with one or more Power Chip Communication protocols e.g. SPMI, PMBUS, SVI3, SVID etc. Should be comfortable with I2C.\nShould be able to create basic circuits on bread board for experimentation and design PCBs.\n\nBachelor’s or master’s degree in electrical engineering\n5+ years of hands-on experience in Bench Validation of Mixed Signal ICs, especially PMICs .\nAbility to work with clarity and predictable timelines to ensure deliverables with high quality.\nCross cultural awareness and sensitivity.               \nResults-oriented and able to deliver on-time under tight schedule pressure.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.\nAt Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.\nWe believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.\nAre you ready to join our team and shape the future with us?\nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "NOC Design Verification Engineers (Engineer/Sr Engineer)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-24T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719958035", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nASIC Verification Engineer (3+ to 5+ Years of Experience)\nKey Requirements\nASIC Verification Engineers with a minimum of 3+ to 5+ years of experience.\nGood hands-on experience with C/C++, classes, templates, and STL libraries. Must possess an excellent understanding of OOP concepts, inheritance, and polymorphism.\nStrong coding experience in Verilog and SystemVerilog.\nExposure to assertion-based verification or formal verification (would be an added advantage).\nDefine and develop testbenches, test plans, and verification environments from scratch for IPs/subsystems.\nWorking experience in scripting and automation, preferably using Python or shell scripting.\nExperience in developing verification plans from scratch and testbench development using detailed specifications and test plans.\nShould be able to perform functional, code, and assertion coverage analysis to ensure complete verification closure.\nIn-depth understanding of AMBA protocols, including AXI, APB, and AHB.\nProficiency with verification tools such as VCS or Cadence simulators and waveform analyzers.\nStrong foundational knowledge of digital design, blocks, and components.\nStrong debugging skills and good knowledge of assertions, functional coverage coding, and coverage closure.\nGood knowledge of code coverage analysis and closure.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "STAFF, ASIC TECHNICAL PROGRAM MANAGEMENT", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-24T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/43332806", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nEngineering Program Manager with proven experience leading ASIC/SoC development programs, responsible for coordinating multi-functional deliverables across Micron. The role requires end‑to‑end ownership of ASIC development—from architecture and RTL through verification, PnR, integration, and silicon validation—along with strong project planning skills in estimation, scheduling, and milestone dependency management.\n\n Job requirements:\nBS/BEE in Electrical or Electronics Engineering with 7+ years of experience.\nExperience in ASIC/SoC design and development programs.\nProven track record of delivering ASIC products end‑to‑end.\nStrong understanding of the ASIC design flow.\nExperience driving risk management, change control, and development reviews.\nFamiliarity with ISO 9001 requirements; experience with FuSa and ISO 26262 is encouraged.\nExperience coordinating programs across multiple, global organizations.\nStrong proficiency with program/project management tools.\nApply AI-enabled engineering tools\n\nJob Function: Responsible for end‑to‑end program execution of semiconductor devices, ensuring schedule, power, and cost targets are met.\nDrive risk management, change control, development reviews, and compliance with ASIC development processes.\nRegularly report to senior management on key achievements, metrics, risks, and mitigation plans.\nPartner closely with design and technical leads, implementation teams, and peer program managers to ensure timely delivery of high‑quality products.\n\nSkills / Experience:\nExperience across the complete ASIC development lifecycle.\nStrong proficiency with Microsoft tools including Microsoft Project (MPP), Advanced Excel, and PowerPoint, along with other project management tools.\nProficiency in business intelligence tools, particularly Microsoft Power BI, for data visualization, reporting, dashboard development, data modeling, and report automation.\nWorking knowledge of Microsoft SharePoint, including document libraries, workflows, and collaboration features.\nStrong interpersonal and communication skills, with the ability to engage effectively at all organizational levels.\nProven track record of program management performance.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "CAD RTL/DV Infrastructure Engineer, Sr Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-24T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719946720", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nWe are seeking a highly motivated CAD RTL/DV Infrastructure Engineer to join our Qualcomm Oryon CPU team. In this role, you will work closely with RTL, DV, and DFT teams to maintain and enhance our CI/CD infrastructure, driving continuous improvement in verification flows. You will collaborate with multiple teams across geographies to ensure robust and efficient design and verification processes\n\n8+ years Experience\n\nKey Responsibilities\nMaintain and enhance CI/CD infrastructure for CPU design and verification workflows.\nPartner with RTL, DV, and DFT teams to optimize verification flows and methodologies.\nDrive automation and continuous improvement initiatives across the CPU team.\nCollaborate with global teams to ensure alignment and scalability of infrastructure.\nWork with EDA tool vendors to drive bug fixes and resolve tool-related issues.\nTroubleshoot and resolve issues in design and verification environments.\nRequired Skills & Experience\nStrong experience with Git, GitHub, Python, and Shell scripting.\nHands-on experience with LSF (Load Sharing Facility) for job scheduling.\nFamiliarity with CI/CD tools such as Jenkins and workflow orchestration tools like Airflow.\nSolid understanding of CI/CD principles and infrastructure management.\nExcellent problem-solving and communication skills for cross-team collaboration.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nPreferred Qualifications\nExperience in RTL design using Verilog/SystemVerilog.\nUnderstanding of CPU microarchitecture concepts.\nFamiliarity with verification methodologies and flows.\nNice to have:Experience with Perforce for source control.\nAbility to create and maintain Splunk dashboards for monitoring and analytics.\n\nTools & Technologies\nGit, GitHub, Jenkins, Airflow, LSF, Python, Shell scripting, Perforce (optional), Splunk (optional).\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RFIC Digital Verification Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-24T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719930124", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nDigital Verification Engineer for IPs, ASICs, and Chipsets used in Qualcomm Snapdragon power solutions.\n \n Job Description\n Qualcomm is a company of inventors that unlocked 6G ushering in an age of rapid AI acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives.\n But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 6Gs potential into world-changing technologies and products. This is the AI Invention Age, and this is where you come in.\n  QCT is currently seeking digital verification engineers for the mixed-signal ASICs that support QCTs mobile platforms for next generation 6G RFIC/PMIC/Codec technologies.\n Successful candidates will be working on the following:\n - Block/Subsystem/SoC level digital verification using constrained-random coverage methodologies at both RTL and Gate Level.\n - The skills involved includes SV/UVM/UVM_RAL/Randomization/Coverage/SVA.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nPreferred Qualifications\n - Experience in writing Test Plans independently\n - Experience in writing/updating Verification Testbench\n -Experience with debugging RTL & Gate level simulations\n -Experience with Functional Coverage &Code Coverage\n -Experience with Scripting in perl, python, tcl\n -Experience in planning Verification architecture, review testbench/ testplans with juniors, identify coverage gaps, propose alternate methods for coverage\n - Should have been involved in leading a chip DV effort\n -  Should have been self-driven and quick learner\n - Experience with Power aware(UPF) verification and debugs is plus\n - Silicon Debug Experience a plus.\n - Experience with Mixed Signal Designs involving DSP a plus\n - Modeling Experience with Matlab, Octave a plus\n  \nMinimum Qualifications\n Required: Bachelor's, Electronics or EE, 3+ years of work experience\n Preferred: Master's, VLSI, Electronics or EE. 2+ years of experience\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "principal Application engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-07-24", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/principal-Application-engineer_R55611", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nsoftware expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.\nThe Cadence Advantage\n•    The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.\n•    Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. \n•    The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success\n•    Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests\n•    You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.\nJob Summary\nAs a senior member of the India Field Organization for the Digital and Signoff Group, you will partner closely with our top semiconductor customers to drive and build unique and innovative methodologies to implement cutting-edge designs. This involves working closely with the customers to understand their key challenges, develop efficient methodologies, help them leverage the latest tool capabilities, and guide them to achieve their design goals. You will have an opportunity to acquire both breadth and depth of technical knowledge, get wide exposure to the latest designs that customers are working on, and have the ability to influence at all levels, both internally and externally.\nThis role also provides a front-row opportunity to participate in the evolution of key technology solutions to the most pressing design problems. In this role, you will have the opportunity to work with product teams to influence product direction with your timely feedback and observations. \nIn addition to wielding technical influence, your unique understanding of the customer and their key careabouts will have a deep impact on the business strategy. You will collaborate closely with the sales teams to help drive account strategy and campaigns.\nThis an excellent opportunity to work in a supportive and friendly work environment, where we are vested in each other’s success, and are passionate about technology  and  innovation.\nJob Responsibilities\n•    Independently drive RTL-to-GDSII metrics on complex designs\n•    Drive methodology and solution-oriented discussions with key stake holders\n•    Partner with sales team to help drive account strategy and campaigns\n•    Evangelize and drive adoption of new technology across customers\n•    Produce out-of-the-box solutions to customer problems using either tool capabilities or scripting techniques\n•    Deploy ML based Solutions to improve productivity and PPA\n•    Narrow down complex problems to pointed tool issues for R&D resolution\n•    Collaborate with worldwide AE teams and mentor junior team members\nQualifications\n•    BE/BTech/ME/MS/MTech in Electrical/Electronics \nExperience and Technical Skills required\n•    8+ years of experience in Digital Implementation flow on advanced nodes\n•    Expertise in one or more domains – Synthesis/PnR/STA\n•    Knowledge of scripting languages & Flow development is a big plus\n•    Must have excellent debugging skills and ability to separate out the critical issues from trivial ones.\nBehavioural skills required\n•    Must possess strong written, verbal and presentation skills\n•    Ability to establish a close working relationship with both customer peers and management\n•    Explore what’s possible to get the job done, including creative use of unconventional solutions\n•    Work effectively across functions and geographies\n•    Push to raise the bar while always operating with integrity\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Senior Circuit Design Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-07-24", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Circuit-Design-Engineer_JR2021805", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people.\n\nToday, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.\nThis is a phenomenal opportunity to contribute to innovative technology in a role that significantly influences silicon performance. As a part of our world-class engineering team, you will help craft the future of AI and accelerated computing, working alongside very hard-working engineers dedicated to groundbreaking innovations.\n\nWhat you'll be doing:\nBe part of a hardworking, talented, multi-functional Global Circuits Team, designing and delivering groundbreaking circuit IPs involving SRAM arrays, Analog and/or Digital circuits.\n\nWork on architecting innovative circuit solutions and methodologies which supervise, measure on-chip silicon performance parameters and close the gap to pre-silicon estimations for logic and RAMs\n\nBe involved in design and verification of Custom Circuit IPs to improve the power, performance, silicon correlation and security of NVIDIA CPU, GPU and Networking chips\n\nParticipate in discussion with various teams to understand challenges related to Vmin, Vmax, VF, Yield, spice modelling, silicon debug and propose innovative solutions.\n\nUnderstanding of existing circuit methodologies for logic/RAMs and suggest improvements.\n\nThis role includes interacting with several global teams across geographies, understanding various methodologies and improving silicon correlation of logic and RAM circuits.\n\nBe a mentor/technical lead for junior team members.\n\nWhat we need to see:\nHave sound fundamentals of CMOS devices, RC circuits, timing concepts involving dynamic and sequential circuits.\n\nHands-on experience with circuit design, spice simulations, statistical modelling, Static/Dynamic timing analysis\n\nKnowledge of silicon corelation, data analytics and physical design is a huge plus.\n\nAbility to close design to the specs by running and developing various flows like EM, IR, Noise, and static timing analysis (STA)\n\nGood communication skills ; should be an excellent teammate.\n\nBE/M-Tech in Electrical & Electronics or equivalent experience.\n\n3-8 years of experience\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We invite you to join our team with some of the most hard-working people in the world working together to promote rapid growth. Are you passionate about becoming a part of an outstanding team supporting the latest in GPU and AI technology?\n\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Digital IC Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-07-24", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25016704", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n In this position, you will be working on high-speed mixed-signal communication circuits using state-of-the art process technology, as well as be involved in the design of high performance digital circuits interfacing to leading edge analog circuitry as part of an overall system.\n\n Your responsibilities will include RTL coding, simulation, synthesis, timing closure, verification, evaluation, debugging of high-speed communication chips both at the circuit level and behavioral level.\n\n As a design engineer, you will prepare test methods and specifications, assist in preparation of application information, data sheets and demo boards. You will develop solutions to complex problems through assessment of various techniques and approaches. You will plan and organize work to ensure timely completion of many independent tasks with general instructions on routine tasks and with detailed instructions on new assignments.\n\n This position involves routine communication with a highly talented team of analog and digital design engineers to solve problems and present information as well as active participation in work groups, providing ideas and collaborative teamwork.\n\nQualifications\nMinimum requirements:\n3+ years of relevant experience\nA thorough understanding of digital logic design\nFamiliarity with the Verilog language and simulators\nA good understanding of analog functionality and exposure to analog IC design methods\nAbility to solve problems using a systematic approach\n\nPreferred qualifications:\nExperience with System Verilog\nDemonstrated strong analytical and problem solving skills\nStrong verbal and written communication skills\nAbility to work in teams and collaborate effectively with people in different functions\nStrong time management skills that enable on-time project delivery\nDemonstrated ability to build strong, influential relationships\nAbility to work effectively in a fast-paced and rapidly changing environment\nAbility to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "RF/ Electrical Engineer", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2026-07-24", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/Electrical-Engineer_R2622239", "is_hardware": true, "platform": "workday", "jd_text": "Who We Are\n\nApplied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips – the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world – like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world. \n\nWhat We Offer\n\nLocation:\nBangalore,IND\nYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. \n\nAt Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. \n \n \nAs an Electrical Engineer, you are responsible for designing, modifying, and troubleshooting electrical or electronic engineering assemblies, layouts, schematics, and drawings to advance the equipment that supports our technology. Using your technical experience and critical thinking skills, you will perform engineering analysis, generate test reports, develop innovative solutions, and create documentation for product releases. You will also coordinate the procurement and assembly of components, identify sources of critical parts, and resolve technical issues to ensure peak performance. \n \nKey Responsibilities\nContribute to the design, development, and validation of RF delivery subsystems and electrical components.\nSupport RF system integration activities, including impedance matching networks, transmission lines, and related hardware.\nCollaborate with cross-functional teams (Mechanical, Electrical, Process) to support design, testing, and issue resolution.\nPerform hands-on lab testing and characterization of RF and electro-mechanical systems using standard measurement equipment.\nTroubleshooting RF and high-voltage system issues using structured problem-solving approaches.\nAnalyze test data and provide insights to improve system performance and reliability.\nSupport EM and circuit simulations using standard tools to aid design validation and optimization.\nDocument test results, analysis, and design updates through clear technical reports and presentations.\nParticipate in design reviews and contribute to discussions on design improvements and validation results.\nAbility to code, develop additions to data solvers, as well as data post-processing\nBasic Qualifications\nBachelor’s degree with ~ 8- 10 years of relevant experience (or Master’s with (5-8  years), PhD with 2- 4 years experience; or equivalent experience. or equivalent practical experience.\nWorking knowledge of RF fundamentals, transmission lines, and impedance matching concepts.\nFamiliarity with RF/EM simulation tools such as HFSS, ADS, Q3D, or similar.\nExperience with circuit design and simulation tools (SPICE, ADS, or equivalent).\nExposure to lab equipment such as network analyzers, spectrum analyzers, oscilloscopes, etc.\nStrong analytical and troubleshooting skills with a structured approach to problem solving.\nBasic scripting or programming exposure (Python, MATLAB, or similar) is desirable.\nGood communication and documentation skills.\n\nPreferred Qualifications\nExposure to semiconductor equipment or industrial systems is a plus.\nAppreciates learning and understanding challenges and limitations within other disciplines on system designs\nGood understanding of high-voltage and RF power systems.\nFamiliarity with PCB/schematic tools (OrCAD, Cadence, or similar).\nInterest in EM modeling and simulation-driven design.\nWillingness to learn cross-disciplinary concepts (mechanical, thermal, plasma interaction).\nExperience with RF/uW generator/source, impedance matching network, transmission line, and antennas. \nTechnical working experience: 100 KHz to 100 MHz, Watt to Kilo-Watt ranges, and high voltage DC delivery. \nFamiliar with high voltage (>10 KV) and high current (>100 Arms) design rules; arcing, tracking, heat, and parasitic.\n\nBehavioral Expectations\nDemonstrates willingness to learn and grow technically.\nWorks effectively within a team environment.\nTakes ownership of assigned tasks and delivers with quality and accountability.\n \n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nAssignee / Regular\nTravel:\nYes, 20% of the Time\nRelocation Eligible:\nYes\n\nApplied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "Senior Engineer(Software Testing)", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-07-24", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Senior-Engineer-Software-Testing-_R3087-26-5", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nWe are looking for an energetic and self-motivated person with a Computer Science background to join our Firmware / Embedded Software team in the Communication Business Unit at Microchip. We are building firmware for high performance System on Chip (SoC) and Ethernet PHY devices developed by our hardware teams. These products include the PIC64-HPSC product (https://www.microchip.com/en-us/products/microprocessors/64-bit-mpus/pic64-hpsc), which is radiation-hardened multi-core RISC-V processor, intended for spaceflight computing and the Meta-DX2 product, an 800 GbE Ethernet PHY/retimer device for data center, enterprise, service provider, and AI/ML networking applications. These devices support the aerospace and communications markets as well as a growing number of applications in next generation embedded systems. Our focus is on technical excellence, teamwork, collaboration, and continuous improvements in an open and encouraging environment.  If you have a strong technical background in firmware or embedded software testing, embedded systems, and communications protocols, then this is the position for you!\nAs a Senior Firmware Verification Engineer, you will be part of a team of professionals designing and implementing tests for embedded software and drivers for modern System-on-Chip (SoC) devices. You will participate in all stages of the firmware / embedded software project, for example: defining functional test plans, building/supporting test frameworks, automated regression environment and test infrastructure, designing and implementing tests and working with the Software Development teams to resolve bugs.  This verification work spans the pre-silicon development phase, which uses FPGA-based prototyping platforms and the post-silicon phase which uses lab-based evaluation boards.  Additionally, our team leverages AI tools such as Claude Code and GitHub CoPilot in all areas of software test development.\n\nRESPONSIBILITIES\nTranslate functional specifications, requirements, and standards into comprehensive test plans\nDesign, develop, and debug tests to verify firmware / embedded software and maintain these tests in regression\nDeveloping and supporting our CI/CD automated regression environment\nDeveloping and maintaining test frameworks for both pre and post silicon testing\nLeverage AI tools such as Claude Code or GitHub CoPilot in all areas of software test development\nSetup and configuration of 3rd party test equipment and Microchip SoC test boards\nWriting and reviewing comprehensive engineering documentation\nWork with the product development, application, and validation engineering teams as part of test related activities\n\nRequirements/Qualifications:\n\nBachelor’s Degree in Computer Science or equivalent\n5+ years of related work experience in Software/Firmware Verification\nStrong knowledge of C/C++ and Python programming and object-oriented design principles\nExperience in using Claude Code or GitHub CoPilot\nExperience with embedded ARM, RISC-V, or MIPS is an asset\nExperience with Linux in an embedded system or an RTOS is an asset\nExperience debugging tests and firmware with prototype FPGA/ASICs is an asset\nExperience with Ethernet/IP/TCP-IP or other communications protocol development is an asset\nMust be comfortable in a lab environment engaging in bring up and debug activities on hardware and firmware systems\nExcellent analytical, problem solving, communication, and documentation skills\nStrong interpersonal skills, experience as part of a collaborative development team, and a passion for mentoring those around you\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Physical Design Lead", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-07-23T07:28:00+00:00", "url": "https://global-external-amd.icims.com/jobs/88447/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. SMTS SILICON DESIGN ENGINEER THE ROLE AMD is looking for an experienced and highly motivated Senior Member of Technical Staff (SMTS) to join the CT Physical Design team. In this role, you will drive the physical implementation of industry-leading high-speed interface IPs including DDR, LPDDR, GDDR, PCIe, and other next-generation mixed-signal PHY solutions used across client, server, and graphics products. As a technical leader, you will work closely with architects, circuit designers, RTL, package, power integrity, signal integrity, SoC, and methodology teams to define and implement innovative physical design solutions that achieve aggressive PPA, frequency, power, and schedule goals on advanced process nodes. The ideal candidate combines deep physical design expertise with strong leadership capabilities and a proven track record of delivering complex, high-performance IPs to production. THE PERSON You are passionate about solving complex physical design challenges in advanced semiconductor technologies. You thrive in fast-paced environments, influence technical direction beyond your immediate team, and enjoy mentoring engineers while driving innovation in implementation methodologies. You possess deep understanding of high-speed digital and mixed-signal design implementation and have successfully delivered multiple tape-outs in advanced technology nodes. KEY RESPONSIBILITIES Lead physical design implementation of complex high-speed IPs such as DDR/LPDDR/GDDR PHYs, PCIe, SerDes, and related subsystems. Own end-to-end implementation activities including some or all of these domains: Floorplanning Power planning Placement Clock architecture CTS Timing closure Signal integrity closure Physical verification Tapeout signoff Drive high-frequency timing closure for challenging datapaths and clock distribution networks. Partner with architects and circuit designers to optimize PHY architectures for performance, power, and implementation efficiency. Develop and deploy innovative implementation methodologies to improve design quality, productivity, and scalability. Collaborate with cross-functional teams including Architecture, RTL, AMS, Package, SI/PI, Product Engineering, SoC, CAD, and EDA vendors. Mentor junior engineers and help grow the technical capability of the organization. Drive continuous improvement initiatives in automation, AI-assisted design methodologies, and signoff flows. PREFERRED EXPERIENCE 10+ years of industry experience in Physical Design for advanced semiconductor products. Proven track record delivering multiple successful tape-outs on advanced technology nodes (N3/N4/N5 or equivalent). Experience closing timing at aggressive frequencies and implementing complex clocking structures. Expertise with industry-standard EDA tools including Cadence and Synopsys implementation/signoff flows. Experience driving methodology development and automation. Demonstrated leadership across cross-functional teams and geographies. TECHNICAL SKILLS Physical Design and Signoff STA and Timing Closure Clock Architecture and CTS Floorplanning and Power Planning IR/EM Analysis Physical Verification SI/PI Analysis Low Power Design (UPF/CPF) Advanced Node Design Methodologies Tcl/Python/Scripting AI-assisted Design Flows (preferred) LEADERSHIP EXPECTATIONS Leads strategic technical initiatives across multiple IP programs. Mentors and develops engineering talent. Drives innovation that improves product competitiveness, engineering productivity, and design quality. EDUCATION BS/MS in Electrical Engineering, Computer Engineering, VLSI Design, or related field. #LI-PM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Staff Engineer Design", "company": "Infineon", "location": "Bangalore", "date_posted": "2026-07-23T06:23:52+00:00", "url": "https://jobs.infineon.com/careers/job/563808970807992", "is_hardware": true, "platform": "eightfold", "jd_text": "Candidate will be leading/involved in planning the modelling of analog /hard IP by means of Verilog and system Verilog. He is also expected to take part of development of modelling support pre-silicon validation.\n\nYour Role\n\nKey responsibilities in your new role\n\nCandidate will be leading/involved in planning the modelling of analog /hard IP by means of Verilog and system Verilog. He is also expected to take part of development of modelling support pre-silicon validation.\n\nMUST have:\nGood understanding of modelling technique for Analog Blocks using Verilog and System Verilog.\nGood exposure on digital verifications,\nAbility to interact and work with team member in multiple geography.\nGood exposure to dotlib generation.\nAdded advantage:Exposure to the MSV simulation flow.\nBasic understanding of analog circuits.\n\nYour Profile\n\nQualifications and skills to help you succeed\n\nBS/MS in Electrical Engineering\nBachelor's - 6 to 11 years’ experience, Master’s - 4 to 10 years’ experience.\nVery good knowledge of Verilog/System Verilog and UVM.\nShould be a good mentor and guide for junior engineers in the team.\nCandidate should have worked on AMS/Digital Block Modelling based RNM modelling.\nExposure to deployment of automation and formal verification methodologies is a plus.\n\nContact:\n    VidhiAshok.Thakkar@infineon.com\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\nThis means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.\nPlease let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.\nClick here for more information about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "PE- CPU Software & Hardware Co-Design Engineer (ML Systems)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-23T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719935379", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Software Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Software Engineer, you will design, develop, create, modify, and validate embedded and cloud edge software, applications, and/or specialized utility programs that launch cutting-edge, world class products that meet and exceed customer needs. Qualcomm Software Engineers collaborate with systems, hardware, architecture, test engineers, and other teams to design system-level software solutions and obtain information on performance requirements and interfaces.\n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 8+ years of Software Engineering or related work experience.\n                                                                    OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 7+ years of Software Engineering or related work experience.\n                                                                    OR\nPhD in Engineering, Information Systems, Computer Science, or related field and 6+ years of Software Engineering or related work experience.\n\n•    4+ years of work experience with Programming Language such as C, C++, Java, Python, etc.\n\nPreferred Qualifications:\n•    Master's Degree in Engineering, Information Systems, Computer Science or related field. \n•    15+ years of Software Engineering or related work experience. \n•    4+ years of experience with Database Management Software.   \n•    4+ years of experience with API.\n•    3+ years in a technical leadership role with or without direct reports.  \n•    3+ years of work experience in a role requiring interaction with executive leadership (e.g., Vice President level and above). \n•    1+ year of work experience with Git, Perforce, or Source Code Management System.\n\nPrincipal Duties and Responsibilities:\n•    Leverages expert Software knowledge and experience to design, develop, create, modify, and validate highly critical embedded and cloud edge software, applications, and/or specialized utility programs.\n•    Analyzes user needs, software requirements, and time and cost constraints to design and customize highly sophisticated software for optimal operational efficiency.\n•    Designs and implements software sub-systems for complex, large-scale products and systems; resolves design, coding, and other technical issues by presenting end-to-end solutions. \n•    Leads design, coding, and testing efforts to ensure that projects are completed to specifications and schedules.\n•    Serves as a technical expert in performing highly complex code reviews, regression tests, and triages and fixes issues to ensure the quality of code. \n•    Collaborates with high-level representatives from other functions (e.g., testing group, product group, customers) to integrate plan for software design of a large initiative.\n•    Writes detailed technical documentation for highly complex Software projects; reviews technical documentation for experienced engineers.\n\nLevel of Responsibility:\n•    Provides supervision to direct reports.  \n•    Decision-making is critical in nature and highly impacts program, product, or project success.\n•    Requires verbal and written communication skills to convey highly complex and/or detailed information. May require strong negotiation and influence with large groups or high-level constituents.\n•    Has a great degree of influence over key organizational decisions (e.g., is making or directly making key decisions that will have substantial impact over the organization).\n•    Tasks often require multiple steps which can be performed in various orders; extensive planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "IC Packaging Staff Engineer - Assembly process/Characterization", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-23T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446715698665", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nWe are looking for a highly motivated packaging engineer capable of leading state-of-the-art advanced IC packaging development and new product introduction of leading-edge package technologies for AI, Mobile, Bluetooth, WiFi, IoT, Power Management, Connectivity Automotive and new emerging markets and driving that innovation into high volume manufacturing in assembly suppliers. Extensive knowledge and experience in Flip Chip, Wire bond and System in Package assembly process, materials, and equipment are required. The position also requires the ability to lead multi-functional teams and solve complex technical problems in working with multiple OSATs. Experience or worked on projects with Wafer-on-Wafer bonding is a plus.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nDuties and Responsibilities:\nResponsible for exploring, development and HVM deployment of FCCSP, FCBGA, and/or SiP/Module packaging technologies.\n\nResponsible for initiating & defining package process flow, material set/ BKM, test vehicle, DOEs & cornering, process control plans to successfully develop manufacturable and reliable products.\n\nInterface with OSATs, substrate/ material suppliers, and tool makers in developing technology related to product requirements. Align with internal product teams on Design Rule and its establishment.\n\nAssociate with internal design team and drive DFM methodology for new technologies.\n\nWork with internal design, modeling and procurement teams to implement technically best and lowest cost packaging.\n\nTechnical program management to plan, execute, and monitor complex processes or product developments. Regular updates on program status to management and share with cross team members.\n\nGood knowledge and understanding of FMEA, SPC/QC concepts, failure mechanism and failure analysis process techniques, manufacturing floor operations and Quality issue handling.\n\nMinimum Qualifications\nMinimum of 10 years of experience in the development and high-volume manufacturing of advanced IC packages.\n\nExpertise in Flip Chip CSP, FCBGA and SiP packaging materials, assembly processes, equipment, and design rules.\n\nStrong understanding of Laser Groove technology and Wire bond process optimization.\n\nExcellent verbal and written communication skills. \n\nExhibit organized technical project management skills.\n\nAble to work independently and lead multiple programs.\n\nAble to lead multi-functional teams to solve complex technical problems.\n\nSelf-driven, passionate, and creative.\n\nPreferred Qualifications\nHands on experience in package manufacturing, experience in technical project management, and working first-hand with semiconductor material suppliers. \n\nUnderstanding industry packaging trends, end-user packaging considerations, and previous experience with high-end mobile consumer products. \n\nProficiency in material and package characterization and statistical data analysis.\n\nKnowledge of reliability test methods and qualification procedure.\n\nSix Sigma Green or Black belt a plus. \n\nEducational Requirements\nRequired: Bachelor’s degree in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, related degree or equivalent practical experience.\n\nPreferred: Master's degree or PhD in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, related Engineering field.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU Circuit Design Lead", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-07-23", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/CPU-Circuit-Design-Lead_JR0285850-1", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nYou will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for leading the design analysis and methodologies of the different types of memory blocks and data path subsystems. Your responsibilities will include but not limited to:\n1. Responsible for methodology enablement for memory blocks to meet over 5GHz Freq and low-power digital designs with optimal area.\n2. In depth understanding of different memory design concepts ((SRAM/RF/ROM).\n3. Expertise in Static timing analysis concepts.\n4. Close work with Layout and Floor planning teams.\n5. Back-end design implementation of new features.\n6. Expertise in Memory post silicon analysis.\n7. Good understanding of statistical variation.\n\nQualifications:\nYou must possess a Masters Degree in Electrical or Computer Engineering with atleast 8 or more years of experience in related field or a Bachelors Degree with atleast 10 years of experience. Technical Expertise in synthesis, P and R tools preferred.\nPreferred Qualifications:\n1. Digital Design Experience, with High Speed, Low Power.\n2. Familiarity with Verilog.\n3. Tcl, Perl, Python scripting.\n4. Good understanding of spice simulations and analysis\n5. Strong verbal and written communication skills.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "R&D Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-07-23", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/R-D-Engineer_R026551-6", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\n      As part of TLR team (top-level-route), R&D Engineer is primarily responsible for :-\n1) Place and Route, CTS, Routablity analysis with respect to congestion.\n2) Well versed in physical verification aspect, DRC, LVS, Antenna, LUP, ( chip finishing and Tapeout)\n3) Integration of analog blocks, Meeting RC requirements for manual/special signals\n4) Good understanding of calibre rule deck of DRC/LVS/DFM,DFY, ERC and ESD latchup.\n5) Responsible for all the integrity checks and post Tapeout eJob view release,\n6) Good scripting knowledge perl and TCL, familiar with caliber, Innovus,\n7) Understanding of VLSI fabrication process,\n8) Implementing timing ECOs. Implementing IR drop fixes, SPEF/GPD extraction, signal EM fixes, Noise analysis.\n9) Responsible for all the integrity checks and post Tapeout eJob view.\n10) Open to new responsibilities in context of  rapid technological change.\n11) Good communication skills, work closely with the team members to accomplish PD milestone.\n12) Secondary competencies :- Good understanding of CTS, STA, PTSI and timing.\nRelevant experience of CAD tools  cadence Innovus, Calibre is preferred.\nExperiance 4 to 8 years\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Senior Lead analog post-silicon validation engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-07-23", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Senior-Lead-analog-post-silicon-validation-engineer_R-10062167", "is_hardware": true, "platform": "workday", "jd_text": "Job Qualification\nBachelor’s or Master’s degree in Electronics Engineering.\n8+ years of experience in analog bench validation and characterization.\nStrong understanding of analog circuit fundamentals, including DC power consumption, gain, settling time, temperature coefficients, and DAC/ADC INL/DNL.\nExperience in silicon validation of analog blocks such as BGR, temperature sensors, ADCs, DACs, LDOs, and IO circuits.\nProficiency in bench automation techniques and tools such as MATLAB, Python, and LabVIEW.\nHands‑on experience debugging bench setups and developing instrument drivers.\nAbility to interpret datasheets, prepare comprehensive test plans, and characterize devices across PVT (Process corners, Voltage and  Temperature).\n Strong working knowledge of laboratory instruments including power supplies, DMMs, oscilloscopes, network analyzers, and spectrum analyzers.\nFamiliarity with automated data processing, plotting, and PCB design.\nExperience in validating digital IP such as Ethernet, SGMII, and other high‑speed serial interfaces, as well as mixed‑signal IPs and SoC IOs (preferred).\nExperience in Automotive and Ethernet‑based systems is an added advantage.\nExcellent verbal and written communication skills.\nJob responsibilities.\nCollaborate with the product definition and design teams prior to silicon availability to thoroughly understand validation requirements- covering device‑level, system‑level, and compliance specifications for Automotive Ethernet products.\nDefine and own the validation plan and schedule, ensuring comprehensive coverage across all use cases and corner conditions.\nDevelop efficient, reusable test methods and automation frameworks for validation setups.\nDesign and implement test hardware and automated test solutions using NI LabVIEW, TestStand, Python, and VBA.\nLead the development of scalable validation boards that meet stringent signal‑ and power‑integrity requirements.\nPerform parametric data collection across PVT corners using automation to execute the full validation plan.\nDrive reviews with extended teams for validation boards, test results, and debug activities, collaborating closely with cross‑functional groups.\nWork with cross‑functional teams (Systems, Applications, Test Engineering, Product Engineering, Quality) to support SoC/IP isue debugging, root‑cause analysis, and solution identification.\nAnalyze correlation between lab evaluation results and ATE test results, and work closely with test engineers to ensure comprehensive and accurate product validation.\nCreate validation plans based on product specifications and track progress through completion.\nDevelop validation boards and automated IC characterization programs for the product.\nDebug post‑silicon test failures with strong expertise in systematic root‑cause analysis.\nThe Analog Validation Engineer is responsible for assuring all instrumentation, scripting and boards are prepared prior to silicon arrival on the bench.\n\nMore information about NXP in India...\n\n#LI-7013", "jd_status": "stored"}, {"title": "SRAM Bitcell Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-07-23", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25016677", "is_hardware": true, "platform": "oracle", "jd_text": "We are seeking a Device/Circuit Engineer to join our SRAM bitcell development team. The ideal candidate will have a strong foundation in device physics and circuit design, with practical experience in advanced process technology. You will work alongside experienced engineers in a collaborative environment to design and optimize SRAM bitcells for implementation across multiple TI product lines.\n\nKey Responsibilities\n\nTechnical Execution:\n\nSupport the design and development of SRAM bitcells at advanced CMOS nodes\n\nExecute bitcell simulations and performance analysis under various PVT conditions\n\nAssist in defining and reviewing bitcell performance against specifications\n\nSupport qualification activities and reliability characterization\n\nProject Support\n\nContribute to project planning and track progress against milestones\n\nDocument design decisions and maintain project records\n\nSupport risk identification and mitigation activities\n\nMeet project deliverables and qualification standards\n\nCollaboration and Communication\n\nWork with senior engineers and SRAM circuit architecture teams on memory bitcell design\n\nCoordinate with process teams to understand technology constraints\n\nPresent technical findings and progress updates to team leads\n\nParticipate in design reviews and technical discussions\n\nLearning and Development\n\nStay current with industry trends in memory design and process technology\n\nActively seek feedback and mentorship from senior engineers\n\nContribute to process and design improvements\n\nQualifications\nEducation\n\nPh.D. in device physics, electrical engineering, or related field, OR\n\nMaster's degree in related field with 3+ years of relevant experience\n\nExperience\n\n0-2 years of professional experience in device/circuit design, process development, or SRAM design\n\nTechnical Skills\n\nWorking knowledge of SRAM bitcell design and basic circuit tradeoffs\n\nSolid understanding of MOSFET device physics fundamentals\n\nFamiliarity with advanced CMOS process technology\n\nProficiency in simulation tools (e.g., Cadence Virtuoso, SPICE, Sentaurus)\n\nPersonal Attributes\n\nStrong problem-solving and analytical skills\n\nExcellent written and verbal communication abilities\n\nAbility to work effectively in a team environment\n\nStrong time management and attention to detail\n\nWillingness to learn and take on challenging assignments\n\nDesirable\n\nInternship or co-op experience in semiconductor device/circuit design or process development\n\nExposure to reliability challenges at transistor and bitcell level (retention, soft errors)\n\nExperience with silicon characterization or measurement\n\nTrack record of delivering quality work on schedule\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Senior Digital Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-07-23", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505895", "is_hardware": true, "platform": "oracle", "jd_text": "We are looking to expand our team with a Senior Digital IC Design Engineer. You will help us develop IP for next generation Automotive, Industrial & Medical products. The successful candidate will participate in the design of complex mixed-signal IPs like DACs, ADCs, PLL and wireless interface etc. \n\nWhy Join Us\n\nWe create a diverse set of world-class products in a friendly and team-oriented atmosphere. We provide an environment of continual learning and growth opportunities and support volunteer & charitable programs. You will be able to build up a career in a successful international company, and you can participate in interesting international projects.\n\n#LI-RG1\n\nResponsibilities\nWhat You’ll Do\n\nDefine architecture and participate in feasibility studies for new analog/mixed-signal IP components\n\nDrive design and verification of state-of-the-art CMOS and SOI designs which can be reused across different market segments.\n\nLead small teams on sub-projects and contribute to SoC integration\n\nPropose innovative solutions to meet customer and product needs\n\nCollaborate on DFT strategies and document designs thoroughly\n\nPartner with test, product, and applications engineering to ensure successful production release\n\nDocumentation: including architecture and circuit descriptions, testing procedures, and safety mechanisms\n\n#LI-RG1\n\nQualifications\nWhat You’ll Need\n\nMinimum BS/MS in Electrical Engineering or related technical field\n\n4-6 years in ultra-low-power digital design using Verilog/System Verilog\n\nCapacity to think at the system level and to operate as a technical leader\n\nCreativity, dynamism, reliability and team spirit\n\nExcellent English written and verbal communication skills\n\nWhat Else You May Bring \n\nExperience in some of the following areas is a plus:\n\nKnowledge Verilog-A or VHDL-AMS.\n\nExperience with embedded CPUs (e.g. ARM Cortex, DSP), AMBA bus protocols (AHB/APB)\n\nExperience in ADC, DAC, PLL, power management systems\n\nProgramming in Python for automation and in C/C++ for embedded software\n\nDesign intent (timing constraints/SDC, power intent/UPF)\n\nDesign of accelerators and signal processing components\n\nRTL to GDS flow, including logic synthesis, place-and-route, STA, power analysis\n\nAdvanced digital verification methodology (e.g. UVM)\n\nKnowledge in Functional Safety\n\n #LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Staff Digital Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-07-23", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505896", "is_hardware": true, "platform": "oracle", "jd_text": "The Role\n\nWe are looking to expand our team with a Principal Digital IC Design Engineer. You will help us develop IP for next generation Automotive, Industrial & Medical products. The successful candidate will participate in the design of complex mixed-signal IPs like DACs, ADCs, PLL and wireless interface etc. \n\nWhy Join Us\n\nWe create a diverse set of world-class products in a friendly and team-oriented atmosphere. We provide an environment of continual learning and growth opportunities and support volunteer & charitable programs. You will be able to build up a career in a successful international company, and you can participate in interesting international projects.\n\n#LI-RG1\n\nResponsibilities\nWhat You’ll Do\n\nDefine architecture and participate in feasibility studies for new analog/mixed-signal IP components\n\nDrive design and verification of state-of-the-art CMOS and SOI designs which can be reused across different market segments.\n\nLead small teams on sub-projects and contribute to SoC integration\n\nPropose innovative solutions to meet customer and product needs\n\nCollaborate on DFT strategies and document designs thoroughly\n\nPartner with test, product, and applications engineering to ensure successful production release\n\nDocumentation: including architecture and circuit descriptions, testing procedures, and safety mechanisms.\n\n#LI-RG1\n\nQualifications\nQualifications\n\nWhat You’ll Need\n\nMinimum BS/MS in Electrical Engineering or related technical field\n\n10 years in ultra-low-power digital design using Verilog/System Verilog\n\nCapacity to think at the system level and to operate as a technical leader\n\nCreativity, dynamism, reliability and team spirit\n\nExcellent English written and verbal communication skills\n\nWhat Else You May Bring \n\nExperience in some of the following areas is a plus:\n\nKnowledge Verilog-A or VHDL-AMS.\n\nExperience with embedded CPUs (e.g. ARM Cortex, DSP), AMBA bus protocols (AHB/APB)\n\nExperience in ADC, DAC, PLL, power management systems\n\nProgramming in Python for automation and in C/C++ for embedded software\n\nDesign intent (timing constraints/SDC, power intent/UPF)\n\nDesign of accelerators and signal processing components\n\nRTL to GDS flow, including logic synthesis, place-and-route, STA, power analysis\n\nAdvanced digital verification methodology (e.g. UVM)\n\nKnowledge in Functional Safety\n\n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "R&D Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-07-23", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/R-D-Engineer_R026553-6", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\n      As part of TLR team (top-level-route), R&D Engineer is primarily responsible for :-\n1) Place and Route, CTS, Routablity analysis with respect to congestion.\n2) Well versed in physical verification aspect, DRC, LVS, Antenna, LUP, ( chip finishing and Tapeout)\n3) Integration of analog blocks, Meeting RC requirements for manual/special signals\n4) Good understanding of calibre rule deck of DRC/LVS/DFM,DFY, ERC and ESD latchup.\n5) Responsible for all the integrity checks and post Tapeout eJob view.\n6) Good scripting knowledge perl and TCL, familiar with caliber, Innovus,\n7) Understanding of VLSI fabrication process,\n8) Implementing timing ECOs. Implementing IR drop fixes, SPEF extraction, signal EM fixes, Noise analysis.\n9) Responsible for all the integrity checks and post Tapeout eJob view release,\n10) Open to new responsibilities in context of  rapid technological change.\n11) Good communication skills, work closely with the team members to accomplish PD milestone.\n12) Secondary competencies :- Good understanding of CTS, STA, PTSI and timing.\nRelevant experience of CAD tools  cadence Innovus, Calibre is preferred.\nExperiance - 4 to 10 years\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "IO and Mixed Signal Circuit Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-07-23", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/IO-and-Mixed-Signal-Circuit-Design-Engineer_R026568", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nWork as part of Mixed Signal and IO Library Development team in Central Engineering. Primary responsibilities include:\nDesign and verification of IO interfaces and mixed signal blocks such as POR, process monitors, voltage/temperature sensors, crystal oscillators etc.\nRTL coding, synthesis and verification of digital wrappers that interface with analog circuitry\nInterface with both custom and P&R layout engineers and oversee physical design and verification.\nDevelop functional models and perform timing characterization of these cells.\nDirectly interface with end customers to understand their requirements, come up with specifications and implement circuit designs that support them.\nCreate necessary infrastructure and generate test vectors to support silicon validation of these blocks on test chips.\nWork with test engineers to support silicon validation either on ATE or on the bench.\nDevelop accurate documentation in the form of datasheets, application notes and integration guides\n\nSkills and Qualifications Required:\nEducational requirements: MSEE with a minimum of 5-10 years of hands-on experience in independently designing mixed signal circuits especially in newer CMOS technologies such as 5nm or 3nm\nMust have experience in designing analog circuits such as PLLs, LDOs, Bandgap references, ADCs or DACs--knowledge of AMS methodology and analog circuit modeling will be a plus\nMust be proficient with Cadence Virtuoso Schematic Capture and ADE along with an excellent knowledge of spice based simulators such as Spectre and/or Hspice\nWorking knowledge of LVS, DRC along with EM/ESD verification tools such as Totem/Pathfinder/PER\nStrong written and oral communication skills in English to be able to work effectively across geographies as well as to be able to interface with end customers\nRequire proficiency in automation using shell scripting or any other languages such as SED, AWK, TCL or PERLˇ\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "UCIe/D2D Post Si Validation Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-07-23", "url": "https://careers.arm.com/job/bengaluru/ucie-d2d-post-si-validation-engineer/33099/98165857552", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Description: D2D/UCIe Functional Validation Engineer\nRole Overview\nWe are looking for a Die-to-Die (D2D)/UCIe Functional Validation Engineer with 3 to 8 years of experience in silicon validation, high-speed interface validation, firmware-based validation, and system-level debug.\nThe candidate will be responsible for validating UCIe-based die-to-die interfaces operating at various UCIe 1.1 Spec defined data rates on complex multi-die and chiplet-based SoC platforms. The role involves validation of the UCIe PHY, Adapter, protocol stack, sideband interface, link initialization, training, reliability mechanisms, power-management flows, and end-to-end data transfer between dies.\nThe engineer will develop and execute validation plans, create test cases, support pre-silicon and post-silicon bring-up, debug complex link failures, and collaborate with architecture, design, PHY, firmware, packaging, signal integrity, and platform teams.\nThe ideal candidate should have a strong understanding of high-speed serial or parallel interfaces, UCIe architecture, die-to-die communication, PHY training, firmware-controlled link initialization, and silicon debug methodologies.\nKey Responsibilities\nPerform functional validation of UCIe-based D2D interfaces on pre-silicon and post-silicon platforms.\nValidate UCIe links operating at 8, 16, 24, 32 GT/s  etc., per lane across supported link widths and package configurations.\nDevelop, enhance, and maintain validation test plans and test cases for the UCIe PHY, Adapter, protocol layer, sideband interface, and end-to-end data paths.\nSupport silicon and platform bring-up, including reset sequencing, clock initialization, PHY initialization, link training, parameter exchange, transition to mission mode, and traffic enablement.\nValidate UCIe link initialization and training across all supported speeds, widths, lane configurations, voltage conditions, temperature conditions, and process corners.\nVerify speed negotiation, link-width negotiation, lane mapping, lane reversal, lane disablement, lane repair, spare-lane usage, and link retraining mechanisms.\nValidate UCIe protocol mappings such as PCIe, CXL, streaming, and raw-mode traffic, where applicable to the platform.\nValidate interfaces between the UCIe Adapter and protocol or logic layers, including RDI, FDI, or equivalent implementation-specific interfaces.\nDevelop and execute end-to-end traffic tests between chiplets using register accesses, memory transactions, DMA traffic, streaming traffic, cache-coherent traffic, and platform-specific protocols.\nValidate bidirectional and simultaneous traffic across multiple D2D links and chiplets.\nVerify protocol reliability mechanisms, including CRC checking, retry, replay, error detection, error reporting, link recovery, and data integrity.\nValidate sideband communication, initialization messages, management transactions, reset handshakes, error notifications, and power-management messages.\nValidate link state transitions, including initialization, active operation, retraining, recovery, low-power entry and exit, reset, and link shutdown.\nValidate warm reset, cold reset, link reset, die reset, firmware restart, surprise reset, and error-recovery scenarios.\nPerform negative testing by injecting protocol, PHY, lane, CRC, timeout, malformed packet, retry, replay, and sideband errors.\nValidate link behavior under lane failures, marginal lanes, degraded channel conditions, clock disturbances, voltage variations, and thermal stress.\nCharacterize link stability, BER, eye margins, timing margins, voltage margins, lane-to-lane skew, jitter tolerance, and long-duration reliability.\nExecute stress scenarios involving maximum bandwidth, bidirectional traffic, multi-link concurrency, repeated retraining, reset loops, power-state transitions, and thermal or voltage stress.\nMeasure bandwidth, latency, protocol efficiency, utilization, retry overhead, and performance scaling across different speeds and link widths.\nDevelop and debug low-level firmware for UCIe initialization, PHY configuration, link training, register programming, error injection, traffic generation, and status monitoring.\nDevelop bare-metal tests and firmware-based validation sequences for early silicon bring-up.\nDevelop automation scripts for test execution, configuration sweeps, register dumps, log parsing, failure detection, and result analysis.\nDebug silicon failures using firmware logs, PHY logs, protocol traces, register dumps, waveform captures, scan dumps, counters, and platform telemetry.\nUse oscilloscopes, BERTs, logic analyzers, protocol analyzers, JTAG debuggers, and other lab equipment to analyze D2D link behavior.\nWork closely with architecture, RTL design, verification, PHY, firmware, packaging, signal integrity, power, clocking, and platform teams to identify root causes and drive issues to closure.\nParticipate in reviews of UCIe architecture, PHY behavior, Adapter functionality, protocol flows, register definitions, firmware sequences, and validation coverage.\nCreate and maintain validation documentation, including test plans, test-case specifications, bring-up checklists, debug guides, issue reports, coverage reports, and execution summaries.\nTrack validation progress, report risks and blockers, and support defect triage through Jira, Bugzilla, or equivalent issue-management systems.\nImprove validation infrastructure, automation frameworks, regression environments, debug tools, and coverage methodology.\n\n#LI-PS2\n \nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\n\nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Engineer ", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-07-22T12:15:03+00:00", "url": "https://jobs.infineon.com/careers/job/563808971773338", "is_hardware": true, "platform": "eightfold", "jd_text": "We are seeking a Circuit Simulation Specialist with strong electronics fundamentals, SPICE simulation expertise, and proficiency in Python & Git to join our engineering team.\n\nYour role\nKey responsibilities in your new role\n\nSimulate and validate electronic circuit designs using SPICE tools\n\nAnalyze waveforms and interpret simulation results\n\nMaintain product libraries and technical databases\n\nAutomate processes using Python scripts\n\nManage repositories through GitLab\n\nCollaborate with R&D, Product Management, and Marketing teams to improve engineering tools and workflows\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor's/Master's degree in Electrical Engineering, Electronics, or a related field\n\n5+ years of work experience and strong understanding of electronic components, circuit theory, and waveform analysis\n\n Hands-on experience with SPICE tools (LTspice, Simulink, or similar)\n\n Experience in circuit modeling, simulation, and validation\n\nProficiency in Python for automation and workflow enhancement\n\nWorking knowledge of Git/GitLab for version control and collaboration\n\nFamiliarity with analog and digital circuit design principles\n\nAbility to create component libraries, simulation profiles, and troubleshoot simulation issues\n\nStrong communication and cross-functional collaboration skills\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nKeerthini M H", "jd_status": "stored"}, {"title": "Physical Design Lead", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-07-22T11:53:00+00:00", "url": "https://global-external-amd.icims.com/jobs/88448/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. SMTS SILICON DESIGN ENGINEER THE ROLE: As a member of the CT India physical design team, you will help bring to life cutting-edge designs. As a member and lead of the Physical design implementation team, you will work closely with the SOC architects, Physical design architects, design leads, IP teams, Physical Design leads and PD/STA engineers to achieve first-pass silicon success. You will be expected to lead design implementation and convergence activities in the backend from a PnR implementation perspective. In this position as a Physical Design Expert, you will be part of a world-class team developing groundbreaking high-performance IP, Test chip and Chiplet designs . This is a great opportunity to join a talented team that is well-invested in the implementation of futuristic designs in advanced process nodes. THE PERSON: You will be responsible for driving a team of silicon design engineers for the successful delivery of project tape-outs from RTL-GDS. You will use your knowledge of Physical design to lead a complete set of Backend activities, Specifically PnR, timing, verification and signoff including IP integration and full-chip aspects. This position requires a detail-oriented candidate, who possesses good communication skills and can handle/work with teams. KEY RESPONSIBILITIES: Lead Physical design team for implementation and convergence of highly complex tiles Will be responsible for delivery of GDS starting from RTL including Signoff and physical verification. Collaborate with cross-functional teams to drive continuous improvements for achieving better PPA. Good understanding of horizontal sign-off flows like VCLP, Formal Equivalence, Low Power Checks, timing convergence (both tile-level and FCT), and full chip integration flows. Understanding design requirements, timelines and various milestones of a project and tracking project convergence status accordingly covering all aspects of the design cycle. Drive methodology development ideas/forums. Collaborate with CAD and EDA vendors to further strengthen AMD and PD closure methodology. Provide technical direction, guidance, and Support to the engineering team. PREFERRED EXPERIENCE: Experienced PD professional with a minimum of 15 years of industry experience in the Physical design domain (RTL to GDS, STA, Physical verification, timing signoff, tapeout). Block-level implementation (Place and Route), which includes Floorplanning, Timing Closure and Physical Verification. Well-versed with Physical Design verification signoff techniques such as Formal equivalence, IR&EM, Timing Closure (STA), Physical verification, VSI, Formal Equivalence Check or LEC, etc. Good understanding of Power, Performance and Area (PPA) optimization techniques. Good experience with Perl/TCL/Shell/Python scripting, and Verilog/VHDL RTL design. Excellent presentation and inter-communication skills. Qualifications: B.Tech/M.Tech/MS/Ph.D. in Computer/Electronics/Electrical Engineering. Candidate must have the ability to drive/manage projects from RTL to GDS, with a minimum experience of managing more than 4 tape-outs. Proficient in physical design industry-standard EDA tools like Fusion compiler/ICC2/Primetime/Redhawk/PTPX, low power and physical verification tools. #LI-SS1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Engineer - ATE Test Engineering", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-07-22T06:15:00+00:00", "url": "https://jobs.infineon.com/careers/job/563808971773329", "is_hardware": true, "platform": "eightfold", "jd_text": "#WeAreIn\nto be the quality gate for our products. Are you in?\n \nJoin the thinkers, builders, and problem-solvers behind tomorrow’s technology.\nAs\na ATE Test Engineer in our Research & Development team, you'll have the opportunity\nto lead and support IoT NPI products Silicon bring-up and production. \n\nAre you in?\n\nYour role\nKey responsibilities in your new role\n\nDevelop\nand document a test plan for new IoT devices.\nDesign\nand debug ATE Test Hardware and Software Production & Reliability. \nDebug\nnew silicon on Automated Test Equipment. \nBring\na quality and cost-effective Test solution for mass production. \nOversee\ntest-related activities (HW & SW) with both internal and external test\nhouses.\nImplement\nTest programs, modify, and release into offsite production.\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor's\n/ Master's Degree in Electronics and Communication OR Bachelor's / Master's\nDegree in Electrical and Electronics.\n\nGood\nunderstanding of semiconductor device fundamentals (Analog/Digital and Circuit\nTheory).\n\nSound\nunderstanding of Semiconductor Design for Test (DFT) techniques such as ATPG\nand PMU blocks like BUCLK and LDO’s with Trimming procedure.\n\nExpertise\nin Semiconductor Testing Methodology, using Teradyne-Ultraflex-RF. Ultraflex +\nis an added advantage. \n\nGood\nprogramming skills in writing and debugging test programs and ATE\nhardware-related issues.\n\nProvide\ntest engineering expertise and troubleshooting support to both internal and\nexternal customers\n\nCompetency\nin programming with Scripting languages (ie., Perl/Python) and high-level\nlanguages (i.e. C/C++, JAVA, Visual Basic).\n\nDevelop\nand debug characterization and production test programs for IoT products (BT,\nBLE, Wi-Fi) on digital/Mixed signal/PMU/RF blocks.\n\nCross-functionally\ncollaborate with project team members across development sites and product\nroles of IP design, applications, DFT, Product engineering, and Test\nengineering.\n\nGood verbal and written communication skills are expected.\n\nFamiliar\nwith UNIX/LINUX environment, commands, and shell scripts.\n\nGood\nteam player, attitude, and thirst for continuous learning Leadership.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Senior Signal Integrity Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-07-22T04:04:00+00:00", "url": "https://global-external-amd.icims.com/jobs/88735/login", "is_hardware": true, "platform": "jibe", "jd_text": "ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. The Role:  We are seeking a seasoned Signal and Power Integrity Engineer with expertise or significant interest in System SIPI. As a member of this team you will ensure the performance requirements of the silicon and the cost requirements of the product are met through the integration of silicon, package and platform electrical design. Packaging Signal Integrity also provides design support to engineering design teams for both current and forward-looking product development and feasibility studies. The Person:  The ideal candidate has the ability to communicate effectively and work in close collaboration with others in AMD as well as with AMD’s customers to ensure optimal engineering design decisions and efficient problem solving, Candidate need to collaborate and work harmoniously with others, while maintaining the ability to work independently.   Key Responsibilities:  Responsible for Signal Integrity and Power Integrity simulations at feasibility, pre-layout, post-layout phases of AECG characterization board and demo board design. Establish design and layout guidelines. Responsible for coordinating with HW design team, layout team, NPI and manufacturing vendors to resolve SI/PI related issues. Responsible for end-to-end channel simulations for multi gigabit serial lines like 56Gbps, 112Gbps and beyond. Responsible for PI analysis simulations of HBM/ /DDR4/LPDDR4/DDR5/LPDDR5 and other memory buses. Responsible for characterizing the various interfaces in the product and verifying the simulations against measurements. Responsible for preparation of and implementing checklists for various stages of PCB development. Worked with architecture team, package design team and PCB design team for future PCB technology. Update the SIPI design and analysis flow and automate the process. Preferred Experience:  8+ years of professional experience as Signal and Power Integrity Engineer Excellent analytical and problem-solving skills along with attention to details Must be a self-starter, able to drive tasks independently and efficiently to completion Strong/effective communication skills Enthusiastic team-first mentality Experience with PCB, Package and IC level power delivery networks  Experience in silicon packaging and PCB design for signal and power integrity  Experience with high-speed digital signaling interfaces such as PCIE, DDR5/DDR6, HDMI  Expertise in electrical modeling EDA and AMS tools such as HFSS, SIwave, HSPICE  Expertise in electromagnetic theory and circuit analysis Academic Credentials:  Undergrad/ Masters in Electrical or Electronics Engineering #LI-PK2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "SRAM Bitcell Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-07-22", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25016644", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n   \n\nWe are seeking a Senior Device/Circuit Engineer to lead SRAM bitcell development and drive innovation across advanced CMOS technology nodes. The ideal candidate will bring deep expertise in device physics, circuit design, and process technology, combined with proven technical leadership and project management skills. You will spearhead the design and optimization of next-generation SRAM bitcells for implementation across multiple TI product lines.\n\n \n\nKey Responsibilities\n\nTechnical Leadership:\n\ndesign, development, and implementation of SRAM bitcells at advanced CMOS nodes\n\nDefine and establish bitcell performance specifications and qualification requirements\n\nLead innovation initiatives in process technology and circuit design to achieve best-in-class memory performance and yield metrics\n\nConduct detailed technical reviews and provide guidance on design tradeoffs and optimization strategies\n\nEstablish design methodologies, standards, and best practices for the team\n\nProject Management\n\nPlan, manage, and oversee project schedules, deliverables, and milestones for multiple concurrent SRAM development projects\n\nEnsure bitcell specifications meet customer requirements, project deadlines, and qualification standards\n\nIdentify, assess, and mitigate process and design risks across PVT and manufacturing variations\n\nDrive timely resolution of technical issues and roadblocks\n\nManage engineering resources and prioritize work across competing objectives\n\nCollaboration and Communication\n\nPartner with SRAM circuit architecture and SoC teams to align memory bitcell goals with system-level requirements\n\nInterface with process technology teams and fab partners to develop and optimize technology to meet specifications\n\nPresent strategic project updates, technical reviews, and comprehensive status reports to senior management and stakeholders\n\nBuild and maintain strong relationships with internal and external technical teams\n\nChampion cross-functional collaboration and knowledge sharing\n\nInnovation, Mentorship, and Continuous Improvement\n\nDrive a culture of continuous improvement in process development, device optimization, design methodologies, and engineering workflows\n\nStay at the forefront of industry trends, emerging technologies, and best practices in memory design and process technology\n\nMentor junior engineers, fostering their technical development and career growth\n\nLead technology roadmapping and strategic planning for next-generation SRAM solutions\n\nContribute to technical publications, patents, and industry engagement\n\nQualifications\nQualifications\n\nEducation\n\nPh.D. in device physics, electrical engineering, semiconductor physics, memory technologies, or related field with 3+ years of experience, OR\n\nMaster's degree in related field with 6+ years of industry experience in process development or SRAM design\n\nExperience\n\n6+ years of professional experience in device/circuit design, process technology development, or SRAM bitcell design at advanced nodes\n\nTechnical Skills\n\nExpert-level understanding of SRAM bitcell design, performance metrics, and critical tradeoffs\n\nDeep knowledge of scaled MOSFET device physics, including short-channel effects and advanced phenomena\n\nComprehensive expertise in advanced CMOS process technology development (28nm and below)\n\nAdvanced proficiency in simulation tools (Cadence Virtuoso, SPICE, Sentaurus) and device modeling\n\nStrong background in design verification, characterization methodologies, and test development\n\nLeadership and Management Skills\n\nProven track record of technical leadership on complex, multi-faceted projects\n\nExcellent project management, organizational, and problem-solving skills\n\nDemonstrated ability to mentor and develop engineering teams\n\nExceptional interpersonal and communication skills (written and verbal)\n\nDesirable\n\nSignificant fab experience (process integration, device development, manufacturing) with advanced CMOS technology from development through production\n\nDeep knowledge of reliability challenges at transistor and bitcell level (retention time, soft errors, BTI, hot carrier effects)\n\nExtensive silicon characterization and silicon-to-model correlation experience\n\nPublished technical papers or patents in semiconductor device/memory design\n\nExperience with yield analysis and Design-for-Yield (DFY) methodologies\n\nBackground in technology road mapping and strategic planning\n\nExperience with advanced process integration challenges at scaled nodes\n\nStrong track record of driving innovation and process/design improvements with measurable impact\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Principal Engineer-High Speed Interface Pre-Silicon Validation/Verification", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-07-22", "url": "https://careers.synopsys.com/job/bengaluru/principal-engineer-high-speed-interface-pre-silicon-validation-verification/44408/88155157664", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Title:\nPrincipal Engineer-High Speed Interface Pre-Silicon Validation/Verification\n \nWe Are:\n \n At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\n \n You Are:\n \n You are a driven and insightful Emulation Expert, passionate about pushing the boundaries of what's possible in ASIC digital design. With a deep understanding of IP interfaces--especially PCIe and DDR--you are skilled in leveraging advanced emulation platforms like Zebu to accelerate verification and product development. Your career is marked by a proven ability to deliver robust, production-ready IP through rigorous emulation and verification cycles. You thrive in highly collaborative, matrixed, and international environments, bringing together diverse teams and perspectives to solve complex challenges.\n \n Your hands-on approach and proactive attitude make you a go-to resource for bridging gaps between Emulation IP and Design IP, ensuring seamless integration and verification of both Controller and PHY components. You have a keen eye for detail and are committed to right-first-time development, always ensuring traceability and completeness across verification requirements. You stay ahead of industry trends, standards, and evolving technologies, and are adept at translating these into actionable insights for your teams. As an excellent communicator and natural collaborator, you are comfortable working with multiple stakeholders and driving change within the organization. Your adaptability, resilience, and commitment to continuous learning set you apart as a leader in your field.\n \n What You'll Be Doing:\n \n  * Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.\n  * Reporting key metrics and driving continuous improvement initiatives in Emulation IP quality and performance.\n  * Providing technical leadership and expertise to define requirements for Emulation IP, ensuring its correct implementation and deployment within verification strategies.\n  * Staying ahead of evolving industry standards, interpreting future changes, ECNs, and specification errata, and integrating this knowledge into Emulation and Design IP teams.\n  * Reviewing and validating test plans for both Emulation IP and Design IP, guaranteeing best-in-class function, feature coverage, and product quality.\n * Collaborating cross-functionally to optimize workflows, standardize methodologies, and ensure compliance with organizational goals.\n  * Mentoring and guiding junior engineers, fostering a culture of innovation and continuous improvement.\n \n The Impact You Will Have:\n \n * Enhancing cross-functional collaboration to elevate product quality and end-customer satisfaction.\n * Transforming the approach to Emulation IP usage in validating cutting-edge digital designs and system architectures.\n  * Driving innovation by defining and refining requirements for IP product development, particularly in emulation contexts.\n  * Championing the adoption of best-in-class verification methodologies across the organization.\n  * Standardizing and optimizing verification workflows to boost efficiency, traceability, and compliance.\n  * Influencing the next generation of emulation and verification solutions, positioning Synopsys as an industry leader.\n * Accelerating time-to-market for high-performance silicon solutions through advanced emulation strategies.\n \n What You'll Need:\n \n  * 15+ years of relevant experience in emulation, verification, or IP product development.\n  * Expert-level knowledge of PCIe/ DDR / Ethernet interfaces, including protocol and verification strategies.\n  * Extensive hands-on experience with Zebu or similar emulation platforms, particularly for IP verification.\n  * Demonstrated track record in leading IP product development initiatives with a focus on emulation.\n * Strong background in cross-functional collaboration, with an ability to drive consensus and deliver results.\n  * Outstanding communication skills, with the ability to influence and inspire change across diverse teams.\n  * Adaptability and comfort working in a fast-paced, matrixed, and international environment.\n \n Who You Are:\n \n  * A proactive and collaborative problem-solver with a passion for excellence.\n  * Innovative thinker who embraces change and seeks out opportunities for continuous improvement.\n  * Strong communicator, able to articulate complex technical concepts to diverse audiences.\n  * Resilient and adaptable, thriving in dynamic environments and embracing new challenges.\n  * Committed to mentoring others and fostering an inclusive, team-oriented culture.\n \n The Team You'll Be a Part Of:\n \n You will join a dynamic, high-performing engineering team focused on IP development, emulation, and verification at the forefront of semiconductor innovation. Our team is collaborative, cross-functional, and globally distributed, working together to solve complex challenges and deliver industry-leading solutions. You will have the opportunity to collaborate with experts across multiple domains, drive impactful initiatives, and shape the future of digital design and verification at Synopsys.\n \n Rewards and Benefits:\n \n  We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process", "jd_status": "stored"}, {"title": "Design Verification Manager, SSG", "company": "Amazon", "location": "Bengaluru, Karnataka, IND", "date_posted": "2026-07-22", "url": "https://www.amazon.jobs/en/jobs/10481539/design-verification-manager-ssg", "is_hardware": true, "platform": "amazon", "jd_text": "As a Design Verification Manager, you will contribute to exploring innovative hardware designs to enhance our devices. You will define verification methodology and implement test plans for advanced functional blocks while collaborating with cross-functional teams to develop world-class hardware devices.  You will participate in the bringup of such blocks on Simulation and Emulation platforms.\n\nYou will work closely with multi-disciplinary groups including Architecture, RTL Design, PD, Validation, Software and Product Design to architect and implement verification environments for complex functional block that enable development of world-class hardware devices. In this role, you will:\n\n• Architect and implement verification environments for complex functional blocks\n• Create and enhance verification environments using SystemVerilog and UVM\n• Develop comprehensive test plans through collaboration with design engineers, SW and architects\n• Implement coverage measures for stimulus and corner-case scenarios\n• Participate in test plan and coverage reviews\n• Drive complex RTL and TB debugs\n• Drive UPF based low power verification\n• Contribute to verification activities across simulation and emulation platforms\n• Work on creating the automation scripts to support DV methodologies\n• Create infrastructure to performs system level performance analysis\n• Manage a team of 6-8 DV Engineers\n\nBasic qualifications\n- Bachelor's degree in electrical engineering, computer engineering, or equivalent\n- Experience using multiple verification platforms: UVM test bench, FPGA, emulator, software environments, and system testing\n- Experience with test plan development, building the necessary test bench infrastructure, developing tests and verifying the design\n- Knowledge of computer science fundamentals in object-oriented design\n- 10+ years or more of practical semiconductor ASIC experience including owning end to end DV of major SOC blocks\n- Managing a team of DV Engineers\n- Experience with RTL development environments\n- Proficiency in hardware description languages and verification methodologies\n- Experience verifying complex IP blocks integrated into SOCs\n- Experience with industry-standard tools and scripting languages (Python or Perl)\n\nPreferred qualifications\n- Advanced degree in computer science, electrical engineering, or related field\n- Experience in system-level debugging\n- Knowledge of SoC architecture\n- Experience in oral and written communication\n- Experience with ARM and DSP instruction set architectures\n- Strong programming skills in SV, UVM and C Knowledge of AMBA bus protocols\n- Experience with formal verification methods Experience with Low power verification methods\n- Experience with Baremetal processor environments\n- Transaction level modelling expertise\n- Familiarity with industry standard I/O interfaces\n- FPGA and emulation platform knowledge\n\nOur inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "jd_status": "stored"}, {"title": "Post-Silicon Debug Tools Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-07-22", "url": "https://careers.arm.com/job/bengaluru/post-silicon-debug-tools-engineer/33099/98140446704", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview:\nWe are seeking a Post-Silicon Debug Tools Engineer to define and drive the next generation of silicon debug tools! In this role you will drive architecture, development, deployment and support of scan and memory extraction tools for system debug environment. The ideal candidate combines outstanding Python software-development skills with a strong technical expertise in memory and scan DFT and debug architecture.\n\nResponsibilities:\nLead the architecture and development of scan and memory extraction post-silicon debug tools as a part of a larger SoC debug toolkit.\nActively collaborate with DFT architecture and design teams to deliver debug tools that communicate with pioneering DFT hardware for system debug use cases.\nDefine and develop debug solutions that integrate scan and memory dump flows into larger silicon debug toolkit.\nPartner with silicon verification teams for end-to-end debug flow validation of scan and memory debug tools in simulation and emulation environments.\nProvide training and support to post-silicon debug teams employing debug tools for issue root-cause and analysis.\nChampion automation, reuse, and scalable debug methodologies that reduce time-to-root-cause.\nInfluence next-generation silicon architecture to ensure test and debug features are designed for observability and diagnosability.\nRequired Skills and Experience :\nBS/MS in Electrical Engineering, Computer Engineering, or related field.\n6+ years of experience in post-silicon validation, debug tools, or SoC bring-up.\nExcellent proficiency with Python language for tool and automation development.\nCompetency in software development concepts including unit testing, code coverage collection, release processes and CI/CD pipelines.\nFamiliarity with Git, Gerrit, Artifactory and CloudBees platform\nStrong understanding of JTAG, trace, scan, MBIST, and on-chip debug architectures.\nFamiliarity with SoC debug ecosystems (CoreSight, IJTAG, ELA, telemetry frameworks, etc.).\nProven track record in collaboration across hardware, software, and validation teams in a fast-paced environment.\n“Nice To Have” Skills and Experience :\nStrong communication skills and proven track record of collaboration with multi-functional and multi-site teams\nIn Return:\nTo join a newly forming Solution Engineering SoC architecture team with significant opportunities to impact the shape, definition, and culture of the team and help build our future success! This will be a fast paced and exciting environment with opportunities to demonstrate your strategic and innovative thinking while directly chipping in to current projects.\nPartner and customer focus\nCollaboration and communication\nCreativity and innovation\nTeam and personal development\n#LI-SC2\nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Sr Application Engineer – GCS ( Virtuoso )", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-07-22", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Sr-Application-Engineer---GCS---Virtuoso--_R53760", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Description\n\nJob Title: Sr Application Engineer – GCS\nWork location : Bangalore\nWork Experience : 2-5 Years or relevant years of experience\nQualifications : BE/BTech/ME/MS/MTech in Electrical/Electronic or equivalent\n\nCadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware, and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications, including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial, and health.\n\nThe Cadence Advantage\n\n· The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, and innovative, and to make an impact.\n· Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of the specific needs of the employees.\n· The unique “One Cadence – One Team” culture builds and fosters diversity, equity, and inclusion to maximize our ability to innovate, drive growth, and win with our customers. Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization.\n· Multiple avenues of learning and development available for employees to explore as per their specific requirements and interests\n· You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.\n\nJob Summary\n\nASK provides remote technical support to WW customers of Cadence in all its Software products. Application Engineers apply their expertise and debugging skills to resolve customer issues quickly, collaborate with R&D to ensure bug fixes, and create technical artifacts for Cadence Support Portal to enable customer self-help. The role requires continuous learning, excellent problem-solving, and communication skills.\nAs a member of the ASK Organization for the Custom IC & Simulation group, you will partner with worldwide Cadence customers to provide post-sales technical consultation for Custom IC domain products involving Front End (Design Editing, Netlisting, Simulation), Back End (Layout Generation, Placement and Routing, Verifying), Design Porting, Tool Setup, and Customization for implementing cutting-edge designs.\nThis involves working closely with the customers to understand and debug complex issues enabling them to proceed further with design cycle phases, helping them leverage the latest tool capabilities, and guiding them with the implementation of software in their design methodologies. You will have an opportunity to acquire both breadth and depth of technical knowledge, get wide exposure to the latest design practices in the industry, and demonstrate expertise by authoring high-impact knowledge content.\nThis role also provides an opportunity to participate in the evolution of key technology solutions to the most pressing design problems. In this role, you will have the opportunity to work with product teams to identify and prioritize product improvement initiatives with your timely feedback and observations.\nThis an excellent opportunity to work in a supportive, flexible, and friendly work environment that ASK offers, where we are vested in each other’s success, and are passionate about technology and innovation.\n\nJob Responsibilities\n\nDuties include but are not limited to assisting customers with flow-setup, queries, and issues raised by them, working with Product R&D on defects and enhancements, and creating a knowledge database for Cadence Online Support customers on common problems and solutions. The goal is to provide a superior Support experience to Cadence customers. Additional responsibilities include working on various company projects that require excellent teaming skills and the ability to work across functional areas to optimize the support flow.\n\nQualifications\n\n· Bachelor/Master/PhD’s Degree in Electrical / Electronics / Electronics and Communication / Embedded System Engineering with 4-7 years of related experience.\nExperience and Technical Skills required\n· Applicable experience includes working product knowledge of Virtuoso Schematic Editor (L/XL), Virtuoso Analog Design Environment (Explorer, Assembler), Virtuoso Layout Suite (L/XL/GXL), Design Framework (DFII) Environment and Various Translators, Any Spice Simulator, PCells, OpenAccess, Installation and Licensing, Technology file, SKILL, and Customization, Standard Cell or Library Characterization, Mixed Signal Simulation etc. Working knowledge & Hands on experience of Cadence or competitor or in-house EDA tools; technical customer support problem-solving experience is a must.\n· Must have excellent debugging skills and the ability to separate critical issues from trivial ones.\n\nBehavioral skills required\n\n· Must possess strong written, verbal, and presentation skills.\n· Ability to establish a close working relationship with customers, peers, and management.\n· Explore what’s possible to get the job done, including creative use of unconventional solutions.\n· Work effectively across functions and geographies.\n· Push to raise the bar while always operating with integrity.\n\nWith Regards,\nK Madhu Prasad\nkmadhup@cadence.com\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Senior Engineer- DEG Layout", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-21T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/43282293", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nRole and Responsibilities\nResponsible for layout design and development of critical analog, mixed-signal, custom digital block, standard cells  and full chip level.\nPerform layout verification like LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem checks,  quality check and documentation.\nResponsible for development of digital block layouts using auto placement and route tools\nResponsible for basic understanding of skill coding and automation\nResponsible for on-time delivery of block-level layouts with acceptable quality.\nDemonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/achievements in multiple project environment.\nGuide developing team members in their execution of Sub block-level layouts & review their work\nContribute to effective project-management.\nEffectively communicating with Global engineering teams to assure the success of layout project.\nResponsible for the reducing the layout effort by using AI tools\n\nQualification/Requirements\n5 to 8-year experience in analog/custom layout design in advanced CMOS process.\nExpertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.\nShould have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,\nGood understanding of Analog Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc.)\nUnderstanding layout effects on the circuit such as speed, capacitance, power and area etc.,\nAbility to understand design constraints and implement high-quality layouts.\nExcellent command and problem-solving skills in physical verification of custom layout.\nMultiple Tape out support experience will be an added advantage.\nExcellent verbal and written communication skills.\nExcellent verbal and written communication skills.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Turing-Design Verification Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-21T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719870533", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAbout the Role\nWe are looking for a skilled and motivated DV Engineer to join our subsystem verification team. In this role, you will be responsible for the functional verification of complex IPs and subsystems that form the building blocks of our next-generation SoCs. You will work closely with design, architecture, and SoC integration teams to define verification strategies, build robust testbenches, and drive coverage closure to deliver high-quality silicon.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nKey Responsibilities\nOwn and drive functional verification of IPs and subsystems from planning through sign-off.\nDevelop verification plans, testbench architecture, and test cases based on design and architecture specifications.\nBuild and enhance reusable, scalable verification environments using System Verilog and UVM.\nDevelop and maintain constrained-random and directed test scenarios, assertions, and functional coverage models.\nDrive coverage closure (code + functional) and debug failures using waveform/log analysis.\nCollaborate with design, architecture, and SoC integration teams to resolve issues and ensure verification completeness.\nContribute to regression setup, triage, and maintenance to ensure verification quality and throughput.\nSupport IP-to-subsystem-to-SoC integration and reuse of verification collateral across levels.\n\nRequired Qualifications\n4–6 years of hands-on experience in ASIC/SoC functional verification.\nStrong proficiency in System Verilog and UVM methodology.\nProven experience in IP, subsystem, and/or SoC-level verification.\nSolid understanding of verification concepts: constrained-random stimulus, functional coverage, assertions (SVA), and scoreboarding.\nStrong debug skills using simulation logs and waveform tools (e.g., Verdi/FSDB).\nGood understanding of digital design fundamentals, bus protocols, and SoC architecture.\nProficiency in scripting (Python/Perl/Tcl) for automation and flow development.\nStrong analytical, problem-solving, and communication skills.\nPreferred / Good-to-Have Skills\nExperience with low-power verification (UPF/Power-aware) flows.\nExposure to Gate-Level Simulation (GLS) including timing and SDF-based verification.\nFamiliarity with formal verification, emulation, or performance verification.\nExperience with industry-standard bus protocols (AXI/AHB/APB, etc.).\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RISC V CPU Design -Staff Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-21T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446717134140", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nQualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. \nWe are hiring talented engineers for CPU RTL development targeted for high performance, low power devices using the RISC-V Architecture. As a CPU Micro-architecture and RTL Design Engineer, you will work with chip architects to conceive of the micro-architecture, and also help with architecture/product definition through early involvement in the product life-cycle. \n\nRoles and Responsibilities \nPerformance exploration. Explore high performance strategies working with the CPU modeling team. \n\nMicroarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification. \n\nRTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals. \n\nFunctional verification support. Help the design verification team execute on the functional verification strategy. \n\nPerformance verification support. Help verify that the RTL design meets the performance goals. \n\nDesign delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability and testability.\n\nPreferred Qualifications \nThorough knowledge of microprocessor architecture including expertise in one or more of the following areas: instruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, prefetching, cache and memory subsystems \n\nKnowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools \n\nKnowledge of logic design principles along with timing and power implications \n\nUnderstanding of low power microarchitecture techniques \n\nUnderstanding of high-performance techniques and trade-offs in a CPU microarchitecture \n\nExperience using a scripting language such as Perl or Python \n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior DFT Engineer", "company": "Analog Devices", "location": "CLOSED-India, Bangalore, Aveda Meta", "date_posted": "2026-07-21", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/CLOSED-India-Bangalore-Aveda-Meta/Senior-DFT-Engineer_R260290", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nResponsibilities\nDFT architecture definition\nUnderstand SoC architecture and test requirements.\n\nWork very closely with the lead Product/Test engineering throughout the DFT definition phase to determine efficient ways to optimize test cost and achieve high test coverage.\n\nDrive and optimize DFT architecture for high performance and efficiency:\nSCAN – scan partition, compression, at-speed, IR and low power\n\nMBIST for memories\n\nJTAG boundary scan insertion\n\nHandle responsibilities pertaining to both block and top-level activities in Hierarchical Scan.\n\nImplementation\nDevelop / Upgrade SCAN & MBIST Insertion flows\n\nDevelop appropriate timing constraints for SCAN/MBIST modes and debug timing violations\n\nATPG flow implementation catering to various fault models, test pattern generation\n\nSCAN , MBIST & BSCAN Pattern Simulation\n\nSolutions to test analog macros\n\nPost-Silicon bring-up/support\nWork with Evaluation/Test Engineering team to bring-up patterns on ATE\n\nWork on failure analysis as required\n\nWork with the Operation team on test cost and yield improvement\n\nImprove DFT methodology to be in sync with latest best practices and technology in the industry\n\nWork closely with physical design team throughout the development cycle.\n\nShould be able to guide newly inducted team members on their bring-up on flow, methodology and execution methods in all aspects of DFT.\n\nRequirements\n\n4-8 years of industry experience in DFT domain.\n\nMust have experience in bringing atleast one or two products to successful production from architecture phase, scan implementation and simulations.\n\nMust have hands-on experience working on post-silicon activities.\n\nHaving working experience with tessent DFT (SCAN, Mbist, Lbist, OCC, EDT, SSN, Boundary Scan) will be preferred.\n\nExceptional interpersonal and communication skills are critical for working, influencing and collaborating with product development groups and CAD tool teams spread across the globe.\n\nScripting skills in Perl/Python/TCL and a good command over HDLs.\n\nCandidates with exposure to deep submicron effects and low power implementation using UPF/CPF will be at an advantage. Candidates with experience using Cadence digital implementation tools (Genus, Tempus) would be preferred.\n\nPrior experience of timing closure/physical design will be an added plus.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Senior Engineer, Analog Design Engineering", "company": "Analog Devices", "location": "India, Bangalore, Nova", "date_posted": "2026-07-21", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-Nova/Senior-Engineer--Analog-Design-Engineering_R263355", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nSenior Analog Design Engineer.\n \nJob Description\nThe charter of Analog Devices’ Consumer Audio team is to develop cutting-edge products for hearables, hearing health, and prosumer audio markets. These mixed-signal audio edge processors combine precision audio, heterogeneous processing, power management, connectivity and algorithms to enable next-generation user experiences.\n\nIn this role, you will contribute to product bring-up, validation, and system debug while building strong application expertise in audio products. You will work across silicon, embedded software, connectivity, and customer use cases, collaborating with global cross-functional teams to help bring innovative audio solutions to market.\nAnalog Devices is seeking a Mixed Signal IC Design Engineer to join the Hearable and Wearable Business Unit to participate in analysis, research, design, simulation, characterization, and release-to-production of high-performance, low power, integrated circuits.    The successful candidate will join a team with a track record of producing breakthrough innovative architectures for Class-D amplifiers and delta-sigma DAC’s and ADC’s, to name a few. The successful candidate must have a strong, intuitive capability in solving complex challenges. The candidate will be self-motivated and be able to work effectively within a team.   \n\nEducation: B.Tech/MS/Ph.D. in Electrical Engineering in CMOS IC design \n\nResponsibilities \n • Architecture investigation, design and verification of analog and mixed-signal blocks \nUnderstanding of a wide range of circuits such as high-gain amplifiers, switched-capacitor circuits, comparators, integrators, precision voltage references, LDOs \n  • Collaboration with digital design and design verification teams for block and system integration and verification at chip level \n  • Interface with product definition, product, applications, and test, engineering to successfully bring new products from initial concept through production release \n  • Evaluate and troubleshoot complex integrated circuit problems in the laboratory Education and Experience Requirements:   \n\n  \n Preferred Qualifications \n • Experience in ADC/DAC design   \n• Experience in audio IC design with a passion for audio   \n• Experience in Cadence schematic capture and SPICE simulation tools  \n• Experience with MATLAB or other modeling tools, and specifically their application to delta sigma modulator design  \n • Understanding of digital signal processing concepts\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 25% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Mixed Signal Design Verification Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-07-21", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Mixed-Signal-Design-Verification-Engineer_JR0285526-1", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact\nAs a Mixed Signal Design Verification Engineer, you will play a pivotal role in verifying and enhancing the functionality of mixed signal logic components, ensuring Intel's products meet the highest standards of quality, performance, and innovation. In this role, you will collaborate with cross-functional teams to validate cutting-edge IPs, pushing the boundaries of technology and innovation. Your work will directly contribute to Intel's leadership in delivering best-in-class solutions that power the future of computing.\n\nKey Responsibilities\n- Perform functional verification of mixed signal logic components, including analog behavioral modeling, to ensure compliance with design specifications.\n- Develop comprehensive IP verification plans, test benches, and verification environments to achieve thorough coverage of mixed signal microarchitecture specifications.\n- Define and execute verification plans, including running system simulation models, analyzing power and timing, and identifying and resolving design bugs.\n- Debug failing tests in the presilicon environment through root cause analysis and implement corrective measures to ensure design functionality.\n- Collaborate closely with digital and analog architects, RTL developers, and physical design teams to improve architectural and microarchitectural features.\n- Lead technical reviews of test plans and validation proofs with design and architecture teams while documenting findings and ensuring thorough validation coverage.\n- Maintain, refine, and enhance functional verification methodologies, infrastructure, and tools to keep pace with industry advancements.\n\nQualifications:\nMinimum Qualifications\n- Bachelor's or Master's degree in Electronics, VLSI Engineering, or a related field.\n- 4-12 years of experience with a Bachelor's degree, or 3-10 years of experience with a Master's degree in ASIC or SoC verification.\n- Excellent knowledge on DDR4/DDR5/LP5/LP6 protocol\n- Expertise in System Verilog, UVM, and Verilog for mixed signal verification.\n- Hands-on experience with industry-standard EDA tools such as Synopsys VCS, Cadence Xcelium/JasperGold, or Mentor Questa.\n- Strong scripting skills in Python, Perl, or Tcl for testbench automation and process efficiency.\n- In-depth knowledge of standard protocols including JTAG, IJTAG, CRI, and APB, as well as multi-clock domain mixed signal designs.\n- Proficiency in constraint-random test generation, root cause analysis, and debugging of complex mixed signal designs.\n\nPreferred Qualifications\n- Experience with low-power design techniques, including UPF and clock gating, to optimize power consumption.\n- Familiarity with Formal Property Verification tools and version control systems such as Git or Perforce.\n- Strong collaboration and communication skills, with the ability to thrive in a dynamic, multidisciplinary team environment.\n\nJoin us to drive verification excellence and shape the future of technology at Intel. Apply today to become part of our mission to deliver transformative innovations.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Principal Engineer", "company": "Infineon", "location": "Bangalore", "date_posted": "2026-07-20T08:20:22+00:00", "url": "https://jobs.infineon.com/careers/job/563808971706738", "is_hardware": true, "platform": "eightfold", "jd_text": "#WeAreIn to transform theoretical concepts into real hardware designs. Are you in?\n\nYour Role\n\nKey responsibilities in your new role\n\nLead and drive power-related design methodologies, analysis, and optimization activities, leveraging strong domain expertise and hands-on experience.\nDevelop, enhance, and maintain design automation solutions and methodologies using scripting languages such as Tcl and Perl.\nProvide technical leadership for flow development and methodology initiatives across geographically distributed and multi-site project teams.\nTranslate product specifications and design requirements into efficient physical implementation solutions using advanced EDA tools and design flows.\nExecute and contribute across all stages of the RTL-to-GDSII (RTL2GDS) design flow, ensuring high-quality and timely project delivery.\nCollaborate with and guide cross-functional teams to achieve performance, power, quality, and schedule targets.\nAnalyze complex technical challenges, identify root causes, and drive effective resolutions by leveraging internal expertise and a global engineering network.\nChampion continuous improvement of design flows, methodologies, and implementation practices to enhance productivity and design quality.\n\nYour Profile\n\nQualifications and skills to help you succeed\n\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Microelectronics, or a related discipline.\n15+ years of experience in CAD and/or Physical Design for highly complex SoCs.\nStrong technical expertise across the entire RTL-to-GDSII design flow, with a deep understanding of all associated methodologies and challenges.\nDemonstrated technical leadership with a proven track record of driving successful design and implementation projects.\nHands-on experience in physical design and CAD methodologies, coupled with effective people management and team leadership skills.\nStrong programming and automation skills, with proficiency in scripting languages such as Tcl, Perl, and Python.\nExtensive experience developing and maintaining tools, flows, and methodologies using Perl, Tcl, and other relevant programming languages.\nExcellent communication, stakeholder management, and leadership skills, with the ability to collaborate effectively across global and cross-functional teams.\n\nContact:\n\n    Gowri.Shenoy@infineon.com\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\nThis means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.\nPlease let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.\nClick here for more information about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Formal Verification Engineer, Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-20T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719772070", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Description\nWe are seeking a highly motivated Formal Verification Lead Engineer with 8 years of experience to join our GCAD Formal team. The ideal candidate will have strong formal verification fundamentals, hands-on experience with formal tools, excellent analytical and scripting skills, and the ability to drive innovative verification methodologies. This role provides the opportunity to collaborate across global architecture, design, and systems teams to influence and strengthen verification sign‑off quality.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nKey Responsibilities\nDrive formal verification of complex design blocks using advanced Formal Apps and robust convergence strategies to achieve exhaustive and high‑confidence sign‑off.\n\nCollaborate with worldwide architecture, design, and systems teams to achieve verification goals.\n\nReview and refine formal setups, proofs, constraints, and abstractions with design/DV teams.\n\nEngage with EDA vendors and evaluate advanced DV methodologies to improve sign‑off quality.\n\nDevelop automation scripts (Python preferred) to enhance efficiency and scalability of FV flows.\n\nAnalyze challenging formal problems and propose effective verification strategies.\n\nMinimum Qualifications\n\n4–6 years of hands-on experience in Formal Verification.Strong understanding of formal concepts, proof strategies, and abstraction techniques.\n\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field\n\nProficiency with formal tools (Jasper, VC Formal, Questa Formal, etc.).\n\nWorking knowledge of property-based FV (SVA ) is a plus.\n\nExcellent scripting skills (Python strongly preferred).\n\nStrong analytical and problem‑solving abilities.\n\nClear communication skills and ability to collaborate with global teams.\n\nA strong willingness to learn, innovate, and deliver high‑quality results.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Validation Engineer II", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-07-20", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Senior-Validation-Engineer-II_R3154-26", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nJOB DESCRIPTION *\nWe are seeking a Senior Validation Engineer-2 for Microchip’s MCU division to support validation and characterization of 8-bit and 32-bit microcontrollers. Microchip is a world leader in 8, 16, and 32- bit microcontrollers. The Validation Engineering position is focused on helping with development of our digital and parametric testing infrastructure. Significant time will be spent developing test cases, performing lab bench experiments, and assisting other team members in the validation of 8 and 32-bit microcontrollers at the unit and system-level. This position is based in Bangalore, India. As a validation engineer, you will work with worldwide teams located in France, USA, Philippines, India and other corporate team members.\n\nJOB REQUIREMENTS\nDevelop and implement functional, performance and system level/use-case validation of 8 and 32 bit microcontrollers\nExperience with Microcontrollers, FPGAs, and in general, Embedded Systems. Familiar with embedded ARM Cortex M family, RISC-V, MIPS is preferred\nExperience with communication busses (GPIB, RS-232, RS-485, SPI/QSPI, I2C, I2S, USB, EBI, Ethernet, etc.).\nExperience with Embedded firmware development and should have strong hands-on knowledge of  embedded C programming language\nCandidate will have the primary role of creating, auditing, and overseeing test procedures, validation plans,  data collection, post-processing of validation data, reports, and documenting results.\nCandidate should be familiar with using lab equipment such as Oscilloscopes, Logic Analyzers, Power Supplies, Arbitrary Waveform and Pulse generators, etc.\nFluent in use of PCB schematics and layout.\nDevelop performance tests for determining circuit margin and datasheet parameters.\nDevelop automated lab-based testing of microcontroller for both digital and analog modules at the unit level and at the full chip level and should be able to troubleshoot and resolve issues found during validation\nDesign or assist in the development of new testing infrastructure for use within the validation team\nDrive design recommendations to improve the validation process, such as enhancements to test software and hardware environments, lab equipment usage, and data management.\nWork with the validation team on customer support requests for released products.\nWork in an international environment (Europe, Asia, USA) with diverse functional groups (Architecture, Analog/Digital Design, Applications, Marketing, Product and Test Engineering).\n\nRequirements/Qualifications:\n\nQualifications\nCandidate must be a College Graduate with a Bachelor’s degree in Electrical / Electronic or Computer Engineering (or equivalent).\nCandidate should have 6 to 8 years of related work experience.\n\nAdditional Qualifications\nExperience with Clock subsystem and Reset subsystems (BOR, POR, Bandgap, WDT etc.) and exposure to Analog peripherals (ADCs, DACs, Comparators, Op-AMPs, CTMU).\nExposure to bench automation tools(NI Tools - LabView/TestStand) and scripting languages is add-on\nExperience in application development, system level test development\nStrong analytical and problem-solving / debug skills. Code and System debugging skills using in circuit emulators and lab equipment such as oscilloscope/logic analyzer.\nExcellent verbal and written communication skills.\nAble to work well in a team environment and adapt real-time.\nAble to think of test cases and customer usage model that may violate the assumptions of designers and architects.\nAble to prioritize tasks and execute to rigorous and dynamic schedules.\nAble to understand and generate board schematics, , board design - schematic entry, BOM creation, net list generation (logical board design)\nComprehensive record keeping and detailed debugging notes.\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Staff System Validation Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-07-20", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505287", "is_hardware": true, "platform": "oracle", "jd_text": "System Validation Staff Engineer\n\nonsemi India is seeking a Pre‑Silicon System Validation Engineer for FPGA‑based validation of power‑conversion ICs. This role, based in Bangalore, involves defining requirements, developing emulation platforms based on the SoC RTL and validating product functionality through hands‑on hardware, software, and system‑level testing.\n\nResponsibilities\n\nPort SoC RTL to FPGA, including placement, timing closure, and emulation bring‑up.\n\nDevelop Verilog models to emulate analog functions on FPGA.\n\nPerform FPGA verification, system integration, and lab testing.\n\nSupport ongoing FPGA and board‑level validation activities.\n\nUse Python and C/C++ for simulation and data analysis.\n\nConduct pre‑silicon verification using simulation tools and FPGA platforms.\n\n#LI-VS1\n\nResponsibilities\nKey Responsibilities\nDevelop and execute comprehensive validation plans covering functional, electrical, system, reliability, and application-level requirements.\nLead silicon characterization, system validation, and root cause analysis of complex product and application issues.\nDesign and implement automated validation solutions using LabVIEW, Python, NI PXI, and related platforms.\nValidate PMD products including SmartFETs, eFuses, power switches, gate drivers, and automotive power solutions.\nCollaborate with Design, Systems, Product Engineering, Applications, Quality, and Reliability teams to drive product readiness and issue resolution.\nDevelop validation methodologies, best practices, and reusable automation frameworks.\nInfluence future product designs through data-driven technical insights and validation expertise.\n#LI-VS1\n\nQualifications\nQualifications\nBS/MS/PhD in Electrical Engineering or related discipline.\nGrade 12: 5+ years of post-silicon validation, characterization, or systems engineering experience.\nGrade 13: 8+ years of experience with recognized technical leadership in validation and power management systems.\nStrong knowledge of analog/mixed-signal circuits, power electronics, automotive systems, and semiconductor validation methodologies.\nExpertise with laboratory instrumentation, automation, and debug techniques.\nExperience with LabVIEW, Python, and automated test systems.\nPreferred\nSmartFET, eFuse, Gate Driver, SBC, or automotive validation experience.\nFunctional Safety, ISO 26262, ISO 21780, SiC/GaN, and AI-assisted validation experience.\n#LI-VS1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Digital Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-07-20", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505894", "is_hardware": true, "platform": "oracle", "jd_text": "We are looking to expand our team with a Senior Digital IC Design Engineer. You will help us develop IP for next generation Automotive, Industrial & Medical products. The successful candidate will participate in the design of complex mixed-signal IPs like DACs, ADCs, PLL and wireless interface etc. \n\nWhy Join Us\n\nWe create a diverse set of world-class products in a friendly and team-oriented atmosphere. We provide an environment of continual learning and growth opportunities and support volunteer & charitable programs. You will be able to build up a career in a successful international company, and you can participate in interesting international projects.\n\n#LI-RG1\n\nResponsibilities\nWhat You’ll Do\nDefine architecture and participate in feasibility studies for new analog/mixed-signal IP components\nDrive design and verification of state-of-the-art CMOS and SOI designs which can be reused across different market segments.\nLead small teams on sub-projects and contribute to SoC integration\nPropose innovative solutions to meet customer and product needs\nCollaborate on DFT strategies and document designs thoroughly\nPartner with test, product, and applications engineering to ensure successful production release\nDocumentation: including architecture and circuit descriptions, testing procedures, and safety mechanisms.\n#LI-RG1\n\nQualifications\nWhat You’ll Need\nMinimum BS/MS in Electrical Engineering or related technical field\n2 years in ultra-low-power digital design using Verilog/System Verilog\nCapacity to think at the system level and to operate as a technical leader\nCreativity, dynamism, reliability and team spirit\nExcellent English written and verbal communication skills\nWhat Else You May Bring \nExperience in some of the following areas is a plus:\nKnowledge Verilog-A or VHDL-AMS.\nExperience with embedded CPUs (e.g. ARM Cortex, DSP), AMBA bus protocols (AHB/APB)\nExperience in ADC, DAC, PLL, power management systems\nProgramming in Python for automation and in C/C++ for embedded software\nDesign intent (timing constraints/SDC, power intent/UPF)\nDesign of accelerators and signal processing components\nRTL to GDS flow, including logic synthesis, place-and-route, STA, power analysis\nAdvanced digital verification methodology (e.g. UVM)\nKnowledge in Functional Safety\n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Senior Principal, Analog Design", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-07-20", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505927", "is_hardware": true, "platform": "oracle", "jd_text": "Description    \n\n  \n\n At onsemi, we help improve lives through silicon solutions every day. Our intelligent power and sensing technologies solve the world’s most complex challenges and lead the way in creating a safer, cleaner, and smarter world. Our group develops MCU and DSP systems as well as hardware accelerators that are used in a large variety of different products and markets.\n\n The Role\n\n We are looking for a Principal Analog Design Engineer with experience in the verification of embedded MCU/DSP systems, to build and manage a new analog design team. This team is chartered to deliver differentiated analog circuits to a series of mixed-signal compute products.\n\n Our commitment to you\n\n As part of the onsemi team, you will have an opportunity to transform your tomorrow and operate in a diverse, inclusive, and socially responsible environment. If you’re passionate about shaping a better future, join us!\n\n  \n\n #LI-MK1\n\nResponsibilities\nResponsibilities   \n \nWhat You’ll Do\n\n•    Design leadership: Create and deliver a series of analog circuits relevant for the mixed-signal products\n•    Problem solving & innovation: Identify novel solutions for delivering differentiation in circuit performance, quality, efficiency\n•    Technical guidance & mentoring: Guide world-wide teams in technical areas, from architecture to productisation\n\nWhat Else You May Bring (Experience in some of the following areas is a plus)\n\n•    Experience in interfacing to embedded CPUs and accelerators\n•    Understanding of signal processing components or processing systems\n•    Awareness in digital design practices and requirements\n \n#LI-MK1\n\nQualifications\nQualifications  \n   \nWhat You’ll Need\n\n•    B.Tech / M.Tech in Electrical Engineering or related technical field\n•    At least 14 years of strong technical experience in analog design, across a breadth of functions, and across technologies\n•    Strong leadership credentials\n•    An extensive technical background within the development of semiconductor products or sub-components (IPs)\n•    Experience with analog test/productization \n•    Strong communication skills\n•    Ability to define strategic actions, with appropriate design trade-off analyses\n\n#LI-MK1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Software Engineer 2", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-07-20", "url": "https://careers.skyworksinc.com/job-invite/77978/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 77978\n\nDescription\n\nSkyworks Solutions is seeking a highly motivated multidisciplinary individual to drive software/AI development and workflows automation to accelerate innovation across our semiconductor products. This role sits at the intersection of muti-tier software product and platform development and EDA tools, silicon design flows, and scalable software systems. Your work will make a direct impact on company's top and bottom line.\n\nThe ideal candidate has hands‑on experience building innovative products from ground up, automate processes, and thrives in a collaborative environment.\n\nResponsibilities\n\nDesign, develop, and maintain software products and platform for semiconductor design automation supporting design, tapeout and post-tapeout workflows\n\nDevelop software / AI solutions to improve productivity, quality, reliability and design reuse.\n\nIntegrate commercial EDA tools via API/CLI into Skyworks design flows\n\nCollaborate with engineering teams to define automation requirements.\n\nDebug design flow issues and improve tool reliability and scalability.\n\nDefine and develop good software development practices\n\nSupport semiconductor tape‑out schedules and continuous improvement initiatives\n\nUse AI/ML to optimize process, built more predictability, reliability across the process flows.\n\nRequired Experience and Skills\n\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field\n\n3-5 years of relevant solid industry Full-stack software development experience\n\nStong experience with software tech-stack - UI (React.js, QT). Backend (Python, C++, Java),  Databases (Azure SQL, Databricks)\n\nExperience with workflow automation\n\nExperience using Machine learning models to solve complex challenges.\n\nExperience developing custom AI agents, MCP servers\n\nExperience leading DevOps (github, jenkins)\n\nExperience hositng application on web server\n\nConfortable working with both Linux and Windows environment\n\nExperience with version control systems such as Git and/or Perforce/CI/CD\n\nSoftware Engineering & Operations\n\nAbility to host, operate, and scale web‑based software tools in Unix/Linux environments\n\nExperience setting up and maintaining Apache (or similar) web servers in on‑premises environments\n\nWorking knowledge building software product which are secure by design \n\nCloud & Modern Tooling\n\nExperience or familiarity with at least one cloud platform (AWS, GCP, or Azure)\n\nExperience using AI‑assisted development tools (e.g., Claude Code, OpenAI Codex, or similar) to improve productivity and automation\n\nDesired Experience and Skills\n\nDomain experience in semiconductor\n\nExposure to large‑scale EDA compute environments or regression infrastructures\n\nExperience supporting hybrid on‑prem + cloud engineering platforms\n\nFamiliarity with CI/CD concepts applied to EDA flows and tooling\n\n#LIPR1\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "POST SILICON VALIDATION ENGINEER", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-07-17T03:04:00+00:00", "url": "https://global-external-amd.icims.com/jobs/88467/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. POST SILICON VALIDATION ENGINEER    THE ROLE:  We are looking for a dynamic, energetic Lead / Senior Systems Design Engineer to join our growing team. As a key contributor to the success of AMD’s product, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The Systems Design Engineering team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.    THE PERSON:  As a Systems Design Engineer, you will drive balanced, scalable, and automated solutions. In this high visibility position, your software systems engineering expertise will be necessary towards product development, definition, and root cause resolution.    KEY RESPONSIBILITIES:  Driving technical innovation to improve AMD’s capabilities across validation, including tool and script development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives Debugging issues found during the process, bring-up, validation, and production phases of SOC programs  Working with multiple teams, and tracking test execution to make sure all features are validated and optimized on time Working closely with supporting technical teams Engaging in other software/hardware modeling frameworks Leading collaborative approach with multiple teams   PREFERRED EXPERIENCE:  Programming/scripting skills (e.g. C/C++, Perl, Ruby, Python) Debug techniques and methodologies RAS and Reset validation: Experience in RAS validation and reset‑flow reliability by executing high‑coverage tests, analyzing failure signatures, and strengthening recovery logic across platforms. Drives systemic quality improvements through targeted debug, automation, and cross‑functional alignment on behavior. Extensive experience with board/platform-level debugging, including delivery, sequencing, analysis, and optimization Extensive knowledge of system architecture, technical debug, and validation strategy Strong analytical/problem-solving skills and pronounced attention to details Must be a self-starter, and able to independently drive tasks to completion Knowledge of system architecture, technical debug, and validation strategies   ACADEMIC CREDENTIALS:  Bachelors or Masters degree in electrical or computer engineering #LI-PK1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "LEAD POST SILICON VALIDATION ENGINEER  ", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-07-17T03:00:00+00:00", "url": "https://global-external-amd.icims.com/jobs/88449/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. LEAD POST SILICON VALIDATION ENGINEER    THE ROLE:  We are looking for a dynamic, energetic Lead / Senior Systems Design Engineer to join our growing team. As a key contributor to the success of AMD’s product, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The Systems Design Engineering team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.    THE PERSON:  As a Systems Design Engineer, you will drive balanced, scalable, and automated solutions. In this high visibility position, your software systems engineering expertise will be necessary towards product development, definition, and root cause resolution.    KEY RESPONSIBILITIES:  Driving technical innovation to improve AMD’s capabilities across validation, including tool and script development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives Debugging issues found during the process, bring-up, validation, and production phases of SOC programs  Working with multiple teams, and tracking test execution to make sure all features are validated and optimized on time Working closely with supporting technical teams Engaging in other software/hardware modeling frameworks Leading collaborative approach with multiple teams   PREFERRED EXPERIENCE:  Programming/scripting skills (e.g. C/C++, Perl, Ruby, Python) Debug techniques and methodologies RAS and Reset validation: Experience in RAS validation and reset‑flow reliability by executing high‑coverage tests, analyzing failure signatures, and strengthening recovery logic across platforms. Drives systemic quality improvements through targeted debug, automation, and cross‑functional alignment on behavior. Extensive experience with board/platform-level debugging, including delivery, sequencing, analysis, and optimization Extensive knowledge of system architecture, technical debug, and validation strategy Strong analytical/problem-solving skills and pronounced attention to details Must be a self-starter, and able to independently drive tasks to completion Knowledge of system architecture, technical debug, and validation strategies   ACADEMIC CREDENTIALS:  Bachelors or Masters degree in electrical or computer engineering #LI-PK1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "LEAD POST SILICON VALIDATION ENGINEER  ", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-07-17T03:00:00+00:00", "url": "https://global-external-amd.icims.com/jobs/88450/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. LEAD POST SILICON VALIDATION ENGINEER    THE ROLE:  We are looking for a dynamic, energetic Lead / Senior Systems Design Engineer to join our growing team. As a key contributor to the success of AMD’s product, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The Systems Design Engineering team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.    THE PERSON:  As a Systems Design Engineer, you will drive balanced, scalable, and automated solutions. In this high visibility position, your software systems engineering expertise will be necessary towards product development, definition, and root cause resolution.    KEY RESPONSIBILITIES:  Driving technical innovation to improve AMD’s capabilities across validation, including tool and script development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives Debugging issues found during the process, bring-up, validation, and production phases of SOC programs  Working with multiple teams, and tracking test execution to make sure all features are validated and optimized on time Working closely with supporting technical teams Engaging in other software/hardware modeling frameworks Leading collaborative approach with multiple teams   PREFERRED EXPERIENCE:  Programming/scripting skills (e.g. C/C++, Perl, Ruby, Python) Debug techniques and methodologies RAS and Reset validation: Experience in RAS validation and reset‑flow reliability by executing high‑coverage tests, analyzing failure signatures, and strengthening recovery logic across platforms. Drives systemic quality improvements through targeted debug, automation, and cross‑functional alignment on behavior. Extensive experience with board/platform-level debugging, including delivery, sequencing, analysis, and optimization Extensive knowledge of system architecture, technical debug, and validation strategy Strong analytical/problem-solving skills and pronounced attention to details Must be a self-starter, and able to independently drive tasks to completion Knowledge of system architecture, technical debug, and validation strategies   ACADEMIC CREDENTIALS:  Bachelors or Masters degree in electrical or computer engineering #LI-PK1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Synthesis Engineer, Lead/Staff/Sr Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-17T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446715517863", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nRequirements: \nLooking for a highly talented and a technically strong leader with an eye for quality to lead a high performing and talented team of engineers in the implementation domain for Display Sub-System.\nAble to handle multiple project execution that are time critical and complex\nAble to communicate effectively with all stakeholders across the organization\nAble to collaborate with cross functional teams for upholding the best practices and enabling smooth execution\nFocus on improving execution efficiency and improve on the optimizations in area, power and performance.\nAble to grow the team in terms of technical depth and size as we do more and more projects\nAble to innovate and bring fresh ideas\nBachelor’s or master’s degree in engineering with 9-13+ Years of experience.\nShould have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.\nExperience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.\nExperience in all aspects of timing closure for multi-clock domain designs.\nShould be familiar with MCMM synthesis and optimization.\nShould have good understanding of low-power design implementation using UPF.\nExperience with scripting language such as Perl/ Python, TCL.\nExperience with different power optimization flows or technique such as clock gating.\nShould be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation\nShould be able to handle ECOs and formal verification and maintain high quality matrix\n\nResponsibilities include:\nSynthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation.\nDevelopment of signoff quality constraints and the development of power intent constraints.\nMay also include running RTL Lint, CLP, MEMBIST, DFT DRC etc.\nTCL script development in addition to running/analyzing/debugging designs.\nHands on with Synopsys DCG/Genus/Fusion Compiler.\nHands on with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains.\nHands on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development\nExperience with either RTL development or Physical Design is also a plus\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Design Implementation Synthesis Engineer, Staff / Sr Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-17T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446717381469", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Description:  \nShould have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.\n\nExperience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.\n\nExperience in all aspects of timing closure for multi-clock domain designs.\n\nShould be familiar with MCMM synthesis and optimization.\n\nShould have good understanding of low-power design implementation using UPF.\n\nExperience with scripting language such as Perl/ Python, TCL.\n\nExperience with different power optimization flows or technique such as clock gating.\n\nShould be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation\n\nShould be able to handle ECOs and formal verification and maintain high quality matrix\n\n8+ yrs experience\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Engineer - HBM Analog Design", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-17T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/39938740", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nContributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits.\n\nDesign, implementation, and improvement of Complex Analog Power Management IPs such as Bandgap reference, Voltage/Current reference, Regulators, Charge-pumps, CMOS Amplifiers, Comparators in advanced semiconductor process nodes for advanced DRAM products.\n\nParasitic modeling and assisting in design validation, reticle experiments and required tape-out revisions.\n\nBeing responsible for and managing the layout process including floor-planning, placement, and routing.\n\nPerforming verification processes with modeling and simulation using industry standard simulators.\n\nContributing to cross group communication to work towards standardization and group success.\n\nWorking with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product.\n\nProactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality.\n\nDriving innovation into the future Memory generations within a dynamic work environment.\n\nLeveraging AI\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Sr Staff STA Application Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-07-17", "url": "https://careers.synopsys.com/job/bengaluru/sr-staff-sta-application-engineer/44408/97907418704", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent a decade or more in the trenches of silicon timing, and you know that the difference between a chip that tapes out on schedule and one that slips by three months often comes down to how well someone understands PrimeTime and can translate that knowledge into action for a stressed design team. You have debugged timing violations at 2 a.m. before a milestone, and you have sat across from skeptical engineering managers explaining why your approach will save them weeks, not cost them risk.\nYou are equally comfortable running a competitive benchmark that proves tool superiority and sitting with a customer's design team walking through setup and hold violations in their actual netlist. You do not just know the theory of process corners and signal integrity, you have lived through the messiness of real designs where nothing is clean and every decision is a tradeoff. When a customer asks a hard question, you do not deflect, you dig in, and if you do not know the answer, you know exactly who in R&D to pull in and how to frame the problem so it gets solved.\nYou think in workflows, not features. Training is not about showing slides, it is about making sure the person leaves able to do the thing. At Synopsys, you will work with the team behind the industry-leading STA tool and the customers who depend on it to ship the chips that power everything.\n\nWhat You'll Be Doing\nDrive PrimeTime adoption and usage with customers in both pre-sales evaluations and post-sales deployment, including competitive benchmarking, proof-of-concept runs, and technical win strategies\nDeliver hands-on customer training on Static Timing Analysis workflows, timing closure techniques, process variation analysis, and signal integrity debugging using PrimeTime\nProvide tape-out support for customer designs, troubleshooting timing violations, setup/hold issues, and corner-case scenarios in real production environments\nCollaborate with R&D to communicate customer requirements, report tool issues, and drive product enhancements based on field deployment feedback\nWork closely with sales, marketing, and field teams to articulate PrimeTime's technical advantages to design teams and engineering management\nDevelop and refine TCL-based automation scripts and methodologies that improve customer productivity and timing closure efficiency\nSupport customers through the full design flow, interfacing with synthesis, physical design, extraction, and ECO processes to ensure seamless PrimeTime integration\n\nThe Impact You Will Have\nAccelerate customer tape-out schedules by resolving critical timing issues and enabling faster, more confident timing closure\nExpand PrimeTime footprint and deepen usage across customer organizations through technical excellence and trusted advisory relationships\nInfluence the PrimeTime product roadmap by translating real-world customer challenges into actionable R&D priorities\nReduce customer risk and rework by delivering training and methodologies that prevent common timing pitfalls before they become schedule killers\nStrengthen Synopsys competitive position by demonstrating measurable performance, capacity, and accuracy advantages in head-to-head evaluations\nEnable design teams to adopt advanced timing analysis techniques for process variation, multi-mode multi-corner, and signal integrity that improve chip performance and yield\nBuild long-term customer partnerships where Synopsys is seen as an extension of their engineering team, not just a tool vendor\n\nWhat You'll Need\nBachelor's degree in Electrical Engineering or equivalent, with 10+ years of hands-on experience in ASIC/SoC design, timing analysis, or related fields, or Master's degree with 9+ years of experience\nDeep working knowledge of Synopsys PrimeTime, including hands-on experience running STA, analyzing timing reports, and debugging violations in real customer designs\nSolid understanding of timing corners, process variations, on-chip variation (OCV), advanced OCV (AOCV), statistical STA, and signal integrity effects on timing\nFamiliarity with the broader digital design flow, including synthesis, place and route, parasitic extraction, and ECO methodologies\nStrong TCL scripting skills for automation, flow customization, and productivity improvements\nDemonstrated ability to communicate complex technical concepts clearly to both engineering teams and management, prior customer-facing experience is a strong plus\nWillingness to travel to customer sites as needed for training, support, and technical engagements\n\nWho You Are\nYou can walk into a customer meeting with a timing report full of violations and walk out with a clear action plan that the design team trusts and can execute\nYou know when to push back on a customer request because the real problem is upstream in their methodology, and you know how to have that conversation without burning the relationship\nYou are comfortable context-switching between a competitive benchmark for a prospect, a tape-out crisis call with an existing customer, and a product enhancement discussion with R&D, all in the same week\nYou treat customer problems like they are your own, not because it is good service, but because you genuinely want to see the design succeed and you know your tool is the reason it will\nYou can explain a nuanced timing tradeoff to an engineering director in two sentences without losing the technical accuracy that matters\nYou stay current on process technology trends, design challenges, and timing methodologies because you know that what worked at 28nm does not always work at 5nm, and your customers need you to know the difference\n\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\n\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "SoC Power Management Architect", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-07-17", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/SoC-Power-Management-Architect_JR0285651", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nAbout the Role\n\nJoin our Silicon Architecture team to drive power-efficient SoC architecture and system-level innovation for next-generation client and AI computing platforms.\nWe are seeking a SoC Power Management Architect to join our Silicon Architecture team.\nThis role focuses on defining and developing cutting-edge System-on-Chip (SoC) architectures with emphasis on power management, performance optimization, and energy efficiency for next-generation computing platforms. You will collaborate across architecture, design, validation, and product teams to deliver scalable solutions from concept through high-volume manufacturing (HVM).\n\nWhat You'll Do\nKey responsibilities will include but not limited to:\nDefine and develop SoC power management architecture to optimize performance, efficiency, and thermal behavior\nMaintain a system-level perspective, ensuring alignment between product goals, constraints, and implementation\nEvaluate design trade-offs and define feature requirements, specifications, and architecture solutions\nDrive power integration strategies across new and existing IP blocks\nPartner with hardware and software teams to ensure successful execution, validation, and enablement\nSupport the full product lifecycle, from early concept through silicon bring-up and production\nAnalyze post-silicon power/performance data to identify optimization opportunities for current and future generations\nContribute to debug, root cause analysis, and continuous improvement efforts\n\nBehavioral traits that we are looking for:\nDemonstrates ownership and accountability for assigned systems\nApplies senior level technical judgment to design and delivery decisions\nThinks holistically about system impact and maintainability\nCollaborates effectively with technical and business partners\nStrong systems thinking with the ability to balance trade-offs across performance, power, and area\nExcellent communication and influence skills across cross-functional stakeholders\nHighly collaborative, with the ability to work effectively in global, matrixed teams\nOwnership mindset with a proactive and results-driven approach\nStrong analytical problem-solving skills and attention to detail\nComfortable operating in ambiguity and early-stage architecture definition\nContinuous learner with curiosity for emerging technologies and industry trends\n\nQualifications:\nMinimum Qualifications:\n- Bachelor's degree in Electronics/Electrical Engineering, Computer Engineering, or a related field, with 12+ years of experience; or Master's degree with 10+ years of experience; or PhD with 6+ years of experience.\n- Expertise in SoC architecture and development methodologies.\n- Strong knowledge of system architecture, microarchitecture fundamentals, and SoC architecture fundamentals.\n- Proficiency in architecture definition and feature definition.\n- Hands-on experience with architecture registers specification and SoC performance modeling and analysis.\n- Demonstrated ability to apply disciplined execution and problem-solving methodologies in complex projects.\n\nPreferred Qualifications and Experience:\n\n- Background knowledge of SOC architecture and power management architecture.\n- Experience in SoC architecture definition and development.\n- Power management feature definition and development experience.\n- Silicon level data collection and analysis skills and experience.\n- Debug skills and experience.\n\nWe are looking for talented candidates eager to make a meaningful impact. If you are passionate about technology and innovation, we encourage you to apply and be part of Intel's journey to create a smarter, more connected world.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Senior Engineer, RTL Design", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-07-17", "url": "https://careers.arm.com/job/bengaluru/senior-engineer-rtl-design/33099/97939808752", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Description\n \nIf you are passionate about pushing the boundaries of Design technology and thrive in a collaborative, dynamic environment, we invite you to join our team as a Design Engineer. Join usto be part of our journey in shaping the future of SoC design and innovation.\n\nResponsibilities\nAs a creative design engineer with a knowledge of subsystems and SoCs you will be part of a team integrating IP and developing logic for SoCs.\nYou will work with the project team to understand and review the architecture, and develop the design specifications.\nYour key responsibilities will include writing micro-architecture specifications, developing the RTL, fixing bugs and running various design checks.\nYou will work with the verification team to review test plans, and help debug design issues.\nYou will work with the performance analysis team to evaluate and improve subsystem performance.\nYou will also contribute to developing and enhancing the design methodologies used by the team.\nYou will guide and support other members of the team as needed to enable the successful completion of project activities.\nYou will balance other opportunities such as working with Project Management on activities, plans, and schedules\n \nRequired Skills and Experience:\n \nIn addition to bringing your accomplishment of either Bachelors or Master’s degree or equivalent experience in Computer Science or Electrical/Computer Engineering.\nExperience of 5+ years working in design of complex compute subsystems or SoCs, you will need: Strong knowledge of digital hardware design and Verilog HDL!\nA thorough understanding and experience of the current design techniques for complex SoC development.\nExperience creating design specifications\nExperience developing RTL for SoC projects\nExperience with Perl, Python or other scripting language\n\n \nDesired Skills and Experience:\nExperience with ARM-based designs and/or ARM System Architectures\nExperience integrating subsystems for PCIe, LPDDR, HBM, UCIe, Ethernet\nExperience with SystemVerilog and verification methodologies – UVM/OVM/e\nExperience leading small teams or projects\nExperience or knowledge in the following areasSynthesis and timing analysis\nStatic design checks, including CDC, RDC, X-Propagation, Linting\nPower management techniques\nDFT and physical implementation\n\n10x Mindset at Arm\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Read more about how we bring the 10x mindset to life on the Arm blog.\n \n#LI-SC2\n \nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Staff Engineer – DFT Engineering", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-07-17", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Staff-Engineer---System-Validation_R258199", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nJob Description:\n \nWe are seeking a skilled and experienced DFT Engineer to join our VLSI design team. The ideal candidate should have a strong background in Design for Testability (DFT) techniques, including LBIST (Logic Built-In Self-Test), ATPG (Automatic Test Pattern Generation), DFT DRC (Design Rule Checking), MBIST (Memory Built-in Sefl-Test), Boundary Scan, JTAG and Analog/Phy DFT.\n \nResponsibilities:\n \nCollaborate with the design team to ensure efficient and effective testability of complex integrated circuits.\nDesign and implement DFT features such as scan chains, compression, and built-in self-test structures to enhance testability.\nConduct DFT DRC checks in RTL/Netlist database to ensure compliance with DFT guidelines and rules.\nUtilize Cadence/Siemen’s DFT tool to perform DFT analysis and optimize testability metrics.\nGenerating high quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models using on-chip test compression techniques.\nMBIST Design (including repair) and Verification using Siemen’s EDA tool.\nValidation of DFT structures/patterns in RTL, Netlist with and without SDF.\nWork closely with the verification team to define and implement DFT verification plans.\nWork closely with physical design team for DFT implementation/constraints strategy for synthesis/STA.\nAnalyze and debug test failures and collaborate with the test engineering team to resolve issues.\nProvide guidance and mentorship to junior DFT engineers.\n \nQualifications:\n \nBachelor's/Master's degree in Electrical/Electronic Engineering, or a related field.\n7-10 years of hands-on experience in DFT methodologies and techniques.\nStrong knowledge of LBIST, ATPG, DFT DRC, Scan compression, Low power DFT Techniques, MBIST, Boundary Scan, Analog DFT, JTAG Architecture, DFT STA Constraint development.\nHand-on experience/expertise in Cadence/Siemen’s DFT EDA tools for Scan stitching, DRC, ATPG, Coverage improvement, MBIST, Boundary Scan.\nProficiency in scripting languages such as Perl, Tcl, and/or Python for automation.\nSolid understanding of digital design fundamentals, RTL coding, Lint/CDC, Low Power Checks and ASIC design flow.\nExcellent problem-solving skills and ability to work effectively in a team-oriented environment.\nStrong communication and interpersonal skills.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Staff Engineer, Physical Design", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-07-16T15:15:07.104000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000138146634-staff-engineer-physical-design", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Key Responsibilities\nLead MCU/subsystem/block-level closure efforts, focusing on timing closure, congestion resolution, power integrity, and physical implementation.\nCollaborate closely with SoC-level teams to align on clocking and floor planning strategies, leveraging strong understanding of SoC methodologies without direct ownership of SoC-level activities.\nWork on the different power domains and implement UPF.\nApply knowledge of clocking methodologies to ensure subsystem clock domain integration aligns with overall SoC clock architecture.\nDevelop and refine subsystem closure methodologies and automation flows to improve design quality and efficiency.\nMentor and guide physical design engineers within the subsystem teams, promoting best practices and methodology adoption.\nWork cross-functionally with RTL designers, STA, power, verification, and backend teams to ensure smooth subsystem integration and closure.\nProactively identify and mitigate physical design risks, coordinating with SoC teams on potential impacts and solutions.\n\nEducation :M.Tech/ B.Tech in Electrical Engineering\n7+ years of experience in physical design focusing on subsystem-level closure for complex hierarchical SoCs at advanced nodes (7nm, 5nm, or below).\nStrong expertise in timing closure, congestion management, and physical implementation at the block and subsystem level.\nSolid understanding of SoC-level floorplanning and clocking methodologies, including clock domain partitioning, clock tree architecture, skew management, and clock gating; candidate is expected to collaborate effectively on SoC-level activities but not lead them.\nHands-on experience with industry-standard physical design and timing tools such as Synopsys ICC2, Cadence Innovus, PrimeTime, and signoff platforms.\nProficient in scripting and automation (Tcl, Python, Perl) to support closure flows and methodology development.\nDeep knowledge of SoC design flows with proven ability to work closely with timing closure, power integrity, clocking, verification.\nSolid understanding of low-power design techniques and power-aware physical implementation.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior Test Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-07-16T05:44:34.808000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000138027599-senior-test-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "This role is an experienced individual contributor position requiring solid hands-on expertise in ATE test development, product validation, and debugging. The candidate will contribute to the development of reliable and cost-effective test solutions, working closely with more senior engineers while progressively increasing autonomy on complex tasks. For this role you are expected to provide and own the schedule on problems of a diverse scope, with occasional guidance. \nRenesas Electronics, a leading global semiconductor company, is rapidly scaling investing in  power delivery business. Products include Point of loads (POL), Hotswap/Efuse, drivers.\nKey Responsibilities\nDevelop and maintain ATE test programs and hardware for analog, mixed-signal, and power management products\nExecute test plan implementation, ensuring required test coverage and quality targets\nSupport product bring-up, characterization, and validation activities\nPerform debug and failure analysis on ATE systems and bench setups\nAnalyze test data to identify issues and improve yield and test stability\nWork closely with Design and Product Engineering teams to resolve technical problems\nSupport production ramp and sustaining engineering activities\nContribute to test time and cost optimization efforts\nFollow established DFT methodologies and test standards\nKey Competencies\nStrong execution and hands-on approach\nGood problem-solving and debugging capability\nAbility to work in team environments with increasing autonomy\nAttention to detail and quality focus\nWillingness to learn and grow technically\n \n\nBachelor’s degree in Electrical/Computer Engineering\n3–6+ years of experience in test engineering or related field\nExperience with ATE platforms (COHU DMDX, STS8300 is a plus)\nBasic understanding of DFT concepts and production test flows\nExperience in debugging analog and mixed-signal circuits\nFamiliarity with lab equipment (oscilloscope, multimeter, spectrum analyzer)\nProgramming skills in C/C++, Python, or similar\nBasic knowledge of data analysis and statistical methods\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Peripherals Design Verification -Sr Staff Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-16T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718044098", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\n11+ years’ experience in unit and IP level verification.\nWorked on coverage driven constraint random verification.\n\nKnowledge of standard protocols such as PCIe, CXL, USB, Ethernet.\n\nStrong in System Verilog, UVM, Test planning\n\nSound experience in testbench (stimulus, agent, monitor, checker) development.\n\nWorked in the verification having c based reference model inside the testbench\n\nExposure in scripting(perl, Python).\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NoC (RTL) Design-Sr Lead/Staff/Sr Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-16T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446715639881", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nMultiple positions across Network-on-chip (NoC)/ Interconnect Architecture, Design and Verification for the next generation System-on-chip (SoC) powering Smartphones, Notebooks, Smart glasses, Automobile, Server and other product categories.\nThe roles and responsibilities for this position includes but not limited to:-\nDefinition & Design of Next-gen Qualcomm coherent and non-coherent interconnect fabric & related IPsResponsible for specification, Micro-Arch and design of interconnect and related IP’s\nActively work with SoC Architecture, verification, physical design team, Soc Floorplan and core teams globally\nPartner with SoC performance team ensuring Interconnect meeting all performance requirement, and with silicon validation team to co-relate pre-silicon and post silicon design assumptions\nResponsible for micro-architecting all relevant debug hooks in NoC Infrastructure to help root cause silicon issues\n\nDeveloping robust, scalable testbench & drive functional, power aware, performance, security, debug feature verification of Next-gen Qualcomm coherent and non-coherent interconnect fabric & related IPsResponsible for testbench definition, testplanning, developing stimulus, scoreboard and coverage closure\nActively work with Systems, Architecture, Design, SoC Design, DV, Performance teams to comprehend the system requirements and drive verification of Interconnects\nParticipate and drive debugs across platforms viz core, SoC, emulation and silicon\n\nWill be part of AIP - NoC/Interconnect core team\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Network-on-chip/interconnect Design -Staff Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-16T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446715752796", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nNetwork-on-chip (NoC)/ Interconnect Design and Architecture for the next generation System-on-chip (SoC) for smartphones, notebooks, smart glasses, tablets and other product categories. The roles and responsibilities for this position includes but not limited to:-\nArchitecture and deployment of Next-gen Qualcomm coherent and non-coherent interconnect fabric\nResponsible for specification, Micro-Arch, design and verification of interconnect and related IP’s\nActively work with SoC Architecture, verification, physical design team, Soc Floorplan, core teams and various other interconnect teams in various other sites\nPartner with SoC performance team ensuring Interconnect meeting all performance requirement, and with silicon validation team to co-relate pre-silicon and post silicon design assumptions\nResponsible for micro-architecting all relevant debug hooks in NoC Infrastructure to help root cause silicon issues\nWill be part of BDC infrastructure (NoC/Interconnect) core team\n\nMinimum Qualifications:\n8+ years of solid experience in IP/SoC design\nUnderstanding of interconnect protocols like CHI/AHB/AXI/ACE/ACE-Lite/NoC concepts\nGood knowledge of  RTL development and verification\nHands-on experience with SoC Design, Verilog RTL coding\nUnderstanding of Verif is a plus\nUnderstanding of multi-core ARMv8/v9 CPU architecture, coherency protocols and virtualization.\nWorking knowledge of Synthesis, DC/DCG synthesis with Synopsys design complier, DFT, verification, formal verification, silicon debug\nWorking knowledge of Lint, CDC, PLDRC, CLP etc\nGood understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification\nManage SoC dependencies, planning and tracking of all front-end design related tasks\nDriving the project milestones across the design, verification and physical implementations\nShould possess effective communication and leadership skills\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Verification Engineer, Switch SoC", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-07-16", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer--Switch-SoC_JR2021393", "is_hardware": true, "platform": "workday", "jd_text": "We are currently seeking an expert SOC Design and Integration Engineer with strong design fundamentals to work in Switch Silicon group. You'll join a group of hardworking engineers to craft and implement the next generation innovative Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing best high-speed communication devices, delivering the highest throughput and lowest latency!\n \nThe Networking Chip Design team in India is a new team which is growing at a fast pace.\n \nWhat you'll be doing:\nYou are encouraged to understand all features of a given project and define project milestones based on internal roadmaps, assign them and track them through agile framework\n\nDefine and develop system-level methodologies, tools, and IPs to build SOCs in an efficient and scalable manner.\n\nWork on SOC Assembly and drive cross-functional teams towards SOC milestone execution.\n\nBe responsible for integrating all the pieces for a given defined project milestone and deliver the model to relevant teams for further verification at cluster/sub-system/SOC/emulation levels.\n\nHave good grasp of Perl, Python, or other industry-standard scripting languages.\n\n \nWhat we need to see:\nBS (or equivalent experience) / MS with 4+ years of practical semiconductor design and architecture experience building complex SoC’s.\n\nMust have firsthand experience & solid understanding of all phases of SOC development in multiple ASIC projects including ASIC architecture, Micro-Architecture, RTL design, verification, timing closure & Physical design.\n\nExposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.).\n\nC/C++ programming or python or any other industry-standard scripting language experience desirable.\n\nExperience working with software teams to tightly define the HW/SW interface including control/status registers, interrupt and error handling.\n\nHands on experience in successful tape outs of multiple complex, high-volume SoCs in advanced process nodes.\n\nExposure to various Chip Design Functions to be able to collaborate and solve complex cross functional problems.\n\nExcellent verbal and written communication skills to interact with cross functional teams to build consensus.\n\nGood teamwork spirit and collaboration skills with team members.\n\nExperience in synthesis, physical design and DFT is a plus.\n\nBackground in RTL Build and Design Automation is a plus.\n\n \nWays to stand out from the crowd:\nChip lead type of technical leadership experience on delivering complex SOCs for enterprise and/or HPC applications.\n\nExperience in RTL coding and debug, as well as performance/power/area analysis and trade-offs\n\nExperience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area.\n\nStrong coding skills in Perl, Python, or other industry-standard scripting languages.\n\n \nWidely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/\n \nNVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior ASIC Power and Thermal Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-07-16", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-ASIC-Power-and-Thermal-Engineer_JR1998409", "is_hardware": true, "platform": "workday", "jd_text": "As one of the technology industry's most desirable employers, NVIDIA has been redefining accelerated computing, computer graphics and leading the Artificial Intelligence revolution. NVIDIA's innovation is fueled by its great technology and amazing people. We seek a Senior Power and Thermal Engineer to join our dynamic and fast-paced Silicon Solution Group. As part of the Silicon Solutions Team, we architect and deliver groundbreaking system solutions that integrate all aspects of the system from silicon design, software design to operations and final deployment in multiple market segments that NVIDIA serves. This position offers a unique opportunity to collaborate with multiple organizations in the company and grow your career in a high impact role. We need a passionate, hard-working, and creative individual to architect and productize next generation power and performance controllers.\n\nWhat You Will Be Doing:\nResponsible for developing test methodologies of next generation power and thermal management features and solutions working with multi-functional teams across the company.\n\nDrive board design requirements, FW/SW design requirements to characterize the silicon\n\nCreate methodologies for deployment of features into products.\n\nWork alongside system architects, designers, chip and board designers, software/firmware engineers, HW/SW applications engineering, process/reliability authorities, ATE engineers, and silicon operations, in a fast-paced, high-energy, collaborative work environment to bring industry-defining products to market.\n\nTraining and mentoring highly motivated engineers to solve complex challenges \n\nWhat We Need to See:\nB. Tech or M. Tech in Electronics Engineering, Computer Science, or related field (or equivalent experience)\n\n8+ years of experience in silicon bring-up, validation, and productization.\n\nExperience with control systems, power/thermal controllers and management.\n\nExpertise and deep understanding in the areas of silicon power, transistor/device physics, power modeling and measurement, active power management\n\nProficiency in Python, Perl or C programming languages is a plus\n\nSelf-starter with strong skills in multi-tasking, influencing, communication, presentation, and consensus-building\n\nEnthusiastic, responsive, and keen on process improvement\n\nWith competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our exclusive engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you.\n\nWe are an equal-opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Sr. Design Automation Engineer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-07-16", "url": "https://careers.skyworksinc.com/job-invite/77968/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 77968\n\nDescription\n\nEnable world-class analog and mixed-signal design on heterogeneous process technologies—from compound-semiconductor platforms (HBT, GaAs) to advanced foundry nodes at 22nm and below. You will develop, validate, and release process design kits for some of the most complex technoligies that design teams can trust: accurate models, verified rule decks, and documented design guidelines. Your work will have a direct business impact by enabling  our design teams develop products with some of the most complex technologies on time, defect-free.\n\nResponsibilities\n\nDevelop and maintain PDK components: device models, pcells, technology files, and DRC/LVS/PEX rule decks\n\nValidate PDK releases against foundry documentation, reference structures, and internal design benchmarks\n\nSupport HBT and GaAs process technologies—device characterization, model fitting, and layout-aware design rules for RF applications\n\nEnable foundry technologies at 22nm and above nodes for analog/mixed-signal design IPs\n\nCollaborate with foundries, internal process teams, and design groups to resolve PDK gaps and drive closure on open issues\n\nBuild regression and QA infrastructure for PDK releases; maintain version control and release notes\n\nRequired Experience and Skills\n\nM.Tech/M.E./M.S. in EE/CE or equivalent from a reputed university\n\n3–5 years in PDK development, technology enablement, and CAD/methodology for analog/mixed-signal design\n\nHands-on experience with Cadence Virtuoso flows (OA database, pcells, techfile, rule deck integration)\n\nStrong understanding of semiconductor device physics for analog/RF: MOS, bipolar/HBT, passive structures, and process corners\n\nExperience with DRC/LVS/PEX deck development or validation in a production PDK environment\n\nProficiency in SKILL and/or Python for PDK automation and QA scripting\n\nAbility to read and interpret foundry design manuals, DRMs, and model documentation\n\nDetail-oriented approach to release management, versioning, and issue tracking\n\nDesired Experience and Skills\n\nDirect experience with GaAs or SiGe HBT PDKs for power amplifier, LNA, or switch applications\n\nFamiliarity with BAW/SAW filter process modules or integrated passive device (IPD) technologies\n\nExperience enabling 22nmand up nodes for analog/RF (thick metals, inductors, varactors, high-voltage devices)\n\nBackground in device modeling or correlation between simulation and silicon data\n\nExposure to foundry interfaces \n\nUnderstanding of RF-specific layout effects and EM-aware PDK considerations\n\n#LIPR1\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Senior SOC Verification Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-07-16", "url": "https://careers.arm.com/job/bengaluru/senior-soc-verification-engineer/33099/97861779392", "is_hardware": true, "platform": "talentbrew", "jd_text": "Senior SoC Design Verification Engineer\nAbout Solutions SoC Engineering\nJoin the Solutions SoC Engineering organization and help shape the future of silicon. We are building a world-class engineering organization focused on delivering innovative, high-performance, and energy-efficient SoC solutions that power next-generation computing across diverse markets.\n\nAs a rapidly growing global team, we bring together expertise across architecture, design, verification, emulation, FPGA, software, and post-silicon validation to deliver first-time-right silicon. Our engineers solve some of the industry's most challenging engineering problems using advanced verification methodologies, automation, and AI-driven tools while maintaining the highest standards of quality and execution.\n\nOur culture is built on technical excellence, ownership, collaboration, and continuous learning. We invest in our people, encourage innovation, and provide opportunities to influence engineering methodologies, contribute across the product lifecycle, and grow alongside an organization that is defining the future of SoC engineering.\nRole Overview\nAs a Design Verification Engineer, you will verify complex Arm-based IPs, subsystems, and SoCs powering next-generation computing platforms. You will develop scalable verification solutions, own end-to-end verification execution, and contribute to advanced SoC methodologies.\nKey Responsibilities\nDevelop and execute verification strategies for IP, subsystem, and SoC designs.\nVerify CPU, PCIe, DDR, Security, coherency, memory subsystem, and interconnect functionality.\nPerform power-aware verification and system scenario/performance validation.\nOwn verification deliverables from planning through verification closure while ensuring quality, schedule, and execution commitments are met.\nArchitect, develop, and maintain reusable verification environments, verification IPs, methodologies, and automation.\nDevelop verification plans, test methodologies, test cases, and coverage closure strategies.\nDrive functional, code, toggle, assertion, and coverage closure.\nDebug RTL, testbench, integration, and system-level issues.\nCollaborate with architecture, design, firmware, emulation, FPGA, validation, and post-silicon teams.\nLeverage automation, scripting, and AI-assisted workflows to improve verification productivity.\nContribute to methodology improvements, documentation, and engineering best practices.\nRequired Skills and Qualifications\nBachelor's or Master's degree in a relevant engineering discipline.\n4–9 years of IP, subsystem, or SoC verification experience.\nStrong Verilog, SystemVerilog, UVM, and modern verification methodologies.\nExperience with Arm-based SoC architecture, coherency, interconnects, memory hierarchy, and UPF.\nExperience with C/C++, scripting, coverage closure, and strong RTL/testbench debug.\nExcellent analytical, communication, and collaboration skills.\nDesired Skills and Qualifications\nExperience with CHI, ACE, AMBA, PCIe, DDR, or Security IP.\nArm System Architecture knowledge.\nAssembly programming.\nFormal verification, emulation, FPGA, gate-level simulation, or post-silicon validation.\n \n#LI-PS1\nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Analog Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-07-16", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009778", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\n This is a great opportunity to be part of an established team that's continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electronics, mobile computing and communications.\n\nIn this role, responsibilities may include:\n\nDesign of I/O circuits like GPIOs (failsafe, non-failsafe), level shifters, LVDS I/O, bandgap, LDO, multi-voltage buffers etc and optimize for power/performance/area\n\nEnsure design robustness through comprehensive PVT corner simulations, reliability analysis,  monte carlo analysis.\n\nPost layout simulations and ability to debug and provide guidance to the layout engineer as needed\n\nDetailed analysis and documentation of the verification data\n\nUnderstanding and providing inputs on dotlibs, verilog, Ibis data generation\n\nCollaborate with cross functional team to enable seamless integration of IP at SoC\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in Electrical Engineering\n\n2 years of relevant experience\n\nPreferred qualifications:\n\nStrong understanding of CMOS transistors, short channel effects etc.\n\nExperience in design of I/O types (Failsafe and Non-Failsafe), multi-voltage design, LVDS\n\nKnowledge of ESD protection schemes, I/O standards, dotlibs, verilog, IBIS\n\nOptimize I/O for performance, power, area\n\nAble to run comprehensive PVT corner simulations, reliability analysis,  monte carlo analysis, and signal integrity checks (crosstalk/ISI)\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Staff Analog Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-07-16", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2504268", "is_hardware": true, "platform": "oracle", "jd_text": "Description for Internal Candidates    \n\n  onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nonsemi’s Core-Analog IP Center of Excellence is hiring an experienced Analog IC design engineer to help us develop IP for next generation Automotive, Industrial & Medical products. The successful candidate will participate in the design of complex CMOS integrated circuits and have familiarity with analog blocks such as bandgaps, amplifiers, filters, precision comparators, LDOs, oscillators, PLLs etc. Experience with signal chain optimization is highly desired.\n\n#LI-VS1\n\nResponsibilities\nDescription for Internal Candidates    \nKey Duties & Responsibilites\nMust have a working knowledge of Cadence Circuit design tools.\n15+ years of relevant experience or Ph.D. in Electrical Engineering with  13+ years of relevant experience in analog circuit design.\nAnalytical approach to problem solving is required. CMOS designs provide challenging learning opportunities where performance, power and reliability are all pushed to the limit while maintaining product execution schedule.\nDrive development and verification of state-of-the-art analog blocks and mixed signal CMOS designs which can be reused across different market segments.\nParticipate in analog circuit requirements discussions, technical issues and other design aspects to arrive at agreed upon product specifications.\nBuild/develop circuits based on an IP specification, drive the layout design and final IP characterization.\nExecute state-of-the-art analog designs while following the best design practices with on time quality design releases.\nPropose innovative and creative solutions where necessary to meet customer & product needs.\nWork diligently with the  given requirements to accomplish project goals and meet schedule requirements.\nDebug of complex integrated circuit problems in the laboratory. Collaborate in debug efforts as needed.\nPerform bench characterization and support application engineering bench evaluation efforts.\nAnalyze design aspects related to DFT and collaborate with other team members to develop DFT strategy for block designs.\nDocument designs including architecture and circuit descriptions, testing procedures, and safety mechanisms.\nInterface with test, product, and applications engineering to drive the design to a successful production release.\n \n#LI-VS1\n\nQualifications\nRequirements    \nAnalog design experience in verification, documentation, and post-silicon validation. Includes broad understanding of integrated circuit design such as amplifiers, filters, BGAP circuits, oscillators etc.\nIn-depth knowledge of semiconductor devices like MOS transistors, BJTs etc.\nKnowledge with behavioral top-level modeling and mixed signal verification methodology.\nKnowledge of UNIX/Linux working environment\nKnowledge of multiple semiconductor design tools like Matlab, Spectre, Spice, Cadence design environment. AMS simulation experience is a plus.\nExcellent written and oral communication.\nProven ability to work independently and in teams.\nHands-on experience in a lab environment working with sensitive measurement equipment and data acquisition.\nVery good debugging ability in circuit operation, and device function\nMaster’s degree in Electrical Engineering with  15+ years of relevant experience or Ph.D. in Electrical Engineering with  13+ years of relevant experience in analog circuit design.\n\n#LI-VS1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Non-Volatile Memory - NVM Architect", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-07-16", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505968", "is_hardware": true, "platform": "oracle", "jd_text": "Senior NVM Architect (EEPROM / ReRAM / Flash)\n\nPosition Summary\n\nWe are seeking an experienced Non-Volatile Memory (NVM) Architect to lead the definition, architecture, and development of next-generation embedded memory IP solutions for automotive, industrial, AI, and mixed-signal SoCs. The ideal candidate will possess deep expertise in EEPROM, ReRAM, or Embedded Flash technologies and have a proven track record of delivering silicon-proven memory architectures from concept through production.\n\nThis role requires strong technical leadership across device technology, memory architecture, circuit design, compiler development, reliability, and product integration while working closely with process development, analog, digital, verification, layout, product engineering, and system architects.\n\n#LI-VS1", "jd_status": "source_unavailable"}, {"title": "Principal Engineer, Subsystem CoE Emulation", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-07-16", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Principal-Engineer--Subsystem-CoE-Emulation_2601474", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nThe Custom Compute and Storage (CCS) Business Unit collaborates with strategic customers\nto develop advanced SoCs—from architecture through production.\nThe Emulation Center of Excellence (CoE) plays a critical role in:\n• Delivering scalable emulation infrastructure\n• Enabling pre-silicon validation\n• Driving software readiness and post-silicon success\nIn this role, you will lead and contribute to emulation of key subsystems including:\n• Boot and Security\n• High-speed interfaces: PCIe, CXL, Ethernet\n• Memory subsystems: DDR, HBM\n• Low-speed peripherals: SPI, I2C, UART\n• USB 3.0\nWhat You Can Expect\n• Strong experience in SoC emulation, validation, and debug\n• Expertise in one or more domains:\no Boot flow and system initialization\no Security architecture and validation\no High-speed protocols: PCIe, CXL, Ethernet\no Memory interfaces: DDR, HBM\no Peripheral interfaces: SPI, I2C, UART, USB 3.0\n• Deep understanding of SoC architecture, interconnects, and system-level integration\n• Hands-on experience with emulation platforms (Palladium, ZeBu, Veloce)\n• Strong debugging skills across HW/SW boundary\n• Proficiency in scripting: Python, Perl, Tcl, Shell\n• Proven ability to lead cross-functional efforts and drive execution\n\nWhat We're Looking For\n• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience.\n\nWhat You Can Expect\n• Lead the development of complex SoC emulation models, including design\nintegration, environment setup, compilation, and debug across industry-leading platforms\n(e.g., Veloce, ZeBu, Palladium).\n• Drive emulation bring-up activities, including clock/reset sequencing, firmware boot,\nand system validation using pre-silicon hardware models.\n• Create and execute emulation test plans to support verification, performance\nanalysis, software development, and system validation needs across multiple teams.\n• Collaborate closely with RTL design, verification, and firmware teams to define\nrequirements, develop accurate hardware models, and ensure seamless integration into\nthe emulation environment.\n• Debug complex SoC and subsystem issues across RTL, firmware, emulation\nplatforms, and toolchain interactions.\n• Optimize emulation performance, including model partitioning, timing, and runtime\nefficiency.\n• Automate flows and improve productivity through scripting (Python, Perl, Tcl, shell)\nand tooling enhancements.\n• Interface with EDA vendors (Synopsys, Cadence, Siemens) to evaluate tool\ncapabilities, resolve technical issues, and drive feature improvements.\n• Define and execute emulation strategy for complex SoCs across multiple subsystems\n(Boot, Security, PCIe, CXL, DDR, HBM, USB, Ethernet, and peripherals)\n• Develop and drive subsystem-level and full-chip emulation test plans\n• Enable pre-silicon validation of firmware, boot flows, and security features\n• Collaborate with cross-functional teams to bring up and debug:o PCIe / CXL link and protocol issues\no DDR / HBM initialization and performance validation\no Ethernet and USB 3.0 integration\no Low-speed peripheral functionality (SPI, I2C, UART)\n• Enable firmware and software teams by providing stable and scalable emulation\nenvironments\n\nAdditional Compensation and Benefit Elements\nWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\n\nInterview Integrity \nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\n\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\n\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n\n#LI-RV1", "jd_status": "stored"}, {"title": "Staff Validation Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-07-16", "url": "https://careers.arm.com/job/bengaluru/staff-validation-engineer/33099/97861779344", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Description: DDR Functional Validation Engineer\nRole Overview\nWe are looking for a DDR Functional Validation Engineer with 3 to 8 years of experience in silicon validation, memory subsystem debug, and firmware-based validation. The candidate will be responsible for validating DDR memory interfaces on complex SoC platforms, executing test plans, developing test cases, debugging silicon issues, and supporting silicon bring-up activities.\nThis role requires strong knowledge of DDR4, DDR5, LPDDR5, and LPDDR6 protocols, along with a good understanding of memory controller and PHY architecture. The ideal candidate should be comfortable working across hardware, firmware, and system-level validation environments.\nKey Responsibilities\nPerform functional validation of DDR memory subsystems on pre-silicon and post-silicon platforms.\nExecute validation test plans for DDR4, DDR5, LPDDR5, and LPDDR6 interfaces.\nDevelop, enhance, and maintain validation test cases for memory controller, DDR PHY, training flows, initialization sequences, low-power features, and system-level stress scenarios.\nSupport silicon bring-up activities, including DDR initialization, boot flow debug, memory training debug, and platform stabilization.\nDebug silicon issues related to DDR functionality, timing, training failures, memory errors, system hangs, boot failures, and performance anomalies.\nWork closely with architecture, design, firmware, platform, and signal integrity teams to identify root causes and drive issues to closure.\nDevelop and debug firmware used for DDR initialization, training, configuration, and validation.\nAnalyze validation failures using logs, traces, register dumps, firmware debug messages, protocol analyzer outputs, oscilloscopes, logic analyzers, and other debug tools.\nValidate memory controller and PHY features across different operating frequencies, voltage corners, power states, and stress conditions.\nCreate and maintain validation documentation, including test plans, test case specifications, debug notes, issue reports, and execution summaries.\nParticipate in reviews of DDR architecture, controller features, PHY behavior, firmware flows, and validation coverage.\nExecute system stress scenarios involving memory bandwidth, concurrency, thermal stress, voltage/frequency scaling, low-power entry/exit, and long-duration stability testing.\nCollaborate with cross-functional teams to improve validation coverage, debug methodology, and automation infrastructure.\nTrack validation progress, report issues clearly, and support defect triage through bug tracking systems.\nRequired Qualifications\n3 to 8 years of experience in silicon validation, post-silicon validation, platform validation, firmware validation, or memory subsystem validation.\nStrong understanding of DDR4, DDR5, LPDDR5, and/or LPDDR6 protocols.\nHands-on experience with DDR functional validation, silicon debug, test execution, and failure analysis.\nExperience in test plan execution and test case creation for memory subsystem features.\nGood understanding of memory controller and DDR PHY architecture.\nExperience with silicon bring-up, board bring-up, or SoC/platform bring-up.\nKnowledge of DDR initialization, memory training, boot flows, and firmware-controlled configuration sequences.\nExperience in firmware development, firmware debug, or low-level embedded software validation.\nBasic understanding of signal integrity concepts such as timing margins, eye diagrams, impedance, jitter, noise, voltage margins, and board-level effects.\nAbility to debug complex hardware, firmware, and system-level issues.\nFamiliarity with system stress validation, including memory stress, power stress, boot stress, reset stress, and long-duration stability scenarios.\nBasic coding skills in C, Python, or scripting languages for test development, automation, log parsing, and debug support.\nAbility to read and understand technical specifications, register descriptions, memory datasheets, protocol documents, and architecture documents.\nStrong analytical, debugging, and problem-solving skills.\nGood communication skills and ability to work with cross-functional teams.\n \nTechnical Skills\nDDR Protocols: DDR4, DDR5, LPDDR5, LPDDR6\nValidation Areas: Functional validation, silicon validation, platform validation, system validation\nDebug Areas: Silicon debug, firmware debug, boot debug, memory training debug, system hang debug\nArchitecture Knowledge: Memory controller, DDR PHY, SoC interconnect basics, boot flows\nFirmware: Low-level firmware development, register programming, initialization sequences\nProgramming/Scripting: C, Python, Perl, Shell scripting, or equivalent\nTools: JTAG debuggers, oscilloscopes, logic analyzers, protocol analyzers, lab debug tools\nTest Areas: Test plan execution, test case creation, regression testing, stress testing, corner testing\n \n#LI-PS2\n \nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Sr Staff Engineer, Digital Design", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-07-15T11:04:04.057000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000137861794-sr-staff-engineer-digital-design", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are looking for a motivated and talented Digital Designer to join our team in creating next-generation Power management solutions. We are looking for a visionary designer to lead the transition from traditional PMICs to Intelligent Power Systems. You will take full ownership of the design cycle, from architecture definition till Tapeout.\nCore Responsibilities\nOwnership of Digital Micro architecture : Develop optimized sub-block architectures, translating complex requirements into efficient RTL and gate-level netlists. Create New IP solution distributed between Analog and digital.\nMust have experience of designing complex state machines, Power sequencers, various control loops and data processing modules.\nLead silicon debug, perform root-cause analysis, and drive design-to-silicon correlation to ensure first-pass success.\nDeep expertise in power-sensitive digital design, power estimation,  CDC ( clock domain crossing), Lint flows.\nKnowledge of OTP, Efuse controllers, various memories controllers.\nMastery of communication protocol, I2C, SPI, PMBUS, SVI3, and SVID. You are expected to build High speed, low pin count custom Interface solution.\nShould be able to implement and analyse filters & feedback loops in Digital, conversant with Z-domain analysis.\nProficient with front end flows and RTL coding using Verilog.\n\nMinimum Requirements:\nBachelor’s or master’s degree in electronics or electrical engineering.\n3 to 14 years in Digital Design and experience of working on Mixed Signal ICs. \nDeep understanding of the complete digital design flow from Spec to tape out.\nStrong command of Verilog / SystemVerilog for design.Critical Analysis.\nHands-on experience with CDC analysis, Low power design techniques.\nSelf-motivated with strong communication skills, capable of working effectively in a team environment.\nMust be a technical leader, team player, mentor and should strive towards fostering a highly creative and productive working environment\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "PLATFORM EMULATION ENGINEER", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-07-15T08:40:00+00:00", "url": "https://global-external-amd.icims.com/jobs/88446/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. PLATFORM EMULATION ENGINEER   THE ROLE:  AMD is seeking a Platform Emulation Engineer to join our Data Center GPU organization. Our products support the rapidly scaling Data Center and High-Performance Compute infrastructure. You will be an integral member of the Platform emulation team responsible for emulation infrastructure development, execution and debug of critical firmware used in our HPC and ML products, developing test plans and execute test cases to enhance silicon test coverage, train and support validation teams on emulation technology, build and execute industry standard HPC benchmarks and applications on the emulator.   THE PERSON:  As a platform emulation engineer you will have an opportunity to work on bleeding edge SoC architecture and technology and participate in development of emulation infrastructure to enable pre-silicon activities to ensure high quality Silicon and fast time to market. You will work alongside our team of innovative engineers to support the deployment of AMD’s Instinct ML products targeting Supercomputers and Data Center workloads.    KEY RESPONSIBILITIES:  CPU/GPU Firmware/OS bring up and debug using leading edge emulators (Veloce, Zebu, Palladium) Develop/modify/enhance functional/stress tests to find silicon bugs on emulator Validate features in firmware including but not limited to RAS, Resets, Power management, Secure boot, Virtualization Validate multi-socket configurations in emulation using firmware Bring up the full AMD graphics software stack in emulation Bring up ML/AI applications in emulation – Collaborate with workloads and SW teams, run apps in multi-socket configurations, collect and interpret results for debug and tuning Checkout of IP features in software simulation model as a pre-step for emulation Interface with Central Emulation team responsible for helping to develop, debug and establish CPU/GPU Emulation environment Provide debug leadership, input to test plans and hands on execution Work with extended teams to debug environment, drive cross team testing (Firmware, Software, Diags/tools, Validation, Apps) Triage failures with design, verification, firmware, software, and emulation teams Research and enable new tools and infrastructure to support emulation activities Run and collect data for analysis on AMD’s high-end emulators and simulation models Develop scripts/tools to parse data from emulation runs Instrument firmware code to support failure debug Run and collect functional and performance data for HPC workloads Attend weekly meetings, status communication, presentations.   PREFERRED EXPERIENCE:  Solid experience working on emulation platforms such as Veloce, Zebu, or Palladium (compilation, debug, performance, and throughput tuning) Debugging experience is a must particularly in HW/SW co-debug environments and Hybrid Emulation environment with Emulation transactors. Ability to trace code across multiple domains and root cause using waveforms and other tracing tools Understanding of Verilog, VHDL design Understanding of System Verilog, DPI, UVM verification environments is a plus Knowledge of computer hardware architecture (Graphic card, CPU/APU, memory, bus logic, and display technologies) Knowledge of computer software architecture and boot flow (bootrom, firmware, bios, device drivers, OS) Knowledge of secure platform concepts such as Root of Trust, Chain of Trust, FW signing, encryption Knowledge of platform management HW and SW components such as BMC, SMC and board management software libraries Knowledge of HPC, Parallel programming (OpenMP, OpenMPI), heterogeneous platforms consisting of CPU and GPU a plus Working knowledge of Linux/Unix environment and shell scripting Experience in Building and Installing software packages on Linux platform a plus Programming skills, C, C++, Python, Tcl, Ruby, assembly (ARM & x86) Familiarity with bug tracking tools such as Jira Excellent oral and written communication skills   ACADEMIC CREDENTIALS:  Bachelors or Masters degree in electrical, electronics or computer engineering with 7+Yrs of exp #LI-PK1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "RTL Design(Peripheral)-Sr Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-15T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718635551", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    12+ years of Hardware Engineering or related work experience.\n•    3+ years of experience with circuit/logic design/validation (e.g., digital, analog, RF).\n•    3+ years of experience utilizing schematic capture and circuit stimulation software.\n•    3+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test highly critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Participates in or leads the implementation of advanced design rules and processes for electronic hardware, equipment, and/or integrated circuitry.\n•    Conducts highly complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops novel manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of highly critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Advises and leads engineers in the development of complex hardware designs, evaluating various design features to identify potential flaws or issues.\n•    Writes detailed technical documentation for highly complex Hardware projects; reviews technical documentation for junior engineers.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making is significant in nature and affects work beyond immediate work group.\n•    Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. \n•    Has a moderate amount of influence over key organizational decisions.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Sr Lead Engineer - GPU PostSi Validation", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-15T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446717775906", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    5+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SoC Thermal Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-15T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719729656", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nJob Title: SoC Thermal Engineer\nSOC Thermal analysis methodology development: encompassing SoC, package and systems, for various Qualcomm products going into smartphones, laptops, automotives and virtual reality headsets. \nDeveloping strategies to predict and improve thermally constrained scores (AnTuTu/Geekbench) and also measure/tune it on post-Si platforms, including infrared imaging.\nThermal measurement : The candidate will be responsible for improving thermal mitigation strategies through power and thermal management to achieve optimal system thermal performance.\n\nSkills:\nShould possess strong analytical skills and mathematical modeling abilities.\nProvide thermal analysis throughout the SoC product development cycle to identify and mitigate thermal risks, including post-silicon validation and customer collaboration.\nPerform SoC-level thermal analysis to support architecture, product specifications, and Power-Performance-Area-Thermal optimization. Recommend thermal mitigation strategies.\nDevelop advanced thermal methodologies, software tools, and scalable processes; collaborate with cross-functional teams to drive efficiency and achieve goals.\nKnowledge of SOC stack up is must\nGood knowledge of scripting in PERL/Python required; some exposure to Machine Learning algorithms/frameworks will be a plus.\nNeed to have thorough knowledge of heat transfer mechanisms and CFD.\nProficiency with state-of-the-art thermal analysis tools – Ansys Icepak/Flotherm\nThermal Measurement will be preferred skill \n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Principal Engineer Analog CAD & AI", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-15T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/40823720", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nRole Summary -\n\nResponsible for developing and implementing end-to-end AI workflows for Analog IP creation, including schematic generation, layout, design optimization, simulation, verification, and signoff at advanced FinFET nodes using available EDA AI tools and collaborating with Data Science teams throughout all phases.\n\nJob Requirements -\n\n15+ years of experience in defining Analog and Digital design methodologies and flows.\nStrong proficiency in Python, SVRF, SKILL scripting for CAD and automation.\nStrong understanding of transistor-level circuit design, including device behavior, biasing, matching, noise, and variability.\nProven experience architecting custom design and verification methodologies for mixed-signal IPs.\nB.Tech / M.Tech / MS in VLSI Design, Microelectronics, or a related field.\nPrior experience applying AI/ML in EDA or design automation is a strong plus.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Design Implementation - Synthesis Engineer, Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-15T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719278268", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nMinimum Qualifications\n\no 4+ Year of industry experiences in the following areas: Expertise in Synthesis - Synopsys Design Compiler, DCG/DC_NXT/Fusion Compiler and/or Cadence RC/Genus.\no Expertise on with multi-voltage, power aware synthesis, UPF flows in synthesis and low power designs.\no Expertise in formal verification with Cadence LEC/ Synopsys Formality\no Expertise in writing and debugging timing constraints\no Perl and/or TCL scripting, makefile flows.\n\nAdditional Job Description\nMasters in Electronics or Electrical Engineering\n\nwork on integration or RTL design is considered plus.\n\nCandidates should have excellent analytical and problem-solving skills\n\nTrack record of driving ideas from design through commercialization  \n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Synthesis Engineer, Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-15T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446715441278", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nMinimum Qualifications\no 4+ Year of industry experiences in the following areas: Expertise in Synthesis - Synopsys Design Compiler, DCG/DC_NXT/Fusion Compiler and/or Cadence RC/Genus.\no Expertise on with multi-voltage, power aware synthesis, UPF flows in synthesis and low power designs.\no Expertise in formal verification with Cadence LEC/ Synopsys Formality\no Expertise in writing and debugging timing constraints\no Perl and/or TCL scripting, makefile flows.\n\nAdditional Job Description\nMasters in Electronics or Electrical Engineering\nwork on integration or RTL design is considered plus.\nCandidates should have excellent analytical and problem-solving skills\nTrack record of driving ideas from design through commercialization  \n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RTL Design Engineer (Peripheral)- Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-15T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446714872343", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Description\nResponsibilities will include\nTo be strong designer who is able to work independent on one of the peripheral IP’s\ncome up with design and microarchitecture solutions\nguide/mentor juniors\nengage with external teams to drive/resolve cross team dependencies.\nTake complete responsibility of one or more project and drive that independently.\nBeing able to make schedule estimates is a plus.\nPeople management experience is a plus\n \nSkills & Requirements needed\n8 to 10 years of work experience in ASIC IP cores design\nRequired: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering\nKnowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB/PCIE/Ethernet preferred.\nWork closely with the SoC verification and validation teams for pre/post Silicon debug\nHands on experience in Low power design is required\nHands on experience in Multi Clock designs, Asynchronous interface is a must.\nExperience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.\nUnderstanding of constraint development and timing closure is a plus.\nExperience in Synthesis / Understanding of timing concepts is a plus.\nStrong experience in micro architecting RTL design from high level design specification.\nExcellent problem solving skills, strong communication and team work skills are mandatory.\nSelf-driven, needs to work with minimum supervision.\nExperience in System Verilog, Verilog, C/C++, Perl and Python is a plus\nAbility to lead a small design team.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "IP Physicial design  engineer (Sr. Lead/Staff)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-15T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719748220", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nJob Description\n6 to 10 years of relevant experience in Physical Design\n\nExtensive hands-on experience in the Physical Design flow, including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification.\n\nStrong expertise in timing closure using PrimeTime and/or Tempus, with a thorough understanding of setup/hold analysis, OCV/POCV methodologies, clocking architectures, and STA signoff.\n\nProven experience working on advanced technology nodes and delivering IP-level Physical Design solutions, including end-to-end ownership from netlist to GDS.\n\nDemonstrated ability to analyze, debug, and resolve timing, congestion, DRC/LVS, EM/IR, and integration-related challenges.\n\nFamiliarity with Mixed-Signal and High-Speed IPs, with the ability to collaborate effectively across Front-End, CAD, STA, and signoff teams.\n\nExcellent analytical and problem-solving skills, with strong attention to detail and the ability to manage multiple programs within demanding project schedules.\n\nStrong automation and scripting capabilities; familiarity with AI-driven methodologies and applications in design flows is considered an advantage.\n\nProficiency in Tcl and Python scripting for flow automation, data analysis, and design debug, driving improved efficiency and productivity.\n\nHands-on experience with industry-leading EDA tools for Physical Design and signoff, including place-and-route, STA, and physical verification tools.\n\nEffective communication and stakeholder management skills, coupled with a collaborative, team-oriented approach to driving cross-functional execution and closure.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Power Design (Turing) - Sr Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-15T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719374031", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    3+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n\nPrincipal Duties and Responsibilities:\n•    Applies Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Assists in the assessment of complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Technical Staff Engineer – Emulation", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-07-15", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Senior-Technical-Staff-Engineer---Emulation_R3015-26", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nRole Overview\nThe chosen candidate will be part of the FPGA Solutions Engineering team, working closely with internal engineering teams and external customers to architect, validate, and deliver next-generation IP cores and system-level platforms. This role bridges the gap between hardware architecture, advanced emulation methodologies, and firmware co-design to enable early silicon-equivalent bring-up and accelerate time-to-market.\nJob Description\nKey Responsibilities\nArchitect Veloce RTL models and UVM-acceleration for EdgeAI, PCIe, Ethernet, DDRC, etc.\nBuild CAD execution flows, develop high-fidelity emulation models, Veloce XACTORs, and system-level use cases to drive deep performance and architectural validation on emulation platforms.\nEngineer shift-left, end-to-end solution development by integrating hard and soft IP RTL with bare-metal firmware on emulation systems.\nDevelop system bring-up frameworks, debug complex RTL/firmware issues, and accelerate time-to-market through comprehensive hardware-software co-validation.\nProvide technical feedback to Silicon Engineering, Software Engineering, and Marketing to enhance future product roadmaps. Provide expert pre- and post-sales design support to customers and sales forces.\n\nRequirements/Qualifications:\n\nEducational & Experience Requirements\nEducation: BSEE / MSEE or equivalent technical degree.\nExperience: A minimum of 10+ years of progressive experience in hardware emulation, RTL design, FPGA methodologies, or HW/SW co-verification.\nTechnical Expertise\nStrong proficiency with Veloce platforms, VirtuaLAB environments, UVM-acceleration, and SystemC-DPI testing methodologies.\nProficient in Verilog, System Verilog, C/C++, RTL synthesis concepts.\nDeep understanding of high-speed IPs including PCIe, Ethernet, DDR3/4/5/, AMBA AHB/APB, SERDES, and USB.\nStrong foundation in DSP theory/processor architectures and embedded processors (e.g., ARM Cortex platforms) is highly desirable.\nWorking knowledge of leading FPGA architectures (e.g., Microsemi, Xilinx, Altera, Lattice) and debugging physical boards.\nProfessional Skills\nStrong analytical and problem-solving skills with a proven ability to debug complex, full-stack hardware-software issues and drive them to closure.\nExcellent written and verbal communication skills for authoring documentation, training modules, and presenting to executive customers.\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Principal SoC Physical Implementation/STA Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-07-15", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Principal-SoC-Physical-Implementation-STA-Engineer_R-10064253", "is_hardware": true, "platform": "workday", "jd_text": "Job Qualification:\n Experienced Static Timing Analysis (STA) Lead with 12+ years of experience doing STA for SoCs and Blocks.\nHe/She should have experience of Multi mode timing constraint development, execution, and final timing signoff for advanced technology nodes.\nHe/She will work closely with Architects,Front End,DFT and the PD team to understand design,clocking,timing ,Requirements and lead the writing constraints and closing timing activities\n\nKey Responsibilities\nConstraint Development: Create, validate, and maintain Synopsys Design Constraints (SDC) for block and full-chip levels, covering false paths, multicycle paths, and test modes.\nTiming Signoff: Perform exhaustive timing analysis across multiple corners and modes (MCMM), adhering to process, voltage, and temperature (PVT) variations.\nViolation Debugging: Debug and resolve setup, hold, transition, and path-based violations (PBA).\nOptimization & ECO: Drive timing closure by generating and evaluating timing Engineering Change Orders (ECOs).\nCross-functional Collaboration: Partner with RTL, physical design, and DFT teams to ensure robust timing integration and refine timing models.\nTool & Flow Automation: Develop and support implementation flows using industry-standard Electronic Design Automation (EDA) tools and improve script-based automation.\nDebugging timing issues from GLS\nDrive a team of STA engineers.\n\nMore information about NXP in India...\n\n#LI-7013", "jd_status": "stored"}, {"title": "Staff Engineer, Design Verification Engineering", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-07-15", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Staff-Engineer--Design-Verification-Engineering_R263858", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nJob Responsibilities:\nVerification of complex designs such as accelerators/ datapath IP, processor core subsystems, complex interfaces/ protocols such as DDR/ Ethernet/ USB etc using leading edge methodologies like UVM & Formal DV\nArchitect the testbench and develop the verification environment in UVM and Formal based verification approaches\nDefine testplan, tests and verification methodology for block / sub-system level verification. Work with design team in generating test-plans and closure of code and functional coverage. Integrate the block testbench at sub-system level UVM environment and verify integration. Interact with analog co-sim and firmware team in enabling toplevel chip verification aspects\nPackage verification environment for Digital IP for seamless integration into verification flow at different stages of execution\nEvaluate 3rd party IPs on key qualitative aspects such as design quality, robustness of Design Verification (DV) practice, ease of DV environment integration and make recommendations. Establish evaluation flows for home-grown & 3rd party IPs for consistent benchmarking of DV evaluation\nBuild expertise on complex interfaces, peripherals & protocols such as DDR, Ethernet, eMMC/ SD, MIPI, Display Port, HDMI, PCIe, high speed D2D\nSupport post-silicon verification activities of the products working with design, product evaluation and applications engineering team\n\nPosition Requirements:\nMinimum B.E./ B.Tech degree in Electrical/Electronics/Computer science\n6 - 10 years experience in design verification with UVM and constrained random, coverage-based verification approaches\nStrong understanding of DV concepts with an eye on developing scalable DV environment architecture that realizes first pass DV success\nExperience with translating Design Verification (DV) requirements such as test plans into a robust DV environment and generate coverage metrics for demonstrating DV convergence\nExperience with AI tools in DV\nAdaptability to learn end application/systems and map into smart verification test plans\nExcellent debugging and analytical skills\nGood interpersonal, teamwork and communication skills to logically & effectively drive discussions with teams spread geographically\nKnowledge of Assertion based formal verification\nUnderstanding of standard on-chip interfaces such as APB/AHB/AXI/ Stream protocols is a strong plus\nKnowledge of Processor/SoC architecture and/or DSP fundamentals is a strong plus\nExperience with ASIC/ SoC product DV & productization is very desirable\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Physical Design Engineer- CPU/GPU", "company": "MediaTek", "location": "Bangalore", "date_posted": "2026-07-14T16:00:00+00:00", "url": "https://careers.mediatek.com/en/jobs/MTB120260417000", "is_hardware": true, "platform": "mediatek", "jd_text": "CPU/GPU R2G Engineer\nResponsible for RTL to GDS design and development activities of MediaTek’s Ghz ARM/Imagination-based graphics processors, AI processors and neural network DS.\n\nInvolve in activities encompass physical design and analysis of complex and timing-critical graphics processor AI processors and neural network DSP.\n\nTechnical disciplines include Physical Implementation (floor-planning, place and route, RC extraction, timing and power optimization) & signoff (DRC, LVS, STA, PI).", "jd_status": "stored"}, {"title": "Regional Field Applications Lead - FPGA", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-07-14T07:14:00+00:00", "url": "https://global-external-amd.icims.com/jobs/86314/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Key Responsibilities : Represent AMD to engage at customer high level leadership, with preferably deep understanding of Indian Government, Defence, and Academia organizations Build, Establish and Expand Technical Relationships with Key Customers' Stakeholders across India Partner with both internal teams and channel partners to Qualify Leads, Identify Customer's Pain Points and Propose Solutions to meet customer's business goals Lead the Qualification process through Demos, Presentations, Architecture designs and Technical workshops Participate in business and detailed technical discussions at all levels of the customer's organization to foster adoption of FPGA, RFSoC, AI and Embedded x86 solutions Develop and Expand customer base across India to ensure a healthy pipeline of opportunities for growth Provide constant feedback and insight to internal stakeholders regarding competition, product, and market trends in the Indian market Requirements Bachelor's Degree in Electronics, Electrical Engineering, Computer Science or related field with 10+ years of working experience At least 5 years of hands-on engineering experience in FPGA, RFSoC, Firmware and Software development using VHDL, Verilog, C/C++ and Python Experience with Embedded x86 platforms and ecosystems is a strong advantage Good knowledge of Machine Learning and Artificial Intelligence, with exposure to AI deployment on adaptive computing or embedded platforms preferred Strong business acumen with the ability to work independently towards business goals Excellent communication and presentation skills in English; proficiency in Hindi or any regional Indian language is a plus Based in Bangalore, India with 25-40% travel within India and occasional travel for global internal events #LI-NS2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "MTS DRAM ASIC Architect", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-14T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/42021990", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nDRAM ASIC Architecture\n\nRole Overview\nMicron is seeking an experienced architect to drive the definition of next-generation DRAM products incorporating advanced CMOS-based logic die technologies.\nThis role will help define how future DRAM products leverage advanced CMOS logic die technologies to enable higher levels of integration, observability, reliability, power efficiency, security, and system differentiation beyond what is achievable in conventional DRAM-only implementations. The architect will define architectures that leverage advanced logic die capabilities to complement and enhance DRAM functionality across LPDDR, DDR, HBM and future heterogeneous memory solutions.\nThe successful candidate will architect I/O, reliability, manageability, interface, test and system-enhancement functions. The role requires strong collaboration across DRAM design, ASIC architecture, packaging, process technology, product engineering, validation, firmware, and system architecture teams.\n\nKey Responsibilities\nDefine next-generation DRAM + logic-die architectures, including functional partitioning between DRAM arrays, peripheral circuitry, and advanced CMOS logic die platforms – to optimize performance, power, cost, reliability, and product differentiation.\nIdentify and evaluate system, interface, reliability, test, management, and control functions that may benefit from advanced logic-die implementations; perform architectural tradeoff analysis covering area, power, latency, yield, testability, reliability, and product scalability.\nDefine scalable CMOS logic-die architectures and subsystem solutions using a combination of custom, semi-custom, and standard IP solutions.\nArchitect high-performance interfaces between DRAM die and logic die, including command, data, clocking, synchronization, test, monitoring, and management paths.\nIdentify emerging opportunities & influence roadmaps for advanced memory system capabilities.\n\nMinimum Qualifications\nBS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related discipline with 5+ years of experience in semiconductor architecture, design, or system engineering.\nExperience in one or more of the following areas: DRAM architecture, memory subsystem architecture, ASIC/SoC architecture.\nGood understanding of DRAM architecture including command flows, timing behavior, bank architecture, refresh management, row hammer mitigation, reliability features, and memory subsystem operation.\nExposure to high-speed I/O, PHY architectures, clocking systems, SI/PI considerations, power delivery, thermal design, and/or die-to-die interfaces.\nDemonstrated ability to lead cross-functional technical discussions, develop architectural proposals, and drive tradeoff-based decision making.\nStrong analytical and problem-solving skills.\nAbility to drive architecture tradeoff studies across multiple engineering disciplines.\nExcellent written and verbal communication skills.\n\nPreferred Qualifications\nExperience with DDR5/DDR6, LPDDR5/LPDDR6, HBM, GDDR, or emerging memory technologies with strong understanding of memory protocols, timing architectures, memory training, calibration, and PHY design.\nExperience evaluating architectural tradeoffs across DRAM die, logic die, advanced packaging, and system-level implementations.\nExperience with die-to-die interconnect technologies including TSV-based architectures, hybrid bonding, 2.5D/3D packaging, stacked-die systems, and advanced memory integration.\nStrong knowledge of CMOS technologies, semiconductor device fundamentals, analog/mixed-signal circuit concepts, and memory interface design.\nUnderstanding of SI/PI, clocking, power delivery, thermal considerations, and heterogeneous integration challenges.\nExperience working with industry standards organizations, customers, or ecosystem partners related to memory technologies.\nExperience with HBM base die architectures, embedded controllers, advanced memory system features, RAS, security, or logic-die-based memory products.\nProven ability to leverage AI‑assisted (vibe) coding techniques to improve efficiency or automate design and analysis methodologies\nLeverage AI tools to automate the tools and workflow\nApplying Artificial Intelligence in workflows to improve build efficiency\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "MSIP PLL Design Verification Engineer, Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-14T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719660573", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nJoin Qualcomm's design verification team in verifying the high-speed mixed-signal IP designs (PLL, DAC, ADC, Sensors, PCIe, USB, MIPI, CXL, C2C, D2D, DDR, etc.) for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle, from system-level concept to tape out and post-silicon support.\n \nResponsibilities:\nDefine pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team.\nArchitect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Functional Verification, UPF / Low power verification, Formal verification and Gate level simulation to ensure high design quality.\nAuthor assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure.\nWork with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post-silicon validation.\nMinimum Qualifications:\nMaster's/Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.\n5+ years ASIC design verification, Pre Silicon Verification or related work experience.\nKnowledge of a HVL methodology like SystemVerilog/UVM.\nExperience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others.\nPreferred Qualifications:\nExperience with Pre Silicon Verification, Low power design verification, Formal verification and Gate level simulation at IP/SS level.\nExperience in scripting languages (Python, or Perl).\nExperience with mixed-signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Convertors (DAC, ADC), or sensors will be an added advantage.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Applications Engineer", "company": "Lattice", "location": "Penang, Malaysia", "date_posted": "2026-07-14", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Penang-Malaysia/Agentic-AI-Applications-Engineer---Level-4_R-100838-1", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nJoin the winning team! Lattice is looking for a motivated and experienced factory Applications Engineer to support application designs & use cases, vendors and customers with our current and future industry-leading devices. As part of the Silicon Product Enablement team, we bridge the customer-factory relationship, clear technical hurdles and provide timely and reliable solutions. While Lattice is successful in helping our customers slash their time-to-market and bottom-line with our market-driven solutions, we want to continue to invite experts to challenge the status quo. Our Silicon Product Enablement team is seeking an outstanding team member to help design and execute \"best-in-class\" solutions for our best-in-class low power, small form factor, high reliability and performance product line. \n\nKey Responsibilities:\nDrive silicon feature enablement & improvement for a particular domain, such as IO, Memory, Serdes, etc. \n\nDevelop silicon enablement collaterals with focus on usability and performance.\n\nDevelop and conduct trainings/workshop for sales & tech support team.\n\nProvide factory support and guidance to resolve customer issues.\n\nCollaborate closely with sales team to understand customer needs & solidify requirements to R&D.\n\nSpecific job skill requirements:\nExperience in FPGA architecture & foundational blocks such as PLL, Embedded Memory blocks, DSP blocks, Input/Output blocks, etc is required.\n\nExperience in a wide variety of physical interface standards, including SSTL, HSTL, LVSTL, HSUL is highly desirable.\n\nExperience in timing closure, PLL/DLLs, physical interface strategies and signal integrity is highly desirable.\n\nHands-on FPGA development experience, including RTL development and verification is highly desirable.\n\nGeneral requirements:\nBS/MS in EE with 10+ years of experience.\n\nHands-on FPGA and/or firmware bring-up/debugging experience using oscilloscopes and signal analyzers is required.\n\nExpertise in FPGA design flows, Verilog and/or VHDL.\n\nOutstanding English communication skills, both written and verbal required.\n\nHands-on experience delivering revenue-generating hardware products is required.\n\nParticipation in all aspects of product development, from architecture and specification through documentation, market release and customer support.\n\nMust be able to work independently and also in a team environment.\n\n \nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nMalaysiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Principal Product Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-07-14", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Product-Engineer_R52811", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nThis position involves:\nInterfacing with customers regarding digital reference flow requirements, includingSynthesis\nFloorplanning\nClock tree synthesis\nPower planning\nPlace and route\nTiming closure\nSign-off\n\nCapturing reference flow requirements, scoping effort on reference flow development\nCreating baseline flows to be used by customers as starting point for digital implementation\nUsing baseline flow to implement test cases for process certification and validation\nUsing implementation testcases for Tempus and Voltus sign-off\nCreating documentation explaining the theory and use behind reference flow steps and commands\nPPA optimization\n\nPosition requires:\nBachelor’s degree with at least 12-15 years of design/EDA experience or Master’s degree with at least 10 years of experience. Master’s degree preferred.\nStrong knowledge in Digital Design Flows, Static Timing Analysis and EMIR is required\nPrior experience with ASIC digital implementation flows and EDA tools is required; Experience with advanced FinFet nodes (7nm and below) required.  Experience with GAA technologies (2nm and below) preferred.\nGood programming knowledge in Unix, Shell scripting, perl and importantly TCL\nStrong customer-facing communication and problem-solving skills\nStrong personal drive for continuous learning and expanding professional skill sets\nExcellent verbal and written communication skills\n\nFamiliar with EDA tool operation, setup and debug:\nDigital: Genus, Innovus, Tempus, Voltus, etc\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Staff Analog design Engineer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-07-14", "url": "https://careers.skyworksinc.com/job-invite/77825/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 77825\n\nDescription\n\nSeeking an experienced Analog design engineer developing complex mixed-signal ICs for EVs, Industrial Control, Industrial Power, Isolation, and other Infrastructure applications. This role will be part of the design group that is at the forefront of the EV revolution, working to develop technologies that will revolutionize vehicles and enable new levels of power efficiency.  Candidate will take a supporting or leading role depending on experience relative to other team members, but regardless of experience level, candidate will be involved in all aspects of the design process from system conceptualization to mass production. For example, candidate will participate in Analog system architecture, block- and system-level RTL design/coding, algorithm and firmware development, Analog circuit back-end (e.g. synthesis, timing closure, P&R preparation, scan insertion), Analog design verification, and full-chip mixed-signal verification.  Responsibilities will also include detailed documentation, test vector development, lab test and evaluation, customer support, and other activities as required to achieve high-volume production.\n\nResponsibilities\n\nArchitects, designs and verifies circuits, systems, algorithms, etc. to meet product requirements\n\nDevelops innovative new designs for patenting or protecting as trade secrets\n\nParticipates and contributes to product definition\n\nBalancing innovation with execution to ensure that the projects are delivered in a timely manner\n\nDemonstrates good judgment in solving a broad range of issues, based on an advanced understanding of industry practices and company policies and procedures\n\nResponsible for custom layout including overseeing the work of layout designers\n\nReports on design results through design reviews\n\nAttends design reviews to provide input and learn from other designers’ experiences\n\nSets the example for more junior members on the technical team by thoughtful use of quantitative analysis and intuition to solve mixed signal problems of advanced complexity\n\nResearch design techniques through technical publications and seminars\n\nRequired Experience and Skills\n\nBSEE + 8 years’ experience\n\nMSEE + 6 years’ experience\n\nPhD EE + 3 years’ experience\n\n \n\nMinimum Requirements\n\nAdvanced knowledge of MOS transistors and analog circuit design\n\nKnowledge of complex AC/DC analysis (poles, zeros, compensation), loop dynamics and feedback systems\n\nAdvanced knowledge of device physics and CMOS/Bi-CMOS fabrication processes\n\nPrevious design experience with complex mixed signal design problems\n\nAdvanced knowledge in signals, systems and transforms\n\nExperience with end-to-end design flow from product definition to high volume manufacturing including support of production test, applications validation and manufacturing problem solving\n\nAdvanced understanding of layout tradeoffs for performance and size\n\nExperience mentoring junior engineers\n\nStrong background in analog signal chain solutions\n\nStrong knowledge of circuit simulation tools, layout verification tools, modeling tools, and UNIX\n\n \n\n#LI-CB1\n\nDesired Experience and Skills\n\nKnowledge of high voltage processes and design in BCD and/or SOI type processes\n\nPrevious design experience with integrated power conversion circuits (Low noise Front end amplifier, SD/SAR ADCs, low noise references, DC-DC/Power converters, charge-pumps, LDO’s, rectifiers, amplifiers)\n\nAdvanced MOS Device modeling skills (noise, excess thermal noise, DIBL)\n\nExceptional laboratory measurement skills\n\nSystem knowledge (e.g., isolators) and advanced design skills in system modeling\n\nUnderstanding of mixed signal solutions including discrete time digital signal processing\n\nFamiliarity with quality systems documentation and procedures\n\nExcellent written and verbal presentation skill\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Principal Electrical Engineer (DV)", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-07-14", "url": "https://careers.skyworksinc.com/job-invite/74922/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 74922\n\nDescription\n\nIf you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high-performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking.  Our work culture values diversity, social responsibility, open communication, mutual trust and respect. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nResponsibilities\n\nWork with a dedicated team of engineers, using the latest verification practices, to verify the digital design intent of our SOC's at the block and system level. \n\nEngage early in the verification process to understand the verification requirements and participate in UVM or SystemVerilog testbench development. \n\nRequired Experience and Skills\n\n10+ years (BSEE), 6+ years (MSEE), or 3+ years (PhD) of relevant industry experience\n\nDeep expertise in Processor Subsystem, ARM cores, SoC verification, Bus Fabric.  \n\nExpertise in developing testbenches using System Verilog and UVM\n\nExperience using directed and constrained-random test methodologies, coverage closure and gate-level simulations\n\nStrong object-oriented programming knowledge using SystemVerilog\n\nStrong problem-solving and debugging skills capable of isolating problems to the block level\n\nExpertise in developing test plans, implementing coverage models, and analyzing results\n\nExperience in the use of scripts to support automation (Python, Make, Csh, Bash, Tcl, etc)\n\nFamiliarity with C-code/embedded firmware/debuggers\n\nAbility to work in a dynamic environment with changing needs and requirements\n\n#LI-CB1\n\nDesired Experience and Skills\n\n \n\nUsing Formal verification methods and tools like Jasper Gold.\n\nReal-time data processing systems\n\nAudio signal processing\n\nAudio performance concepts (SNR, THD, SINAD, DR, etc.)\n\nFamiliarity with standard interfaces (SPI, I2S, PDM, PWM, USB, etc.)\n\nFamiliarity with wireless protocols (Wi-Fi, BLE, BT, MAC/PHY)\n\nFamiliarity with wireless different processors (ARM, HiFi, RISC-V)\n\nFPGA hardware emulation\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "SoC Verification Technical Lead", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-07-14", "url": "https://careers.synopsys.com/job/bengaluru/soc-verification-technical-lead/44408/97791386448", "is_hardware": true, "platform": "talentbrew", "jd_text": "Alternate Job Title:\nSoC Verification Technical Lead\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in the trenches of SoC verification, where the difference between a chip that tapes out on schedule and one that slips six months often comes down to a verification plan you wrote in week two. You know that verification is not just about coverage numbers, it is about understanding what can actually break in silicon and making sure it does not.\nLeading a team does not mean delegating and disappearing. You are in the weaveform debugger alongside your engineers when a protocol violation shows up at 2am, and you can spot a gap in a testbench architecture during a design review without needing to see the code. You have learned to read a customer's SOC spec and immediately know where the risk lives, whether it is in the interconnect, the power domain crossings, or that custom accelerator block nobody wants to talk about yet.\nYou do not wait for perfect requirements. You ask the right questions, build a verification plan that actually maps to what can go wrong, and adjust as the design evolves. At Synopsys, you will work directly with customers building chips for AI, automotive, aerospace, and high-performance computing, and the verification strategies you build will determine whether their silicon works.\nWhat You'll Be Doing\nLead verification execution for customer SoC, subsystem, and IP projects, from verification planning through signoff, working directly with customer engineering teams to define scope and deliverables\nLead verification teams of 3-4 engineers, assigning tasks, reviewing testbenches and coverage reports, and mentoring engineers through complex debug scenarios\nDevelop verification plans that map customer requirements to testbench architecture, coverage goals, and resource allocation, then track execution and adjust as designs evolve\nIntegrate and deploy Synopsys VCS, Verdi, and third-party VIP for protocols like PCIe, Ethernet, USB, and DDR into customer verification environments\nDebug complex multi-protocol and multi-domain SoC issues using waveform analysis, coverage analysis, and cross-functional collaboration with design, architecture, and post-silicon teams\nIdentify project risks early, propose mitigation strategies, and communicate status and blockers to Synopsys management and customer stakeholders\nDrive methodology improvements across the SSG verification team, whether that is UVM reuse strategies, regression optimization, or new tool adoption\nThe Impact You Will Have\nYour verification plans and execution will directly determine whether customer chips tape out on schedule or slip quarters, affecting product launch timelines for AI accelerators, automotive SoCs, and aerospace systems\nThe engineers you mentor will grow into technical leads themselves, building verification capability across Synopsys that scales to future customer engagements\nYour early identification of design risks and verification gaps will prevent costly respins and post-silicon surprises for customers building chips in 5nm and below\nThe methodology improvements you drive will reduce verification cycle time and improve coverage quality across dozens of SSG projects annually\nYour direct customer engagement will shape how leading semiconductor companies adopt and deploy Synopsys EDA tools and IP in their verification flows\nThe testbench architectures and VIP integration strategies you build will become reusable assets for future projects, compressing ramp time for new customer engagements\nYour technical leadership will help Synopsys win and retain customer relationships in high-performance computing, automotive, and aerospace markets where verification complexity is a competitive differentiator\nWhat You'll Need\nBachelor's or Master's in Electronics Engineering, Computer Engineering, or related field with 5+ years of hands-on SoC, subsystem, or IP verification experience\nDeep technical expertise in UVM testbench development, coverage analysis, verification planning, and complex multi-domain debug\nProven experience leading verification teams through full project cycles, including resource planning, task assignment, and delivery against customer schedules\nStrong working knowledge of industry-standard protocols such as PCIe, Ethernet, USB, or DDR, and how they interact in real SoC architectures\nHands-on proficiency with Synopsys VCS, Verdi or equivalent waveform analysis tools, and integration of third-party VIP into verification environments\nExperience with ARM-based technologies including Coresight debug infrastructure, processor architecture, or AMBA protocols is a strong plus\nSolid understanding of ASIC design flows, RTL design concepts, and how verification fits into the broader chip development process\nWho You Are\nYou can walk into a customer meeting, hear a high-level SoC architecture description, and walk out with a verification plan that identifies the three highest-risk areas before anyone else in the room sees them\nWhen a regression fails at 3am and your team is stuck, you can look at the waveform, the coverage report, and the testbench code and know within 15 minutes whether it is a real bug or a testbench issue\nYou give feedback that makes engineers better, not just feedback that makes you feel heard, and your team knows the difference\nYou do not let a project drift. If a customer requirement is vague or a timeline is unrealistic, you say so early and propose a path forward that actually works\nYou can explain a complex protocol violation to a customer architect, a verification coverage gap to your manager, and a UVM sequence bug to a junior engineer, and all three conversations will be clear and useful\nYou stay current on verification methodology and tooling not because it is required but because you care about doing this work well, and you bring that knowledge back to your team\nThe Team You'll Be Part Of\nYou will join the System Solutions Group (SSG), a team that delivers end-to-end SoC design and verification services to Synopsys customers across automotive, high-performance computing, aerospace, and defense. SSG works on everything from individual IP blocks to full turnkey SoCs, partnering with customers ranging from startups to industry leaders and government agencies. Your verification work will span subsystems and full chips, and you will collaborate closely with Synopsys architecture, design, EDA application engineering, and sales teams to deploy tool and IP solutions that solve real customer problems.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Staff Electrical Engineer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-07-14", "url": "https://careers.skyworksinc.com/job-invite/76531/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 76531\n\nDescription\n\nSeeking an experienced analog/mixed-signal design engineer for developing complex mixed-signal ICs for Timing and Infrastructure applications. The position requires a strong analog mixed-signal design background including a strong history of innovative product and IP definition and design.  Depending on experience level, the individual will participate in product roadmaps, definition, technology selection, design, and verification. The individual will have a role in defining and implementing the overall system architecture, designing transistor-level analog circuit blocks, simulating sub-system performance, creating and using behavioral models of blocks and the entire IC, doing and/or supervising physical layout, verifying circuit and chip-level operation and performance, and assisting with tape-out related activities. Responsibilities will also include detailed documentation, silicon evaluation and debugging, production test development support, customer support, and other activities as required for the achievement of high volume production.\n\n \n\n#LI-CB1\n\nResponsibilities\n\nArchitects, designs and verifies circuits, logic, systems, algorithms, etc. to meet product requirements\n\nDetermine design approaches and parameters\n\nDevelops innovative new designs for patenting or protecting as trade secret\n\nDemonstrates good judgment in solving a broad range of issues, based on an advanced understanding of industry practices and company policies and procedures\n\nResponsible for custom layout, including overseeing the work of layout designers\n\nReports on design results through design reviews, in accordance with company quality requirements and resolves action items generated as a result of these reviews\n\nAttends design reviews to provide input and learn from other designers’ experiences\n\nResearch design techniques through technical publications and seminars\n\nSupports marketing in product definition\n\nHaving a wide-ranging experience uses professional concepts and company objectives to resolve complex issues in creative and effective way\n\nDetermines methods and procedures on new assignments and may coordinate the activities of other personnel\n\nRequired Experience and Skills\n\nMS + 8-12  years of Analog Mixed Signal IC design experience / PhD + 6-9  years of Analog Mixed Signal IC design experience\n\nStrong knowledge of engineering fundamentals\n\nAdvanced knowledge of CMOS fabrication processes\n\nAdvanced knowledge of MOS transistors and analog/digital circuit design\n\nKnowledge of complex AD/DC analysis (poles, zeros, compensation)\n\nAdvanced signal analysis knowledge\n\nBasic understanding of CMOS and BCD parasitic junctions and the risks associated with them\n\nStrong parasitic analysis knowledge (capacitance, resistance, power grid)\n\nAdvanced knowledge of circuit building blocks (e.g., OPAMP, gm-C filters, switch capacitors, ADC, DAC, state-machines, and bus interfaces)\n\nAdvanced understanding of layout tradeoffs for performance and size\n\nAdvanced design skills in system modeling\n\nStrong knowledge of UNIX, Matlab, and circuit simulation tools\n\nProficiency in layout verification, DRC, LVS\n\nDesired Experience and Skills\n\nWorking knowledge of device physics\n\nWorking knowledge of digital design and design flows\n\nSystem knowledge (e.g., High Performance PLLs)\n\nKnowledge of scripting language (python, shell, skill)\n\nAdvanced laboratory measurement skills (analog, digital)\n\nKnowledge of MS Office documentation, spreadsheet, presentation tools or equivalent tools\n\nFamiliarity with quality systems documentation and procedures\n\nCompetency with design tools\n\nExcellent written and verbal presentation skills\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Lead Automative Use Cases Validation Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-07-13T06:45:00+00:00", "url": "https://global-external-amd.icims.com/jobs/86032/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. MTS SOFTWARE SYSTEM DESIGN ENGINEER Lead Automative Use Cases Validation Engineer THE ROLE: Join AMD’s PAVS team as an Automotive Infotainment Stack Validation Engineer, leading validation strategies and end to end use case validation for AMD’s Automotive Virtualization on AMD platforms. The role focuses on validating Xen based virtualization, multi OS domains (Android, Yocto, FreeRTOS/SafeRTOS), IVI features, graphics, and Ryzen AI workloads. You will work across the hypervisor, OS domains, drivers, and system level performance to enable next generation automotive compute platforms. THE PERSON: Your curiosity will drive your learning and innovation to improve how we as a group, and an organization, can get better every day. Your peers will provide you a results-oriented and encouraging environment for your career growth, fueling your opportunity to be a part of Delighting Our Customers.   KEY SKILLS: Virtualization (Xen): Multi VM Validation (Android/Yocto/FreeRTOS), virtio (camera/audio/media/GPU/NPU), passthrough (UART/I2C/SPI), AVIC, QoS. Boot Optimization testing with core boot for S3 & S5 OS Domains: Validation of Safe Linux, SDV AAOS, Yocto, and FreeRTOS/SafeRTOS including graphics workflows, automotive use cases, and IVI related feature validation. FreeRTOS/SafeRTOS: Control-domain validation, CRC, safe rendering, crash fallback, mixed criticality flows. Graphics/Display: AMD compositor (superframes, gestures, clone, virtual outputs), projection (Android Auto, CarPlay). Debug/Recovery: Full stack debug using Unified Debugger, system recovery validation. Cloud & AI: VAS on AWS/Google Cloud, V710; Ryzen AI workloads Audio: HiFi5 pipelines, ACP validation Security: Secure Boot to DomU, validation KEY RESPONSIBILITIES: Validate Xen based virtualized platforms across Android, Yocto, FreeRTOS. Optimize and validate boot flows across firmware → hypervisor → OS. Validate virtio pipelines and device passthrough. Validate compositor, display, GPU, and projection workflows. Lead system-level debug, performance tuning, mixed criticality validation. Support Secure Boot, safety flows, and cybersecurity validation. Collaborate with firmware, kernel, virtualization, graphics, and AI teams. Drive automating features PREFERRED EXPERIENCE: Strong in C/C++, Python, Shell automation. Deep experience with Linux kernel, hypervisors, drivers, bootloaders, SoC power states. Hands-on with Xen, multi VM orchestration, and automotive compute platforms. Test Automation: Development and automate test suites for virtualization, boot flows, OS domains, and IVI features. Frameworks & Tools: PyTest, Framework, custom Python/Shell-based automation, Jenkins/GitLab CI pipelines.  ACADEMIC CREDENTIALS: Bachelor’s or Master's degree in Computer or Electrical Engineering or equivalent #LI-NR1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Electrical Engineer", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2026-07-13", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/Electrical-Engineer_R2620090", "is_hardware": true, "platform": "workday", "jd_text": "Who We Are\n\nApplied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips – the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world – like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world. \n\nWhat We Offer\n\nLocation:\nBangalore,IND\nYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. \n\nAt Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. \n \n \nAs an Electrical Engineer, you are responsible for designing, modifying, and troubleshooting electrical or electronic engineering assemblies, layouts, schematics, and drawings to advance the equipment that supports our technology. Using your technical experience and critical thinking skills, you will perform engineering analysis, generate test reports, develop innovative solutions, and create documentation for product releases. You will also coordinate the procurement and assembly of components, identify sources of critical parts, and resolve technical issues to ensure peak performance. \n \nRole Responsibilities: \nDesign or modify electrical or electronic engineering assemblies, layouts, schematics, drawings or specifications of moderate scope under general supervision \n\nPerform basic engineering analysis under general supervision \n\nCarry out Virtual Analysis for Electrical schematics Designs and 3D Electrical Modelings\n\nPerform and generate basic engineering test reports; generate related alpha/gamma documentation for product releases \n\nCoordinate the procurement and assembly of electrical or electronic components and equipment, and identify sources of critical parts and subsystems to resolve technical issues \n\nKnowledge on E3s, Nx, PCad PCBA Design Tools\n\nTroubleshoot a variety of moderately complex electrical problems \n\nImplement concepts for product issues and electrical solutions of moderate difficulty \n\nAssist in the development of electrical product specifications \n\nClearly communicate complex information in straightforward situations\n\nElectrical Standards Knowledge like CE, UL, SEMI & IPC\n\nMinimum Qualifications:\nBachelor’s degree\n\n2-4 years of related experience\n\nPreferred Qualifications:\nA solid understanding of the industry’s key business drivers  \n\nGood communication/interpersonal skills to explain complex information to others   \n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nAssignee / Regular\nTravel:\nYes, 10% of the Time\nRelocation Eligible:\nYes\n\nApplied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "Staff Application Engineer - Physical Implementation", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-07-13", "url": "https://careers.synopsys.com/job/bengaluru/staff-application-engineer-physical-implementation/44408/97730002480", "is_hardware": true, "platform": "talentbrew", "jd_text": "Alternate Job Titles:\nStaff Application Engineer – Physical Implementation\nSenior Implementation Solutions Engineer\nStaff Engineer – RTL-GDS Flow\nCustomer Success Engineer – EDA Tools\nTechnical Application Engineer – AI/ML Implementation\nWe Are:\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are:\nYou are driven by the kind of challenges that don’t have a single right answer—only sharper questions, better tradeoffs, and a team that’s willing to iterate until the outcome is undeniable. You thrive in environments where the bar keeps moving, where priorities shift with new data, and where you’re expected to stay calm, curious, and decisive at the same time. You don’t wait to be told what to do; you look for the friction points, the recurring pain, and the moments where a small change in approach can unlock a big jump in results.\nYou bring a customer-first mindset that shows up in how you work every day. You listen carefully, clarify goals, and make sure everyone is solving the same problem before anyone starts optimizing. You communicate with precision and empathy—direct enough to prevent surprises, thoughtful enough to keep relationships strong. When something goes wrong, you treat it as a shared puzzle, not a personal failure, and you keep the focus on progress: isolate the issue, align on next steps, and close the loop with clear outcomes.\nYou’re a natural bridge-builder. You enjoy connecting dots across teams, translating needs into action, and keeping feedback grounded in real-world impact. You balance attention to detail with an instinct for the bigger picture, and you measure success by the momentum you create—helping others move faster, make better decisions, and deliver results they can stand behind.\nWhat You’ll Be Doing:\nSolving complex PPA (Performance, Power, Area) challenges using Synopsys’ latest implementation technologies, including AI/ML Implementation, Physical Synthesis RTL-GDS.\nSolving complex Formal verification challenges, early power estimation using latest technologies\nBenchmarking Synopsys solutions against competitors to displace alternative implementation flows anddemonstratesuperior results.\nDeveloping, debugging, andoptimizingSynthesisimplementation methodologies and flows for emerging semiconductor technologies.\nProviding technical solutions byidentifyingdesign and EDA tool issues and delivering actionable resolutions for customers.\nTranslating technical findings into requirements for R&D, driving tool enhancements and adaptive long-term solutions.\nDeployingnew technologyfeatures in the latest EDA tool versions and enabling customer migration for best-in-class PPA.\nProactivelyidentifyingcustomer pain points and proposing innovative solutions to address them.\nCollaborating closely with Synopsys R&D and product development teams to shape future technology directions.\n\nActing as a customer advocate during internal discussions and as a brand ambassador when engaging externally.\nThe Impact You Will Have:\nElevating customer success by delivering robust technical solutions and enablingoptimaltoolutilization.\nDriving Synopsys’ competitive advantage by displacing rival implementation flows andshowcasingsuperior PPA outcomes.\nContributing to the enhancement of Synopsys products by providing critical feedback and requirements to R&D.\nAccelerating customer adoption ofnew technologynodes and EDA tool versions to achieve best-in-class results.\nStrengthening Synopsys’ reputation as the industry leader in physical implementation and innovation.\nFostering long-term customer relationships through proactive engagement and continuous support.\nWhat You’ll Need:\nAt least 5+ years of experience inSynthesis, with proven ability to debug and resolve synthesis challenges, including low power understanding.\nStrong exposure tomethodologychanges aimed at achieving targeted PPA metrics for complex designs.\nProficiencyinsynthesis and formal verificationtools and flows is highlyadvantageous.\nAdvanced scripting skills (TCL, Unix, Perl) for automation and debugging.\nExcellent communication skills, including the ability tointerface effectively withcustomers and internal teams.\nWho You Are:\nSelf-motivated and dedicated, with a passion for continuous learning and improvement.\nStrong analytical thinker with outstanding debug skills and attention to detail.\nCollaborative team player who thrives in dynamic, fast-paced environments.\nCustomer-centric, always advocating for the best outcomes and solutions.\nResilient and adaptable, able to manage multiple priorities and deliver results.\n\nThe Team You’ll Be A Part Of:\nJoin our Application Engineering team in Bangalore, where you’ll work directly with industry pioneers and innovators. The team’s mission is to solve critical design challenges, enhance quality-of-results metrics, and empower customers to achieve best-in-class performance. Collaboration with R&D and product development is central, ensuring that customer needs drive future technology advancements. Together, we set the standards for excellence in semiconductor design and implementation.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Principal DFT Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-07-13", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-DFT-Engineer_R55135", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nPrior 7-12 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)\nShould possess intimate knowledge of DFT insertion flows\nBasic scan chain insertion using synthesis or other software tools\nExperience in compression scan insertion, LBIST and other scan technologies\nIntimate knowledge of memory build-in self-test (MBIST)\nExpertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals\nDebug and Analysis of failures to improve fault coverage\nVerification of ATPG testbenches and debugging root cause of simulation mis-compares\nWorking knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687\nKnowledge of timing analysis and equivalency checks would be added bonus\nAbility to work in collaborative team environment\nPrior experience with Cadence tools and flows is highly desirable\nShould be able to finish DFT tasks independently\nStrong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems\nAbility to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers\nSelf-driven and committed individual who can work in a fast-paced project environment\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Senior Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-07-12", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Senior-Engineer_R026379-4", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nCandidate would be required to work on various phases of SOC physical design activities. The job will include but not limited to  block level – floor-planning, partitioning, placement, clock tree synthesis, route, physical verification (LVS/DRC/ERC/Antenna etc).\nShould be able to meet congestion, timing and area metrics.  Candidate would be required to do equivalence checks, STA, Crosstalk delay analysis ,noise analysis, power optimization. Should be able to implement timing and functional ECOs.\n \nShould have excellent problem solving skill to help through congestion resolution and timing closure. Should have experience formal verification and timing analysis and ECO implementation.\nExperience with tools such as Innovus/Encounter, ICC, Caliber, LEC, Primetime etc is highly desirable.\n \nCandidate should be able to work independently and guide other team members. Should be experienced in working in a global team and dynamic environment.\nShould possess ability to learn and adapt to new tools and methodologies.\nExcellent communication skill is a must. \n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Staff Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-07-12", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Staff-Engineer_R026385-6", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nCandidate would be required to work on various phases of SOC physical design activities. The job will include but not limited to  block level – floor-planning, partitioning, placement, clock tree synthesis, route, physical verification (LVS/DRC/ERC/Antenna etc).\nShould be able to meet congestion, timing and area metrics.  Candidate would be required to do equivalence checks, STA, Crosstalk delay analysis ,noise analysis, power optimization. Should be able to implement timing and functional ECOs.\n \nShould have excellent problem solving skill to help through congestion resolution and timing closure. Should have experience formal verification and timing analysis and ECO implementation.\nExperience with tools such as Innovus/Encounter, ICC, Caliber, LEC, Primetime etc is highly desirable.\n \nCandidate should be able to work independently and guide other team members. Should be experienced in working in a global team and dynamic environment.\nShould possess ability to learn and adapt to new tools and methodologies.\nExcellent communication skill is a must. \n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "R&D Engineer IC Design", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-07-12", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/R-D-Engineer-IC-Design_R026394-6", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nDesigns and develops integrated circuits.  Oversees definition, design, verification, and documentation for ASIC development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. May also review vendor capability to support development.  - Knowledge: Having wide-ranging experience, uses professional concepts and company objectives to resolve complex issues in creative and effective ways. \n• Strong project management skills\n• Leads design and delivery of new\nproducts/process\n• Functional breadth and depth, plus expert in complementary fields\n• Applies broad concepts and theories to achieve innovative and effective solutions to complex problems - Job Complexity / Contribution : Works on complex issues where analysis of situations or data requires an in-depth evaluation of variable factors. Exercises judgment in selecting methods, techniques and evaluation criteria for obtaining results. Networks with key contacts outside own area of expertise.  \n• Will champion significant projects, programs and business initiatives using demonstrated creativity and ingenuity\n• Team leader\n• Leads major projects\n• Influences or impacts others'\npriorities, decisions or activities\n• Escalation point for complex issues\n• Coaches and mentors other junior team members - Supervision : Incumbents provide a leadership role for the work group through knowledge in his/her area of specialization. Generally free to determine work priorities based on general direction from managers.     \n• Determines methods and procedures on new assignments\n• Consults with management on long-range goals\n• Determines own priorities, both tactical and strategic - Experience : Bachelors and 8+ years of related experience; at this level post-graduate coursework may be desirable or\nMasters degree and 6+ years of related experience or PhD and 3+ years of related experience\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "R&D Engineer IC Design", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-07-12", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/R-D-Engineer-IC-Design_R026396-4", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nDesigns and develops integrated circuits.  Oversees definition, design, verification, and documentation for ASIC development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. May also review vendor capability to support development.  - Knowledge: Having wide-ranging experience, uses professional concepts and company objectives to resolve complex issues in creative and effective ways. \n• Strong project management skills\n• Leads design and delivery of new\nproducts/process\n• Functional breadth and depth, plus expert in complementary fields\n• Applies broad concepts and theories to achieve innovative and effective solutions to complex problems - Job Complexity / Contribution : Works on complex issues where analysis of situations or data requires an in-depth evaluation of variable factors. Exercises judgment in selecting methods, techniques and evaluation criteria for obtaining results. Networks with key contacts outside own area of expertise.  \n• Will champion significant projects, programs and business initiatives using demonstrated creativity and ingenuity\n• Team leader\n• Leads major projects\n• Influences or impacts others'\npriorities, decisions or activities\n• Escalation point for complex issues\n• Coaches and mentors other junior team members - Supervision : Incumbents provide a leadership role for the work group through knowledge in his/her area of specialization. Generally free to determine work priorities based on general direction from managers.     \n• Determines methods and procedures on new assignments\n• Consults with management on long-range goals\n• Determines own priorities, both tactical and strategic - Experience : Bachelors and 8+ years of related experience; at this level post-graduate coursework may be desirable or\nMasters degree and 6+ years of related experience or PhD and 3+ years of related experience\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Staff Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-07-12", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Staff-Design-Engineer_R026393", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nCandidate would be required to work on various phases of SOC physical design activities. The job will include but not limited to  block level – floor-planning, partitioning, placement, clock tree synthesis, route, physical verification (LVS/DRC/ERC/Antenna etc).\nShould be able to meet congestion, timing and area metrics.  Candidate would be required to do equivalence checks, STA, Crosstalk delay analysis ,noise analysis, power optimization. Should be able to implement timing and functional ECOs.\n\nShould have excellent problem solving skill to help through congestion resolution and timing closure. Should have experience formal verification and timing analysis and ECO implementation.\nExperience with tools such as Innovus/Encounter, ICC, Caliber, LEC, Primetime etc is highly desirable.\n\nCandidate should be able to work independently and guide other team members. Should be experienced in working in a global team and dynamic environment.\nShould possess ability to learn and adapt to new tools and methodologies.\nExcellent communication skill is a must. \n\n \n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "IC Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-07-12", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/IC-Design-Engineer_R026407", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nIn this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria\nfor achieving Right-first time silicon.\nCandidate should have very good experience in layout activities of block and level. Should be well experienced in floor-planning,\npartitioning, placement, clock tree synthesis, route and physical verification.\nResponsibilities include, but not limited to:\n• Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies\n• Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt.\n• Implement timing and functional ECO\n• P&R, Extraction, Physical verification, work towards STA closure\n• Build automation flows wherever needed/adapt to existing flows for re-use\n• Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&R, PV, STA, ECO\n• Needs to be automation savvy with high expertise in one of the programming languages used in the industry\n• Clearly know requisites for executing his/her job and lead by example\n• Bring tangible improvement in TAT with better quality\nMinimum Qualifications:\n• MSEE/MSCS 3+ years (BSEE/BSCS 5+ years)\n• A deep understanding of backend digital design flow\n• Proficient in timing constraints, physical constraints\n• Proficient in handling EDA tools across floorplan/partition/placement/cts/route stages for SoC TOP.\n• Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk\n• Proficiency in Tcl and Perl\n• Excellent analytical skills\n• Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "IC Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-07-12", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/IC-Design-Engineer_R026408", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nIn this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria\nfor achieving Right-first time silicon.\nCandidate should have very good experience in layout activities of block and level. Should be well experienced in floor-planning,\npartitioning, placement, clock tree synthesis, route and physical verification.\nResponsibilities include, but not limited to:\n• Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies\n• Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt.\n• Implement timing and functional ECO\n• P&R, Extraction, Physical verification, work towards STA closure\n• Build automation flows wherever needed/adapt to existing flows for re-use\n• Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&R, PV, STA, ECO\n• Needs to be automation savvy with high expertise in one of the programming languages used in the industry\n• Clearly know requisites for executing his/her job and lead by example\n• Bring tangible improvement in TAT with better quality\nMinimum Qualifications:\n• MSEE/MSCS 3+ years (BSEE/BSCS 5+ years)\n• A deep understanding of backend digital design flow\n• Proficient in timing constraints, physical constraints\n• Proficient in handling EDA tools across floorplan/partition/placement/cts/route stages for SoC TOP.\n• Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk\n• Proficiency in Tcl and Perl\n• Excellent analytical skills\n• Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "IC Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-07-12", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/IC-Design-Engineer_R026409", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nIn this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria\nfor achieving Right-first time silicon.\nCandidate should have very good experience in layout activities of block and level. Should be well experienced in floor-planning,\npartitioning, placement, clock tree synthesis, route and physical verification.\nResponsibilities include, but not limited to:\n• Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies\n• Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt.\n• Implement timing and functional ECO\n• P&R, Extraction, Physical verification, work towards STA closure\n• Build automation flows wherever needed/adapt to existing flows for re-use\n• Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&R, PV, STA, ECO\n• Needs to be automation savvy with high expertise in one of the programming languages used in the industry\n• Clearly know requisites for executing his/her job and lead by example\n• Bring tangible improvement in TAT with better quality\nMinimum Qualifications:\n• MSEE/MSCS 6+ years (BSEE/BSCS 8+ years)\n• A deep understanding of backend digital design flow\n• Proficient in timing constraints, physical constraints\n• Proficient in handling EDA tools across floorplan/partition/placement/cts/route stages for SoC TOP.\n• Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk\n• Proficiency in Tcl and Perl\n• Excellent analytical skills\n• Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "IC Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-07-12", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/IC-Design-Engineer_R026410", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nIn this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria\nfor achieving Right-first time silicon.\nCandidate should have very good experience in layout activities of block and level. Should be well experienced in floor-planning,\npartitioning, placement, clock tree synthesis, route and physical verification.\nResponsibilities include, but not limited to:\n• Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies\n• Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt.\n• Implement timing and functional ECO\n• P&R, Extraction, Physical verification, work towards STA closure\n• Build automation flows wherever needed/adapt to existing flows for re-use\n• Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&R, PV, STA, ECO\n• Needs to be automation savvy with high expertise in one of the programming languages used in the industry\n• Clearly know requisites for executing his/her job and lead by example\n• Bring tangible improvement in TAT with better quality\nMinimum Qualifications:\n• MSEE/MSCS 6+ years (BSEE/BSCS 8+ years)\n• A deep understanding of backend digital design flow\n• Proficient in timing constraints, physical constraints\n• Proficient in handling EDA tools across floorplan/partition/placement/cts/route stages for SoC TOP.\n• Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk\n• Proficiency in Tcl and Perl\n• Excellent analytical skills\n• Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "IC Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-07-12", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/IC-Design-Engineer_R026411", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nIn this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria\nfor achieving Right-first time silicon.\nCandidate should have very good experience in layout activities of block and level. Should be well experienced in floor-planning,\npartitioning, placement, clock tree synthesis, route and physical verification.\nResponsibilities include, but not limited to:\n• Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies\n• Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt.\n• Implement timing and functional ECO\n• P&R, Extraction, Physical verification, work towards STA closure\n• Build automation flows wherever needed/adapt to existing flows for re-use\n• Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&R, PV, STA, ECO\n• Needs to be automation savvy with high expertise in one of the programming languages used in the industry\n• Clearly know requisites for executing his/her job and lead by example\n• Bring tangible improvement in TAT with better quality\nMinimum Qualifications:\n• MSEE/MSCS 6+ years (BSEE/BSCS 8+ years)\n• A deep understanding of backend digital design flow\n• Proficient in timing constraints, physical constraints\n• Proficient in handling EDA tools across floorplan/partition/placement/cts/route stages for SoC TOP.\n• Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk\n• Proficiency in Tcl and Perl\n• Excellent analytical skills\n• Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "R&D Engineer IC Design", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-07-12", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/R-D-Engineer-IC-Design_R026397-6", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nDesigns and develops integrated circuits.  Oversees definition, design, verification, and documentation for ASIC development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. May also review vendor capability to support development.  - Knowledge: Having wide-ranging experience, uses professional concepts and company objectives to resolve complex issues in creative and effective ways. \n• Strong project management skills\n• Leads design and delivery of new\nproducts/process\n• Functional breadth and depth, plus expert in complementary fields\n• Applies broad concepts and theories to achieve innovative and effective solutions to complex problems - Job Complexity / Contribution : Works on complex issues where analysis of situations or data requires an in-depth evaluation of variable factors. Exercises judgment in selecting methods, techniques and evaluation criteria for obtaining results. Networks with key contacts outside own area of expertise.  \n• Will champion significant projects, programs and business initiatives using demonstrated creativity and ingenuity\n• Team leader\n• Leads major projects\n• Influences or impacts others'\npriorities, decisions or activities\n• Escalation point for complex issues\n• Coaches and mentors other junior team members - Supervision : Incumbents provide a leadership role for the work group through knowledge in his/her area of specialization. Generally free to determine work priorities based on general direction from managers.     \n• Determines methods and procedures on new assignments\n• Consults with management on long-range goals\n• Determines own priorities, both tactical and strategic - Experience : Bachelors and 8+ years of related experience; at this level post-graduate coursework may be desirable or\nMasters degree and 6+ years of related experience or PhD and 3+ years of related experience\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "IC Design Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-07-12", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/IC-Design-Engineer_R026412", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nIn this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria\nfor achieving Right-first time silicon.\nCandidate should have very good experience in layout activities of block and level. Should be well experienced in floor-planning,\npartitioning, placement, clock tree synthesis, route and physical verification.\nResponsibilities include, but not limited to:\n• Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies\n• Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt.\n• Implement timing and functional ECO\n• P&R, Extraction, Physical verification, work towards STA closure\n• Build automation flows wherever needed/adapt to existing flows for re-use\n• Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&R, PV, STA, ECO\n• Needs to be automation savvy with high expertise in one of the programming languages used in the industry\n• Clearly know requisites for executing his/her job and lead by example\n• Bring tangible improvement in TAT with better quality\nMinimum Qualifications:\n• MSEE/MSCS 6+ years (BSEE/BSCS 8+ years)\n• A deep understanding of backend digital design flow\n• Proficient in timing constraints, physical constraints\n• Proficient in handling EDA tools across floorplan/partition/placement/cts/route stages for SoC TOP.\n• Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk\n• Proficiency in Tcl and Perl\n• Excellent analytical skills\n• Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Staff Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-07-12", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/Staff-Engineer_R026383", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nCandidate would be required to work on various phases of SOC physical design activities. The job will include but not limited to  block level – floor-planning, partitioning, placement, clock tree synthesis, route, physical verification (LVS/DRC/ERC/Antenna etc).\nShould be able to meet congestion, timing and area metrics.  Candidate would be required to do equivalence checks, STA, Crosstalk delay analysis ,noise analysis, power optimization. Should be able to implement timing and functional ECOs.\n \nShould have excellent problem solving skill to help through congestion resolution and timing closure. Should have experience formal verification and timing analysis and ECO implementation.\nExperience with tools such as Innovus/Encounter, ICC, Caliber, LEC, Primetime etc is highly desirable.\n \nCandidate should be able to work independently and guide other team members. Should be experienced in working in a global team and dynamic environment.\nShould possess ability to learn and adapt to new tools and methodologies.\nExcellent communication skill is a must. \n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "R&D Engineer IC Design", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-07-12", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/R-D-Engineer-IC-Design_R026398-6", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nDesigns and develops integrated circuits.  Oversees definition, design, verification, and documentation for ASIC development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. May also review vendor capability to support development.  - Knowledge: Having wide-ranging experience, uses professional concepts and company objectives to resolve complex issues in creative and effective ways. \n• Strong project management skills\n• Leads design and delivery of new\nproducts/process\n• Functional breadth and depth, plus expert in complementary fields\n• Applies broad concepts and theories to achieve innovative and effective solutions to complex problems - Job Complexity / Contribution : Works on complex issues where analysis of situations or data requires an in-depth evaluation of variable factors. Exercises judgment in selecting methods, techniques and evaluation criteria for obtaining results. Networks with key contacts outside own area of expertise.  \n• Will champion significant projects, programs and business initiatives using demonstrated creativity and ingenuity\n• Team leader\n• Leads major projects\n• Influences or impacts others'\npriorities, decisions or activities\n• Escalation point for complex issues\n• Coaches and mentors other junior team members - Supervision : Incumbents provide a leadership role for the work group through knowledge in his/her area of specialization. Generally free to determine work priorities based on general direction from managers.     \n• Determines methods and procedures on new assignments\n• Consults with management on long-range goals\n• Determines own priorities, both tactical and strategic - Experience : Bachelors and 8+ years of related experience; at this level post-graduate coursework may be desirable or\nMasters degree and 6+ years of related experience or PhD and 3+ years of related experience\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "Formal Verification Lead", "company": "Tesla", "location": "Bengaluru, India ; India", "date_posted": "2026-07-10T02:30:00", "url": "https://hire-r1.mokahr.com/social-recruitment/tesla/100004142?#/job/587d6023-0915-4395-9694-282e546d223b", "is_hardware": true, "platform": "mokahr", "jd_text": "What to Expect\nTesla’s AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge custom silicon. The team designs and develops advanced AI inference chips that accelerate Tesla’s machine learning workloads. A cornerstone of this effort is Dojo, Tesla’s custom supercomputer built to train massive neural networks on fleet video data. The hardware powers the neural networks behind Full Self-Driving (FSD) and the Tesla Optimus humanoid robot.\nTesla is rapidly expanding its AI Hardware engineering presence in Bengaluru to design and verify next-generation custom silicon. We are seeking a Lead Formal Verification Engineer to build and lead the formal verification function from India. You will work closely with global architects, RTL designers, and both formal and simulation verification teams (primarily in the US) to deliver high-quality tape-outs while establishing world-class formal verification practices, tools, and talent in Bengaluru.\nThis is a high-impact leadership role where you will shape the formal verification strategy for complex AI accelerator designs and help scale the India site’s verification capabilities. If you thrive on solving challenging problems, mentoring engineers, and driving technical excellence in a fast-paced environment, this role is for you.\n\nWhat You’ll Do\nLead and mentor a team of formal verification engineers in Bengaluru, providing technical direction, coaching, and career development while building the function from the ground up.\nDefine comprehensive formal verification plans, strategies, and sign-off criteria for critical AI Hardware IP blocks and subsystems in alignment with global architecture and design teams.\nReview and influence RTL design architecture and specifications to improve verifiability and reduce verification complexity.\nProve functional correctness of design features using advanced formal methods (model checking, logical equivalence checking, theorem proving) and drive formal sign-off in conjunction with simulation-based verification.\nDevelop, maintain, and scale regressions, custom tools, infrastructure, and integrated formal + functional verification methodologies optimized for high-complexity AI/ML accelerator designs.\nEstablish best practices, training programs, and process improvements for formal verification across the India team and in close collaboration with US-based counterparts.\nDrive cross-functional technical alignment on verification closure, tape-out readiness, and risk mitigation with global stakeholders.\nSupport hiring and help grow a high-caliber formal verification team in Bengaluru.\nRepresent the India verification team in design reviews, methodology discussions, and executive-level technical updates.\n\nWhat You’ll Bring\nBachelor’s, Master’s, or PhD in Electrical Engineering, Computer Science, Computer Engineering, or equivalent practical experience.\n8+ years of experience verifying complex hardware systems, with significant hands-on work in formal verification (model checking or logical equivalence checking). Prior experience leading verification efforts, small teams, or acting as a technical lead/staff engineer is strongly preferred.\nSolid programming skills in SystemVerilog, SVA (or PSL), and scripting languages.\nProven expertise in debugging complex ASIC/SoC designs — CPU, GPU, fabric/NoC, memory subsystems, high-speed protocols (PCIe, Ethernet, etc.), or AI/ML accelerators.\nStrong knowledge of advanced computer architecture and micro-architecture concepts.\nExperience with formal verification tools and flows (e.g., JasperGold, VC Formal, or equivalent) is highly desirable.\nExcellent communication and collaboration skills to work effectively with distributed global teams across time zones.\nPassion for Tesla’s mission and a track record of delivering results in high-stakes, fast-moving environments.\nExperience with AI hardware accelerators or high-performance computing chips is a strong plus.", "jd_status": "stored"}, {"title": "Staff Engineer, Design Verification", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-07-10T02:14:21.415000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000136965722-staff-engineer-design-verification", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.\nWe are seeking a highly experienced IP Design Verification Engineer to join the Verification R&D team at Renesas. In this role, you will be a part of team responsible for SOC verification, ensuring first‑pass silicon success through building verification environment from scratch using best in class methodologies, metric‑driven verification, and intelligent coverage convergence using AI tools.\nYou will play a key technical role in defining verification strategies, architecting testbenches, defining Test Plans tracing Requirements, driving coverage closure using advanced automation and AI‑assisted techniques, and collaborating closely with Architecture, RTL, chip top, and Validation teams to deliver high‑quality, reusable IPs for next‑generation microcontrollers and microprocessors.\nResponsibilities:\nBe a part of end‑to‑end verification execution for SOC owning complex digital IP’s and subsystems from specification to sign‑off\nDefine and drive IP‑level verification strategies, including test plans, coverage models, and closure criteria\nDevelop scalable, reusable UVM‑based verification environments for IP and subsystem verification\nLead functional, code, assertion, and cross‑coverage closure, ensuring high‑quality sign‑off with clear metrics\nApply AI/ML‑assisted verification techniques to accelerate coverage convergence, identify stimulus gaps, and optimize regression efficiency\nDrive constraint random and directed test methodologies for thorough protocol, corner‑case, and stress verification\nCollaborate with RTL, Architecture, Emulation, and SoC Verification teams to ensure seamless IP integration\nReview IP specifications and work with architects to translate requirements into robust verification plans and checkers\nDevelop and deploy advanced checkers, scoreboards, assertions (SVA), and protocol monitors\nWork with EDA vendors to evaluate and adopt next‑generation verification, coverage, and analytics tools\nMentor junior engineers and promote best‑in‑class verification practices and continuous improvement\nSupport Gate‑Level Simulation (GLS), low‑power verification, and post‑silicon debug when required.\n\nBachelor’s or Master’s degree in electronics Engineering\n5-12 years of experience in SoC Verification domains and have working knowledge of industry standard EDA toolkits.  \nStrong expertise in UVM‑based testbench architecture and development\nProven experience in metric‑driven verification, including functional and code coverage closure\nDeep understanding of SystemVerilog, UVM, assertions (SVA), and verification best practices\nExperience with directed and constrained‑random verification methodologies\nExperience debugging complex design issues in simulation, emulation, and post‑silicon environments\nProficiency in Verilog/SystemVerilog, with working knowledge of C/C++, Shell scripting\nStrong analytical, problem‑solving, and communication skills\nPreferred/Plus Qualifications\nHands‑on experience using AI/ML‑based verification tools for:Coverage gap analysis\nTest stimulus optimization\nRegression triage and coverage acceleration\n\nScripting expertise in Python, Perl, or TCL for automation and analytics\nExposure to formal verification and hybrid formal‑simulation flows\nFamiliarity with high‑speed or complex IPs, such as:H.264\nSecurity, debug, or safety‑crititical\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "RFIC Digital Verification Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-10T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719633762", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nQualcomm is a company of inventors that unlocked 6G ushering in an age of rapid AI acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives.\n\nBut this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 6Gs potential into world-changing technologies and products. This is the AI Invention Age and this is where you come in.\n\n QCT is currently seeking digital verification engineers for the mixed-signal ASICs that support QCTs mobile platforms for next generation 6G RFIC/PMIC/Codec technologies.\n\nSuccessful candidates will be working on the following:\n\n- Block/Subsystem/SoC level digital verification using constrained-random coverage methodologies at both RTL and Gate Level.\n\n- The skills involved includes SV/UVM/UVM_RAL/Randomization/Coverage/SVA.\n\nPreferred Qualifications\n\n- Experience in writing Test Plans independently\n\n- Experience in writing/updating Verification Testbench\n\n-Experience with debugging RTL & Gate level simulations\n\n-Experience with Functional Coverage &Code Coverage\n\n-Experience with Scripting in perl, python, tcl\n\n-Experience in planning Verification architecture, review testbench/ testplans with juniors, identify coverage gaps, propose alternate methods for coverage\n\n- Should have been involved in leading a chip DV effort\n\n-  Should have been self-driven and quick learner\n\n- Experience with Power aware(UPF) verification and debugs is plus\n\n- Silicon Debug Experience a plus.\n\n- Experience with Mixed Signal Designs involving DSP a plus\n\n- Modeling Experience with Matlab, Octave a plus\n\nMinimum Qualifications\n\nRequired: Bachelor's, Electronics or EE\n\nPreferred: Master's, VLSI, Electronics or EE.\n\n1 to 3 years ASIC design, verification, or related work experience\n\nJob Families for Job Profiles\nHardware Engineering\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Sr.Lead STA Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-10T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719658494", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nJob Overview:\nAs a Sr.Lead (STA) Engineer, you will be a key contributor to SoC level timing closure, working closely with RTL, CAD, DFT and physical design teams.\nYou will drive timing analysis and closure for complex, multi‑GHz designs across block, cluster, and full‑chip hierarchies, ensuring aggressive frequency and power targets are met.\n \nRoles and Responsibilities\nWork closely with RTL team to understand different protocols (DDR, PCIE, UCIE etc..), critical paths, and performance goals, and to define, implement, and validate timing constraints.\nPerform STA for high‑performance designs at block, cluster, and SoC/top‑level hierarchies across multiple modes, corners, and scenarios.\nAnalyze timing on frequency‑critical paths and collaborate with RTL and DFT teams to drive logic and micro‑architectural fixes.\nProvide actionable timing feedback to block‑level and top‑level physical design engineers\nGenerate and review timing ECOs (logic and physical) to close setup, hold, noise, and cross‑talk violations.\nNeed to lead STA team for a given project.\nPreferred Qualifications\nBachelor’s or master’s degree in electrical/Electronic Engineering with 5-9 years of hands‑on experience in STA and timing closure.\nStrong experience with STA and timing closure for high‑performance SoCs.\nExpertise in multi‑clock, multi‑domain designs with aggressive frequency targets.\nExperience in deep sub‑micron technology nodes and advanced process technologies.\nProven experience performing STA on large CPU/SoC designs with multi‑scenario and signoff‑quality closure.\nFamiliarity with standard cell libraries,  transistor fundamentals, and worst‑case corner selection for timing signoff.\nStrong understanding of industry‑standard synthesis, and tape‑out flows.\nExcellent communication skills to work effectively with  RTL designers, PD, and CAD teams.\nIn‑depth knowledge of timing effects such as noise, cross‑talk, OCV/variation, and their impact on designs.\nFamiliarity with both Tempus and Primetime STA tools\nFamiliarity with scripting languages like perl, tcl, awk etc..\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Principal Digital Verification Engineer", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-07-10", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Principal-Digital-Verification-Engineer_R2706-25", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nRole Summary\nThe Digital Verification Engineer will be a key driver in the development and implementation of advanced verification methodologies for our digital-based products. The primary objective is to define, develop, and deploy robust verification setups, own the entire verification lifecycle, and continuously optimize the digital verification flow to ensure the highest quality of new product releases, from initial test plan creation through silicon validation support.\n\nKey Responsibilities\nVerification Ownership: Be responsible for the entire verification flow, from initial test plan creation to final product stream-out and silicon validation support.\nMethodology Development: Define and continuously improve the verification methodology and processes for digital designs.\nFramework Architecture: Define the architecture and lead the implementation of UVM-based verification frameworks.\nCode Implementation: Develop comprehensive code for UVM components, tests, sequences, Register Abstraction Layer (RAL), and functional coverage models. Code System Verilog Assertions (SVA) to enhance verification robustness.\nExecution & Analysis: Run verification regressions, thoroughly analyze results, and collaborate closely with design engineers to efficiently debug fail scenarios.\nPost-Silicon Support: Provide support for analytical debug of silicon during the prototype design phase.\n\nRequirements/Qualifications:\n\nQualifications\nRequired Skills\nTechnical Proficiency:Expertise in UVM methodology.\nExtensive experience in architecting and coding moderately complex UVM-based verification frameworks.\nProficiency in System Verilog coding.\nDemonstrated ability to code System Verilog Assertions (SVA).\n\nSoft Skills:Must possess excellent problem-solving skills.\nMust have good communication skills and the ability to work effectively and collaboratively in a team environment.\nMust be self-motivated and committed to producing the best quality results.\n\nPreferred Skills\nScripting: Knowledge of and experience with scripting languages (e.g., Python, Perl, Tcl).\nDomain Knowledge: Experience working with memory products is highly preferable.\nSimulation Environment Expertise: Experience with mixed signal simulation environments is preferable.\n\nExperience & Education\nExperience: Minimum of 10 years’ experience in UVM verification.\nEducation: Bachelor’s degree or higher in Electrical Engineering\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Lead Digital design and verification for MixSignal IP/Subsystem", "company": "NXP", "location": "Noida", "date_posted": "2026-07-10", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Noida/Lead-Digital-design-and-verification-for-MixSignal-IP-Subsystem_R-10064366", "is_hardware": true, "platform": "workday", "jd_text": "Generic Job Description (not Job Level specific): The Digital Design Engineer / Architect is responsible for defining and realizing Digital functions on IPs, Subsystem or IC level based on required specifications. The individual is responsible for design, verification and evaluation of those. The individual is accountable for designing according to specifications, quality and reliability needs. Participation in problem solving for Digital and system domain of the device. Author of the design-specific documentation for internal and external use.\n\nMore information about NXP in India...\n\n#LI-2734", "jd_status": "stored"}, {"title": "Sr. Principal Layout Designer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-07-10", "url": "https://careers.skyworksinc.com/job-invite/77693/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 77693\n\nDescription\n\nRole Overview\n\nCustom IC Mask/Layout design for 40/22nm/other Analog, RF, and mixed/signal circuits. \n\nLead end to end layout development for any blocks/IP from concept to tapeout. \n\nProvide technical guidance on floorplanning, placement, routing, shielding, matching, and layout optimization techniques. \n\nResponsibilities\n\n \n\nWork closely with the junior engineers’ and contractors’ team for scheduling tasks, guiding them in the floor planning of blocks, implementation, reviews, and closure. \n\nWork closely with design engineers and CAD support by maintaining effective communication. \n\nReview and approve layouts for quality, DRC/LVS/PEX closure, EM/IR compliance, ESD robustness, and manufacturability. \n\nDevelop methods to improve efficiency in layout methodology and drive best practices for a quality, reliable and timely outputs. \n\n \n\n#LI-CB1 \n\nRequired Experience and Skills\n\nBachelor / Master’s Degree with 8-10 years of relevant experience \n\nStrong proficiency in using Cadence Virtuoso XL for layout and Calibre for DRC/LVS/PEX.  \n\nIn‑depth understanding of CMOS IC mask design and verification, with solid knowledge of fabrication, electromigration, IR drop, coupling capacitance, device and signal matching, and Layout‑Dependent Effects (LDE). \n\nSelf‑driven professional with effective planning and reporting capabilities. \n\nDesired Experience and Skills\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Sr. Principal Layout Designer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-07-10", "url": "https://careers.skyworksinc.com/job-invite/77694/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 77694\n\nDescription\n\nRole Overview\n\nCustom IC Mask/Layout design for 40/22nm/other Analog, RF, and mixed/signal circuits. \n\nLead end to end layout development for any blocks/IP/chip from concept to tapeout. \n\nProvide technical guidance on floorplanning, placement, routing, shielding, matching, and layout optimization techniques.\n\nResponsibilities\n\nWork closely with the junior engineers’ and contractors’ team for scheduling tasks, guiding them in the floor planning of blocks, implementation, reviews, and closure. \n\nWork closely with design engineers and CAD support by maintaining effective communication. \n\nReview and approve layouts for quality, DRC/LVS/PEX closure, EM/IR compliance, ESD robustness, and manufacturability. \n\nDevelop methods to improve efficiency in layout methodology and drive best practices for a quality, reliable and timely outputs. \n\nRequired Experience and Skills\n\nBachelor / Master’s Degree with 10-12 years of relevant experience \n\nStrong proficiency in using Cadence Virtuoso XL for layout and Calibre for DRC/LVS/PEX.  \n\nIn‑depth understanding of CMOS IC mask design and verification, with solid knowledge of fabrication, electromigration, IR drop, coupling capacitance, device and signal matching, and Layout‑Dependent Effects (LDE). \n\nSelf‑driven professional with effective planning and reporting capabilities. \n\n \n\n#LI-CB1 \n\nDesired Experience and Skills\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Principal Layout Designer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-07-10", "url": "https://careers.skyworksinc.com/job/Principal-Layout-Designer/77692", "is_hardware": true, "platform": "successfactors", "jd_text": null, "jd_status": "source_unavailable"}, {"title": "Verification Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-07-10", "url": "https://careers.arm.com/job/bengaluru/verification-engineer/33099/97592961952", "is_hardware": true, "platform": "talentbrew", "jd_text": "Today, ARM is well recognized as the market leader in the CPU and System IP industry and this has been achieved by consistently delivering reliable and high quality IP products. The cost of design and manufacturing is high and that warrants “right first time” approach for all IP and System products. Time-to-market is essential for our partners to take care of steadfast competition in the marketplace, being first would enable them to get premium value from the end products. In this context, Design Verification of CPU IPs is an exciting challenge requiring an engineering abilities that is both broad and deep.\n\nSystem Validation engineers in this group are responsible for driving validation specifications & methodology and deliver on the validation of IPs for the next generation of compute solution. .You will work closely with architecture, design, verification, modelling, performance analysis, SW development, Emulation and FPGA and Board development engineers.\n \nResponsibilities:\n \nWork with project team to understand, review the system requirements and deliver emulator testbench specifications.\nKey responsibilities will include owning the development of validation platform in emulation, debug methodology, developing and implementing the test content, finding bugs, and running various validation checks for IPs (CPUs and SystemIPs), Interfaces (like CHI, PCIe etc.) in emulation environment. Will guide other members of the team as needed to enable the successful completion of project activities\n \nRequired Skills and Experience :\n\n3-5 Years of Experience!\nBachelors (BS) or Masters (MS/MSc) in Electronics, Electrical or Computer Engineering - although other degrees will be considered with relevant work experience\nYou will need experience of Emulation and system level validation for IPs and sub-systems and ASIC products. Emulation build skills and knowledge for a subsystem in at least one emulation system is required. Execution of the design in emulation platform and knowledge of hardware and software interplay is required.\nYou possess the knowledge of Validation test content using C, C++ etc and how they can be performed in an emulation-based system.\nExpertise on hardware behavioral language (Verilog, System Verilog)\nExposure to producing validation specifications and documentation describing sophisticated designs\nAbility to work under time-scale pressure and meet ambitious targets without compromising on quality\nUnderstanding of the fundamentals of computer architecture, system IP, memory subsystem, accelerator.\nPractical experience of working on Processor based system designs\n\n“Nice To Have” Skills and Experience :\n\nDemonstrated understanding of CPU/ GPU subsystem in SoC environment and proven expertise in owning validation requirements & Validation Plan.\nHands on Experience in validating multiple sub systems for ASICs/ SoCs in system environment ( across Emulation, FPGA and Development/Eval board), owning all phases of validation ( Test development, Execution and Debug) for owned sub systems.\nUnderstanding of SoC security aspects\n\n#LI-PS2\n \nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "IP Verification Lead with PCIe", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-07-09T15:32:00+00:00", "url": "https://global-external-amd.icims.com/jobs/87879/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. SMTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, build, and execute the verification plan for AMD's FPGA, ASIC IPs, resulting in no bugs in the final design.   THE PERSON:  You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.   KEY RESPONSIBILITIES:  Collaborate with architects, hardware engineers, and firmware engineers to understand product requirements Build test plan documentation for functionality, performance and product use caes Develop UVM based testbench with support for directed and random test cases to achieve high quality design Debug test failures, drive bug finding and coverage convergence activities Use AI to drive efficiency and automation Collaborate with partner verification and validation teams to provide silicon debug support   PREFERRED EXPERIENCE:  Proficient in IP level ASIC verification. Knowledge of PCIe, CXL or other IO protocol required Experience with DMA verification is preferred Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog   Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment.   Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Good understanding and hands-on experience in the UVM concepts and SystemVerilog language   Exposure to usage of LLMs, AI Agents in verification is preferred Scripting language experience: Perl, Makefile, shell preferred.   Exposure to leadership or mentorship is an asset   ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-AB1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Staff Engineer, Physical Design", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-09", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Staff-Engineer--Physical-Design_R-101404", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nAbout the Role\nAs a Staff Physical Design Engineer, you will be a key technical contributor driving the physical design implementation, timing closure, and structural backbone of our next-generation designs. In this role, your primary focus will be mastering the critical intersection of global signal planning, advanced clocking architectures, and high-performance physical design interconnects. You will be responsible for translating complex RTL into high-performance silicon implementations by analyzing the design from both a physical layout and a circuit-level perspective—ensuring that long-wire signal distribution and clocking networks inherently support robust electrical performance.\nWe are looking for a \"full-stack\" physical design engineer who understands that chip performance relies heavily on efficient distribution networks. You should be the type of engineer who enjoys diving into schematics and microarchitecture to understand how clocking choices impact PPA, how global wire parasitics affect latency, and how transistor-level behavior influences chip-level signal and timing integrity.\n\nKey Responsibilities- What you’ll do\nAdvanced Clock Distribution & Circuit Design: Architect and implement high-speed, low-skew clock distribution networks (e.g., mesh, H-tree, hybrid topologies). Apply circuit-level understanding to optimize clock buffers, clock gaters, latches, and multi-source CTS.\n\nInterconnect Physical Design: Manage the physical implementation of global signal planning, including high-speed bus routing, long-wire interconnect span limits, and repeater insertion strategies. Optimize long interconnect paths to mitigate RC delay, wire resistance variations, and routing congestion.\n\nCircuit-Level Timing & Noise Integrity: Leverage a strong fundamental grasp of RC interconnect modeling and transistor-level behavior to resolve deep-submicron physical effects—such as crosstalk delay, Electromigration (EM), and dynamic IR-drop on clock and global signal lines.\n\nArchitectural & Circuit Co-Optimization: Partner with RTL and Architecture teams to influence design decisions. Bridge the gap between logic design and circuit reality, identifying bottlenecks early (such as asynchronous clock domain crossings and interconnect span limits) and suggesting structural or microarchitectural optimizations.\n\nTechnical Leadership & Signoff: Act as the subject matter expert for interconnect structures, clock planning, and circuit techniques during implementation. Mentor junior engineers and contribute to the evolution of advanced design methodologies and flows.\n\nRequirements - What you’ll bring\nExperience: 8+ years of hands-on physical design experience with a proven track record of successful tape-outs on advanced process nodes (7nm and below preferred).\n\nClocking & Interconnect Expertise: Deep familiarity with the physical implementation of advanced clocking structures, global interconnect routing, multi-corner multi-mode (MCMM) timing closure, and jitter analysis.\n\nCircuit-Level Understanding: Strong fundamentals in VLSI design, including CMOS circuit behavior, RC delay networks and transistor-level timing/noise concepts.\n\nTool Mastery: Expert-level proficiency with industry-standard EDA tools—specifically Synopsys (Fusion Compiler, PrimeTime) and/or Cadence (Innovus, Tempus) implementation and sign-off tools, with heavy emphasis on CTS, parasitic extraction (RC), and Static Timing Analysis (STA) engines.\n\nProblem Solving: Ability to debug complex timing violations, cross-talk delay, global interconnect routing congestion, and transient IR drop issues with minimal supervision.\n\nEducation: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.\n\nWhy join us?\nIn this role, you will be pivotal in driving Power, Performance, and Area (PPA) optimizations across significant design sections, operating at the critical intersection of clock architecture, global interconnect optimization, and circuit integrity. You will have the autonomy to shape the foundational distribution networks in all our designs, working on diverse product lines from extremely efficient edge devices to demanding high-performance platforms. We offer the opportunity to collaborate with world-class engineers in a supportive, fast-paced, and learning-rich environment.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Staff Engineer, Physical Design", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-09", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Staff-Engineer--Physical-Design_R-101403", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nAbout the Role\nAs a Staff Physical Design Engineer, you will be a key technical contributor driving the physical design implementation of our next-generation IPs. You will be responsible for translating complex RTL into high-performance implementation, ensuring architecture/design achieves its absolute peak physical potential.\nWe are looking for a true \"full-stack\" physical design engineer who is deeply curious about the logic they are building. You should be the type of engineer who thrives at the convergence of microarchitecture and physical layout, enjoying the challenge of analyzing how an architectural datapath choices affect congestion, how a memory floorplan impacts PPA, and how to push the boundaries of Power, Performance, and Area (PPA) through cross-functional collaboration.\n\nKey Responsibilities - What you’ll do\nEnd-to-End Implementation: Drive the complete physical design flow (Synthesis, Floorplanning, P&R, Signoff) for major sub-systems and diverse IP blocks, ensuring they meet or exceed aggressive targets for PPA.\n\nArchitectural & RTL Co-Optimization: Actively partner with RTL and Architecture teams from early-stage design to signoff. Identify physical and structural bottlenecks early—such as routing congestion in complex crossbars, dynamic power hot-spots in execution units, and interconnect span limits—and co-design microarchitectural or structural solutions to overcome them.\n\nCross-Product PPA Push: Apply advanced physical design techniques customized to the unique demands of different design classes. This includes driving extreme leakage/dynamic power efficiency for edge IPs, rigorous reliability and redundancy structures for automotive standards, or maximizing bandwidth and throughput for high-speed fabrics.\n\nTechnical Leadership: Act as the subject matter expert for complex implementation challenges; contribute to flows/methodology/automation; mentor junior engineers and champion best practices.\n\nRequirements - What you’ll bring\nExperience: 8+ years of hands-on physical design experience with a proven track record of successful tape-outs on advanced process nodes (7nm and below preferred).\n\nVersatile IP Implementation Expertise: Deep familiarity with the physical implementation of at least one major IP domain (such as CPUs, high-speed interconnects/fabrics, cache/memory hierarchies, or specialized accelerators) and a proven ability to adapt to new logic classes.\n\nCo-Design Mindset: A strong understanding of how physical design choices influence microarchitecture, with the intellectual curiosity to pick up the specific nuances of diverse product lines.\n\nTool Mastery: Expert-level proficiency with industry-standard EDA tools—specifically Synopsys (Fusion Compiler, PrimeTime) and/or Cadence (Innovus, Tempus) implementation and sign-off suites.\n\nAdvanced Problem Solving: Ability to debug complex physical design challenges, including structural timing violations, routing congestion, and dynamic IR drop with minimal supervision.\n\nEducation: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.\n\nWhy join us?\nIn this role, you will be pivotal in driving aggressive PPA optimizations across significant design sections, operating at the critical intersection of physical layout, RTL design, and hardware architecture. You will have the autonomy to make a substantial impact across our entire product portfolio from highly efficient IoT cores, dense memory systems, and demanding high-performance platforms. We offer the opportunity to collaborate with world-class engineers in a supportive, fast-paced, and learning-rich environment.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Senior Principal Emulation Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-07-09", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Senior-Principal-Emulation-Engineer_R-10064873", "is_hardware": true, "platform": "workday", "jd_text": "Senior Principal Emulation Engineer (G5)\nLocation: Bangalore, India\nExperience: 12+ Years\nOrganization: ACE – Emulation & Prototyping\n\nRole Summary\nLead complex SoC emulation programs and manage the ACE Emulation team in Bangalore. Responsible for driving end-to-end emulation model development, platform enablement, project execution, stakeholder engagement, and team growth while supporting pre-silicon verification, validation, firmware, and software development activities.\n\nKey Responsibilities\nLead planning, development, qualification, and delivery of emulation models for large SoC programs.\nDrive emulation strategy, methodology, performance optimization, and debug infrastructure.\nManage multiple emulation projects, resources, schedules, risks, and customer escalations.\nLead and mentor the Bangalore Emulation team, including hiring, performance management, and technical development.\nCollaborate with Architecture, Design, Verification, DFT, Validation, FW/SW, and Program Management teams to ensure successful milestone execution.\nDrive automation and process improvements to improve model quality, usability, and turnaround time.\nRequired Qualifications\nB.E./B.Tech/M.S. in Electrical, Electronics, Computer Engineering, or related field.\n12+ years of experience in SoC Emulation, Verification, Digital Design, or Pre-Silicon Validation.\nProven experience leading large-scale emulation projects and engineering teams.\nStrong hands-on expertise in Synopsys ZeBu and Siemens Veloce model development, bring-up, debug, and deployment.\nSolid understanding of SoC architecture, RTL design, SystemVerilog/UVM, verification flows, and Linux environments.\nProficiency in scripting and automation using Python, Tcl, Shell, or similar languages.\nDesired Qualifications\nExperience with FPGA-based SoC prototyping platforms and methodologies.\nExposure to firmware/software bring-up and system-level debug.\nExperience working with EDA vendors and leading methodology improvements.\nLeadership Expectations\nStrong technical leadership with the ability to influence product and methodology direction.\nExcellent communication and stakeholder management skills.\nProven ability to lead geographically distributed teams and deliver against aggressive product milestones.\n\nMore information about NXP in India...\n\n#LI-7013", "jd_status": "stored"}, {"title": "Senior ASIC Engineer, Power Integrity", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-07-09", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-ASIC-Engineer--Power-Integrity_JR2014249", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been at the forefront of technological innovation for over two decades. Our journey began with the invention of the GPU in 1999, which revolutionized the PC gaming market, redefined modern computer graphics, and transformed parallel computing. More recently, our advancements in GPU deep learning have ignited the era of modern AI, positioning NVIDIA as a leader in this next wave of computing.\n\nWe are now looking for a motivated Senior Engineer with expertise in Power Integrity, Modeling and Simulation to join our dynamic and growing Circuits Solutions Group. If you are looking for a significant and exciting role in improving the netlist and timing quality of our designs and if you are a strong self-starter and highly motivated individual who loves to collaborate and find solutions to hard technical problems, join us today!\n\nWhat you’ll be doing:\nParticipate in innovative Processor design in deep submicron technologies.\n\nWork as part of a global circuits team to design innovative power delivery and power management solutions.\n\nBuild models of analog and digital circuits and systems in a variety of environments with different degrees of abstraction and complexity.\n\nPerform detailed block-level and system-level simulations to ensure good reliability, performance, and stability of the designs.\n\nBe a mentor/technical lead for junior team members.\n\nWhat we need to see:\nBSEE (or equivalent experience)/MS or PhD degree in Electrical or Computer Engineering with 5+ years of experience.\n\nExperience with industry-standard EDA (Cadence Virtuoso, Allegro) and simulation tools (VCS, HSpice, Spectre, Primesim, etc.).\n\nExperience modeling and simulating digital and analog circuits and systems.\n\nExperience/familiarity with Analog and Mixed Signal (AMS) simulations, as well as standard languages like Verilog and VerilogA.\n\nWays to stand out from the crowd:\nHands-on experience modeling and simulating complex power delivery networks (PDN) from die level all the way to platform level.\n\nFamiliarity with other industry-standard tools such as Ansys Siwave, HFSS, Sigrity, Matlab/Simulink, Simplis, etc.\n\nUnderstanding of control loops and feedback systems is a plus.\n\nProficiency in scripting language, such as, Perl, Tcl, Python, Skill, and automation methods/algorithms is a plus.\n\nWe are dedicated to solving some of the world's most complex problems, from healthcare to robotics, self-driving cars to blockbuster movies, and beyond. Our work in AI and digital twins is transforming industries and profoundly impacting society. We thrive on seamless collaboration, shared success, and a commitment to diversity and individuality. Everyone at NVIDIA contributes, and everyone belongs. Join us at NVIDIA, where you will be part of an eclectic, passionate group of professionals dedicated to making a lasting impact on the world. Together, we will continue to push the frontiers of technology and create a better tomorrow.", "jd_status": "stored"}, {"title": "Silicon Power Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-07-09", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Silicon-Power-Engineer_JR2013002", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking a highly motivated, experienced Hardware Engineer to join our dynamic and fast-paced Silicon Solutions Group! Artificial intelligence is changing the world significantly starting with the technologies used in our day to day lives, cars we drive, autonomous machines in agriculture farms & factories, smart cities and science & technology development activities. GPUs are providing spectacular speed ups to scientific and medical research, enabling the advancement of humanity like never before. There has never been a more exciting time to work in NVIDIA.\n\nAs part of the Silicon Solutions Team, we architect and deliver groundbreaking solutions for productizing NVIDIA's chips into consumer, professional, server, mobile, and automotive markets. Silicon characterization, correlation to arch & design expectations, finalize product specifications, develop productization techniques and infrastructure around it are part of our responsibilities. Dealing with challenges of the latest process node technologies is also part of the work.\n\nWhat you'll be doing:\nPerform test case execution, debug silicon issues related to correlation and functionality, generate high quality results and provide design feedback.\n\nFind creative solutions to sophisticated silicon and system level problems and be on the frontline to lead show-stopper bugs, to enable product shipment.\n\nWork alongside system architects, chip and board designers, software/firmware engineers, HW/SW applications engineers, process/reliability specialists, ATE engineers, and operations in a dynamic & high-energy work environment to bring industry-defining products to market.\n\nCollaborate with cross-functional teams to craft essential next generation product features that are important for performance, power optimization, and power management.\n\nCollaborate to craft tools for post-silicon work, build post-silicon method‐ ologies to characterize silicon power, correlate silicon behaviour with simulation\n\nWork with various Arch & Design teams to come up with test plans of new features.\n\nCollaborate with other validation &bring up teams to bring up/characterize silicon power and power saving features.\n\nWork with design & estimation teams to correlate with pre-silicon expectation, work with HW and SW teams to do the vital tuning and optimization of silicon power.\n\nDevelop power consumption models to be used in binning, productization and customer application notes, characterize and develop various power control mechanisms together with Arch/Design/SW teams.\n\nWhat we need to See:\nB. Tech or M. Tech in Electronics Engineering stream, with 2+ years related work experience, excellent problem solving, collaborative, and interpersonal skills.\n\nStrong understanding of aspects related to silicon power and performance, technology node impacts, Hardware and Software interactions at system level.\n\nHands-on experience with silicon bring up, validation and productization, good knowledge in board and system design considerations, Power supply design.\n\nVery good problem solving and hardware debugging skills, very good data analysis and logical reasoning skills.\n\nStrong familiarity with HW lab environment and understanding of various lab equipment.\n\nExperience in working with windows. Linux exposure is highly preferred.\n\nWorking experience with scripting languages like perl and/or python is a plus point.\n\nMust be a great teammate and ready to collaborate with global teams from diverse cultural backgrounds in a high energy environment.\n\nExposure to critical path analysis, power analysis, process technologies, transistor/device physics, silicon reliability and aging mechanisms.\n\nBackground with power supply and substrate noise analysis and mitigation. Exposure to digital design, circuit analysis, computer architecture, BIOS, drivers, and software applications.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior Engineer-STA", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-07-09", "url": "https://careers.arm.com/job/bengaluru/senior-engineer-sta/33099/97551864016", "is_hardware": true, "platform": "talentbrew", "jd_text": "Responsibilities:\nTiming constraints development and validation for functional and test modes\nTiming analysis and closure responsibilities at SoC level as well as block/subsystem level\nECO generation and tracking to closure by collaborating with PD, Design, Constraint team and other partners\nRequired Skills and Experience :\nExperience in performing timing closure at SoC level and block level\nHands-on experience with industry leading STA and ECO generation tools(PrimeTime, Tempus, Tweaker)\nIP integration and timing signoff\nMust have worked on lower technology nodes, preferably sub 7nm\nStrong data analysis and presentation skills\nWell versed with TCL/PERL or Python\nExperience in collaborating across silicon engineering groups in your organization as well as with EDA vendors\nWork experience of 2-5 years in Physical Implementation and Signoff methodologies\nStrong Communication and Problem-Solving Skills\n\nIn Return:Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of any characteristic.\n\n#LI-PS2\n \nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\n\nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Functional Verification Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-08T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719498539", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nResponsibilities\nWill be responsible for verification of IP, Block or Subsystem at Soc Level\nGenerate appropriate documentation for verification (e.g. test plan, test strategy document, assertion list etc)\nResponsible for analyse / debug given blocks/tasks in verification\nShould be able to develop and own the verification environment, verification components developed\n\nRequirements\n2-6 years of experience with a Bachelors/ Master’s degree in the field of Electrical, Electronics or computer engineering\nShould have good understanding of verification flow, challenges and requirements of functional verification\nShould have worked on IP level or Block level or SoC level functional verification\nSkilled in the aspects of digital verification such as constrained random verification, functional coverage, code coverage, assertions, methodology & philosophy\nExpert in System Verilog, Verilog and OVM/UVM verification methodology\nShould have working experience on AMBA interface protocols (AXI, AHB, APB)\nKnowledge of Verilog/System Verilog, digital simulation and debug is a must\nHands on experience on working one or more of the following protocols is a must – UART, I2C, SPI, QSPI, I3C, eMMC, CAN,\nHands on experience on working with one or more of following protocols is desired – PCIe, USB, DDR, LPDDR, GBE, SATA\nExperience with Perl, python or similar scripting language is required\nAbility to adopt & learn quickly and willingness to proactively take on responsibilities beyond the job description to accomplish team goals\nWorking knowledge of industry standard debug tools, waveform viewer is essential\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "STAFF Engineer -DEG Layout", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-08T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/41980975", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nRole and Responsibilities\nResponsible for layout design and development of critical analog, mixed-signal, custom digital block, standard cells  and full chip level.\nPerform layout verification like LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem checks,  quality check and documentation.\nResponsible for development of digital block layouts using auto placement and route tools\nResponsible for basic understanding of skill coding and automation\nResponsible for on-time delivery of block-level layouts with acceptable quality.\nDemonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/breakthroughs in multiple project environment.\nGuide developing team-members in their execution of Sub block-level layouts & review their work\nChip in to effective project-management.\nEffectively communicating with Global engineering teams to assure the success of layout project.\nResponsible for the reducing the layout effort by using AI tools\n\nQualification/Requirements\n10 to 14-year experience in analog/custom layout design in advanced CMOS process.\nExpertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.\nShould have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,\nGood understanding of Analog Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc.)\nUnderstanding layout effects on the circuit such as speed, capacitance, power and area etc.,\nAbility to understand design constraints and implement high-quality layouts.\nExcellent command and problem-solving skills in physical verification of custom layout.\nMultiple Tape out support experience will be an added advantage.\nAutomate layout execution tasks using AI\nExcellent verbal and written communication skills.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Senior Manager, Design Evaluation Engineering", "company": "Analog Devices", "location": "India, Bangalore, Nova", "date_posted": "2026-07-08", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-Nova/Eval-Manager--Consumer-Audio_R260111", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nJob Description:\nADI’s ULP Audio Business Unit is looking for a dynamic and enthusiastic leader to work with a multi-faceted team of individuals equipped with the knowledge required to create complete solutions, including aspects of acoustics, connectivity, algorithms, and software engineering.\nYour main role will be to lead pre and post silicon validation of mixed signal audio edge processors with integrated connectivity such as Bluetooth in addition to product customer support. This position requires strong working knowledge of Analog (ADC, DAC, Power, and Audio) circuits, connectivity standards such as Bluetooth and embedded software development systems. If you are excited about solving customer challenges, then our team might be your next career step.\nMinimum Qualifications:\nBSEE/MSEE in Electronics/Electrical/Computers or equivalent degree with more than 15 years’ experience\nStrong experience in pre and post silicon validation and board bring up\nHands on knowledge of hardware design and adept at usage of oscilloscopes, signal generators, power supplies and logic analyzers etc.\nStrong fundamentals in one or more protocols like SPI, I2C, UART, USB, Bluetooth, WiFi etc\nWorking Knowledge of embedded systems programming with proficiency in assembly programming a nice to have.\nComfortable in a leading technical communication with customer and experience in creating hardware reference documents and datasheets.  \nExcellent written and verbal communication skills\nPreferred Qualifications:\nPassion for Audio or Music\nPractical Audio experience in semiconductor or system company\nExperience with test equipment such as Audio Precision, NTi, HATS etc.\nKnowledge of signal processing techniques and digital audio including relevant interface protocols\nAt least two years of experience in supervising and mentoring teams\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Senior Packaging Technical Engineer - Hardware", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-07-08", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Packaging-Technical-Engineer---Hardware_JR2012324", "is_hardware": true, "platform": "workday", "jd_text": "We are now looking for a Senior Packaging Technical Engineer. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing.\n\nNVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work , to amplify human imagination and intelligence. Make the choice to join us today.\n\nWhat you’ll be doing:\nYour responsibilities include defining the chip pad ring, substrate interconnect scheme, and lead the package layout design process.\n\nWe collaborate with large teams consisting of Circuit, Signal Integrity, RTL, Place and Route, substrate layout and system design Engineers and Managers.\n\nWork to define a chip floor plan, pad ring, substrate, and ball out implementing a robust world-class electrical package!\n\nCommunicate effectively with various teams throughout the company\n\nWhat we need to see:\nBSEE or equivalent experience.\n\nMinimum of 8+ years in board/system design. Experience with package design is preferred.\n\nGood understanding of transmission line theory, power delivery and signal integrity is desired.\n\nStrong programming and scripting skills in Perl, Python, Tcl desired, Cadence Skill and EXCEL familiarity are helpful.\n\nEnthusiastic and able to work with a minimum of supervision.\n\nYou seek to solve complex technical problems.\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We welcome you join our team with some of the most hard-working people in the world working together to promote rapid growth. Are you passionate about becoming a part of a best-in-class team supporting the latest in GPU and AI technology? If so, we want to hear from you.", "jd_status": "stored"}, {"title": "Principal Design Verification Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-07-08", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2504707", "is_hardware": true, "platform": "oracle", "jd_text": "Senior Principal Digital IC Verification Engineer - Digital Compute Team \n\n \n\n \n\nAbout Us \n\n \n\n \n\nAt onsemi, we help improve lives through silicon solutions every day. Our intelligent power and sensing technologies solve the world’s most complex challenges and lead the way in creating a safer, cleaner, and smarter world. Our group develops MCU and DSP systems as well as hardware accelerators that are used in a large variety of different products and markets. \n\n \n\n \n\nThe Role \n\n \n\n \n\nWe are expanding the team to India and are looking for a Senior Principal Digital IC Verification Engineer. You will participate to the development of embedded MCU and DSP systems as well as hardware accelerators for cryptography. \n\n \n\n \n\nWhy Join Us \n\n \n\n \n\nWe create a diverse set of world-class products in a friendly and team-oriented atmosphere. We provide an environment of continual learning and growth opportunities and support volunteer & charitable programs. We offer a competitive benefit package and a great place to work. You will be able to build up a career in a successful international company, and you can participate in interesting international projects. \n\n \n\n#LI-RT1\n\nResponsibilities\nWhat You’ll Do \n \n\nDefine the verification strategy and the detailed verification plans for blocks and systems \n\nCoordinate/lead the verification activities in the project teams and reach verification closure for the projects \n\nDevelop SystemVerilog/UVM environments for blocks and top-level SoCs \n\nDebug functional errors in RTL \n\nParticipate to verification methodology improvement activities \n\nCoach and mentor younger engineers \n\n \nWhat You’ll Need \n \n\nMinimum BS/MS in Electrical Engineering or related technical field \n\nAt least 13 years of digital verification experience \n\nSolid understanding of verification best practices such as verification planning, requirements tracking, and functional coverage \n\nIn-depth knowledge and some years of proven experience in state-of-the-art verification methodologies (e.g. UVM), constrained random driven verification, assertion-based verification, test environment architecture & creation, regression management, coverage collection, and formal verification \n#LI-RT1\n\nQualifications\nExperience in technical project/task leadership \n\nExcellent written and verbal communication skills in English \n\n \nWhat Else You May Bring  \n \n\nExperience in some of the following areas is a plus: \n\nExperience in the verification of CPU/MCU (sub)systems, SystemRDL or IP-XACT \n\nProgramming in Python for automation and in C/C++ for embedded software \n\nVerification of signal processing components \n\n3rd party verification IP deployment \n\n \nOur commitment to you \n \n\n \nAs part of the onsemi team, you will have an opportunity to transform your tomorrow and operate in a diverse, inclusive, and socially responsible environment. If you’re passionate about shaping a better future, join us and define your future! \n#LI-RT1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Principal Electrical Engineer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-07-08", "url": "https://careers.skyworksinc.com/job/Principal-Electrical-Engineer/77594", "is_hardware": true, "platform": "successfactors", "jd_text": null, "jd_status": "source_unavailable"}, {"title": "Analog IC Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-07-08", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25011677", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\nThe Interface Multiplexers group is hiring passionate analog design engineers for their team in Bangalore. You’ll create ultra‑fast (Multi‑GHz) analog multiplexers and switches with NRZ/PAM4 signaling, handling multi‑voltage domains, sub‑Ohm ON resistance (≤1% ΔRₒₙ), nA‑level off‑leakage, ≥30 dB off‑isolation, and 40 V fault tolerance. These high‑speed, low‑loss switches power cutting‑edge data‑center, consumer, medical, test‑and‑measurement, and high‑fidelity audio systems\n\n This is a great opportunity to be part of an established team that's continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electronics, mobile computing and communications.\n\nIn this role, responsibilities may include:\n\nLead an Analog IC design team with product ownership and responsibility from definition to release to manufacturing\n\nDirect, guide and participate in activities of a research or technical design function responsible for designing, developing, modifying and evaluating electronic parts, components, integrated circuits for a variety of applications\n\nMake assignments for team members, providing design guidance as needed, developing schedules and monitoring progress throughout the project\n\nEvaluate intermediate and final results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout\n\nCollaborate with Design Verification teams during the pre-PG phase of a project to ensure completion of all technical tasks before PG\n\nWork with systems engineers, application engineers and marketing to prepare product briefs, datasheets, application notes and assisting in the definition of the product to meet customer needs as well as contributing to roadmap formulation and new concept creation\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nInterface and lead discussions with the customer and/or TI field sales/field applications teams to understand customer designs, problems and support as required\n\nActively participate in hiring, developing and evaluating personnel to ensure efficient operation of the organization and growth of the individuals into leader", "jd_status": "source_unavailable"}, {"title": "Senior Digital Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-07-07T05:55:49.591000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000136141039-senior-digital-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Job Purpose and Dimensions:\nDevelop micro-architecture and front-end digital design deliverables from concept to silicon with minimal supervision\nDevelop digital functional blocks for various power management ASICs\nPrincipal Accountabilities:\nLead optimized digital blocks design meeting functional and low power constraints and ensure spec compliance\nMust have experience of defining Digital/Analog boundaries and digital design scope for Power Management ICs\nMust have experience of defining the micro-architectures and sub-blocks for the ICs to ensure optimized Digital design, RTL design and Gate level netlist etc\nMust be able to handle Clock Domain Crossing across multiple clock domains seamlessly and in a glitch free manner. Should be able to lead/collaborate for Logic Synthesis, Formal verification, Power estimation and STA\nShould have experience of OTP, MTP, Efuse read/writes, controller design and data bus handling, Register read/write, Trimming of Analog parts/functions\nShould be familiar with one or more Power Chip Communication I/Ps and protocols e.g. I2C, PMBUS, SPI etc.\nVerification test planning, feature extraction and verification test case development\nExperience with silicon debugs, root cause analysis of issues\nSupport DFT strategy and implementation\nInterface with Placement and Route team for digital hand-off and post layout verification\nPerform physical silicon device area and power evaluation where necessary\nAuthor high-quality documentation for digital blocks\nKey Performance Measures:\nMicro-architecture, functional, test plan specification delivered according to project schedule\nRTL coding using Verilog/System Verilog\nFirst time right success rate\nPro-actively taking ownership of responsibilities\nDeliver quality Spec and RTL within predictable schedule\nKnowledge, Skills and Experience:\n3-6 years of experience in Logic design /micro-architecture / RTL coding\nMust have hands on experience with Power product design, synthesis and timing analysis for complex Digital Circuits\nExperience in Verilog/System-Verilog is a must\nExperience working in semiconductor ideally PMIC with focus on mixed signal integrated circuits \nHands on experience developing block and top-level timing constraints for STA and Placement and Route sign off \nUnderstanding of design constraints and synthesis scripts \nWork independently on straightforward tasks, with little direction from manager \nAbility to propose innovative solutions \nResults-oriented and able to deliver on-time under a tight schedule \nCross cultural awareness and sensitivity \nProactive attitude about own role and contribution to company goals \nAbility to work both independently and part of a team \nFlexible to undertake occasional international travel at short notice \nExcellent command of verbal and written English \nConcise and precise communication and interpersonal skills within multi-site and multi-cultural environment \n\nDegree level qualification in Electronics Engineering\n3-6 years of relevant experience required.\nKey Relationships:\nDesign team, in particular TPL (Technical Project Leader) and digital leads/manager\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Mgr/Sr Mgr, Analog Engineering", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-07-07T05:51:42.265000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000136140592-mgr-sr-mgr-analog-engineering", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Manage the design team for day-to-day work \nPlan design resources to complete top-level schematic, layout and provide on-time tape out \nTechnical project lead and/or technical guidance \nAnalog and Power design of integrated circuit development projects \nHands-on block level design from specification to clean database \nInterface with layout, verification, test, product and application engineers to successfully bring new products from initial concept through release to production \nParticipate in discussions and draft documents of technical issues and other design aspects with internal teams and customers \nInstigate regular peer reviews with other analog engineers \nGuide the layout of circuit blocks for high-speed performance and precision operations \nAnalyze different process options to select the best process for given target application \nDrive specification requirements for the chip \nVisit customers to learn about the application and total system level solution \nRun block-level and top-level mixed-mode simulations to meet datasheet parameters \nLab evaluation and support for circuit blocks/whole ICs \nSupport test development and ramp to production \nManage the design team for day-to-day work \nPlan design resources to complete top-level schematic, layout and provide on-time tape out \nTechnical project lead and/or technical guidance \nAnalog and Power design of integrated circuit development projects \nHands-on block level design from specification to clean database \nInterface with layout, verification, test, product and application engineers to successfully bring new products from initial concept through release to production \nParticipate in discussions and draft documents of technical issues and other design aspects with internal teams and customers \nInstigate regular peer reviews with other analog engineers \nGuide the layout of circuit blocks for high-speed performance and precision operations \nAnalyze different process options to select the best process for given target application \nDrive specification requirements for the chip \nVisit customers to learn about the application and total system level solution \nRun block-level and top-level mixed-mode simulations to meet datasheet parameters \nLab evaluation and support for circuit blocks/whole ICs \nSupport test development and ramp to production \n\nBSEE (MSEE pref.) or equivalent with 11-20 years professional industry experience in Analog design engineering role \nExperience in management position \nMust have a design experience with several of the following: ADCs (SAR/Sigma Delta), precision amplifiers, bandgap references, switching regulators, LDOs, DAC, system level simulation \nDesign experience in CMOS/BICMOS is required \nExperience working with small geometry BCD processes is a plus \nAdvanced knowledge of Mixed-Signal Cadence tools and parasitic-extraction is preferred \nMust have a written and verbal cross-functional communication skills \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Staff Engineer , Analog Design", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-07T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/42248903", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nResponsibilities will include, but are not limited to:\nContributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits.\nDesign, implementation, and improvement of Complex Analog Power Management IPs such as Bandgap reference, Voltage/Current reference, Regulators, Charge-pumps, CMOS Amplifiers, Comparators in advanced semiconductor process nodes for advanced DRAM products.\nParasitic modeling and assisting in design validation, reticle experiments and required tape-out revisions.\nBeing responsible for and managing the layout process including floor-planning, placement, and routing.\nPerforming verification processes with modeling and simulation using industry standard simulators.\nContributing to cross group communication to work towards standardization and group success.\nWorking with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product.\nProactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality.\nDriving innovation into the future Memory generations within a dynamic work environment.\nLeveraging AI\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "CPU DFT Manager", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-07-07", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/CPU-DFT-Manager_JR0285257", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nKey Responsibilities:\nLeadership and Management:\n-Manage and technically guide a high-performing DFT team focused on X86 CPU DFT design and validation.\n-Develop detailed execution plans for parallel activities across multiple projects and ensure timely, high-quality delivery.\nDFT Design and Verification:\n-Implement JTAG, Memory BIST, and Memory Repair (BIRA/BISR) circuitry using industry-standard tools.\n-Drive DFT verification for features such as scan, arrays, and DFD using RTL simulations and emulation.\n-Create plans and tests for validating portions of complex microarchitecture using written specs, RTL code, and other test guides.\nTechnical Problem Solving:\n-Debug failures to root cause and learn architecture/microarchitecture deeply.\n-Collaborate with post-silicon/manufacturing teams on ATE, debugging and resolving issues.\n-Cross-Functional Collaboration:\n-Work closely with global stakeholders to address DFT challenges and improve product quality.\n-Ensure alignment of timelines and deliverables across sites.\n\nQualifications:\n•\t10+ years of experience in DFT domain at IP or SoC level.\n•\t5+ years of experience managing and leading teams.\n•\tStrong knowledge and experience in Spyglass DFT.\n•\tHands-on skills in implementing JTAG, Memory BIST and Memory Repair (BIRA/BISR) circuitry.\n•\tExpertise in DFT Design and verification using RTL simulations and emulation.\n•\tGood understanding of timing constraints and DFT mode timing analysis.\n•\tProficiency in RTL coding and shell scripting.\n•\tExperience working with post-silicon/manufacturing teams on ATE, including debugging and issue resolution.\n•\tExperience with X86 CPU architecture and microarchitecture.\n•\tFamiliarity with advanced process nodes and hierarchical DFT strategies.\n•\tStrong communication and leadership skills for cross-site collaboration.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nBusiness group:\nSilicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Senior Verification Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-07-07", "url": "https://careers.arm.com/job/bengaluru/senior-verification-engineer/33099/97460323488", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview\n \nOur Solution Engineering division develops and verifies IPs for a variety of SoC projects, integrating both internally developed designs and third-party IP.\nWe are looking for a creative and motivated Senior Verification Engineer to verify RTL implementing new features in Arm-based SoCs, ensuring both new and existing functionality meets architectural and quality requirements.\n \nResponsibilities\n \nIn addition to bringing your accomplishment of either a Bachelor's or Master's degree in Computer Science, Electrical/Computer Engineering, or a related field, you will:\n \n- Collaborate closely with RTL designers and architects to understand specifications and microarchitecture details.\n- Develop new verification environments and enhance existing environments, including stimulus generation, checking, and coverage infrastructure.\n- Create and execute verification plans and test plans.\n- Implement verification strategies in partnership with other verification engineers.\n- Drive functional and code coverage closure.\n- Debug and resolve complex design and verification issues.\n- Contribute to continuous improvement of verification methodologies, infrastructure, and best practices.\n- Provide technical guidance and support to less experienced engineers.\n \nRequired Skills and Experience\n \n- 5+ years of experience in IP, subsystem, or SoC verification.\n- Strong proficiency in SystemVerilog and Verilog.\n- Experience with UVM or other industry-standard verification methodologies.\n- Experience developing constrained-random verification environments and reusable verification components.\n- Experience creating verification plans and test plans.\n- Understanding of SoC verification, including software-driven verification flows.\n- Experience with scripting languages such as Python, Perl, or similar.\n- Strong debugging, analytical, and problem-solving skills.\n- Strong interpersonal and communication skills, with the ability to collaborate effectively across geographically distributed teams.\n \n'Nice To Have' Skills and Experience\n \n- Experience with Arm-based designs and/or Arm system architectures.\n- Experience with AMBA protocols such as CHI, AXI, AHB, and APB.\n- Experience with JTAG, SWD, or TAP-based debug infrastructures.\n- Experience with clock domain crossing (CDC), reset domain crossing (RDC), and power-aware verification.\n- Exposure to low-power design techniques and UPF/CPF methodologies.\n- Experience with DFT concepts, including scan and MBIST.\n10x Mindset at Arm\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Read more about how we bring the 10x mindset to life on the Arm blog.\n \n#LI-SC2\nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Digital backend engineer", "company": "NXP", "location": "Noida", "date_posted": "2026-07-07", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Noida/Senior-Digital-backend-engineer_R-10064364", "is_hardware": true, "platform": "workday", "jd_text": "Generic Job Description (not Job Level specific): The Digital Physical Design Engineer / Architect is responsible for a physical implementation of IP, Subsystem or IC design. The individual is responsible from RTL synthesis to GDS implementation and optimization of design including floorplanning, routing, timing convergence (STA) including related design ECO and physical verification for fulfilling all Technology & reliability related rules, such as DRC/LVS/Electromigration/IR drops. The individual contributes to problem solving related to physical design. Contributes to define best Physical design strategy per technology node.\nMore information about NXP in India...\n\n#LI-2734", "jd_status": "stored"}, {"title": "Staff Verification Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-07-07", "url": "https://careers.arm.com/job/bengaluru/staff-verification-engineer/33099/97460326192", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview\n \nOur Solution Engineering division develops SoCs for various application segments, using the latest IP products from Arm and other vendors.\nWe are looking for a creative and hard-working Verification Engineer to verify RTL implementing upcoming features in the ARM SoC, ensuring both new functionality and existing features meet architectural requirements.\n \nResponsibilities\nCollaborate closely with the RTL team in different Geography, to understand microarchitecture details\nDevelop new verification environments and enhance existing verification environments, including stimulus generators, and checkers\nVerify new ARM architecture features function as specified and do not impact existing functionality\nImplement verification strategies in partnership with other verification engineers\nContribute to continuous improvement in verification methodology based on learnings\nMentor early-tenure verification engineers\n \nRequired Skills & Experience:\n \nIn addition to bringing your accomplishment of either Bachelors or Master’s degree in Computer Science or Electrical/Computer Engineering or a similar related field, you will demonstrate:\nMore than 8 years of proven experience in an IP/SOC verification\nAdvanced proficiency in System Verilog and Verilog, with deep knowledge of UVM Methodology.\nExperience writing verification plan and test plan.\nExperience with Testbench development using any standard verification methodology\nExperience with Perl, Python or other scripting language\nStrong interpersonal skills to collaborate with multi-functional and geographically distributed teams to accomplish tasks\n \n'Nice to Have' Skills and Experience:\nExperience with AMBA protocols (CHI, AXI, AHB, APB, ATB), JTAG/SW/TAP.\nHands-on experience with Arm CoreSight IP and debug/trace architectures.\nExperience with ARM-based designs and/or ARM System Architectures\n \nIn return:\nYou will get to utilize your engineering skills to build support for the latest technologies and systems, impacting products in existing and emerging areas for years to come!\n \n10x Mindset at Arm\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, priorities collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Read more about how we bring the 10x mindset to life on the Arm blog.\n \n#LI-SC2\nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Staff Design Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-07-07", "url": "https://careers.arm.com/job/bengaluru/staff-design-engineer/33099/97460325616", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview\n \nOur Solution Engineering division develops SoCs for various application segments, using the latest IP products from Arm and other vendors.\nWe are looking for a creative and hard-working SoC Design Engineer to join the team and help develop Debug Subsystems, based primarily—but not exclusively—on CoreSight IPs.\nAs a member of the design team, you will contribute to the specification, design, and verification of various subsystems.\n \nResponsibilities\nDesign engineers are required to demonstrate deep technical expertise across the full spectrum of activities that enable successful product delivery. This includes strong proficiency in low-power and high-speed design techniques, along with the ability to develop solutions that are highly optimized for area efficiency.\nKey duties involve defining and documenting micro-architecture specifications, developing RTL implementations, and performing comprehensive design checks to ensure correctness and quality.\nEngineers will work in close partnership with the verification team to assess test coverage, review verification plans, and assist in debugging and resolving design defects.\n \nRequired Skills & Experience:\nIn addition to bringing your accomplishment of either Bachelors or Master’s degree in Computer Science or Electrical/Computer Engineering or a similar related field, you will need:\nMore than 10+ years' experience working in design of complex subsystems or SoCs\nExperience with ARM-based designs and/or ARM System Architectures\nHands-on experience with Arm CoreSight IP and debug/trace architectures.\nAdvanced proficiency in SystemVerilog and Verilog.\nExperience with power, clock domain crossing, and reset domain crossing\nExperience with Perl, Python or other scripting language\n \n'Nice to Have' Skills and Experience:\nExposure to low-power design techniques (UPF/CPF).\nExperience with DFT concepts: Scan, Mbist, SSN...\nWork with physical design teams to address floor-planning, clocking, reset strategies, and timing closure considerations.\nLeadership, mentoring or coaching experience\n \n#LI-SC2\nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Pre-si Verification Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-07-07", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Pre-si-Verification-Engineer_JR0285305", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Client Engineering Group is looking for a highly motivated Pre-Si SoC Verification Engineer to join the graphics instead die frontend design and verification team for the next generation of Client SOC. In this role, the candidate's responsibilities include, although not limited to:\nResponsible for ensuring functional correctness and quality of SoC designs before silicon tape-out, through simulation, emulation, and advanced verification methodologies.\nThe role involves testbench development, coverage-driven verification, and debug of complex SoC architectures.\n\nQualifications:\nExperience : 8 to 15 years\n\nKey Responsibilities\n• Define and develop SoC / subsystem / IP verification plans aligned to architecture specifications\n• Build and maintain System Verilog/UVM-based testbenches and verification environments\n• Develop constrained-random and directed test scenarios and validation content\n• Execute simulation and emulation-based verification to validate functionality, power, and performance\n• Perform debug and root-cause analysis of RTL and testbench failures in pre silicon environment\n• Analyze and drive functional, code, and assertion coverage closure\n• Collaborate with architecture, RTL design, post silicon, and validation teams\n• Document verification plans and participate in design/verification reviews\n• Continuously improve verification methodology, infrastructure, and automation flows\n• Incorporate learning from post silicon validation to enhance future verification coverage\n• Good at leveraging AI across verification coding, debugging , quality sign-off requirements.\n• Minimum 8-15 year of relevant experience in SoC/subsystem/IP level verification\n• Qualifications BE or B Tech or M Tech ECE or Computer Science with 8-15 years front-end pre-si verification.\n• Lead verification activities while mentoring and guiding junior team members to ensure high-quality project execution.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nBusiness group:\nSilicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Senior Staff Engineer Design", "company": "Infineon", "location": "Bangalore BTP (India)", "date_posted": "2026-07-06T16:09:48+00:00", "url": "https://jobs.infineon.com/careers/job/563808961408546", "is_hardware": true, "platform": "eightfold", "jd_text": "Job Description\nIn your new role you will:Contribute to the implementation of highly complex automotive SoC designs in a multi-site organization covering all aspects of Physical Design.\nWork independently in different phases of the RTL2GDS flow: With focus on (one or many) Synthesis, Constraints and equivalence check, Generation of Floorplans, Placement, Clock Trees, Routing and Power Distribution Network for efficient Timing Closure with Signal Integrity and Physical Sign off including Power Integrity\nWork with industry standard tools for physical design and signoff with good understanding of scripting languages (shell, perl, tcl) and Make flow.\nFocus on PPA, define the Partition shapes, pins and feedthrough along with IP integration guidelines are followed (reviewed along with IP owners) to suit the requirements.\nAnalyze and solve problems of high complexity using your global expert network\nDrive the PnR closure of multimillion gate designs in lower technology nodes, perform SoC level IR/EM analysis, debugging and fixing.\nRunning SoC level Physical verification, debugging and fixing including Chip finishing, metal fill, Sealring and Tapeout checks\nBe a member of an expert network and drive innovation, methodology for the RTL to GDS2 development cycle of next generation automotive SoCs.\n\nYour Profile\nYou are best equipped for this task if you have:\nA degree in Electrical Engineering, Microelectronics or a similar field.\nAt least 8 yrs of exp in Physical Design of highly complex SoCs.\nUnderstanding of RTL coding, IP handling (including internal/external) along with integration issues is big plus.\nProgramming skills and knowledge in scripting languages like Tcl, Perl or Python.\nExperience in working as a member of SoC design teams with high cost and quality awareness.\nFluent English language skills – with German being an added plus.\nUnderstanding of industry standard tools for physical design and signoff\nBe a quick learner and become productive from the beginning\nBe a team player while taking and acting on responsibilities.\n\nContact:\n    Gowri Shenoy, LinkedIn\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\nThis means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.\nPlease let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.\nClick here for more information about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Senior Staff Engineer Software", "company": "Infineon", "location": "Bangalore MG (India)", "date_posted": "2026-07-06T03:39:20+00:00", "url": "https://jobs.infineon.com/careers/job/563808971417835", "is_hardware": true, "platform": "eightfold", "jd_text": "Provide hands-on technical leadership for the architecture, design, development, verification, integration, and delivery of virtual prototypes for Infineon Automotive Microcontrollers based on heterogeneous multi-core architectures, including CPU cores such as TriCoreTM, Arm, RISC-V, vector DSP, and related technologies.\n\nYour Role\n\nKey responsibilities in your new role\n\nAct as hands-on technical lead for virtual prototype and system modelling, covering architecture, implementation strategy, design reviews, and best practices using SystemC, TLM 2.0, CCI, UVM,  Synopsys Virtualizer, ASTC VLAB, and related ESL tools.\nLead requirements analysis and define scalable SystemC model architectures aligned with product, verification, and software  enablement goals.\nOwn SystemC model implementation and unit verification, ensuring quality, maintainability, reuse, and milestone alignment.\nLead virtual prototype integration, system testing, and complex debug with drivers, startup software, and RTL SoC verification environments.\nSupport quality governance, audit readiness, technical sign-off, issue closure, and release readiness.\nDrive root-cause analysis and cross-functional debug for internal and external stakeholder use cases.\nIdentify and mitigate risks across architecture, implementation, verification, integration, and delivery.\nImprove design and test methodologies, automation, reuse, quality practices, and responsible GenAI-assisted workflows for virtual prototype development.\nCollaborate with RTL IP, subsystem, and SoC teams to enable early testbench development, verification readiness, and cross-domain  alignment..\nBuild team competence through mentoring, knowledge sharing, hiring support, training, and continuous capability development.\n\nYour Profile\n\nQualifications and skills to help you succeed\n\nB.Tech, B.E., M.Tech, or M.S. in Electrical Engineering, Electronics, Computer Science, Instrumentation, or a  related discipline.\n5+ years of relevant experience, including hands-on contribution and technical leadership in virtual prototype development, system modelling, verification, integration, or embedded software enablement.\nExpert in System-C/ TLM 2.0 on various development platform (Windows/Linux etc.)\nDevelopment of functional/cycle approximate models using SystemC and tools such as Synopsys Virtualizer ASTC VLAB etc. based on Visual Studio, g++ (for Linux)\nVerification of models using various methods, such as standalone SystemC based unit verification, co-simulation with RTL (System Verilog) and SW based system testing etc.\nGood grasp over the techniques and technologies to identify issues in customer environments using traces, logs etc.\nExposure to the scripting languages such as python.\nExpert knowledge of computer architecture, embedded CPU (ARM/RISC-V), real-time systems, Automotive communication platforms (Ethernet, CAN, FlexRay etc.)\nEmbedded system test development using C/C++ and automated execution/debugging.\nHands-on experience on embedded compilers such as GNU, Tasking etc. and debuggers such as PLS, Lauterbach T32 etc.\nGood team player in a multi-site/multi-cultural work environment\nDemonstrated strength of strong Communication skills, Innovation mindset, stakeholder management, risk management, quality, and process compliance, mentoring and coaching of peers etc.\nExposure to GenAI-assisted workflows for virtual prototype development using tools such as GitHub Copilot, Microsoft Copilot, ChatGPT, or enterprise LLM assistants for code scaffolding, test ideation, documentation,  debug support, and validation of generated outputs.\n\nContact:\n    Pooja.AnandaChowta@infineon.com, LinkedIn\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\nThis means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.\nPlease let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.\nClick here for more information about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Staff Engineer - ASIC Physical Design", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-06T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/42175536", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nMicron Technology’s vision is to transform how the world uses information to enrich life and our commitment to people, innovation, tenacity, collaboration, and customer focus allows us to fulfill our mission to be a global leader in memory and storage solutions. This means conducting business with integrity, accountability, and professionalism while supporting our global community.\n\nRole:\n\nThe team member will typically work on processors, controller architectures or ASICs for Enterprise SSD Group. Should be proficient in block level low power aware floorplanning, placement, clock tree synthesis, routing, RC extraction, STA timing closure, IR/EM analysis, DRC/LVS/ERC and tape out activities.\nRequirements\nMinimum of 8 years of hands-on physical design implementation experience along with APR flow development and PPA analysis\n\nSTA closure at block\n\nProficient in using AI\n\nExperience in Advanced process technology nodes (5nm/3nm preferred)\n\nExperience with Cadence layout tools (Innovus, Tempus, etc..)\n\nHands on work experience in Physical verification closure (DRC/LVS/Antenna) with Caliber tool\n\nExperience in closing all the IR issues within the block based on feedback\n\nShould be strong in fundamentals of digital electronics and microprocessors\n\nShould have very good analytical skills\n\nRequired soft skills – English language proficiency, Good collaboration and interpersonal skills. Good analytical and Problem-solving skills along with strong ownership, commitment and time management.\n\nBachelor’s or Masters with a relevant education is in the field of electronics and computer architecture\n\nPreferred Skills:\n·Strong verbal communication skills\n·Cadence PnR tools\n·Formal verification experience\n·Digital electronics and microprocessors experience\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Senior Customer Release Engineer", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-06", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Senior-Customer-Release-Engineer_R-101410", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nRole Overview:\n\nAs a Senior Customer Release Engineer, you will report to the Release Management team under Platform Execution and Operation. You will be assigned to execution programs and will be responsible for ensuring SiFive IP customer deliverables are integrated, validated, and delivered on time with high quality. Success will be measured based on on-time releases, defect escape rate, release quality, and automation improvements. This is a cross-functional coordination and technical debugging role, not a primary RTL or verification development role. You will work with architects, program managers, engineering, and sales support teams to release and deliver SiFive products on schedule.\n\nKey Responsibilities:\nOwn release readiness and delivery for customer IP drops. \n\nManage integration/configuration issues across Core and UnCore content. \n\nGenerate release collateral and perform quality checks. \n\nDrive schedule/risk tracking with PMs and engineering leads.\n\nCollaborate with sales and support teams to ensure customer requirements are met.\n\nTechnical Requirements\nMust-haves:\nStrong Python.\n\nExperience with release/build/productization workflows. \n\nFamiliarity with structured metadata/config formats such as JSON, YAML, and ideally IP-XACT. \n\nUnderstanding of hardware/IP delivery lifecycle.\n\nExperience with embedded programming in Assembly and C/C++, along with build tools such as CMake and Make.\n\nEducation & Experience\nRequired Qualifications:\nBE/ME/MTech/MS in ECE, EE, or Computer Science.\n\n4+ years of relevant experience.\n\nSolid understanding of SoC design and verification flows at a working level. \n\nStrong problem-solving/debugging skills. \n\nStrong communication and collaboration skills. \n\nExperience with Linux, Git, Jira, and Confluence. \n\nSelf-starter / learning agility. \n\nPreferred Qualifications:\nFPGA prototyping, emulation, and simulation depth. \n\nCPU architecture and embedded bring-up depth. \n\nVerilog/System Verilog.\n\nScala, Haskell .\n\nUVM, assertions, coverage, power estimation, Spy Glass.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Safety Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-07-06", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Safety-Engineer_R-10064424", "is_hardware": true, "platform": "workday", "jd_text": "Company Description\n\nNXP Semiconductors N.V. enables secure connections for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets.\n\nBusiness Unit Description\n\nNXP’s Functional Safety Competence Center empowers all business units to deliver functionally safe and standard compliant solutions, addressing current and emerging challenges in the automotive and industrial safety markets.\n\nJob Summary\n\nThis Safety Engineer position is part of the Functional Safety Competence Center and contributes to the development of safety-compliant semiconductor products. Key responsibilities are defining, analyzing, and validating safety concepts and architectures, including developing safety requirements and performing Safety Analyses. The Safety Engineer collaborates with implementation teams, systems, hardware, and software teams to deliver robust, certifiable solutions and to ensuring a Functional Safety compliant development process.\nCandidates with strong experience in Microcontroller and Microprocessor architecture and Safety product development are preferred. Exceptions may be made for candidates having no prior safety experience but have strong background in chip design architecture and are motivated to learn Functional Safety.\n\nRequired:\nBachelor’s degree in Electronics/Electrical/Computer Engineering or equivalent.\n5–8 years of experience in semiconductor product development with exposure to functional safety.\nStrong understanding of microcontroller and microprocessor architectures and their application in automotive or industrial safety domains.\nStrong understanding of IP and SoC level Safety mechanisms.\nUnderstanding safety standards (ISO 26262 or IEC 61508) and associated development lifecycles and work products.\nExperience with safety analysis techniques such as FTA, DFA, and FMEDA.\nAbility to collaborate effectively in cross-functional and global teams.\n\nPreferred:\nExperience in functional safety design and development within Tier 1 or Tier 2 automotive suppliers.\nBroad exposure to semiconductor product development (e.g., IP design, verification, DFT, physical implementation, tools, and methodologies).\nHands-on experience with safety analysis and modeling tools (e.g., Medini).\nExperience in safety audits, assessments, and certification activities.\n Familiarity with requirements management tools such as ELM7.\n\nResponsibilities:\nDefine and develop functional and technical safety concepts based on product architecture, technology, and intended functionality.\nContribute to the capture and management of requirements using appropriate requirements management tools.\nCollaborate with cross-functional teams to ensure consistent and effective implementation of safety concepts.\nPerform safety analyses at IP and product levels, including FTA, DFA, and FMEDA.\nSupport the definition and review of safety verification and validation strategies.\nContribute to safety audits, assessments, and internal reviews.\nSupport customers in the integration and application of NXP safety products, including tailored solutions where required.\n\nMore information about NXP in India...\n\n#LI-29f4", "jd_status": "stored"}, {"title": "SOC Verification - Sr Manager", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-07-06", "url": "https://careers.synopsys.com/job/bengaluru/soc-verification-sr-manager/44408/97411555904", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Title:SoC Verification Manager\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent over a decade in SoC verification, and somewhere along the way you realized that the hardest part of the job is not just catching bugs, it is building a team that catches them before they become expensive problems. You know what good verification looks like because you have written testbenches, debugged waveforms at 2 a.m., and closed coverage gaps on complex subsystems yourself. Now you lead teams through that same work, and you are good at it.\nYou understand customer engagements are not internal projects. Scope creeps, requirements shift, and timelines compress. You have learned to read between the lines when a customer says 'we need verification support' and figure out what they actually need, then translate that into a plan your team can execute without drama.\nManaging seven engineers across multiple projects means you spend your day context-switching between technical reviews, customer calls, and mentoring conversations. You do not micromanage, but you also do not disappear. You know when to step in and when to let someone work through a problem. At Synopsys, you will lead verification work that directly enables customers building chips for AI, automotive, aerospace, and high-performance computing. The work is real, the customers are demanding, and your team will depend on you to keep it all moving.\nWhat You'll Be Doing\nLead and manage a team of 7-8 SoC and subsystem verification engineers working on customer engagements across automotive, aerospace, defense, and high-performance computing domains\nWork directly with Synopsys customers to scope verification activities, define deliverables, and translate their technical challenges into actionable verification plans\nAssess project complexity and resource needs, then propose staffing and timeline plans that actually hold up under execution pressure\nMentor engineers daily on verification methodology, debug strategies, coverage closure, and customer communication, growing their technical depth for future assignments\nReview testbench code, verification plans, coverage reports, and waveform analysis to provide feedback that improves quality before deliverables go to the customer\nReport project status to senior management, flag risks early, and work through execution issues with peers and stakeholders across SSG, sales, and business unit application engineering teams\nDrive adoption of Synopsys verification tools including VCS, Verdi, and Synopsys VIP within customer projects, and collaborate with internal teams to refine methodology and improve efficiency\nThe Impact You Will Have\nYour team will deliver verification solutions that enable customers to tape out complex SoCs on schedule, directly affecting product launches in AI, automotive, and aerospace markets\nThe engineers you mentor will grow into technical leads and customer-facing verification experts, strengthening Synopsys capability to take on larger, more complex engagements\nYour project scoping and resource planning will determine whether customer engagements stay on track or slip, affecting both customer satisfaction and SSG revenue\nThe verification methodology improvements you drive will be reused across future projects, compounding efficiency gains across the entire Systems Solutions Group\nYour ability to translate customer needs into clear verification scope will shape how Synopsys tools and IP get deployed in real-world SoC projects\nThe quality standards you enforce will define what customers expect from Synopsys verification services, setting the bar for future engagements\nYour collaboration with sales and AE teams will help position SSG for new customer opportunities and expand the types of verification work Synopsys can take on\nWhat You'll Need\nBachelor's or Master's in Electronics Engineering or related field with 12+ years of hands-on experience in SoC verification\nDeep technical expertise across pre-silicon verification including UVM testbench development, coverage analysis, verification planning, and complex debug using waveform tools\nStrong working knowledge of industry-standard protocols such as PCIe, Ethernet, USB, DDR, and familiarity with processor, interconnect, or debug architectures\nProven hands-on experience with VCS, Verdi or similar waveform analyzers, and integration of third-party VIP including Synopsys VIP\nDemonstrated ability to lead verification teams through complex SoC, subsystem, or IP verification projects from planning through delivery\nExperience managing verification scope, timelines, and resources for customer-facing projects or service engagements is a strong plus\nSolid understanding of ASIC design flows, RTL design concepts, and how verification fits into the broader chip development lifecycle\nWho You Are\nYou can walk into a customer meeting, listen to a vague request for 'verification support,' and walk out with a concrete scope, timeline, and resource plan that your team can actually execute\nYou review a coverage report or testbench and immediately spot what is missing, not just technically but strategically, and you explain it in a way that helps the engineer see it too\nYou manage multiple projects without losing track of details, and your team knows you will catch issues before they escalate to the customer or senior management\nYou push back when a customer asks for something unrealistic or when internal stakeholders propose a plan that will not work, and you do it in a way that keeps the relationship intact\nYou communicate clearly with engineers, customers, and executives, adjusting your level of detail depending on who is in the room without oversimplifying or overcomplicating\nYou treat mentoring as part of the job, not an extra task, and engineers on your team get better at verification because you invest time in their growth\nThe Team You'll Be Part Of\nYou will join the System Solutions Group (SSG), a team that delivers end-to-end SoC design and verification services to Synopsys customers. SSG works on everything from subsystem blocks to full turnkey SoCs, serving customers that range from startups to industry leaders across high-performance computing, automotive, aerospace, and defense. Your verification team will collaborate closely with architects, RTL designers, and post-silicon teams, and you will work alongside peers in other SSG functions, sales, and Synopsys business unit application engineering teams to deliver customer engagements and refine internal methodology.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "IC Verification Engineer", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-07-06", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/IC-Verification-Engineer_R026427", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\nJob Description:\nArchitect and develop scalable and reusable Testbench environment using the framework of Verification Methodologies.\nDrive Test plans for all features for Block/Core/SOC and Write Functional coverage for these features.\nBuild pseudo-random tests to verify and get to full Functional coverage and bring the Verification to closure\nDebug Regression failures, analyze Functional Coverage gaps and improve tests to cover the gaps\nWork with other members of the team, guide/mentor junior team members\nLead the documentation of verification strategy including Test plans, Verification Environment, pseudo-random tests, etc. Lead reviews with design/architecture.\nDriver Verification quality and Efficiency improvements\n\nMandatory Requirements:\nBachelors degree in Electrical/Electronics/Equivalent with 12+ years of experience of Masters degree in Electrical/Electronics/Equivalent with 10+ years of experience\nDecade+ experience in developing complex Verification Environments, developing Test plans, Functional coverage and pseudo-random testing\nMust have gone through a full ASIC cycle right from Architecture development to Tapeout with full focus on Verification\nVery proficient in System Verilog and Verification Methodologies like UVM/VMM\nGood debug skills in analyzing regression failures and understanding of complex designs\nA good understanding of a complex protocol like PCI Express or other multi-layered protocol\nWork with the team and mentor junior engineers\nThese requirements are a plus:\nExperience in PCIe protocol\nScripting knowledge of Python or Perl\nComfort with Makefiles\nExperience with Verifying with other protocols like AXI\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "SoC Verification Technical Lead", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-07-06", "url": "https://careers.synopsys.com/job/bengaluru/soc-verification-technical-lead/44408/97411555808", "is_hardware": true, "platform": "talentbrew", "jd_text": "Alternate Job Title:SoC Verification Technical Lead\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in the trenches of SoC verification, where the difference between a chip that tapes out on schedule and one that slips six months often comes down to a verification plan you wrote in week two. You know that verification is not just about coverage numbers, it is about understanding what can actually break in silicon and making sure it does not.\nLeading a team does not mean delegating and disappearing. You are in the weaveform debugger alongside your engineers when a protocol violation shows up at 2am, and you can spot a gap in a testbench architecture during a design review without needing to see the code. You have learned to read a customer's SOC spec and immediately know where the risk lives, whether it is in the interconnect, the power domain crossings, or that custom accelerator block nobody wants to talk about yet.\nYou do not wait for perfect requirements. You ask the right questions, build a verification plan that actually maps to what can go wrong, and adjust as the design evolves. At Synopsys, you will work directly with customers building chips for AI, automotive, aerospace, and high-performance computing, and the verification strategies you build will determine whether their silicon works.\nWhat You'll Be Doing\nLead verification execution for customer SoC, subsystem, and IP projects, from verification planning through signoff, working directly with customer engineering teams to define scope and deliverables\nBuild and manage verification teams of 3-8 engineers, assigning tasks, reviewing testbenches and coverage reports, and mentoring engineers through complex debug scenarios\nDevelop verification plans that map customer requirements to testbench architecture, coverage goals, and resource allocation, then track execution and adjust as designs evolve\nIntegrate and deploy Synopsys VCS, Verdi, and third-party VIP for protocols like PCIe, Ethernet, USB, and DDR into customer verification environments\nDebug complex multi-protocol and multi-domain SoC issues using waveform analysis, coverage analysis, and cross-functional collaboration with design, architecture, and post-silicon teams\nIdentify project risks early, propose mitigation strategies, and communicate status and blockers to Synopsys management and customer stakeholders\nDrive methodology improvements across the SSG verification team, whether that is UVM reuse strategies, regression optimization, or new tool adoption\nThe Impact You Will Have\nYour verification plans and execution will directly determine whether customer chips tape out on schedule or slip quarters, affecting product launch timelines for AI accelerators, automotive SoCs, and aerospace systems\nThe engineers you mentor will grow into technical leads themselves, building verification capability across Synopsys that scales to future customer engagements\nYour early identification of design risks and verification gaps will prevent costly respins and post-silicon surprises for customers building chips in 5nm and below\nThe methodology improvements you drive will reduce verification cycle time and improve coverage quality across dozens of SSG projects annually\nYour direct customer engagement will shape how leading semiconductor companies adopt and deploy Synopsys EDA tools and IP in their verification flows\nThe testbench architectures and VIP integration strategies you build will become reusable assets for future projects, compressing ramp time for new customer engagements\nYour technical leadership will help Synopsys win and retain customer relationships in high-performance computing, automotive, and aerospace markets where verification complexity is a competitive differentiator\nWhat You'll Need\nBachelor's or Master's in Electronics Engineering, Computer Engineering, or related field with 5+ years of hands-on SoC, subsystem, or IP verification experience\nDeep technical expertise in UVM testbench development, coverage analysis, verification planning, and complex multi-domain debug\nProven experience leading verification teams through full project cycles, including resource planning, task assignment, and delivery against customer schedules\nStrong working knowledge of industry-standard protocols such as PCIe, Ethernet, USB, or DDR, and how they interact in real SoC architectures\nHands-on proficiency with Synopsys VCS, Verdi or equivalent waveform analysis tools, and integration of third-party VIP into verification environments\nExperience with ARM-based technologies including Coresight debug infrastructure, processor architecture, or AMBA protocols is a strong plus\nSolid understanding of ASIC design flows, RTL design concepts, and how verification fits into the broader chip development process\nWho You Are\nYou can walk into a customer meeting, hear a high-level SoC architecture description, and walk out with a verification plan that identifies the three highest-risk areas before anyone else in the room sees them\nWhen a regression fails at 3am and your team is stuck, you can look at the waveform, the coverage report, and the testbench code and know within 15 minutes whether it is a real bug or a testbench issue\nYou give feedback that makes engineers better, not just feedback that makes you feel heard, and your team knows the difference\nYou do not let a project drift. If a customer requirement is vague or a timeline is unrealistic, you say so early and propose a path forward that actually works\nYou can explain a complex protocol violation to a customer architect, a verification coverage gap to your manager, and a UVM sequence bug to a junior engineer, and all three conversations will be clear and useful\nYou stay current on verification methodology and tooling not because it is required but because you care about doing this work well, and you bring that knowledge back to your team\nThe Team You'll Be Part Of\nYou will join the System Solutions Group (SSG), a team that delivers end-to-end SoC design and verification services to Synopsys customers across automotive, high-performance computing, aerospace, and defense. SSG works on everything from individual IP blocks to full turnkey SoCs, partnering with customers ranging from startups to industry leaders and government agencies. Your verification work will span subsystems and full chips, and you will collaborate closely with Synopsys architecture, design, EDA application engineering, and sales teams to deploy tool and IP solutions that solve real customer problems.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior Design Engineer - Memory Subsystem", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-07-05", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Design-Engineer---Memory-Subsystem_JR2014081", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking passionate, highly motivated, and creative senior design engineers to be part of a team working on the design of state of the art memory sub-system components used in their industry-leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nIn this position, you will be encouraged to make architectural trade-offs based on features, performance requirements and system limitations, come up with micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. You will work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and backend teams to accomplish your tasks.\n\nWhat you’ll be doing:\nOwn micro-architecture and RTL development of design modules.\n\nMicro-architect features to meet performance, power and area requirements.\n\nWork with HW architects to define critical features.\n\nCollaborate with verification teams to verify the correctness of implemented features.\n\nInteract with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable.\n\nCo-operate with FPGA and S/W teams to prototype the design and ensure that S/W is tested.\n\nWork on post-silicon verification and debug.\n\nWhat we need to see:\nBS / MS or equivalent experience.\n\n4+ years of design experience.\n\nExperience in micro-architecture and RTL development of complex designs.\n\nExposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).\n\nDeep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping,, timing analysis, floor-planning, ECO, bring-up & lab debug.\n\nExpertise in Verilog.\n\nWays to stand out from the crowd:\nDesign experience in memory subsystem or network interconnect IP.\n\nGood debugging and problem solving skills.\n\nScripting knowledge (Python/Perl/shell).\n\nGood interpersonal skills and ability & desire to work as a part of a team.\n\nNVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Turing Design Verification Principal Manager", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-03T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446716913360", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff / Sr. Staff Engineer DV", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-03", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Staff---Sr-Staff-Engineer-DV_R-101408", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nKey Responsibilities:\nLead the verification and optimization of our diverse RISC-V Low Power Profiles, including UPF.\n\nDrive and achieve quality closure targets at both the CPU and block levels.\n\nCollaborate closely with microarchitecture and RTL design teams to optimize complex Power flows.\n\nProvide technical leadership and mentorship to junior team members to foster team growth and enrichment.\n\nActively participate in the test planning and execution phases for new architecture and design features.\n\nRequirements\n7+ Years of experience in low power or power aware or power management\n\nExperience with hands on UVM Test Bench development is must\n\nExperience in core uArch is highly desirable.\n\nExperience in leading effort and driving multiple projects\n\nExperience with power simulation on vcs and upf.\n\nExperience with script writing in Python, Perl or Tcl.\n\nExperience with power impact at architecture, logic design, and circuit levels.\n\nExcellent problem solving skill and ability to work in a dynamic and diverse environment.\n\nQualification:\nA minimum of bachelor’s or master’s Degree, or equivalent in Electrical & Electronic Engineering or Electrical & Communication Engineering or VLSI with consistently good academics\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Staff Engineer, Physical Design - Cores", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-07-03", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Staff-Engineer--Physical-Design---Cores_R-101165", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nAbout the Role -- \n\nAt SiFive, we’re redefining the compute landscape with our industry-leading RISC-V compute platforms. As a Staff Physical Design Engineer (CPU Cores), you will own the physical implementation of critical, high-performance processor core blocks from RTL to GDSII. You will deliver high-frequency, power-efficient CPU designs on advanced and legacy process nodes.\nWhile your primary focus will be in physical design, we are looking for engineers capable of operating across design-abstraction layers. You will collaborate across architecture, RTL, and power teams. Leveraging a deep understanding of the processor pipeline and design goals, you will be instrumental in co-designing PPA (Power, Performance, Area) optimizations. This work directly enhances the frequency, area, and power-efficiency of our core IP.\n\nResponsibilities - What you’ll do\nOwn Core Implementation: Drive the physical design implementation for high-frequency CPU core blocks and execution pipelines, managing synthesis, place & route, and signoff.\n\nEngage in Cross-Abstraction-Layer Co-Design: Go beyond standard implementation by actively collaborating with Architecture/RTL/Power for PPA co-optimisation. Understand the CPU microarchitecture to identify logic-depth bottlenecks early and suggest RTL pipelining strategies or structural changes.\n\nSolve Core-Specific Challenges: Tackle physical bottlenecks unique to CPU cores, including timing closure, datapath placement, routing congestion, complex clock tree synthesis (CTS) for high-speed pipelines, and rigorous dynamic power optimization.\n\nAggressive PPA Optimization: Optimize block-level implementation for aggressive Power, Performance, and Area (PPA) goals, managing complex PPA trade-offs to meet target frequencies across various product lines.\n\nCollaborate Cross-Functionally: Work closely with CPU architecture, RTL design, and Power teams to close design requirements and ensure efficient physical realization of the instruction set architecture.\n\nEnhance Methodology: Support and improve physical design flows, automation scripts, and methodologies tailored specifically for high-frequency, complex core implementation.\n\nRequirements - What you’ll bring\n7+ years of hands-on experience in physical design implementation with a proven track record of block-level tape-outs involving high-speed digital logic like CPUs.\n\nCPU/Datapath Expertise: Specific experience implementing complex control logic, execution units (ALUs, FPUs), or custom data-paths. Familiarity with the physical challenges of pushing high-frequency design limits.\n\nCross-Abstraction Awareness: A solid understanding of processor microarchitecture (e.g., instruction pre-fetch, execution units, data forwarding paths). You should be comfortable reading RTL to understand the design intent and collaborate effectively with front-end teams.\n\nStrong Problem Solving: Proven ability to optimize for aggressive PPA targets using industry-standard physical design techniques, accompanied by a detail-oriented mindset and clear communication of results.\n\nTool Proficiency: Hands-on knowledge of RTL to GDS implementation with Synopsys and/or Cadence implementation and sign-off tools.\n\nEducation: Bachelor’s or Master’s in Electrical or Computer Engineering.\n\nWhy join us?\nBe part of the RISC-V movement and help define the future of computing architecture.\n\nWork on industry-leading IP adopted by top customers and shipped in high volumes worldwide.\n\nCollaborate with world-class engineers in a supportive, fast-paced, learning environment.\n\nEnjoy a culture that values innovation, ownership, and technical excellence.\n\nOur large IP portfolio offers opportunities to engineer solutions across multiple IPs and product families over time.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Analog Circuit Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-07-03", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Analog-Circuit-Design-Engineer_JR0283533", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact:\nAt Intel, Analog Circuit Design Engineers are at the forefront of innovation, shaping the future of analog and mixed-signal IPs. This critical role involves designing, developing, and optimizing high-speed analog circuits in advanced process nodes, contributing directly to Intel's industry-leading products and technologies. As part of our high-speed IO design team, you will play a pivotal role in creating next-generation memory interface PHYs, driving power, performance, and functionality improvements in cutting-edge circuits. Your expertise will directly impact Intel's ability to deliver high-quality solutions to meet the ever-evolving demands of technology.\n\nKey Responsibilities:\n- Design, develop, and build analog circuits for advanced process nodes, enabling high-performance and robust functionality.\n- Perform circuit design, validation, extraction of chip parameters, and simulation of analog behavior models.\n- Optimize circuits for power efficiency, performance, area, timing, and yield goals.\n- Create test plans to verify designs against block microarchitecture specifications, evaluating test results for design validation.\n- Collaborate with cross-functional teams to define design specifications, collect feedback, and resolve design issues.\n- Conduct layout reviews and ensure optimal placement and routing in collaboration with architecture and layout teams.\n- Contribute to post-silicon debug and validation efforts to support high-volume manufacturing.\n- Continuously refine design methodologies and processes to improve turnaround time and design quality.\n\nQualifications:\nMinimum Qualifications:\n- Bachelor's degree in Electrical Engineering or an equivalent specialized field, or equivalent experience as required for the role.\n- 10+ years with Master's degree, or 4+ years with PhD in analog circuit design.\n- Proficiency with industry-standard tools such as Cadence Virtuoso, Spectre, PrimeSim, HSPICE, ADE, and Custom Compiler.\n- Expertise in designing high-speed analog circuits such as TX/RX blocks, PLLs, DLLs, SerDes, and voltage regulators.\n- Strong fundamentals in CMOS design, circuit simulation, and high-speed analog design concepts.\n- Familiarity with DRC, LVS, and post-layout extraction tools.\n\nPreferred Qualifications:\n- Experience in post-silicon debug, electrical validation, and correlating measurements to simulations.\n- Knowledge of scripting languages such as TCL, Perl, Python, or C for design automation tasks.\n- Familiarity with modeling and simulation of high-speed interface interconnects and channels.\n- Strong problem-solving, analytical skills, and ability to work in a fast-paced collaborative team environment.\n- Demonstrated leadership experience, ability to mentor junior team members, and drive innovation in circuit design.\n\nIf you are passionate about creating impactful designs, driving technological innovation, and collaborating with a talented team, we invite you to apply and take the next step in your career with Intel.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nBusiness group:\nThe Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Principal Engineer Design", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-07-02T09:00:32+00:00", "url": "https://jobs.infineon.com/careers/job/563808971417840", "is_hardware": true, "platform": "eightfold", "jd_text": "Your Role\n\nKey responsibilities in your new role\n\nDesign Lead for Power Management ICs and POL ICs\nWork closely with Concept Engineering, Applications, Marketing, and Project Managers to define feature set, chip architecture, resourcing, schedule and cost.\nMentor less experienced designers in the art of mixed-signal design, highlighting good design practices\nSupport / plan DFT strategy and DFT design implementation.\nSupport production test development and ramp to production.\nSpecification and transistor-level design of low-power /high-performance analog circuits and power management modules meeting performance, silicon area, power and timescale constraints with CMOS/BCD technology.\nPerform all aspects of IC analog/mixed signal design from definition to production.\nPotential areas of design include Buck converter design, precision analog blocks, as well as higher voltage integrated drivers, switching FETs, sense and protection circuitry.\n\nYour Profile\n\nQualifications and skills to help you succeed\n\nMS in Electrical Engineering or related field and minimum of 5 years of IC design experience.\nStrong foundation in analog & mixed signal design\nHave experience as a design team lead and manager\nAttention to detail during all aspects of architecture definition, circuit design, debug and documentation.\nExceptional interpersonal, time management and communication skills.\nDesign experience with Power Management ICs and LDMOS/BCD process technologies and PDKs\nExperience in different modulator architectures.\nProficiency with the complete suite of Cadence tools for mixed signal design\nSolid knowledge of EDA design tools and Cadence design environment and hands-on experience with Virtuoso Custom IC Environment.\nGood communication and teamwork skills.\nStrong hand-on experiences in lab for silicon evaluation and validation.\nPower electronics knowledge is a big plus.\n\nContact:\n    VidhiAshok.Thakkar@infineon.com\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\nThis means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.\nPlease let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.\nClick here for more information about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Sr Lead Engineer - DFT", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-02T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718716777", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    5+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Infra Power Design Verification Staff Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-02T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719462963", "is_hardware": true, "platform": "eightfold", "jd_text": "As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\nKey Responsibilities:\nDevelop and maintain UVM-based verification environments for high-speed interconnect protocols (PCIe, CXL, AXI).\n\nCreate and execute verification plans for high-speed interconnect protocols including PCIe, CXL, AXI, and CHI.\n\nPerform block-level and top-level verification, including functional coverage, assertion-based verification, and regression testing.\n\nCollaborate with RTL designers, architects, and validation teams to ensure design correctness and coverage closure.\n\nWork closely with design and architecture teams to understand specifications and derive verification strategies.\n\nUse third-party VIPs (e.g., Synopsys, Mentor) for protocol compliance and simulation.\n\nImplement and enhance scoreboards, agents, monitors, and sequences.\n\nIntegrate and validate SMMU and Coresight components in Subsystem environments.\n\nDrive verification closure through coverage convergence and assertion-based verification.\n\nContribute to performance, power, and cost optimization considerations during verification.\n\nMentor junior engineers and contribute to verification methodology improvements.\n\nDebug failures at RTL and gate-level simulations.\n\nRequired Skills:\nStrong proficiency in System Verilog, UVM, and verification methodologies.\n\nDeep understanding of PCIe Gen3/Gen4/Gen5/Gen6, CXL 1.1/2.0/3.0, AXI/CHI protocols, and SMMU/Coresight architecture.\n\nFamiliarity with Synopsys/Mentor VIPs for PCIe/CXL and AMBA protocols.\n\nExpertise in assertion-based verification (SVA) and coverage-driven testing.\n\nProficiency in Perl/Python/Tcl scripting for automation.\n\nKnowledge of power-aware verification (UPF), formal verification, and performance/power optimization.\n\nExperience with coverage-driven verification and random constraint-based testing.\n\nExperience with scripting languages like Python, Perl, or Tcl.\n\nPreferred Qualifications:\nBachelor’s/Master’s/Ph.D. in Electrical, Electronics, or Computer Engineering.\n\n8–12+ years of ASIC/Subsystem/SoC verification experience.\n\nExperience with PCIe, USB, Ethernet, or other peripheral protocols is a plus.\n\nExposure to post-silicon validation and lab bring-up is desirable.", "jd_status": "stored"}, {"title": "Sr Lead Engineer - DFT", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-02T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718854270", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    5+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Principal Engineer, DFT", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-02T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446717629071", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Description\n\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n\nQualcomm's Global CAD Organization is seeking a highly experienced and innovative technical leader to drive the development and deployment of next-generation DFT, ATPG, and MBIST methodologies for industry-leading SoCs built on advanced semiconductor technology nodes. In this strategic role, you will work within a highly collaborative global environment, partnering with SoC Design, DFT, Product Engineering, Test Engineering, Diagnostics teams, and leading EDA vendors to define and deliver scalable, high-quality Design-for-Test solutions that enable first-pass silicon success and manufacturing excellence.\n\nThis position offers a unique opportunity to influence company-wide DFT methodology direction, drive technology innovation, and contribute to the development of cutting-edge mobile, AI, automotive, and compute products.\n\nKey Responsibilities\nLead the architecture, development, integration, and deployment of advanced DFT, ATPG, MBIST methodologies and flows across the complete product lifecycle, from RTL design through post-silicon validation and production test.\nCollaborate closely with global DFT teams and EDA partners to develop scalable and efficient solutions that improve productivity, quality, and test coverage.\nEvaluate emerging DFT technologies, tools, and methodologies through proof-of-concepts, methodology studies, design-of-experiments (DoE), and joint development initiatives with EDA vendors.\nDrive methodology enhancements, automation frameworks focused on improve design productivity, minimizing test cost and test time, and maximizing defect coverage and silicon quality.\nDefine and execute the DFT methodology roadmap to address future product requirements, technology scaling challenges, and evolving test strategies.\nProvide technical leadership, mentorship, and guidance to engineering teams while influencing cross-functional stakeholders and driving alignment across global organizations.\n\nQualifications\nBachelor's, Master's, or higher degrees in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.\n12–15 years of industry experience in VLSI CAD/EDA methodology development with significant focus on DFT, ATPG, and test optimization methodologies.\n\nRequired Technical Skills\nDeep expertise in DFT methodologies, including:Scan insertion and optimization\nATPG development and test compression\nMemory BIST (MBIST)\nFault modeling and coverage analysis\n\nStrong hands-on experience with industry-standard DFT, ATPG, MBIST tools such as: Siemens   Tessent , Synopsys TestMAX, SMS\nProven track record of driving methodology innovation and delivering measurable improvements in test quality, productivity, and execution efficiency.\nStrong programming and automation skills using TCL, Python\nSolid understanding of SoC DFT architecture, Product test engineering practices, ATE environments, silicon bring-up, and manufacturing test flows.\nExperience working with software development best practices including version control, configuration management, release processes, quality assurance, and support infrastructure.\nDemonstrated ability to lead complex technical projects, influence cross-functional teams, and drive successful execution in a global engineering environment.\nExposure to development of AI/ML-based solutions, and intelligent automation to enhance DFT implementation workflows.\n\nPreferred Leadership Attributes\nStrong technical leadership with the ability to define vision, influence strategy, and drive execution.\nExcellent communication, presentation, and stakeholder management skills.\nAbility to collaborate effectively across geographically distributed teams and diverse functional organizations.\nSelf-driven, highly organized professional with strong analytical problem-solving capabilities.\nPassion for technology innovation and continuous improvement.\n\nKeywords\nDFT, ATPG, Scan Insertion, Scan Compression, MBIST, Tessent, TestMAX, TetraMAX, VLSI Test, DFT CAD Methodology, SoC DFT, DFT EDA Tools, Semiconductor Test and Diagnostic\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU Verification Infrastructure Tools Architect", "company": "NVIDIA", "location": "India, Hyderabad", "date_posted": "2026-07-02", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Hyderabad/CPU-Verification-Infrastructure-Tools-Architect_JR2020428", "is_hardware": true, "platform": "workday", "jd_text": "We are looking for a Hardware and Software Developer. The role is multifaceted - SoCV testbench Infrastructure, Bare-metal boot, Silicon Bringup Tools and CPU/SOC/GPU test frameworks. It involves a detailed understanding of the nVidia CPU, GPU, SOC system and boot architectures. The tools and technologies are complex and involve code that coordinates many IPs in the overall SOC. A key part of NVIDIA's strength is our development tools and environments that enable our incredible pace of delivering new technology to the market. We are looking for a creative and hardworking engineer who is passionate about joining a dynamic & agile SoCV/Emulation Infrastructure and test-frameworks team.\n\nWhat you will be doing:\nThe work includes building tools, infrastructure, and test frameworks used in RTL-simulations, c-simulations, Emulation, FPGA, and on Silicon.\n\nYou will understand Tegra system architecture, with a focus on all IPs in the SOC that are involved in boot and security features.\n\nThe tools that you build give Design and Verification teams the ability to access registers/memory/DMA engines and other features in their unit. The tools also enable test re-use across multiple platforms (RTL, models, Emulation, and Silicon). The gamut of tools is wide and you also develop features used for Silicon bring up (example: FUSE, ATE, Security, Flash/DMA, Board I2Cs, USB debug devices among others). We strive for the highest quality of test frameworks and tools that we deliver from this team.\n\nYou would assess and build C-model or RTL-simulation capability that allows us to simulate the features before Silicon arrival in a pre-silicon environment.\n\nWhat we need to see:\nBS or MS in Computer Science or Electronics Engineering or equivalent experience with 5+ years of experience\n\nStrong programmer who is proficient with C, C++, Python.\n\nUnderstanding of SOC and System Architecture.\n\nUnderstanding of How the SOC Devices like DMA, interrupt-engines, CPU, boot-devices, MMU/IOMMU function.\n\nOperating System and Device-Driver concepts and ability to write no-OS test frameworks - i.e tests that run directly on the bare-metal SOC.\n\nA good programmer takes pride in building scalable and maintainable software.\n\nUnderstanding Hardware and/or Software development life cycle.\n\nWay to stand out from the crowd:\nPrevious experience handling Silicon Bringup and in enabling Emulation/FPGA related test frameworks.\n\nExposure to Testbench architectures (C++ testbenches, SV/UVM based testbenches).\n\nVerilog and System Verilog coding skills are a plus.\n\nWith competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us and, due to unprecedented growth, our elite engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you! We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.", "jd_status": "stored"}, {"title": "Sr. Staff Applications Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-07-02", "url": "https://careers.synopsys.com/job/bengaluru/sr-staff-applications-engineer/44408/100128500096", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nAre you passionate about solving the toughest timing challenges at advanced nodes? Join Synopsys’ Signoff Static Timing Analysis (STA) team and work with industry-leading tools like PrimeTime, enabling the world’s most advanced semiconductor designs.\n \nIn this customer-facing role, you will act as a technical expert in timing signoff, collaborating with semiconductor companies to support Synopsys industry-leading PrimeTime signoff solutions for advanced node designs. You will work closely with customers, R&D, and product engineering teams to address complex timing challenges and drive methodology adoption.\n\nThis is a high-visibility, customer-facing role requiring strong technical depth, execution ownership, and cross-functional collaboration with Product and R&D teams. We are looking to hire in Bangalore only for this role.\n\nWhat You'll Be Doing\nWork directly with leading semiconductor companies to resolve complex timing closure and signoff challenges on advanced node designs, often under tight tapeout schedules\nDebug critical timing issues including setup and hold violations, clock domain crossings, SI-induced timing failures, and variation-related signoff problems using PrimeTime\nGuide customers through MMMC analysis, OCV/AOCV/POCV methodologies, and SI-aware timing flows tailored to 5nm and below process nodes\nCollaborate with R&D and product engineering teams to reproduce customer issues, identify root causes, and drive tool enhancements or methodology improvements\nDevelop reference flows, automation scripts in Tcl and Python, and best practice documentation that customers can adopt and adapt to their specific design environments\nDeliver technical training sessions, workshops, and live demos to customer design teams, covering PrimeTime capabilities, signoff methodologies, and advanced node considerations\nDrive adoption of the latest PrimeTime technologies and signoff features by demonstrating value, building proof-of-concept flows, and supporting production deployment\n\nThe Impact You Will Have\nEnable successful tapeouts for cutting-edge semiconductor designs by solving timing signoff challenges that would otherwise delay or block production schedules\nImprove customer productivity and signoff quality by delivering automation scripts and methodology improvements that reduce manual effort and catch issues earlier\nInfluence PrimeTime product direction by channeling real customer pain points, design challenges, and feature requests directly to the R&D team\nBuild long-term technical partnerships with key accounts, becoming the trusted advisor they turn to when timing signoff gets complicated\nAccelerate adoption of advanced PrimeTime features across the customer base, translating new capabilities into production value faster than competitors can respond\nReduce customer support escalations by proactively addressing methodology gaps, training design teams, and building reusable solutions\nShape industry best practices for timing signoff at advanced nodes by documenting what actually works in production, not just what works in theory\n\nWhat You'll Need\nBachelor's degree in Electronics and Communication Engineering, plus Master's degree in VLSI, Embedded Systems, or Communication Systems\nStrong hands-on experience with Synopsys PrimeTime for static timing analysis and signoff, including real production design exposure\nDeep understanding of timing constraints using SDC, MMMC analysis frameworks, and variation-aware methodologies including OCV, AOCV, and POCV\nProven ability to debug complex timing issues such as setup and hold violations, clocking problems, signal integrity effects, and variability-driven failures\nProficiency in Tcl scripting for tool automation and flow development, Python or Perl scripting experience is a strong plus\nExperience with advanced node designs at 5nm and below, including the unique timing challenges and signoff requirements at those geometries\nExcellent communication skills and demonstrated ability to engage directly with customers, understand their technical challenges, and deliver solutions that work in their environment\n\nWho You Are\nYou can walk into a customer meeting, listen to a timing problem described in five different ways by five different engineers, and identify the actual root cause before the meeting ends\nYou are comfortable saying 'I don't know, but I will find out' when faced with an unfamiliar issue, and you follow through quickly with a real answer, not a deflection\nYou write automation scripts that other engineers actually want to use because they solve real problems and do not require a PhD to understand\nYou know when to escalate an issue to R&D and when to solve it with a methodology change, and you can explain that tradeoff clearly to both the customer and the product team\nYou treat customer tapeout schedules as your own deadlines, and you organize your work to unblock them even when it means jumping between three different accounts in one day\nYou can explain why a particular POCV derate is causing a timing violation to a senior design engineer without losing the technical nuance, and then explain the business impact to their manager in two sentences\n\nThe Team You'll Be Part Of\nLeading the key customers and providing technical assistance on the Synopsys Signoff tools for Key customers in India.\n\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Program Management Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-07-02", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009340", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n Texas Instruments (TI) is looking for an energetic, service minded leader, who enjoys helping others to succeed by providing team members and clients with motivation and support in a positive and professional work environment as a Program Management Engineer. We are seeking a highly motivated individual who will challenge teammates to achieve flawless execution goals, while maintaining strong working relationships. Success in this role is measured by the ability to grow the number of new products and drive the forecasted return on investment.\n\nResponsibilities include:\n\nLead a cross functional team on the execution of releasing new products and ensuring successful return on investment for every development; the team consists of Design, Marketing, Systems& Applications, Validation, Product& Test Engineering, Firmware/Software Engineering, Manufacturing, Field, and Quality\n\nWork with wafer fabrication, assembly& test sites to guarantee schedule, cost and quality\n\nPlan the project using MS Project from Assess Opportunity Phase to Release to Market and is responsible to make sure the project comes in on budget\n\nProvide clear direction to both, team and external support organizations like device fabrication and assembly and test sites\n\nDrive and motivate all team members critical to the flawless execution of each product and project\n\nProvide weekly and monthly updates to senior management on status of projects, explaining the issues facing a project\n\nInteract with customers in support of project status, key milestones, and deliveries. This includes samples deliveries, special work requests, wafer lot starts and reliability tests\n\nPerform product reliability and characterization of integrated circuits to ensure they meet the product requirement specifications and manufacturing requirements\n\nWork with failure analysis (FA) to determine root cause of any reliability and qualification failures\n\nMaintain thorough and up-to-date project schedules with all related milestones\n\nDevelop and implement Qualification plans\n\nCommunicate weekly to management on status of each project\n\nEffectively coordinate material logistics and shipment/assembly/test prioritization\n\nMaintain Galileo system per new product development guidelines\n\nSuccess will be measured by the ability to grow the number of new products and drive the forecasted return on investment.\n\nQualifications\nMinimum requirements:\n\nBachelor in Electrical Engineering, Mechanical Engineering or related engineering degree\n\n5 years of experience with project engineering/management experience on highly complex products/projects\n\nProven leadership capabilities in leading multifaceted global organizations\n\nSuccessful proven track record in indirect management and influence\n\nPreferred qualifications:\n\nAbility to manage multiple projects simultaneously, and set realistic plans based on required tasks with available resources\n\nAbility to effectively coordinate and lead global development teams on projects that include design, silicon fabrications, production test development, qualification and production ramp; Programs will be driven out of multiple global locations\n\nAbility to provide clear direction to both internal teams and external support organizations like device fabrication and assembly sites\n\nKnowledge of device packaging and wafer fabrication process\n\nKnowledge of reliability requirements and tri-temp characterization methodology using statistical analysis\n\nAbility to work in a team environment and understand cross-functional team dynamics\n\nAbility to work with global customers to align project schedules with customers' key milestones\n\nDemonstrated strong analytical and problem solving skills\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nStrong time management skills that enable on-time project delivery\n\nDemonstrated ability to build strong, influential relationships\n\nAbility to work effectively in a fast-paced and rapidly changing environment\n\nAbility to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Verification Engineer - Networking IPs", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-07-02", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Verification-Engineer---Networking-IPs_JR2020605", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people.\nToday, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.\nWe are seeking enthusiastic, driven, and imaginative individuals to join our networking group. As the owner of networking IP's unit and cluster level verification, you will contribute to projects crafting the future of our datacenter chips and systems. You will gain direct experience of chip working with high-performance queuing and scheduling sub-systems.\n \nWhat you'll be doing:\nYou will develop verification components and API's for unit and cluster level test benches. These will verify queuing and scheduling algorithms and designs.\nDuring the course of a project, you will drive the following aspects of verification for your unit:\nArchitect the testbenches and craft verification environment using Specman language and methodology\n\nDefine test plans, tests and verification infrastructure for clusters and systems\n\nBuild efficient and reusable bus functional models, monitors, checkers, and scoreboards\n\nImplement functional coverage and own unit/cluster level verification closure\n\nWork with architects, designers, FPGA, and post-silicon teams to ensure that your unit is robust\n\nWhat we need to see:\nBTech or MTech in ECE, EE, CSE, or an equivalent degree is required. Candidates should have over 3 years of experience in verification closure of complex units, sub-systems, or SOC level verification.\n\nProven experience in networking specific Datapath and Switching verification IP's.\n\nExperience in the latest verification methodologies like SV and UVM would be beneficial\n\nGood debugging and analytical skills with exposure to industry-standard verification tools for simulation and debug\n\nGood interpersonal skills, ability to work as a diligent teammate, and excellent communication skills to collaborate with cross-cultural global teams and work in a matrix organization\n\nWays to stand out from the crowd:\nExposure on using AI (like Claude or Cursor) extensively for code development would be a big plus\n\nA mentality towards constant improvement and looking to build a multiplier effect through your work and automation\n\nExposure to Formal verification would be excellent\n\nWe have some of the most experienced and dedicated people in the world working at NVIDIA. If you're creative and independent, with a genuine passion for adopting newest technology, we want to hear from you. Join us and be part of something outstanding!\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.\nRecognized as one of the most sought-after employers in the technology sector, NVIDIA provides highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Principal Architecture Engineer", "company": "Lattice", "location": "Pune, India", "date_posted": "2026-07-02", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Pune-India/Principal-Architecture-Engineer_R-100862-1", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nThe FPGA Architecture Team at Lattice Semiconductor is seeking a Principal FPGA Architect to build and lead a team of FPGA architecture evaluation experts focused on shaping the next generation of FPGA architectures and tools. This role sits at the intersection of RTL design, FPGA architecture, and design methodology, with a strong emphasis on hands-on FPGA implementation and analysis rather than abstract modeling alone.\nThe successful candidate will define and drive a methodology for implementing representative and forward-looking FPGA workloads on existing and future FPGA architectures, analyzing results, and providing actionable architectural feedback. The goal is to influence FPGA hardware features, microarchitecture, and EDA tools to deliver optimal power, performance, area, and usability for real customer designs.\nThis role includes technical leadership and team building, close collaboration with FPGA architects, RTL designers, EDA/tool teams, and silicon validation, and ownership of architectural insights from early exploration through silicon correlation.\nResponsibilities:\nBuild, mentor, and lead a team of FPGA architecture evaluation and analysis engineers.\nDefine and execute a strategy for RTL-based FPGA architecture evaluation, using realistic workloads and design patterns.\nImplement, synthesize, place-and-route, and analyze complex FPGA designs across multiple architectures and process generations.\nEvaluate architectural tradeoffs involving: Logic, routing, memory, DSP, and interconnect structures\nTiming closure, routability, utilization, and power efficiency\nTool behavior, compile time, and QoR sensitivity\n\nProvide clear, data-driven feedback to FPGA architecture teams to guide: Hardware feature definition and optimization\nMicroarchitectural changes\nTool and flow improvements\n\nCorrelate architectural hypotheses with RTL results, post-P&R data, and silicon measurements where available.\nDrive design-space exploration using RTL and FPGA tools rather than purely abstract models.\nPartner with EDA, software, and silicon teams to ensure architectural intent translates into real-world results.\nRepresent the evaluation team in architectural reviews and cross-functional forums.\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Mixed Signal CAD Engineer", "company": "onsemi", "location": "Bucharest, RO", "date_posted": "2026-07-02", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505798", "is_hardware": true, "platform": "oracle", "jd_text": "As part of the Corporate R&D Design systems technology department we are responsible for the evaluation, acquisition, development, integration and support of design tools and methodologies towards the world wide BU development teams. We are looking for a senior mixed signal cad engineer and are offering a position in our RnD center in Bucharest or Bangalore.", "jd_status": "source_unavailable"}, {"title": "FPGA Prototyping/ Emulation Staff Application Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-07-02", "url": "https://careers.synopsys.com/job/bengaluru/fpga-prototyping-emulation-staff-application-engineer/44408/97236810816", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in prototyping & emulation platforms , verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\n \nYou Are:\nYou are an expert in FPGA‑based prototyping and emulation with a deep understanding of FPGA architectures and hands‑on experience with industry‑leading platforms such as HAPS and ZeBu. You bring strong FPGA debugging skills and a practical, execution‑focused approach to solving complex system challenges. Your collaborative mindset and proactive attitude enable you to drive results in fast‑moving environments. You excel at working closely with R&D, Product Validation, Product Engineering teams and Customers to evaluate, deploy, and enhance cutting‑edge prototyping and emulation technologies. Your passion for innovation and continuous improvement ensures the delivery of high‑quality, optimized solutions that accelerate product development.\n \n \nWhat You’ll Be Doing:\n \nValidate advanced prototyping and emulation features using large, complex customer SoC designs, ensuring high performance, scalability, and functionality across HAPS and ZeBu-based systems.\nAnalyze complex design and product challenges, develop innovative solutions, and provide strategic recommendations that enhance customer productivity, debug efficiency, and overall satisfaction\nProvide technical leadership and domain expertise to define and refine requirements for HAPS and ZeBu product flows, driving accurate implementation and continuous quality improvements.\nCollaborate cross‑functionally with R&D, Applications Engineering, and global teams to deliver seamless customer experiences and accelerate successful prototyping deployments.\n \nThe Impact You Will Have:\nStrengthen cross‑functional collaboration to elevate product quality and enhance end‑customer satisfaction.\nDrive innovation by defining forward‑looking requirements for product development.\nStandardize and optimize workflows to improve efficiency, promote reuse, and ensure compliance with organizational and industry best practices.\n \nWhat You’ll Need:\n \n5+ years of hands-on experience in FPGA-based Prototyping, FPGA design, and Hardware debug. \nStrong proficiency in Verilog, System Verilog, RTL design, Synthesis, Simulation, and working with latest FPGA architectures.\nPractical experience with scripting languages such as Python and Tcl, along with familiarity in design automation flows and productivity tools.\nExceptional analytical and problem‑solving skills, with a proven ability to deliver innovative and scalable solutions to challenging technical problems.\nKnowledge of ARM® bus architectures, display controllers/interfaces, and industry‑standard protocols such as USB, PCIe, SATA, DDR etc. (preferred).\n \nWho You Are:\nYou are a strong analytical thinker with exceptional problem‑solving skills. A natural collaborator, you communicate with clarity and influence, enabling effective teamwork across diverse technical and organizational groups. You thrive in dynamic, fast‑changing environments and bring a proactive, solution‑oriented mindset to every challenge. Your passion for innovation and continuous improvement drives you to push boundaries and elevate standards. Adaptable and resourceful, you embrace new ideas, learn quickly, and consistently deliver outstanding results. Your ability to work seamlessly with cross‑functional teams makes you a trusted partner and an asset to any organization.\n \nThe Team You’ll Be a Part Of:\nYou will be part of a dynamic and innovative team focused on driving the next generation of prototyping and emulation solutions. Our team thrives on collaboration, continuous learning, and pushing the boundaries of technology. We work closely with cross-functional teams to deliver high-quality solutions that meet the evolving needs of our customers.\n \nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\n\n#TPG", "jd_status": "stored"}, {"title": "Analog Circuit Design Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-07-02", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Analog-Circuit-Design-Engineer_JR0283532", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact:\nAt Intel, Analog Circuit Design Engineers are at the forefront of innovation, shaping the future of analog and mixed-signal IPs. This critical role involves designing, developing, and optimizing high-speed analog circuits in advanced process nodes, contributing directly to Intel's industry-leading products and technologies. As part of our high-speed IO design team, you will play a pivotal role in creating next-generation memory interface PHYs, driving power, performance, and functionality improvements in cutting-edge circuits. Your expertise will directly impact Intel's ability to deliver high-quality solutions to meet the ever-evolving demands of technology.\n\nKey Responsibilities:\n- Design, develop, and build analog circuits for advanced process nodes, enabling high-performance and robust functionality.\n- Perform circuit design, validation, extraction of chip parameters, and simulation of analog behavior models.\n- Optimize circuits for power efficiency, performance, area, timing, and yield goals.\n- Create test plans to verify designs against block microarchitecture specifications, evaluating test results for design validation.\n- Collaborate with cross-functional teams to define design specifications, collect feedback, and resolve design issues.\n- Conduct layout reviews and ensure optimal placement and routing in collaboration with architecture and layout teams.\n- Contribute to post-silicon debug and validation efforts to support high-volume manufacturing.\n- Continuously refine design methodologies and processes to improve turnaround time and design quality.\n\nQualifications:\nMinimum Qualifications:\n- Bachelor's degree in Electrical Engineering or an equivalent specialized field, or equivalent experience as required for the role.\n- 13+ years with Master's degree, or 6+ years with PhD in analog circuit design.\n- Proficiency with industry-standard tools such as Cadence Virtuoso, Spectre, PrimeSim, HSPICE, ADE, and Custom Compiler.\n- Expertise in designing high-speed analog circuits such as TX/RX blocks, PLLs, DLLs, SerDes, and voltage regulators.\n- Strong fundamentals in CMOS design, circuit simulation, and high-speed analog design concepts.\n- Familiarity with DRC, LVS, and post-layout extraction tools.\n\nPreferred Qualifications:\n- Experience in post-silicon debug, electrical validation, and correlating measurements to simulations.\n- Knowledge of scripting languages such as TCL, Perl, Python, or C for design automation tasks.\n- Familiarity with modeling and simulation of high-speed interface interconnects and channels.\n- Strong problem-solving, analytical skills, and ability to work in a fast-paced collaborative team environment.\n- Demonstrated leadership experience, ability to mentor junior team members, and drive innovation in circuit design.\n\nIf you are passionate about creating impactful designs, driving technological innovation, and collaborating with a talented team, we invite you to apply and take the next step in your career with Intel.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nBusiness group:\nThe Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Sr. Staff Applications Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-07-02", "url": "https://careers.synopsys.com/job/bengaluru/sr-staff-applications-engineer/44408/97218351760", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nAre you passionate about solving the toughest timing challenges at advanced nodes? Join Synopsys’ Signoff Static Timing Analysis (STA) team and work with industry-leading tools like PrimeTime, enabling the world’s most advanced semiconductor designs.\n \nIn this customer-facing role, you will act as a technical expert in timing signoff, collaborating with semiconductor companies to support Synopsys industry-leading PrimeTime signoff solutions for advanced node designs. You will work closely with customers, R&D, and product engineering teams to address complex timing challenges and drive methodology adoption.\n\nThis is a high-visibility, customer-facing role requiring strong technical depth, execution ownership, and cross-functional collaboration with Product and R&D teams. We are looking to hire in Bangalore only for this role.\n\nWhat You'll Be Doing\nWork directly with leading semiconductor companies to resolve complex timing closure and signoff challenges on advanced node designs, often under tight tapeout schedules\nDebug critical timing issues including setup and hold violations, clock domain crossings, SI-induced timing failures, and variation-related signoff problems using PrimeTime\nGuide customers through MMMC analysis, OCV/AOCV/POCV methodologies, and SI-aware timing flows tailored to 5nm and below process nodes\nCollaborate with R&D and product engineering teams to reproduce customer issues, identify root causes, and drive tool enhancements or methodology improvements\nDevelop reference flows, automation scripts in Tcl and Python, and best practice documentation that customers can adopt and adapt to their specific design environments\nDeliver technical training sessions, workshops, and live demos to customer design teams, covering PrimeTime capabilities, signoff methodologies, and advanced node considerations\nDrive adoption of the latest PrimeTime technologies and signoff features by demonstrating value, building proof-of-concept flows, and supporting production deployment\n\nThe Impact You Will Have\nEnable successful tapeouts for cutting-edge semiconductor designs by solving timing signoff challenges that would otherwise delay or block production schedules\nImprove customer productivity and signoff quality by delivering automation scripts and methodology improvements that reduce manual effort and catch issues earlier\nInfluence PrimeTime product direction by channeling real customer pain points, design challenges, and feature requests directly to the R&D team\nBuild long-term technical partnerships with key accounts, becoming the trusted advisor they turn to when timing signoff gets complicated\nAccelerate adoption of advanced PrimeTime features across the customer base, translating new capabilities into production value faster than competitors can respond\nReduce customer support escalations by proactively addressing methodology gaps, training design teams, and building reusable solutions\nShape industry best practices for timing signoff at advanced nodes by documenting what actually works in production, not just what works in theory\n\nWhat You'll Need\nBachelor's degree in Electronics and Communication Engineering, plus Master's degree in VLSI, Embedded Systems, or Communication Systems\nStrong hands-on experience with Synopsys PrimeTime for static timing analysis and signoff, including real production design exposure\nDeep understanding of timing constraints using SDC, MMMC analysis frameworks, and variation-aware methodologies including OCV, AOCV, and POCV\nProven ability to debug complex timing issues such as setup and hold violations, clocking problems, signal integrity effects, and variability-driven failures\nProficiency in Tcl scripting for tool automation and flow development, Python or Perl scripting experience is a strong plus\nExperience with advanced node designs at 5nm and below, including the unique timing challenges and signoff requirements at those geometries\nExcellent communication skills and demonstrated ability to engage directly with customers, understand their technical challenges, and deliver solutions that work in their environment\n\nWho You Are\nYou can walk into a customer meeting, listen to a timing problem described in five different ways by five different engineers, and identify the actual root cause before the meeting ends\nYou are comfortable saying 'I don't know, but I will find out' when faced with an unfamiliar issue, and you follow through quickly with a real answer, not a deflection\nYou write automation scripts that other engineers actually want to use because they solve real problems and do not require a PhD to understand\nYou know when to escalate an issue to R&D and when to solve it with a methodology change, and you can explain that tradeoff clearly to both the customer and the product team\nYou treat customer tapeout schedules as your own deadlines, and you organize your work to unblock them even when it means jumping between three different accounts in one day\nYou can explain why a particular POCV derate is causing a timing violation to a senior design engineer without losing the technical nuance, and then explain the business impact to their manager in two sentences\n\nThe Team You'll Be Part Of\nLeading the key customers and providing technical assistance on the Synopsys Signoff tools for Key customers in India.\n\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "RTL Design -Director(SOC Lead)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-07-01T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719430728", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nThe Director-SoC Lead role is a structural requirement as we chart our path for our next-generation switch and IO chiplet programs that address the needs of AI and Data Centre SoCs.\n\nThis Director-level SoC Lead spans the continuum from high-level system architecture to micro-architectural partitioning and hands-on RTL direction. The mandate spans multi-million gate integration, IP dependency orchestration, synthesis convergence, and timing closure within highly constrained PPA envelopes. At these technology nodes, the architecture is inseparable from the physical reality choices made in topology, buffering strategy, clocking domains, or protocol partitioning, which directly determine feasibility. Only an SoC leader with deep exposure to complex IP optimization and full-chip convergence can prevent costly late-stage refactoring.\n\nYou will be part of the CSG team focused on Data Center innovation through next-gen architectures for Dragonfly which is Qualcomm's rack-scale Agentic AI platform, reshaping compute efficiency and scalability for the AI era .\n\nDefine and defend architectural trade-offs\n\nDrive milestone discipline across design, verification, and physical implementation\n\nAssess cross-IP friction\n\nMentor engineers on design-for-convergence principles\n\nDesign knowledge on Ethernet switch and IO chiplet programs are strategically important.\n\nExperience in ultra-high bandwidth data processing space, where low-latency transport, scalable throughput, and energy-efficient data movement are distinct.\n\nLeadership in this space requires someone who has navigated the full design convergence cycle: Architecture → Micro-Architecture → RTL → Verification → Synthesis → Timing Closure.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n\nMinimum Qualifications:\n\n18+ years of solid experience in IP/SoC design and micro-architecture\nGood knowledge of Digital Design and RTL development\n\nHands-on experience with SoC Design, Verilog RTL coding\n\nMinimum requirement is Bachelor of Engineering however preferred is Masters of Engineering in Computer Science or Computer Engineering. PhD in Computer Science, Engineering, Information Systems, or related field and 18+ years relevant working experience, thereof 5+ years relevant management experience is welcome\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "ASIC Verification Engineer", "company": "NVIDIA", "location": "India, Hyderabad", "date_posted": "2026-07-01", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Hyderabad/ASIC-Verification-Engineer_JR2020484", "is_hardware": true, "platform": "workday", "jd_text": "We are looking for a Hardware and Software Developer. The role is multifaceted - SoCV testbench Infrastructure, Bare-metal boot, Silicon Bringup Tools and CPU/SOC/GPU test frameworks. It involves a detailed understanding of the nVidia CPU, GPU, SOC system and boot architectures. The tools and technologies are complex and involve code that coordinates many IPs in the overall SOC. A key part of NVIDIA's strength is our development tools and environments that enable our incredible pace of delivering new technology to the market. We are looking for a creative and hardworking engineer who is passionate about joining a dynamic & agile SoCV/Emulation Infrastructure and test-frameworks team.\nWhat you will be doing:\nThe work includes building tools, infrastructure, and test frameworks used in RTL-simulations, c-simulations, Emulation, FPGA, and on Silicon.\n\nYou will understand Tegra system architecture, with a focus on all IPs in the SOC that are involved in boot and security features.\n\nThe tools that you build give Design and Verification teams the ability to access registers/memory/DMA engines and other features in their unit. The tools also enable test re-use across multiple platforms (RTL, models, Emulation, and Silicon). The gamut of tools is wide and you also develop features used for Silicon bring up (example: FUSE, ATE, Security, Flash/DMA, Board I2Cs, USB debug devices among others). We strive for the highest quality of test frameworks and tools that we deliver from this team.\n\nYou would assess and build C-model or RTL-simulation capability that allows us to simulate the features before Silicon arrival in a pre-silicon environment.\n\nWhat we need to see:\nBS or MS in Computer Science or Electronics Engineering or equivalent experience with 0-2 years of experience\n\nStrong programmer who is proficient with C, C++, Python.\n\nUnderstanding of SOC and System Architecture.\n\nUnderstanding of How the SOC Devices like DMA, interrupt-engines, CPU, boot-devices, MMU/IOMMU function.\n\nOperating System and Device-Driver concepts and ability to write no-OS test frameworks - i.e tests that run directly on the bare-metal SOC.\n\nA good programmer takes pride in building scalable and maintainable software.\n\nUnderstanding Hardware and/or Software development life cycle.\n\nWay to stand out from the crowd:\nPrevious experience handling Silicon Bringup and in enabling Emulation/FPGA related test frameworks.\n\nExposure to Testbench architectures (C++ testbenches, SV/UVM based testbenches).\n\nVerilog and System Verilog coding skills are a plus.\n\nWith competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us and, due to unprecedented growth, our elite engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you! We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Verification Engineer, Performance", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-07-01", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Verification-Engineer--Performance_JR2014531", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.\n\nWe are now looking to hire strong performance verification engineers with a sharp understanding of CPU and memory architecture. NVIDIA makes some of the fastest CPUs in the world and is solving problems, with its vast arsenal of CPUs, GPUs and SW, in areas such as High-performance computing, Automated driving, Medical imaging and much more! We are seeking highly motivated engineers to join this dynamic and innovative team that owns performance alignment of CPUs and CPU fabrics made by NVIDIA! Do you want to be part of the team that explores and defines the next generation of CPUs?\n\nWhat will you be doing:\nResponsibilities will include development of test plans and strategies, develop simulation environments, system bring-up, validation, and automation to deliver best-in-class CPUs.\n\nDevelop and maintain CPU simulator infrastructure, hardware CPU test and performance infrastructure.\n\nAnalyze and validate CPU and fabric performance, helping to understand current, and guide the development of future CPU products.\n\nDefinition and development of tool chain and workflows that enables the full system performance alignment.\n\nSilicon based competitive analysis of NVIDIA CPUs.\n\nWhat we need to see:\nMaster's or Bachelor's degree in EE/CS or equivalent experience\n\n3+ years of experience preferably in the areas of CPU / SOC Performance Verification and Analysis\n\nStrong understanding of computer system architecture and operating system fundamentals.\n\nHands-on experience with HDLs such as Verilog / System Verilog.\n\nKnowledge of verification methodologies and tools for IP and SoC level verification.\n\nExperience with System Verilog, C/C++, Python languages and relevant frameworks.\n\nBackground with debug on Silicon.\n\n Ways to stand out from the crowd:\nDetailed knowledge of the ARM and/or x-86 architecture.\n\nPrior experience with performance analysis of CPUs.\n\nExperience with analysis and characterization of CPU workloads.\n\nNVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.  \n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Director, Design verification engineering", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-07-01", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Director--Design-verification-engineering_R263708-1", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nKey Responsibilities\nStrategic Technical Leadership: Define verification strategy and architecture for complex Edge AI based digital designs, providing expert consultation across multiple projects and teams\nExecution excellence & Innovation: Pioneer advanced verification methodologies and frameworks that drive organization-wide improvement in verification effectiveness and efficiency. Promote continuous improvement to verification techniques to ensure ‘Zero Defect’ chips\nTeam management: Lead a verification team and deliver to multiple parallel projects. Plan and scale the verification domain with efficient resource management.\nCross-Organizational Influence: Drive verification decisions across organizational lines, collaborating with design teams, product managers, and executives on verification requirements and sign-off criteria. Work with Product test engineering, Silicon validation, and SW team for first-pass Si success and high-volume production.\nComplex Problem Resolution: Lead resolution of the most challenging verification issues requiring specialized knowledge and creative solutions\nTechnical Mentorship: Develop talent across the organization by mentoring verification engineers at all levels and establishing verification methodologies and best practices\nIndustry Leadership: Represent ADI at industry forums, contribute to standards development, and collaborate with EDA tool vendors to influence future verification technologies\nStrategic Quality Assurance: Establish verification metrics and quality standards across product lines that ensure design accuracy and reliability\n\nMust Have Skills\nSystemVerilog and UVM Mastery: Recognized expert-level knowledge of SystemVerilog and Universal Verification Methodology for architecting sophisticated verification environments for Edge AI class of designs\nVerification Strategy and Architecture: Exceptional ability to develop comprehensive verification strategies that drive coverage-driven methodologies and verification closure across multiple product lines\nDigital Verification Expertise: Deep understanding of digital SOC design principles (Processor, Interconnect/Fabric, AHB/AXI protocols, Memory, Security, Boot, High and Low speed peripherals understanding) and verification methodologies, with proven ability to implement innovative verification approaches for complex designs\nAdvanced Debugging Mastery: Superior RTL/System level and GLS debugging skills across multiple design abstractions, with demonstrated ability to solve the most complex verification challenges\nVerification Methodology Innovation: Proven track record of developing and implementing new verification methodologies that advance the state of the art\nTechnical Leadership and Influence: Demonstrated ability to influence verification direction across the organization, mentor engineering teams, and drive methodology adoption through technical expertise\nStrategic Problem Solving: Advanced analytical capabilities to identify and solve unusually significant verification challenges with high impact across product lines\n\nPreferred Education and Experience\nMaster's degree or PhD in Electrical Engineering, Computer Engineering, or related field\n15+ years of relevant verification experience with complex digital SOC designs\nExperience leading verification teams and/or major verification initiatives\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Design Verification Lead", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-06-30T12:46:00+00:00", "url": "https://global-external-amd.icims.com/jobs/87581/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. SMTS SILICON DESIGN ENGINEER THE ROLE: The candidate will get to work on the Verification of complex PLLs that are delivered to various AMD SoCs.   THE PERSON:  You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience in collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.   KEY RESPONSIBILITIES:  Verification of IP features : Test plan creation, Verification of the IP in RTL, Gatesim and Analog Mixed Signal simulations. Create methodology-based (UVM) verification testbenches and components from scratch for various IP features. Quality deliverables through regressions Verification coverage: code-coverage, functional coverage, assertions to achieve 100% verification completeness Reviews, and feedback to design/architecture teams.   PREFERRED EXPERIENCE:  Years of experience 15+ Required. Expertise in System Verilog, methodology based testbench architectures such as UVM, and System Verilog assertions (SVA) Expertise in code and functional coverage. Excellent Problem solving and debugging skills. Excellent Communication skills Strong digital design knowledge. Exposure to UPF based low power RTL verification. Prior experience in leading a team is desirable. Prior experience in PLL verification and Mixed signal verification methodology is highly desirable. Exposure to digital-analog co-simulations (cosims) is desirable.   ACADEMIC CREDENTIALS:  Bachelors or Masters degree in Electronics engineering/Electrical Engineering #LI-PM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Engineer Verification", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-06-30T05:45:33+00:00", "url": "https://jobs.infineon.com/careers/job/563808971373582", "is_hardware": true, "platform": "eightfold", "jd_text": "Your Role\n\nKey responsibilities in your new role\n\nTake responsibility of developing SV RNM models and its verification against schematic.\nDeveloping automatic checkers\nGain knowledge on AMS methodologies/Simulators\nTake responsibility of analog vectors (test parameters) verification at SoC level using DMS verification flow involving UVM testbench and RNM models.\nKnowledge on Scripting.\n\nYour Profile\n\nQualifications and skills to help you succeed\n\nMixed signal verification engineers responsible for AMS verification of Multi phase controllers, power switches.\nDevelopment of SV RNM models for analog blocks like ADC, buck-boost controller, ldo etc.\nVerification of SV RNM models against schematic.\nVerification of analog vectors at SoC (DMS verification flow involving UVM, SV RNM)\nGood understanding on EDA tools/simulators      (Cadence - virtuoso schematic editor, Xcelium,APS/XPS).\n Good understanding of analog design concepts\nAutomation using shell/Perl/Python script.\nSelf-motivated to work effectively & should be able to handle work independently.\n\nContact:\n    VidhiAshok.Thakkar@infineon.com\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\nThis means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.\nPlease let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.\nClick here for more information about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Signal Integrity/Power Integrity Engineer", "company": "Tesla", "location": "Bengaluru, India ; India", "date_posted": "2026-06-30T02:30:00", "url": "https://hire-r1.mokahr.com/social-recruitment/tesla/100004142?#/job/de11a73d-6266-42d0-a1bb-2bd648d5dbfe", "is_hardware": true, "platform": "mokahr", "jd_text": "Position Description \nTesla’s AI Hardware Group is looking for a Signal Integrity/Power Integrity Engineer. In this position, you will work with the team to develop next generation AI chips and systems for all Tesla vehicles, Optimus robots, and Data centers. You will be responsible for Optimus and FSD car computer’s signal and power integrity design/validation, including high speed SerDes, parallel link interfaces, and core power rails from on-die, package, PCB, through connectors, cables, etc. In Tesla, we build everything from the First Principle. You are responsible for the end-to-end SIPI design, sign-off, and validation that is essential to a great product. \n\nResponsibilities \nDesign SOC package, PCB and system with optimized power integrity and signal integrity \nWork with cross functional team and vendors on high-speed interconnect design, including advanced packaging, connector, socket, cable, etc. \nWork with silicon, package and PCB physical design team on high-speed interfaces and power integrity layout optimization \nWork with power supply design engineers and vendors to bring up power delivery network and characterize the electrical performance \nDevelop and execute test plans to validate system level and component level signal and power integrity, including interconnect channel measurement, SerDes validation/equalization optimization, DDR shmoo validation, noise droop measurement, etc. \n\nRequirements \nDegree in a relevant field, or equivalent experience \nRelevant product design and validation experience \nSolid understanding of system and package level SI and PI, electromagnetic theory \nPrior design and SI/PI modeling experience with high-speed serial interfaces, memory interfaces, and power integrity analysis \nFamiliar with lab equipment, such as oscilloscope, VNA, BERT scope, etc. \nExperience with lab correlation and validation of simulation results \nFamiliar with power supply circuit design and validation is a plus \nStrong hands-on skills in data analysis, debugging and lab measurement \nScripting in MATLAB or Python is a plus \nSerDes/DDR IO circuit design and validation is a plus", "jd_status": "stored"}, {"title": "Staff Level Power Integrity Engineer", "company": "Tesla", "location": "Bengaluru, India ; India", "date_posted": "2026-06-30T02:30:00", "url": "https://hire-r1.mokahr.com/social-recruitment/tesla/100004142?#/job/fb662695-34d5-493a-8475-d2b207227b0e", "is_hardware": true, "platform": "mokahr", "jd_text": "About the job \nWe are seeking a highly skilled Senior or Staff Power Integrity Engineer to lead the design, simulation, and validation of advanced Power Delivery Networks (PDNs) for our next-generation AI chips, packages and systems for Tesla’s Robotaxi, Optimus and data center. This critical role owns the integrity of high-current power delivery from the voltage regulator output down to the SoC, ensuring minimal noise, and superior power efficiency. \n \nWhat You'll Do \nArchitect and optimize low-impedance PDNs, including VRMs, PCB planes, and pcb/package-level decoupling strategies, to meet strict target impedance and voltage droop specifications.\nPerform 3D/2D electromagnetic simulation, DC IR drop, AC impedance, and transient analysis using industry-standard tools (Ansys SIwave/HFSS, Cadence Sigrity/PowerSI).\nCollaborate closely with SoC design, package, and PCB layout teams to influence stack-up, ballmaps, and routing guidelines to achieve first-pass silicon success.\nDefine PI test patterns and validation items. Lead lab bring-up, measurement, and debugging of PI issues. Correlate simulation models with measurements using VNAs, Oscilloscopes.\nDevelop and standardize automated simulation workflows and reporting pipelines (Python, MATLAB, or TCL) .\nAct as the design owner, mentor junior engineers, and drive technical decisions across cross-functional teams \n \n What You'll Bring \n5+ years of relevant industry experience in Power Integrity, Power Delivery Network (PDN) design, or related field.\nDeep understanding of EM theory, transmission line theory, and DC/AC circuit analysis.\nProficient in EDA tools such as Ansys (HFSS, SIwave, Q3D), Cadence (Sigrity PowerSI/PowerDC), or Keysight ADS.\nHands-on experience with high-speed instruments such as VNA, Oscilloscopes, or TDR.\nBackground in advanced IC packaging technologies (including 2.5D/3D integration, silicon interposers, and chiplets), on-chip IR analysis, signal integrity preferred.\nDegree in Engineering, Computer Science, or equivalent in experience and evidence of exceptional ability", "jd_status": "stored"}, {"title": "Staff engineer , ASIC AMS Verification", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-06-30T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/42799659", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\n​Job Description:\nTo be part of a highly skilled and challenging high speed DDR & ONFI PHY design team working on the newest technology nodes\nUVM-AMS Integration: Design scalable, reusable metric-driven verification environments using SystemVerilog/UVM combined with mixed-signal simulators.Real Number Modeling (RNM): Author precise and fast behavioral models using SystemVerilog (EEnet/wreal) or Verilog-AMS to replace heavy SPICE sub-circuits, drastically accelerating chip-level verification.Full-Chip Co-Simulation: Bring up and support top-level gate-level simulations (GLS), power-aware verification (UPF/CPF), and mixed-signal co-simulations to catch interface bugs.\nResponsible for overall IP and sub-system verification from test plan creation, UVM development to signoff.\nLeading, mentoring and coaching junior team members\nWork closely with Digital and Analog designers\nSkills Required:\nGood experience of logic simulation, UVM environment and testbench creation\nExperience in AMS simulations\nUnderstanding of Analog blocks like SDLL DCC Band gap\nExperience with RTL debugging, score boarding and code coverage analysis\nUnderstanding of DDR/LPDDR JEDEC or NAND ONFI and DFI protocols\nSound knowledge of Verilog and System Verilog languages\nExposure to modelling and validating complex analog circuits in Verilog and Verilog-A\nM.S./M.Tech, BS/BE (Electronics)\nExperience Required: 5+ Years\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "RTL Design (NOC) - Sr Staff Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-06-30T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718511431", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nRole :\n\nThe role requires design experience of more than 10 years working on RTL Design and Debug.\nThe position is that of a Technical Leader to oversee complex coherent NoCs in large System on Chips which span from Mobile to IOT to Compute , Auto and Servers.\n\nPrimary skills required are IP Design, RTL Coding, DV debug, Expertise in CDC, Synthesis, DFT and engaging with the silicon bring up team to validate the functionality. The role provides ample opportunity and skill build in SoC and NoC Systems domain. The role involves significant interaction across SoC teams , core IP teams to architect and engineer the NoCs that form the lifeline of the product functionality. Delivery of the NOC designed will be a part of the role.\n\nWe look for strong analytical skills and a strong academic background with a flair for taking on the challenges that come with cutting edge Infrastructure on the most complex SoC’s\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior IP Verification Engineer(IOMMU-N)", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-06-30", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Senior-IP-Verification-Engineer-IOMMU-N-_R-101398", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nCore Responsibilities:\nVerification Planning: Analyze architectural specifications to define verification strategies and create comprehensive test plans that outline test cases, checkers, and coverage goals.\n\nTestbench Development: Design and implement scalable, reusable, and constrained-random verification environments using System Verilog and UVM (Universal Verification Methodology).\n\nStimulus & Constraint Generation: Write complex sequences and constrained-random tests to stress-test the IP across corner cases.\n\nDebugging: Perform deep-dive root cause analysis on RTL design failures and testbench issues using waveform viewers (e.g., Verdi, SimVision).\n\nCoverage Closure: Define and track functional and code coverage metrics. Write covergroups and coverpoints to ensure all architectural features have been exercised.\n\nLanguages    : System Verilog, Verilog, Python/Perl (scripting), C/C++\n\nMethodologies:    UVM (highly preferred), OVM, or VMM\n\nProtocols    AXI, AHB,\n\nRequirements:\n3+ years of experience in DV preferably in CPU verification with Bachelor's or Master's in Engineering\n\nProficiency in System Verilog and UVM methodology.\n\nVery good object-oriented programming skills.\n\nAny CPU architecture knowledge (x86, ARM or RISC-V) with test writing/test plan implementation experience.\n\nAny scripting knowledge, preferably python.\n\nBus interface knowledge like AXI or PCIE\n\nIntegration experience with third party VIPs like bus VIPs.\n\nCPU micro-arch knowledge.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Senior Staff Verification Engineer For Worldguard", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-06-30", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Senior-Staff-Verification-Engineer-For-Worldguard_R-101397", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nCore Responsibilities\nVerification Planning: Analyze architectural specifications to define verification strategies and create comprehensive test plans that outline test cases, checkers, and coverage goals.\n\nTestbench Development: Design and implement scalable, reusable, and constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology).\n\nStimulus & Constraint Generation: Write complex sequences and constrained-random tests to stress-test the IP across corner cases.\n\nDebugging: Perform deep-dive root cause analysis on RTL design failures and testbench issues using waveform viewers (e.g., Verdi, SimVision).\n\nCoverage Closure: Define and track functional and code coverage metrics. Write cover groups and cover points to ensure all architectural features have been exercised.\n\nMust have knowledge about the RISC-V and Processor based verification using C.\n\nMust have knowledge about the security architecture and fully independent to own and deliver.\n\nLanguages    : System Verilog, Verilog, Python/Perl (scripting), C/C++\n\nMethodologies    UVM (highly preferred), OVM, or VMM\n\nProtocols    AXI, AHB,\n\nRequirements:\n10+ years of experience in DV preferably in CPU verification with a Bachelor’s or Master’s in Engineering\n\nProficiency in System Verilog and UVM methodology.\n\nVery good object-oriented programming skills.\n\nAny CPU architecture knowledge (x86, ARM or RISC-V) with test writing/test plan implementation experience.\n\nAny scripting knowledge, preferably python.\n\nBus interface knowledge like AXI or PCIE\n\nIntegration experience with third party VIPs like bus VIPs.\n\nCPU micro-arch knowledge.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Principle DFT Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-06-30", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Principle-DFT-Engineer_R-10063975", "is_hardware": true, "platform": "workday", "jd_text": "We are seeking an experienced DFT Engineer (7–12 years) with strong hands-on expertise in Scan Insertion, ATPG, and Gate-Level Simulation (GLS) for complex SoC designs. The candidate will be responsible for implementing and verifying scan architectures, performing scan insertion, generating and analyzing ATPG patterns for stuck-at and transition faults, and executing GLS with and without SDF for DFT validation. The role requires close collaboration with RTL, physical design, and test teams to ensure high fault coverage, clean DFT signoff, and timely tape-out support. Proficiency with industry-standard DFT tools (Mentor/Siemens Tessent, Synopsys, or Cadence), solid Verilog/SystemVerilog skills, and the ability to debug DFT and GLS issues independently are essential. Prior experience supporting pre- and post-silicon activities is a plus.\n\nMore information about NXP in India...\n\n#LI-9415", "jd_status": "stored"}, {"title": "MTS Digital Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-06-30", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2504581", "is_hardware": true, "platform": "oracle", "jd_text": "Responsibilities: \n\nOnSemi is seeking a Sr. Principal Digital design, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products, LED drivers, SiC drivers, smart-Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following: \n\nWork with different product lines for SoC RTL implementation of power driver digital controls for LED/SiC/smartFET/Efuse application, peripherals like I2C, SPI, LIN, CAN protocols \n\nThe candidate will work on digital design architecture, digital RTL, low power design, synthesis and timing analysis with PD engg, Physical Design (PD) interface for the power management chips \n\nThe candidate will be able to work as part of a large and focused team of engineers and will be able to collaborate successfully as needed with design architects, digital verification, project management, and digital and analog design teams in multiple worldwide geographies\n\nDefine and implement micro-architecture to RTL implementation with the refining of features requirements throughout the design process\n\nSupport the bring-up of various features at a system level in various pre-silicon platforms like SOCV, Emulation, FPGA.\n\nOwn technical outcome of design, verification, implementation, and execution of Power Management ICs with complexities that can span from simple regulators to complex designs, control loops, and digital interfaces  \n\nUnderstand project goals, execute with realistic schedule, report status of progress  and understand clarity of project details and milestones \n\nLead and support Customer issues, Production issues, FW and System development, Failure Analysis\n\nSupport post-silicon validation activities for your designs.\n\n#LI-RG1\n\nResponsibilities\nWork with different product lines for SoC RTL implementation of power driver digital controls for LED/SiC/smartFET/Efuse application, peripherals like I2C, SPI, LIN, CAN protocols \nThe candidate will work on digital design architecture, digital RTL, low power design, synthesis and timing analysis with PD engg, Physical Design (PD) interface for the power management chips \nThe candidate will be able to work as part of a large and focused team of engineers and will be able to collaborate successfully as needed with design architects, digital verification, project management, and digital and analog design teams in multiple worldwide geographies\nDefine and implement micro-architecture to RTL implementation with the refining of features requirements throughout the design process\nSupport the bring-up of various features at a system level in various pre-silicon platforms like SOCV, Emulation, FPGA.\nOwn technical outcome of design, verification, implementation, and execution of Power Management ICs with complexities that can span from simple regulators to complex designs, control loops, and digital interfaces  \nUnderstand project goals, execute with realistic schedule, report status of progress  and understand clarity of project details and milestones \nLead and support Customer issues, Production issues, FW and System development, Failure Analysis\nSupport post-silicon validation activities for your designs.\n#LI-RG1\n\nQualifications\nQualifications: \nBS in Electrical Engineering or related + 14 years of experience, or MS + 12 years of experience in defining and implementing Digital Design, Architecture/u-Architectures and ASIC/Mixed signal SoC chip developments\nThe ideal candidate should have thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status\nSolid understanding of RTL design, CDC, synthesis, timing analysis and CDC, UPF and system Verilog (assertion)\nSolid understanding of Verilog, TCL and Perl/Python/XML programming languages\nExperience in developing ASIC/Mixed signal ICs for various Power chips like LED/SiC/GAN drivers, SmartFET and Efuses. \nUnderstanding of digital architecture trade-offs for power, performance, and area\nSolid track record of releasing complex ICs/ IPs to market \nGoal and outcome-focused with the ability to handle multiple projects within the team \nAbility to clearly articulate issues, challenges, and concerns to all levels of management \nMust have good written and verbal cross-functional communication skills\nExperience with microprocessor interconnects and integrating peripherals into the interconnect\n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "SoC Design Director", "company": "Astera Labs", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-06-29T00:00:10-04:00", "url": "https://job-boards.greenhouse.io/asteralabs/jobs/4706987005", "is_hardware": true, "platform": "greenhouse", "jd_text": "Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\n\nJob Title: SoC Design Manager \n\nAbout the Role \n\nWe are seeking an experienced and highly motivated SoC Design Manager to lead a team of engineers responsible for the design and development of next-generation System-on-Chip (SoC) solutions. The ideal candidate will possess strong technical expertise in digital design, excellent leadership skills, and a proven track record of delivering complex SoC projects from architecture through silicon. \n\nRoles & Responsibilities \n\nTechnology Background \n\nExperience of working on complex, large SoCs on latest technology nodes under tight schedules. Exposure to chiplets is desirable. \n\nExpertise around handling chip level design challenges around clocking, resets, power domains/distribution is a must  \n\nExperience of working with DFT, PD, DV teams to solve critical technical challenges of cross-domain nature \n\nExperience of working on PCIE, UCIE, UALink, Ethernet products is highly desirable. \n\nMust have working knowledge of embedded processors and firmware execution to enable key SoC level features  \n\nSoC Design & Development \n\nOwn the design and development of SoC subsystems from specification through RTL implementation. \n\nReview architecture and microarchitecture specifications and translate them into efficient design solutions. \n\nOversee RTL coding, integration, and design reviews to ensure quality and compliance with design standards. \n\nDrive design closure while meeting performance, power, area, and schedule targets. \n\nProject Execution \n\nDefine project plans, resource allocation, and execution timelines. \n\nTrack deliverables and ensure milestones are met on schedule. \n\nIdentify technical and program risks and implement mitigation plans. \n\nProvide regular status updates to leadership and key stakeholders. \n\nCross-Functional Collaboration \n\nWork closely with Architecture, Verification, DFT, Physical Design, Firmware, and Software teams throughout the development cycle. \n\nSupport verification planning and debug activities to ensure robust design quality. \n\nCollaborate with implementation teams to address synthesis, timing, power, and integration challenges. \n\nQuality & Process Improvement \n\nEstablish and enforce design methodologies, coding guidelines, and best practices. \n\nDrive continuous improvement in design processes, productivity, and quality metrics. \n\nEnsure designs meet functional, performance, and reliability requirements. \n\nSilicon Bring-Up & Product Support \n\nSupport post-silicon validation, debug, and product qualification activities. \n\nAssist in root-cause analysis and resolution of silicon issues when required. \n\nProvide technical leadership for future product enhancements and next-generation designs. \n\nTeam Leadership & Management \n\nLead, mentor, and manage a team of SoC/RTL design engineers. \n\nDrive team performance, career development, and succession planning. \n\nParticipate in hiring and onboarding of new team members. \n\nFoster a collaborative and high-performance engineering culture. \n\n \n\nRequired Qualifications \n\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field. \n\n15+ years of experience in ASIC/SoC design and development. \n\n5+ years of experience leading engineering teams or technical projects. \n\nStrong expertise in RTL design using Verilog/SystemVerilog. \n\nExperience with SoC integration, interconnects, memory subsystems, and industry-standard protocols such as AXI, AHB, APB, PCIe, USBUALink, Ethernet, or DDR. \n\nStrong understanding of the complete ASIC development lifecycle. \n\nExperience working with Verification, Physical Design, DFT, and Post-Silicon Validation teams. \n\nExcellent debugging, problem-solving, and communication skills. \n\nExperience with AI/ML, networking, datacenter, automotive, or high-performance computing SoCs. \n\nKnowledge of low-power design techniques and clock/reset architectures. \n\nExperience with scripting languages such as Python, Perl, or Tcl. \n\nPrior experience delivering multiple successful tape-outs. \n\nExperience managing globally distributed engineering teams. \n\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.", "jd_status": "stored"}, {"title": "Senior DFT Engineer - Hardware", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-06-29", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-DFT-Engineer---Hardware_JR2018536", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nAs an NVIDIAN, you’ll be immersed in a diverse, inclusive and supportive environment where everyone is inspired to do their life's best work. The complexity of IOs increased many-fold to support the sophisticated speeds that power our product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. IODFX Engineering team at NVIDIA works on groundbreaking innovations involving crafting creative solutions for IO and interconnect testing for some of the industry's most complex semiconductor chips. Join the team and see how you can make a lasting impact on the world.\n\nWhat you'll be doing:\nPOR to Post Silicon Testing of DFX features for high speed IOs. This includes crafting of test features crucial for manufacturing testability of HighSpeed IOs. Architect, Design & Validate these test features with a robust & scalable testplan development at unit-level and SOC/Full Chip level using verification methodologies like UVM and NVIDIA Internal tools. Pre-Silicon Simulation and Debug of Test functionality using standard Industry tools and sign off on Test coverage for various products using standard coverage metrics.\n\nAbility to work on automation, flow development & improvement, coverage metrics, test execution, bug identification/fix and IO-test productization.\n\nSolve complex Test problems in the mixed-signal world and develop a scalable test solution that works across platforms.\n\nWork with powerful Industry-standard tools for Design and verification methodologies along with SV, UVM, Perl, Python and adapt to NVIDIA custom tools/flows.\n\nPartnering closely with our IP teams for design/verification of IOBIST test-logic, Collaborating with Mixed Signal Circuit design teams to understand the analog design components in an IO cell. Collaborate with other DFX teams, coordinate with Post Silicon Test Engineering and Production Engineering teams for productizing quality test at efficient test cost.\n\nWhat we need to see:\nBtech/BE/BS or Mtech/ME/MS in EE/ECE or equivalent experience\n\nSolid Analytical and Problem Solving skills.\n\nGood understanding and Exposure to Logic design, Architecture & Verification\n\nStrong background in DFT Engineering and Post Si DFX Productization\n\nStrong Coding skills in industry standard scripting languages.\n\n5+ yrs of experience in DFT and/or Industry-standard verification flows like constrained random testing, UVM, coverage metrics, profiling tools, X prop, etc. will be plus.\n\nOutstanding written and oral communication skills with the curiosity to learn.\n\nWith competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us and, due to unprecedented growth, our elite engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Applications Engineering, Architect", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-06-29", "url": "https://careers.synopsys.com/job/bengaluru/applications-engineering-architect/44408/97142010864", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are: \nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\n \nYou Are: \nYou are a passionate and driven professional with a profound mastery of hardware-assisted verification (HAV), using emulation and FPGA prototyping methodologies, with a sharp focus on performance optimization. Your expertise covers the entire lifecycle of HW/SW product development, from early RTL verification to software bring up and platform delivery. You possess a keen analytical mind adept at root cause analysis, especially when it comes to emulation runtime performance bottlenecks. Collaborative by nature, you work seamlessly with peers, customers, and R&D teams, building strong relationships and fostering open communication. You thrive in technologically advanced environments where the pace is fast and innovation is constant. You are eager to learn, excited by new challenges, and motivated to make a tangible impact on customer satisfaction and success.\n \nWhat You’ll Be Doing: \nArchitecting custom emulation methodologies using ZeBu to solve high value problems of customer.\nPrimary technical interface for debugging and resolving issues in ZeBu flow/methodology.\nProviding technical leadership and product evaluation support to key emulation customers across the globe.\nLeading comprehensive root cause analyses to resolve and prevent emulation performance bottlenecks.\nEnsuring the highest standards of verification for SoC designs, contributing to the creation of robust and reliable products.\nWork with internal R&D teams to define product requirements and validate new tool features based on real-world customer usage.\n \nThe Impact You Will Have: \nElevating emulation runtime performance through the development and deployment of cutting-edge technologies.\nDelivering effective root cause analysis that drives measurable improvements in performance and customer satisfaction.\nEnhancing verification processes for SoC designs, ensuring the delivery of high-quality, reliable silicon products.\nBuilding strong, collaborative relationships that drive customer success and foster innovation.\nContributing to the global deployment of advanced performance technologies in ZeBu platforms.\nDriving a culture of continuous innovation and technical excellence within the team and broader organization.\n \nWhat You’ll Need: \nMinimum 15+ years of experience in emulation methodology, spanning early RTL verification to software bring up.\nProven expertise in verification, with a focus on System on Chip (SoC) design bring-up and validation. This includes an extended knowledge of most frequent bus and memory protocols, and a good understanding of OSes booting sequence.\nComprehensive knowledge of the architecture of emulation / FPGA prototyping platforms and their eco-systems.\nA good understanding of the compilation and runtime flows on these emulation platforms.\nDemonstrated experience in using debug features of these emulation platforms, and in conducting root cause analysis for emulation runtime performance issues.\nStrong collaborative skills, with a track record of working effectively with cross-functional teams to drive product and customer success.\nProficient with HDL (Verilog/VHDL), HVL(e/vera/SystemVerilog), C/C++, Unix, and having a strong understanding of ASIC design flows, VLSI, and/or CAD-engineering. \nExperience on VMM/OVM/UVM and knowledge of simulator-emulator co-emulation are preferred.\n \nWho You Are: \nA collaborative team player who thrives in dynamic, fast-paced environments.\nDetail-oriented and analytical, with exceptional problem-solving skills.\nCurious, adaptable, and eager to embrace new challenges and responsibilities.\nAn effective communicator, skilled at conveying complex technical information to diverse audiences.\nAn innovative thinker with a passion for continuous improvement and learning.", "jd_status": "stored"}, {"title": "FPGA Prototyping Staff Applications Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-06-29", "url": "https://careers.synopsys.com/job/bengaluru/fpga-prototyping-staff-applications-engineer/44408/97079287248", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nYou have spent years in the trenches of FPGA-based prototyping, where the difference between a design that boots and one that stalls at initialization is often buried three layers deep in a timing violation or a poorly mapped partition. You know HAPS and ZeBu not from marketing slides but from late nights debugging signal integrity issues and optimizing multi-FPGA configurations that actually have to work under real customer SoC loads.\nWalking into a room with a failing prototype does not rattle you. You pull waveforms, trace signals, check constraints, and methodically narrow down what broke and why. You speak the language of RTL engineers, understand what synthesis tools are doing under the hood, and can explain a complex partitioning tradeoff to a product manager without losing the technical thread.\nCollaboration is not a buzzword for you. You have worked across R&D, validation, and customer-facing teams, translating what a customer needs into requirements that engineers can build and what engineering delivers into something a customer can deploy. At Synopsys, you will work on prototyping platforms that power the development of the next generation of semiconductors, and the solutions you validate will directly accelerate how our customers bring their chips to market.\n\nWhat You'll Be Doing\nValidate advanced HAPS prototyping features using large, complex customer SoC designs, running real workloads to ensure performance, scalability, and functional correctness across multi-FPGA systems\nDebug and resolve intricate design and prototyping issues, from RTL synthesis bottlenecks to inter-FPGA communication failures, and document solutions that improve customer workflows\nDefine and refine technical requirements for HAPS prototyping flows by working directly with R&D, translating field insights into actionable product improvements\nCollaborate with Applications Engineering and Product Validation teams globally to deliver seamless customer deployments, troubleshoot escalations, and ensure prototyping platforms meet real-world use cases\nBuild and optimize automation scripts in Python and Tcl to streamline validation workflows, improve test coverage, and accelerate turnaround time for feature releases\nProvide technical leadership during customer engagements, offering strategic recommendations on partitioning strategies, debug methodologies, and best practices for FPGA-based prototyping\nDrive continuous improvement by analyzing recurring issues, proposing design flow enhancements, and contributing to internal knowledge bases and training materials\n\nThe Impact You Will Have\nAccelerate time-to-market for customer SoCs by validating prototyping features that directly improve debug efficiency and system bring-up speed\nElevate product quality by identifying gaps early in the development cycle and driving cross-functional alignment on fixes and enhancements\nStandardize prototyping workflows across global teams, reducing variability and increasing reuse of validated methodologies\nStrengthen customer satisfaction by delivering solutions that solve real bottlenecks in their prototyping environments, not just check feature boxes\nInfluence the product roadmap by translating field experience into requirements that shape the next generation of HAPS capabilities\nBuild institutional knowledge through documentation and training that scales your expertise across the organization\nEnable faster adoption of new prototyping technologies by creating clear, repeatable deployment processes that work across diverse customer environments\n\nWhat You'll Need\n6+ years of hands-on experience in FPGA-based prototyping, FPGA design, or hardware validation, with direct exposure to large SoC designs and multi-FPGA systems\nStrong proficiency in Verilog and SystemVerilog, with deep understanding of RTL design, synthesis, simulation, and modern FPGA architectures from vendors like Xilinx or Intel\nPractical experience with HAPS or ZeBu prototyping platforms, including partitioning, mapping, debug, and deployment workflows\nSolid scripting skills in Python and Tcl for automation, flow development, and productivity tooling\nProven ability to debug complex hardware and RTL issues using tools like waveform viewers, logic analyzers, and FPGA vendor debug utilities\nBachelor's or Master's degree in Electronics Engineering, Computer Engineering, or equivalent practical experience\nExperience with ARM bus architectures, display interfaces, or industry-standard protocols such as USB, PCIe, SATA, or DDR is a strong plus\n\nWho You Are\nYou can take a cryptic customer bug report, reproduce the issue in a lab setup, and walk out with a root cause analysis and a workaround, all without waiting for perfect information\nYou communicate technical tradeoffs clearly, whether you are explaining a partitioning constraint to an R&D engineer or walking a customer through a debug strategy over a call\nYou stay organized across multiple validation efforts, customer escalations, and internal projects without losing track of what needs to ship next week\nYou push back when a requirement is too vague or a proposed solution does not align with how customers actually use the platform, and you do it constructively\nYou learn quickly, whether it is a new FPGA architecture, an unfamiliar protocol, or a customer's proprietary design flow, and you apply that knowledge to deliver results\nYou thrive in environments where priorities shift, timelines are tight, and the work requires both deep technical focus and cross-team coordination\n\nThe Team You'll Be Part Of\nYou will be part of a dynamic and innovative team focused on driving the next generation of prototyping solutions. Our team thrives on collaboration, continuous learning, and pushing the boundaries of technology. We work closely with cross-functional teams to deliver high-quality solutions that meet the evolving needs of our customers.\n\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\n#TPG", "jd_status": "stored"}, {"title": "IP Design Director", "company": "Astera Labs", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-06-28T23:58:24-04:00", "url": "https://job-boards.greenhouse.io/asteralabs/jobs/4706992005", "is_hardware": true, "platform": "greenhouse", "jd_text": "Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\n\nJob Description – IP Digital Design Manager \n\nPosition Overview \n\nWe are seeking an experienced and highly motivated Digital Design Manager to lead the micro-architecture, design, development, and delivery of IPs and Subsystems from  for next-generation switch products. This role combines deep technical expertise with strong people leadership and program management skills. \n\nThe successful candidate will be responsible for managing a team of IP digital design engineers while driving the successful execution of complex IP development programs. The role requires close collaboration with Architecture, Verification, Physical Design, DFT, Firmware, Software, Product Engineering, and SoC Integration teams to ensure delivery of high-quality IPs that meet performance, power, area, quality, and schedule objectives. \n\nThis position offers the opportunity to influence product roadmaps, establish engineering best practices, and contribute to the development of industry-leading semiconductor solutions. \n\n \n\nKey Roles & Responsibilities \n\nTechnology Background \n\nDeep understanding of complex networking protocols such as PCIE, UALink, Ethernet is a must \n\nExperience of working on latest generations of these protocols is highly desirable.  \n\nExpertise of standard front-end design flows / tools / HDLs for digital design \n\nTechnical Leadership \n\nLead the end-to-end development of digital Ips / Subsystems from architecture through silicon validation. \n\nPartner with architects and product teams to define IP requirements, features, performance targets, and scalability needs. \n\nDrive microarchitecture development and ensure alignment with overall SoC and product requirements. \n\nReview and approve architecture specifications, design documents, RTL implementations, and verification plans. \n\nEnsure IP designs achieve performance, power, area (PPA), reliability, and quality targets. \n\nLead technical reviews and provide guidance on complex design challenges. \n\nDrive design trade-off decisions and risk mitigation strategies. \n\nLead the post-silicon support once silicon is back in the lab. Prior experience of post-silicon work is highly desirable. \n\n \n\nIP Development & Delivery \n\nOwn the successful delivery of IP/Subsystem releases according to committed schedules and quality goals. \n\nEnsure all IP deliverables, including RTL, verification collateral, documentation, synthesis constraints, and integration guides, are completed and released on time. \n\nDrive IP reuse strategies to maximize engineering efficiency across multiple products and platforms. \n\nEstablish standards for IP packaging, version control, configuration management, and release processes. \n\nEnsure compliance with internal design methodologies and industry best practices for all front-end flows such as Lint, CDC, Power Analysis, Timing Constraints. \n\nWork with cross-functional teams to ensure that requirements, dependencies from all stakeholders are met and incorporated into the deliverables \n\n \n\nTeam Leadership & People Management \n\nBuild, lead, and mentor a high-performing IP design team. \n\nSet clear goals and expectations for team members. \n\nConduct performance reviews, development planning, and regular coaching sessions. \n\nIdentify skill gaps and implement training and development initiatives. \n\nParticipate in workforce planning, recruiting, interviewing, hiring, and onboarding activities. \n\nFoster an inclusive, collaborative, and innovation-driven culture. \n\nPromote technical excellence and continuous learning within the organization. \n\n  \n\n Required Qualifications \n\nEducation \n\nBachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or a related field. \n\nMaster's degree preferred. \n\nExperience \n\n15+ years of experience in semiconductor design and development. \n\n5+ years of experience managing engineering teams and complex IP development programs. \n\nProven track record of successfully delivering multiple IPs into production silicon. \n\nExperience managing cross-functional engineering programs across geographically distributed teams. \n\nExperience delivering IPs for AI, networking, datacenter, automotive, mobile, or high-performance computing products. \n\nExperience leading global engineering teams. \n\nExperience managing multiple concurrent IP development programs. \n\nFamiliarity with safety-critical and security-focused design methodologies. \n\nExperience driving IP reuse strategies across multiple product generations. \n\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.", "jd_status": "stored"}, {"title": "Staff Engineer, Silicon & Data Automation Systems (Design, DFT, Diagnostics, Yield)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-06-28T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719393575", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nWe are seeking a highly motivated and technically strong Staff Engineer, Silicon & Data Automation Systems to help build and expand a growing automation team supporting silicon and system yield engineering, spanning design, DFT, diagnostics, and yield engineering workflows. This role will focus on developing production-grade automation, data pipelines, database-backed applications, and engineering tools that improve the speed, quality, and scalability of complex semiconductor engineering workflows.\nThis position is part of a broader effort to increase automation capacity within the silicon engineering organization, beginning with new engineering roles in the Bangalore Design Center (BDC). The engineer will work closely with U.S.-based yield automation leadership and stakeholders, including regular overlap with U.S. Central Time morning hours.\nThis is a senior individual contributor role. The successful candidate will build new automation capabilities under architectural guidance, contribute to robust production systems, and use modern AI-assisted engineering practices to increase development velocity and quality. This role requires an AI-first engineering mindset, where LLM-based coding agents and AI-assisted automation tools are used as core productivity multipliers while maintaining strong human ownership of correctness, security, review, and production safety.\nThe ideal candidate is a strong Linux, data, database, and automation engineer who can work effectively in complex semiconductor engineering environments. Prior experience with semiconductor engineering domains such as silicon design, DFT, validation, diagnostics, or yield is strongly preferred but not required for candidates with strong automation and data engineering depth.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nKey Responsibilities\nAutomation Development & Production Engineering\nDesign, develop, test, and maintain automation tools that improve silicon and system yield engineering workflows, including data processing, diagnostics, reporting, and operation efficiency.\n\nBuild reliable Linux-based automation services, scripts, data loaders, and backend systems used by engineering teams.\n\nDevelop production-grade solutions with appropriate logging, monitoring, error handling, alerting, documentation, and operational supportability.\n\nContribute to systems that are maintainable, fault-tolerant, secure, and suitable for long-running production use.\n\nDebug and resolve automation issues across Linux servers, databases, file systems, scheduled jobs, data feeds, and dependent engineering systems.\n\nWork under architectural guidance to implement new automation capabilities while developing deeper ownership of specific tools, workflows, or data domains over time.\n\n \nData Systems & Database Automation\nBuild and maintain data pipelines that collect, transform, validate, and load engineering and manufacturing data across design, DFT, validation, diagnostics, and yield-related systems.\n\nWork with relational databases, SQL, schema design, query optimization, and database-backed automation workflows.\n\nIntegrate data from multiple sources, including engineering systems, manufacturing data feeds, logs, reports, and analysis outputs.\n\nDevelop tools that make complex data easier to access, validate, monitor, and act upon.\n\nEnsure data quality, traceability, and operational robustness in automation that supports engineering analysis and decision-making.\n\n \nAI-Assisted Engineering & Automation Acceleration\nUse LLM-based coding agents and AI-assisted automation tools responsibly as part of day-to-day engineering work.\n\nApply AI-assisted development practices to improve code quality, accelerate troubleshooting, generate tests, improve documentation, and increase engineering output.\n\nBuild or integrate AI-enabled engineering tools where appropriate, including automation agents, internal assistants, MCP servers, and workflow accelerators.\n\nMaintain strong human review and engineering judgment for AI-generated code, SQL, analysis, documentation, and operational recommendations.\n\nEnsure AI-assisted workflows follow appropriate standards for security, correctness, maintainability, and production safety.\n\nHelp establish practical patterns for using AI-first development methods in production engineering environments.\n\n \nTooling, Applications & Workflow Integration\nBuild backend tools, dashboards, web applications, APIs, command-line utilities, and scheduled automation to support engineering needs.\n\nUse appropriate technologies for the problem, including Python, shell scripting, SQL, Django or similar frameworks, REST APIs, log analytics tools, and enterprise data systems.\n\nIntegrate automation into existing engineering workflows without disrupting production operations.\n\nCollaborate with engineers and stakeholders to identify manual pain points and convert them into reliable automated solutions.\n\nCreate clear documentation, usage guidance, and operational notes so tools can be supported and extended over time.\n\n \nCross-Functional Collaboration\nWork closely with engineers across design, DFT, validation, diagnostics, and data domains to understand requirements and deliver practical solutions.\n\nCommunicate technical findings, implementation options, risks, and tradeoffs clearly to both software-oriented and semiconductor engineering audiences.\n\nParticipate in code reviews, design discussions, troubleshooting sessions, and production readiness reviews.\n\nCollaborate effectively across time zones, including regular overlap with U.S. Central Time morning hours.\n\nContribute to a growing team culture focused on engineering rigor, accountability, automation leverage, and continuous improvement.\n\n \nRequired Qualifications\nBachelor’s or Master’s degree in Computer Science, Electrical Engineering, Data Engineering, Software Engineering, or related field, or equivalent practical experience.\n\nStrong hands-on experience with Linux-based development and automation, including shell scripting, server-side troubleshooting, cron or scheduled jobs, file systems, permissions, and operational debugging.\n\nStrong programming skills in Python or a comparable language used for automation, data processing, backend systems, or engineering tools.\n\nStrong experience with SQL, relational databases, data modeling, query development, and database-backed applications.\n\nExperience building automation that processes, validates, transforms, or integrates large technical datasets.\n\nExperience developing production-quality software or automation with testing, logging, error handling, documentation, and maintainability.\n\nExperience using Git or similar version control systems in a collaborative environment.\n\nPractical experience using LLM-based coding agents or AI-assisted development tools to improve productivity.\n\nAbility to review AI-generated work critically and maintain ownership of correctness, security, reliability, and production readiness.\n\nStrong debugging and problem-solving skills across software, data, database, and Linux environments.\n\nExcellent written and verbal communication skills in English.\n\nAbility to work effectively with U.S.-based stakeholders with required time overlap.\n\nAdditional consideration:\nCandidates with strong software, data, or automation backgrounds from non-semiconductor domains will be considered if they demonstrate the ability to learn complex engineering workflows quickly.\n\n \nPreferred Qualifications\nExperience with semiconductor design, DFT, validation, diagnostics, yield, or product engineering environments.\n\nExperience working with engineering datasets such as test data, DFT outputs, manufacturing data, diagnostic data, or high-volume silicon or system telemetry.\n\nFamiliarity with semiconductor data formats such as STDF, KLARF, wafer maps, lot history, test results, binning, dispositions, or assembly data.\n\nExperience building automation for engineering teams in semiconductor, manufacturing, hardware, or similar domains.\n\nExperience with Oracle, PL/SQL, ODBC, database loaders, schema design, or production database integration.\n\nExperience with Django or similar backend frameworks.\n\nExperience with REST APIs, internal tools, dashboards, reporting systems, or workflow applications.\n\nExperience with log analytics, monitoring, Splunk, or observability tools.\n\nExperience with batch compute, distributed jobs, LSF or grid environments, or multi-server automation.\n\nExperience building or integrating AI-assisted tools, internal agents, MCP servers, or RAG workflows.\n\nFamiliarity with responsible AI-assisted development practices, including human-in-the-loop review and secure handling of generated outputs.\n\nExperience working across global teams and time zones.\n\n \nDesired Technical Profile\nThe ideal candidate operates across multiple layers of the engineering stack:\nLinux: Comfortable diagnosing runtime issues, managing scripts, and troubleshooting production systems.\n\nData: Able to handle complex, messy engineering data and build reliable transformations with traceability.\n\nDatabases: Strong SQL skills with practical understanding of schemas, performance, and data integrity.\n\nAutomation: Able to convert manual workflows into robust and scalable systems.\n\nProduction Mindset: Builds systems that are observable, maintainable, secure, and resilient.\n\nAI-First Engineering: Uses AI tools to increase output while maintaining full accountability.\n\nEngineering Communication: Works effectively with domain experts and delivers practical solutions.\n\n \nWhat Success Looks Like\nA successful engineer in this role will:\nDeliver reliable automation that reduces manual effort for silicon and systems yield engineering teams across design, DFT, diagnostics, and yield workflows.\n\nBuild data tools and pipelines that engineers trust and reuse.\n\nImprove development velocity and quality through responsible use of AI-assisted tools.\n\nContribute production-ready systems that scale across teams and time zones.\n\nLearn semiconductor workflows well enough to translate engineering needs into practical solutions.\n\nOperate as a strong senior individual contributor while growing into deeper ownership.\n\nHelp establish the foundation for a larger Bangalore-based automation capability.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "DFT Engineer (ATPG/Scan Insertion)", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-06-26T05:28:00+00:00", "url": "https://global-external-amd.icims.com/jobs/86496/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. MTS SILICON DESIGN ENGINEER    THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.     THE PERSON:  You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.   KEY RESPONSIBILITIES:  Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues  Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements   PREFERRED EXPERIENCE:  Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools  Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++   Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment.   Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience.   Scripting language experience: Perl, Ruby, Makefile, shell preferred.   Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions.     ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-AA1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "RTL Design Engineer -Security /Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-06-26T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719198709", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nKey Responsibilities\n·  Develop micro-architecture and RTL design for Cores related to security. Responsible for block level design.\n·  Micro architecture and enabling SW teams to use HW blocks.\n·  Running ASIC development tools including Lint and CDC.\n·  Report status and communicate progress against expectations.\n \nMinimum Qualifications\n·  Bachelor's degree in Engineering, Information Systems, Computer Science, or related field.\n·  2+ years Hardware Engineering experience or related work experience.\nPreferred Qualifications\n·  8 to 11 years of work experience in ASIC/SoC Design\n·  Experienced in RTL design using Verilog / System Verilog.\n·  Knowledge of cryptography, public/private key, hash functions, random number generator, encryption/signatures algorithms (AES, SHA, GMAC, etc.) will be a plus.\n·  Experienced in Linting, CDC and LEC.\n·  Experienced in database management flows with Clearcase/Clearquest.\n·  Ability to program effectively in Verilog, C/C++, Python, Perl\n·  Excellent oral and written communications skills\n·  Proactive, creative, curious, motivated to learn and contribute with good collaboration skills..\nngineering Preferred: Master's, Electrical Engineering\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RISCV CPU Design Verification Staff Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-06-26T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446716929281", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nQualcomm is hiring strong DV engineers to verify high performance and low power RISC V based CPUs in Bangalore.\nRoles and Responsibilities\no  Develop and execute verification plans for units and features of a CPU design\no  Use simulation and formal verification methodologies to execute test plans, develop testbench components like checkers, assertions, stimulus generators.\no  Work closely with system architects, design team, software teams and Soc team to validate system use cases.\no  Work closely with emulation team to enable verification on emulators and FPGA platforms.\no  Debug and triage failures in simulation, emulation and/or Silicon.\nBE/BTech degree in CS/EE with 8+ years’ experience.\no Implementation of assembly and C language tests for verifying CPU architecture.\no  Experience in C/C++, scripting languages, HDLS like Verilog/System Verilog\no  Good Understanding of CPU architectures and CPU micro-architectures. Industry experience with CPU architecture (eg: x86, ARM, MIPS, RISCV, POWER) will be a plus\no  Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.\nPreferred Requirements:\no  Strong understanding of power management features in CPUs and CPU based Socs.\no  In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture\no  Experience with advanced verification techniques such as formal and assertions is a plus\no  Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Analog Circuit Design - IO Design Engineer", "company": "Samsung", "location": "SSIR, Goldstone, Bangalore, India", "date_posted": "2026-06-26", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/SSIR-Goldstone-Bangalore-India/Analog-Circuit-Design---IO-Design-Engineer_R118179-1", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centres outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.\nRole and Responsibilities\n\nRoles and Responsibilities\n\n1) Proficient in GPIO cells like TX, RX & Serial Interface logics.\n2) Sound knowledge on Analog basic blocks design like comparators, schmitt triggers, filters & Opamps.\n3) At least 2 or 3-Projects tape out experience is required preferably in GPIO platforms.\n4) Strong knowledge on High voltage designs(LVCMOS33, LVCMOS25 & LVCMOS18 serial interfaces) with stacked driver(2-stack or 3-stack)architecture implementation.\n5) Design knowledge on Power clamp, Ground clamp cell developments.\n6) Expected experience range : 7 to 13 years. \n\nSkills and Qualifications\n\nExperience – 7 to 13 Years of experience\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "Analog Circuit Design Lead Engineer-HSI", "company": "Samsung", "location": "SSIR, Goldstone, Bangalore, India", "date_posted": "2026-06-26", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/SSIR-Goldstone-Bangalore-India/Analog-Circuit-Design-Lead-Engineer-HSI_R118176", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.\nRole and Responsibilities\n\nCandidate with 6-10 years of experience in architecting and designing various Analog circuit blocks especially high-speed serial interfaces, Low dropout regulators (LDOs), high-speed clocking circuitries, High-speed Seriallizers/Deseriallizers, Transmitter Drivers etc.\nShould have strong Analog design fundamentals with attention to details and quality.\nShould have gone through multiple full Analog block design cycles that involve Specification definition, designing to meet corner conditions, Post-layout simulations and optimizations, Quality & reliability checks etc.\nInvolvement in post-silicon validation and debug will be an additional plus point.\nShould possess good communication and presentation skills with experience in collaborating and working with global teams.\nShould be a good team player and should possess strong aptitude toward quality and completeness of documentation, cross-functional deliverables, Review packages and other transactions within and outside the team.\nShould be well versed with advanced and state-of-the-art circuit design tools. Prior experience in scripting (python, Matlab, Skill etc) and AI based circuit optimization is a definite plus point.\n\nSkills and Qualifications\n\nExperience – 6 to 10 Years of experience\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "Analog Circuit Design QA Lead Engineer", "company": "Samsung", "location": "SSIR, Goldstone, Bangalore, India", "date_posted": "2026-06-26", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/SSIR-Goldstone-Bangalore-India/Analog-Circuit-Design-QA-Lead-Engineer_R118175", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.\nRole and Responsibilities\n\n- Ideal Candidate should have 10+ years of experience in Analog Design and leading a Project.\n- He should have at least one domain experience\n- High speed Clocking circuits or Serdes design experience\n- Analog (ADC/DAC) experience\n- Thermal sensors, OSC, LDO design experience.\n- Candidate should have experience in full design cycle of Analog and Mixed Signal IP. \n\nRoles\n-  will lead Analog QA design Activities.\n-  will Review Analog Design with focus on quality of IP .\n-  will suggest Testbenches and Analyse when circuit can fail.\n-  will interact with Design team, and layout team .\n-  will Review IP Design kit .\n\nSkills and Qualifications\n\nExperience – 10 -18 Years of experience\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "STD Cell QA Engineer", "company": "Samsung", "location": "SSIR, Goldstone, Bangalore, India", "date_posted": "2026-06-26", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/SSIR-Goldstone-Bangalore-India/STD-Cell-QA-Engineer_R118173", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.\nRole and Responsibilities\n\nStrong knowledge and hands-on experience in QA methodologies for standard cell libraries, including test plan development, regression testing, and post-layout verification\n4 to 13 years of experience in Standard Cell Circuit design of high-performance flip flops, latches, multibit flip flops, voltage level shifters, power optimization cells, and clock cells.\nStrong knowledge and hands-on experience in developing environments and extracting post-layout netlists.\nGood understanding of CMOS device characteristics, design rules, latch-up, and electro migration.\nProficiency in digital circuit simulation, design and optimization for better PPA.\nHands-on experience in statistical/variation analysis.\nContributing to the creation of cutting-edge semiconductor technologies that power a wide range of applications.\nEnhancing the performance and efficiency of standard cell circuits, impacting the overall quality of our products.\nDriving innovation in power optimization and clock cell design, leading to more energy-efficient solutions.\n\nSkills and Qualifications\n\nExperience – 4 to 13 Years of experience\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "Library Design Engineer", "company": "Samsung", "location": "SSIR, Goldstone, Bangalore, India", "date_posted": "2026-06-26", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/SSIR-Goldstone-Bangalore-India/Library-Design-Engineer_R118171-1", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.\nRole and Responsibilities\n\nWork on library architecture discussion & optimization effort to improve overall Library PPA.\n\nDrive layout optimization effort by identifying & reducing parasitics to push circuit PPA.\n\nWork on Library PPA for different technology, architecture, PDK releases.\n\nDevelop standard cell circuits that push design PPA.\n\nWork on PNR block to validate the IP in testchips & benchmark new tech/PDK libraries.\n\nWork on Library Characterization (Timing/Power/Variation/etc) for all libraries.\n\nEngage with CPU, SOC and GPU teams on physical design requirements.\n\nSkills and Qualifications\n\nExperience – 6 to 13 Years of experience\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "SRAM Layout Engineer", "company": "Samsung", "location": "SSIR, Goldstone, Bangalore, India", "date_posted": "2026-06-26", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/SSIR-Goldstone-Bangalore-India/SRAM-Layout-Engineer_R118170", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.\nRole and Responsibilities\n\n· Must have 4 - 8 years of experience in SRAM Layout in advanced CMOS process\n\n· Should be able to perform SRAM Memory layout development and physical verification activities for complex designs as per provided specifications.\n\n· Should have expertise in layout area and routing optimization, design rules, yield and reliability issues.\n\n· Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.\n\n· Should have adequate knowledge of schematics, interface with circuit designer and CAD team.\n\n· Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,\n\nSkills and Qualifications\n\nExperience – 4 to 8 Years of experience\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "Architect - Performance Verification and Analysis", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-06-26", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Architect---Performance-Verification-and-Analysis_JR2020222", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.\n\nThe NVIDIA GPU and SoC Architecture group is seeking strong architects with great analytical skills and a deep understanding of system architecture and performance to use your skills creatively on processor and system architecture performance of full applications driving scalable improvements for all of our artificial intelligence/machine learning, automotive, geforce and high-performance computing products. This position offers you the opportunity to have a real impact on the hardware and software that underlies the most exciting trends in modern computing in the world. We are looking for someone who is passionate about and loves what you do and excited about creatively applying what you know to make a difference.\n\nWhat you'll be doing:\nPerformance analysis/ bottleneck analysis of complex, high performance GPUs and System-on-Chips (SoCs).\n\nWork on hardware models of different levels of extraction, including performance models, RTL test benches and emulators to find performance bottlenecks in the system.\n\nWork closely with the architecture and design teams to explore architecture trade-offs related to system performance, area, and power consumption.\n\nUnderstand key performance usecases for the product. Develop  workloads and test suites targeting graphics, machine learning, automotive, video, compute vision applications running on these products.\n\nDrive methodologies for improving turnaround time, finding representative data-sets and enabling performance analysis early in the product development cycle.\n\nDevelop required infrastructure including performance simulators, testbench components and analysis tools.\n\nWhat we need to see:\nBE/BTech or MS/MTech, or equivalent experience in relevant area, PhD is a plus.\n\n2+ years of relevant experience dealing with system level architecture and performance issues.\n\nStrong understanding of System-on-Chip (SoC) architecture, graphics pipeline, CPU architecture, memory subsystem architecture and Network-on-Chip (NoC)/Interconnect architecture.\n\nSolid programming (C/C++) and scripting (Bash/Perl/Python) skills. Exposure to Verilog/System Verilog, SystemC/TLM is a strong plus.\n\nStrong debugging and analysis (including data and statistical analysis) skills, including use of RTL dumps to debug failures.\n\nExposure to performance simulators, cycle accurate/approximate models or emulators for pre-silicon performance analysis is a plus.\n\nExcellent communication and organization skills.\n\nAbility to work in a global team environment.\n\nWays to stand out from the crowd:\nStrong background in System Level Performance aspects for Graphics and High Performance Computing.\n\nExposure to GPU application programming interfaces like CUDA, OpenGL, DirectX.\n\nExpertise in data analysis and visualization.\n\nWidely considered to be one of the technology world’s most desirable employers, NVIDIA leads the way in groundbreaking developments in Artificial Intelligence, High-Performance Computing and Visualization. The GPU, our invention, serves as the visual cortex of modern computers and is at the heart of our products and services. Our work opens up new universes to explore, enables amazing creativity and discovery, and powers what were once science fiction inventions from artificial intelligence to autonomous cars.\n\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "ASIC / Digital Design Director of Engineering", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-06-26", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505695", "is_hardware": true, "platform": "oracle", "jd_text": "Job Title: Director of Engineering – Automotive Networking\n\n Location: Bangalore India\n\n  \n\nAbout the Role\n\n We are looking for a Director of Engineering to lead development of next-generation Automotive Networking solutions including SerDes, Ethernet, and high-speed communication SoCs.\n\n You will drive strategy, architecture, and execution while working closely with global teams, customers, and business leadership to deliver market-leading products.\n\nWhy Join Us\n\n Join a global team shaping the future of connected vehicles through advanced automotive networking technologies.\n\nResponsibilities\nKey Responsibilities\n•    Define product architecture and roadmap for Automotive Networking solutions\n•    Lead cross-functional teams delivering SoCs from concept to production\n•    Drive system-level design across MAC, PCS, PHY, and Digital Front-End subsystems [JD Staff D...Networking | Outlook]\n•    Own execution excellence: schedules, quality, risk management, and silicon success\n•    Partner with Product Management and customers on solution definition\n•    Build and scale world-class engineering teams globally\n•    Drive innovation in design methodologies, verification, and integration\n\nQualifications\nRequired Qualifications\n•    BS/MS/PhD in Electrical Engineering or related field\n•    20+ years of experience in semiconductor or SoC development\n•    Proven leadership of large engineering teams and complex programs\n•    Expertise in: \no    Networking / communication SoCs (Ethernet, SerDes, high-speed links)\no    RTL-to-silicon development flows\no    Cross-functional integration (Analog, Firmware, Systems)\n\nPreferred Qualifications\n•    Automotive domain experience (ISO 26262, AEC-Q100)\n•    Experience with Ethernet PHY/MAC or similar high-speed architectures \n•    Customer-facing or product definition experience\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Manager, Design Verification", "company": "Analog Devices", "location": "CLOSED-India, Bangalore, Aveda Meta", "date_posted": "2026-06-26", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/CLOSED-India-Bangalore-Aveda-Meta/Manager-Physical-Design_R256091", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \n\nRole Overview\nThe Lead Physical Design Engineer is role which combines deep hands-on implementation expertise with technical leadership. This role owns complex block- and/or top-level physical design for advanced-node SoCs and leads a small group of engineers to achieve high-quality, on-time delivery.\n\nKey Responsibilities\nTechnical Ownership\n\nOwn end-to-end physical implementation (floorplanning, power planning, placement, CTS, routing, ECO) for complex blocks or subsystems across advanced technology nodes (e.g., 22nm, 16nm, 7nm, 5nm, 4nm).\nDrive timing closure, congestion resolution, IR/EM, signal integrity, and physical verification (DRC/LVS/antenna) to meet PPA and quality targets.\nDefine and refine hierarchical PNR strategies, IO ring/PG structures, and integration guidelines for large SoCs.\nPerform in-depth analysis and debug of tool issues, timing failures, and physical design anomalies; propose robust, scalable solutions.\n\nMethodology and Automation\n\nDevelop, maintain, and enhance physical design methodologies, scripts, and flows (e.g., for PDN, PG, clock structure, exception handling, signoff automation).\nProactively identify opportunities for flow improvements and standardization to reduce turnaround time and error rates.\nEvaluate EDA tool features and drive best practices in collaboration with CAD/enablement teams.\n\nTechnical Leadership & Team Enablement\n\nProvide technical direction to a small group of physical design engineers, including task breakdown, priority setting, and quality expectations.\nMentor junior engineers and NCGs in PNR, STA and debug practices to build a strong second tier of technical capability.\nReview floorplans, constraints, and implementation choices from team members, giving clear, actionable feedback.\nAct as a go-to technical reference within the PD team.\n\nCross-Functional Collaboration\n\nWork closely with RTL design, STA, DFT, CAD, and packaging teams to converge on implementation-friendly architectures and constraints.\nCommunicate risks, options, and trade-offs clearly to project leads and managers, and help shape mitigation plans.\nParticipate in design reviews and signoff reviews, representing physical design status, risks, and recommendations.\n\nRequired Qualifications\n\nStrong experience in physical design implementation for complex digital SoCs, typically 8–12+ years in physical design or equivalent level of mastery.\nProven hands-on expertise with industry-standard PNR and signoff tools (e.g., Cadence Innovus, Synopsys ICC2, Tempus/PrimeTime, RedHawk, Voltus, etc.).\nDemonstrated success in closing challenging blocks/subsystems on advanced nodes (timing-, IR-, and congestion-critical designs).\nSolid understanding of:\nFloorplanning and partitioning strategies\nPower grid and PDN methodology (including IR/EM mitigation)\nAdvanced clock tree/clock mesh design and constraints\nSTA constraints (modes/corners, exceptions, derates)\nPhysical verification and reliability checks\n\nLeadership Expectations\n\nStrong problem-solving and debugging mindset, with a bias toward scalable, automated solutions.\nClear, concise communication skills—able to explain complex technical issues and options to different audiences.\nDemonstrated commitment to mentoring, knowledge sharing, and raising the capability of the broader team.\nComfortable operating in a dynamic environment with shifting priorities while maintaining quality and accountability.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "RTL Design - SrLead/Sr Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-06-25T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719282083", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    12+ years of Hardware Engineering or related work experience.\n•    3+ years of experience with circuit/logic design/validation (e.g., digital, analog, RF).\n•    3+ years of experience utilizing schematic capture and circuit stimulation software.\n•    3+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test highly critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Participates in or leads the implementation of advanced design rules and processes for electronic hardware, equipment, and/or integrated circuitry.\n•    Conducts highly complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops novel manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of highly critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Advises and leads engineers in the development of complex hardware designs, evaluating various design features to identify potential flaws or issues.\n•    Writes detailed technical documentation for highly complex Hardware projects; reviews technical documentation for junior engineers.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making is significant in nature and affects work beyond immediate work group.\n•    Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. \n•    Has a moderate amount of influence over key organizational decisions.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Design Implementation - Synthesis, Sr Staff Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-06-25T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719278297", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nMinimum Qualifications\n\no 13+ Year of industry experiences in the following areas: Expertise in Synthesis - Synopsys Design Compiler, DCG/DC_NXT/Fusion Compiler and/or Cadence RC/Genus.\no Expertise on with multi-voltage, power aware synthesis, UPF flows in synthesis and low power designs.\no Expertise in formal verification with Cadence LEC/ Synopsys Formality\no Expertise in writing and debugging timing constraints\no Perl and/or TCL scripting, makefile flows.\n\nAdditional Job Description\nMasters in Electronics or Electrical Engineering\n\nwork on integration or RTL design is considered plus.\n\nCandidates should have excellent analytical and problem-solving skills\n\nTrack record of driving ideas from design through commercialization  \n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior GPU Floorplan Design Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-06-25", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-GPU-Floorplan-Design-Engineer_JR2020167", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking a talented GPU Floorplan design Engineer to design and implement the world’s leading GPU's as part of completely new team being built in Bangalore. This role sits at the intersection of architecture, RTL, performance analysis, and physical design, with a strong focus on path forward, early planning, feasibility studies, and physical trade-off exploration. This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n\nWhat you will be doing:\nWorking with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.\n\nDrive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities.\n\nSolve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.\n\nYou will build tools and improve existing infrastructure to optimize chip area and speed of execution.\n\nWhat we need to see:\nB.Tech./ M.Tech. with 5+ years of experience in floorplan, SOC planning, ASIC Physical design or related roles.\n\nA deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.\n\nHands-on experience with chip-level or subsystem-level floorplanning and physical planning\n\nSolid understanding of timing, congestion, power distribution, and physical constraints\n\nExperience in Verilog, System Verilog or similar HVL.\n\nExperience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.\n\nStrong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview.\n\nPython, Perl and C/C++ programming language experience.\n\nWays to stand out from the crowd:\nExperience in driving development of large scale ASIC floorplan is a huge plus.\n\nNVIDIA is widely considered to be one of the technology world’s most desirable employers. Our products are leading the way with groundbreaking developments in Artificial Intelligence, Autonomous Driving, High-Performance Computing and Visualization. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the fastest and most power efficient chips in their class? If so, we want to hear from you.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior DFT Engineer - Hardware", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-06-25", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-DFT-Engineer---Hardware_JR2020076", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nAs an NVIDIAN, you’ll be immersed in a diverse, inclusive and supportive environment where everyone is inspired to do their life's best work. The complexity of IOs increased many-fold to support the sophisticated speeds that power our product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. IODFX Engineering team at NVIDIA works on groundbreaking innovations involving crafting creative solutions for IO and interconnect testing for some of the industry's most complex semiconductor chips. Join the team and see how you can make a lasting impact on the world.\n\nWhat you'll be doing:\nPOR to Post Silicon Testing of DFX features for high speed IOs. This includes crafting of test features crucial for manufacturing testability of HighSpeed IOs. Architect, Design & Validate these test features with a robust & scalable testplan development at unit-level and SOC/Full Chip level using verification methodologies like UVM and NVIDIA Internal tools. Pre-Silicon Simulation and Debug of Test functionality using standard Industry tools and sign off on Test coverage for various products using standard coverage metrics.\n\nAbility to work on automation, flow development & improvement, coverage metrics, test execution, bug identification/fix and IO-test productization.\n\nSolve complex Test problems in the mixed-signal world and develop a scalable test solution that works across platforms.\n\nWork with powerful Industry-standard tools for Design and verification methodologies along with SV, UVM, Perl, Python and adapt to NVIDIA custom tools/flows.\n\nPartnering closely with our IP teams for design/verification of IOBIST test-logic, Collaborating with Mixed Signal Circuit design teams to understand the analog design components in an IO cell. Collaborate with other DFX teams, coordinate with Post Silicon Test Engineering and Production Engineering teams for productizing quality test at efficient test cost.\n\nWhat we need to see:\nBtech/BE/BS or Mtech/ME/MS in EE/ECE or equivalent experience\n\nSolid Analytical and Problem Solving skills.\n\nGood understanding and Exposure to Logic design, Architecture & Verification\n\nStrong Coding skills in industry standard scripting languages.\n\n3+ yrs of experience in DFT and/or Industry-standard verification flows like constrained random testing, UVM, coverage metrics, profiling tools, X prop, etc. will be plus.\n\nOutstanding written and oral communication skills with the curiosity to learn.\n\nWith competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us and, due to unprecedented growth, our elite engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior System Integration and Validation Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-06-25", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-System-Integration-and-Validation-Engineer_JR2019683", "is_hardware": true, "platform": "workday", "jd_text": "The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. System Integration sits at the intersection of all of them. It is the layer where every architecture, design, software, and manufacturing decision meets reality. When something breaks late in a program, it usually breaks here first.\n\nWe are hiring a Senior Engineer to lead system validation, debug, and cross-functional alignment on one of our most consequential silicon programs. Your work will sit on the critical path of every flagship build, and the judgment you bring to ambiguous, multi-team failures is the difference between shipping on milestone and slipping! The two hardest, highest-leverage problems in this seat:\nFind critical silicon and platform issues before they reach the customer — by shifting validation coverage left with system stress, PVT, and feature-interaction tests that catch escapes before software hardens. Your work shows up in DPPM, escape rate, and ramp confidence.\n\nBuild AI-enabled validation as a real capability, not a demo — by deploying debug, triage, root-cause hypothesis generation, and regression workflows with the evals and guardrails that make them trustworthy enough to gate production decisions.\n\nWhat you’ll be doing:\nOwn end-to-end system validation of NVIDIA GPU, SoC, and platform programs — feature checks, PVT stress, system-stress campaigns at scale, and multi-unit fleet testing.\n\nLead debug of the hardest cross-stack issues — logic, signal integrity, power delivery, firmware, and software interaction — and drive them to root cause with reusable workarounds and productized fixes.\n\nDevelop test plans, scripts, and automation for next-generation chips ahead of physical builds, translating architecture, boot flows, high-speed I/O, and power and thermal dependencies into executable coverage.\n\nDesign and deploy AI-enabled debug and validation workflows used by the team — with explicit guardrails (evals, regression validation, false-positive handling) and measurable impact on cycle time, debug velocity, or escape rate.\n\nTranslate complex silicon and system risk into decision-ready options for technical and executive audiences — without padding or hand-waving.\n\nPartner with globally distributed teams across silicon design, DFT, firmware, software, manufacturing, and platform engineering — including counterpart engineers in India and other major hubs.\n\nLead crisis-mode debug task forces when a program is stuck, and convert the learnings into reusable methodology for adjacent programs.\n\nWhat we need to see:\nBTech/BE or MTech/ME in Electronics, Electrical, or Computer Engineering (or equivalent experience), plus 8 to 12 years of post-silicon validation, system integration, or platform debug experience on shipped GPU, CPU, or SoC products.\n\nHands-on debug depth across silicon, board, and software boundaries — logic design, signal integrity, power delivery, high-speed I/O, and PVT behavior — with strong EE fundamentals across SI/PI, power delivery, and thermal, and a working understanding of GPU, CPU, or SoC architecture across PC, Datacenter, or Automotive.\n\nAt least one specific example of taking an ambiguous, multi-team failure to root-cause closure with a productized fix, and a track record of leading a project team end-to-end through a real crisis with decision points you owned.\n\nDemonstrated AI-driven validation workflow you built or scaled, not just used — with adoption beyond yourself and measurable impact on debug velocity, coverage, or escape rate. You can describe the guardrails you put in place and where AI is dangerous in your workflow.\n\nWays to stand out from the crowd:\nA history of building reusable validation methodology, debug playbooks, or test frameworks that were adopted by other programs or teams — backed by patents, conference papers, invited talks, or recognized contributions.\n\nHands-on subsystem depth in HBM, SerDes or high-speed I/O, power and thermal, or advanced packaging — failure modes, debug instrumentation, and the tradeoffs that show up in production.\n\nExperience partnering deeply with a counterpart team in India or another major engineering hub — examples of shared culture, shared metrics, and shared on-call across geographies.\n\nAI work that goes beyond personal-copilot use — agentic workflows, RAG-grounded debug assistants, regression bucketing, or automated triage deployed at team scope with adoption metrics.\n\nNVIDIA is the world leader in accelerated computing, and our work powers AI, gaming, robotics, autonomous systems, and scientific discovery. We invest in our people with competitive benefits, flexible time off, and continuous learning, and we build a team where everyone can do their best work. Come help us build chips that change what is possible!\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Principal Analog Layout Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-06-25", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505291", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Principal Analog layout Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and e-fuses for consumer, industrial and automotive applications. In this role, you will focus on the following \n\n  Produce high quality layout for complex AMS IP blocks (voltage regulators, bandgap, current sense-amp, amplifier, high voltage switches, drivers etc) \n\nContribute to area estimation and optimization, floor planning, power routing, shielding, physical verification (DRC, ERC, LVS, ESD, etc.), as well power analysis (EM / IR-Drop) \n\nContribute and support team in taping out high-performance microcontroller chip \n\nActively seek out opportunities to work with cross-functional teams (Chip team, Tech, CAD) \n\nDevelop scripts and methods for layout design automation \n\n#L1-LK1\n\nQualifications\nExperience in delivering high quality analog layout IPs \n\nGood understanding of layout fundamentals and best practices \n\nProficiency in interpretation of CALIBRE DRC, ERC, LVS, reports \n\nProgramming knowledge in SKILL, Perl, and/or Python is a bonus \n\nExperience with CADENCE or MENTOR GRAPHICS layout tools \n\nSolid understanding of semiconductor manufacturing process and DFM techniques \n\nProficient at debugging/fixing LVS/DRC errors \n\nMust be familiar with Cadence Design Environment (CDE) and Unix OS \n\nMust have strong communication skills and be a team player \n\n#L1-LK1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Digital Mixed Signal (DMS) Design Verification Engineer", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-06-25", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Digital-Mixed-Signal--DMS--Design-Verification-Engineer_R263418", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nAnalog Devices is seeking a Digital Mixed Signal (DMS) Design Verification Engineer who will be responsible for design verification of highly integrated solutions and products in a multifunctional team. You will be working on driving real revenue growth on the next generation of Intelligence at the Edge products across multiple products and business units. \n\nAbout the Role \n\nKey member of design verification team, which has both DMS and digital DV engineers. The candidate will be responsible for completing modeling & verification of large integrated products.   The candidate is also encouraged to participate in cross company technical initiatives as well as patent and publish work where possible. \n\nRequirements \n\nB.Tech/M.Tech with 2+ years of industry experience in analog/mixed signal behavioral modeling at various levels of abstraction and full chip verification using these behavioral models & digital RTL/PA/Gates. \n\nGood understanding of analog design concepts and mixed signal design architectures. Exposure to products that integrate a wide variety of Analog/Mixed-Signal/RF building blocks such as Power Management, ADCs, DACs, PLL, bandgap references, oscillators, SerDes and related digital control and signal processing. \n\nHands on experience in developing verification plan, verification environments and verification/debug of complex mixed signal products at block & chip-top levels. \n\nExceptional interpersonal and communication skills, collaborate with multiple teams spread across the globe to get the work done. \n\n \n\nResponsibilities \n\nCome up with verification strategy for a product after going through product requirements and design specifications. \n\nCreate models for analog/mixed-signal blocks for chip-top verification, tradeoff accuracy vs. speed. Validate models against actual design (self-checking tests). \n\nCreate verification plans, build verification environment, develop self-checking testcases. Bring up chip top mixed-signal verification environments (DMS DV). \n\nDeploy industry standard SV/UVM based metric driven verification approach. \n\nCollaborate and work closely with team members from various disciplines (system architects, digital design, analog design, digital DV, DFT etc.) for first pass silicon. \n\nSupport test and characterization teams in post-silicon validation. \n\nCollaborate with CAD team to deploy next generation innovative design verification methodologies to reduce overall TTM. \n\n \n\nSkill Set [Experience of following is desired, not all but most of them] \n\nModelling of analog blocks \n\nSV-RNM \n\nFamiliarity with Analog/Mixed-Signal/RF design architectures and debug experience with schematic capture tools such as Cadence Virtuoso and waveform viewers such as Cadence Simvision. \n\nExperience and debug with digital simulators such as Cadence Xcelium/Synopsys VCS. \n\nExperience with SV/UVM (agent creation, env building, score-boarding, RAL etc.). \n\nTracking of verification metrics(Vplan & Coverage) and regression management, Metric Driven Verification (MDV) framework using tools such as Cadence vManager. \n\nExperience with languages/tools/software relating to product development is an added advantage. \n\nC \n\nAutomation with scripting languages: Python/Perl/Shell etc. \n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Modelling Lead (SystemC / Virtual-Platform Architect) ", "company": "Lumilens", "location": "Bengaluru, India", "date_posted": "2026-06-24T21:40:54.946000+00:00", "url": "https://jobs.ashbyhq.com/lumilens/33571f85-7e75-4646-80a0-16592bb6ce32", "is_hardware": true, "platform": "ashby", "jd_text": "About Lumilens\nAt Lumilens we are building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new era of computing faster, cooler, and massively more efficient.\nWe’re a well-funded startup backed by Mayfield and led by veterans who’ve built and scaled some of the most transformative technologies in the industry.\nThis isn’t incremental innovation, it’s a ground-floor opportunity to rethink the optical layer from the silicon up. The market is moving fast, and we’re moving faster. You’ll work alongside a team of world-class engineers solving some of the hardest challenges in optics, systems, and scale. Every line of code, every design decision, every breakthrough you help deliver will shape the infrastructure of tomorrow.\nIf you're looking for mission, momentum, and the chance to make an outsized impact, jump on the rocket ship. We’re just getting started.\nAbout the role. You will build the executable model of the chip before silicon exists. Your architecture models will settle the decisions that are expensive to change late, including datapath latency, throughput, buffer sizing, and control-loop tuning. Your reference models will become the golden checkers the verification team scores against, and the platform will run real firmware months ahead of RTL. This is a founding, critical-path role: the virtual platform is what unblocks the firmware and architecture work in parallel with design.\nWhat You'll Own\nA SystemC/TLM-2.0 virtual platform — MCU (ISS-backed) + peripherals + memory map + a UCIe transactor + host stub — that firmware runs on pre-RTL.\n\nArchitecture/performance models: architectural trade studies, end-to-end datapath throughput and latency, FIFO/buffer sizing, design-space/configuration exploration.\n\nGolden reference models handed to DV as scoreboards.\n\nBehavioral models of the analog and control circuits.\n\nPartner with the FE architect and firmware lead to keep model, RTL, and firmware views coherent.\n\nRequired\n8+ years in architecture/performance modelling or virtual-platform development for complex SoCs.\n\nStrong SystemC and TLM-2.0; solid modern C++.\n\nBuilt or led a virtual platform / ESL model that real firmware ran on for pre-silicon bring-up.\n\nIntegrating a third-party ISS (e.g., Arm or RISC-V) into a SystemC/TLM platform; modelling buses, memory maps, and peripherals.\n\nArchitecture/performance modelling judgment — knowing what to abstract versus model faithfully.\n\nComfortable spanning hardware micro-architecture and embedded software.\n\nPreferred\nFamiliarity with High-speed serial links and die-to-die / chiplet interconnects, and link-layer concepts such as FEC and equalization (e.g. PCIe, UALink, Ethernet or memory-semantic interconnects like CXL).\n\nExperience feeding golden models into a UVM/DV verification flow.\n\nModelling for mixed-signal or optical/SerDes systems, including control-loop / plant modelling.\n\nHigh-throughput datapath modelling.\n\nWhat We Offer\nCompetitive salary commensurate with experience\n\nComprehensive benefits package including health, dental, and vision\n\nProfessional development opportunities and certification support\n\nAccess to cutting-edge technology and cloud platforms\n\nCollaborative work environment with cross-functional teams\n\nLumilens is an equal opportunity employer. All qualified applicants will receive consideration without regard to race, color, religion, gender identity, sexual orientation, veteran status, disability, or any other legally protected status.", "jd_status": "stored"}, {"title": "Verification Lead (Lead DV) ", "company": "Lumilens", "location": "Bengaluru, India", "date_posted": "2026-06-24T20:25:53.869000+00:00", "url": "https://jobs.ashbyhq.com/lumilens/b6a08465-22c2-4df7-833f-db4d751568c0", "is_hardware": true, "platform": "ashby", "jd_text": "About Lumilens\nAt Lumilens we are building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new era of computing faster, cooler, and massively more efficient.\nWe’re a well-funded startup backed by Mayfield and led by veterans who’ve built and scaled some of the most transformative technologies in the industry.\nThis isn’t incremental innovation, it’s a ground-floor opportunity to rethink the optical layer from the silicon up. The market is moving fast, and we’re moving faster. You’ll work alongside a team of world-class engineers solving some of the hardest challenges in optics, systems, and scale. Every line of code, every design decision, every breakthrough you help deliver will shape the infrastructure of tomorrow.\nIf you're looking for mission, momentum, and the chance to make an outsized impact, jump on the rocket ship. We’re just getting started.\nAbout the Role\nYou own verification end to end for a first-of-its-kind chiplet. As a founding hire you define the methodology before there's RTL to verify — this role is on the critical path, and getting the coverage strategy and regression infrastructure right early is the single biggest schedule lever we have.\n \nWhat You'll Own\nThe full DV strategy: verification plan, coverage model (functional + code), UVM architecture, and signoff criteria from block to full-chip.\n\nStand up regression/CI infrastructure and nightly runs before design hands over first RTL.\n\nVerification of the in-house engines against an algorithmic golden model, with programmable error injection and error-pattern coverage.\n\nHardware-assisted verification: bring up and own the emulation / FPGA-prototyping methodology.\n\nUCIe VIP and compliance, link-training, loopback, lane-repair scenarios, bit-exact transparency and more.\n\nPerformance and throughput verification.\n\nUVM register verification, firmware co-simulation, and boot flows on the MCU subsystem.\n\nMixed-signal co-simulation — verifying the digital front end against behavioral models of analog/mixed-signal blocks.\n\nGate-level and low-power (UPF) verification as part of signoff.\n\nLead and grow the DV team (across FEC, UCIe, MCU, datapath, and full-chip).\n\nRequired\n10+ years ASIC/SoC verification, with team leadership on at least one complex SoC from plan to tapeout.\n\nProven leadership verifying large, complex digital SoCs / subsystems, including interconnect fabric and full-chip closure.\n\nDeep UVM/SystemVerilog; coverage-driven verification; constrained-random methodology.\n\nHands-on with hardware-assisted verification — emulation (e.g., Palladium/Veloce) and/or FPGA prototyping (e.g., HAPS/Protium).\n\nComfortable with mixed-signal verification (Verilog-AMS or SV real models).\n\nRegression/CI at scale (grid, triage automation), and rigorous coverage closure.\n\nPreferred\nHigh-speed SerDes, PAM4, or FEC/coding (Reed-Solomon) verification experience.\n\nUCIe, PCIe/CXL, Ethernet, UALink or comparable die-to-die / link-layer VIP and compliance experience.\n\nNIC Cards, Ethernet/IB Switches, Cache-coherency verification (multi-core / coherent fabric).\n\nLow-power/UPF and gate-level simulation methodology.\n\nPerformance-verification methodology.\n\nFormal verification for control/interlock logic; portable-stimulus.\n\nWhat We Offer\nCompetitive salary commensurate with experience\n\nComprehensive benefits package including health, dental, and vision\n\nProfessional development opportunities and certification support\n\nAccess to cutting-edge technology and cloud platforms\n\nCollaborative work environment with cross-functional teams\n\nLumilens is an equal opportunity employer. All qualified applicants will receive consideration without regard to race, color, religion, gender identity, sexual orientation, veteran status, disability, or any other legally protected status.", "jd_status": "stored"}, {"title": "Lead Performance Modeling Engineer – GPU SoC", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-06-24T09:30:00+00:00", "url": "https://global-external-amd.icims.com/jobs/87086/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Lead Performance Modeling Engineer – GPU SoC   The Role: Architect, Analyze and optimize high-performance SoCs for Cloud computing, and machine learning acceleration. Propose solutions to enhance performance and optimize power. Explore, analyze and optimize next-generation data center systems. The Person: Do you seek the most sophisticated challenges in the computing industry? As a passionate system performance architect on our design engineering team, you will propose and implement solutions to our next generation GPU SoC and data center system application performance issues. Key Responsibilities: Serve as a Performance Architect in AMD's electronics design engineering team. Participate in microarchitecture exploration, performance modeling, and analysis for next-generation GPU and data center systems. Intimately understand design architecture and propose solutions to enhance performance Responsible for micro-benchmarking, workload characterization, competitive analysis, bottleneck identification, and optimization. Develop tools and methodology for performance analysis of workloads. Communicate, propose, and implement solutions to processor and system performance issues. Preferred Experience: Experience with GPU, CPU or computer system microarchitecture Experience with the development and usage of computer system performance models Experience with computer workload analysis Strong programming skills, including experience with C++ and Python (or similar) Academic Credentials: Bachelors, Masters, or PhD degree in Electrical Engineer, Computer Engineering, Computer Science or a closely related field Masters or PhD with emphasis on Computer Architecture performance studies preferred #DC-GPU #LI-PK1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Soc Design Verification Director ", "company": "Astera Labs", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-06-24T08:27:38-04:00", "url": "https://job-boards.greenhouse.io/asteralabs/jobs/4703985005", "is_hardware": true, "platform": "greenhouse", "jd_text": "Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\n\n \n\nJob Title: Director of SoC Design Verification\n\nOverview\n\nWe are seeking a seasoned Director of SoC Design Verification with 20+ years of experience to lead verification for our next-generation System-on-Chip products. This is a hands-on leadership role where you will define the SoC-level verification strategy, oversee execution across multiple IPs and subsystems, and ensure first-pass silicon success for complex designs in compute, networking, and storage domains.\n\nKey Responsibilities\n\nOwn and drive the end-to-end SoC verification methodology, ensuring seamless integration of IP-level verification into system-level environments.\n\nLead, mentor, and grow a diverse team of engineers, fostering technical excellence, innovation, and collaboration.\n\nGuide verification of complex SoC subsystems including HSIO, peripherals, interconnects, memory controllers, coherency fabrics, and system-level protocols.\n\nChampion advanced methodologies (UVM, formal verification, emulation, AI-augmented flows) to accelerate coverage closure and improve efficiency.\n\nCollaborate closely with RTL design, architecture, firmware, and validation teams to debug, refine, and optimize SoC-level verification processes.\n\nRepresent verification in executive reviews, customer engagements, and industry forums.\n\nShape workforce transformation by building hybrid skill sets and preparing the team for AI-driven verification challenges.\n\nQualifications\n\nBachelor’s degree in Electrical or Computer Engineering (Master’s preferred).\n\n20+ years of experience in design verification, with a proven track record of leading teams and delivering complex SoC/silicon products.\n\nDeep expertise in SoC-level verification, including interconnect fabrics, coherency protocols, HSIO, and peripheral subsystems.\n\nStrong background in UVM-based test plan development, assertions, coverage analysis, and abstraction layer design.\n\nDemonstrated ability to manage priorities, engage with stakeholders, and drive organizational success.\n\nRequired Experience\n\nHands-on expertise with SoC-level verification environments, including integration of multiple IPs, HSIO, and peripherals.\n\nDeep experience in UVM-based test plan development, sequence generation, and coverage analysis.\n\nStrong background in writing assertions, cover properties, and analyzing coverage data at both IP and SoC levels.\n\nExperience in developing scalable verification infrastructures to simplify and accelerate SoC-level deployments.\n\nPreferred Experience\n\nExpertise in verifying complex SoC subsystems such as NoC-based interconnects, coherency fabrics, HSIO, and memory hierarchies.\n\nExperience with buffering, queuing, QoS, and system-level performance analysis.\n\nFamiliarity with emulation, FPGA prototyping, and hybrid verification flows.\n\nKnowledge of AI-driven verification methodologies and workforce transformation strategies.\n\nExperience with AI/ML accelerators, networking, automotive, data center, or high-performance computing SoCs.\n\nFamiliarity with low-power verification methodologies and power-aware verification.\n\n \n\nWhy Join Us?\n\nOpportunity to lead cutting-edge SoC development programs.\n\nInfluence verification strategy across next-generation products.\n\nBuild and grow a world-class verification organization.\n\nWork with highly talented engineering teams on innovative technologies.\n\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.", "jd_status": "stored"}, {"title": "ARM Server SoC Software & Firmware Systems Engineer (Sr. Staff / Principal)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-06-24T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446719135898", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Software Engineering\nGeneral Summary:\nOur Mission\nQualcomm is transforming the compute industry by delivering cloud-scale, production-ready ARM server platforms. We design server-class SoCs that integrate high-performance CPUs with advanced interconnects and a robust software stack—optimized for performance, reliability, security, and operational efficiency at hyperscale.\nOur charter is to deliver reference ARM server platforms based on Qualcomm server SoCs, spanning silicon enablement, firmware, OS and hypervisor integration, documentation, and ecosystem support for datacenter customers.\nJob Summary\nQualcomm is seeking a Sr. Staff / Principal level ARM Server SoC Software & Firmware Systems Engineer to act as a system-level technical leader for our next-generation ARM server platforms.\nThis role is a cross-disciplinary technical leadership position with responsibility for guiding end-to-end system architecture across silicon, firmware, OS, and platform software. You will align multiple engineering teams around architectural intent, guide critical design decisions, track execution across organizational boundaries, and ensure delivery meets production and hyperscale requirements.\nKey Responsibilities\nOwn and guide the system-level architecture for ARM server SoCs across hardware, firmware, OS, hypervisors, and platform services.\nOperate as a technical integrator across CPU, SoC, firmware, OS, performance, RAS, security, and platform teams.\nDefine and enforce clean cross-layer contracts (HW ↔ FW ↔ OS ↔ Hypervisor) using industry standards such as ACPI, PSCI, SBSA/SBBR, and SystemReady.\nProvide architectural leadership for boot flows, runtime firmware, power and performance management, RAS, security, virtualization, memory, PCIe, and telemetry.\nDrive alignment on architectural principles, tradeoffs, and design decisions across multiple teams without direct authority.\nIdentify architectural risks and cross-team dependencies early; guide execution and issue resolution to closure.\nReview designs and implementations to ensure adherence to architectural intent, scalability, and production-quality expectations.\nTranslate hyperscaler, customer, and ecosystem requirements into clear technical architecture and execution priorities.\nInfluence long-term platform and SoC roadmaps through system-level analysis and technical leadership.\nProduce high-quality architecture documentation, technical guidance, and executive-level summaries.\nMentor senior engineers and emerging architects across firmware and system software domains.\nMinimum Qualifications\n\nBachelor’s degree in Computer Science, Electrical Engineering, or a related field.\n12+ years of experience in system software, firmware, or SoC architecture for server or datacenter platforms.\nStrong understanding of ARM64 server architectures and system software stacks.\nBroad technical depth across firmware, OS, hypervisors, power/performance management, RAS, memory, PCIe, and platform services.\nDemonstrated experience leading large, cross-functional technical initiatives without direct reporting authority.\nProven ability to reason at system level and balance architectural rigor with execution realities.\nExcellent communication skills with the ability to engage engineering teams, senior leadership, and customers\nPreferred Qualifications\nMaster’s degree or equivalent industry experience.\n15+ years of experience delivering production server SoCs or hyperscale platforms.\nExperience working directly with hyperscaler customers or large datacenter operators.\nFamiliarity with ARM, OCP, or related industry standards bodies.\nDemonstrated success operating at Sr. Staff or Principal Engineer level, influencing architecture and execution across organizations\n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Software Engineering or related work experience.\n                                                                    OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Software Engineering or related work experience.\n                                                                    OR\nPhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Software Engineering or related work experience.\n\n•    3+ years of work experience with Programming Language such as C, C++, Java, Python, etc.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Principal Firmware Test Architect", "company": "NXP", "location": "Bangalore", "date_posted": "2026-06-24", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/NFC-Firmware-Senior-Architect_R-10063071", "is_hardware": true, "platform": "workday", "jd_text": "NFC‑based platforms are at the heart of secure connected experiences across mobile, wearables, automotive, and IoT ecosystems. They span domains such as wireless power transfer, secure NFC  transactions, digital wallets, infrastructure services, and platform enablement. As a Senior Firmware Test Architect in the NFC Firmware organization, you will play a critical role in defining, shaping, and delivering robust, scalable firmware architectures including test capabilities that operate close to silicon and enable product differentiation across multiple NFC use cases.\nThis role is intentionally broad and technology‑agnostic, allowing the architect to contribute across Wireless Charging (WLC), Wallet, Infrastructure, platform firmware, core libraries, validation, or system‑level enablement, depending on business needs and project priorities.\nWe are seeking a Senior Firmware Test Architect to lead the definition and execution of end-to-end validation strategy, test architecture, and automation frameworks for next-generation NFC platforms. This role is pivotal in ensuring product quality, scalability, and performance across complex embedded systems. \nYour Responsibilities:\nHe/She should work as NFC Firmware Test architect and drive end to end firmware validation strategy for new product development, debugging and maintenance of NXP's flagship embedded software for NFC products.\nDefine test methodology, coverage and quality metrics for unit, integration testing and compliance levels for firmware based on RISC V/ARM platform.\nDefine test requirements and test specifications.\nDrive test driven development across Firmware teams.\nArchitect and design scalable test frameworks, automation infrastructure, and validation environments.\nReview, approve code submitted by validation engineers and maintain overall quality of deliverables.\nClosely interact with Hardware Development team, system architects and other component technical experts with aim of improving SOC test capabilities.\nEffectively collaborate with partner companies and ensure product considers partner requirements and constraints.\nBuild and enhance automated test setups, validation labs, and tooling ecosystems\nMentor and guide validation engineers; establish best practices, processes, and standards\n\nYour Profile:\nMandatory:10-15 years of Embedded Firmware validation experience preferably in mobile or RTOS based embedded systems.\nBachelor’s or Master’s Degree in Electronics & Communication, Power Electronics, Computer Science from reputed institute with strong academic records.\nExperience of bare metal validation on embedded platform(8,16,32 bit platforms, preferably RISC V & ARM architecture)\nExcellent C programming skills and Python scripting for automation.\nExperience in debugging HW/FW/Silicon interfaces and failure analysis using Debuggers. (TRAC32/J-LINK/LPC-LINK)\nMust have experience in low level firmware programming embedded systems / low level Drivers such as boot loaders, SPI/I2C drivers, UART drivers, RF, embedded RTOS, etc.\nMust have exposure to RTL, FPGA, and silicon bring up experience.\nHands-on knowledge of RTOS, its concepts and usage.\nGood knowledge and experience of working on SOC HW IP datasheet, low level driver development, etc.\nExposure to IDEs like LPCXpresso, Keil, Eclipse\nExposure to change management / configuration management, bug tracking tools.\nHands-on with AI based efficiency gaining tools.\nExperience in building test frameworks, automation platforms, and validation infrastructure\nMust have knowledge of at least one RF connectivity technology like NFC, WiFi, UWB, Zigbee, LoRa, BLE, etc.\n\nOptionalExposure to Jenkins is an added advantage\nGood understanding of NFC technology.\n\nPersonalityExcellent analytical, problem solving, debugging skills & influencing skills with go-to attitude\nSelf-motivated, Proactive, good verbal and written communication.\nSufficiently mobile and flexible, work location based out of Bangalore\nExperienced in requirements derivation, proposing Low level / High level design (besides coding) in the above-mentioned domains\nEmpathic communicator, able to see things from the other person's point of view and a good team player with cross functional, cross cultural & Global teams\n\nDesired Skill Set\nKnowledge of software development life cycle (SDLC) for embedded firmware development\nKnowledge of Embedded platforms and working closely with Hardware teams is preferred\nKnow-how of smart card Contact less Proximity Standards such as ISO14443, ISO15693, ISO18092, ISO7816 etc.\nNear Field Communication Standards.\nWilling to travel to other countries on need basis\n\nMore information about NXP in India...\n\n#LI-29f4", "jd_status": "stored"}, {"title": "Staff Electrical Engineer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-06-24", "url": "https://careers.skyworksinc.com/job-invite/77669/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 77669\n\nDescription\n\nIf you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high-performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking.  Our work culture values diversity, social responsibility, open communication, mutual trust and respect. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nResponsibilities\n\nWork with a dedicated team, verifying analog and mixed-signal building blocks for SOCs, with a focus on the portable, ultra-low power audio markets.\n\nParticipate in all aspects of the mixed-signal design verification, in partnership with the design engineering team, to develop and implement a mixed-signal verification infrastructure to verify all functional and performance requirements. \n\nRequired Experience and Skills\n\n8+ years (BSEE) or 8+ years (MSEE) or 3+ years (PhD) of relevant industry experience\n\nInsatiable curiosity to learn about new circuit architectures to advance ultra-low power audio devices\n\nA keen understanding of modern mixed-signal verification challenges and solutions.\n\nSolid foundation in network theory, amplifier design and data converters.\n\nExperience developing RNM behavioral models using System Verilog/VerilogAMS for analog blocks like analog/digital PLLs, ADCs, DACs, LDOs.\n\nExperience developing and maintaining chip level performance simulations of mixed-signal SOC designs.\n\nAbility to create and maintained mixed signal verification plans based on early system specifications or incomplete design definitions.\n\nCompetent in the Cadence Virtuoso environment to setup and execute parameterized simulations of analog and SOC designs.\n\nExperienced in producing detailed technical reports and documentation.\n\nExperienced in Low-power audio amplifiers (Class D), audio converters, audio interfaces (I2S, PDM), and audio performance metrics (Dynamic Range, SNR, THD) is highly preferred.\n\nExperienced in Flow automation using command line scripts using Python, Matlab, Ocean, Perl, Csh, Make, etc.\n\nSimulation performance and accuracy trade-offs based on design requirements\n\nExperienced in Power-aware mixed-signal verification\n\nHands-on verification of sub-45nm CMOS SOC designs\n\n \n\n#LI-CB1\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Staff Electrical Engineer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-06-24", "url": "https://careers.skyworksinc.com/job-invite/77670/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 77670\n\nDescription\n\nIf you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high-performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking.  Our work culture values diversity, social responsibility, open communication, mutual trust and respect. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nResponsibilities\n\nWork with a dedicated team of engineers, using the latest verification practices, to verify the digital design intent of our SOC's at the block and system level. \n\nEngage early in the verification process to understand the verification requirements and participate in UVM or SystemVerilog testbench development. \n\nResponsible for creating tests to verify the SOC design at the system or block level and to implement checking mechanisms to ensure coverage closure.\n\nRequired Experience and Skills\n\n8+ years (BSEE), 6+ years (MSEE), or 3+ years (PhD) of relevant industry experience\n\nExpertise in developing testbenches using System Verilog and UVM\n\nExperience using directed and constrained-random test methodologies, coverage closure and gate-level simulations\n\nStrong object-oriented programming knowledge using SystemVerilog\n\nStrong problem-solving and debug skills capable of isolating problems to the block level\n\nExpertise in developing test plans, implementing coverage models, and analyzing results\n\nExperience in the use of scripts to support automation (Python, Make, Csh, Bash, Tcl, etc)\n\nFamiliarity with C-code/embedded firmware/debuggers\n\nAbility to work in a dynamic environment with changing needs and requirements\n\n \n\n#LI-CB1\n\nDesired Experience and Skills\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Sr. Electrical Engineer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-06-24", "url": "https://careers.skyworksinc.com/job-invite/77675/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 77675\n\nDescription\n\nIf you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high-performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking.  Our work culture values diversity, social responsibility, open communication, mutual trust and respect. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nResponsibilities\n\nWork with a dedicated team, verifying analog and mixed-signal building blocks for SOCs, with a focus on the portable, ultra-low power audio markets.\n\nParticipate in all aspects of the mixed-signal design verification, in partnership with the design engineering team, to develop and implement a mixed-signal verification infrastructure to verify all functional and performance requirements. \n\nRequired Experience and Skills\n\n6+ years (BSEE) or 4+ years (MSEE) or 3+ years (PhD) of relevant industry experience\n\nInsatiable curiosity to learn about new circuit architectures to advance ultra-low power audio devices\n\nA keen understanding of modern mixed-signal verification challenges and solutions.\n\nSolid foundation in network theory, amplifier design and data converters.\n\nExperience developing RNM behavioral models using System Verilog/VerilogAMS for analog blocks like analog/digital PLLs, ADCs, DACs, LDOs.\n\nExperience developing and maintaining chip level performance simulations of mixed-signal SOC designs.\n\nAbility to create and maintained mixed signal verification plans based on early system specifications or incomplete design definitions.\n\nCompetent in the Cadence Virtuoso environment to setup and execute parameterized simulations of analog and SOC designs.\n\nExperienced in producing detailed technical reports and documentation.\n\nExperienced in Low-power audio amplifiers (Class D), audio converters, audio interfaces (I2S, PDM), and audio performance metrics (Dynamic Range, SNR, THD) is highly preferred.\n\nExperienced in Flow automation using command line scripts using Python, Matlab, Ocean, Perl, Csh, Make, etc.\n\nSimulation performance and accuracy trade-offs based on design requirements\n\nExperienced in Power-aware mixed-signal verification\n\nHands-on verification of sub-45nm CMOS SOC designs\n\n \n\n#LI-CB1\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Sr. Electrical Engineer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-06-24", "url": "https://careers.skyworksinc.com/job-invite/77674/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 77674\n\nDescription\n\nIf you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high-performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking.  Our work culture values diversity, social responsibility, open communication, mutual trust and respect. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nResponsibilities\n\nWork with a dedicated team of engineers, using the latest verification practices, to verify the digital design intent of our SOC's at the block and system level. \n\nEngage early in the verification process to understand the verification requirements and participate in UVM or SystemVerilog testbench development. \n\nResponsible for creating tests to verify the SOC design at the system or block level and to implement checking mechanisms to ensure coverage closure.\n\nRequired Experience and Skills\n\n6+ years (BSEE), 4+ years (MSEE), or 3+ years (PhD) of relevant industry experience\n\nExpertise in developing testbenches using System Verilog and UVM\n\nExperience using directed and constrained-random test methodologies, coverage closure and gate-level simulations\n\nStrong object-oriented programming knowledge using SystemVerilog\n\nStrong problem-solving and debug skills capable of isolating problems to the block level\n\nExpertise in developing test plans, implementing coverage models, and analyzing results\n\nExperience in the use of scripts to support automation (Python, Make, Csh, Bash, Tcl, etc)\n\nFamiliarity with C-code/embedded firmware/debuggers\n\nAbility to work in a dynamic environment with changing needs and requirements\n\n \n\n#LI-CB1\n\nDesired Experience and Skills\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Tapeout Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-06-24", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25011383", "is_hardware": true, "platform": "oracle", "jd_text": "About the team\n\nThis position is on TI’s Advanced Technology Development (ATD) Mask Technology and Pattern Generation (MTPG) team.\n\nWe support mask building, reticle generation, scribe array generation, layout generation & verification methodologies. \n\n \n\nTapeout Engineer \n\n \n\nSeeking motivated Tapeout engineer \n\n \n\nSupporting product and test chip PG’s across various technologies at TI\n\n \n\nJob description:\n\nConversion of product or technology development test chip layouts (LAFF, GDS) into fracture data \n\nPreparing mask orders for shipment to vendors and managing the integrity and archival of data that is generated through this process. (Mask Data Preparation)\n\ngenerate reticle floorplan databases\n\nDrive automations for use in the PG/Tapeout process.\n\nCollaborate with & guide various teams within Advanced Technology Development (process development, PDK), EDA and business units to ensure the necessary information is available to complete the PG process.\n\nEnsure consistent application of methodologies and best practices\n\nQualifications\nRequired Key Skills\n\n \n\nUnderstanding of Layout and basics of fabrication process (FEOL/BEOL) \n\nKnowledge of Mask data tools like Cadence Virtuoso, (Pegasus designrev / Mentor calibredrv \n\nMaintain a high standard for cycle time and quality\n\n \n\nEducational Qualifications\n\n \n\nBachelors / Master’s degree in Computer Science, Electrical/Electronic Engineering or related field with (2-5) years of Hardware Engineering or related work experience.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Sr. Electrical Engineer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-06-24", "url": "https://careers.skyworksinc.com/job-invite/77673/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 77673\n\nDescription\n\nIf you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high-performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking.  Our work culture values diversity, social responsibility, open communication, mutual trust and respect. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nResponsibilities\n\nWork with a dedicated team of engineers, using the latest verification practices, to verify the digital design intent of our SOC's at the block and system level. \n\nEngage early in the verification process to understand the verification requirements and participate in UVM or SystemVerilog testbench development. \n\nResponsible for creating tests to verify the SOC design at the system or block level and to implement checking mechanisms to ensure coverage closure.\n\nRequired Experience and Skills\n\n6+ years (BSEE), 4+ years (MSEE), or 3+ years (PhD) of relevant industry experience\n\nExpertise in developing testbenches using System Verilog and UVM\n\nExperience using directed and constrained-random test methodologies, coverage closure and gate-level simulations\n\nStrong object-oriented programming knowledge using SystemVerilog\n\nStrong problem-solving and debug skills capable of isolating problems to the block level\n\nExpertise in developing test plans, implementing coverage models, and analyzing results\n\nExperience in the use of scripts to support automation (Python, Make, Csh, Bash, Tcl, etc)\n\nFamiliarity with C-code/embedded firmware/debuggers\n\nAbility to work in a dynamic environment with changing needs and requirements\n\n \n\n#LI-CB1\n\nDesired Experience and Skills\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Staff Electrical Engineer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-06-24", "url": "https://careers.skyworksinc.com/job-invite/77672/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 77672\n\nDescription\n\nIf you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high-performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking.  Our work culture values diversity, social responsibility, open communication, mutual trust and respect. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nResponsibilities\n\nWork with a dedicated team of engineers, using the latest verification practices, to verify the digital design intent of our SOC's at the block and system level. \n\nEngage early in the verification process to understand the verification requirements and participate in UVM or SystemVerilog testbench development. \n\nResponsible for creating tests to verify the SOC design at the system or block level and to implement checking mechanisms to ensure coverage closure.\n\nRequired Experience and Skills\n\n8+ years (BSEE), 6+ years (MSEE), or 3+ years (PhD) of relevant industry experience\n\nExpertise in developing testbenches using System Verilog and UVM\n\nExperience using directed and constrained-random test methodologies, coverage closure and gate-level simulations\n\nStrong object-oriented programming knowledge using SystemVerilog\n\nStrong problem-solving and debug skills capable of isolating problems to the block level\n\nExpertise in developing test plans, implementing coverage models, and analyzing results\n\nExperience in the use of scripts to support automation (Python, Make, Csh, Bash, Tcl, etc)\n\nFamiliarity with C-code/embedded firmware/debuggers\n\nAbility to work in a dynamic environment with changing needs and requirements\n\n \n\n#LI-CB1\n\nDesired Experience and Skills\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Staff Analog Design Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-06-23T06:15:16.471000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000133511174-staff-analog-design-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Looking for a 7+ years experienced Engineer with good understanding of Analog concepts, experience of from scratch design of key analog blocks, integrating smaller blocks to create functional I/Ps and full ownership of those, ICs and well versed with Transistor level design flow, to join the 2.6B$ Power Business Unit. The candidate will get to work on a wide range of exciting products such as PMICs, Linear and Switching DC-DC converters powering the next generation of most sought-after phones and hand held devices. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas’s massive Power product portfolio.\nEssential Functions:\nMust be proficient in designing and owning key analog blocks including Bangdap references, Analog Buffers, Op-Amps, Comparators, High speed level shifters etc.\nMust be able to come up with architectures to meet block level performance specifications.\nMust be well versed of the standard architectures and be able to bring in innovative ideas to improve designs to meet challenging specifications.\nShould have clear understanding of analog layouts and should be able to work closely with and guide layout engineers to ensure quality layout to meet the desired performance.\nMust be conversant with the standard design, extraction and simulation flows & tools, speed, convergence, accuracy trade-offs and should be able to optimize setups based on Pre/Post (with/without) Parasitic using simulator options, debug and navigate through tool related challenges.\nShould be able to mentor Freshers and Junior engineers for upscaling their technical skills as well as other skills needed for better efficacy.\nShould be able to develop multiple blocks with minimal supervision, take full ownership to drive all aspects within committed schedule and work closely with Sr members of Design team to support them build subsystem/chip top.\nExperience of silicon validation and debug is a strong advantage.\nShould have good understanding of ESD and be able to design the I/O ring for the IC\n\nMinimum Requirements:\nBachelor’s or Master’s degree in Electrical Engineering\n7+ years in Analog Circuit Design, Simulation and Verification\nSolid understanding of analog designs and proven experience of block designs with full ownership.\nSchematic generation, simulation and verification using modern CAD tools\nDesign & verification experience of simple analog blocks, Monte Carlo analysis using industry standard CAD tools\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Design Implementation - Synthesis Principal Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-06-23T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718316815", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nMinimum Qualifications\n\no 18+ Year of industry experiences in the following areas: Expertise in Synthesis - Synopsys Design Compiler, DCG/DC_NXT/Fusion Compiler and/or Cadence RC/Genus.\no Expertise on with multi-voltage, power aware synthesis, UPF flows in synthesis and low power designs.\no Expertise in formal verification with Cadence LEC/ Synopsys Formality\no Expertise in writing and debugging timing constraints\no Perl and/or TCL scripting, makefile flows.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n\nMasters in Electronics or Electrical Engineering\n\nwork on integration or RTL design is considered plus.\n\nCandidates should have excellent analytical and problem-solving skills\n\nTrack record of driving ideas from design through commercialization  \n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Principal Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-06-23", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Design-Engineer_R54817-1", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nB.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or related field\n7–10 years of hands-on DV experience in semiconductor/ASIC/SoC companies\nDeep expertise in SystemVerilog and UVM (Universal Verification Methodology)\nStrong understanding of digital design fundamentals — RTL, timing, clocking, resets\nExperience with industry-standard simulators: Xcelium, VCS, Questa\nProficiency in coverage-driven verification — functional, code, and toggle coverage\nHands-on experience with formal verification tools and flows\nExperience with bus protocols such as AXI, AHB, APB, PCIe, DDR, or similar\nStrong debug skills — waveform analysis (Verisium, SimVision)\nFamiliarity with low-power verification (UPF/CPF) and gls/power-aware gls simulation\n \nCore Responsibilities\n\nStrategy and Architecture\nVerification Planning: Define the overall verification strategy, including the choice of methodology (typically UVM/SystemVerilog), tools, and infrastructure.\nTestbench Architecture: Design scalable, reusable, and robust verification environments. This includes developing Bus Functional Models (BFMs), monitors, scoreboards, and checkers.\nFeature Extraction: Analyze architectural specifications to identify critical features and corner cases that require rigorous testing.\n\nExecution and Technical Leadership\nCustomer Interaction: Technically lead DV execution of small to mid-sized customer ASIC projects. Handle customer interactions. Convert high level customer requirements into DV execution plan.   \nDevelopment: Write complex test cases and sequences to achieve high functional coverage.\nDebug: Lead the root-cause analysis of complex design bugs, collaborating closely with design engineers to implement fixes.\nConstraint Random Testing: Implement constrained-random stimulus generation to explore the design space beyond directed tests.\nFormal Verification: Utilize formal tools to prove specific properties or find deep-seated bugs that simulation might miss.\n\nMetric Management\nCoverage Analysis: Monitor and analyze functional and code coverage metrics.\nGate-Level Simulation (GLS): Oversee simulations on the synthesized netlist to verify timing and reset behavior.\nSign-off: Define the \"definition of done\" and provide final technical approval for the verification phase.\n\nSoft Skills and Leadership\nMentorship: Guiding junior engineers on coding standards and debugging techniques.\nCross-functional Collaboration: Acting as the primary technical point of contact between the design, architecture, and emulation teams.\nProject Management: Managing timelines, identifying risks in the verification schedule, and prioritizing tasks to meet project deadlines.\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Lead Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-06-23", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Design-Engineer_R54815-1", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nCore Responsibilities\n1. Strategy and Architecture\nVerification Planning: Define the overall verification strategy, including the choice of methodology (typically UVM/SystemVerilog), tools, and infrastructure.\nTestbench Architecture: Design scalable, reusable, and robust verification environments. This includes developing Bus Functional Models (BFMs), monitors, scoreboards, and checkers.\nFeature Extraction: Analyze architectural specifications to identify critical features and corner cases that require rigorous testing.\n2. Execution and Technical Leadership\nDevelopment: Write complex test cases and sequences to achieve high functional coverage.\nDebug: Lead the root-cause analysis of complex design bugs, collaborating closely with design engineers to implement fixes.\nConstraint Random Testing: Implement constrained-random stimulus generation to explore the design space beyond directed tests.\nFormal Verification: Utilize formal tools to prove specific properties or find deep-seated bugs that simulation might miss.\n3. Metric Management\nCoverage Analysis: Monitor and analyze functional and code coverage metrics.\nGate-Level Simulation (GLS): Oversee simulations on the synthesized netlist to verify timing and reset behavior.\nSign-off: Define the \"definition of done\" and provide final technical approval for the verification phase.\nSoft Skills and Leadership\nMentorship: Guiding junior engineers on coding standards and debugging techniques.\nCross-functional Collaboration: Acting as the primary technical point of contact between the design, architecture, and emulation teams.\nProject Management: Managing timelines, identifying risks in the verification schedule, and prioritizing tasks to meet project deadlines.\nRequired Qualifications\nB.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or related field\n4–6 years of hands-on DV experience in semiconductor/ASIC/SoC companies\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "ASIC Design/Verification, Architect", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-06-23", "url": "https://careers.synopsys.com/job/bengaluru/asic-design-verification-architect/44408/94524277376", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nAn experienced and highly skilled ASIC Digital Verification Engineer with a passion for ensuring the highest quality in digital design. You have a deep understanding of verification methodologies and are proficient in using advanced verification tools and techniques. Your expertise allows you to work independently, taking on complex challenges and delivering innovative solutions. You are detail-oriented, with a strong analytical mindset, and can communicate effectively with various stakeholders. Your ability to mentor and lead junior engineers is a testament to your extensive experience in the field. You thrive in a collaborative environment and are committed to continuous learning and improvement.\nWhat You’ll Be Doing:\nDesigning, implementing and optimizing verification environments to ensure the correctness of Interface IP protocols.\nCreating, executing and tracking against detailed test plans to verify complex ASIC designs.\nDeveloping and maintaining verification IP and testbenches using System Verilog and UVM.\nCollaborating with design and architecture teams identifying fix bugs.\nPerforming functional coverage analysis and driving coverage closure.\nMentoring and guiding junior verification engineers in best practices and methodologies.\nThe Impact You Will Have:\nEnsuring the delivery of high-quality, reliable ASIC designs that meet customer specifications.\nEnhancing the robustness and efficiency of our verification processes and methodologies.\nContributing to the successful launch of Interface IP products, impacting various industries.\nDriving innovation and excellence within the verification team.\nImproving the overall performance and functionality of Synopsys' IP offerings.\nFostering a culture of continuous improvement and technical excellence.\nWhat You’ll Need:\n\nExtensive experience in ASIC digital verification, specifically with Interface IP protocols, such as PCIe, CXL, DDR, Ethernet, AMBA (CHI, AXI, AHB, APB).\nProficiency in System Verilog, SVA and UVM methodologies.\nStrong understanding of digital design and verification concepts.\nFamiliarity with wider digital ASIC and IP development flow, including RTL design through synthesis.\nExperience with simulation tools such as VCS, Model Sim, or similar.\nStrong analytical and problem-solving skills, with the ability to tackle complex and unique design challenges.\nExcellent communication skills, with the ability to effectively collaborate with cross-functional teams and stakeholders.\nWho You Are:\nDetail-oriented with a strong analytical mindset.\nExcellent communicator, able to convey complex technical concepts clearly.\nCollaborative team player who thrives in a dynamic environment.\nProactive and self-motivated, with a commitment to continuous learning.\nMentor and leader, capable of guiding and developing junior engineers.\nThe Team You’ll Be A Part Of:\nYou will be part of a highly skilled and motivated verification team focused on delivering cutting-edge Interface IP solutions. The team is dedicated to maintaining the highest standards of quality and performance, working collaboratively to tackle complex verification challenges. You will have the opportunity to work alongside industry experts and contribute to the development of next-generation technologies.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Staff Engineer, QNX Driver and middleware, SoC Automotive Embedded SW", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-06-22T11:46:29.119000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000133342109-staff-engineer-qnx-driver-and-middleware-soc-automotive-embedded-sw", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Job profile – QNX Developer for middleware and frameworks for Automotive SoCs. \nYou will develop highly optimized software architecture for Renesas R-Car Gen5 series devices. Strong working knowledge of QNX FreeRTOS environment for multi-core heterogenous SoCs is a key requirement. You will implement requirements for the next-generation IVI/ADAS products that comprise tools, software, and hardware. Your main responsibilities will be in the following areas: \nRelevant working experience \nQNX \nWorking knowledge developing drivers, middleware and applications for QNX \n\nHands on debugging using standard QNX tools and debuggers such as Lauterbach. \n\nFamiliarity with QNX build system. \n\nCamera pipeline \nHands on knowledge on camera bring up  \n\nDriver development for camera pipeline \n\nCamera frameworks and ISP \n\nDeveloping camera based applications with AI \nPrimarily with QNX \n\nSystem integration with QNX camera frameworks \n\nSystem tuning (boot time, QoS) \n\nHypervisor  \nWorking knowledge with QNX Hypervisor may be an added advantage \n\nWorking knowledge of SMMU and virtualization approaches. \n\nDomains/Peripherals \nRealization of ADAS/IVI usecases on any heterogeneous platform. \n\nOverall automotive system knowledge. \n\nTools \nGit/Gerrit \n\nPerformance optimization tools  \n\nHands on debugging expertise on heterogeneous SoC environments \n\nEducation and Background: \nBachelors or Masters graduate (Electronics or Computer Science) \n\nOver 6+ years of embedded SW development on QNX/Linux/Android/Zephyr/FreeRTOS \n\nRelevant Experiences (Combination of good-to-have and must-have): \nRelevant industry experience in embedded software development with a proven track record in translating complex use cases requirements into design, system specifications, standards, and software solutions.  \nAbility to work independently with strong motivation towards meeting deadlines with efficiency and focus \n\nArchitecture \n\nSystem architecture experience for heterogeneous / multi-core embedded SoC computing platforms. \n\nDevelopment \n\nEmbedded system software development experience including low level firmware, kernel, and user space components on an SoC product comparable to the Renesas R-Car family \n\nAbility to develop and debug on both real hardware as well as simulation and emulation environments \n\nDebug:  \n\nAbility to debug complex system level use cases involving hardware and software elements such as bandwidth/QoS knobs. \n\nSoftware debugging including CLI, PCB, and application level debug techniques  \n\nAbility to debug high speed communication interfaces including HW/SW co-debug \n\nCollaboration: \n\nAbility to collaborate with sales, marketing, architecture, customer, partners, and other groups to create best in class reference solutions, solve problems, and enable customer success  \n\nAbility to expand upon existing solutions in collaboration with architects and prior design teams \n\nAbility to work independently as well as in small teams \n\nCommunication: \n\nExcellent written and verbal communication due to frequent customer and internal communications; ability to provide direct, efficient, and clear customer communications under pressure \n\nFamiliarity with global business cultures (Japan, Europe, US, India) and strong cross cultural sensitivity \n\nFamiliarity with verbal and written Japanese (nice to have) \n\nTravel: \n\nFlexibility to manage occasional international travel on short notice to support customer success or internal initiatives \n\nAdditional notes: \nLocation : Bangalore \n\n​Reporting to Senior Manager of Engineering \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "(India) System IP Design Engineer", "company": "Tenstorrent", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-06-22T05:00:00-04:00", "url": "https://job-boards.greenhouse.io/tenstorrent/jobs/5164498007", "is_hardware": true, "platform": "greenhouse", "jd_text": "Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.\n\nWe’re looking for a hands-on RTL Design Engineer to own the microarchitecture and RTL implementation of the Power Management Subsystem/Interrupt Controllers/AXI Interconnect/Cache Controller. You’ll collaborate with cross-functional teams—architecture, firmware, software, DV, and PD—to define, design, and optimize power management solutions for next-generation RISC-V/ARM-based SoCs.\n\nThis role is hybrid, based out of Bangalore, India.\n\nWe welcome candidates at various experience levels. During the interview process, you will beevaluated and offered a level that aligns with your experience, which may differ from the one in this posting.\n\n \n\nWho You Are\n\n5–10 years of experience in ASIC/SOC/IP design, with hands-on experience in microarchitecture and RTL development\n\nSkilled in Verilog/SystemVerilog and comfortable working across design, debug, and analysis\n\nDesign and develop microarchitectures for a set of highly configurable IPs\n\nMicroarchitecture and RTL coding ensuring optimal performance, power, area\n\nWork with verification teams on assertions, test plans, debug, coverage, etc.\n\nDeep understanding of power management concepts—clocking, reset, DVFS, and low-power modes\n\nFamiliar with RISC-V or ARM-based SoCs and standard bus protocols (AXI, AHB, APB, CHI)\n\nAwareness of functional safety (ISO 26262) practices in hardware design\n\nWhat We Need\n\nAbility to own microarchitecture definition and RTL development of Power Management Subsystem/Interrupt Controllers/AXI Interconnect/Cache Controller\n\nExperience driving verification closure, performance debug, synthesis, timing, and power optimization\n\nExperience with large high-speed, pipelined, stateful designs, and low power designs\n\nIn-depth understanding of on-chip interconnects and NoC's\n\nExperience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and NoC's\n\nFamiliarity with RAS designs, QoS in fabrics, PCIe/IO is a plus\n\nExcellent problem-solving skills and attention to detail\n\nStrong communication and collaboration skills\n\nStrong skills in LINT, CDC/RDC, and power intent checks\n\nProficiency with DV and analysis tools like Verdi, NCSIM, and power estimation tools\n\nHands-on experience in design-for-power, debug, and test methodologies\n\nWhat You Will Learn\n\nBuilding power-efficient, high-performance subsystems for advanced RISC-V/ARM architectures\n\nCross-functional collaboration from concept to silicon bring-up\n\nEnhancing subsystem performance through innovative power, performance, and area optimizations\n\nLeadership and mentorship experience by guiding junior design engineers.\n\n \n\nTenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.\nThis offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.  Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).   These requirements apply to persons located in the U.S. and all countries outside the U.S.  As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.  If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.", "jd_status": "stored"}, {"title": "Principal Digital IP Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-06-22", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Digital-IP-Engineer_R-10063817", "is_hardware": true, "platform": "workday", "jd_text": "In this role, you will be responsible for developing high-quality, reusable IPs for SoC/subsystem integration and driving designs from concept through silicon. This position offers an opportunity to work on cutting-edge semiconductor technologies and collaborate with global cross-functional teams.\n\nKey responsibilities\nWork with architecture teams and put up the micro-architecture based on the IP requirements\nDevelop RTL using Verilog/SystemVerilog/VHDL based on micro-architectural specifications\nTranslate system-level requirements into high-quality IP designs\nOptimize designs for power, performance, and area\nPerform design checks such as Lint, CDC, synthesis, and STA\nDrive bug fixing and closure\nSupport design reviews and sign-off processes\nCollaborate with verification teams on test plans and coverage closure\n\nRequired skills\nStrong experience in RTL design (Verilog/SystemVerilog/VHDL)\nSolid understanding of SoC/IP design and integration\nHands-on experience with:Lint, CDC, synthesis, timing analysis\nExperience in Low-power design techniques\n\nPreferred skills\nExperience in full-cycle IP/SoC development\nExposure to formal verification or low-power flows\nExperience with post-silicon validation and bring-up\n \n\nMore information about NXP in India...\n\n#LI-29f4", "jd_status": "stored"}, {"title": "Principal Digital IP Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-06-22", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Digital-IP-Engineer_R-10063816", "is_hardware": true, "platform": "workday", "jd_text": "In this role, you will be responsible for developing high-quality, reusable IPs for SoC/subsystem integration and driving designs from concept through silicon. This position offers an opportunity to work on cutting-edge semiconductor technologies and collaborate with global cross-functional teams.\n\nKey responsibilities\nWork with architecture teams and put up the micro-architecture based on the IP requirements\nDevelop RTL using Verilog/SystemVerilog/VHDL based on micro-architectural specifications\nTranslate system-level requirements into high-quality IP designs\nOptimize designs for power, performance, and area\nPerform design checks such as Lint, CDC, synthesis, and STA\nDrive bug fixing and closure\nSupport design reviews and sign-off processes\nCollaborate with verification teams on test plans and coverage closure\nRequired skills\nStrong experience in RTL design (Verilog/SystemVerilog/VHDL)\nSolid understanding of SoC/IP design and integration\nHands-on experience with:Lint, CDC, synthesis, timing analysis\nExperience in Low-power design techniques\n\nPreferred skills\nExperience in full-cycle IP/SoC development\nExposure to formal verification or low-power flows\nExperience with post-silicon validation and bring-up\n \n\nMore information about NXP in India...\n\n#LI-29f4", "jd_status": "stored"}, {"title": "Sr.Principal Digital IP Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-06-22", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/IP-Design-Engineer_R-10063815", "is_hardware": true, "platform": "workday", "jd_text": "In this role, you will be responsible for developing high-quality, reusable IPs for SoC/subsystem integration and driving designs from concept through silicon. This position offers an opportunity to work on cutting-edge semiconductor technologies and collaborate with global cross-functional teams.\n\nKey responsibilities\nWork with architecture teams and put up the micro-architecture based on the IP requirements\nDevelop RTL using Verilog/SystemVerilog/VHDL based on micro-architectural specifications\nOptimize designs for power, performance, and area\nPerform design checks such as Lint, CDC, synthesis, and STA\nDrive bug fixing and closure\nSupport design reviews and sign-off processes\nCollaborate with verification teams on test plans and coverage closure\n\nRequired skills\nStrong experience in RTL design (Verilog/SystemVerilog/VHDL)\nSolid understanding of SoC/IP design and integration\nHands-on experience with:Lint, CDC, synthesis, timing analysis\nExperience in Low-power design techniques\n\nPreferred skills\nExperience in full-cycle IP/SoC development\nExposure to formal verification or low-power flows\nExperience with post-silicon validation and bring-up\n \n\nMore information about NXP in India...\n\n#LI-29f4", "jd_status": "stored"}, {"title": "Principal DFT Engineer", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-06-22", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Principal-DFT-Engineer_R256070", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nJob Description: Principal Digital DFT Engineer\nRole Summary\nThe Principal Digital DFT Engineer is responsible for architecting, implementing, and verifying advanced DFT solutions for complex digital ASICs and SoCs. This position emphasizes direct technical execution, deep problem-solving, and ownership of DFT flows for robust testability and manufacturing yield.\nKey Responsibilities\nOwn and drive all aspects of DFT architecture, definition, and implementation for digital chips, including scan insertion, ATPG, boundary scan, MBIST, logic BIST, JTAG and test compression techniques.\nHands-on execution with EDA tools for scan synthesis, test pattern generation, fault simulation, and DFT rule checks.\nCreate and validate test plans targeting high coverage for stuck-at, transition, and critical path faults.\nIntegrate DFT with RTL and physical design teams; resolve complex trade-offs impacting fault coverage, PPA, or manufacturability.\nOptimize test modes, design for manufacturability, and debug silicon failures from bring-up through production ramp.\nDevelop and implement low-overhead test structures and warranty schemes for new and legacy IP.\nDirectly debug, analyze, and resolve DFT-related issues in simulation, emulation, and in the lab using standard test equipment.\nDeliver documented DFT architectures, test strategies, implementation scripts (TCL/Python/Perl), and design guidelines for engineering teams.\nCollaborate with ATE test engineers to implement production test solutions, reduce test costs, and improve coverage.\nMentor engineers in DFT methodology, best practices, tool usage, and industry standards.\nRequired Qualifications\nBachelor’s or Master’s degree in Electrical/Electronics/VLSI Engineering or equivalent.\n10+ years’ proven hands-on experience in DFT for digital ASIC/SoC development, with multiple tapeouts for large designs.\nExpert skills in DFT flows: scan, ATPG, MBIST, BIST, JTAG, boundary scan, fault simulation.\nStrong command of EDA tools: Synopsys DFT Compiler, Tessent, Cadence Modus, or equivalent.\nScripting abilities (TCL, Python, Perl) for DFT automation and reporting.\nSolid knowledge of RTL design, synthesis, timing, and SoC architecture constraints.\nDemonstrated ability to debug complex DFT and test-mode issues at lab and production level.\nAbility to create technical documentation, guides, and mentor junior engineers.\nNice-to-Have Skills\nExperience with DFT for advanced nodes (≤ 7nm), 2.5D/3D packaging, or high-speed IP.\nProduction ATE pattern development and test data evaluation.\nKnowledge of safety (ISO 26262) or security-oriented DFT requirements.\nDFT for memory BIST (SRAM/DRAM), and custom macro testing.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Sr. Principal Layout Designer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-06-22", "url": "https://careers.skyworksinc.com/job-invite/77817/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 77817\n\nJob Description\n\nSeeking a Principal Layout Designer responsible for the layout of Analog integrated circuits, utilizing commercial/standard bulk CMOS and SOI technologies in accordance with design rules.\n\nIn this role you will be working closely with design engineers in the layout and verification of analog and integrated circuits for wireless consumer electronic products using the Cadence Design environment and Calibre verification tools. \n\nDesigner will participate in all aspects of project management, including, project planning, working with engineers to identify scope of project, validating designs, deliverables, and creation of manufacturing and assembly documentation within the required cycle time per company and program requirements.\n\nPosition requires remote interfacing with domestic and international design engineering and layout teams in multiple design centers across multiple time zones. \n\nResponsibilities\n\nCompletes work through use of CAD layout software\n\nWorks closely with the engineer to provide high quality layout in a timely manner\n\nAbility to do block level, macro level and top level; floor planning, assembly and verification\n\nExperience working in multiple processes\n\nAbility to lead peers/teams on complex blocks and top level\n\nCommunicates regular status updates\n\nTakes on mentoring/leadership roles to promote high quality work of entire team\n\nAbility to learn and evaluate new tool/features with little supervision and proactively share knowledge with peers\n\nAbility to recognize common analog structures and floorplan blocks/”top level” utilizing best analog layout practices\n\nCreate and give presentations, write “how to” documents and training instructions for layout and engineering peers.\n\nRecommends new/changes to policies, methodologies and established procedures \n\nOther duties as required.\n\nQualifications\n\nBachelor’s degree in electrical engineering or equivalent\n\nMinimum 6+ years of experience in the layout of integrated circuits  \n\nKNOWLEDGE, SKILLS, ABILITIES\n\n \n\nStrong understanding of basic electrical properties and principles\nStrong familiarity with Cadence Virtuoso, Layout XL, SKILLCAD, Calibre and Unix\n\nIntermediate to advance knowledge on skill programming / writing scripts a plus\nAdvanced knowledge of layout dependent effects with regarding to device and process matching techniques\nExecution in Top Level assembly of Layout\nStrong knowledge of Latch-up prevention\nStrong knowledge of ESD protection schemes\n\n \n\n#LIPR1\nStrong familiarity with P&R methods is a plus\nOutstanding communication and verbal presentation skills\n\n       Previous experience in the preparation of layout data for release to foundry a plus\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "SoC Performance Modeling & Architecture Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-06-19T12:02:00+00:00", "url": "https://global-external-amd.icims.com/jobs/84935/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Role Overview We are seeking a highly skilled and motivated SoC Performance Modeling & Architecture Engineer to drive the definition, analysis, and optimization of our next-generation Systems-on-Chip (SoCs). In this role, you will be responsible for the end-to-end performance lifecycle—from workload analysis and microarchitectural modeling to post-silicon correlation. You will evaluate complex architectural trade-offs across CPU, GPU, NPU/ML accelerators, Memory, and Network-on-Chip (NoC) subsystems to maximize performance-per-watt and shape the roadmap for future silicon. Key Responsibilities 1. Performance Modeling & Simulation Leverage and Maintain Cycle-Approximate Models: Leverage, and maintain execution-driven and trace-driven SoC performance simulators (e.g., using C++, SystemC, or Python). Explore Architectural Space: Construct scalable models to project the performance of future SoC configurations and validate architectural concepts before RTL freeze. Hardware/Software Co-Design: Model the interaction between hardware subsystems and low-level software stacks to identify system-wide bottlenecks. 2. Workload Analysis & Benchmarking Characterize Workloads: Profile and analyze industry-standard benchmarks and real-world use cases across CPU (e.g., SPEC CPU), GPU (e.g., 3DMark, GFXBench), and Machine Learning/AI (e.g., MLPerf, LLM inference, CNNs). Trace Generation: Capture and manipulate instruction and memory traces from both pre-silicon environments and post-silicon hardware. 3. Subsystem & Interconnect Analysis NoC & Fabric Optimization: Evaluate Network-on-Chip (NoC) topologies, routing algorithms, arbitration schemes, and bandwidth/latency characteristics under heavy multi-master workloads. Memory Hierarchy Evaluation: Analyze the impact of cache hierarchies (L1/L2/System Cache), memory controllers, and various memory technologies (e.g., LPDDR5/6, HBM) on system performance. 4. PPA (Power, Performance, Area) Trade-off Studies Multi-Domain Trade-offs: Evaluate complex trade-offs when scaling or configuring different combinations of CPU cores, GPU compute units, and ML accelerators. Required Qualifications & Skills Technical Expertise Education: BS/MS in Computer Engineering, Electrical Engineering, Computer Science, or a related field. Experience: 5+ years of industry experience in SoC/Processor architecture and performance modeling. Programming: Strong proficiency in C/C++ and Python Architecture Knowledge: Deep understanding of modern computer architecture, including pipelining, out-of-order execution, cache coherence protocols, and virtual memory. Modeling Frameworks: Direct experience with performance modeling frameworks (e.g., gem5, SystemC, or proprietary cycle-accurate/cycle-approximate simulators). Preferred Qualifications Hands-on experience with post-silicon debug tools and reading hardware performance counters (e.g., ARM PMU, Intel VTune, or internal test chips). Familiarity with ML frameworks (PyTorch, TensorFlow) and compiling/mapping models to specialized hardware accelerators. Experience utilizing data visualization tools to present complex performance metrics cleanly to cross-functional stakeholders. #LI-AA1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Principal Hardware DFT Lead", "company": "NXP", "location": "Noida", "date_posted": "2026-06-19", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Noida/Principal-Hardware-DFT-Lead_R-10064020", "is_hardware": true, "platform": "workday", "jd_text": "We are looking for a Principal HW DFT Engineer who will architect, implement, and validate NXP’s Automotive grade products.  You will be responsible for advanced test strategies and implementation, verification and validation of pre/post tapeout of DFT features, overall test coverage improvements, and work closely with RTL and physical team on DFT timing constraints and closures. \n \nMain Job Tasks and Responsibilities:\n \nArchitecture & Strategy: Define and implement advanced DFT strategies, including Scan Architecture, JTAG, Memory BIST (MBIST), and Logic BIST (LBIST)\nImplementation & Verification: Lead the integration of digital subsystems, perform scan insertion, and generate ATPG (Automatic Test Pattern Generation) patterns while ensuring high fault coverage.\nSilicon Support: Drive post-silicon validation and debug activities to root cause failures and improve manufacturing test efficiency.\nCollaboration: Coordinate with physical design and test engineering teams to ensure timing closure and that test patterns are operational immediately upon silicon arrival.\n \nMinimum Required Qualifications\nEducation: B.S./M.S. Electrical/Computer Engineering (or similar degrees)\nExperience: Typically requires 10+ years of industry experience in SoC DFT implementation, verification, static timing closure,  test coverage analysis and improvement, and silicon bring-up on ATE\nTool Expertise: Proficiency with industry-standard EDA tools from Mentor Graphics/Siemens (Tessent), Cadence, or Synopsys\nTechnical Skills:\nDFT - Scan insertion and architecture, ATPG: Proficiency in generating test vectors to detect manufacturing faults like stuck-at, transition, and advanced faults, Built-In Self-Test (BIST): Integration of Memory BIST (MBIST) for embedded SRAM/ROM and Logic BIST (LBIST) for autonomous logic testing, Boundary Scan & JTAG, Test Compression: Implementing techniques to reduce test data volume and application time, which is critical for large System-on-Chip (SoC) designs.\nHardware Design & Implementation - HDL Proficiency: Strong command of Verilog or SystemVerilog for modifying RTL to insert test logic and writing test wrappers.  Timing & Constraints: Knowledge of Static Timing Analysis (STA) and creating DFT-specific timing constraints (SDC files) to ensure test logic does not degrade functional performance. \nVerification & Debug - Simulation: Conducting gate-level simulations (GLS) and verifying DFT logic for correctness before fabrication.  Post-Silicon Debug: Analyzing silicon data from Automated Test Equipment (ATE) to diagnose failures and improve manufacturing yield. \nSoftware & Tool Proficiency - EDA Tool Suites: Mastery of industry-standard tools such as Synopsys TestMAX/DFT Compiler, Mentor Graphics Tessent, and Cadence Modus. Scripting & Automation: Expertise in Tcl, Python, or Perl to automate test insertion flows, run simulations, and parse coverage reports.\n\nMore information about NXP in India...\n\n#LI-2734", "jd_status": "stored"}, {"title": "Staff Engineer - Formal Verification", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-06-19", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Staff-Engineer---Formal-Verification_R-101363", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nResponsibilities:\nIdentify blocks suitable for applying Formal Verification\n\nCreate Formal Test-plan for blocks identifying properties to be implemented and sign-off metrics\n\nImplementation and maintenance of Formal Verification environments in Chisel\n\nApplying various FV techniques to reduce complexity and prove correctness of DUT\n\nDebugging RTL to identify causes of failure scenarios\n\nGuide and train team members on effective usage of Formal Verification tools\n\nDevelop/modify scripts to automate the verification process\n\nReview formal setups and proofs with design and verification teams\n\nMaintain and extend assertion libraries\n\nRequirements:\n8+ years of experience in Formal Verification of Digital Hardware Design\nExtensive experience with Formal Abstraction Techniques and sign-off process\nFamiliarity with industry-standard Formal Verification Tools, such as VC Formal, JasperGold\nKnowledge of Hardware Description and Verification Languages, such as VHDL, Verilog/ SystemVerilog\nKnowledge of Object-oriented Programming is a plus\nA keen interest in Processors and Digital systems\nStrong reasoning skills and excellent attention to detail\nGood inter-personal and teamwork skills!\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Director, Analog Design", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-06-18T13:34:36.869000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000132869701-director-analog-design", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Job Responsibilities \n \nCollaborate with Product Line Manager to prioritize near-term product execution imperatives and long-term strategic initiatives \nSynthesize technical goals from business strategy \nDefine design IP, process technology, and packaging requirements to meet portfolio performance and cost targets \nIdentify and adopt tools and methodologies for ongoing improvements in development time and product quality \nWork with cross functional groups to integrate new capabilities into the design process  \nAlign product development plans to leverage capabilities \nDirect the IC design and verification team to deliver on cost, performance, and time-to-market goals \nGrow the design organization with top talent in support of product roadmap  \nCollaborate within the larger design community on sharing of IP, resources, methodologies, and knowhow \nVisit customers to learn about the application and total system level solution \nCultivate a culture of excellence with a commitment to exceed customer expectations \n\nJob Requirements \nBSEE (MSEE pref.) or equivalent with 20+ years professional industry experience in design engineering role, including 10 years of management experience \nBackground in power management design\nA demonstrated track record of managing the development of commercially successful power IC products building, retaining, and managing a global team \nStrong communications skills and broad technical skills are required \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Principal System Applications Engineer", "company": "Infineon", "location": "Bangalore (India)", "date_posted": "2026-06-18T05:55:40+00:00", "url": "https://jobs.infineon.com/careers/job/563808970586017", "is_hardware": true, "platform": "eightfold", "jd_text": "As a Principal System Applications Engineer in our IoT Solutions team, you will lead the design and delivery of system-level projects that showcase how Infineon silicon and software can enable differentiated features in Edge Artificial Intelligence (AI) and Internet of Things(IoT) applications.\n\nYour Role\n\nKey responsibilities in your new role\n\nAs a Principal System Applications Engineer in our IoT Solutions team, you will lead the design and delivery of system-level projects that showcase how Infineon silicon and software can enable differentiated features in Edge Artificial Intelligence (AI) and Internet of Things(IoT) applications. Projects can include proof-of-concept demonstrations, reference designs, and application specific evaluation /development platforms. You will be part of Infineon’s Consumer, Computing, & Communication (C3) Segment, focused on Edge AI and IoT applications. If you enjoy creating creative system-level embedded solutions to solve real-world problems focused on Edge AI & IoT applications, then apply now!\nKey Responsibilities in your new role:\nTranslate marketing requirements into technical requirements and specifications\nCreate hardware and software architectures for system projects\nDefine technical architecture strategy and direction for IoT system projects, serving as the team's technical authority\nMentor and guide junior and senior engineers through technical reviews and design feedback\nWork with project managers to develop engineering project plans\nCollaborate with cross-functional team members to create system-level solutions that can include Edge AI, wireless connectivity, human machine interfaces (HMI), motor control, and sensor fusion\nPublish software via GitHub and create technical documentation\nSupport go-to-market activities for solutions including conducting technical training, attending trade shows to demo solutions, and supporting lead customers.\n\nYour Profile\n\nQualifications and skills to help you succeed\n\nA Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Electronics and Communication Engineering (required);advanced degree preferred.\n10+ years' experience with embedded systems, IoT, and Edge AI\nExperience with C, C++.\nExperience with real-time operating systems (RTOS) such as Free RTOSor Zephyr.\nExperience with Embedded software or microcontroller platforms such as Infineon, XMC, PSoC, OPTIGA, Arduino, STM32, iMX RT or Raspberry Pi.\nExperience with hardware design and debug skills including PCB schematic review, oscilloscope, logic analyzer, and hands-on board bring-up.\nExperience with Python scripting and data analysis, TensorFlow or PyTorch frameworks.\nExperience with model optimization or quantization for embedded AI (TinyML, Tensorflow Lite, etc.)\nExperience with Wi-Fi, Bluetooth, and modern IoT protocols (Matter, BLE Mesh, Thread) including experience with cloud platforms such as AWS, Azure IoT Hub, or Google Cloud IoT.\nExperience with embedded security fundamentals including secure boot, TLS/DTLS, and familiarity with Infineon OPTIGA Trust security solutions.\nStrong communication skills.\nCollaborates effectively across different functional groups.\nPreferred Qualifications:\nExperience defining or contributing to technical product roadmaps in collaboration with product marketing\nExperience with Infineon Modus Toolbox SDK and AIROC Wi-Fi/Bluetooth portfolio\nPublications, patents, or conference presentations in the embedded AI or IoT domain.\n\nContact:\n    umeshdatta.bamrule@infineon.com\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\nThis means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.\nPlease let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.\nClick here for more information about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "CPU Verification Engineer - Core Enablement", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-06-18T05:01:00+00:00", "url": "https://global-external-amd.icims.com/jobs/86975/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. SENIOR SILICON DESIGN ENGINEER THE ROLE: AMD is looking for talented, detail-oriented, and motivated design verification engineers who are interested in functional verification of x86 microprocessor cores. You’ll have the unique opportunity to work on and learn about some of the industry’s cutting edge micro-architectural designs while you create verification models and plans for verifying the architecture of the X86 CPU core. Your contributions will impact products that span the global x86 market from server to desktop and laptop designs. THE PERSON: The ideal candidate will have a strong interest in Computer Architecture, Digital Logic Design and Verification and should strive to continuously learn on the job. Excellent communication, organization, and teamwork skills are paramount, as is the ability to identify and tackle different problems with diligence, whether it is a tool, flow or process issue, or a logic design or verification issue. You should be adaptive, self-motivated, able to strike a balance between collaborative problem-solving and independent solution development. Candidate should have a solid track record of working on complex designs with hands-on experience on architecting and developing test-bench, test-bench components, test-planning and execution of test plan, coverage development and closure. Candidate should have working experience with global teams spread across different geography and time-zones. KEY RESPONSIBILITIES: · Collaborate with architects, design engineers, and other verification engineers to understand new CPU features to be verified. · Build test plan documentation, accounting for interactions with other features, various design sub-units within CPU, SOC and also hardware, firmware, and software use cases if applicable. · Estimate time required to write new feature tests and any required changes to the test environment and tools. · Develop directed and random verification tests. · Understanding the existing test bench setup and look for opportunities to improve it. · Debug test failures to determine the root cause; work with RTL design engineers to resolve design defects and correct any stimulus or testbench issues. · Use scripting and internal AI tools to come up with innovative solutions to day-to-day problems and to improve individual as well as team's productivity. · Develop functional coverage properties as needed. · Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements. · Mentor junior engineers as needed. PREFERRED EXPERENCE: · ASIC design verification experience of 5 to 10 years. · Understanding or technical expertise in functional verification of microprocessor designs. · Experience with Verilog/System Verilog HDL, programming in Perl/Python/Ruby, C/C++, Makefile and logic simulation. · Experience with x86, ARM or any other industry standard microprocessor architecture. · Strong understanding of computer architecture and assembly programming, preferably x86. · A passion for computer architecture and a good understanding of modern out-of-order superscalar processor architecture. · Strong understanding the design and verification life cycle. · Experience in CPU cache/memory subsystem verification is a plus · Simulation and debugging with a Verilog based functional simulator. · General functional verification experience with digital designs. · Working experience in UNIX software environment. · Strong problem-solving and debugging skills in both pre- and post-silicon environments. · Exposure to leadership or mentorship is an asset. · Familiarity with use of AI is a plus. ACADEMIC CREDENTIALS:      Bachelor's or Master’s degree in Electrical/Electronics Engineering, Computer Engineering, Computer Science or similar with a focus on computer architecture #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Execution and Quality Validation Engineer", "company": "Graphcore", "location": "Bengaluru, India", "date_posted": "2026-06-18T02:56:07-04:00", "url": "https://job-boards.greenhouse.io/graphcore/jobs/8598240002", "is_hardware": true, "platform": "greenhouse", "jd_text": "About us\n\nGraphcore is one of the world’s leading innovators in Artificial Intelligence compute.\n\nIt is developing hardware, software, and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry.\n\nAs part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone.\n\nGraphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers, and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation.\n\nJob Summary\n\nReporting to the Validation leadership team, the Senior Execution and Quality Validation Engineer will be responsible for executing validation plans, developing automation solutions, and improving product quality across Graphcore silicon and platform technologies.\n\nWorking closely with architecture, design, verification, firmware, software, systems engineering, and validation teams, the successful candidate will contribute to scalable validation methodologies, improve test coverage and execution efficiency, and help ensure products meet high standards of functionality, reliability, and performance before customer deployment.\n\nThe role requires strong technical skills, attention to detail, and a passion for improving validation quality through effective execution, automation, and continuous improvement.\n\nThe Team\n\nThe Validation Execution and Quality team sits within the Validation organisation and is responsible for improving validation effectiveness, test execution efficiency, product quality, and release readiness across Graphcore silicon and platform products.\n\nThe team develops validation methodologies, automation frameworks, test execution infrastructure, and quality processes that enable engineering teams to execute validation activities at scale. Working closely with validation, architecture, firmware, software, systems, and design teams, the group helps ensure products are thoroughly validated before release.\n\nResponsibilities and Duties\n\nExecute validation strategies for silicon, subsystem, and platform technologies across functional, performance, reliability, and stress testing \n\nPlan, optimize, verify, and test critical electronic systems, including silicon, FPGA-based platforms, test systems, and associated validation infrastructure \n\nDevelop and execute validation plans to ensure products meet quality, reliability, and performance objectives \n\nCreate detailed test plans from high-level validation requirements and test cases, ensuring timely execution and high-quality results \n\nDesign, develop, and maintain automation frameworks that enable efficient execution of test plans, regression suites, and validation activities \n\nSupport silicon and platform validation activities from bring-up through product readiness \n\nAnalyse validation results and system behaviour to identify issues and opportunities for improvement \n\nCollaborate with architecture, design, verification, firmware, software, systems engineering, and validation teams to implement new validation requirements and improve test coverage \n\nIntegrate new validation capabilities and test solutions into existing validation infrastructure to improve productivity, quality, and execution efficiency \n\nDevelop automated data collection, analysis, and reporting solutions to improve engineering visibility and decision-making \n\nEvaluate design features to identify functional, compatibility, integration, and reliability risks \n\nInvestigate validation failures using structured debug and root-cause analysis methodologies \n\nContribute to improvements in validation techniques, workflows, automation, and engineering processes \n\nSupport power, performance, and system-level validation activities through development of scalable validation infrastructure and methodologies \n\nContribute to validation best practices, documentation, and engineering standards \n\nAct as a quality-focused validation engineer, helping identify and resolve issues before products reach customers \n\nCandidate Profile\n\nEssential:\n\nExperience in silicon validation, hardware validation, system validation, or related engineering disciplines\n\nStrong understanding of validation methodologies, test planning, test execution, and quality processes \n\nExperience developing automation frameworks for validation, regression execution, and test orchestration \n\nStrong Python programming skills for automation, data analysis, and infrastructure development \n\nStrong understanding of hardware systems, silicon bring-up, and validation workflows \n\nExperience translating high-level requirements into structured validation plans and test cases \n\nExperience analysing validation results and participating in root-cause investigations for complex technical issues \n\nUnderstanding of validation coverage, quality metrics, release readiness criteria, and risk assessment methodologies \n\nExperience collaborating across architecture, design, verification, firmware, software, systems, and validation teams \n\nExcellent analytical, diagnostic, and problem-solving skills \n\nStrong communication skills and the ability to work effectively across multidisciplinary engineering teams\n\nDesirable\n\nExperience with post-silicon bring-up and system integration activities \n\nExperience developing regression systems and automated test execution infrastructure \n\nExperience with FPGA-based validation environments \n\nExperience automating laboratory equipment and validation environments \n\nFamiliarity with CI/CD systems and continuous testing methodologies \n\nExperience developing dashboards, reporting systems, or engineering analytics tools \n\nExperience with C, C++, or embedded software development \n\nExperience working on AI accelerator, high-performance compute, or semiconductor products \n\nExperience contributing to validation standards, quality metrics, and engineering best practices", "jd_status": "stored"}, {"title": "Senior Principal Verification Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-06-18", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505731", "is_hardware": true, "platform": "oracle", "jd_text": "We are seeking an experienced Senior Principal ASIC/SoC Verification Engineer to join our dynamic and fast‑paced engineering team. In this role, you will be responsible for ensuring the functional correctness, robustness, and overall quality of our cutting‑edge semiconductor and SoC designs. If you thrive in a collaborative environment and enjoy solving complex technical challenges, this opportunity is an excellent fit.\n\n#LI-RG1\n\nResponsibilities\nResponsibilities\n\n1. Verification Planning and Execution\n\nDevelop and execute comprehensive SoC/IP‑level verification plans aligned with design specifications and project goals.\n\nDrive verification closure through functional, code, and assertion coverage, ensuring high‑quality deliverables.\n\nApply industry‑standard ASIC/SoC verification techniques including test planning, testbench creation, constrained‑random and directed stimulus, assertions, and coverage‑driven verification.\n\nPerform SoC integration verification, validating interactions across subsystems, interfaces, and power/performance domains.\n\n2. Testbench & Environment Development\n\nArchitect, develop, and enhance SystemVerilog UVM/OVM‑based testbenches for IP and SoC‑level verification.\n\nBuild and integrate reusable Verification IP (VIP) and scalable verification components.\n\nCollaborate with internal teams and third‑party VIP providers to ensure seamless integration and compliance.\n\nDevelop checkers, scoreboards, monitors, and coverage models to support robust verification.\n\n3. Methodology, Flows & Best Practices\n\nDemonstrate strong understanding of ASIC/SoC design and verification methodologies, including constraint‑random verification and object‑oriented programming principles.\n\nContribute to verification methodology improvements, automation, and flow optimization.\n\nEnsure adherence to best practices in UVM architecture, reuse, and maintainability\n\n4. Advanced Verification Skills\n\nPerform Gate‑Level Simulation (GLS) including SDF annotation, timing verification, and debug of post‑synthesis/post‑layout issues.\n\nExecute power‑aware verification using UPF/CPF, validating power modes, isolation, retention, and sequencing.\n\nDebug complex SoC‑level issues involving multiple clock domains, resets, and power states.\n\nApply formal verification techniques where appropriate to complement simulation‑based verification.\n\n5. Technical Skills\n\nStrong proficiency in SystemVerilog (UVM/OVM) and scripting languages such as Python, Perl, Tcl, C/C++, and Verilog PLI.\n\nFamiliarity with standard protocols and interfaces (e.g., I2C, SPI, UART, AXI/AHB/APB).\n\nExperience with simulation, debug, and coverage tools from major EDA vendors (Synopsys, Cadence, Siemens).\n\nKnowledge of CI/regression automation, version control, and workflow tools is a plus\n\n6. Collaboration & Communication\n\nWork effectively with design, architecture, DV, validation, and firmware teams to drive verification to completion.\n\nCommunicate technical concepts clearly through documentation, reviews, and cross‑functional discussions.\n\nDemonstrate initiative, strong analytical problem‑solving skills, and adaptability in a diverse team environment.\n\n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Senior Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-06-18", "url": "https://careers.arm.com/job/bengaluru/senior-engineer/33099/96595985776", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Description:\nArm’s hardware is at the heart of the computing and connectivity revolution that continues to transform the way people live and businesses operate. As we continue to grow, we need the best engineers to join a team responsible for the development of sophisticated Subsystems and Solutions. Soon, we could be using your talents to develop the technologies that will enable the latest compute solutions in today's Enterprise, Auto and Client markets.\nResponsibilities:\nAs a verification engineer with a knowledge of subsystems and SoCs you will make valuable contributions to a team tasked with verifying the functional correctness of SS/SoC.\nEngineers will have ample opportunities to collaborate with designers and architects to understand design specifications and build a functional verification strategy.\nKey responsibilities will include writing test plans, defining test methodologies, and completing functional verification to the required quality levels and schedules.\nWill collaborate with engineers in architecture, design, verification, implementation, modeling, performance analysis, silicon validation, FPGA and board development.\nSenior engineers are also encouraged to support junior members.\nRequired Skills and Experience :\n5-7 years of proven experience in working on IP/Subsystem Verification.\nExperienced in one or many of these technologies/ protocols – PCIe,CXL,AMBA\nPreferred Experience in PCIe Gen6 and later generations.\nPreferred Experience in RAL (Register verification).\nGood understanding in any of of cross functional flows like Reset, Ras(Error and Interrupt), Security, low Power for High-speed IO IPs.\nGood Skills in System Verilog, shell programming/scripting (e.g. Tcl, Perl, Python etc.)\nExperienced in one or more of various verification methodologies – UVM, formal and low power.\nExposure to all stages of verification: requirements collection, creation of test plans, testbench implementation, test cases development, documentation, and support.\n“Nice To Have” Skills and Experience :\nPossess knowledge of object-oriented programming concepts\nPractical experience of working on PCIe Sub System design. \n#LI-PS2\n \nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\n\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Electronics Hardware  Design Engineer", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2026-06-18", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/Senior-Electronics-Hardware--Design-Engineer_R2621363", "is_hardware": true, "platform": "workday", "jd_text": "Who We Are\n\nApplied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips – the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world – like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world. \n\nWhat We Offer\n\nLocation:\nBangalore,IND\nYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. \n\nAt Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. \n \n \nAs an Electrical Engineer, you are responsible for designing, modifying, and troubleshooting electrical or electronic engineering assemblies, layouts, schematics, and drawings to advance the equipment that supports our technology. Using your technical experience and critical thinking skills, you will perform engineering analysis, generate test reports, develop innovative solutions, and create documentation for product releases. You will also coordinate the procurement and assembly of components, identify sources of critical parts, and resolve technical issues to ensure peak performance. \n \nKey Responsibilities\nTechnically lead and/or execute engineering projects, including development of key suppliers\nProblem identification and troubleshooting a wide range of complex electrical/electronics problems with limited to no supervision\nSpecify the development of design or modify engineering assemblies, layout/schematics and/or detailed drawings/specifications of complex scope\nInterfaces with internal and external customers regarding complex electrical issues for specific projects\nImplement concepts for wide range of complex product issues and solutions\nGenerate product specifications with limited to no supervision\nSpecify and/or perform engineering analysis of complex scope\nDefine, coordinate, perform and generate engineering test reports\n\nFunctional Knowledge\nIn-depth skills of Analog & Digital circuit design using ADC, DAC, Op-amps, Transistors, MOSFETS, Sensors, Signal Conditioning circuits, microcontroller/ Microprocessor, Memories, Various communication interfaces (I2C,SPI, RS485,Ethernet), IOT platforms \n\nExperience with designs using Industrial IO modules, industrial controllers (PLC), PID controllers, Industrial bus protocols(Ethercat, Devicenet ) etc. \n\nExperience in developing detailed schematics and schematic capture using CAD tools.  \n\nElectronic circuit modeling & simulation. \n\nWorked on projects from requirement to final product release (circuit design, prototyping and testing) and maintenance. \n\nHand on experience on testing tools(DSO,DMM,FG, electronic loads etc.), , circuit validation,  board bring up , functional testing , trouble shooting, Failure analysis . \n\nExpertise  on PCB design process,  Technical document writing \n\n​\n\nBusiness Expertise\nInterprets internal/external business challenges and recommends best practices to improve products, processes or services\n\nLeadership\nMay lead functional teams or projects with moderate resource requirements, risk, and/or complexity \n\nProblem Solving\nLeads others to solve complex problems; uses sophisticated analytical thought to exercise judgment and identify innovative solutions\n\nImpact\nImpacts the achievement of customer, operational, project or service objectives; work is guided by functional policies\n\nInterpersonal Skills\nCommunicates difficult concepts and negotiates with others to adopt a different point of view\n\nGood to have skills: \n\n·        Knowledge in product certification process (Handle testing at EMC/ Safety) labs is preferred. \n\nExpertise with FW development with C, C++ , Python etc , FPGA &CPLD programming,  \n\nKnowledge in Documentation, release process , Reliability testing, \n\nObsolescence process, Customer support for field issues, Interact with suppliers  \n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nAssignee / Regular\nTravel:\nYes, 10% of the Time\nRelocation Eligible:\nYes\n\nApplied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "Lead CAD Integration & Validation Engineer – Analog/Mixed-Signal/RF", "company": "NXP", "location": "Bangalore", "date_posted": "2026-06-18", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Analog-RF---Mixed-Signal-Verification-Engineer---Architect_R-10063655", "is_hardware": true, "platform": "workday", "jd_text": "The Lead CAD Integration & Validation Engineer – Analog/Mixed-Signal/RF operates in a Design Enablement role and is responsible for defining and executing comprehensive pre-silicon verification strategies to support Analog/Mixed-Signal/RF SoC development. The role ensures seamless integration of foundry PDKs, process models, EDA views, CAD methodologies, and tools through integration testing using AMS/RF IP cores as validation vehicles. The individual leads the development and execution of integration tests and CAD flow validation frameworks to evaluate compatibility, stability, scalability, and correctness across design platforms. This includes analysis, cross-version impact and performance assessment (PDK, tools, technology, methodologies), and end-to-end pre-silicon validation from schematic to sign-off to ensure consistency. The role collaborates with methodology teams, EDA tool vendors, and IP and design teams to drive new technology or feature enablement and deployment across 28nm to 5nm nodes, while leveraging automation and AI-driven techniques to improve robustness, productivity, and design quality.\n\nRequired skillset:\nStrong expertise in Analog, RF, and Mixed-Signal pre-silicon verification methodologies\nGood understanding of foundry PDKs, Process models, EDA views involved in simulation and validation process\nGood hands-on experience with Cadence Virtuoso, ADE, Spectre, AMS Designer, Keysight ADS and similar other industry standard tools\nProficiency in RF and EM tools such as Keysight RFPro, Ansys HFSS, Cadence EMX, Clarity\nExperience with Analog and mixed signal modelling using spice, Verilog-A/MS, vams, wreal and co-simulation (Analog + Digital + RF domains)\nExperience in functional, structural, and integration-level verification\nScripting skills in SKILL, TCL, Python, or similar\nNote: Out of Scope for this role: Post-silicon or hardware-level testing, development and validation using lab instruments, and standards compliance testing.\nDesired skillset:\nStrong fundamentals in Analog and CMOS RF circuit blocks, such as amplifiers, PLLs, ADC/DACs, mixers, oscillators, filters, and RF front-end components\nKnowledge of reliability and aging analysis (BTI, HCI, EM effects)\nUnderstanding of Layout, parasitic effects, PVT variations, and post-layout verification\nSoft Skills\nStrong technical leadership and mentoring capabilities\nGood problem-solving and analytical thinking\nClear communication and documentation skills\nAbility to drive initiatives and influence technical decisions\nStrong ownership and accountability for deliverables\n\nAcademics & Experience Level\nEducation: B.Tech/M.Tech in Electronics and Communication / Electrical and Electronics or related fields of engineering\nExperience: 8+ years of experience in Semiconductor / EDA domain\n\nMore information about NXP in India...\n\n#LI-7013", "jd_status": "stored"}, {"title": "Electrical Engineer III", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2026-06-18", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/Electrical-Engineer-III_R2610025", "is_hardware": true, "platform": "workday", "jd_text": "Who We Are\n\nApplied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips – the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world – like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world. \n\nWhat We Offer\n\nLocation:\nBangalore,IND\nYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. \n\nAt Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. \n \n \nAs an Electrical Engineer, you are responsible for designing, modifying, and troubleshooting electrical or electronic engineering assemblies, layouts, schematics, and drawings to advance the equipment that supports our technology. Using your technical experience and critical thinking skills, you will perform engineering analysis, generate test reports, develop innovative solutions, and create documentation for product releases. You will also coordinate the procurement and assembly of components, identify sources of critical parts, and resolve technical issues to ensure peak performance. \n \nRole Responsibilities: \nDesign or modify electrical or electronic engineering assemblies, layouts, schematics, drawings, or specifications of difficult scope \n\nIdentify and troubleshoot a variety of complex electrical problems with limited supervision \n\nDefine, coordinate, perform and generate engineering test reports with limited supervision \n\nPerform engineering analysis of difficult scope with limited supervision \n\nTechnically lead or execute engineering projects, including the development of key suppliers \n\nImplement concepts for a variety of complex product issues and electrical solutions of difficult scope \n\nGenerate electrical product specifications; specify and review engineering documentation \n\nServe as a resource for junior colleagues; lead project teams, as needed\n\nClearly communicate difficult or sensitive information; build consensus \n\nMinimum Qualifications: \nBachelor’s degree\n\n4-7 years of experience in a related field\n\nPreferred Qualifications: \nStrong knowledge of industry best practices, key business drivers, competition in the marketplace, and how your area of expertise integrates with others  \n\nDemonstrated leadership skills to lead small projects as needed  \n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nAssignee / Regular\nTravel:\nYes, 10% of the Time\nRelocation Eligible:\nYes\n\nApplied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "CPU Design Verification Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-06-17T13:31:00+00:00", "url": "https://global-external-amd.icims.com/jobs/87154/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.     THE PERSON:  You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.   KEY RESPONSIBILITIES:  Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues  Analyze and enhance legacy test plans to accommodate new Design for Debug feature developments Perform debug triage of failures from simulation and emulation environments for CORE and sub-level regressions Develop assembly tests, C++ checkers to support new features Write complex Perl scripts to update simulation files in a deterministic manner Recreate post-silicon failures in pre-silicon environment Debug and resolve test cases in assembly language Conduct silicon debug and root cause analysis with minimal logging support Scope new features and execute comprehensive test planning cycles Utilize JTAG protocols for debugging and validation   PREFERRED EXPERIENCE:  8+ years of experience in ASIC Design Verification with strong computer architecture knowledge Expert-level understanding of CPU architecture, L2/L3 cache architectures, and processor subsystems (x86 or ARM) Proficiency in C++ and assembly language programming Advanced Perl scripting capabilities Deep knowledge of digital design, RTL design, and verification flows Strong troubleshooting and analytical debugging skills with ability to debug without logs Experience with OOP concepts Post-silicon debugging experience preferred Ability to quickly adapt to complex infrastructure environments Excellent hands-on debug skills and attention to detail Proficient in debugging firmware and RTL code using simulation tools  Experienced with Verilog, System Verilog, C, and C++   Scripting language experience: Perl, Ruby, Makefile, shell preferred.   Exposure to leadership or mentorship is an asset ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Hardware Test Engineer", "company": "Lumilens", "location": "Bengaluru, India", "date_posted": "2026-06-17T12:29:55.669000+00:00", "url": "https://jobs.ashbyhq.com/lumilens/8c2bb962-56ae-4a3b-bc91-2ef11187eef7", "is_hardware": true, "platform": "ashby", "jd_text": "Hardware Test Engineer\n \nAbout Lumilens\n \nAt Lumilens, we are building critical photonics infrastructure powering tomorrow’s AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new era of computing—faster, cooler, and massively more efficient. Join our collaborative team to shape the future of high-speed optical connectivity.\n \nPosition Overview\n \nLumilens is seeking a skilled Hardware Test Engineer with 10-12 years of experience to join our innovative hardware team. In this role, you will be responsible for ensuring the quality, reliability, and compliance of our high-performance photonics and semiconductor solutions through rigorous hardware testing practices. You will play a key role in the development lifecycle, collaborating with engineering and manufacturing teams to deliver products that meet the highest standards.\n \nKey Responsibilities\n \nDesign and execute comprehensive hardware test plans and test cases for new product introductions and existing hardware platforms\n\nDevelop and maintain automated test setups, utilizing industry-standard frameworks and tools\n\nAnalyze and debug hardware issues, working cross-functionally with design and development teams\n\nEnsure testing aligns with industry standards and regulatory requirements\n\nInterpret hardware schematics and datasheets to facilitate thorough testing methodologies\n\nConduct environmental testing, including thermal and humidity assessments\n\nPerform and document EMC (Electromagnetic Compatibility) tests as needed\n\nOperate a variety of test equipment, including oscilloscopes, multimeters, and logic analyzers\n\nMaintain detailed test records, results, and reports for product validation and compliance\n\n \nRequired Technical Skills\n \nProficiency in hardware testing methodologies and best practices\n\nStrong knowledge of electrical and electronic systems\n\nExperience designing and executing test plans and test cases\n\nFamiliarity with test automation tools and frameworks\n\nAbility to read and interpret hardware schematics and datasheets\n\nKnowledge of industry standards and regulations for hardware testing\n\nUnderstanding of signal integrity and power integrity concepts\n\nProficiency using test equipment, such as oscilloscopes, multimeters, and logic analyzers\n\nExperience with hardware debugging and troubleshooting techniques\n\nUnderstanding of digital and analog circuit design principles\n\nFamiliarity with environmental testing (temperature and humidity chambers)\n\nUnderstanding of electromagnetic compatibility (EMC) testing\n\n \nQualifications\n \nBachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field\n\n10-12 years of hands-on experience in hardware testing within optical, semiconductor, or related technology sectors\n\nStrong analytical, organizational, and collaborative communication skills\n\n \nWhy Join Lumilens?\n \nWork at the forefront of AI, networking, and optical semiconductor technology\n\nCollaborative and innovative environment\n\nOpportunities for career growth\n\nCompetitive salary and comprehensive benefits package\n\n \nLumilens is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, or any other protected characteristic.", "jd_status": "stored"}, {"title": "Principal Cache RTL Design - CPU Team", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-06-17T11:58:00+00:00", "url": "https://global-external-amd.icims.com/jobs/86851/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. PMTS SILICON DESIGN ENGINEER THE PERSON:  You have a passion for modern, complex processor architecture, digital design as well as verification/design quality. You are a team player who has excellent communication skills, strong analytical & problem-solving skills and are willing to learn and ready to take on problems. A global mindset and ability to work in a multi – site environment are keys to being successful in this role. KEY RESPONSIBILITIES:  RTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design Architect and design of power management features, cache, coherency. Design optimization for implementing power efficient IP, implementing the RTL using low power techniques Responsible for the inter IP integration issues resolution Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem. Work closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design Architecting, micro-architecting and documentation of the design features Lead design team from all aspects of the RTL deliverables. Mentor the junior members of the RTL team to meet the team goals Represents AMD to the outside technical community, partners and vendors Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion. PREFERRED EXPERIENCE: 15+ years of experience in Digital IP/ASIC design and Verilog RTL development Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification. Should be well versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation. Expert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects. Should possess expertise in front-end EDA tools sign-off and its flows. Familiarity with low power design and low power flow is an added plus. Ability to program with scripting languages such as Python or Perl is a plus; Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements; Proven interpersonal skills, leadership and teamwork; Excellent writing skills in the English language, editing and organizational skills required; Skilled at prioritization and multi-tasking; Good understanding of engineering terminology used within the semiconductor industry; Good understanding of digital design concepts; Knowledge of, or experience in, functional design verification or design is highly desired. ACADEMIC CREDENTIALS: Master’s degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or VLSI design Engineering. #LI-RR1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Debug Validation Engineer", "company": "Graphcore", "location": "Bengaluru, India", "date_posted": "2026-06-17T07:10:05-04:00", "url": "https://job-boards.greenhouse.io/graphcore/jobs/8593486002", "is_hardware": true, "platform": "greenhouse", "jd_text": "About us\n\nGraphcore is one of the world’s leading innovators in Artificial Intelligence compute.\nIt is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry.\n\nAs part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone.\n\nGraphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation.\n\nJob Summary\n\nReporting to senior leadership within Architecture and Validation, the Debug Validation Engineer will drive post-silicon debug and validation activities for next-generation AI compute silicon and systems. The role is responsible for leading teams focused on identifying, reproducing, analysing and resolving complex silicon, firmware and system-level issues during bring-up, characterization and product readiness.\n\nThis position combines deep technical debugging expertise with strong cross-functional collaboration across multiple engineering disciplines. The role will work closely with architecture, RTL, firmware, software and systems teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage. The role will work closely with architecture, RTL, firmware, software, systems and platform teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage.\n\nThe Team\n\nThe Post-Silicon Debug and Validation team sits within the Architecture and Validation organisation and is responsible for bring-up, debug and validation of Graphcore silicon and systems.\n\nThe team works across the full product lifecycle, supporting first silicon bring-up, subsystem validation, system integration and production readiness activities. Engineers collaborate closely with hardware, firmware, software and systems teams to investigate complex failures, develop debug methodologies and improve validation infrastructure.\n\nResponsibilities and Duties\n\nLead post-silicon debug and validation activities for AI compute silicon and platform technologies\n\nContribute to debug and validation activities across multiple projects and milestones\n\nDrive prioritisation, planning and execution of debug and validation activities across multiple projects and milestones\n\nInvestigate and resolve complex silicon, firmware, software and system-level issues during bring-up and validation\n\nDevelop structured debug methodologies and failure analysis processes to improve issue resolution efficiency\n\nCollaborate closely with architecture, RTL, firmware, software and systems engineering teams to identify root causes and implement corrective actions\n\nDrive debug of CPU, memory, interconnect and high-speed I/O subsystems under functional, stress and workload conditions\n\nDevelop and enhance automated debug, regression and validation infrastructure using Python and related technologies\n\nAnalyse logs, traces, telemetry and hardware data to isolate and characterize system failures and performance issues\n\nSupport development of validation tests, debug tooling and custom diagnostics to improve coverage and observability\n\nDefine validation metrics, debug workflows and reporting standards to ensure consistent and repeatable analysis\n\nDrive continuous improvement of debug processes, validation methodologies and engineering workflows\n\nCommunicate technical risks, status and recommendations clearly to engineering leadership and cross-functional stakeholders\n\nSupport silicon readiness reviews and contribute to product quality and release decisions\n\nContribute to continuous improvement of debug methodologies, validation infrastructure and engineering workflows\n\nCandidate Profile\n\nEssential:\n\nStrong experience in bare metal environments\n\nGood knowledge of SoC and platform architectures\n\nExpertise in debug infrastructure and post-silicon debug methodologies\n\nStrong programming skills in Python, C, or debug scripting languages such as CMM\n\nHighly motivated self-starter with a collaborative and team-oriented approach\n\nAbility to work across teams and programming languages to identify root causes of deep and complex issues\n\nExperience of the post-silicon validation process applied in digital ASIC environments\n\nStrong Linux and Python experience\n\nExceptional communication skills and the ability to collaborate effectively to solve complex problems\n\nExcellent problem-solving, analytical and diagnostic skills\n\nDeep knowledge of scan, DFT, JTAG and trace infrastructure\n\nStrong debug skills including fault tree analysis, failure isolation, fishbone methodologies and system-level debug techniques\n\nAbility to work independently on technically complex debug and validation activities across hardware, firmware and software domains\n\nDesirable\n\nUnderstanding of DFT flows from insertion through post-silicon validation\n\nExperience developing tooling for parsing and analysing debug data, including scan dump parsing\n\nDriver-level experience with one or more of the following technologies:\n\nPCIe\n\nEthernet\n\nMemory technologies including LPDDR, DDR and HBM\n\nPeripheral interfaces such as I2C, I3C and SPI\n\nExperience using CoreSight and similar debug infrastructure including CTI, ETx, DStream, JLink, Lauterbach, ATB and STM\n\nGood knowledge of mixed-signal building blocks such as PLLs, high-speed PHYs and IC control/communication protocols\n\nExperience with Arm CPU architectures, system IP and associated debug tooling\n\nExperience with AMBA protocols\n\nUnderstanding of ML applications and associated workloads\n\nExperience in characterization, failure analysis, test development, statistical analysis and customer support", "jd_status": "stored"}, {"title": "Senior DDR & Execution Validation Engineer", "company": "Graphcore", "location": "Bengaluru, India", "date_posted": "2026-06-17T07:09:28-04:00", "url": "https://job-boards.greenhouse.io/graphcore/jobs/8593496002", "is_hardware": true, "platform": "greenhouse", "jd_text": "Job Summary\n\nReporting to the Memory Validation leadership team, the Senior Silicon DDR/HBM Validation Engineer will be responsible for the bring-up, validation, characterization and debug of advanced memory subsystems used in next-generation AI compute platforms.\n\nThe role will focus on DDR and HBM technologies, working closely with silicon design, firmware, characterization, platform and systems teams to ensure robust memory subsystem functionality, performance and reliability. The successful candidate will take ownership of significant validation activities, contribute to debug and root-cause analysis efforts, and help improve validation methodologies, automation and infrastructure.\n\nThe Team\n\nThe Memory Validation team sits within the Validation organisation and is responsible for the bring-up, validation, characterization and debug of memory subsystems across Graphcore silicon and platform products.\n\nThe team supports DDR and HBM validation activities throughout the product lifecycle, from first silicon through production readiness. Engineers work closely with architecture, RTL, firmware, characterization, systems and platform teams to ensure memory technologies meet functionality, performance, reliability and performance objectives.\n\nResponsibilities and Duties\n\nExecute validation and bring-up activities for DDR and HBM memory subsystems \n\nVerify memory bring-up software, firmware and scripts against defined project requirements \n\nDebug firmware, hardware and system-level issues and contribute to root-cause analysis activities \n\nAnalyse system logs, validation data and characterization results to identify failures and performance issues \n\nPerform PHY characterization and analog-level analysis during stress testing and validation activities \n\nDevelop and execute functional, stress, performance and corner-case validation tests \n\nPerform signal integrity, voltage, frequency and timing measurements using laboratory instrumentation \n\nCharacterize memory bandwidth, latency, training behaviour and subsystem stability across operating conditions \n\nDevelop Python-based automation, test infrastructure and reporting tools to improve validation efficiency \n\nCollaborate with architecture, RTL, firmware and platform teams to investigate and resolve technical issues \n\nContribute to memory subsystem debug activities spanning silicon, firmware, board and system domains \n\nSupport development of validation methodologies, debug procedures and reporting frameworks \n\nContribute to continuous improvement of validation infrastructure and engineering processes \n\nSupport silicon characterization, production readiness and qualification activities \n\nDocument validation results and communicate findings to the wider engineering team \n\nCandidate Profile\n\nEssential\n\nStrong experience validating DDR, LPDDR, HBM or related DRAM technologies \n\nDeep understanding of DRAM architecture, memory subsystem operation and memory controller functionality \n\nExperience with firmware, BIOS and Embedded C development \n\nStrong programming skills in C and Python \n\nHands-on experience using laboratory equipment including oscilloscopes and related measurement instrumentation \n\nExperience interfacing with low-speed peripherals including GPIO, SPI, I2C and UART/serial interfaces \n\nExperience performing functional testing and signal measurements including voltage, frequency and timing analysis \n\nStrong knowledge of embedded systems and microcontroller-based platforms \n\nHands-on experience with board bring-up and hardware validation activities \n\nExperience debugging complex hardware, firmware and system-level issues \n\nExperience performing silicon characterization and analysing validation results \n\nStrong analytical, diagnostic and problem-solving skills \n\nExcellent communication and collaboration skills with the ability to work effectively across multidisciplinary teams \n\nDesirable\n\nExperience with memory IP bring-up environments, firmware or validation software \n\nExperience with DDR or HBM PHY behaviour, memory controller architectures, training algorithms and calibration flows \n\nKnowledge of memory subsystem performance analysis and workload characterization \n\nExperience with memory margining, stress testing and reliability validation \n\nFamiliarity with JTAG, trace infrastructure and low-level debug tools \n\nExperience with high-performance compute, AI accelerator or data center systems \n\nUnderstanding of signal integrity and power integrity considerations in high-speed memory systems \n\nExperience developing validation automation frameworks and regression environments \n\nExperience supporting first-silicon bring-up and production readiness activities", "jd_status": "stored"}, {"title": "Sr. Engineer II – Verification", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-06-17", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Sr-Engineer-II---Verification_R2522-26", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nMicrochip's Data Center Solutions Business Unit (DCS) maintains a broad portfolio of products widely deployed by the industry's leading server/storage OEMs and hyperscale data centers. Customers deploy DCS solutions into applications ranging from Big Data capacity storage to Artificial Intelligence and Machine Learning, technologies that are helping shape the next digital age. Our product portfolio includes SAS, PCIe, NVMe, and CXL products that connect, manage, and secure the world's information, including Flash Controllers, High-Performance Switches, RAID Controllers, and Memory Controllers.\n\nAs a Senior Verification Engineer, you will lead the development of verification environments for our next-generation Data Center Storage products, including enterprise-class NVMe SSD controllers and other PCIe-based products. These complex SoC silicon devices enable top-tier data centers across Next-Gen Storage, Artificial Intelligence, and High-Performance Computing market segments.\n\nJob Responsibilities\nDefine comprehensive verification plans and build testbenches for device, subsystem, and IP-level designs using UVM/ SystemVerilog.\n\nInterpret requirements, protocol specifications, and micro-architecture specifications to drive verification strategy.\n\nVerify designs using state-of-the-art methodologies, including SystemVerilog/UVM coverage-driven verification, assertion-based verification (ABV), and formal verification techniques.\n\nExecute simulations using Cadence Xcelium and perform debug using Cadence Verisium Manager.\n\nDevelop test cases, checkers, and functional coverage models aligned with the verification test plan.\n\nDrive verification coverage closure and participate in coverage review meetings.\n\nCollaborate with cross-functional teams including firmware, emulation, and silicon validation.\n\nSupport pre-silicon emulation bring-up and debug activities.\n\nSupport post-silicon validation bring-up and debug, including development and documentation of hardware workarounds.\n\nMentor junior engineers and contribute to team-level process improvements.\n\nRequirements/Qualifications:\n\nRequired Qualifications\nBachelor's degree with 8–10 years of experience, or Master's degree with 6–8 years of experience in silicon verification.\n\nDemonstrated expertise in RTL verification using coverage-driven verification (CDV) methodologies.\n\nProficiency in HDL/HVL languages: SystemVerilog, Verilog, or VHDL , industry protocols such as AXI, APB, AHB\n\nSolid programming skills in C and/or C++.\n\nScripting experience in one or more languages (Python, Perl, TCL, Shell, etc.)\n\nStrong understanding of digital systems and computer architecture.\n\nFamiliarity with Unix/Linux environments and version control systems (Git, SVN)\n\nExcellent written and verbal communication and documentation skills.\n\nStrong analytical and problem-solving skills with attention to detail.\n\nProven ability to work independently and collaboratively in a fast-paced team environment.\n\nPreferred Qualifications\nHands-on experience with one or more industry protocols such as PCIe, CXL, NVMe, DDR, SAS, SATA.\n\nExperience with formal verification tools (e.g., Cadence JasperGold, Synopsys VC Formal)\n\nPrior experience in storage controller or memory controller verification\n\nExperience mentoring or technically leading a small team\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Security Operations Center (SOC) Functional Lead (Individual Contributor)", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2026-06-17", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/Security-Operations-Center--SOC--Functional-Lead--Individual-Contributor-_R2621907", "is_hardware": true, "platform": "workday", "jd_text": "Who We Are\n\nApplied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips – the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world – like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world. \n\nWhat We Offer\n\nLocation:\nBangalore,IND\nYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more. \n\nAt Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. \n\nRole Summary \n\nThe Security Operations Center (SOC) Functional Lead is a senior individual contributor who provides functional leadership, technical direction, and operational oversight for SOC capabilities. The role focuses on strengthening threat detection, incident response, and continuous improvement across cybersecurity operations. \n\nThis role requires strong expertise in SOC operations, incident response, detection engineering, and security platforms, along with the ability to influence stakeholders, guide analysts, and deliver scalable operational improvements. \n\n \n\nCore Responsibilities \n\nProvide functional leadership and operational coordination for SOC activities \n\nLead high-severity incident response, threat detection, and continuous improvement initiatives \n\nGuide analysts, improve playbooks and detection content, and enhance SOC processes and tooling \n\nPartner with IT, Risk, Compliance, and business stakeholders to strengthen security posture \n\nTrack key operational metrics and support governance, risk, and compliance requirements \n\nKey Requirements \n\nStrong expertise in SOC operations, incident response, SIEM/SOAR, and threat detection \n\nAbility to provide functional leadership, mentor analysts, and lead cross-functional initiatives \n\nStrong communication, stakeholder management, and problem-solving skills \n\nUnderstanding of security frameworks, governance, and compliance requirements \n\nEducation \n\nBachelor’s or Master’s in Cybersecurity, Computer Science, or related field \n\nExperience \n\n10+ years of experience in cybersecurity, including SOC operations, incident response, and detection engineering \n\nExperience in senior individual contributor, technical lead, or functional lead roles \n\nExposure global SOC environment \n\nCertifications (Preferred) \n\nCISSP, CISM, or equivalent \n\nGIAC (GCIA, GCED, GCIH) \n\nMicrosoft SC-200 / AZ-500 or equivalent \n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nAssignee / Regular\nTravel:\nYes, 10% of the Time\nRelocation Eligible:\nYes\n\nApplied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "Senior Staff Engineer Design", "company": "Infineon", "location": "Bangalore BTP (India)", "date_posted": "2026-06-16T18:10:29+00:00", "url": "https://jobs.infineon.com/careers/job/563808971242486", "is_hardware": true, "platform": "eightfold", "jd_text": "#WeAreIn to transform theoretical concepts into real hardware designs. Are you in?\n\nYour Role\n\nKey responsibilities in your new role\nDevelop micro-architecture and RTL coding for IP development in system Verilog/Verilog\nWork with the stakeholders and manage the digital IP roadmap\nPerform      comprehensive quality checks to ensure robustness and accuracy of IP      design including Lint, CDC, RDC, synthesis, DFT checks, ATPG\nPut      strong processes in place to ensure no bugs escape from IP qualification      flow\nTechnically      lead and mentor the juniors working with you\n\nYour Profile\n\nQualifications and skills to help you succeed\nBachelor’s or master’s degree in electrical or Electronics Engineering\n8+ years of experience in semiconductor Digital IP development, with demonstrated leadership within your area of expertise\nProven experience in digital IP RTL development\nExperience IO controller design will be  an added advantage\nKnowledge of commonly used bus protocols like AHB/APB is a must\nProven technical leadership skills in driving IP roadmaps with stakeholders\nStrong debugging skills for resolving integration-level issues and system level issues\nProficiency in System Verilog, Verilog\nExperience working with automated flows for generating RTL, along with the ability to enhance these workflows through scripting\nFamiliarity with leveraging AI tools to optimize and improve RTL integration workflows\nExperience in managing RTL releases and handling release containersProactive and collaborative approach to risk identification and mitigation, with excellent communication and presentation skills\nAbility to thrive in a fast-paced, global environment, collaborating with cross-functional teams including Architecture, IP, Physical Design, Verification, and DFX\nWorking knowledge of UNIX and Windows environments, along with MS Office tools (PowerPoint, Excel) and version control systems such as Git\nProficiency in scripting languages, particularly Python\n\nContact:\n    Gowri Shenoy, LinkedIn\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\nThis means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.\nPlease let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.\nClick here for more information about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Principal Execution & QA Validation Engineer", "company": "Graphcore", "location": "Bengaluru, India", "date_posted": "2026-06-16T06:49:41-04:00", "url": "https://job-boards.greenhouse.io/graphcore/jobs/8591764002", "is_hardware": true, "platform": "greenhouse", "jd_text": "About us\n\nGraphcore is one of the world’s leading innovators in Artificial Intelligence compute.\n\nIt is developing hardware, software, and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry.\n\nAs part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone.\n\nGraphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers, and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation.\n\nJob Summary\n\nReporting to the Validation leadership team, the Principal Execution and Quality Validation Engineer will be responsible for driving validation execution, automation, product quality, and release readiness across Graphcore silicon and platform technologies.\n\nThe role combines deep expertise in hardware validation, test automation, and quality engineering with a strong focus on execution excellence. Working closely with architecture, design, verification, firmware, software, systems engineering, and validation teams, the successful candidate will develop scalable validation methodologies, improve test coverage and execution efficiency, and ensure products meet the highest standards of functionality, reliability, and performance before customer deployment.\n\nAs a recognized technical leader within the validation organisation, this role will influence validation strategies, automation roadmaps, and quality practices across multiple projects and engineering disciplines.\n\nThe Team\n\nThe Validation Execution and Quality team sits within the Validation organisation and is responsible for improving validation effectiveness, test execution efficiency, product quality, and release readiness across Graphcore silicon and platform products.\n\nThe team develops validation methodologies, automation frameworks, test execution infrastructure, and quality processes that enable engineering teams to execute validation activities at scale. Working closely with validation, architecture, firmware, software, systems, and design teams, the group helps ensure products are thoroughly validated before release.\n\nResponsibilities and Duties\n\nDefine and drive validation strategies for complex silicon, subsystem, and platform technologies, ensuring comprehensive coverage across functional, performance, reliability, and stress testing \n\nLeverage advanced hardware knowledge to plan, optimize, verify, and test critical electronic systems, including silicon, FPGA-based platforms, test systems, and associated validation infrastructure \n\nDevelop and execute validation plans that ensure products meet quality, reliability, and performance objectives before release \n\nCreate detailed test plans from high-level validation requirements and test cases, ensuring timely execution and high-fidelity results \n\nDesign, develop, and maintain automation frameworks that enable rapid execution of test plans, regression suites, and validation activities \n\nLead silicon and platform validation activities from bring-up through product readiness \n\nConduct complex analysis of validation results and system behaviour to identify issues and opportunities for improvement \n\nCollaborate with architecture, design, verification, firmware, software, systems engineering, and validation teams to implement new validation requirements and improve test coverage \n\nIntegrate new validation capabilities, methodologies, and test solutions into existing validation infrastructure to improve productivity, quality, and execution efficiency \n\nDevelop automated data collection, analysis, and reporting solutions to improve engineering visibility and decision-making \n\nEvaluate complex design features to identify functional, compatibility, integration, and reliability risks \n\nInvestigate and drive resolution of complex validation failures through structured debug and root-cause analysis methodologies \n\nAssess validation techniques, workflows, and engineering processes, introducing automation and process improvements to maximize productivity \n\nSupport power, performance, and system-level validation activities through development of scalable validation infrastructure and methodologies \n\nInfluence validation roadmaps, infrastructure development, and engineering best practices across the validation organisation \n\nAct as the final validation authority for assigned areas, ensuring issues are identified and resolved before products reach customers \n\nDrive continuous improvement initiatives that improve validation quality, execution efficiency, and engineering productivity \n\nMentor engineers on validation methodologies, automation frameworks, test execution strategies, and quality practices \n\nCandidate Profile\n\nEssential:\n\nStrong experience in silicon validation, hardware validation, system validation, or related engineering disciplines \n\nDeep understanding of validation methodologies, test planning, test execution, and quality processes \n\nStrong experience developing automation frameworks for validation, regression execution, and test orchestration \n\nExpert-level Python programming skills for automation, data analysis, and infrastructure development \n\nStrong understanding of hardware systems, silicon bring-up, and validation workflows \n\nExperience translating high-level requirements into structured validation plans, test cases, and measurable quality outcomes \n\nExperience analysing validation results and driving root-cause investigations for complex technical issues\n\nStrong understanding of validation coverage, quality metrics, release readiness criteria, and risk assessment methodologies \n\nExperience collaborating across architecture, design, verification, firmware, software, systems, and validation teams \n\nExcellent analytical, diagnostic, and problem-solving skills \n\nExceptional communication skills and the ability to influence technical direction across multidisciplinary engineering teams \n\nAbility to independently lead complex technical initiatives and drive adoption of new validation methodologies and tools \n\nDesirable\n\nExperience with post-silicon bring-up and system integration activities \n\nExperience developing large-scale regression systems and automated test execution infrastructure \n\nExperience with FPGA-based validation environments \n\nExperience automating laboratory equipment and validation environments \n\nFamiliarity with CI/CD systems and continuous testing methodologies \n\nExperience developing dashboards, reporting systems, or engineering analytics tools \n\nExperience with C, C++, or embedded software development \n\nExperience working on AI accelerator, high-performance compute, or semiconductor products \n\nExperience defining organisational validation standards, quality metrics, and engineering best practices", "jd_status": "stored"}, {"title": "Principal Debug Validation Engineer", "company": "Graphcore", "location": "Bengaluru, India", "date_posted": "2026-06-16T06:49:20-04:00", "url": "https://job-boards.greenhouse.io/graphcore/jobs/8591785002", "is_hardware": true, "platform": "greenhouse", "jd_text": "About us\n\nGraphcore is one of the world’s leading innovators in Artificial Intelligence compute.\nIt is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry.\n\nAs part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone.\n\nGraphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation.\n\nJob Summary\n\nReporting to senior leadership within Architecture and Validation, the Debug Validation Lead will drive post-silicon debug and validation activities for next-generation AI compute silicon and systems. The role is responsible for leading teams focused on identifying, reproducing, analysing and resolving complex silicon, firmware and system-level issues during bring-up, characterization and product readiness.\n\nThis position combines deep technical debugging expertise with strong cross-functional collaboration across multiple engineering disciplines. The role will work closely with architecture, RTL, firmware, software and systems teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage. The role will work closely with architecture, RTL, firmware, software, systems and platform teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage.\n\nThe Team\n\nThe Post-Silicon Debug and Validation team sits within the Architecture and Validation organisation and is responsible for bring-up, debug and validation of Graphcore silicon and systems.\n\nThe team works across the full product lifecycle, supporting first silicon bring-up, subsystem validation, system integration and production readiness activities. Engineers collaborate closely with hardware, firmware, software and systems teams to investigate complex failures, develop debug methodologies and improve validation infrastructure.\n\nResponsibilities and Duties\n\nLead post-silicon debug and validation activities for AI compute silicon and platform technologies\n\nContribute to debug and validation activities across multiple projects and milestones\n\nDrive prioritisation, planning and execution of debug and validation activities across multiple projects and milestones\n\nInvestigate and resolve complex silicon, firmware, software and system-level issues during bring-up and validation\n\nDevelop structured debug methodologies and failure analysis processes to improve issue resolution efficiency\n\nCollaborate closely with architecture, RTL, firmware, software and systems engineering teams to identify root causes and implement corrective actions\n\nDrive debug of CPU, memory, interconnect and high-speed I/O subsystems under functional, stress and workload conditions\n\nDevelop and enhance automated debug, regression and validation infrastructure using Python and related technologies\n\nAnalyse logs, traces, telemetry and hardware data to isolate and characterize system failures and performance issues\n\nSupport development of validation tests, debug tooling and custom diagnostics to improve coverage and observability\n\nDefine validation metrics, debug workflows and reporting standards to ensure consistent and repeatable analysis\n\nDrive continuous improvement of debug processes, validation methodologies and engineering workflows\n\nCommunicate technical risks, status and recommendations clearly to engineering leadership and cross-functional stakeholders\n\nSupport silicon readiness reviews and contribute to product quality and release decisions\n\nContribute to continuous improvement of debug methodologies, validation infrastructure and engineering workflows\n\nCandidate Profile\n\nEssential:\n\nStrong experience in bare metal environments\n\nGood knowledge of SoC and platform architectures\n\nExpertise in debug infrastructure and post-silicon debug methodologies\n\nStrong programming skills in Python, C, or debug scripting languages such as CMM\n\nHighly motivated self-starter with a collaborative and team-oriented approach\n\nAbility to work across teams and programming languages to identify root causes of deep and complex issues\n\nExperience of the post-silicon validation process applied in digital ASIC environments\n\nStrong Linux and Python experience\n\nExceptional communication skills and the ability to collaborate effectively to solve complex problems\n\nExcellent problem-solving, analytical and diagnostic skills\n\nDeep knowledge of scan, DFT, JTAG and trace infrastructure\n\nStrong debug skills including fault tree analysis, failure isolation, fishbone methodologies and system-level debug techniques\n\nAbility to work independently on technically complex debug and validation activities across hardware, firmware and software domains\n\nDesirable\n\nUnderstanding of DFT flows from insertion through post-silicon validation\n\nExperience developing tooling for parsing and analysing debug data, including scan dump parsing\n\nDriver-level experience with one or more of the following technologies:\n\nPCIe\n\nEthernet\n\nMemory technologies including LPDDR, DDR and HBM\n\nPeripheral interfaces such as I2C, I3C and SPI\n\nExperience using CoreSight and similar debug infrastructure including CTI, ETx, DStream, JLink, Lauterbach, ATB and STM\n\nGood knowledge of mixed-signal building blocks such as PLLs, high-speed PHYs and IC control/communication protocols\n\nExperience with Arm CPU architectures, system IP and associated debug tooling\n\nExperience with AMBA protocols\n\nUnderstanding of ML applications and associated workloads\n\nExperience in characterization, failure analysis, test development, statistical analysis and customer support", "jd_status": "stored"}, {"title": "Staff Engineer Verification", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-06-16T04:37:34+00:00", "url": "https://jobs.infineon.com/careers/job/563808971196009", "is_hardware": true, "platform": "eightfold", "jd_text": "Your Role\n\nKey responsibilities in your new role\n\nCreate Subsystem Verification plan for PMBUS, AVS interface and signoff protocol compliance\nFormal verification coverage of critical control interfaces\nSV, UVM based Verification environment.\nRNM based simulation, Matlab model’s integration - DPI in Verification strategy.\nSOC Integration verification and system level scenarios development\nGLS Verification including root causing down to flop level\nCode Coverage, functional coverage\nFault Injection Campaign Execution for ASIL-D Products\nFamiliarity with industry standard protocols like I2C/I3C, UART, AHB/APB, SMBUS, SPI.\nMandatory:\nDemonstration of AI-driven productivity improvements in Verification test case generation and coverage closure\nShould have thrived in fast paced environments in the recent past\nIn Depth debug and Root cause analysis skills\n\nYour Profile\n\nQualifications and skills to help you succeed\n\nB.E./B.Tech/M.E./M.Tech in Electrical/Electronic Engineering Bachelor's - 7 to 9 years’ experience, Master’s - 6 to 9 year’s experience\nIn depth understanding of ASIC verification concepts and techniques. Ability to architect complex module / sub system / full chip testbenches and build verification infrastructure in SV/UVM.\nShould be a good mentor and guide the junior engineers in the team.\nExperience in ARM based SoC verification covering RTL, Power Aware and Gate level simulations is a plus.\nGood knowledge in industry standard protocols is preferable\n\nContact:\n    VidhiAshok.Thakkar@infineon.com\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\nThis means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.\nPlease let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.\nClick here for more information about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Low Power Design Engineer(NPU)-Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-06-16T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718080311", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nHands on experience in writing UPF based on power spec for block/SOC having complex power crossings\n\nHands on experience in validating power intent using CLP\n\nHands on experience on Power analysis using PTPX  \n\nUnderstanding on issues related to MV cell (isolation, level shifter, retention etc) insertion during synthesis\n\nGood understanding on optimization of dynamic & leakage power during RTL development and physical implementation\n\nGood understanding on power correlation between Pre-Si and Post-Si\n\nAutomation skill in TCL and/or Perl\n\nGood communication skill\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nAdditional Job Description\n\nCreating power spec for Qualcomm  DSP IPs based on the design spec\n\nPower intent development using UPF for DSP IPs based on power spec\n\nPower intent validation  at RTL level , Gate level (synthesis , PD ) using CLP\n\nFixing power intent based on PA DV feedback for any issue related to power intent Debugging issues related to MV cell  insertion during synthesis and modifying UPF accordingly   \n\nDynamic and Leakage power projection of DSP IPs during starting of the project\n\nDynamic and Leakage power no. generation using PTPX  and tracking the same at different stages of implementation flow\n\nHighlighting issues related to dynamic and leakage power mismatch compared to the target and working with Synthesis and PD teams to fix the issues\n\nWorking with cross function teams (SOC, Sub System etc) for smooth handoff of power intent and Dynamic & leakage power no. at different stages of project execution\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Design Verification Engineer", "company": "Lattice", "location": "Manila, Philippines", "date_posted": "2026-06-16", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/Manila-Philippines/Senior-Design-Verification-Engineer_R-100987", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nAccountabilities: \nDevelop comprehensive verification plans, clear metrics and continuously measure progress against the plan throughout the project\n\nVerify design blocks, sub systems and full chip using assertion-based verification, formal verification, directed tests and randomized tests\n\nUnderstand the specifications, use cases and develop System Verilog and ‘C’ based testbenches in UVM environment\n\nDesign and develop testbench components such as Universal Verification Components, BFMs and verification tools\n\nDefine and design verification regression environment\n\nPerform Functional coverage, RTL code coverage, assertion coverage, and gate level simulations\n\nCollaborate with design engineers, IP developers and SW developers to deliver high quality SoC verification on aggressive time schedules\n\nDevelop best practices and world class methods for SoC verification\n\nRequired Skills\n6-10 years Digital Design Verification Related Experience\n\nBachelor or Masters Degree in Computer Science, Computer Engineering, Electronics and Electrical Engineer\n\nSkill in debugging and analyzing complex digital design\n\nExperience in HDL and HVL Languages and Methodologies\n\nExperience in ASIC/FPGA/SoC verification or development cycle\n\nExperience in simulation tools like Cadence IES/XCELIUM, Synopsys VCS or Mentor's Questa\n\nHands-on experience in Python, Perl or Shell Scripting, TCL and Make.\n\nStrong communication, analytical and documentation skills and ability to interface with other groups/site\n\nStay up to date on industry trends and direction of verification technology development\n\nLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.\n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.\n\nLattice\nFeel the energy.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nPhilippinesLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Senior IP Verification Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-06-16", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Verification-Engineer--Digital-IP_R-10063872", "is_hardware": true, "platform": "workday", "jd_text": "IP verification engineer\nIn this role you will be responsible for verifying complex IPs and subsystems involving RISCV CPU cores, memory controllers, and interconnects, collaborating with global design and architecture teams.\n \nJob Responsibility: \nResponsible for the pre-silicon verification of IP modules or, IP subsystems\nResponsible for defining and writing IP verification plans based on requirements documents (industry standards, product requirements, IP architecture and IP implementation specifications)\nInterface to HW, FW, and SW design teams, as well as to architecture and system engineering teams, to understand functionality and application of the IP or subsystem.\nResponsible for executing verification plan according to the product specification and verification requirements defined by product architects.\nResponsible for architecting, developing, debugging and running UVM based verification environment for RTL simulation.\nDefine and develop test cases in an appropriate verification framework. Create stimulus and assertions, run simulation, debug test cases on the design models (RTL, power aware RTL, gate level, FPGA, Emulation platform), run regression, collect and analyze code/functional coverage.\n\nJob Qualification:\nDegree in Electrical Engineering or Computer Science, with 5+ years of experience on IP/Sub-System Verification\nProven experience in testbench design and development using UVM methodology for IP/Subsystem and SOC.\nExperience in Microcontroller and Microprocessor architecture, Interconnect, Cache Coherency.\nExperience in protocols like AHB/AMBA, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers.\nAdvanced knowledge of Verilog, System Verilog, C/C++, Shell.\nGood knowledge in scripting like Perl, TCL or Python is a plus\nHigh proficiency in Metric Driven Verification concepts, functional and code coverage.\nHigh proficiency in directed and constrained random methodologies.\nGood knowledge of formal verification methodologies and assertions.\nExperience with debugging of designs pre- and post-silicon, in simulation and on the bench.\nExcellent written and verbal communication skill. \n\nMore information about NXP in India...\n\n#LI-29f4", "jd_status": "stored"}, {"title": "Senior Principal GPU verification Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-06-16", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/GPU-verification-lead_R-10063868", "is_hardware": true, "platform": "workday", "jd_text": "GPU verification lead\nIn this role you will be responsible for verifying complex GPU IPs and subsystems, ensuring functional correctness, performance, and first-pass silicon success, collaborating with global design and architecture teams\n\nKey responsibilities\nDevelop and execute verification plans for GPU IP blocks (vector graphics, shader cores, memory interfaces and caches)\nBuild scalable SystemVerilog/UVM-based verification environments with reusable UVM components (agents, monitors, scoreboards)\nDevelop models for GPU command processing, memory transactions and cache coherency\nLead and mentor junior verification engineers\nOwn end-to-end IP verification sign-off\nManage regressions and debug failures\nTrack coverage metrics and verification closure\n\nRequired expertise\nExperience: 13+ years\nStrong experience in SystemVerilog, UVM, and Verilog\nGood understanding of Functional verification methodologies\nAssertions (SVA) and coverage\nExperience debugging complex RTL and testbench issues\nExperience in Formal verification is an added plus\n \n\nMore information about NXP in India...\n\n#LI-29f4", "jd_status": "stored"}, {"title": "Principal IP verification engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-06-16", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/IP-verification-engineer_R-10063870", "is_hardware": true, "platform": "workday", "jd_text": "IP verification engineer - Principal\nIn this role you will be responsible for verifying complex IPs involving memory controllers, and interconnects, collaborating with global design and architecture teams.\n\nKey responsibilities\nDevelop and execute verification plans for memory controllers, interconnects and other infrastructural IPs\nBuild scalable SystemVerilog/UVM-based verification environments with reusable UVM components (agents, monitors, scoreboards)\nOwn end-to-end IP verification sign-off\nAchieve high-quality metrics including functional coverage and code coverage\nManage regressions and debug failures\nCollaborate closely with design teams to resolve issues\nRequired expertise\nExperience: 10+ years\nStrong experience in SystemVerilog, UVM, and Verilog\nGood understanding of Functional verification methodologies, Assertions (SVA) and coverage\nGood understanding of interconnect protocols such as AXI, AHB, CHI and PCIE\nExperience debugging complex RTL and testbench issues\nExperience in Formal verification is an added plus\n \n\nMore information about NXP in India...\n\n#LI-29f4", "jd_status": "stored"}, {"title": "Lead Standard cell design/characterization Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-06-16", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Lead-Standard-cell-design-characterization-Engineer_R-10063683", "is_hardware": true, "platform": "workday", "jd_text": "Job Overview\nNXP-CTO/DE/FDIP/Logic Library Team is responsible for all the standard Cell library solutions (Differentiated IP augmentation along with internalization for 3rd party library Ips). Consultancy to design teams on Reliability, DfT, Timing Closure, etc.\n\nJob qualification:\nExperience in Standard Cell Circuit design, Characterization and/or Layout design of various Standard cells and Macros (viz. flip flops, latches, multibit flip flops, level shifters, Power Switch Cells, Retention flops, Synchronizer cells etc.) in planer and non-planar technology nodes.\n\nAt least 7-9 years of experience in StdCell domain\n\nAIML/Agentic AI literacy\n\nWork involved is Characterization, Layout design and EDA development of StdCells.\n\nOverview and good understanding of Circuit and MC simulations, Layout Dependent Effects and overall RTL2GDS flow (STA, PnR).\n\nGood understanding of CMOS and FinFET technologies.\n\nGood understanding and expertize in using of State-of-the-art EDA tools from Siemens, Cadence and Synopsys for simulations, characterization, and layout developments.\n\nContribute in the improvement/development of circuit design, Characterization of StdCell libraries.\n\nImplement Innovative solutions within Standard cell library development domain.\n\nDevelop EDA views including Characterization of NLDM, CCSP. CCSN and AOCV, LVF for standard cell libraries\n\nExposure to AOCV, LVF model characterization is plus.\n\nWorking knowledge in MS Excel, PowerBI and/or Tableau could be an added advantage.\n\nWorking Knowledge of SKILL / Python / TCL / PERL scripting could be an added advantage.\n\nMore information about NXP in India...\n\n#LI-7013", "jd_status": "stored"}, {"title": "Staff Systems Engineer (Timing IC-Validation)", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-06-16", "url": "https://careers.skyworksinc.com/job-invite/77771/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 77771\n\nAbout Skyworks\n\nIf you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high-performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out of the box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nSkyworks offers the industry’s broadest Timing product portfolio of crystal oscillator, clock generator, clock buffer, jitter attenuator and network synchronizer products. Our patented technology combines best-in-class frequency flexibility with the lowest jitter in the industry, delivering quick-turn, customized solutions that simplify board design, eliminate discrete components, and maximize system performance.\n\nPosition Overview\n\nThe IC Validation team leads all post-silicon activities, including chip bring-up, validation, and characterization of new timing devices. You will play a key role in our New Product Introduction (NPI) cycle, as our products cross from pre-silicon design to post-silicon validation to ensure exceptional product quality and performance. In this role, the ability to quickly debug and resolve performance issues will be critical to delivering world-class products to our customers.\n\nWe seek candidates who demonstrate a passion for learning, initiative, curiosity, and engineering ingenuity. A positive attitude and a strong disposition for teamwork are essential.\n\nPosition Responsibilities\n\nSupport our Timing Design team based out of the Skyworks Bangaluru office with new IC bring-up, validation, and characterization.\n\nTest and debug system and block functionality of new timing ICs.\n\nPerform silicon characterization through the development of robust and reusable tests to determine device datasheet specifications\n\nLead the design and development of high-speed PCBs (EEVBs), including discrete analog circuits, used for validation and characterization.\n\nAssemble and maintain test setups in the laboratory to support validation and characterization.\n\nDefine, develop, and/or acquire software and/or hardware tools in support of silicon test efforts.\n\nDevelop automation scripts to automate data collection, decrease data collection times, ensure repeatable measurements, and generate reports.\n\nOwn post-processing the characterization data, conducting a detailed analysis (we use JMP for this purpose), and then reviewing the analyzed data with the IC design and marketing teams.\n\nRequired Experience and Skills\n\nBachelor’s in Electrical Engineering with 8+ years of relevant experience, or a Master’s with 6 years of experience.\n\nStrong EE fundamentals; experience with PLLs, synthesizers, and jitter strongly preferred\n\nBackground in validation, test, or characterization of IC devices\n\nExtensive hands-on experience with lab instrumentation (oscilloscopes, signal generators, spectrum/phase noise analyzers, power supplies, etc.)\n\nAbility to troubleshoot and debug hardware and software\n\nExperience developing automated test systems and validation infrastructure\n\nProficiency in programming for test/automation (Python, .NET preferred, or similar)\n\nExperience with test frameworks and data analysis tools (JMP, MATLAB, or equivalent)\n\nExcellent communication skills, with the ability to convey complex technical concepts to cross-functional teams\n\n \n\n#LI-CB1\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Principal  Analog Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-06-16", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505289", "is_hardware": true, "platform": "oracle", "jd_text": "Description for Internal Candidates    \n\n  onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nonsemi’s Core-Analog IP Center of Excellence is hiring an experienced Analog IC design engineer to help us develop IP for next generation Automotive, Industrial & Medical products. The successful candidate will participate in the design of complex CMOS integrated circuits and have familiarity with analog blocks such as bandgaps, amplifiers, filters, precision comparators, LDOs, oscillators, PLLs etc. Experience with signal chain optimization is highly desired.\n\n#LI-VS1\n\nResponsibilities\nKey Duties & Responsibilites\nMust have a working knowledge of Cadence Circuit design tools.\n12-15 years of relevant experience or Ph.D. in Electrical Engineering with 10-12 years of relevant experience in analog circuit design.\nAnalytical approach to problem solving is required. CMOS designs provide challenging learning opportunities where performance, power and reliability are all pushed to the limit while maintaining product execution schedule.\nDrive development and verification of state-of-the-art analog blocks and mixed signal CMOS designs which can be reused across different market segments.\nParticipate in analog circuit requirements discussions, technical issues and other design aspects to arrive at agreed upon product specifications.\nBuild/develop circuits based on an IP specification, drive the layout design and final IP characterization.\nExecute state-of-the-art analog designs while following the best design practices with on time quality design releases.\nPropose innovative and creative solutions where necessary to meet customer & product needs.\nWork diligently with the  given requirements to accomplish project goals and meet schedule requirements.\nDebug of complex integrated circuit problems in the laboratory. Collaborate in debug efforts as needed.\nPerform bench characterization and support application engineering bench evaluation efforts.\nAnalyze design aspects related to DFT and collaborate with other team members to develop DFT strategy for block designs.\nDocument designs including architecture and circuit descriptions, testing procedures, and safety mechanisms.\nInterface with test, product, and applications engineering to drive the design to a successful production release.\n#LI-VS1\n\nQualifications\nRequirements    \nAnalog design experience in verification, documentation, and post-silicon validation. Includes broad understanding of integrated circuit design such as amplifiers, filters, BGAP circuits, oscillators etc.\nIn-depth knowledge of semiconductor devices like MOS transistors, BJTs etc.\nKnowledge with behavioral top-level modeling and mixed signal verification methodology.\nKnowledge of UNIX/Linux working environment\nKnowledge of multiple semiconductor design tools like Matlab, Spectre, Spice, Cadence design environment. AMS simulation experience is a plus.\nExcellent written and oral communication.\nProven ability to work independently and in teams.\nHands-on experience in a lab environment working with sensitive measurement equipment and data acquisition.\nVery good debugging ability in circuit operation, and device function\nMaster’s degree in Electrical Engineering with  12+ years of relevant experience or Ph.D. in Electrical Engineering with  10+ years of relevant experience in analog circuit design.\n#LI-VS1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Senior Digital IP Design Manager", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-06-16", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505674", "is_hardware": true, "platform": "oracle", "jd_text": "Job Description Job Summary: Sr/ Digital IP Design Manager\n\nLocation: Bangalore, India\nCompany: onsemi\n\nRole Overview onsemi is seeking a Digital IP Design Manager to manage the design of digital datapath and subsystem IP for next-generation CMOS image sensors and the onsemi Treo platform. This role will manage a talented sub-team of digital design engineers, drive technical execution, and help shape the future of scalable, automotive‑grade digital IP design.\n\n  The ideal candidate combines strong hands-on digital design expertise with necessary experience of people leadership, and a forward-looking mindset, including curiosity around how AI and automation can improve digital design productivity and cycle time.\n\nResponsibilities Key Responsibilities Technical Leadership \n\nLead the design of digital datapath IP and modules for CMOS image sensors, including high‑performance, low‑power pipelines. \n\nDrive development of core platform digital-on-top and subsystem IP for the onsemi Treo platform. \n\nEnsure IP meets automotive quality, safety, and reliability requirements (e.g., robustness, configurability, reuse). \n\nPartner closely with architecture, DV, PD, analog, mixed-signal, system, full-chip integration, firmware, and software teams to deliver end-to-end solutions.  \n\nProvide technical guidance on RTL quality, low-power design, clocking/reset strategies, and design-for-test to design engineers. \n\nParticipate in technical reviews, risk assessment, and post-silicon learning. \n\nTeam & People Management \n\nLead and mentor talented digital IP designers. \n\nBring quality, flow and schedule focus to the team.\n\nFoster collaboration, accountability, innovation and continuous improvement. \n\nInnovation & Productivity \n\nStay curious and engaged with emerging trends, especially AI/ML-driven approaches to:\n\nRTL generation and review\n\nIntegration and Si debug productivity\n\nDesign-space exploration\n\nChampion adoption of tools and processes that reduce cycle time and improve first-time-right outcomes\n\n#LI-VS1\n\nResponsibilities\nPreferred / Nice-to-Have Qualifications \nExperience with CMOS image sensor digital pipelines or imaging-related IP. \nFamiliarity with platform or subsystem-level IP development. \nExposure to functional safety concepts relevant to automotive products. \nExperience driving or adopting EDA automation, scripting, or AI-assisted workflows. \nPrior experience scaling or building a new team. \n#LI-VS1\n\nQualifications\nQualifications Required Qualifications \n12+ years of overall experience in digital IC design. \n3+ years of proven people management or technical leadership experience. \nStrong background in digital IP or SoC development. \nExperience working on Automotive IP or automotive semiconductor products. \nHands-on experience with:RTL design (SystemVerilog / Verilog)\nLow-power design techniques\nIP reuse and configurability\n\nDemonstrated ability to lead cross-functional technical efforts. \nStrong communication skills and the ability to influence across teams and geographies.\n#LI-VS1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Sr. Systems Engineer (Timing IC-Validation)", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-06-16", "url": "https://careers.skyworksinc.com/job-invite/77773/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 77773\n\nAbout Skyworks\n\nIf you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high-performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out of the box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nSkyworks offers the industry’s broadest Timing product portfolio of crystal oscillator, clock generator, clock buffer, jitter attenuator and network synchronizer products. Our patented technology combines best-in-class frequency flexibility with the lowest jitter in the industry, delivering quick-turn, customized solutions that simplify board design, eliminate discrete components, and maximize system performance.\n\nPosition Overview\n\nThe IC Validation team leads all post-silicon activities, including chip bring-up, validation, and characterization of new timing devices. You will play a key role in our New Product Introduction (NPI) cycle, as our products cross from pre-silicon design to post-silicon validation to ensure exceptional product quality and performance. In this role, the ability to quickly debug and resolve performance issues will be critical to delivering world-class products to our customers.\n\nWe seek candidates who demonstrate a passion for learning, initiative, curiosity, and engineering ingenuity. A positive attitude and a strong disposition for teamwork are essential.\n\nPosition Responsibilities\n\nSupport our Timing Design team based out of the Skyworks Bangaluru office with new IC bring-up, validation, and characterization.\n\nTest and debug system and block functionality of new timing ICs.\n\nPerform silicon characterization through the development of robust and reusable tests to determine device datasheet specifications\n\nLead the design and development of high-speed PCBs (EEVBs), including discrete analog circuits, used for validation and characterization.\n\nAssemble and maintain test setups in the laboratory to support validation and characterization.\n\nDefine, develop, and/or acquire software and/or hardware tools in support of silicon test efforts.\n\nDevelop automation scripts to automate data collection, decrease data collection times, ensure repeatable measurements, and generate reports.\n\nOwn post-processing the characterization data, conducting a detailed analysis (we use JMP for this purpose), and then reviewing the analyzed data with the IC design and marketing teams.\n\nRequired Experience and Skills\n\nBachelor’s in Electrical Engineering with 5+ years of relevant experience, or a Master’s with 3 years of experience.\n\nStrong EE fundamentals; experience with PLLs, synthesizers, and jitter strongly preferred\n\nBackground in validation, test, or characterization of IC devices\n\nExtensive hands-on experience with lab instrumentation (oscilloscopes, signal generators, spectrum/phase noise analyzers, power supplies, etc.)\n\nAbility to troubleshoot and debug hardware and software\n\nExperience developing automated test systems and validation infrastructure\n\nProficiency in programming for test/automation (Python, .NET preferred, or similar)\n\nExperience with test frameworks and data analysis tools (JMP, MATLAB, or equivalent)\n\nExcellent communication skills, with the ability to convey complex technical concepts to cross-functional teams\n\n \n\n#LI-CB1\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Sr. Systems Engineer (Timing IC-Validation)", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-06-16", "url": "https://careers.skyworksinc.com/job-invite/77772/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 77772\n\nAbout Skyworks\n\nIf you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high-performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out of the box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nSkyworks offers the industry’s broadest Timing product portfolio of crystal oscillator, clock generator, clock buffer, jitter attenuator and network synchronizer products. Our patented technology combines best-in-class frequency flexibility with the lowest jitter in the industry, delivering quick-turn, customized solutions that simplify board design, eliminate discrete components, and maximize system performance.\n\nPosition Overview\n\nThe IC Validation team leads all post-silicon activities, including chip bring-up, validation, and characterization of new timing devices. You will play a key role in our New Product Introduction (NPI) cycle, as our products cross from pre-silicon design to post-silicon validation to ensure exceptional product quality and performance. In this role, the ability to quickly debug and resolve performance issues will be critical to delivering world-class products to our customers.\n\nWe seek candidates who demonstrate a passion for learning, initiative, curiosity, and engineering ingenuity. A positive attitude and a strong disposition for teamwork are essential.\n\nPosition Responsibilities\n\nSupport our Timing Design team based out of the Skyworks Bangaluru office with new IC bring-up, validation, and characterization.\n\nTest and debug system and block functionality of new timing ICs.\n\nPerform silicon characterization through the development of robust and reusable tests to determine device datasheet specifications\n\nLead the design and development of high-speed PCBs (EEVBs), including discrete analog circuits, used for validation and characterization.\n\nAssemble and maintain test setups in the laboratory to support validation and characterization.\n\nDefine, develop, and/or acquire software and/or hardware tools in support of silicon test efforts.\n\nDevelop automation scripts to automate data collection, decrease data collection times, ensure repeatable measurements, and generate reports.\n\nOwn post-processing the characterization data, conducting a detailed analysis (we use JMP for this purpose), and then reviewing the analyzed data with the IC design and marketing teams.\n\nRequired Experience and Skills\n\nBachelor’s in Electrical Engineering with 5+ years of relevant experience, or a Master’s with 3 years of experience.\n\nStrong EE fundamentals; experience with PLLs, synthesizers, and jitter strongly preferred\n\nBackground in validation, test, or characterization of IC devices\n\nExtensive hands-on experience with lab instrumentation (oscilloscopes, signal generators, spectrum/phase noise analyzers, power supplies, etc.)\n\nAbility to troubleshoot and debug hardware and software\n\nExperience developing automated test systems and validation infrastructure\n\nProficiency in programming for test/automation (Python, .NET preferred, or similar)\n\nExperience with test frameworks and data analysis tools (JMP, MATLAB, or equivalent)\n\nExcellent communication skills, with the ability to convey complex technical concepts to cross-functional teams\n\n \n\n#LI-CB1\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Principal Application Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-06-16", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Application-Engineer_R53452", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nLocation: Bangalore / Noida\n\nCadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.\n\nThe Cadence Advantage\nThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.\nCadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.\nThe unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success\nMultiple avenues of learning and development available for employees to explore as per their specific requirement and interests\nYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.\n\nJob Summary\nAs a senior member of the India Field Organization for the Digital and Signoff Group, you will partner closely with our top semiconductor customers to drive and build unique and innovative methodologies to implement cutting-edge designs. This involves working closely with the customers to understand their key challenges, develop efficient methodologies, help them leverage the latest tool capabilities, and guide them to achieve their design goals. You will have an opportunity to acquire both breadth and depth of technical knowledge, get wide exposure to the latest designs that customers are working on, and have the ability to influence at all levels, both internally and externally.\n\nThis role also provides a front-row opportunity to participate in the evolution of key technology solutions to the most pressing design problems. In this role, you will have the opportunity to work with product teams to influence product direction with your timely feedback and observations.\n\nIn addition to wielding technical influence, your unique understanding of the customer and their key careabouts will have a deep impact on the business strategy. You will collaborate closely with the sales teams to help drive account strategy and campaigns.\n\nThis an excellent opportunity to work in a supportive and friendly work environment, where we are vested in each other’s success, and are passionate about technology  and  innovation.\n\nJob Responsibilities\nIndependently drive RTL-to-GDSII metrics on complex designs\nDrive methodology and solution-oriented discussions with key stake holders\nPartner with sales team to help drive account strategy and campaigns\nEvangelize and drive adoption of new technology across customers\nProduce out-of-the-box solutions to customer problems using either tool capabilities or scripting techniques\nDeploy ML based Solutions to improve productivity and PPA\nNarrow down complex problems to pointed tool issues for R&D resolution\nCollaborate with worldwide AE teams and mentor junior team members\n\nQualifications\nBE/BTech/ME/MS/MTech in Electrical/Electronics\n\nExperience and Technical Skills required\n10+ years of experience in Digital Implementation flow on advanced nodes\nExpertise in one or more domains – Synthesis/PnR/STA\nKnowledge of scripting languages & Flow development is a big plus\nMust have excellent debugging skills and ability to separate out the critical issues from trivial ones.\n\nBehavioural skills required\nMust possess strong written, verbal and presentation skills\nAbility to establish a close working relationship with both customer peers and management\nExplore what’s possible to get the job done, including creative use of unconventional solutions\nWork effectively across functions and geographies\nPush to raise the bar while always operating with integrity\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Analog EDA Frontend Lead Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-06-16", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25011190", "is_hardware": true, "platform": "oracle", "jd_text": "EDA is a central organization in TI responsible for developing, deploying and supporting EDA methodology, tools, flows and solutions for worldwide TI Businesses. The EDA solutions span across different domains of IC development, covering IP and SoC development. The team supports all Analog and Embedded business groups across worldwide sites. The team’s charter includes definition of differentiated solutions by defining and developing in-house tools, flows and methodologies augmenting the tools available from EDA vendors. The team enables business teams succeed with best PPA and faster time to market deliveries.\n \nAs an Analog EDA Lead in the team, you will be working on below EDA solutions.\nWork with cross-functional teams within EDA and internal customers and stakeholders in IP and SoC design teams to define, evaluate, and ensure support new EDA solutions\nCollaborate with vendors (Cadence, Synopsys etc) in technical tool evaluations, intersect TI methodologies with vendor roadmaps and offer best solutions to worldwide TI teams.\nInterface between TI ATD teams, TI Foundry services team and external Foundry customers towards successful TI PDKs usage in Foundry design executions.\n \nMinimum Requirements:\nBachelor’s/Master’s degree in Electronics, Electrical Engineering or related field of study\n4-8 years of relevant EDA/CAD experience combined with a passion for automation\n2-3 years of technical lead as Analog Frontend\n\nQualifications\nPreferred Qualifications:\n\nGood CMOS circuits basics, analog circuits simulation and layout experience\n\nDemonstrated strong analytical and problem solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to work effectively in a fast-paced and rapidly changing environment\n\nAbility to take the initiative and drive to results\n\nSkills to manage time, delegate and multi-task at work\n\nStrong verbal and written communication skills\n\nMentoring and experience with people management will be added advantage\n\nTeam-work is imperative in this role\n\n \n\nPreferred Skills/ Experience\n\n4-8 years of experience in EDA/CAD in Backend Analog Design Tools (Virtuoso, Layout, DRC, LVS, Extraction, Basic simulation, etc )\n\nPrior experience for having interfaced with EDA vendors towards flow evaluations, licensing and roadmap definitions\n\nPrior experience in programming languages and technologies as needed for projects: Python, TCL, Cadence SKILL, Unix, Shell programming etc\n\nOptional: AI/ML solutions, Compute infrastructure, Data management\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Senior Lead Radar SW System Validation Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-06-16", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Senior-Lead-Radar-SW-System-Validation-Engineer_R-10063744", "is_hardware": true, "platform": "workday", "jd_text": "A Senior Validation Engineer responsible for leading validation activities, driving test automation, ensuring end-to-end validation coverage, and contributing to system-level quality improvements for radar and embedded platforms. The role requires a strong balance of test execution, automation, debugging, and technical ownership, along with the ability to collaborate across cross-functional teams.\nSkills & Expertise:\nTest execution and validation for embedded/radar systems\nExposure to Python-based automation frameworks\nHands-on experience with lab setup, hardware bring-up, and debugging\nExperience using measurement tools such as logic analyzers\nBasic knowledge of automotive radar validation (velocity, range, RF setups)\nFamiliarity with LabVIEW/TestStand environments\nStrong collaboration and coordination skills in cross-functional teams\nExperience supporting lab infrastructure, procurement, and test environment readiness\nLead and own validation for assigned modules/features, ensuring end-to-end test coverage from requirements to validation sign-off.\n\nDefine test strategies, test plans, and validation approaches aligned with product requirements.\nDrive improvements in test coverage, traceability, and execution efficiency.\nDesign, develop, and enhance automation frameworks (primarily Python-based) for validation workflows.\nDrive automation adoption across test cases, ensuring scalability, maintainability, and reusability.\nIntegrate validation frameworks into CI/CD pipelines and release validation flows.\nDomain Expertise :\nRadar System Validation & Analysis\nLead validation activities for automotive radar systems, including:Velocity, range, and angle validation\nRF test setups and antenna calibration\nProcessing chain validation and result analysis\n\nAnalyze complex validation failures and drive root cause investigation with development teams.\nContribute to improving validation methodologies for radar signal processing workflows.\nHardware & Test Infrastructure Leadership\nOwn lab infrastructure readiness including:Test bench setup and bring-up\nHardware configuration and integration\nValidation environment stabilization\n\nDrive improvements in test infrastructure reliability and scalability.\n Test Execution Excellence & Coverage Management\nEnsure high-quality test execution with accurate result validation and reporting.\nDrive:Test list consolidation\nTest synchronization across teams\nCoverage metrics tracking\n\nMentor junior engineers on test execution and best practices.\n\n#LI-DNI", "jd_status": "stored"}, {"title": "Senior IP Verification Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-06-16", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Verification-Engineer--Digital-IP_R-10063869", "is_hardware": true, "platform": "workday", "jd_text": "IP verification engineer\nIn this role you will be responsible for verifying complex IPs involving graphics pipelines, memory subsystems, and interconnects, collaborating with global design and architecture teams.\nKey responsibilities\nDevelop and execute verification plans for memory controllers, interconnects and other infrastructural IPs\nBuild scalable SystemVerilog/UVM-based verification environments with reusable UVM components (agents, monitors, scoreboards)\nOwn end-to-end IP verification sign-off\nAchieve high-quality metrics including functional coverage and code coverage\nManage regressions and debug failures\nCollaborate closely with design teams to resolve issues\nRequired expertise\nExperience: 6+ years\nStrong experience in SystemVerilog, UVM, and Verilog\nGood understanding of Functional verification methodologies, Assertions (SVA) and coverage\nGood understanding of interconnect protocols such as AXI, AHB, CHI and PCIE\nExperience debugging complex RTL and testbench issues\nExperience in Formal verification is an added plus\n \n\nMore information about NXP in India...\n\n#LI-29f4", "jd_status": "stored"}, {"title": "NPU AI/Processor Architectue(RTL) Design -Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-06-15T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718772108", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    5+ years of Hardware Engineering or related work experience.\n•    2+ years of experience with circuit design (e.g., digital, analog, RF).\n•    2+ years of experience utilizing schematic capture and circuit simulation software.\n•    2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Integrates features and functionality into hardware designs in line with proposals or roadmaps.\n•    Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues.\n•    Writes detailed technical documentation for Hardware projects.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making may affect work beyond immediate work group.\n•    Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. \n•    Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Lead Engineer - IP Design", "company": "NXP", "location": "Bangalore", "date_posted": "2026-06-15", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Senior-Lead-Engineer---IP-Design_R-10063536-1", "is_hardware": true, "platform": "workday", "jd_text": "Job Opportunity: Seeking highly motivated, energetic, team-oriented person driving roadmaps for IP / Subsystem domain including complete IP portfolio, going deeper into logic design and architecting and developing Complex IPs / Subsystems solutions.\nWorking closely with experienced and motivated team of Global experts in Systems, SoC Design functions to lead or address the design/architectural challenges in the context of the complex IP and overall System level solutions. Work through a wide spectrum of skill from developing High level Specifications to actual design Implementation.\n\nKey Responsibilities\n \nOwn and drive Roadmaps for complete IP / Subsystem domains portfolio within global R&D team.\nPerform benchmarks against other industry players and ensure differentiating features for our customer with high level of innovation.\nArchitect and Design complex IP and Subsystems across a range of protocols required for Edge processing and Automotive Self Driving Vehicles, In-Vehicle experience, Gateway Systems, Fail Safe Subsystems (ASIL-D) etc.\nOwn, Lead an Drive IP / Subsystem from Concept till IP Design and Development achieving final design performance in integrated system within aggressive, market driven schedules.\nEnsure quality adherence during all stages of the IP development cycle and carry out a thorough analysis of existing processes, recommend and implement the process improvements to ensure ‘Zero Defect’ designs and drive and mentor teams towards that.\nOwn and Drive global IP design methodologies across sites with global stakeholders.\n \nKey Skills\nSelf starter with 8 to 12 years of experience to Architect and Design complex IP design / Sub-system with minimal supervision.\nExperience in High Speed Serial protocols and associated high speed challenges on controller and PHY for PCIe, Ethernet & Serdes\nUnderstanding of key External Memory interface protocols including DDR4 / LPDDR4, QuadSPI Flash interfaces.\nExperience in microcontroller architecture, bus protocols like AHB/AMBA,AXI.\nExtensive hands on knowledge of HDLs (Verilog/VHDL), Scripting languages (Perl, Tcl), C/C++ for hardware modeling.\nUnderstanding of end to end IP development flow including complex CDC, RDC constructs, IP Synthesis, DFT ATPG coverage.\nHave worked on Testbench and Testplan development closely with the verification team.\nHands on work on pre silicon validation using FPGA/Emulation Board would be a significant added advantage.\n\nKey Soft Skills\n\nProficient skills in both written and verbal communication. Can articulate well. \nHas a sense of Ownership and engages everyone with Trust and Respect. \nShould demonstrate Emotional Intelligence and Leadership values with ability to work well as a part of team both local and remote or multisite.\n\nMore information about NXP in India...\n\n#LI-2734", "jd_status": "stored"}, {"title": "Staff Engineer, Digital Design Engineering", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-06-15", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Staff-Engineer--Digital-Design-Engineering_R263148", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nStaff Digital Design Engineer\n\nCome join Analog Devices (ADI) – a place where Innovation meets Impact. For more than 55 years, Analog Devices has been inventing new breakthrough technologies that transform lives. At ADI you will work alongside the brightest minds to collaborate on solving complex problems that matter from autonomous vehicles, drones and factories to augmented reality and remote healthcare.\n\nADI fosters a culture that focuses on employees through beneficial programs, aligned goals, continuous learning opportunities, and practices that create a more sustainable future. \n\nADI At A Glance\n\nAnalog Devices operates at the center of the modern digital economy, converting real-world phenomena into actionable insight with its comprehensive suite of analog and mixed signal, power management, radio frequency (RF), and digital and sensor technologies. ADI serves 125,000 customers worldwide with more than 75,000 products in the industrial, communications, automotive, and consumer markets. ADI is headquartered in Wilmington, MA. Visit http://www.analog.com. \n\nDescription:\nThe Digital IP team within Analog Devices Inc. is responsible for developing, curating, and providing reusable strategic IPs to Business Units to accelerate product development across the company. The team is looking for an experienced Digital Design Staff Engineer / Lead who will be responsible for providing technical leadership to the digital design team, while managing IP development and delivery.\n\nThe ideal candidate would be someone with strong technical background combined with management acumen and demonstrable ability to handle ambiguity while still finding creative ways to make things happen.\n\nA key focus area for this position includes interacting and engaging with internal customers to communicate, identify, improve, and maintain developed IP, as well as scout for 3rd party IPs and evaluate them on a regular basis for future requirements.\n\nJob Responsibilities:\nProvide technical leadership and mentorship to digital design engineers across CDC, low‑power design, synthesis and timing closure, DFT improvements, and silicon debug\nArchitect and design key digital blocks (accelerators, datapath IPs) in Verilog/SystemVerilog with configurability to optimize Power, Performance, and Area (PPA)\nDemonstrate deep understanding of heterogeneous processor subsystems (A55, M55, M4, U55, RISC‑V, DSP) and supporting infrastructure including caches, interconnects, GIC, DMA, MMU, CoreSight debug/trace, TZC, SMPU, and SPU\nCollaborate closely with product teams, program managers, and leadership to align schedules, milestones, commitments, and deliverables\nDrive adoption of AI tools (e.g., Copilot and approved third‑party tools) to improve efficiency and accelerate execution\nBuild and lead expertise in complex interfaces and protocols including DDR, Ethernet, eMMC/SD, MIPI, DisplayPort, HDMI, PCIe, and high‑speed D2D\nDrive development of IP‑centric design management infrastructure and flows across Methodics, Perforce, GitHub, and IP catalog systems\nDevelop and maintain a digital IP catalog to enable efficient information sharing and reuse across business units\nPackage digital IPs for seamless integration across design stages, including RTL, constraints, CDC and timing waivers, DFT DRCs/waivers, and software programming sequences\nConduct detailed design reviews and enforce adherence to quality metrics and best practices\nLead evaluation of third‑party IPs on PPA, design quality, DFT robustness, DV maturity, and integration ease; provide clear recommendations\nEstablish consistent benchmarking and evaluation flows for in‑house and third‑party IPs\nManage and streamline consolidation and curation of digital IP assets, including standard peripherals, processor cores, and high‑speed interface IPs\nReduce complexity and ambiguity across teams and processes by distilling technical detail into clear, actionable guidance and recommendations\n\nPosition Requirements:\nMinimum B.E. /B. Tech degree in Electrical/Electronics/Computer science\n12+ years of relevant experience with a strong focus on definition/ architecture/ u-arch/ design and hands-on RTL coding experience using Verilog and System-Verilog\nStrong understanding of all aspects of ASIC/SoC product development incl Design Verification/ timing constraints/ closure, physical implementation, quality assurance flows with hands-on prior experience in a few of these aspects\nProven experience in managing/ handling large complex hardware projects in lead role\nStrong understanding of control path and data-path digital design concepts with an eye for realizing correct by construction solutions\nExperience with specifying Design Verification (DV) requirements such as test plans, coverage metrics, and evaluate DV quality so as to realize robust design quality\nStrong knowledge of Lint, CDC, formal equivalence, DFT concepts, power analysis, low power design\nExperience with developing timing constraints and ability to carry out logic synthesis and Static timing analysis\nAbility to technically mentor a large digital design team\nGood interpersonal, teamwork and communication skills to drive discussions logically & effectively with teams spread geographically\nStrong understanding of standard on-chip interfaces such as APB/AHB/AXI/ Stream protocols\nKnowledge of Processor/SoC architecture and/or DSP fundamentals\nServe as the focal point for communications. Compile regular status updates for all stakeholders and effectively escalate critical issues and risks as necessary\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Engineering Manager 2", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-06-15", "url": "https://careers.skyworksinc.com/job-invite/77662/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 77662\n\nDescription\n\nThe candidate will help staff, and lead MSB’s IC Verification Team in Bengaluru with a mission of building a strong team focused on chip-level verification. This team will be a key part of our Mobile Solutions Business, which consists of highly integrated front end modules that integrate Filters, Switches, LNAs, and matching in densely packed & complex front-end modules for Cellular and WiFi applications. The team will work directly and closely with design teams in the US.\n\n  \n\nAs the Verification manager, you will be responsible for a team of engineers driving chip top level verification. You and your team will engage in frequent technical meetings and design reviews with chip leads and counterparts abroad.  \n\n \n\nIn this position, you have the opportunity to make uniquely large impact on the success of the company and will have visibility at the highest levels of the company.\n\n \n\nWe are looking for a passion to win/contribute and ability to work in, and thrive in, a fast-paced dynamic team environment.\n\nResponsibilities\n\nThe candidate will report to the Engineering Director locally and have a team of Engineers reporting to them. These Engineers will have a matrix reporting structure to various teams in US leading IC design. \n\n \n\nResponsibilities will include, but not be limited to:\n\nRecruiting & Staffing:\n\nJointly drive staffing & recruiting with HR to ensure a world-class team is brought together to execute on complex, highly critical programs.\n\nTechnical Leadership:\n\nAct as the IC Verification & Technical Leader for a team focused on the verification of RFICs that are integrated into our complex front-end modules\n\nExperience managing large technical teams\n\nA track record of growing successful design teams\n\nAbility to set & articulate clear goals and drive accountability to those \n\nUse of AI tools to improve productivity, efficiency, automation, bug-tracking and reporting\n\nCommunication:\n\nDrive company communications, strategy, and goals via team meetings and regular 1:1 and reporting to chip leads and managers in the US.\n\nTravel to US will be required from time to time\n\nRequired Experience and Skills\n\nThe candidate must have excellent written and spoken communications, sufficient to present program technical status & schedule progress to senior management.\n\nTechnical requirements:\n\nStrong experience with the Cadence suite of EDA tools\n\nDeep and broad expertise in functional AMS verification of RFICs including RF/Analog/Digital content\n\nDevelop and maintain verification plans, strategies and methodology\n\nPerform functional, behavioral and regression verification\n\nCollaborate with RF designers and chip leads for successful tapeout and release of products to guarantee first-pass success\n\nAutomate verification flows and reporting infrastructure\n\nStrong debug and root-cause analysis skills\n\nCircuit Analysis:\n\nUnderstanding of analog blocks including low bit count data converters (ADC & DAC blocks), Bandgaps, Op-Amps, Bias blocks, Charge-pumps, Temp sensor, LDO, ESD, e-fuse and other supporting cells.\n\nKnowledge of RF SOI technology including RF switch, tuning & RF LNA design.\n\nDigital Design including SPI & MIPI interface design, Decoding logic, and simple state machines.\n\nSemiconductor device and process knowledge including SOI, bulk CMOS, SiGe.\n\nMinimum Requirements\n\nBSEE; MS preferred\n\n10+ years of IC Design/Verification experience\n\n6+ years of Technical Leadership and Management experience\n\n#LI-PR1\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Sr. Manager, Engineering", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-06-15", "url": "https://careers.skyworksinc.com/job-invite/77661/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 77661\n\nDescription\n\nThe candidate will help staff, and lead MSB’s Analog/RF Design Team in Bengaluru with a mission of building a strong team focused on RF/Analog IC design. This team will be a key part of our Mobile Solutions Business, which consists of highly integrated front end modules that integrate Filters, Switches, LNAs, and matching in densely packed & complex front-end modules for Cellular and WiFi applications. The team will work directly and closely with design teams in the US.\n\n  \n\nAs the Analog/RF manager, you will be responsible for a team of engineers driving IC block-level designs and layout. You and your team will engage in frequent technical meetings and design reviews with chip leads and counterparts abroad.  \n\n \n\nIn this position, you have the opportunity to make uniquely large impact on the success of the company and will have visibility at the highest levels of the company.\n\n \n\nWe are looking for a passion to win/contribute and ability to work in, and thrive in, a fast-paced dynamic team environment.\n\nResponsibilities\n\nThe candidate will report to the Engineering Director locally and have a team of Engineers reporting to them. These Engineers will have a matrix reporting structure to various teams in US doing IC design. \n\n \n\nResponsibilities will include, but not be limited to:\n\nRecruiting & Staffing:\n\nJointly drive staffing & recruiting with HR to ensure a world-class team is brought together to execute on complex, highly critical programs.\n\nTechnical Leadership:\n\nAct as the IC Design & Technical Leader for a team focused on the design of complex front- end modules\n\nExperience managing large technical teams\n\nA track record of growing successful design teams\n\nAbility to set & articulate clear goals and drive accountability to those \n\nUse of AI tools to improve productivity, efficiency, automation, bug-tracking and reporting\n\nCommunication:\n\nDrive company communications, strategy, and goals via team meetings and regular 1:1 and reporting to chip leads and managers in the US.\n\nTravel to US will be required from time to time\n\nRequired Experience and Skills\n\nThe candidate must have excellent written and spoken communications, sufficient to present program technical status & schedule progress to senior management.\n\nEDA & Software tools:\n\nStrong experience with the Cadence suite of EDA tools\n\nKnowledge of commonly used IC layout tools\n\nKnowledge of 2D/3D EM simulation tools\n\nExperience with PVT and statistical simulations\n\nCircuit Design:\n\nBroad and deep expertise in core Analog Design including low bit count data converters (ADC & DAC blocks), Bandgaps, Op-Amps, Bias blocks, Charge-pumps, Temp sensor, Clock and timing, LDO, ESD, e-fuse and other supporting cells.\n\nGood understanding of RF SOI technology including RF switch, tuning & RF LNA design.\n\nBasic Digital Design including SPI & MIPI interface design, Decoding logic, and simple state machines.\n\nSemiconductor process knowledge including SOI, bulk CMOS, SiGe.\n\nMust understand the basic device physics, ability to develop and use advanced linear and nonlinear models or simulation techniques and be able to translate between the model, simulation, physical implementation, and the measured performance of a device\n\n \n\nWorking knowledge of RF multi-chip modules including 3D Packaging, assembly, thermals and EMI basics.\n\nKnowledge of test equipment and common tests and parameters\n\nMinimum Requirements\n\nMinimum Requirements:          \n\n \n\nBSEE; MS preferred\n\n10+ years of IC Design experience\n\n6+ years of Technical Leadership and Management experience\n\n \n\n#LI-PR1\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Principal Engineer, Design Verification", "company": "Analog Devices", "location": "India, Bangalore, Nova", "date_posted": "2026-06-14", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-Nova/Principal-Engineer--Digital-Design-Engineering_R258366", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nJob Summary\nWe are seeking a highly experienced Principal Verification Engineer to lead and drive functional verification for complex ASIC/SoC designs. This role requires deep technical expertise, strong architecture-level thinking, strong understanding of Ethernet specifications, and the ability to mentor teams while ensuring delivery of high-quality silicon. The ideal candidate will own verification strategy end-to-end and work closely with design, architecture, and post-silicon teams. The candidate will play a key role in ensuring standards compliance, performance, interoperability and robustness of ethernet products.\nKey Responsibilities\nTechnical Leadership\nDefine and own verification strategy and methodology (UVM/SystemVerilog) at IP, subsystem, and SoC levels\nThoroughly understand and interpret Ethernet and related protocol specifications (IEEE standards, architecture specs, and micro-architecture documents) and translate them into comprehensive verification plans, assertions, and test scenarios\nArchitect scalable verification environments, reusable VIPs, and checkers\nDrive coverage-driven verification, including functional, code, and assertion coverage\nLead verification planning, testbench architecture, and test plan sign-off\nIdentify, Review and guide complex test scenarios and corner cases\nExecution & Quality\nEnsure first-pass silicon success through rigorous functional and protocol compliance verification\nDrive bug triage, root-cause analysis, and closure across IP, Subsystem and SoC levels\nDefine and track verification metrics, quality KPIs, and sign-off criteria\nValidate performance, stress, and corner scenarios such as congestion, backpressure, and error injection\nSupport emulation, FPGA prototyping, and post-silicon validation for Ethernet bring-up and debug\nCross-Functional Collaboration\nWork closely with architecture, RTL, DFT, physical design, firmware, and software teams\nProvide early verification input during architecture and micro-architecture definition, especially around standards compliance and performance assumptions\nCollaborate with software teams on driver, firmware, and traffic validation\nMentorship & Process\nMentor and technically guide verification engineers across experience levels\nEstablish and enforce verification best practices and coding standards\nDrive continuous improvements in verification flows, reuse, and productivity\nRequired Qualifications\nBachelor’s or Master’s degree in Electrical/Electronics Engineering or related field from reputed college\n10+ years of experience in ASIC/SoC design verification\nStrong hands-on expertise in SystemVerilog, UVM, and SVA\nStrong understanding of Ethernet architecture and protocols (MAC, PCS, PHY interfaces)\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Senior Design Verification Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-06-14", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25008907", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n  Texas Instruments is seeking Design Verification Engineer. In this role you will confirm the accuracy of designs for analog and mixed signal electronic parts, components, or integrated circuitry for analog and mixed signal electronic equipment and other hardware systems before pattern generation/mask development. The role will require working independently from the product development team who designed the devices to confirm adherence to known design rules, procedures, and best practices. Additional job functions include analyzing equipment to establish operating data and conducting experimental tests and evaluating results to confirm the device meets all requirements in the specifications. You may also run software simulations, selecting components and equipment based on analysis of specifications and reliability. As a Design Verification Engineer you may also review vendor capability to support product development. Requires a BS degree or equivalent experience in the design of equipment, components or circuitry.\n\n   \n\n \n\nThe Ethernet product team (part of High Speed Data Org) at Texas Instruments' Bangalore site designs and delivers advanced Ethernet PHY devices, serving critical Industrial (Std.) and Automotive applications. The team has a track record of delivering successful family of products catering to 10Mbps,100Mbps, 1Gbps for both Standard Ethernet and Single pair Ethernet (SPE) for Automotive standards.\n\nThe DSP data path is at the core of the Ethernet PHY and implements the functions of equalization, echo cancellation, data recovery and symbol timing recovery. Crucial for a stable connection, Ethernet PHY training necessitates the challenging joint convergence of various feedback loops inside the DSP. The design team drives innovation in design and digital verification (DV), leading to robust link performance metrics such as link up time, link stability, BER.\n\n \n\nThe team also develops the architecture for, and efficiently implements, Forward Error Correction (FEC) schemes (Viterbi algorithm, Reed-Solomon (RS) decoding).\n\nFurthermore, the team specializes in implementing solutions that ensure robust electromagnetic interference (EMI) and electromagnetic compatibility (EMC) performance.\n\n \n\nJob Description:\n\n               We are looking for a motivated and technically strong Design Verification (DV) Engineer to join the High-Speed Data (Ethernet) development team. The ideal candidate will lead chip-level DV, that requires creating test benches, simulation and validation of complex systems in which the signal processing (DSP) data path is the core component.\n\nHe / She will lead and participate in Module level DV using Matlab generated vectors, DUT level DV and system level DV involving 2 or more DUTs.\n\nHe / She will lead the Analog and channel model development for FPGA emulation. This involves (i) Coming up with suitable architecture for building synthesizable channel models, (ii) Bringing up the FPGA synthesis and (iii) Verify design as well as system performance (BER, SNR etc.) in FPGA platforms and automate DV regressions and the analysis of results.\n\nHe / She will closely work with the digital and analog design team members in pre-silicon verification of next-generation products. Towards the end of the PG cycle, he will bring up the GLS to sign off and to estimate digital power consumption.\n\n \n\nKey Responsibilities:\n\nStudy specifications, review design (RTL) to come up with test-cases for coverage.\n\nDevelop test-benches for Module level, DUT level and system level verification.\n\nOwn critical features, Lead the debug effort to ensure quality.\n\nWork on FPGA-based emulation / prototyping for design validation and performance evaluation.\n\nLead the Synthesizable Modeling effort for Analog & Channel Models.\n\nAnalyze simulation/emulation results and provide insights to improve design quality.\n\nDocument models, assumptions, and results clearly.", "jd_status": "source_unavailable"}, {"title": "Senior Physical Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-06-14", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25007629", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \nIn this position, you will be working on high-speed mixed-signal communication circuits using state-of-the art process technology, as well as be involved in the design of high performance digital circuits interfacing to leading edge analog circuitry as part of an overall system.\n\nYour responsibilities will include RTL coding, simulation, synthesis, timing closure, verification, evaluation, debugging of high-speed communication chips both at the circuit level and behavioral level.\n\nAs a design engineer, you will prepare test methods and specifications, assist in preparation of application information, data sheets and demo boards. You will develop solutions to complex problems through assessment of various techniques and approaches. You will plan and organize work to ensure timely completion of many independent tasks with general instructions on routine tasks and with detailed instructions on new assignments.\n\nThis position involves routine communication with a highly talented team of analog and digital design engineers to solve problems and present information as well as active participation in work groups, providing ideas and collaborative teamwork.\n\nQualifications\nMinimum requirements:\n\n2+ years of relevant experience\n\nA thorough understanding of digital logic design\n\nFamiliarity with the Verilog language and simulators\n\nA good understanding of analog functionality and exposure to analog IC design methods\n\nAbility to solve problems using a systematic approach\n\nPreferred qualifications:\n\nExperience with System Verilog\n\nDemonstrated strong analytical and problem solving skills\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nStrong time management skills that enable on-time project delivery\n\nDemonstrated ability to build strong, influential relationships\n\nAbility to work effectively in a fast-paced and rapidly changing environment\n\nAbility to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "refreshed"}, {"title": "Staff Engineer Design", "company": "Infineon", "location": "Bangalore (India)", "date_posted": "2026-06-12T13:43:12+00:00", "url": "https://jobs.infineon.com/careers/job/563808970728440", "is_hardware": true, "platform": "eightfold", "jd_text": "#WeAreIn to transform theoretical concepts into real hardware designs. Are you in?\n\nYour Role\nKey responsibilities in your new role\nDevelop and implement high-performance, low-power, and area-efficient digital designs for ASICs and SoCs using industry-standard EDA tools\nWork closely with design teams to understand the requirements and constraints of the design, and provide feedback on design feasibility,timing and power\nWrite and implement block level and top-level constraints for synthesis, perform timing closure and power analysis\nDevelop and implement synthesis flows and methodologies, and driveimprovements in the design process\nDebug and resolve design issues related to synthesis, timing, power, and area\nUnderstanding of DFT flows, including scan insertion and ATPG\nOptimize designs for power,performance, are and meet design goals within the given schedule\nImplement pipelining at different levels for performance optimization and timing closure\nPerform power analysis and optimize designs for low power\n\nYour Profile\nQualifications and skills to help you succeedB.Tech/M.Tech in Electronics or related field with 8+ years of relevant experience\nStrong fundamentals in Synthesis and STA, with hands-on experience in timing sign-off, margin calculations, and leading STA for full-chip projects\nExpertise in MCMM analysis, multi-power domain designs, constraint mode merging, and STA flow development with bottleneck identification\nProficient in SDC constraints, timing ECO generation, and driving TAT reduction across complex designs\nExperience collaborating closely with Design and Physical Design teams to meet aggressive schedules\nSkilled in Synopsys/Cadence EDA tools, with scripting knowledge in Tcl/Perl as an added advantage\nStrong analytical, communication, and mentoring skills with ability to work across cross-functional and global teams.\nProficient with EDA tools from Synopsys/Cadence/Mentor\n\nContact:\n    Gowri Shenoy, LinkedIn\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\nThis means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.\nPlease let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.\nClick here for more information about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Lead Principal Engineer IO Design", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-06-12T05:29:50+00:00", "url": "https://jobs.infineon.com/careers/job/563808971200847", "is_hardware": true, "platform": "eightfold", "jd_text": "#WeAreIn to draw on our creativity to develop analog and mixed-signal circuit solutions. Are you in?\n\nYour Role\n\nKey responsibilities in your new role\n\nleading a team of analog mixed signal design engineers, technically and functionally.\nTechnically Own complete design & development of IO library designs\nLead interaction with system architects of product development to close IO specifications & requirements.\nDrive IO integration into the sub-system, resolving all technical issues. Should act as an advisor (Expert support) for the IO selection/Implementations/Integration/qualification at the sub-system.\nOwn IO quality sign-off & checklist at different milestones to ensure quality deliverables to SOC.\nAct as an IO architect responsible for defining the overall concept, including the sub-blocks in alignment with product requirements.\nGuide the team members on the effective implementation of the IOs. Review their designs and continuously drive down turnaround time, design robustness/optimisations, and IO area/power.\nSupport the FE / BE development hands-on as per the project needs.\nContinuous improvement and development of design and verification methodologies for improving quality and efficiency.\nEnsuring compliance with all Infineon Quality/Process practices for library development.\n\nYour Profile\n\nQualifications and skills to help you succeed\n\n15+ years of Solid experience in IO design, preferably for interface standards like LVTTL, LVCMOS, DDR, SPI, xSPI, Oscillator, LVDS, overvoltage/under voltage tolerant circuits.\nGood understanding of ESD & LU concepts.\nGood understanding of the characterization methodology used in the IO library development.\nCandidate should be able to technically lead a small team of designers/layout engineers and come up with new architectures and plans/schedules.\nCandidate should have delivered a few designs from spec to silicon with complete knowledge of associated deliverables.\nDisciplined process management, problem-solving skills, multitasking ability, and attention to quality and detail.\nDemonstrated strong analytical and problem-solving skills. Strong verbal and written communication skills.\nAbility to work in teams and collaborate effectively with people in different functions\n\nContact:\n    Keerthini M H\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\nThis means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.\nPlease let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.\nClick here for more information about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Power & Performance Validation Engineer", "company": "Graphcore", "location": "Bengaluru, India", "date_posted": "2026-06-12T00:21:36-04:00", "url": "https://job-boards.greenhouse.io/graphcore/jobs/8587365002", "is_hardware": true, "platform": "greenhouse", "jd_text": "Power and Performance Validation Engineer\n\nAbout us\n\nGraphcore is one of the world’s leading innovators in Artificial Intelligence compute.\nIt is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry.\n\nAs part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone.\n\nGraphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation.\n\nJob Summary\n\nReporting to senior leadership within Architecture and Validation, the Power and Performance Validation Lead will drive validation strategy and execution for advanced AI compute silicon and systems. The role is responsible for leading power, thermal and performance validation activities across pre-silicon and post-silicon environments to ensure products meet efficiency, reliability and scalability expectations.\n\nThis role requires strong technical expertise and collaboration across multiple engineering disciplines to deliver robust validation methodologies, scalable automation frameworks and actionable performance insights.\n\nThe Team\n\nThe Power and Performance Validation team sits within the Architecture and Validation organisation and is responsible for validating the performance, efficiency and thermal behaviour of Graphcore silicon and systems.\n\nThe team supports the full product lifecycle, from early architectural modelling through to first silicon bring-up, characterization and production readiness. Engineers work closely with cross-functional teams globally to debug complex issues, optimize workloads and continuously improve validation infrastructure and methodologies.\n\nResponsibilities and Duties\n\nDefine and lead validation strategies for power, thermal and performance characterization of AI compute silicon and platforms\n\nContribute to planning and execution of validation activities across multiple projects and milestones\n\nDevelop comprehensive validation plans covering functional, stress, workload and corner-case scenarios\n\nLead post-silicon bring-up and characterization activities for power and performance validation\n\nDrive validation of CPU, memory, interconnect and high-speed I/O subsystems under complex workload conditions\n\nDevelop scalable automation frameworks, regression infrastructure and reporting tools using Python\n\nDesign and execute benchmark workloads, parameter sweeps and performance experiments to identify optimization opportunities\n\nCollaborate with architecture, RTL, firmware, software and systems teams to debug and resolve complex technical issues\n\nDefine validation metrics, pass/fail criteria and reporting methodologies to ensure repeatable and high-quality analysis\n\nGuide development of custom workload generators and micro-benchmarks where required\n\nAnalyse power, thermal and performance data to identify bottlenecks and recommend improvements\n\nContribute to continuous improvement of validation processes, tooling and engineering practices\n\nCommunicate technical findings, project status, risks and recommendations clearly to stakeholders and engineering leadership\n\nSupport knowledge sharing and contribute to continuous improvement across the validation organisation\n\nCandidate Profile\n\nEssential:\n\nStrong experience in power and performance validation, silicon characterization or system performance engineering\n\nDeep understanding of modern SoC architecture, including CPU, memory, interconnect and high-speed I/O technologies\n\nStrong Linux systems knowledge and low-level performance analysis experience\n\nStrong Python programming skills for automation, orchestration and data analysis\n\nExperience with benchmarking and profiling tools such as stress-ng, fio, perf, iperf or equivalent technologies\n\nExperience debugging complex hardware and software interactions\n\nAbility to define structured validation methodologies, workload models and test strategies\n\nStrong analytical skills with the ability to interpret large datasets and identify system bottlenecks\n\nStrong communication and cross-functional collaboration skills\n\nAbility to work independently on complex technical tasks while collaborating effectively across teams\n\nDesirable\n\nExperience with AI accelerator, GPU or high-performance compute architectures\n\nExperience with pre-silicon modelling or simulation environments\n\nKnowledge of power management technologies and silicon characterization methodologies\n\nProgramming experience in C/C++ for low-level system or benchmark development\n\nFamiliarity with hardware instrumentation and telemetry systems\n\nExperience working with high core-count or large-scale compute systems\n\nExperience contributing to shared validation infrastructure and engineering best practices", "jd_status": "stored"}, {"title": "Senior Power & Performance Validation Engineer", "company": "Graphcore", "location": "Bengaluru, India", "date_posted": "2026-06-12T00:11:28-04:00", "url": "https://job-boards.greenhouse.io/graphcore/jobs/8587344002", "is_hardware": true, "platform": "greenhouse", "jd_text": "Senior -Power and Performance Validation Engineer\n\nAbout us\n\nGraphcore is one of the world’s leading innovators in Artificial Intelligence compute.\nIt is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry.\n\nAs part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone.\n\nGraphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation.\n\nJob Summary\n\nReporting to senior leadership within Architecture and Validation, the Power and Performance Validation Lead will drive validation strategy and execution for advanced AI compute silicon and systems. The role is responsible for leading power, thermal and performance validation activities across pre-silicon and post-silicon environments to ensure products meet efficiency, reliability and scalability expectations.\n\nThis role requires strong technical expertise and collaboration across multiple engineering disciplines to deliver robust validation methodologies, scalable automation frameworks and actionable performance insights.\n\nThe Team\n\nThe Power and Performance Validation team sits within the Architecture and Validation organisation and is responsible for validating the performance, efficiency and thermal behaviour of Graphcore silicon and systems.\n\nThe team supports the full product lifecycle, from early architectural modelling through to first silicon bring-up, characterization and production readiness. Engineers work closely with cross-functional teams globally to debug complex issues, optimize workloads and continuously improve validation infrastructure and methodologies.\n\nResponsibilities and Duties\n\nDefine and lead validation strategies for power, thermal and performance characterization of AI compute silicon and platforms\n\nContribute to planning and execution of validation activities across multiple projects and milestones\n\nDevelop comprehensive validation plans covering functional, stress, workload and corner-case scenarios\n\nLead post-silicon bring-up and characterization activities for power and performance validation\n\nDrive validation of CPU, memory, interconnect and high-speed I/O subsystems under complex workload conditions\n\nDevelop scalable automation frameworks, regression infrastructure and reporting tools using Python\n\nDesign and execute benchmark workloads, parameter sweeps and performance experiments to identify optimization opportunities\n\nCollaborate with architecture, RTL, firmware, software and systems teams to debug and resolve complex technical issues\n\nDefine validation metrics, pass/fail criteria and reporting methodologies to ensure repeatable and high-quality analysis\n\nGuide development of custom workload generators and micro-benchmarks where required\n\nAnalyse power, thermal and performance data to identify bottlenecks and recommend improvements\n\nContribute to continuous improvement of validation processes, tooling and engineering practices\n\nCommunicate technical findings, project status, risks and recommendations clearly to stakeholders and engineering leadership\n\nSupport knowledge sharing and contribute to continuous improvement across the validation organisation\n\nCandidate Profile\n\nEssential:\n\nStrong experience in power and performance validation, silicon characterization or system performance engineering\n\nDeep understanding of modern SoC architecture, including CPU, memory, interconnect and high-speed I/O technologies\n\nStrong Linux systems knowledge and low-level performance analysis experience\n\nStrong Python programming skills for automation, orchestration and data analysis\n\nExperience with benchmarking and profiling tools such as stress-ng, fio, perf, iperf or equivalent technologies\n\nExperience debugging complex hardware and software interactions\n\nAbility to define structured validation methodologies, workload models and test strategies\n\nStrong analytical skills with the ability to interpret large datasets and identify system bottlenecks\n\nStrong communication and cross-functional collaboration skills\n\nAbility to work independently on complex technical tasks while collaborating effectively across teams\n\nDesirable\n\nExperience with AI accelerator, GPU or high-performance compute architectures\n\nExperience with pre-silicon modelling or simulation environments\n\nKnowledge of power management technologies and silicon characterization methodologies\n\nProgramming experience in C/C++ for low-level system or benchmark development\n\nFamiliarity with hardware instrumentation and telemetry systems\n\nExperience working with high core-count or large-scale compute systems\n\nExperience contributing to shared validation infrastructure and engineering best practices", "jd_status": "stored"}, {"title": "Staff Power and Performance Validation Engineer ", "company": "Graphcore", "location": "Bengaluru, India", "date_posted": "2026-06-12T00:10:36-04:00", "url": "https://job-boards.greenhouse.io/graphcore/jobs/8587313002", "is_hardware": true, "platform": "greenhouse", "jd_text": "Staff Power and Performance Validation Engineer\n\nAbout us\n\nGraphcore is one of the world’s leading innovators in Artificial Intelligence compute.\nIt is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry.\n\nAs part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone.\n\nGraphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation.\n\nJob Summary\n\nReporting to senior leadership within Architecture and Validation, the Power and Performance Validation Lead will drive validation strategy and execution for advanced AI compute silicon and systems. The role is responsible for leading power, thermal and performance validation activities across pre-silicon and post-silicon environments to ensure products meet efficiency, reliability and scalability expectations.\n\nThis role requires strong technical expertise and collaboration across multiple engineering disciplines to deliver robust validation methodologies, scalable automation frameworks and actionable performance insights.\n\nThe Team\n\nThe Power and Performance Validation team sits within the Architecture and Validation organisation and is responsible for validating the performance, efficiency and thermal behaviour of Graphcore silicon and systems.\n\nThe team supports the full product lifecycle, from early architectural modelling through to first silicon bring-up, characterization and production readiness. Engineers work closely with cross-functional teams globally to debug complex issues, optimize workloads and continuously improve validation infrastructure and methodologies.\n\nResponsibilities and Duties\n\nDefine and lead validation strategies for power, thermal and performance characterization of AI compute silicon and platforms\n\nContribute to planning and execution of validation activities across multiple projects and milestones\n\nDevelop comprehensive validation plans covering functional, stress, workload and corner-case scenarios\n\nLead post-silicon bring-up and characterization activities for power and performance validation\n\nDrive validation of CPU, memory, interconnect and high-speed I/O subsystems under complex workload conditions\n\nDevelop scalable automation frameworks, regression infrastructure and reporting tools using Python\n\nDesign and execute benchmark workloads, parameter sweeps and performance experiments to identify optimization opportunities\n\nCollaborate with architecture, RTL, firmware, software and systems teams to debug and resolve complex technical issues\n\nDefine validation metrics, pass/fail criteria and reporting methodologies to ensure repeatable and high-quality analysis\n\nGuide development of custom workload generators and micro-benchmarks where required\n\nAnalyse power, thermal and performance data to identify bottlenecks and recommend improvements\n\nContribute to continuous improvement of validation processes, tooling and engineering practices\n\nCommunicate technical findings, project status, risks and recommendations clearly to stakeholders and engineering leadership\n\nSupport knowledge sharing and contribute to continuous improvement across the validation organisation\n\nCandidate Profile\n\nEssential:\n\nStrong experience in power and performance validation, silicon characterization or system performance engineering\n\nDeep understanding of modern SoC architecture, including CPU, memory, interconnect and high-speed I/O technologies\n\nStrong Linux systems knowledge and low-level performance analysis experience\n\nStrong Python programming skills for automation, orchestration and data analysis\n\nExperience with benchmarking and profiling tools such as stress-ng, fio, perf, iperf or equivalent technologies\n\nExperience debugging complex hardware and software interactions\n\nAbility to define structured validation methodologies, workload models and test strategies\n\nStrong analytical skills with the ability to interpret large datasets and identify system bottlenecks\n\nStrong communication and cross-functional collaboration skills\n\nAbility to work independently on complex technical tasks while collaborating effectively across teams\n\nDesirable\n\nExperience with AI accelerator, GPU or high-performance compute architectures\n\nExperience with pre-silicon modelling or simulation environments\n\nKnowledge of power management technologies and silicon characterization methodologies\n\nProgramming experience in C/C++ for low-level system or benchmark development\n\nFamiliarity with hardware instrumentation and telemetry systems\n\nExperience working with high core-count or large-scale compute systems\n\nExperience contributing to shared validation infrastructure and engineering best practices", "jd_status": "stored"}, {"title": "Principal Verification Engineer, Digital IP", "company": "NXP", "location": "Bangalore", "date_posted": "2026-06-12", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Verification-Engineer--Digital-IP_R-10063901", "is_hardware": true, "platform": "workday", "jd_text": "Job Title: Principal Verification Engineer\nPrimary Location: Bengaluru, India\nRole Summary:\nWe are part of MCU/MPU Engineering, a central design organization within NXP, developing products for multiple business lines in Automotive, Internet of Things (IoT), Networking, and Radio Frequency products, with expertise in hardware engineering, including architecture, IP, and full SoC Design. \n\nMME's Digital IP team produces design solutions covering the very wide range of SoCs required by the business lines. The team is challenged to produce industry-leading solutions covering very cost-sensitive, low-power devices to highly integrated, high-performance, multi-cohort devices compliant with the latest automotive and industrial safety and security standards.\nJob Responsibility:\nResponsible for the pre-silicon verification of IP modules or, IP subsystems\nResponsible for defining and writing IP verification plans based on requirements documents (industry standards, product requirements, IP architecture and IP implementation specifications)\nInterface to HW, FW, and SW design teams, as well as to architecture and system engineering teams, to understand functionality and application of the IP or subsystem.\nResponsible for executing verification plan according to the product specification and verification requirements defined by product architects.\nResponsible for architecting, developing, debugging and running UVM based verification environment for RTL simulation.\nDefine and develop test cases in an appropriate verification framework. Create stimulus and assertions, run simulation, debug test cases on the design models (RTL, power aware RTL, gate level, FPGA, Emulation platform), run regression, collect and analyze code/functional coverage.\nJob Qualification:\nDegree in Electrical Engineering or Computer Science, with 10+ years of experience on IP/Sub-System Verification\nProven experience in testbench design and development using UVM methodology for IP/Subsystem and SOC.\nAdvanced knowledge of Verilog, System Verilog, C/C++, Shell.\nHigh proficiency in Metric Driven Verification concepts, functional and code coverage.\nHigh proficiency in directed and constrained random methodologies.\nGood knowledge of formal verification methodologies and assertions.\nExperience with debugging of designs pre- and post-silicon, in simulation and on the bench.\nExcellent written and verbal communication skill. \nGood knowledge in scripting like Perl, TCL or Python is a plus\n\nMore information about NXP in India...\n\n#LI-7013", "jd_status": "stored"}, {"title": "DFX CAD Tools Development Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-06-12", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/DFX-CAD-Tools-Development-Engineer_JR2019454", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nAs part of the CAD team our engineers develop and support tools for all of NVIDIA's semiconductor products. In addition, they also develop in-house tools in the area of Design for Test (DFT) and Design for Power (DFP) using C++, Python, and TCL. Below are some of the some of the teams' activities. We are a diverse team needing someone who is not afraid of a challenge. If this is you, come join us today.\n\nWhat you will be doing:\nBe responsible for architecting highly automated and customizable design flows using software engineering with modular design and object oriented techniques.\n\nWork closely with our diverse team members on flows to provide DFT, and DFP methodologies for industry-leading chip designs.\n\nSupport development of tools using C++/Python/TCL.\n\nWork cross functionally with DFT Methodology, Implementation and design teams with important DFT and power tools development tasks.\n\nWhat we need to see:\n2+ years of relevant work experience.\n\nSmart, diligent and motivated to work in our CAD group.\n\nBE or BTech or MTech in Computer Science, or Electronics Engineering, or Electrical Engineering, or equivalent experience.\n\nKnowledge or experience with DFT, DFP is a plus.\n\nFamiliar with Verilog, VLSI and ASIC design principles, including knowledge of logic cells.\n\nSoftware engineering: software design, algorithms, and QA.\n\nStrong C++ programming experience.\n\nSolid programming and scripting skills in Python or TCL desired.\n\nKnowledge of GenAI, LLM, AI Code Generation is a plus.\n\nHaving strong interpersonal skills will serve you well in this role.\n\nNVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative and autonomous, we want to hear from you!\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior Principal Verification Engineer, Digital IP", "company": "NXP", "location": "Bangalore", "date_posted": "2026-06-12", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Sr-Principal-Verification-Engineer--Digital-IP_R-10063899", "is_hardware": true, "platform": "workday", "jd_text": "Job Title: Sr. Principal Verification Engineer\nPrimary Location: Bengaluru, India\nRole Summary:\nWe are part of MCU/MPU Engineering, a central design organization within NXP, developing products for multiple business lines in Automotive, Internet of Things (IoT), Networking, and Radio Frequency products, with expertise in hardware engineering, including architecture, IP, and full SoC Design. \n\nMME's Digital IP team produces design solutions covering the very wide range of SoCs required by the business lines. The team is challenged to produce industry-leading solutions covering very cost-sensitive, low-power devices to highly integrated, high-performance, multi-cohort devices compliant with the latest automotive and industrial safety and security standards.\nJob Responsibility:\nResponsible for the pre-silicon verification of IP modules or, IP subsystems\nResponsible for defining and writing IP verification plans based on requirements documents (industry standards, product requirements, IP architecture and IP implementation specifications)\nInterface to HW, FW, and SW design teams, as well as to architecture and system engineering teams, to understand functionality and application of the IP or subsystem.\nResponsible for executing verification plan according to the product specification and verification requirements defined by product architects.\nResponsible for architecting, developing, debugging and running UVM based verification environment for RTL simulation.\nDefine and develop test cases in an appropriate verification framework. Create stimulus and assertions, run simulation, debug test cases on the design models (RTL, power aware RTL, gate level, FPGA, Emulation platform), run regression, collect and analyze code/functional coverage.\nJob Qualification:\nDegree in Electrical Engineering or Computer Science, with 12+ years of experience on IP/Sub-System Verification\nPrior experience as a tech lead or DV manager is strongly preferred\nProven experience in testbench design and development using UVM methodology for IP/Subsystem and SOC.\nAdvanced knowledge of Verilog, System Verilog, C/C++, Shell.\nHigh proficiency in Metric Driven Verification concepts, functional and code coverage.\nHigh proficiency in directed and constrained random methodologies.\nGood knowledge of formal verification methodologies and assertions.\nExperience with debugging of designs pre- and post-silicon, in simulation and on the bench.\nExcellent written and verbal communication skill. \nGood knowledge in scripting like Perl, TCL or Python is a plus\n\nMore information about NXP in India...\n\n#LI-7013", "jd_status": "stored"}, {"title": "Principal Engineer Digital Design", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-06-11T07:04:07+00:00", "url": "https://jobs.infineon.com/careers/job/563808971195754", "is_hardware": true, "platform": "eightfold", "jd_text": "The Multi Phase controller IP Lead is responsible for end-to-end definition, execution, and delivery of a control- and filter-centric signal processing digital IP that interfaces with high complexity AFEs. This role drives architecture closure across algorithm intent, fixed-point implementation, RTL micro-architecture, register/bus interfaces, verification strategy, and implementation readiness. The IP Lead aligns System modelling, Analog, RTL, DV, and DMS/AMS teams to ensure the IP meets functional, performance, latency, quality, and integration goals.\n\nYour Role\n\nKey responsibilities in your new role\n\nTechnical Ownership\n\nOwn end-to-end IP definition from requirements through architecture, implementation, verification, and handoff.\n Translate system and product requirements into a clear IP micro-architecture and execution plan.\n Drive closure on algorithm intent, control behavior, filter architecture, latency budgets, and implementation trade-offs.\n Review and converge control/filter algorithm definition, sampling intent, and expected behavior with signal-processing architects.\n Drive fixed-point architecture decisions including numeric precision, dynamic range, saturation, rounding, scaling, and pipeline placement.\n Oversee RTL architecture for filter data path, coefficient programming, update paths, loop delays, state machines, and control logic.\n Own top-level design decisions affecting timing, CDC, reset strategy, area, power, and implementation robustness.\n Guide register architecture, status/control visibility, firmware programmability, and system integration behavior.\n Drive architecture and RTL for AHB/PM Bus/AVS or other system-facing interfaces, including arbitration and error handling.\n Define verification goals and signoff expectations jointly with DV and AMS verification leads.\n Ensure availability of golden models, bit-true checking strategy, coverage goals, and end-to-end latency checks.\n Drive closure on corner cases including overflow, convergence, saturation recovery, limit cycles, reset behavior, and protocol exceptions.\n Ensure analog assumptions, abstraction boundaries, and mixed-signal interaction points are verified appropriately.\n Review and close functional gaps across RTL, DV, DMS/AMS, and system validation.\n Break down execution into work packages, milestones, dependencies, and risk mitigation plans.\n\nYour Profile\n\nQualifications and skills to help you succeed\n\nBachelor’s or Master’s degree in Electrical Engineering,\n Strong experience leading digital or mixed-signal-adjacent IP development.\n Strong understanding of control loops, DSP/filter implementations, or fixed-point digital signal processing.\n\nContact:\n    VidhiAshok.Thakkar@infineon.com\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\nThis means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.\nPlease let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.\nClick here for more information about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "DFT Lead - ATPG", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-06-11T05:50:00+00:00", "url": "https://global-external-amd.icims.com/jobs/86977/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. SMTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning PREFERRED EXPERIENCE: Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.) Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-RR1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Principal Power & Performance Validation Engineer", "company": "Graphcore", "location": "Bengaluru, India", "date_posted": "2026-06-11T04:00:44-04:00", "url": "https://job-boards.greenhouse.io/graphcore/jobs/8587305002", "is_hardware": true, "platform": "greenhouse", "jd_text": "About us\n\nGraphcore is one of the world’s leading innovators in Artificial Intelligence compute.\nIt is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry.\n\nAs part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone.\n\nGraphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation.\n\nJob Summary\n\nReporting to senior leadership within Architecture and Validation, the Power and Performance Validation Lead will drive validation strategy and execution for advanced AI compute silicon and systems. The role is responsible for leading power, thermal and performance validation activities across pre-silicon and post-silicon environments to ensure products meet efficiency, reliability and scalability expectations.\n\nThis role combines deep technical expertise with people leadership responsibilities, including team development, prioritisation, mentoring and delivery coordination across multiple projects and stakeholders.\n\nThe Team\n\nThe Power and Performance Validation team sits within the Architecture and Validation organisation and is responsible for validating the performance, efficiency and thermal behaviour of Graphcore silicon and systems.\n\nThe team supports the full product lifecycle, from early architectural modelling through to first silicon bring-up, characterization and production readiness. Engineers work closely with cross-functional teams globally to debug complex issues, optimize workloads and continuously improve validation infrastructure and methodologies.\n\nResponsibilities and Duties\n\nDefine and lead validation strategies for power, thermal and performance characterization of AI compute silicon and platforms\n\nLead, mentor and support a team of validation engineers, providing technical guidance, coaching and career development\n\nDrive planning, prioritisation and execution of validation activities across multiple projects and milestones\n\nDevelop comprehensive validation plans covering functional, stress, workload and corner-case scenarios\n\nLead post-silicon bring-up and characterization activities for power and performance validation\n\nDrive validation of CPU, memory, interconnect and high-speed I/O subsystems under complex workload conditions\n\nDevelop scalable automation frameworks, regression infrastructure and reporting tools using Python\n\nDesign and execute benchmark workloads, parameter sweeps and performance experiments to identify optimization opportunities\n\nCollaborate with architecture, RTL, firmware, software and systems teams to debug and resolve complex technical issues\n\nDefine validation metrics, pass/fail criteria and reporting methodologies to ensure repeatable and high-quality analysis\n\nGuide development of custom workload generators and micro-benchmarks where required\n\nAnalyse power, thermal and performance data to identify bottlenecks and recommend improvements\n\nContribute to continuous improvement of validation processes, tooling and engineering practices\n\nCommunicate technical findings, project status, risks and recommendations clearly to stakeholders and engineering leadership\n\nSupport hiring activities, onboarding and team growth initiatives\n\nCandidate Profile\n\nEssential:\n\nStrong experience in power and performance validation, silicon characterization or system performance engineering\n\nExperience leading or managing engineering teams within a technical environment\n\nDeep understanding of modern SoC architecture, including CPU, memory, interconnect and high-speed I/O technologies\n\nStrong Linux systems knowledge and low-level performance analysis experience\n\nStrong Python programming skills for automation, orchestration and data analysis\n\nExperience with benchmarking and profiling tools such as stress-ng, fio, perf, iperf or equivalent technologies\n\nExperience debugging complex hardware and software interactions\n\nAbility to define structured validation methodologies, workload models and test strategies\n\nStrong analytical skills with the ability to interpret large datasets and identify system bottlenecks\n\nStrong communication, stakeholder management and cross-functional collaboration skills\n\nAbility to lead complex technical initiatives across geographically distributed teams\n\nDesirable\n\nExperience with AI accelerator, GPU or high-performance compute architectures\n\nExperience with pre-silicon modelling or simulation environments\n\nKnowledge of power management technologies and silicon characterization methodologies\n\nProgramming experience in C/C++ for low-level system or benchmark development\n\nFamiliarity with hardware instrumentation and telemetry systems\n\nExperience working with high core-count or large-scale compute systems\n\nExperience scaling or building technical engineering teams", "jd_status": "stored"}, {"title": "Senior DFT Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-06-11", "url": "https://careers.synopsys.com/job/bengaluru/senior-dft-engineer/44408/96459427024", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are\nYou have spent the last few years deep in the world of Design for Test, and you know that a good DFT flow is not just about coverage numbers, it is about catching the failure that would have cost millions in a production run. You think in test patterns, fault models, and compression ratios, and you have learned that the difference between a tool that works in theory and one that works in production is usually in the details someone missed three reviews ago.\nYou are comfortable jumping between RTL debugging, Python automation, and customer architecture conversations without losing sight of what you are actually building. When a scan compression flow fails at 2am, you do not panic, you pull logs, trace the issue, and find the root cause. You ask the right questions when a spec is vague, and you push back when a test plan does not cover the corner cases that matter.\nYou like hard problems, especially the ones where the answer is not obvious and requires you to think across multiple layers of the ASIC flow. You have worked with MBIST, ATPG, scan chains, and diagnostics enough to know where things break and how to fix them before they reach a customer.\nAt Synopsys, you will work on DFT tools that power silicon development across automotive, AI, mobile, and high-performance computing. The team is global, the problems are real, and what you build will matter.\nWhat You'll Be Doing\nDevelop detailed test plans for new DFT features, then build, execute, and automate test cases using Verilog, System Verilog, or VHDL\nReview specifications and test plans from Product Engineering and R&D teams, providing feedback to ensure feature completeness before product release\nCollaborate with cross-functional teams to create in-house test cases and implement scalable DFT solutions tailored to customer architectures and methodologies\nBuild and validate prototype test flows and reference designs that demonstrate new DFT features like compression, ATPG for transition delay faults, cell-aware faults, and Memory and Logic BIST\nPerform Quality of Results analysis, troubleshooting, and root cause analysis to resolve complex issues across the ASIC flow, from synthesis to sign-off\nConduct diagnostics analysis and debugging to improve tool reliability, performance, and customer experience\nWork with AI agents to review and create assistive or generative AI documentation for test products, and manage performance and installation testing\nThe Impact You Will Have\nImprove the quality and performance of Synopsys DFT tools that customers rely on to ship high-performance silicon for AI, automotive, and mobile applications\nEnable customers to implement robust test methodologies that catch defects earlier, reduce silicon respins, and accelerate time to market\nDrive innovation in DFT automation and AI-driven testing, making cutting-edge solutions accessible across diverse industry segments\nStrengthen Synopsys reputation as a trusted partner in delivering scalable, reliable, and high-performance test solutions\nFacilitate cross-team knowledge sharing by providing actionable feedback and creating comprehensive documentation that helps engineers and customers alike\nAdvance the adoption of new DFT features and methodologies, ensuring Synopsys products remain competitive and future-ready\nSupport the seamless integration of new test technologies, keeping Synopsys at the forefront of semiconductor innovation\nWhat You'll Need\nBachelor's, Master's, or MTech in Electrical/Electronics Engineering, Computer Science, or a related field with 3+ years of relevant experience in DFT or ASIC test\nHands-on expertise in DFT technologies such as JTAG, MBIST, Scan, ATPG, and related test architectures\nProficiency in RTL coding using Verilog, System Verilog, and/or VHDL\nAdvanced scripting skills in Perl, Tcl/Tk, Python, or similar languages for automation and tool integration\nSolid understanding of ASIC design flow, including design planning, synthesis, physical design, and sign-off verification tools\nFamiliarity with change management tools like Perforce for collaborative development and version control is a plus\nExperience with DFT compression, diagnostics, or AI-enabled test automation is a plus\nWho You Are\nYou can debug a failing scan chain at 10pm, trace it back to a clock gating issue, and explain the root cause to an R&D engineer in two sentences without losing the nuance\nYou are organized enough to manage multiple test plans, automation scripts, and customer escalations at once, and disciplined enough to document what you learn along the way\nYou do not wait for perfect information to get started, you work with what you have, ask the right questions, and move forward\nYou push back when a test plan does not cover the corner cases that matter, and you advocate for quality even when timelines are tight\nYou are comfortable working across global teams, bridging gaps between Product Engineering, R&D, and customer-facing teams with clear communication and technical depth\nYou enjoy learning new technologies and methodologies, whether it is a new fault model, a new scripting framework, or an AI-driven test agent\nThe Team You'll Be Part Of\nYou will join the Synopsys Product Engineering Team within the Test Group, a dynamic organization focused on validating, hardening, and delivering cutting-edge Design for Test solutions. The team is composed of engineers and innovators who collaborate across product engineering and R&D to create industry-leading methodologies and tools. As part of Product Engineering, you will work at the intersection of customer requirements, product quality, and technical innovation, ensuring that DFT features are thoroughly tested, well-documented, and ready for real-world deployment. Together, you will address challenges in diverse domains such as autonomous systems, AI, high-performance computing, and mobile networking, driving the next wave of silicon innovation.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\n\n#TPG", "jd_status": "stored"}, {"title": "Platform Integration Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-06-11", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Platform-Integration-Engineer_JR0284555", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nIntel is seeking an experienced Platform Integration Engineer for the Intel Chassis Group. The Chassis Group is chartered to deliver the chassis for multiple SoCs within Intel.\n\nThe role involves\n•\tWorking with the SoC architecture teams to understand the SoC chassis requirements\n•\tDesigning and developing high-performance networks-on-chip which meet the SoC PPA requirements using chassis foundation library components\n•\tCoordinating with the foundation IP development team within the Chassis Group to modify/create IP components as per SoC needs\n\nQualifications:\nMinimum Qualifications\n•\tBachelor's/Master's degree in Science, Electrical Engineering or equivalent\n•\t6+ years of experience in SOC and/or IP design\n\nPreferred Qualifications\n•\t5+ years' experience in microarchitecture and design IP systems, including 2+ years' experience in fabric design/integration\n•\tExpertise in Verilog/System Verilog Design, Lint/CDC/RDC and timing constraints\n•\tGood understanding of AMBA protocols (CHI, AXI, AHB, APB) and PCIe/CXL\n•\tExperience in analyzing power, performance and area trade-offs in designs\n•\tAbility to work with physical design to understand floorplan limitations\n\nIn addition to the qualifications a successful candidate will demonstrate:\n•\tCommunication skills\n•\tCapacity to work with geographically distributed engineering teams across multiple time zones.\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nBusiness group:\nThe Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Analog IC Design Manager", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-06-10", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010909", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\nTexas Instruments is seeking an Analog Design Manager. In this role, you will direct and guide the activities of a research or technical design function responsible for designing, developing, modifying and evaluating analog and mixed signal electronic parts, components or integrated circuitry for electronic equipment and other hardware systems. You may also evaluate final results of research and development projects to assure accomplishment of technical objectives. In addition, job functions include preparing and presenting reports outlining the outcome of technical projects and making recommendations for actions necessary to achieve desired results. As an Analog Design Manager, you may also select, develop, and evaluate personnel to ensure the efficient operation of the function.\nWe are looking for an experienced Design Manager to lead our Wide VIN Bucks design team focused on high-performance DC-DC buck regulators for industrial and automotive applications.\nThe team owns the charter for all buck converters with input voltages above 60V and consists of 15 engineers. This role requires a strong technical leader who can drive execution across multiple parallel projects while mentoring and guiding a young, high-potential team.\nKey Responsibilities\nLead and drive design execution for multiple Wide VIN buck regulator projects from concept to production\nProvide deep technical leadership in switching regulators, especially buck converters\nMentor and develop engineers through hands-on technical guidance, design reviews, and architectural direction\nCollaborate closely with systems and cross-functional teams to define competitive product specifications and differentiated solutions\nDrive innovation, product quality, execution excellence, and first-pass silicon success\nEnsure timely delivery of high-quality designs aligned with business and product goals\nBuild a strong product-first and customer-focused engineering culture\nRequirements\nStrong experience in analog/power management IC design with deep expertise in switching regulators and buck converters\nProven track record of leading high-performing design teams and delivering complex products to market\nStrong execution mindset with ability to manage multiple projects in parallel\nExperience working across systems, architecture, verification, layout, validation, and product engineering teams\nPassion for mentoring and developing engineering talent\nExperience in industrial and/or automotive power products is highly desirable\n\nQualifications\nMinimum requirements:\nMinimum education (i.e., bachelor's degree in electrical engineering)\nMinimum of 10 years of experience\nPreferred qualifications:\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\nStrong verbal and written communication skills\nAbility to quickly ramp on new systems and processes\nDemonstrated strong interpersonal, analytical and problem-solving skills\nAbility to work in teams and collaborate effectively with people in different functions\nAbility to take the initiative and drive for results\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Staff SW Systems Design Engineer", "company": "Analog Devices", "location": "India, Bangalore, Nova", "date_posted": "2026-06-10", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-Nova/Staff-SW-Systems-Design-Engineer_R263019", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nStaff Engineer – SW Systems Design Engineering \nExperience Required: 7+ Years\nRole Type: Individual Contributor / Technical Leader \nPosition Overview\nWe are seeking a Staff Engineer in SW Systems Design Engineering to join Engineering Enablement group. In this high-impact role, you will define and lead the strategy for system-level modeling, virtual prototyping, and early customer enablement. You will also bridge the gap between SoC architecture, hardware design, and software teams, ensuring that our next-generation SoC models and prototypes are performance-optimized and ready for customer engagement well before silicon tape-out. \nKey Responsibilities\nCreate high-fidelity virtual platforms that enable internal early SW development and demonstrate ADI capabilities and enable ADI customers in defining and developing their products using models for ADI SoCs. \nDevelop AI skills, tools and environments that ease building and adoption of virtual prototypes for both internal teams and  ADI customers\nTroubleshoot complex system-level issues, serving as the escalation point for pre-silicon customer feedback.\nCollaborate closely with ADI customers and internal product teams to create right virtual platforms.\nRequired Qualifications\nExperience: 7+ years of industry experience in SoC design, architecture, or system-level modeling.\nModeling Expertise: Strong hands-on experience in SystemC, TLM 2.0, C/C++ or equivalent high-level modeling, and virtual platforms\nSoftware Proficiency: Expert-level C++ programming skills, with experience in Python and scripting for modeling automation.\nArchitecture Knowledge: Deep understanding of SoC architecture, including CPU subsystems (ARM/RISC-V), bus protocols (AMBA AXI/CHI), and memory hierarchies.\nLeadership: Demonstrated ability to drive technical decisions across cross-functional teams (Architecture, HW, SW, Product Marketing teams). \n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Principal Physical Design Lead - CPU", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-06-09T06:38:00+00:00", "url": "https://global-external-amd.icims.com/jobs/84353/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. PMTS Silicon Design Engineer THE ROLE: The position will involve working with a very experienced CPU physical design team. The person is responsible for delivering the physical design of critical CPU units to meet challenging goals for frequency, power, and other design requirements for AMD's next-generation processors in a fast-paced environment with cutting-edge technology. THE PERSON: Engineer with a good attitude, strong analytical skills, effective communication, and excellent problem-solving abilities. KEY RESPONSIBILITIES: Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure. Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA. Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff. Handling different PNR tools - Synopsys fusion compiler, Cadence, PrimeTime, StarRC, Calibre, Apache Redhawk PREFERRED EXPERIENCE: 16+ years of professional experience in physical design, preferably with high-performance designs. Must have closed high-performance IPs- CPU/GPU/DPU/memory controller, etc. Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality; familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow - Perl/Tcl/Python Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in advanced sub 7nm nodes Excellent physical design and timing background. A good understanding of computer architecture is preferred. Strong analytical/problem-solving skills and pronounced attention to detail. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering #LI-RR1 #LI-Hybrid CTERR1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "SoC Functional Safety and Cybersecurity Manager", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-06-09", "url": "https://careers.arm.com/job/bengaluru/soc-functional-safety-and-cybersecurity-manager/33099/96199716256", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Description:\nArm is looking for an experienced SoC Functional Safety and Cybersecurity Manager to join the Arm Global Standards and Compliance team.\n\nThis role will support automotive SoC programs across Functional Safety, Automotive Cybersecurity, and quality activities, working closely with engineering and business teams throughout development, assessment, and release of Physical AI products.\n\nYou will build practical, scalable compliance approaches for ISO 26262 and ISO/SAE 21434, improve development workflows, support external assessments, and deploy the best engineering practices across Arm's automotive and robotic products.\nResponsibilities:\nEnable Automotive and Robotics programs from development through certification.\nWork with engineering teams to align development practices with industry standards and customer requirements.\nDrive readiness for external assessments and conduct internal audits and reviews.\nHelp teams prepare compliance evidence, safety documentation, and assessment responses.\nEstablish process improvements, trainings, corrective actions, and best-in-class practices across SoC programs.\nContribute to internal and external safety readiness initiatives across Automotive, robotics, AI, and industrial domains.\nRequired Skills and Experience:\n10+ years of strong experience in semiconductor or SoC development within safety-critical industries.\nPractical knowledge of ISO 26262, ISO/SAE 21434, ASPICE, IEC 61508, or similar standards.\nExperience supporting engineering teams in compliance, audit, and process improvement activities.\nExperience with Functional Safety and/or cybersecurity assessments and work products.\nAbility to work across technical and organizational boundaries in complex engineering environments.\nStrong communication, stakeholder management, and problem-solving skills.\n10x Mindset at Arm\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Read more about how we bring the 10x mindset to life on the Arm blog.\n\n #LI-SC2 \nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Staff Analog Design Automation Engineer", "company": "Analog Devices", "location": "India, Bangalore, Nova", "date_posted": "2026-06-09", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-Nova/Staff-Analog-Design-Automation-Engineer_R263122", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nJob Description :\n \nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge – the point where the physical and digital worlds interact, where data is generated, and real-time insights are derived. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9.4 billion in FY24 and approximately 26,000 people globally working alongside over 125,000 global customers, ADI ensures today’s innovators stay Ahead of What’s Possible™.\n \nADI’s Analog Tools and Technology Group (Part of Engineering Enablement) is an innovative group which creates solutions to the complex analog and mixed signal product development challenges using the latest tools and technologies. We strive to enable ADI product development teams to perform at their peak efficiency while maintaining ADI’s leadership in innovation and performance. We develop unique, flexible solutions that can address the needs of ADI’s broad portfolio of product developments.\n\nThe Staff Mixed-Signal Design Automation Engineer will lead a team of talented engineers in the definition, architecting, specification, and implementation of the next generation mixed-signal product design flows in ADI. This team will interact closely with ADI product development teams to implement intuitive capabilities that are aligned with the product development requirements. These flows will leverage state of the art tools from the CAE industry as well as ADI internally developed capabilities.\n \nJob Duties and Responsibilities\nIn this role, you will work with a highly capable team developing our most advanced mixed signal design automation capabilities.  You should exhibit a strong, intuitive capability in solving complex challenges. Self-motivation and the ability to work effectively within a geographically diverse team will also be important.  Your work will include:\n·         Closely collaborating with ADI analog and mixed signal IC design teams and engineering enablement groups to develop and deploy innovative analog IC design flow/tools powered by AI\n·         Collaborating with peers within the Analog Tools and Technology group and Engineering Enablement to develop design process migration tools and methods using AI  \n·         Comprehending how mixed-signal product development flows interact and co-exist with other product development flows as well as product line methodologies\n·         Possessing and maintaining an in-depth knowledge of external design tools and methodologies\n·         Mentoring junior staff and peers on emerging capabilities in Analog and mixed signal IC design tools\n \n \nQualifications\n·         M.S. or beyond in Electrical Engineering\n·         7-10 years’ experience in Analog/mixed-signal IC design and design tool use and/or development\n·         Strong understanding of a wide range of circuits such as wide bandwidth amplifiers and comparators, switched capacitor circuits, precision voltage and current references, LDOs.\n·         Experience in analog circuit design and simulation in Finfet and/or Power processes\n·         While not a must, experience in power product design and development is advantageous.\n·         Experience in Cadence and/or Synopsys design creation and simulation tools.\n·         Programming experience is a must.\n·         Good written and verbal communication skills, and ability to work in a large team.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Engineer II – DFT", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-06-09", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Engineer-II---Design_R89-26", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nWe are looking for a highly motivated DFT / ATPG Engineer with 2+ years of experience in SoC/ASIC test methodology, ATPG, scan and MBIST. The candidate should have strong hands-on expertise in DFT implementation on hierarchical designs and good experience with Tessent/Modus tools for ATPG, MBIST, and diagnosis.\nIn addition to core DFT responsibilities, this role will also contribute to DFT automation flow development using Python and support contemporary AI-based technical initiatives internally within Microchip, aimed at improving productivity, debug efficiency, and overall flow quality.\nKey Responsibilities\n\nDevelop and maintain Python-based automation flows and utilities for DFT setup, pattern generation support, report parsing, coverage analysis, debug, and productivity improvement.\nContribute to flow development and automation infrastructure to improve ATPG execution efficiency and methodology reuse across projects.\nSupport and participate in internal AI-driven technical initiatives related to DFT/ATPG automation, debug assistance, data analysis, and engineering productivity improvement within Microchip.\nHandle DFT implementation and support for hierarchical designs.\nWork on Tessent/Modus ATPG flow for DFT setup, pattern generation, validation, and coverage analysis.\nSupport Tessent/Modus MBIST flow for MBIST hardware generation and integration.\nUse Tessent/Modus diagnosis tools for failure analysis and on-silicon debug.\nPerform scan pattern simulation, debug, and pattern validation.\nSupport ATPG pattern delivery to the Test Engineering / ATE team.\nDebug simulation and DFT issues at block and SoC level.\nCollaborate with CAD, Design, STA, Product Engineering, and Test teams to drive DFT solutions and new initiatives.\n\nRequirements/Qualifications:\n\n2+ years of experience in DFT / ATPG engineering.\nStrong hands-on experience in scan pattern simulation and debug.\nStrong knowledge of Python scripting for automation, flow development, and methodology enhancement.\nInterest or exposure in applying AI/ML-based engineering techniques for automation, debug, or data analysis is a plus.\nGood written and verbal communication skills.\nHands-on expertise in handling DFT on hierarchical designs.\nStrong experience with Tessent and/or Cadence Modus ATPG tools for DFT setup and pattern generation.\nExperience with Tessent/Modus MBIST tools for MBIST hardware generation.\nExperience with Tessent/Modus diagnosis tools for on-silicon debug.\nPreferred Skills\nFamiliarity with Perl, Tcl, or Shell scripting is a plus.\nStrong problem-solving and debugging skills.\nSelf-motivated team player with the ability to work across cross-functional teams.\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Senior Staff Engineer - AMS IP Verification", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-06-09", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Senior-Staff-Engineer---Design-Verification---SerDes-PHY-AMS_2601686", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nCentral Engineering AMS IP delivers high quality analog and mixed signal IP and verification for Marvell’s advanced IPs, SoCs and platforms. The team provides scalable, reusable solutions across high speed interfaces (SerDes, DDR, D2D, PCIe, Ethernet PHY components) and advanced process nodes (5nm, 3nm, 2nm), enabling first time right silicon, reduced integration risk, and faster time to market through strong design verification convergence and system level validation.\nWhat You Can Expect\n• Drive end‑to‑end verification ownership for complex SerDes / AMS / mixed‑signal IPs across advanced nodes (5nm, 3nm, 2nm).\n• Lead verification of high‑speed interfaces including SerDes, PCIe, Ethernet, DDR, D2D, PAM4/PAM2‑based designs.\n• Define and execute verification plans covering calibration, link training, power modes, analog‑digital interaction, and firmware‑driven flows.\n• Debug and resolve complex issues spanning RTL, AMS models, firmware, VIPs, and system‑level behaviors.\n• Drive coverage closure, regression stability, and sign‑off readiness with high quality standards.\n• Own or co‑own Gate‑Level Simulation (GLS), power‑aware verification, CDC/RDC validation, and timing‑aware checks.\n• Collaborate closely with Design, Architecture, Firmware, and Silicon teams to ensure early alignment and risk mitigation.\n• Contribute to verification infrastructure, checkers, automation, and reusable frameworks.\n• Mentor junior engineers and act as a technical role model within the team.\n• Identify opportunities to improve productivity and quality, including use of automation or AI‑assisted verification tools.\n\nWhat We're Looking For\nThe Senior Staff Engineer is a highly experienced hands‑on technical contributor who drives complex verification and AMS bring‑up efforts while influencing verification strategy and execution quality across projects. This role combines deep domain expertise, strong ownership, and cross‑team collaboration, with growing responsibility for technical direction and mentoring.\n \nRequired Technical Qualifications\n• 8–12 years of hands‑on experience in verification and/or AMS systems.\n• Strong expertise in SystemVerilog, UVM, and modern verification methodologies.\n• Deep understanding of:\n    • SerDes / PHY architectures\n    • AMS and mixed‑signal verification\n    • Calibration and link training flows\n    • Register models and firmware interaction\n• Experience integrating and using industry VIPs (Synopsys, Cadence, Siemens/Mentor, Avery).\n• Proven ability to debug difficult issues across multiple abstraction layers.\n• Solid understanding of system‑level behavior and trade‑offs, not just block‑level execution.\n\nLeadership & Behavioral Expectations\n• Demonstrates strong technical ownership and reliability.\n• Leads by example through hands‑on execution and disciplined problem solving.\n• Communicates technical issues clearly to diverse stakeholders.\n• Makes sound decisions under ambiguity with a quality‑first mindset.\n• Actively supports team growth through mentoring and knowledge sharing.\n• Begins to influence technical direction and best practices beyond individual tasks.\n\nNice‑to‑Have / Differentiators\n• Experience across multiple technology nodes and IP generations.\n• Contributions to verification methodology improvements or reusable infrastructure.\n• Exposure to post‑silicon debug and correlation.\n• Participation in internal tech forums, papers, or conferences (DVCon, VLSI‑D, internal reviews).\n\nSuccess Criteria\n• Consistently delivers complex verification areas with high quality and minimal rework.\n• Reduces integration and silicon risk through proactive technical engagement.\n• Becomes a go‑to technical expert within the domain.\n• Scales impact by enabling others, not just individual execution.\n\nAdditional Compensation and Benefit Elements\nWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\n\nInterview Integrity \nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\n\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\n\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n\n#LI-RV1", "jd_status": "stored"}, {"title": "Principal Engineer Digital Design", "company": "Infineon", "location": "Bangalore", "date_posted": "2026-06-08T09:00:27+00:00", "url": "https://jobs.infineon.com/careers/job/563808971195910", "is_hardware": true, "platform": "eightfold", "jd_text": "Join us as a DFT/DFX Technical Lead and drive the test architecture strategy for next-generation multi-phase controller solutions. In this role, you will define and implement advanced Design-for-Test (DFT/DFX) methodologies, establish industry-leading verification flows, and ensure compliance with stringent automotive quality standards. Working alongside global cross-functional teams, you will provide technical leadership, shape product quality from concept to silicon, and enable the development of cutting-edge power management technologies that power tomorrow's intelligent systems.\n\nYour role\nKey responsibilities in your new role\n\nLead the DFX topic for the Multi phase controllers\ntargeted for Auto and Humanoids \nDefine the DFX Architecture and Verification of the\nDFX features\nTop Level Integration\nAnalog Patterns flow establishment\nSPyglass flows for Early Detection of DFT coverage\nloss\nDevelop DFT constraints in alignment with CIC team\nEstablish flows to meet the Auto Standards for ex.\nFault sims\nTechnical guidance to the DES DFT team\n\nYour profile\nQualifications and skills to help you succeed \n\nStrong experience in DFX of Mixed Signal chips\nAbility to driver DFT Arch and be a bridge between\nDigital Design team and DFT\nImplementation team if DES\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nVidhi Thakkar", "jd_status": "stored"}, {"title": "Staff Engineer Verification", "company": "Infineon", "location": "Bangalore BTP (India)", "date_posted": "2026-06-08T05:45:08+00:00", "url": "https://jobs.infineon.com/careers/job/563808969276934", "is_hardware": true, "platform": "eightfold", "jd_text": "#WeAreIn to make sure that our circuits are designed to perfection.​ Are you in?\n\nYour Role\n\nKey responsibilities in your new role\ncreate and define verification plans\ndevelop verification environments for our ICs using Universal Verification Methodology (UVM)\ndraw on test scenarios using System Verilog\nverify functionality using the Constrained Random approach\ndevelop assertions in System Verilog for formal verification\nInteract with other disciplines, such as Concept and Application Engineering, to define verification plans and strategies\nprovide proactive support to users of our verification flow environment\nbe responsible for our verification methods\n\nYour Profile\n\nQualifications and skills to help you succeed\nYou have successfully completed a university degree in Electrical Engineering, Computer Science or a similar academic discipline\nYou have at least 3 years of experience in Metric Driven Verification(digital and/or mixed-signal)\n You have capabilities and experience in working with microcontroller-based ICs, as well as security and safety requirements;\nYou have excellent know-how with UVM especially using System Verilog\nHave knowledge of firmware and RTL design (VHDL/Verilog)\n Ideally have knowledge of Cadence verification software\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\nThis means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.\nPlease let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.\nClick here for more information about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Lead Engineer Senior - Performance Modeling", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-06-08T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718846162", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Systems Engineering\nGeneral Summary:\nQualcomm is the world's leading developer of next-generation of always connected Edge-AI processing technology and is committed to building a world-class organization that will lead the industry.\n\nBe part of the team developing next generation Audio and Always On / Edge AI subsystems and platforms.  The ASIC Audio/Edge AI Systems Engineer is responsible for system architecture definition activities supporting a sophisticated multimedia Low Power Audio/Edge AI subsystem across a broad range of mobile, XR, compute, and automotive products.\n\nCandidates will be responsible for all aspects of the ASIC hardware architecture definition/validation including the following:\nOwning end to end system architecture\n\nCapturing detailed technology requirements working closely with product, hardware and software engineering teams\n\nDeveloping detailed ASIC system architectures to support requirements and authoring subsystem hardware specifications\n\nDefining architecture validation plans and reviewing development results\n\nOptimization and debug via modelling, system simulation and testing across key criteria including power and performance.\n\nCollaborating, reviewing and enabling design and system teams to execute on dependent specifications\n\nPost-silicon commercialization support and customer engineering documentation\n\nDefining and patenting novel architectures that drive industry leadership.\n\nJob Function:\nOversees hardware architecture for ASIC systems development for a variety of products.\n\nDetermines architecture design, and validation via system simulation.\n\nDefines module interfaces/formats for simulation.\n\nEvaluates all aspects of the HW architecture flow from high-level development to validation and review.\n\nAnalyzes equipment to establish operation data, conducts experimental tests, and evaluates results.\n\nUses System tools, such as, MathWorks MATLAB, SIMULINK, VISIO and other toolboxes.\n\nUses language such as HDL, C/C++, System C, Perl, Python.\n\nProvides technical expertise for next generation initiatives.\n\nMinimum Qualifications:\nBachelor's degree in Science, Engineering, or related field and 10+ years of ASIC design, verification, or related work experience.\nOR\nMaster's degree in Science, Engineering, or related field and  8+ years of ASIC design, verification, or related work experience.\nOR\nPhD in Science, Engineering, or related field.\n\nPrincipal Duties and Responsibilities:\nLeverages experience in DSP, machine learning algorithms, SoC hardware and computer architecture concepts to develop proposals to address system audio and edge-AI requirements using processor, memory, bus and low-power design techniques.\n\nUses expertise in low-power design methodology, optimization and validation using various CAD tools and design techniques to optimize system power.\n\nLeverages experience in digital system performance analysis and systems modelling to ensure performance goals met.\n\nLeverages Verilog/VHDL and digital hardware design tools such as Synopsys/Cadence/Mentor ASIC design and simulation tool sets, power analysis and simulation, scripting languages (Python, Perl, TCL, C, etc.) to optimize system.\n\nEffectively utilizes advanced problem solving and ASIC engineering practices to resolve complex architecture, design, or verification problems.\n\nWrites technical documentation and provides technical expertise for design or project reviews and project meetings.\n\nActs as a tech lead on small to large projects and owns team deliverables of the project.\n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience.\n                                                                    OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.\n                                                                    OR\nPhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NPU/AI Processor Synthesis Sr Staff Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-06-08T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446716312205", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nRole Overview\nThe NPU Synthesis Lead will be responsible for driving synthesis and timing closure for Neural Processing Unit (NPU) IP and subsystems in cutting-edge SoCs. This role involves leading synthesis flows, optimizing for PPA (Performance, Power, Area), and collaborating with architecture, RTL, and physical design teams to ensure high-quality netlists for advanced technology nodes.\nKey Responsibilities\nSynthesis Ownership\nLead RTL-to-gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler, Cadence Genus).\n\nDevelop and maintain synthesis scripts and flows for hierarchical and flat designs.\n\nTiming Closure\nDrive pre-layout and post-layout timing closure across multiple voltage and process corners.\n\nCollaborate with STA teams to resolve setup/hold violations.\n\nPower & Area Optimization\nApply physical-aware synthesis techniques to meet aggressive PPA targets.\n\nImplement low-power strategies using UPF/CPF flows.\n\nConstraint Management\nValidate and maintain SDC constraints for clocks, I/O delays, multi-cycle paths, and false paths.\n\nCross-Functional Collaboration\nWork closely with RTL design, DFT, and physical design teams for seamless handoff.\n\nProvide feedback to architecture and RTL teams for QoR improvements.\n\nQuality Checks\nPerform LEC (Logical Equivalence Check), CLP (Clock/Power checks), and linting.\n\nFlow Innovation\nExplore advanced synthesis methodologies and EDA tool capabilities for better QoR.\n\nTeam Leadership\nMentor junior engineers and drive best practices across synthesis and timing teams.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nRequired Skills\nTechnical Expertise\nStrong knowledge of ASIC design flow: RTL → Synthesis → STA → P&R.\n\nProficiency in synthesis tools (Design Compiler, Genus) and STA tools (PrimeTime).\n\nLow-Power Design\nExperience with UPF/CPF-based flows and multi-voltage designs.\n\nScripting\nAdvanced skills in Tcl, Perl, Python for automation.\n\nEDA Tools\nFamiliarity with Spyglass, Lint, CDC tools, and power analysis tools.\n\nLeadership\nAbility to lead synthesis teams and coordinate with cross-functional groups.\n\nEducation\nBachelor’s/Master’s in Electrical Engineering, Computer Engineering, or related field.\n\nExperience\n12+ years in ASIC synthesis and timing closure, with at least 2 years in NPU or AI processor design.\n\nPreferred\nExperience with advanced nodes (5nm/3nm), hierarchical synthesis, and physical-aware flows.\n\nPrior tape-out experience for NPU or DSP cores.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "NPU/AI Processor Synthesis Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-06-08T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718088595", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nRole Overview\nThe NPU Synthesis Lead will be responsible for driving synthesis and timing closure for Neural Processing Unit (NPU) IP and subsystems in cutting-edge SoCs. This role involves leading synthesis flows, optimizing for PPA (Performance, Power, Area), and collaborating with architecture, RTL, and physical design teams to ensure high-quality netlists for advanced technology nodes.\nKey Responsibilities\nSynthesis Ownership\nLead RTL-to-gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler, Cadence Genus).\n\nDevelop and maintain synthesis scripts and flows for hierarchical and flat designs.\n\nTiming Closure\nDrive pre-layout and post-layout timing closure across multiple voltage and process corners.\n\nCollaborate with STA teams to resolve setup/hold violations.\n\nPower & Area Optimization\nApply physical-aware synthesis techniques to meet aggressive PPA targets.\n\nImplement low-power strategies using UPF/CPF flows.\n\nConstraint Management\nValidate and maintain SDC constraints for clocks, I/O delays, multi-cycle paths, and false paths.\n\nCross-Functional Collaboration\nWork closely with RTL design, DFT, and physical design teams for seamless handoff.\n\nProvide feedback to architecture and RTL teams for QoR improvements.\n\nQuality Checks\nPerform LEC (Logical Equivalence Check), CLP (Clock/Power checks), and linting.\n\nFlow Innovation\nExplore advanced synthesis methodologies and EDA tool capabilities for better QoR.\n\nTeam Leadership\nMentor junior engineers and drive best practices across synthesis and timing teams.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Lead Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-06-08", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Design-Engineer_R52876", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nThe Lead Analog Design Engineer will take a Key role on the Analog and Mixed signal design team as part of a Die to Die Product Development Team. \nJob  Responsibilities: \nDesign of High Speed D2D and SERDES products at industry standard data rates up on leading edge technology nodes (e.g. 3nm FinFET CMOS) \nDesign and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications  \nWork closely with Layout Design Engineers to design IC circuit blocks and PMA sections  \nWork with Technical Team Leads in the areas of circuit design and SERDES architectures \nWork with global teams (US, west coast and east coast), which work in different time-zones \n\nJob Qualifications: \nBEng, MEng, PhD or equivalent. \nCandidate’s background should include a minimum of 5 years of CMOS design experience, preferably in the area of CMOS SERDES or high-speed I/O IC design \nShould have a good understanding of jitter and signal equalization techniques \nDesign experience in some of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators \nExcellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment \nPosition requires proficiency in using CAD tools for circuit simulation, layout and physical verification \n\nAdditional Skills/Preferences:  \nCadence tool experience is desirable and design experience at >10Gbps and in <16nm technologies  \nLab test experience as part of silicon evaluation is advantageous \n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Principal Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-06-08", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Design-Engineer_R52874", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nThe Lead Analog Design Engineer will take a Key role on the Analog and Mixed signal design team as part of a Die to Die Product Development Team. \nJob  Responsibilities: \nDesign of High Speed D2D and SERDES products at industry standard data rates up on leading edge technology nodes (e.g. 3nm FinFET CMOS) \nDesign and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications  \nWork closely with Layout Design Engineers to design IC circuit blocks and PMA sections  \nWork with Technical Team Leads in the areas of circuit design and SERDES architectures \nWork with global teams (US, west coast and east coast), which work in different time-zones \n\nJob Qualifications: \nBEng, MEng, PhD or equivalent. \nCandidate’s background should include a minimum of 8 years of CMOS design experience, preferably in the area of CMOS SERDES or high-speed I/O IC design \nShould have a good understanding of jitter and signal equalization techniques \nDesign experience in some of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators \nExcellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment \nPosition requires proficiency in using CAD tools for circuit simulation, layout and physical verification \n\nAdditional Skills/Preferences:  \nCadence tool experience is desirable and design experience at >10Gbps and in <16nm technologies  \nLab test experience as part of silicon evaluation is advantageous \n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Sr Principal Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-06-08", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Sr-Principal-Design-Engineer_R54511", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nThe Lead Analog Design Engineer will take a Key role on the Analog and Mixed signal design team as part of a Die to Die Product Development Team.\nJob Responsibilities:\nDesign of High Speed D2D and SERDES products at industry standard data rates up on leading edge technology nodes (e.g. 3nm FinFET CMOS)\nDesign and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications\nWork closely with Layout Design Engineers to design IC circuit blocks and PMA sections\nWork with Technical Team Leads in the areas of circuit design and SERDES architectures\nWork with global teams (US, west coast and east coast), which work in different time-zones\n\nJob Qualifications:\nBEng, MEng, PhD or equivalent.\nCandidate’s background should include a minimum of 8 years of CMOS design experience, preferably in the area of CMOS SERDES or high-speed I/O IC design\nShould have a good understanding of jitter and signal equalization techniques\nDesign experience in some of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators\nExcellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment\nPosition requires proficiency in using CAD tools for circuit simulation, layout and physical verification\n\nAdditional Skills/Preferences:\nCadence tool experience is desirable and design experience at >10Gbps and in <16nm technologies\nLab test experience as part of silicon evaluation is advantageous\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Principal Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-06-08", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Design-Engineer_R52873-1", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nThe Lead Analog Design Engineer will take a Key role on the Analog and Mixed signal design team as part of a Die to Die Product Development Team. \nJob  Responsibilities: \nDesign of High Speed D2D and SERDES products at industry standard data rates up on leading edge technology nodes (e.g. 3nm FinFET CMOS) \nDesign and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications  \nWork closely with Layout Design Engineers to design IC circuit blocks and PMA sections  \nWork with Technical Team Leads in the areas of circuit design and SERDES architectures \nWork with global teams (US, west coast and east coast), which work in different time-zones \n\nJob Qualifications: \nBEng, MEng, PhD or equivalent. \nCandidate’s background should include a minimum of 8 years of CMOS design experience, preferably in the area of CMOS SERDES or high-speed I/O IC design \nShould have a good understanding of jitter and signal equalization techniques \nDesign experience in some of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators \nExcellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment \nPosition requires proficiency in using CAD tools for circuit simulation, layout and physical verification \n\nAdditional Skills/Preferences:  \nCadence tool experience is desirable and design experience at >10Gbps and in <16nm technologies  \nLab test experience as part of silicon evaluation is advantageous \n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Staff Analog Design Engineer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-06-08", "url": "https://careers.skyworksinc.com/job-invite/76661/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 76661\n\nDescription\n\nStaff Analog IC Design Engineer, Power\n\nSeeking an experienced Analog/Power IC design engineer for developing complex analog mixed signal/integrated power management ICs for Industrial Control, Industrial Power, Isolation, and other Infrastructure applications. This design group is at the forefront of the EV revolution, working to develop technologies that will revolutionize vehicles and enable new levels of power efficiency.  The position requires a deep analog circuit design background including a strong history of innovative product and IP definition and design.  The desired individual will participate in product roadmaps, definition, technology selection, design, and verification. The individual will have a role in defining and implementing the overall system architecture, designing transistor-level analog circuit blocks, simulating sub-system performance, creating and using behavioral models of blocks and the entire IC, doing and/or supervising physical layout, verifying circuit and chip-level operation and performance, and assisting with tape-out related activities. Responsibilities will also include detailed documentation, silicon evaluation and debugging, production test development support, customer support, and other activities as required to achieve high volume production.\n\nResponsibilities\n\n \n\nArchitects, designs and verifies circuits, systems, algorithms, etc. to meet product requirements\n\nDevelops innovative new designs for patenting or protecting as trade secrets\n\nParticipates and contributes to product definition\n\nBalancing innovation with execution to ensure that the projects are delivered in a timely manner\n\nDemonstrates good judgment in solving a broad range of issues, based on an advanced understanding of industry practices and company policies and procedures\n\nResponsible for custom layout including overseeing the work of layout designers\n\nReports on design results through design reviews\n\nAttends design reviews to provide input and learn from other designers’ experiences\n\nSets the example for more junior members on the technical team by thoughtful use of quantitative analysis and intuition to solve mixed signal problems of advanced complexity\n\nResearch design techniques through technical publications and seminars\n\nMinimum Requirements\n\n8+ Years of  Analog/Power IC design engineer experience.\n\nAdvanced knowledge of MOS transistors and analog circuit design\n\nKnowledge of complex AC/DC analysis (poles, zeros, compensation), loop dynamics and feedback systems\n\nAdvanced knowledge of device physics and CMOS/BiCMOS fabrication processes\n\nPrevious design experience with complex mixed signal design problems\n\nAdvanced knowledge in signals, systems and transforms\n\nExperience with end to end design flow from product definition to high volume manufacturing including support of production test, applications validation and manufacturing problem solving\n\nAdvanced understanding of layout tradeoffs for performance and size\n\nExperience mentoring junior engineers\n\nStrong background in analog signal chain solutions\n\nStrong knowledge of circuit simulation tools, layout verification tools, modeling tools, and UNIX\n\n \n\nAdditional Skills (one or more of these are highly desirable)\n\nKnowledge of high voltage processes and design in BCD and/or SOI type processes\n\nPrevious design experience with integrated power conversion circuits (SD-ADC, SAR ADC, DC-DC/Power converters, charge-pumps, LDO’s, oscillaotrs, rectifiers, amplifiers)\n\nAdvanced MOS Device modeling skills (noise, excess thermal noise, DIBL)\n\nExceptional laboratory measurement skills\n\nSystem knowledge (e.g., isolators) and advanced design skills in system modeling\n\nUnderstanding of mixed signal solutions including discrete time digital signal processing\n\nFamiliarity with quality systems documentation and procedures\n\nExcellent written and verbal presentation skills\n\n#LI-CB1\n\nRequired Experience and Skills\n\nDesired Experience and Skills\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Staff AMS Verification Engineer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-06-08", "url": "https://careers.skyworksinc.com/job-invite/77439/", "is_hardware": true, "platform": "successfactors", "jd_text": "If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates.\n\nRequisition ID: 77439\n\nDescription\n\nSkyworks Solutions is seeking an accomplished Staff level Engineer to join our Analog/Mixed-Signal (AMS) Verification team. In this role, you will play a critical part in developing and advancing industry-leading AMS verification methodologies, defining scalable workflows, and selecting best-in-class tools to enable zero-defect product development while meeting competitive project schedules.\nThe successful candidate will perform hands-on verification of complex mixed-signal blocks, including data converters (DAC, ADC), power-on-reset circuits (POR), low-dropout regulators (LDOs), oscillators, state machines, and digital interfaces. You will derive comprehensive verification and test plans directly from product and system requirements, working closely with design teams to build deep design understanding and provide clear, actionable feedback on functionality, performance, and coverage.\nThis position requires a strong background in analog or mixed-signal circuit theory and with demonstrated expertise in simulation and verification environments such as Cadence. Verification will leverage both traditional analog/mixed-signal (AMS) techniques and event-driven digital mixed-signal (DMS) methodologies. Accordingly, experience developing SystemVerilog testbenches and creating analog behavioral models using Verilog-A and SystemVerilog Real Number Modeling (RNM) is highly desirable.\nThe ideal candidate brings excellent communication skills, a highly collaborative working style, and a passion for excellence.\n\n#LI-DB1\n\nResponsibilities\n\nYour key responsibilities will include but not be limited to:\n•    Perform end-to-end analog/mixed-signal verification of RFICs from block-level through full-chip integration, leveraging schematic, behavioral, and functional views to achieve comprehensive coverage while meeting project schedules.\n•    Develop Verilog-A and SystemVerilog RNM behavioral models for analog and mixed-signal circuits. Perform equivalence checks to validate behavioral models match schematics. \n•    Define and execute verification plans derived directly from product specifications.\n•    Partner closely with design teams to develop deep understanding of custom circuits, providing verification feedback on functionality and performance.\n•    Review layout and floorplans to proactively identify and resolve issues.\n•    Continuously improve verification methodologies with an emphasis on scalability, reusability, and portability across programs.\n•    Optimize models to ensure accuracy while maintaining efficient simulation performance \n•    Document modeling and verification methodologies, and promote best practices across teams and programs.\n•    Stay current with industry trends and emerging techniques in analog and mixed-signal modeling and verification.\n\nRequired Experience and Skills\n\n•    MSEE with 8+ years of related experience \n•    Hands on AMS design experience with strong knowledge of Analog/Mixed-Signal circuits, including LDOs, PORs, ADCs, Voltage-Current references and oscillators. \n•    Experience creating and verifying Verilog-A and SystemVerilog RNM behavioral models for analog circuits.\n•    Knowledge of analog layout and best practices for isolation, matching, noise avoidance and reliability. \n•    Knowledge of semiconductor process technologies such as CMOS, GaAs/Silicon HBT, SOI, BiCMOS\n•    Experience with EDA tools, such as Cadence Virtuoso and ADS.\n•    Basic scripting language skills, such as Python, is a plus.\n•    Excellent communications skills with the ability to work and thrive in a team environment\n\nSkyworks is an Equal Opportunity Employer.  All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.", "jd_status": "stored"}, {"title": "Staff R&D Engineer (C++)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-06-08", "url": "https://careers.synopsys.com/job/bengaluru/staff-r-and-d-engineer-c/44408/96150977248", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nYou are a highly skilled R&D engineer who is energized by working deep in the core internals of a large, mission-critical EDA product. You take pride in writing robust, performant, and maintainable C++ on UNIX/Linux, leveraging modern IDEs and AI-assisted developer environments to accelerate development. You have a deep appreciation for the data structures, memory layouts, and algorithmic choices that determine whether a tool scales gracefully to billion-gate designs and enjoy reasoning about netlist representations, graph traversals, hashing strategies, and the subtle trade-offs between runtime, memory footprint, and capacity.\nYou communicate clearly and employ a methodical approach to solving complex problems. You see software craftsmanship — clean interfaces, disciplined testing, and measurable improvements — as the foundation of long-term product health.\n\nWhat You'll Be Doing\nArchitect, develop, and own core infrastructure of the Formalityverificationengine.\nDrive runtime, memory, and capacity improvements profiling production designs and re-engineering hotspots to deliver step-function gains.\nDesign and hardenparallelarchitecturesto scale equivalence checkingtomodernmulti-core machines.\nTake end-to-end technical ownership of complex customer escalations rooted in layers — reproducing, root-causing, fixing, and adding the safeguards that prevent regression.\nInitiatedesign reviews, raise the bar on code quality and unit-test coverage.\nCollaborate across teams to enable the abstractions needed for future capabilities.\n\nThe Impact You Will Have\nDefine the structural and performance ceiling of Formality, directly enabling our customers to sign off larger and more complex designs with confidence.\nStrengthen the long-term architectural foundation of a flagship Synopsys product trusted across every major semiconductor company.\nInfluence the technical direction of the team through design leadership, mentorship, and a strong example of engineering rigor.\nHelp accelerate the tape-out cycles of the chips that power AI, mobile, automotive, and high-performance computing worldwide.\n\nWhat You'll Need\nBE/B.Techin Computer Science, Electrical, or Electronics Engineering with strong relevant experience, or an MS / PhD in a related discipline.\n\n5+ years (BE/B.Tech),3+ years (MS), or 2+ years (PhD) of professional software development experience in large, production C++ codebases, with demonstrated module ownership and technical leadership on non-trivial features.\nExpert command of modern C++, the STL, templates, and idiomatic memory and lifetime management for performance-sensitive systems.\nStrong fundamentals in data structures and algorithms — graphs, hash tables, trees, traversal andBDD— with a track record of applying them to real engineering problems.\nDemonstrated ability to profile, diagnose, and optimize for runtime, memory, and scalability on multi-million-instance workloads.\nWorking knowledge of HDLs (Verilog /SystemVerilog/ VHDL) and digital design fundamentals; familiarity with synthesis, equivalence checking, or related EDA flows is strongly preferred.\nComfort with TCL, Python, and shell scripting for tool infrastructure, regressions, and developer tooling.\nExposure to AI-assisted developer tools such as Cursor or GitHub Copilot, and a curiosity for adopting modern productivity practices.\nExcellent written and verbal communication, with the ability to lead technical discussions across teams.\n\nWho You Are\nA systems thinker who understands how a small change deep in thesystemripples through the entire product.\nA disciplined engineer who values measurement over intuition and tests over hope.\nA mentor and collaborator who lifts the technical quality of everyone around you.\nA pragmatic problem-solver who balances long-term architecture with short-term delivery.\nA continuous learner who keeps pace with advances in C++ and EDA methodology.\n\nThe Team You'll Be A Part Of\nYou will join the Formality R&D team — the group responsible for the structural backbone of one of the industry's most established formal equivalence checking tools. We own the data, the infrastructure, and the performance characteristics that every other Formality capability is built upon. The team values deep technical ownership, careful engineering, and a culture where strong opinions are tested against data. You will work alongside experienced engineers solving problems at the limits of design size, with broad exposure to formal verification, synthesis, and large-scale software systems.\n\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\n\n#TPG", "jd_status": "stored"}, {"title": "SoC Hardware Architect", "company": "NXP", "location": "Noida", "date_posted": "2026-06-05", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Noida/SoC-Hardware-Architect_R-10063819", "is_hardware": true, "platform": "workday", "jd_text": "Business Line Description:\nNXP's MPU Engineering (ACE) team is a central engineering organization responsible for developing and delivering Systems-on-a-Chip (SoCs) for NXP's Automotive, Edge, and Radar Processing business lines. MME's SoC Hardware Architecture team produces architectural solutions covering the very wide-range of SoCs required by the business lines. The team is challenged to produce industry-leading solutions covering very cost-sensitive, low power devices to highly-integrated, high performance, multi-domain devices compliant with the latest automotive and industrial safety and security standards.\n\n \nJob Summary:\nExperience in  architecting complex SoCs in leading-edge process nodes involving multiple processors, coherent/non-coherent interconnects, memory controllers, Ethernet interfaces, high bandwidth accelerators, high speed connectivity peripherals like PCIe etc\n\nWork with cross-functional architecture teams to develop holistic system-level SoC platform architectures targeting a specific product class or developing a specific technology solution which is scalable across a wide-range of product types and tiers.\n\nDeliver architecture specifications which include detailed system-level use-case definitions, hardware/software partitioning, alignment with existing industry standards, and relevant key performance indicators (KPIs).\n\nCollaborate with design and execution teams throughout the entire product development cycle to ensure your solution is successfully deployed in commercial product.\n\nDeveloping specifications for both internal and 3rd-party IP, participating in make v. buy analysis, and selecting the right IP.\n\n \nKey Challenges:\nExperience in designing or architecting complex SoCs in leading-edge process nodes with multiple independent compute environments.\n\nExposure to ISO26262-compliant and mixed-criticality architectures.\n\nDeep knowledge of ARM architecture specifications.\n\nExpertise in one or more the following technical areas: coherent and non-coherent interconnect, DDR memories, interconnect/system memory QoS, power & operating state management, PCIe, USB, networking, debug, boot, virtualization, machine-learning compute, or multimedia & pixel processing.\n\nAbility to work at the system-level, identifying optimal partitioning of solutions between hardware and software, working closely with software architects.\n\nTrack record of assessing performance, power, and area tradeoffs and determining the correct balance for a given product type.\n\nExperience in defining IP components to solve system issues.\n\n  \nJob Qualifications:\nBachelor's in Electrical Engineering or other similar discipline with at least 15 years of relevant experience. \n\nMaster's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with 10 or more years of experience preferred.\n\nMore information about NXP in India...\n\n#LI-2734", "jd_status": "stored"}, {"title": "Senior Staff Engineer Test Engineering", "company": "Infineon", "location": "Bangalore", "date_posted": "2026-06-04T06:42:34+00:00", "url": "https://jobs.infineon.com/careers/job/563808971026669", "is_hardware": true, "platform": "eightfold", "jd_text": "12+ years’ experience in ATE Testing of power products ( Power stages, Power modules, Point of Loads, Power sequencer, etc.)\n\nYour Role\n\nKey responsibilities in your new role\n\n12+ years’ experience in ATE Testing of power products ( Power stages, Power modules, Point of Loads, Power sequencer, etc.)\nStrong Analog/Mixed/Power products test knowledge\n Experience in defining test strategy for new products\n Ensure DFT/DFM standards for new products\n New products Test development experience from Design to release Production\n Proven records with Test cost reduction techniques\n Strong leader with Technical back ground\n Experience in ATE Char/Qual Programs development\n Well experienced in Test Hardware/Software qualification and release process\n Good Work Experience in ETS800 tester platform.\n Familiar in Programming languages ( C, C++ , Java, Python, etc.)\n\nYour Profile\n\nQualifications and skills to help you succeed\n\nTest Content development in ETS800/ 93K power tester\nTest HW design & development\nQual/ATE Char program/HW development\nNew silicon test bring up/debug\nMentoring/Leading test engineering team on power products\nLeading new products test development\n\nContact:\n    VidhiAshok.Thakkar@infineon.com\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\nThis means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.\nPlease let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.\nClick here for more information about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Design Engineering Architect", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-06-04", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Design-Engineering-Architect_R54512", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nThe Lead Analog Design Engineer will take a Key role on the Analog and Mixed signal design team as part of a Die to Die Product Development Team.\nJob Responsibilities:\nDesign of High Speed D2D and SERDES products at industry standard data rates up on leading edge technology nodes (e.g. 3nm FinFET CMOS)\nDesign and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications\nWork closely with Layout Design Engineers to design IC circuit blocks and PMA sections\nWork with Technical Team Leads in the areas of circuit design and SERDES architectures\nWork with global teams (US, west coast and east coast), which work in different time-zones\n\nJob Qualifications:\nBEng, MEng, PhD or equivalent.\nCandidate’s background should include a minimum of 8 years of CMOS design experience, preferably in the area of CMOS SERDES or high-speed I/O IC design\nShould have a good understanding of jitter and signal equalization techniques\nDesign experience in some of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators\nExcellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment\nPosition requires proficiency in using CAD tools for circuit simulation, layout and physical verification\n\nAdditional Skills/Preferences:\nCadence tool experience is desirable and design experience at >10Gbps and in <16nm technologies\nLab test experience as part of silicon evaluation is advantageous\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Principal Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-06-04", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Design-Engineer_R52872", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nThe Lead Analog Design Engineer will take a Key role on the Analog and Mixed signal design team as part of a Die to Die Product Development Team. \nJob  Responsibilities: \nDesign of High Speed D2D and SERDES products at industry standard data rates up on leading edge technology nodes (e.g. 3nm FinFET CMOS) \nDesign and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications  \nWork closely with Layout Design Engineers to design IC circuit blocks and PMA sections  \nWork with Technical Team Leads in the areas of circuit design and SERDES architectures \nWork with global teams (US, west coast and east coast), which work in different time-zones \n\nJob Qualifications: \nBEng, MEng, PhD or equivalent. \nCandidate’s background should include a minimum of 8 years of CMOS design experience, preferably in the area of CMOS SERDES or high-speed I/O IC design \nShould have a good understanding of jitter and signal equalization techniques \nDesign experience in some of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators \nExcellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment \nPosition requires proficiency in using CAD tools for circuit simulation, layout and physical verification \n\nAdditional Skills/Preferences:  \nCadence tool experience is desirable and design experience at >10Gbps and in <16nm technologies  \nLab test experience as part of silicon evaluation is advantageous \n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Principal Engineer, STA", "company": "Astera Labs", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-06-03T05:04:08-04:00", "url": "https://job-boards.greenhouse.io/asteralabs/jobs/4700203005", "is_hardware": true, "platform": "greenhouse", "jd_text": "Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\n\nRole Overview\n\nAstera Labs is hiring a Principal Engineer, Static Timing Analysis to own top-level timing closure and signoff for our next-generation connectivity silicon powering rack-scale AI infrastructure. In this role, you'll drive full-chip STA strategy across advanced process nodes, partner with physical design, RTL, DFT, and CAD teams, and ensure first-pass timing success on some of the most complex SoCs in the industry.\n\nThis is a high-impact technical leadership role at a hyper-growth company purpose-built for AI connectivity. Your work directly enables the PCIe, CXL, UALink, and Ethernet platforms that hyperscalers depend on — and you'll have the ownership, influence, and tooling to do the best work of your career.\n\nKey Responsibilities\n\nFull-Chip STA Signoff & Timing Closure\n\nOwn end-to-end top-level STA signoff across multiple modes, corners, and operating conditions (MMMC) for complex AI connectivity SoCs\n\nDrive timing convergence on advanced process nodes (5nm/4nm/3nm and below) from early floorplan through tapeout\n\nAnalyze and resolve setup, hold, recovery/removal, and clock-domain crossing (CDC) timing violations at the chip level\n\nMethodology & Flow Development\n\nDefine and evolve STA methodology, constraints (SDC) strategy, and signoff criteria across the organization\n\nDevelop and automate flows using PrimeTime, PrimeTime SI, and related signoff tools for crosstalk, noise, and IR-aware timing\n\nEstablish best practices for hierarchical STA, ETM/IPXACT model generation, and budgeting across blocks\n\nCross-Functional Technical Leadership\n\nPartner with Physical Design, RTL, DFT, CAD, and Package teams to drive timing-aware design decisions from architecture through tapeout\n\nReview and sign off on block-level timing handoffs, ensuring consistency between block and top-level closure\n\nCollaborate with low-power design teams on UPF/CPF, multi-voltage, and clock-gating timing implications\n\nMentorship & Technical Strategy\n\nMentor STA engineers and review timing reports, ECOs, and signoff collateral\n\nDrive root-cause analysis of silicon timing issues and feed learnings back into methodology\n\nInfluence tool selection, EDA vendor engagements, and STA roadmap for future products\n\nBasic Qualifications\n\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field\n\n10+ years of hands-on experience in Static Timing Analysis on complex ASIC/SoC designs\n\nProven track record of full-chip top-level STA signoff on at least one tapeout at advanced nodes (7nm or below)\n\nDeep expertise with PrimeTime, PrimeTime SI, and SDC constraint development\n\nStrong understanding of clocking architectures, CDC, OCV/AOCV/POCV, crosstalk, and IR-aware timing\n\nProficiency in scripting (Tcl, Python, Perl) for STA flow automation and report analysis\n\nPreferred Qualifications\n\nExperience with high-speed connectivity SoCs (PCIe Gen 6/7, CXL, UALink, or Ethernet)\n\nFamiliarity with hierarchical STA, ETM/ILM models, and timing budgeting across large partitions\n\nExperience with low-power signoff (UPF/CPF), multi-voltage domains, and DVFS timing implications\n\nStrong cross-functional collaboration and mentorship skills in a fast-paced product environment\n\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.", "jd_status": "stored"}, {"title": "Engineer, Physical Design", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-06-03T04:45:07.694000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000129909171-engineer-physical-design", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are looking for a motivated Physical Design Engineer to join our Renesas team who can work independently with little or no supervision.  Our candidate should be able to execute physical design flow (RTL-GDSII & STA) per planned schedule, assess risk and meet all deliverables. Candidate must monitor and drive the program from initiation to tapeout, interfacing with internal and external stakeholders and achieve alignment across cross-functional teams.\nResponsibilities:\nDrive block level/full chip Place & route and timing closure (Synthesis, PNR, STA and Physical verification).\nClosely work with mixed signal custom design team on full chip floorplan to integrate analog macros\nPerform Physical verification DRC, LVS, Antenna & IR-EM checks and fixing errors\nRun timing analysis, debug timing violations and implement functional, timing ECOs and perform formal verification.\nWork on multi-mode and multi-corner timing closure, RC extraction, Cross talk and signoff.\nWork closely with RTL design team to understand design, constraints, clocking and identify issues.\nSetup scan insertion and Integrate DFT\nScript in Tcl/perl to find workaround and solutions to problems and tool issues.\nCustomize Synthesis, PNR, STA flows and scripts for various finfet technologies.\n\nB.Tech or M.Tech in Electronics or Electrical with atleast 2+ years experience in physical design & timing closure.\nOwned Physical Design and taped out at least a minimum of 1 projects, at least one of them being a first-generation project\nThorough in PD flows, physical verification and multiple tape out experience.\nWorked on Synthesis, timing analysis & closure, generating ECOs.\nExperienced in Cadence synthesis, place and route, timing analysis and verification tools.\nStrong scripting skills - Tcl, perl, csh etc.\nAbility to create methodologies and automate flows.\nWorked with foundries/IP vendors on tech files, libraries, IP collaterals\nVery good knowledge of timing libraries, corners/modes, process variations and signal integrity related issues in advanced technology nodes (28nm and below)\nAbility to work in a dynamic environment with changing requirements\nTeam player with excellent communication skills\nHighly motivated and inspired to continue learning & improving as an individual and as part of a group.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Sr Staff Quality Assurance Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-06-03T04:00:48.846000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000129907880-sr-staff-quality-assurance-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Job Summary\nThe Product Quality Engineer (PQE) is responsible for ensuring quality and reliability performance of our products, wherever they are designed, manufactured, and assembled, by performing best in class Product Qualification in accordance with international standards and customer requirements. The PQE is also responsible for Reliability Monitoring through ORT.\nThe PQE works cross-functionally with Design, Test, Manufacturing, Reliability Labs, FA Labs, and Customer/Supplier Quality to prevent defects, drive robust product quality and continuous improvement initiatives.\nKey Responsibilities\nAttend related Milestones Meetings starting at Design kick-off through to production transfer.\nDefine, perform, and review Qualification (new products, second source, material changes, design changes, process changes, …)\nDefine, evaluate, and implement suitable stress tests for related product applications.\nEnsure product compliance with internal specifications, customer requirements, and applicable standards (e.g., ISO 9001, IATF 16949, IEC, JEDEC, AEC, etc.).\nCommunicate qualification plans and data with customer (Silicon, Package and Board Level).\nParticipate in risk assessments (e.g., DFMEA) and ensure mitigation actions are implemented and validated.\nReview qualification test results, assess risks, and provide quality approval for production release or change management.\nGenerate and publish qualification reports.\nHandling of the resolution for qualification related issues in a timely manner.\nCoordinate failure analysis for qualification failures using electrical, mechanical, or materials analysis techniques.\nDefine and implement measures jointly with related teams to achieve high product robustness.\nHighlight in timely manner potential criticalities and risks on the success of qualifications.\nEnsure lessons learned from product quality issues are systematically fed back into design and process improvements.\nKey Performance Measures\nQualification achievement in terms of timing, quality, and costs.\nOverall Product Quality achievement alignment to Division KPIs\n\nBachelor’s or master’s degree in engineering with 8+ years of relevant experience\nPrior team leadership experience is preferred.\nGood understanding of semiconductors and the semiconductor industry.\nGood understanding of semiconductor manufacturing processes (wafer fab, assembly, test).\nStrong knowledge on industry quality, reliability standards, and qualification methodologies.\nExperience with failure analysis workflows and quality tools (FMEA, 8D, root cause analysis).\nStrong analytical and structured problem-solving mindset.\nGood understanding of automotive customer or AI product customer high quality requirement.\nExcellent communication skills with both technical and non-technical stakeholders.\nAbility to work independently and with cross-functional teams.\nCustomer-focused, detail-oriented, and able to manage multiple priorities.\nComfortable working in a global, multicultural environment.\nSelf-motivated and business service minded.\nExcellent interpersonal, organizational and communications skills\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Senior SOC Verification Engineer - Networking", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-06-03", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-SOC-Verification-Engineer---Networking_JR2018721", "is_hardware": true, "platform": "workday", "jd_text": "We are now looking for a SOC Verification Engineers! NVIDIA is seeking outstanding SOC Verification Engineers to verify world’s leading Smart Network Interface Cards (Smart-NICs) and Data Processing Units (DPUs). NVIDIA’s Networking Chip Design group works on Smart-NICs and DPUs which help accelerate network performance while reducing the CPU overhead of Internet Protocol (IP) packet transport, freeing more processor cycles to run applications. These networking processors also embed innovative hardware engines that offload and accelerate security with in-line encryption/decryption.With unmatched RDMA over Converged Ethernet (RoCE) performance, NVIDIA Smart-NICs and DPUs deliver efficient, high-performance remote direct-memory access (RDMA) services to bandwidth- and latency-sensitive applications!\n\nThe Networking Chip Design in India is a new team which is growing at a fast pace! We are currently seeking Verification Engineers with strong verification fundamentals to work in NVIDIA Networking Group's SOC team. As a SOC Verification Engineer at NVIDIA, be responsible for verification of the design, architecture and micro-architecture with opportunities for pre-silicon, emulation, and post-silicon activities. You will be working closely with architects, designers, emulation team, Software teams, pre and post silicon verification teams to accomplish your tasks.\n\nWhat you’ll be doing:\nBe responsible for integrating all the pieces for a given defined project milestone and deliver the model to relevant teams for further verification at cluster/sub-system/SOC/emulation levels.\n\nCome up with verification infrastructure and automated flows to ease the process of integrating multiple IPs\n\nUse advanced verification methodologies like e-specman, SV-UVM etc. and have good grasp of scripting languages like python,perl etc.\n\nPartnering closely with our design team to understand our architecture and the collaborate with Quality Assurance engineers to deliver excellent test coverage and improve the Hardware quality.\n\nCoordinate with internal and external teams across time zones.\n\nWhat we need to see:\nBS or MS in EEE or ECE with 4+ years of experience in design verification\n\nGood understanding of Logic Design and Architecture.\n\nStrong coding skills in SV, scripting languages (Perl/python) and C++.\n\nAbility to collaborate and work with multiple groups\n\nExposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.).\n\nExposure to Cluster/Sub-system/Fullchip/SOClevel verification environments\n\nWays to stand out from the crowd:\nPrior experience of SmartNICs (or DPU) and/or high-speed interconnects.\n\nStrong debugging, problem-solving and analytical skills.\n\nScripting knowledge (Python/Perl/shell).\n\nGood interpersonal skills and ability & desire to work as an excellent teammate.\n\nWidely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/\n\nNVIDIA is committed to encouraging a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.", "jd_status": "stored"}, {"title": "Staff Engineer Design", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-06-02T06:46:56+00:00", "url": "https://jobs.infineon.com/careers/job/563808961499536", "is_hardware": true, "platform": "eightfold", "jd_text": "#WeAreIn \r\nFor jobs that impact everyone's life. Build the future nobody’s dreamed of yet...\r\nAre you ready to rethink the impossible?\r\n\r\nAs a Staff Engineer Design on our Research & Development team, you'll have the opportunity to merge creativity with your\r\ntechnical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life.\r\n\r\nAre you in? \r\n\nIn your new role you will:\n\nDesign analog and mixed-signal system blocks of DC-DC converter power stages and POL ICs including POR, Bandgap, LDO, Oscillators, drivers,current sensing, test modes etc.\nAssist in defining the requirements for analog and mixed-signal blocks, aligning them with IP Module architecture, and ensuringcompliance with requirements through documentation.\nProvide essential support to physical design engineers, post-silicon validation, production testing, and other critical activities extending beyond the design phase.\nCommunicates with cross functional/inter disciplinary team as needed to make sure the team is aware of the assumptions and progress made by the design team.\nBalance innovation with execution: to ensure that the projects aredelivered in a timely manner.\n\nYou are best equipped for this task if you have:\n\nA Master’s degree in Electrical/Electronic Engineering, microelectronics, or comparable with a focus on electronics.\n5+ years of experience in Analog IC design with a proven track record of delivering high-performance DC-DC converter Power IC solutions.\nGood Analytical skills and a very good understanding of Analog Design, like biasing, small signal and large signal analysis.\nProficiency with industry-standard design verification and simulation tools.\nUnderstanding of process technologies and device behaviour, which are important for high voltage, high power operation and reliability issues.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\nThis means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.\nPlease let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.\nClick here for more information about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Sr. Manager, ASIC Verification - Interface IP- PCIe/CXL", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-06-02", "url": "https://careers.synopsys.com/job/bengaluru/sr-manager-asic-verification-interface-ip-pcie-cxl/44408/95886030560", "is_hardware": true, "platform": "talentbrew", "jd_text": "* Sr. Manager, ASIC Verification - Interface IP- PCIe/CXL\n \n We Are\n \n Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n \n You Are\n \n You have spent a decade deep in PCI Express, and you know the specification the way most people know their commute. You have read the errata, tracked the ECNs, and debugged corner cases that only show up when three features collide in a way the spec never quite spelled out. You are the person teams pull into a room when something does not make sense.\n \n You have lived on both sides of the verification equation. Maybe you built Verification IP, maybe you used it to validate complex controller and PHY designs, but either way, you understand the gap between what a VIP can do and what a design team actually needs. That gap frustrates you, and you have strong opinions about how to close it. You think in requirements and traceability. Working across geographies and functions does not slow you down. You communicate clearly, align stakeholders without drama, and get results.\n \n What You'll Be Doing\n \n * Own the alignment between Verification IP capabilities and Design IP verification needs, identifying gaps in feature coverage for both Controller and PHY\n * Drive requirements definition for Verification IP based on real Design IP verification use cases\n * Track PCI Express specification updates, ECNs, and errata, translating changes into actionable requirements for both VIP and Design IP teams\n * Review and critique testplans across projects, pushing teams toward best-in-class coverage and traceability\n * Report VIP deployment metrics and drive continuous improvement in how VIP is integrated into verification flows\n * Work hands-on with UVM-based verification environments to validate VIP usage and model best practices\n \n The Impact You Will Have\n \n * You will close the gap between what Verification IP delivers and what Design IP teams actually need\n * Your work will shift verification left, catching issues earlier and reducing costly respins downstream\n * You will change how teams think about VIP as a strategic asset that evolves with design needs\n * Your protocol expertise will ensure Synopsys PCIe and CXL IP stays ahead of specification changes\n * You will standardize verification workflows, raising the bar for testplan rigor and coverage discipline\n * You will improve cross-functional collaboration between VIP and Design IP teams, reducing friction and improving product quality\n \n What You'll Need\n \n * 15+ years of hands-on experience in digital verification, with significant time on PCI Express or high-speed serial protocols\n * Deep subject matter expertise in PCI Express Link Layer and PHY Layer, including specification details and errata\n * Proven experience in IP product development, either building Verification IP or deploying it to verify complex Design IP\n * Strong UVM knowledge and experience in UVM-based verification environments\n * Track record of driving results in cross-functional, matrixed organizations across geographies\n * Experience with CXL or other coherent interconnect protocols is a plus\n \n Who You Are\n \n * You are results driven and define the path forward without waiting for perfect alignment\n * You critique testplans and verification strategies constructively, making the work better without making it personal\n * You are adaptable and thrive where priorities shift, teams are distributed, and stakeholders have competing needs\n * You think in systems, seeing how a gap in VIP coverage today becomes a customer escalation tomorrow\n * You are hands-on when it matters, jumping into a testbench or debugging a protocol sequence to unblock the team\n \n The Team You'll Be Part Of\n \n Your recruiter will share more about the team structure and mission during the interview process.\n \n Rewards and Benefits\n \n We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Validation/Characterization Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-06-02", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010896", "is_hardware": true, "platform": "oracle", "jd_text": "TI offers one of the world's largest comprehensive portfolios of high-performance synchronous rectifiers & modules.\n\nSR (SRLVB) is an exciting group within TI looking to power products for datacentre applications and demonstrate the significant performance benefits of TI’s technologies. Now specifically, we are expanding our SR product portfolio to aggressively grow our share in a fast-growing market.\n\nAccordingly, we are establishing a highly talented and aggressive team willing to take up tough challenges, drive innovation and build industry-best products for SR. This team has full product development responsibility from definition till releasing product to market. We also take pride in challenging norms on innovation & executing those innovative ideas into products with aggressive, customer-driven timelines.\n\nChange the world. Love your job.\n\nValidation engineers are said to have a ';break-the-part'; mentality. This means they spend some of their time working to identify the use-cases in which the device will stop working as intended and understand the impact and cause of those failures. Sometimes, those are acceptable failures, but others we may need to mitigate for quality, safety, or other reasons. Plus, we want to ensure that our parts are consistently performing to the specifications that we set in our data sheet, and even to some more conservative limits or as defined in the VVCM (validation/verification compliance matrix). To do this, they must design PCB boards and develop automation software that will increase coverage and reduce data collection time. Validation engineers will also design, develop, and implement necessary methods of measuring device performance and troubleshooting any related systems, equipment or device issues that arise. Validation engineers are often working in a post-silicon lab or on the software programs required to run their measurements.\n\nQualifications\nMinimum requirements:\n\nMinimum education (ie bachelor's degree in electrical engineering)\n\n5 years of experience.\n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Test Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-06-02", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010897", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n  This is a unique opportunity to be part of a team that drives testing of highly integrated multi-rail power management devices going into markets with significant growth potential. The ideal candidate would have a background that includes probe and final test development of complex mixed signal circuits.\n\nTI offers one of the world's largest comprehensive portfolios of high-performance synchronous rectifiers & modules.\n\n SR (SRLVB) is an exciting group within TI looking to power products for datacentre applications and demonstrate the significant performance benefits of TI’s technologies . Now specifically, we are expanding our SR product portfolio to aggressively grow our share in a fast-growing market.\n\nAccordingly, we are establishing a highly talented and aggressive team willing to take up tough challenges, drive innovation and build industry-best products for SR. This team has full product development responsibility from definition till releasing product to market. We also take pride in challenging norms on innovation & executing those innovative ideas into products with aggressive, customer-driven timelines.\n\nResponsibilities include:\n\nWork with design team to understand design specifications\n\nGenerate test plan, create test and char program, design ATE hardware interface boards\n\nDebug characterizing silicon on ATE, correlate results with bench data\n\nAnalyze silicon results, supporting failure analysis tasks\n\nPerform statistical analysis of yield fallout, debug and fix yield issues; optimize test time\n\nWork with production team to release products to volume production\n\nTest strategy definition and implementation for new DCDC converter products\n\nATE (Automatic Test Equipment) test hardware and software\n\nSilicon qualification& characterization including qual hardware development\n\nComprehensive device debugging, design validation and failure analysis\n\nDrive for robust and cost effective test solutions while being accountable for product quality\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in Electrical Engineering\n\n5 years of relevant experience\n\nATE experience on Teradyne Eagle or equivalent analog ATE (iFlex, LTX, VLCT), although Eagle experience is preferred and is a differentiator\n\nCharacterization test program and hardware development experience, Production test program and hardware development experience\n\nStrong technical knowledge of electronic devices and circuits, and Analog test techniques\n\nData analysis skills using Spotfire, dataPower or equivalent tool based on STDF\n\nExperienced with various lab equipment such as scopes, power supplies, sourcemeters, loads etc.\n\nExperience with product engineering activities such as yield improvement and test time reduction\n\nStrong understanding of the IC product development process, from concept to volume production\n\nPreferred qualifications:\n\nMixed signal test techniques and experience with developing mixed-signal tests on TI roadmap testers\n\nExperienced with test program and hardware offload to TI offshore manufacturing sites\n\nProficiency in programming/scripting in C++, Python, C#\n\nLabview, Teststand experience\n\nRevision control tools experience : Subversion, Git\n\nDemonstrated strong analytical and problem solving skills\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nStrong time management skills that enable on-time project delivery\n\nDemonstrated ability to build strong, influential relationships\n\nAbility to work effectively in a fast-paced and rapidly changing environment\n\nAbility to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Staff Application Engineer – Physical Implementation", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-06-02", "url": "https://careers.synopsys.com/job/bengaluru/staff-application-engineer-physical-implementation/44408/95886030464", "is_hardware": true, "platform": "talentbrew", "jd_text": "Alternate Job Titles:\nStaff Application Engineer – Physical Implementation\nSenior Implementation Solutions Engineer\nStaff Engineer – RTL-GDS Flow\nCustomer Success Engineer – EDA Tools\nTechnical Application Engineer – AI/ML Implementation\nWe Are:\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are:\nYou are energized by the hard problems—the ones where constraints collide, priorities shift, and the “right” answer depends on making smart, explicit tradeoffs. You thrive in fast-moving environments because you bring structure without slowing momentum: you clarify the goal, identify the true blockers, and keep the work anchored to outcomes that matter. You don’t wait for direction when you see a gap. You step in, propose a path, and invite others into a shared plan that’s clear, realistic, and measurable.\nYou operate with a customer-first instinct that shows up in how you listen and how you act. You seek to understand the intent behind a request, not just the words, and you’re comfortable challenging assumptions when it protects the end result. You communicate with purpose—direct, calm, and tailored to your audience—so engineers get actionable detail while stakeholders get crisp decisions and timelines. When pressure rises, you stay steady and pragmatic, breaking complex issues into solvable pieces and keeping progress visible so trust stays high.\nYou’re a natural connector across teams. You enjoy translating between different perspectives, aligning people around shared definitions of success, and turning feedback into forward motion. You balance attention to detail with an instinct for the big picture, and you care as much about repeatable methodology as you do about the immediate win. Above all, you take ownership: you follow through, you close loops, and you leave things better than you found them.\nWhat You’ll Be Doing:\nSolving complex PPA (Performance, Power, Area) challenges using Synopsys’ latest implementation technologies, including AI/ML Implementation, Physical Synthesis RTL-GDS, Multi Source CTS, and Indesign Fusion.\nBenchmarking Synopsys solutions against competitors to displace alternative implementation flows and demonstrate superior results.\nDeveloping, debugging, and optimizing RTL-GDS implementation methodologies and flows for emerging semiconductor technologies.\nProviding technical solutions by identifying design and EDA tool issues and delivering actionable resolutions for customers.\nTranslating technical findings into requirements for R&D, driving tool enhancements and adaptive long-term solutions.\nDeploying new technology features in the latest EDA tool versions and enabling customer migration for best-in-class PPA.\nProactively identifying customer pain points and proposing innovative solutions to address them.\nCollaborating closely with Synopsys R&D and product development teams to shape future technology directions.\nActing as a customer advocate during internal discussions and as a brand ambassador when engaging externally.\nThe Impact You Will Have:\nElevating customer success by delivering robust technical solutions and enabling optimal tool utilization.\nDriving Synopsys’ competitive advantage by displacing rival implementation flows and showcasing superior PPA outcomes.\nContributing to the enhancement of Synopsys products by providing critical feedback and requirements to R&D.\nAccelerating customer adoption of new technology nodes and EDA tool versions to achieve best-in-class results.\nStrengthening Synopsys’ reputation as the industry leader in physical implementation and innovation.\nFostering long-term customer relationships through proactive engagement and continuous support.\nWhat You’ll Need:\nAt least 3+ years of experience in Physical Implementation (RTL-GDS), with proven ability to debug and resolve synthesis & PnR challenges.\nStrong exposure to methodology changes aimed at achieving targeted PPA metrics for complex designs.\nProficiency in Synopsys implementation tools and flows is highly advantageous.\nAdvanced scripting skills (TCL, Unix, Perl) for automation and debugging.\nExcellent communication skills, including the ability to interface effectively with customers and internal teams.\nWho You Are:\nSelf-motivated and dedicated, with a passion for continuous learning and improvement.\nStrong analytical thinker with outstanding debug skills and attention to detail.\nCollaborative team player who thrives in dynamic, fast-paced environments.\nCustomer-centric, always advocating for the best outcomes and solutions.\nResilient and adaptable, able to manage multiple priorities and deliver results.\nThe Team You’ll Be A Part Of:\nJoin our Application Engineering team in Bangalore, where you’ll work directly with industry pioneers and innovators. The team’s mission is to solve critical design challenges, enhance quality-of-results metrics, and empower customers to achieve best-in-class performance. Collaboration with R&D and product development is central, ensuring that customer needs drive future technology advancements. Together, we set the standards for excellence in semiconductor design and implementation.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Pre-silicon Validation Engineer - Emulation", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-06-01T08:38:00+00:00", "url": "https://global-external-amd.icims.com/jobs/86048/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Pre-Silicon Validation Engineer (Emulation Validation)   THE ROLE:  We are looking for a dynamic, energetic Systems Design Engineer to join our growing team. As a key contributor to the success of AMD’s product, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry-leading technologies to market. The Systems Design Engineering team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.    THE PERSON:  As a Systems Design Engineer, you will drive balanced, scalable, and automated solutions. In this high visibility position, your software systems engineering expertise will be necessary towards Product development, definition, and root cause resolution.    KEY RESPONSIBILITIES:  Driving technical innovation to improve AMD’s capabilities across validation, including tool and script development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives Debugging issues found during the process, bring-up, validation, and production phases of SOC programs Working with multiple teams, and tracking test execution to make sure all features are validated and optimized on time Working closely with supporting technical teams Engaging in other software/hardware modeling frameworks     PREFERRED EXPERIENCE:   Significant 5+ years of relevant experience in complex SoC verification & Validation Prior hands-on experience with FPGA and/or emulation platforms (Veloce, Palladium, ZEBU, HAPs, Protium) Developing C/C++/Uefi based test content. Validating hardware features for at least 3 or more projects in a pre-silicon environment Debugging failures using waveform viewers, log files and microcode trace dumps Knowledge of low power design emulation/verification and power management fundamentals Knowledge of UEFI, Windows Operating Systems, Linux Knowledge of x86 and/or ARM SoC Architecture Knowledge of Memory subsystem, high speed IO peripherals like PCIe, USB, NPU, SoC & IP level Power Management flow, Security protocols. Knowledge of one or more protocols; USB, AXI, PCI, PCIe, MIPI. Good to have Pre-Silicon Validation Experience on SOC, Subsystems , MMIP, accelerators, CPU/Power Management/HSIO -PCIe/USB using Embedded C and BIOS Extensive knowledge of system architecture, technical debug, and validation strategy Strong analytical/problem-solving skills and pronounced attention to details Must be a self-starter, and able to independently drive tasks to completion   ACADEMIC CREDENTIALS:  Bachelors or Masters degree in electrical or computer engineering #LI-SS1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Physical Design Engineer, Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-06-01T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718705419", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nQualcomm Bangalore Camera Team is focused on developing high-performance, power-efficient, and highly optimized cores. In this role, you will drive end-to-end ownership of complex hierarchical modules, taking designs from RTL to GDSII, including synthesis, place & route, and timing closure, with a strong emphasis on achieving best-in-class PPA (Power, Performance, Area).\nYou will play a key role in delivering designs that push the boundaries of performance, efficiency, and scalability.\nWe foster a collaborative, creative, and flexible work environment, united by a shared vision to build innovative methods that have a meaningful impact.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nBachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\nOR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\nOR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nExperience:\n6+ years of experience in Physical Design, including floorplanning, Place & Route (PNR), Clock Tree Synthesis (CTS), and STA signoff checks\n\nHands-on experience owning end-to-end Physical Design from netlist to GDSII, including HM-level PV, LEC, low-power checks, PDN design, and STA closure\n\nExperience with voltage islands and low-power design methodologies, flows, and implementation\n\nStrong focus on achieving optimal PPA (Power, Performance, Area)\n\nStrong familiarity with industry-standard tools such as Fusion Compiler (FC), Genus, Innovus, , PrimeTime (PT), Tempus, Voltus, and RedHawk\n\nSolid understanding of the full Physical Design flow from floorplanning to post-route optimization and timing signoff, including IR drop analysis and physical verification\n\nExperience in implementing complex ECOs for timing convergence across multiple corners using Tweaker, Tempus, and physical ECO flows in PrimeTime\n\nKnowledge of power optimization techniques and methods to minimize power consumption\n\nExperience in deep submicron technology nodes (preferred)\n\nUnderstanding of high-performance and low-power implementation techniques (preferred)\n\nStrong fundamentals in Physical Design and VLSI concepts\n\nProficiency in scripting languages such as Perl, Python and TCL\n\nRoles and Responsibilities\nCollaborate with cross-functional teams (Design, CAD) to address critical physical design challenges in Camera PNR Implementation.\n\nDevelop innovative techniques within Physical Design and optimization space to meet stringent PPA targets.\n\nEngage with external CAD tool vendors and internal CAD teams to identify and enhance optimization issues related to Camera designs.\n\nPartner with all block-level implementation teams to analyze, implement, and improve optimization methods relevant to the designs.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff Engineer, Analog Design", "company": "Analog Devices", "location": "India, Bangalore, Nova", "date_posted": "2026-06-01", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-Nova/Staff-Engineer--Analog-Design_R262616", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nCome develop technology solutions that solve planetary scale problems in the Analog Devices Automotive Electrification business unit.  The electric vehicle and green-energy revolution is here, and we are changing the world with our industry leading battery monitoring technology. From the high-performance and thrill that EVs deliver to the carbon-footprint reduction that makes the world a greener place, we are looking for more innovators in the hardware, software, and system solutions that can help to make it all a reality.  Whether you are a car-lover, a battery-geek, or a technologist with a passion for a cleaner and more sustainable future, ADI Automotive Electrification is a premier career destination with a bright future. \n\nThis is an excellent opportunity to join a high performing team, working on the design of the next generation of automotive BMS chips. The designs include industry-leading low power radio transceivers, the industry’s highest precision battery monitoring technology, embedded micro-controllers, and other differentiated analog and digital components, developed in high voltage and advanced technology nodes. The Analog Design team is responsible for breaking down system level requirements into design specifications, architecting and designing analog/RF signal chains & subsystems, doing transistor level analog circuit design and simulations, doing block-level and system-level modeling and simulations, delivering blocks that meet timing, area, and performance requirements, as well as supporting  post-silicon validation and debug.\n\nLocation: Bangalore\nJob Levels available:  Staff Analog Design Engineer\nExperience Range : 7 to 12 Years\nMinimum Qualification: BS/BTech/MS/MTech degree and relevant experience in Analog Design. Job level will be commensurate with experience.\nPositions Available: Analog Design, RF Design\n\nDesired Skill Set (not every applicant will have all of these skills)\nExpertise and strong hands-on experience in transistor level analog design  \nExperience and a proven track record of bringing your designs to production\nUnderstanding of device level operation & physics\nKnowledge of low power design in sub-40nm process OR High Voltage analog circuit design experience & knowledge of BCD/HV processes\nGood understanding of layout considerations for either high precision analog applications or high speed analog design in sub-40nm process nodes and ability to oversee the same\nKnowledge of System aspects such as Noise Figure, Phase Noise, IIP3, ACI, BER, PER, Spurious Analysis is desirable for RF positions\nAnalog Design positions require design experience in any of the following analog blocks: Amplifiers/OPAMP circuits, ADCs/DACs, LDOs, Bandgaps & Bias Circuits, Temperature Sensor, Oscillators\nSenior Analog Design positions require the ability to architect and design analog signal chains for high precision analog applications.\nRF Design positions require experience in any of the following Analog design blocks: Low Noise Amplifier(LNA), Mixer, Charge Pump, Voltage Controlled Oscillator(VCO), Frequency Dividers, Power Amplifier etc.; knowledge of Wireless Transceiver architectures and System trade-offs will be a plus\nExperience in analog/mixed-signal co-simulations & analog verification\nExperience in lab evaluation of initial silicon, programming and data analysis in C#, Python, and/or Matlab\nStrong analytical and problem-solving skills\nStrong written and verbal communication skills\n\nIf this job posting draws your interest, we would love to hear from you!\n\nCome join Analog Devices – a place where Innovation meets Impact.  For the past 50 years, Analog Devices has been inventing innovative technologies that transform lives. Get hands-on experience working with the brightest minds to solve complex problems that matter - from autonomous vehicles, drones and factories to augmented reality to remote healthcare.  Enjoy a culture that values aligned goals, balanced work-life priorities, continuous learning throughout your career and shared rewards.  At ADI, we invest in you and succeed together because we believe that happy, healthy, intellectually challenged people drive our growth and market leadership.   \n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Senior Digital Design Engineer", "company": "Analog Devices", "location": "India, Bangalore, Nova", "date_posted": "2026-06-01", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-Nova/Senior-Digital-Design-Engineer_R262668", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nJob Description:\nOwn end-to-end physical implementation for major IP blocks and/or full-chip designs, ensuring alignment with ADI’s Career Development Framework (Expertise, Autonomy & Scope, Business Impact).\nDevelop and optimize floorplans (macro placement, IO ring planning, power grid design, congestion/area/timing analysis)\nExecute place-and-route, clock tree synthesis, and timing closure using industry-standard tools (Cadence Innovus).\nPerform detailed static timing analysis (STA) and drive sign-off across PVT corners and operating modes.\nIdentify and resolve physical verification issues (DRC/LVS/ERC) in close partnership with process/CAD/foundry teams, ensuring robust manufacturability.\nAutomate design flows (e.g., hierarchical PNR, IO ring automation, Flash PG) to improve efficiency and quality; contribute to continuous flow enhancements.\nCollaborate with RTL, DFT, verification, package, and library teams to meet performance, power, and area (PPA) targets and project milestones.\nMentor and coach junior engineers, sharing best practices in physical design and advancing team capability.\nDocument methodologies and contribute to best practices, supporting a culture of learning and continuous improvement.\nDemonstrate ADI values by being agile in adapting to changing business needs, leading by example, and striving for best-in-class results.\nRequired Qualifications:\nBachelor’s or Master’s in Electrical/Electronics Engineering or related discipline.\n5+ years of hands-on experience of ASIC/SoC physical design at advance nodes such as 40,28,22,16 etc.\nStrong proficiency in floorplanning, PNR, STA, and physical verification using industry EDA tools.\nExperience developing or deploying automated flows (Tcl, Perl, Python) to improve design productivity.\nDeep understanding of fabrication process limitations, ESD/IR/EM analysis, and robust sign-off methodologies.\nDemonstrated ability to communicate clearly, collaborate cross-functionally, and work effectively in a fast-paced, innovative environment.\nPreferred Qualifications:\nExperience with hierarchical design and large-scale SoC integration.\nSound Knowledge in EDA synthesis and formal equivalence checking\nBackground in low power and multi-voltage design methodologies (UPF/CPF).\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Principal SoC FW Validation/Productization Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-06-01", "url": "https://careers.arm.com/job/bengaluru/principal-soc-fw-validation-productization-engineer/33099/95839452256", "is_hardware": true, "platform": "talentbrew", "jd_text": "Principal SoC FW Validation/Productization Engineer\n \nArm is redefining what is possible in cloud and data center computing. Our Neoverse platforms are helping power a new era of infrastructure – combining advanced silicon with the system software required to turn ambitious technology into production-ready solutions.\nAre you excited by solving complex system-level problems, leading engineers and ensuring sophisticated SoC platforms are ready for production?\nWe are looking for a Principal Software Engineer in the infrastructure solutions software team in our CE-SW group. This role combines hands-on technical leadership with responsibility for leading and developing a local engineering team. The focus will be on driving the validation and productisation of our infrastructure platforms, with strong collaboration across software engineering, quality, test and release functions.\nCome and make an impact at scale!\nResponsibilities:\nYou will:\nLead and develop a team of software engineers at your site, providing technical direction, coaching and career development while remaining hands-on in solving complex engineering challenges.\nDrive system validation and productisation for Infrastructure System Solutions, establishing effective validation plans, quality criteria and approaches to product readiness.\nAdvance scalable test infrastructure, CI, regression capabilities and quality metrics to improve coverage, efficiency and confidence throughout the development lifecycle.\nCollaborate across Arm locations and engineering teams to manage dependencies, resolve complex system-level issues and drive effective execution across pre-silicon and silicon environments.\nRequired Skills and Experience :\nStrong experience in complex system software, with a technical background in SoC, firmware, platform software or system-level validation across pre-silicon and/or silicon environments.\nProven experience leading and developing software engineers, combining line management with strong hands-on technical leadership.\nStrong knowledge of software quality, validation methodologies, automated testing, CI and product readiness for complex systems.\nExcellent technical judgement, problem-solving and communication skills, with the ability to collaborate effectively across engineering teams and geographical locations.\n“Nice To Have” Skills and Experience :\nKnowledge of server-class SoCs, including RAS, power management, PCI Express (PCIe), Compute Express Link (CXL), memory and virtualization.\nFamiliarity with the Linux kernel, Trusted Firmware-A (TF-A), UEFI EDK II, OpenBMC or Kernel-based Virtual Machine (KVM).\nExperience with automated system validation, hardware test environments, server farms or continuous integration infrastructure.\nIn Return:\nAt Arm, we’re shaping the future of infrastructure computing and turning advanced technology into production-ready solutions. This role offers the scope to influence our products, engineering practices and teams while contributing to some of our most sophisticated platforms.\nJoin us and help shape world-class infrastructure technology at Arm!\nWe will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Principal ASIC Digital Design Engineer (Verification)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-06-01", "url": "https://careers.synopsys.com/job/bengaluru/principal-asic-digital-design-engineer-verification/44408/95856496016", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\n Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\n You have spent over a decade in verification, and you have learned that the difference between a verification flow that works and one that collapses under pressure is usually a decision made at the architecture stage. You are the engineer who catches that decision before it becomes technical debt. You think in systems, not scripts. You know that building verification infrastructure is not about assembling tools, it is about creating an environment where teams can move fast without breaking things.\n \n You have built verification environments from scratch using VCS, Verdi, VMS Execution Manager, and UVM, and you know where each tool shines and where it does not.\n \nWhat You'll Be Doing\n * Architect and implement unified verification flows for Synopsys digital IP products using VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs\n * Build scalable verification infrastructure from the ground up, designing environments that support complex IP and SoC projects across global teams\n * Define, document, and propagate verification methodologies and best practices that become the standard across Synopsys digital IP projects\n * Lead and mentor verification engineers, providing technical guidance on UVM, SystemVerilog, flow optimization, and debugging strategies\n * Drive technical initiatives independently, managing high-impact assignments from concept through deployment and adoption\n * Collaborate with EDA tool development teams to influence product roadmaps, provide feedback, and optimize verification workflows for real-world use cases\n * Troubleshoot and refine verification processes for internal teams and customers, diagnosing flow bottlenecks and delivering solutions that stick\n \nThe Impact You Will Have\n * Establish verification methodology standards that accelerate time-to-market for Synopsys digital IP and SoC products\n * Enable global verification teams to deliver higher quality results faster by providing robust, reusable flows and infrastructure\n * Shape the verification strategy for next-generation Synopsys IP offerings, directly influencing product quality and customer satisfaction\n * Reduce verification cycle time and resource overhead across multiple projects by standardizing tooling and best practices\n * Develop the next generation of verification engineers at Synopsys, building a culture of technical excellence and continuous learning\n * Influence the evolution of Synopsys EDA tools by providing critical, field-tested feedback to product teams\n * Strengthen Synopsys' leadership position in semiconductor verification by driving adoption of cutting-edge methodologies across the organization\n \nWhat You'll Need\n * 10+ years of hands-on experience in IP or SoC verification, with a proven track record of leading technical initiatives and delivering complex verification environments\n * Deep expertise with Synopsys verification tools including VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and Verification IP (VIP)\n * Strong programming and scripting skills in SystemVerilog, UVM, Tcl, and Python for automation and flow development\n * Demonstrated ability to architect verification flows and infrastructure for complex digital designs, from initial concept to production deployment\n * Bachelor's degree in Electronics, Electrical, or Computer Engineering; advanced degrees are a plus\n * Experience managing multiple technical projects independently, balancing priorities and delivering high-quality results on schedule\n * Ability to document and communicate technical methodologies clearly across global, cross-functional teams\n \nWho You Are\n * You can explain a complex verification tradeoff to a product manager in two sentences without losing the nuance, and then turn around and debug a UVM testbench with a junior engineer\n * You take ownership of problems that do not have clear owners, and you see them through to resolution even when it means coordinating across time zones and teams\n * You push back when a methodology does not make sense for the use case, and you do it with data and a better alternative, not just criticism\n * You are organized enough to manage five verification projects at once and strategic enough to know which one needs your attention today\n * You teach by showing, not just telling, and you measure your success by how much your team grows, not just what you deliver personally\n * You stay current with verification trends and tools, and you bring new ideas to the table backed by practical understanding of what will actually work in production\n \nThe Team You'll Be Part Of\n You will be a core member of the newly established Digital IP Verification Methodology (COE) team, a group of forward-thinking engineers dedicated to advancing verification excellence at Synopsys. The team collaborates across global sites, driving innovation in methodology, tool integration, and best practices. Together, you will shape the future of digital IP verification, enabling Synopsys and its customers to deliver world-class silicon solutions.", "jd_status": "stored"}, {"title": "Sr. Principal Product Engineer – Digital & Signoff Group (DSG)", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-06-01", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Sr-Principal-Product-Engineer---Digital---Signoff-Group--DSG-_R54770-1", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nSr. Principal Product Engineer – Digital & Signoff Group (DSG)\nLocation: Bangalore\nTeam: Cadence DSG (Digital & Signoff Group)\n\nThe Opportunity\nJoin Cadence’s Digital and Signoff Group (DSG) as a Product Engineer, where you will act as the vital bridge between R&D, Application Engineering, and our global customers. In this high-impact role, you will influence the next generation of chip design software, helping industry leaders solve complex physical design challenges at 7nm and below.\n\nKey Responsibilities\nTechnical Expert: Serve as the primary place-and-route (P&R) resource for internal development teams and external customers. Product Evolution: Collaborate with R&D to track, diagnose, and resolve software issues, ensuring a robust tool release cycle. Design Benchmarking: Execute competitive benchmarks to demonstrate Cadence’s edge in Power, Performance, and Area (PPA). Flow Innovation: Develop and deploy customized RTL-to-GDSII methodologies and scripts to meet specific customer design goals. Strategic Collaboration: Partner with Product Marketing to align technical capabilities with market needs and customer roadmaps.\n\nRequirements\nEducation:\nBachelors in Electronics Engineering (EE) + 8 or more years of industry experience,\nOR\nMasters in Electronics Engineering (EE) + 6 or more year of digital implementation experience.\n\nCore Expertise: Deep understanding of the full ASIC design flow (RTL-to-GDSII) with a focus on physical design and timing analysis. Advanced Node Experience: Proven hands-on experience with timing closure and PPA optimization at 7nm, 5nm, or below. Tool Proficiency: High familiarity with industry-standard EDA tools for synthesis, placement, routing, and signoff. Scripting Skills: Proficiency in Tcl, Python, or Perl (familiarity with AI-driven productivity tools is a major plus).\nCommunication: Strong verbal and written skills to translate complex technical issues into actionable solutions.\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Staff Engineer, SoC Verification", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-06-01", "url": "https://careers.arm.com/job/bengaluru/staff-engineer-soc-verification/33099/95845691664", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview:\nArm’s hardware is at the heart of computing and connectivity revolution that continues to transform the way people live and businesses operate. Working as a team and engaging with the world’s most famous technology companies, we are driving innovation into all areas where compute is possible to help us build better solutions for the billions of people using our technology worldwide. As we continue to grow, we need the best engineers to join a team responsible for the development of compute subsystems and solutions. You could be using your talents to develop the technologies that will enable the very latest compute solutions in today's enterprise and client markets.\nResponsibilities:\nSolution engineering team’s mission is to enable our partners by delivering secure, performant and reliable hardware and software that are easy to use. System Verification engineers in this group are responsible for driving verification specifications & methodology and deliver on the verification of SoC for the next generation of compute solution. Working in a highly focused group within Arm's Solutions Engineering Systems Development team, where the candidate will help verify our next generation compute solutions using innovative technologies, methodologies and tools. Key responsibilities will include verification plan, test plan, debug methodology, developing and implementing the test content, finding bugs, and running various verification checks for Arm IP and high-speed interfaces like PCIe, DDR, USB, etc.\nRequired Skills and Experience :\n8 to 12 Years of experience with Bachelors or Masters in Electronics, Electrical or Computer Engineering\nExperience in SoC Verification test content using C, C++ etc.\nExpertise in Arm Architecture, Arm core and Arm system IP (SMMU/GIC/DMS etc.).\nUnderstanding of the fundamentals of computer architecture and systems\nKnowledge of shell programming/scripting (e.g. Tcl Perl, Python etc.)\nExpected to own verification and compliance testing for select components of a modern system.\n“Nice To Have” Skills and Experience :\nDemonstrated understanding of CPU, GPU, Peripheral IP (PCI/CXL/USB/UFS/ETH) subsystem in SoC environment and proven expertise in owning verification requirements and plan.\nKnowledge of microarchitecture and experience with RTL debugging tools and methodologies is a plus.\nHands on Experience in verification of multiple sub systems for ASICs/ SoCs in system environment (Emulation, FPGA, FVP), owning all phases of verification (Test development, Execution and Debug) for owned sub systems.\nUnderstanding of SoC security aspects\n#LI-SC2\nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Staff RTL Design Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-06-01", "url": "https://careers.synopsys.com/job/bengaluru/senior-staff-rtl-design-engineer/44408/95856495952", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years building RTL that ships in silicon, not just passes simulation. When you read a protocol specification, you see the corner cases that will break three months into verification, and you architect around them before anyone else notices.\nYou are comfortable taking a huge page Ethernet spec and walking out with a micro-architecture that balances latency, power, and area without needing someone to hold your hand. You write Verilog that other engineers can actually read and maintain. You have debugged enough asynchronous FIFO issues and CDC violations to know what good design discipline looks like, and you hold yourself to it even when schedules get tight.\nMulti-site collaboration does not slow you down. You can review someone's RTL in a different timezone, leave clear feedback, and move the design forward without waiting for a meeting. At Synopsys, you will work on IP cores that power everything from AI accelerators to automotive systems, and the designs you own will matter.\n\nWhat You'll Be Doing\nDesign and code RTL for high-speed Ethernet IP cores ranging from 100G to 1.6T, focusing on low latency and timing closure in complex datapath and control logic\nTranslate protocol specifications and functional requirements into micro-architecture and detailed design documents for DesignWare IP in Ethernet, AMBA AXI, CHI, PCIe, USB, MIPI, or memory controller domains\nBuild and refine directed Verilog testbenches to improve functional and code coverage, analyzing metrics and defining targeted test cases that catch real bugs\nPerform technical reviews of functional specs, micro-architecture documents, and RTL code from peers across global design teams\nDrive timing analysis and closure for high-speed designs using synthesis, STA, lint, CDC, and formal verification flows\nApply low power design methodologies and automotive safety requirements to IP development\nCollaborate with verification, integration, and product teams across Bangalore, the US, and other global sites to deliver production-quality IP on schedule\n\nThe Impact You Will Have\nYour RTL will ship in customer SoCs powering data center infrastructure, automotive platforms, and AI systems used by millions of people\nThe micro-architecture decisions you make today will determine whether a customer's chip meets their performance and power targets six months from now\nYour coverage improvements and directed tests will catch silicon bugs before tapeout, saving customers months of respins and lost revenue\nThe design quality and documentation you deliver will set the standard for how the rest of the IP team approaches complex protocol implementations\nYour timing closure work on multi-gigabit interfaces will enable Synopsys to stay ahead in the race toward higher-speed Ethernet and interconnect IP\nThe technical reviews you provide will level up junior engineers and prevent architectural mistakes from becoming costly late-stage fixes\nYour ability to work across sites will keep globally distributed projects on track and reduce friction in cross-functional handoffs\n\nWhat You'll Need\nBachelor's in Electrical Engineering with 8+ years of hands-on ASIC or IP design experience, or Master's with 6+ years\nDeep RTL design experience on IP cores or SoC subsystems that have taped out or shipped to customers\nStrong working knowledge of at least one protocol from this list: AMBA (AHB, AXI, CHI), SD, eMMC, DDR, PCIe, USB, MIPI. High-speed Ethernet (100G and above) experience is a strong plus\nProven ability to create micro-architecture and detailed design documents from functional specs for small to medium complexity blocks, especially control-path designs like async FIFOs, DMA engines, or SRAM/DPRAM interfaces\nHands-on experience with Verilog or SystemVerilog, simulation tools, synthesis flows, static timing analysis, lint, CDC, and formal verification tools\nSolid understanding of high-speed, low-latency design techniques and timing closure challenges. Experience with datapath designs or arithmetic algorithms like FEC is a plus\nFamiliarity with Perforce or similar version control systems, and scripting in Perl or shell for automation\n\nWho You Are\nYou can take a vague feature request and turn it into a clean, implementable design without needing three rounds of clarification meetings\nWhen you review RTL, you catch the subtle issues that would have caused problems in integration, and you explain them clearly enough that the engineer learns something\nYou know how to prioritize when you are juggling timing closure, coverage improvements, and a design review scheduled for tomorrow, and nothing falls through the cracks\nYou communicate technical tradeoffs in writing and in review meetings with enough clarity that engineers in other timezones can act on your feedback without a follow-up call\nYou push back when a spec is ambiguous or a schedule does not account for real design complexity, and you do it in a way that moves the conversation forward\nYou treat documentation as part of the design, not an afterthought, because you know the next person reading your micro-arch doc might be you in six months\n\nThe Team You'll Be Part Of\nYou will join the IPG Group at the Bangalore Design Center as a technical individual contributor working on DesignWare IP cores. This is a multi-site team spread across global locations, focused on delivering high-speed protocol IP in areas like Ethernet, AMBA, PCIe, USB, MIPI, and memory controllers. The work is technically challenging, the designs are complex, and the team expects you to own your deliverables with minimal supervision while collaborating across timezones to hit shared milestones.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Principal Product Engineer – Digital & Signoff Group (DSG)", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-06-01", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Product-Engineer---Digital---Signoff-Group--DSG-_R54769", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nPrincipal Product Engineer – Digital & Signoff Group (DSG)\nLocation: Bangalore\nTeam: Cadence DSG (Digital & Signoff Group)\n\nThe Opportunity\nJoin Cadence’s Digital and Signoff Group (DSG) as a Product Engineer, where you will act as the vital bridge between R&D, Application Engineering, and our global customers. In this high-impact role, you will influence the next generation of chip design software, helping industry leaders solve complex physical design challenges at 7nm and below.\n\nKey Responsibilities\nTechnical Expert: Serve as the primary place-and-route (P&R) resource for internal development teams and external customers. Product Evolution: Collaborate with R&D to track, diagnose, and resolve software issues, ensuring a robust tool release cycle. Design Benchmarking: Execute competitive benchmarks to demonstrate Cadence’s edge in Power, Performance, and Area (PPA). Flow Innovation: Develop and deploy customized RTL-to-GDSII methodologies and scripts to meet specific customer design goals. Strategic Collaboration: Partner with Product Marketing to align technical capabilities with market needs and customer roadmaps.\n\nRequirements\nEducation:\nBachelors in Electronics Engineering (EE) + 6 or more years of industry experience,\nOR\nMasters in Electronics Engineering (EE) + 4 or more year of digital implementation experience.\n\nCore Expertise: Deep understanding of the full ASIC design flow (RTL-to-GDSII) with a focus on physical design and timing analysis. Advanced Node Experience: Proven hands-on experience with timing closure and PPA optimization at 7nm, 5nm, or below. Tool Proficiency: High familiarity with industry-standard EDA tools for synthesis, placement, routing, and signoff. Scripting Skills: Proficiency in Tcl, Python, or Perl (familiarity with AI-driven productivity tools is a major plus).\nCommunication: Strong verbal and written skills to translate complex technical issues into actionable solutions.\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Sr. Lead IP/RTL Design Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-05-29T05:19:00+00:00", "url": "https://global-external-amd.icims.com/jobs/74404/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Sr. Lead IP/RTL Design Engineer THE ROLE: As a member of the Data Fabric Team , you will help bring to life cutting-edge designs. Your role will be to micro-architect , design and deliver data fabric IP RTL components , while managing the requirements of power, performance and area , to meet next-gen fabric requirements. You will work closely with the architecture, Verification and Physical Design teams to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior architects and design engineers. The candidate will be highly detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBILITIES: Define Data Fabric/ NoC features and capabilities required to meet SoC requirements on power, performance, Area targets. Close architecture and micro-architecture requirements, drive technical specifications for data fabric and its IP blocks to meet those requirements, and provide technical direction to execution teams Lead discussions on ARM/x86 core interfacing to AMD data fabric IPs, to match SoC requirements. Lead design on one or more domains for the data fabric implementation. Work with architects and design leads to identify and assess complex technical issues/risks and develop as well as implement solutions to achieve product requirements Knowledge sharing and mentoring Work closely with Design teams for Area refinement, Timing targets , Verification Test plan reviews, Pre-Si bug resolution and Performance/Power Verification sign offs Work closely with Verification teams to ensure quality component development Support Post-Si teams for functional issues debug/resolution PREFERRED EXPERIENCE: Excellent foundation in NoC architecture and CPU/GPU coherency. Preferred expertise in ARM/other core architecture Preferred CHI protocol experience Experience analyzing NoC Fabric , CPU, or System-level Micro-Architectural features to identify performance bottlenecks within different workloads Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture and logic design Excellent communication skills. Ability to lead team technically. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR5 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "RTL Design (GPU)-Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-05-29T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718545547", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\n•GPU Design and micro-Architect who will work across functions like GPU architecture and Systems in design and micro-architecture of the next generation GPU features. \n•Work very closely with Architecture teams to come up with micro-architecture and hardware specification for features \n•Design and RTL ownership \n•Work very closely with Design Verification teams to review test plans and sign off the validation of all design features across products \n•Work closely with physical design teams to achieve the right power, performance and area metrics for the GPU block\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Lead Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-05-28", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Design-Engineer_R53756", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\n1. Proficient in Verilog coding and RTL design, data path designs,\n2. Knowledge of RTL checks ex- LINT, SDC, CDC\n3. Familiar with synthesis flow and timing constraints\n4. Experience in writing Verilog testbench and running simulations.\n5. Familiar with any of the interface Protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "DFT Solutions Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-05-28", "url": "https://careers.synopsys.com/job/bengaluru/dft-solutions-engineer/44408/95696068656", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years deep in the details of digital IC design, and you know that the difference between a chip that works and one that doesn't often comes down to decisions made during DFT planning. You are the engineer who catches those decisions early, who can look at a scan architecture and immediately see where the coverage gaps will show up three months later during silicon bring-up. You have debugged enough ATPG failures and MBIST issues to know that the best solutions start with understanding what the customer is actually trying to build, not just what they think they need.\nYou operate at the intersection of deep technical work and customer collaboration. You can spend the morning implementing a complex test access network for a multi-IP SoC and the afternoon explaining to a customer why their current flow is leaving test coverage on the table, and you are equally comfortable in both modes. You do not wait for perfect specs. You ask the right questions, prototype quickly, and iterate based on what you learn.\nAt Synopsys, you will work with customers designing some of the most complex chips in automotive, AI, and consumer electronics, and what you deliver will directly determine whether their silicon works on the first spin.\n\nWhat You'll Be Doing\nDeliver end-to-end DFT solutions for customer designs, from architecture planning and scan insertion through pattern generation, silicon bring-up, and diagnostics analysis\nImplement and validate test solutions including scan, MBIST, and IEEE 1687 architectures for complex SoCs with multiple IP blocks\nParticipate in customer design reviews to understand their flows, identify gaps, and propose specific improvements that reduce test time or increase coverage\nPrototype and validate new DFT methodologies in collaboration with Solution Architects, proving out viability before customer deployment\nProvide technical support and training to customers, including hands-on problem resolution, methodology workshops, and account-level engagement\nConduct product demonstrations, competitive benchmarking, and evaluations to help win new customers and expand adoption of Synopsys test solutions\nAnalyze silicon test data, diagnose failures, and present findings to both internal teams and customer stakeholders with clear recommendations\n\nThe Impact You Will Have\nEnable first-time silicon success for customers by delivering robust, validated DFT solutions that catch issues before tapeout\nAccelerate time-to-market for automotive and consumer electronics customers by optimizing their test flows and reducing pattern generation cycles\nExpand Synopsys' footprint in next-generation test technologies by proving out new methodologies that become standard practice across accounts\nBuild long-term customer relationships that turn one-time engagements into strategic partnerships, increasing account value and retention\nRaise the technical capability of customer teams through training and knowledge transfer, creating a multiplier effect beyond individual projects\nShape the direction of Synopsys test products by feeding real-world customer challenges and use cases back to R&D teams\nContribute to measurable improvements in test coverage, pattern count reduction, and silicon yield across diverse customer programs\n\nWhat You'll Need\nBachelor's degree with 7+ years or Master's degree with 5+ years in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field\nHands-on experience with RTL coding, DFT insertion, ATPG pattern generation, and silicon bring-up for digital ICs\nDeep knowledge of scan architectures, fault models, test access networks, and IEEE standards including 1149.1, 1500, and 1687\nProven ability to handle scan implementation and validation for large, multi-IP SoCs with complex hierarchies and multiple clock domains\nExperience with MBIST concepts, architecture planning, and integration in automotive or safety-critical design environments is a strong plus\nFamiliarity with industry-standard DFT tools and flows, exposure to Synopsys TetraMAX, DFT Compiler, or MBIST Architect is valuable\nStrong written and verbal communication skills to translate technical concepts for both engineering teams and non-technical stakeholders\n\nWho You Are\nYou can walk into a customer design review, absorb their methodology in real time, and walk out with three specific recommendations they can act on next week\nYou are comfortable working independently on complex technical problems while knowing when to pull in a Solution Architect or R&D engineer for a second opinion\nYou manage multiple customer engagements at once without dropping threads, keeping track of where each project stands and what needs to happen next\nYou prototype quickly and iterate based on feedback, treating customer pushback as useful signal rather than friction\nYou explain tradeoffs clearly, whether you are talking to a junior engineer learning DFT or a VP trying to understand why test time matters for their product schedule\nYou stay current on emerging test standards and methodologies because you are genuinely curious about where the technology is headed, not just what you need to know today\n\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\n\n#TPG", "jd_status": "stored"}, {"title": "Senior ASIC Design Engineer - XBAR IP", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-05-28", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-ASIC-Design-Engineer---XBAR-IP_JR2009959", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking passionate, highly motivated, and creative senior design engineers to be part of its Graphics team working on the design of state of the art memory subsystem components used in their industry-leading Graphics Processors. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n\nIn this position, you will be expected to make architectural trade-offs based on features, performance requirements and system limitations, come up with micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. You will work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and backend teams to accomplish your tasks.\n\nWhat you’ll be doing:\nOwn micro-architecture and RTL development of design modules.\n\nMicro-architect features to meet performance, power and area requirements.\n\nWork with HW architects to define critical features.\n\nCollaborate with verification teams to verify the correctness of implemented features.\n\nCo-operate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable.\n\nInteract with FPGA and S/W teams to prototype the design and ensure that S/W is tested.\n\nWork on post-silicon verification and debug.\n\nWhat we need to see:\nBS / MS or equivalent experience.\n\n5+ years of design experience.\n\nExperience in RTL design of complex design units for at least two or three projects.\n\nExposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).\n\nDeep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.\n\nExpertise in Verilog.\n\nWays to stand out from the crowd:\nDesign experience in memory subsystem or network interconnect IP.\n\nGood debugging and problem solving skills.\n\nScripting knowledge (Python/Perl/shell).\n\nLeadership experience in leading small 2-3 member teams.\n\nGood interpersonal skills and ability & desire to work as a part of a team.\n\nNVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.\n\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Sr Analog Physical Design Engineer | Kilby Labs", "company": "Texas Instruments", "location": "Dallas, TX, US", "date_posted": "2026-05-28", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010558", "is_hardware": true, "platform": "oracle", "jd_text": "Senior Analog Physical Design Engineer position is available within Kilby Labs, the central R&D organization at TI.  The lab is chartered to develop novel and innovative technologies and strategies for new business opportunities, drive next generation differentiated technologies for existing businesses and recruit top technical talent for TI.  This role will require strong technical expertise, attention to detail, and the ability to deliver innovative solutions.\n\nResponsibilities will include:\n\n1.   Collaborating with our design teams, sometimes from multiple geographical locations, to understand the architecture and key requirements in the creation of test/production dies, and the managing of the circuit layouts from floor planning to fabrication. \n\n2.   Project lead and team leader, providing technical guidance, planning, timelines, and resource assignments.\n\n3.   Conducting layout reviews and confirming all verifications and specifications have been met.\n\n4.   Working with our design and packaging teams to develop custom lead-frames.\n\n5.   Work closely with our ATD and PDK teams on new process and device development using Pcell Designer and other automated generation tools for various test vehicles.\n\n6.   Analysis and closure of Electro Migration, Thermal gradients, and layout parasitics.\n\n7.    Identifying ESD and latchup issues.\n\n8.   Back annotation support.\n\n9.   Mentor and guide contract layout engineers in India, review their work and provide feedback to meet quality and schedule expectations.", "jd_status": "source_unavailable"}, {"title": "STAFF Engineer -DEG Layout", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-05-27T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/41970410", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nRole and Responsibilities\nResponsible for layout design and development of critical analog, mixed-signal, custom digital block, standard cells  and full chip level.\nPerform layout verification like LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem checks,  quality check and documentation.\nResponsible for development of digital block layouts using auto placement and route tools\nResponsible for basic understanding of skill coding and automation\nResponsible for on-time delivery of block-level layouts with acceptable quality.\nDemonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/breakthroughs in multiple project environment.\nGuide developing team-members in their execution of Sub block-level layouts & review their work\nChip in to effective project-management.\nEffectively communicating with Global engineering teams to assure the success of layout project.\nResponsible for the reducing the layout effort by using AI tools\n\nQualification/Requirements\n12 to 18-year experience in analog/custom layout design in advanced CMOS process.\nExpertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.\nShould have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,\nGood understanding of Analog Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc.)\nUnderstanding layout effects on the circuit such as speed, capacitance, power and area etc.,\nAbility to understand design constraints and implement high-quality layouts.\nExcellent command and problem-solving skills in physical verification of custom layout.\nMultiple Tape out support experience will be an added advantage.\nAutomate layout execution tasks using AI\nExcellent verbal and written communication skills.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Staff DFT Engineer", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-05-27", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Staff-DFT-Engineer_R260295", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nWe are seeking a Staff DFT Engineer who can own and drive the complete DFT strategy for complex SoCs from architecture through production silicon. This role requires deep hands-on expertise, strong technical judgment, and the ability to lead and mentor junior engineers while collaborating cross-functionally with design, PD, validation, and manufacturing teams.\n\nThe ideal candidate operates independently, makes architecture-level decisions, and is accountable for test quality, coverage, and silicon readiness.\n\nResponsibilities:\n\nDFT Architecture & Planning\nOwn DFT architecture definition at chip and subsystem level\nDefine scan, compression, LBIST, MBIST, boundary scan, and test access strategies\nDrive testability requirements early in the RTL design phase\nBalance coverage, test time, power, area, and schedule tradeoffs\n\nDFT Implementation (End-to-End Ownership)\nLead and execute:\nScan insertion, stitching, and DRC closure\nATPG (stuck-at, transition, path delay)\nTest compression and pattern optimization\nOwn DFT signoff including coverage, IR drop, power, and timing impacts\nDebug and resolve DFT issues across RTL, synthesis, P&R, and gate-level stages\n\nATPG & Test Quality\nGenerate, analyze, and optimize ATPG patterns\nAchieve high fault coverage with minimal pattern count\nReview and sign off on:Fault coverage reports\nPattern volume and test time\n\nDiagnose coverage holes and drive design or methodology fixes\n\nSilicon Bring-Up & Production Support\nSupport first silicon bring-up, failure analysis, and yield ramp\nDebug scan, BIST, and tester-related failures\nCollaborate with ATE and manufacturing teams to improve yield and test robustness\nDrive ECOs for DFT-related silicon issues\n\nTechnical Leadership & Mentorship\nAct as DFT technical lead for one or more chips\nGuide and review work of junior and senior DFT engineers\nDefine best practices, checklists, and reusable DFT methodologies\nProvide technical direction and design reviews\n\nCross-Functional Collaboration\nWork closely with:RTL designers\nPhysical design (PD)\nFunctional verification\nProduct engineering and manufacturing\n\nCommunicate DFT requirements and risks clearly to stakeholders\n\nPreferred/Nice-to-Have Experience:\nExperience with high-volume production test, ATE bring-up, and test cost optimization.\nExposure to safety-critical applications (automotive, industrial) and standards (e.g., ISO 26262) from a test/reliability standpoint.\nExperience with on-chip debug, trace, and design-for-debug features.\nScripting skills in Python/Tcl/Perl for DFT automation, log analysis, and flow integration.\nPrior experience mentoring or leading small DFT teams or task forces.\n\nQualifications and Experience:\nProven experience in leading DFT teams through end-to-end SoC execution, from architecture to silicon bring-up.\nDemonstrated expertise in developing DFT architecture from scratch for complex SoC designs.\nStrong team management and leadership experience with a track record of mentoring and growing engineering talent.\nBachelor's or Master’s degree in Electrical/Electronics Engineering or a closely related field.\n7+ years of hands-on experience in DFT methodologies and industry-standard test techniques.\nDeep knowledge and hands-on experience with:\nLogic BIST (LBIST)\nAutomatic Test Pattern Generation (ATPG)\nDFT Rule Checks (DFT DRC)\nScan chain compression and stitching\nLow-power DFT techniques and constraints\nMemory BIST (MBIST) including repair mechanisms\nBoundary Scan (IEEE 1149.1)\nAnalog DFT strategies\nJTAG architecture and TAP integration\nDFT-specific STA constraints\nProficient in using industry-standard DFT EDA tools, including cadence, Siemens.\nStrong scripting and automation skills using Perl, Tcl, and/or Python.\nSolid understanding of digital design fundamentals, including RTL design, Lint/CDC, low power checks, and the full ASIC design flow.\nExcellent problem-solving skills, with the ability to troubleshoot and resolve complex DFT issues efficiently.\nStrong communication and interpersonal skills, capable of working effectively in cross-functional and team-oriented environments.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Staff Design Verification Engineer", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-05-27", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Staff-Design-Verification-Engineer_R260296", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nStaff Design Verification Engineer\n\nAbout the Role\nAs a Staff Design Verification Engineer at Analog Devices, you will provide technical leadership in developing verification strategies for our most complex analog and mixed-signal designs. You'll architect sophisticated verification environments, mentor junior engineers, and collaborate across organizational boundaries to ensure product quality and reliability.\nWorking with limited direction, you'll apply your deep technical expertise to solve critical verification challenges while representing ADI in interactions with key customers and industry partners. This senior position involves significant influence on verification methodology adoption and technical decisions that impact crucial organizational objectives.\n\nKey Responsibilities\nStrategic Leadership: Architect and lead verification strategy for complex digital and mixed-signal designs, acting as a key contributor in critical verification environments\nVerification Architecture: Design and implement sophisticated UVM-based verification environments that ensure comprehensive test coverage and design quality\nTechnical Mentorship: Guide and develop junior engineers, serving as a resource for colleagues with less experience while modeling professional behaviors\nCross-Functional Direction: Coordinate work across organizational lines, collaborating with design teams on verification requirements and sign-off criteria\nProblem Resolution: Lead complex debugging efforts across RTL and gate-level simulations with minimal direction, developing resolutions that require in-depth analysis\nCoverage Closure: Drive functional and code coverage closure using advanced verification methodologies to ensure design accuracy\nPost-Silicon Support: Lead post-silicon validation activities, contributing expertise to address critical issues\nCustomer Representation: Serve as principal customer contact on projects, representing ADI's technical excellence and customer commitment\n\nMust Have Skills\nSystemVerilog and UVM Expertise: Expert-level knowledge of SystemVerilog and Universal Verification Methodology for architecting advanced verification environments for complex designs\nTest Planning and Strategy: Demonstrated ability to develop comprehensive verification plans that drive coverage-driven methodologies and verification closure\nMixed-Signal Verification: Deep understanding of mixed-signal design principles and verification methodologies, with experience implementing sophisticated verification approaches\nDebugging Mastery: Advanced debugging skills across multiple design abstractions, with proven ability to resolve complex verification issues with minimal direction\nEDA Tool Proficiency: Extensive experience with electronic design automation tools (Cadence/Synopsys) and formal verification techniques\nScripting and Automation: Advanced proficiency in Python, Perl, TCL, or Shell scripting for creating sophisticated verification automation frameworks\nTechnical Leadership: Demonstrated ability to influence verification direction, mentor junior engineers, and drive methodology adoption across teams\n\nPreferred Education and Experience\nMS/PhD in Electrical Engineering, Computer Engineering, or related field\n7-10+ years of relevant digital design verification experience, with particular emphasis on mixed-signal verification\n\nWhy You'll Love Working Here\nAt Analog Devices, you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on professional growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world.\nYour expertise will shape the future of technology, and you'll be supported by a culture that values continuous advancement and professional growth. Join us and help create the technologies that bridge the physical and digital worlds, making a tangible difference in how people live, work, and connect.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Staff Design Verification Engineer", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-05-27", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Staff-Design-Verification-Engineer_R260297", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nStaff Design Verification Engineer\n\nAbout the Role\nAs a Staff Design Verification Engineer at Analog Devices, you will provide technical leadership in developing verification strategies for our most complex analog and mixed-signal designs. You'll architect sophisticated verification environments, mentor junior engineers, and collaborate across organizational boundaries to ensure product quality and reliability.\nWorking with limited direction, you'll apply your deep technical expertise to solve critical verification challenges while representing ADI in interactions with key customers and industry partners. This senior position involves significant influence on verification methodology adoption and technical decisions that impact crucial organizational objectives.\n\nKey Responsibilities\nStrategic Leadership: Architect and lead verification strategy for complex digital and mixed-signal designs, acting as a key contributor in critical verification environments\nVerification Architecture: Design and implement sophisticated UVM-based verification environments that ensure comprehensive test coverage and design quality\nTechnical Mentorship: Guide and develop junior engineers, serving as a resource for colleagues with less experience while modeling professional behaviors\nCross-Functional Direction: Coordinate work across organizational lines, collaborating with design teams on verification requirements and sign-off criteria\nProblem Resolution: Lead complex debugging efforts across RTL and gate-level simulations with minimal direction, developing resolutions that require in-depth analysis\nCoverage Closure: Drive functional and code coverage closure using advanced verification methodologies to ensure design accuracy\nPost-Silicon Support: Lead post-silicon validation activities, contributing expertise to address critical issues\nCustomer Representation: Serve as principal customer contact on projects, representing ADI's technical excellence and customer commitment\n\nMust Have Skills\nSystemVerilog and UVM Expertise: Expert-level knowledge of SystemVerilog and Universal Verification Methodology for architecting advanced verification environments for complex designs\nTest Planning and Strategy: Demonstrated ability to develop comprehensive verification plans that drive coverage-driven methodologies and verification closure\nMixed-Signal Verification: Deep understanding of mixed-signal design principles and verification methodologies, with experience implementing sophisticated verification approaches\nDebugging Mastery: Advanced debugging skills across multiple design abstractions, with proven ability to resolve complex verification issues with minimal direction\nEDA Tool Proficiency: Extensive experience with electronic design automation tools (Cadence/Synopsys) and formal verification techniques\nScripting and Automation: Advanced proficiency in Python, Perl, TCL, or Shell scripting for creating sophisticated verification automation frameworks\nTechnical Leadership: Demonstrated ability to influence verification direction, mentor junior engineers, and drive methodology adoption across teams\n\nPreferred Education and Experience\nMS/PhD in Electrical Engineering, Computer Engineering, or related field\n7-10+ years of relevant digital design verification experience, with particular emphasis on mixed-signal verification\n\nWhy You'll Love Working Here\nAt Analog Devices, you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on professional growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world.\nYour expertise will shape the future of technology, and you'll be supported by a culture that values continuous advancement and professional growth. Join us and help create the technologies that bridge the physical and digital worlds, making a tangible difference in how people live, work, and connect.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Staff Design Verification Engineer", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-05-27", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Staff-Design-Verification-Engineer_R260299", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nStaff Design Verification Engineer\n\nAbout the Role\nAs a Staff Design Verification Engineer at Analog Devices, you will provide technical leadership in developing verification strategies for our most complex analog and mixed-signal designs. You'll architect sophisticated verification environments, mentor junior engineers, and collaborate across organizational boundaries to ensure product quality and reliability.\nWorking with limited direction, you'll apply your deep technical expertise to solve critical verification challenges while representing ADI in interactions with key customers and industry partners. This senior position involves significant influence on verification methodology adoption and technical decisions that impact crucial organizational objectives.\n\nKey Responsibilities\nStrategic Leadership: Architect and lead verification strategy for complex digital and mixed-signal designs, acting as a key contributor in critical verification environments\nVerification Architecture: Design and implement sophisticated UVM-based verification environments that ensure comprehensive test coverage and design quality\nTechnical Mentorship: Guide and develop junior engineers, serving as a resource for colleagues with less experience while modeling professional behaviors\nCross-Functional Direction: Coordinate work across organizational lines, collaborating with design teams on verification requirements and sign-off criteria\nProblem Resolution: Lead complex debugging efforts across RTL and gate-level simulations with minimal direction, developing resolutions that require in-depth analysis\nCoverage Closure: Drive functional and code coverage closure using advanced verification methodologies to ensure design accuracy\nPost-Silicon Support: Lead post-silicon validation activities, contributing expertise to address critical issues\nCustomer Representation: Serve as principal customer contact on projects, representing ADI's technical excellence and customer commitment\n\nMust Have Skills\nSystemVerilog and UVM Expertise: Expert-level knowledge of SystemVerilog and Universal Verification Methodology for architecting advanced verification environments for complex designs\nTest Planning and Strategy: Demonstrated ability to develop comprehensive verification plans that drive coverage-driven methodologies and verification closure\nMixed-Signal Verification: Deep understanding of mixed-signal design principles and verification methodologies, with experience implementing sophisticated verification approaches\nDebugging Mastery: Advanced debugging skills across multiple design abstractions, with proven ability to resolve complex verification issues with minimal direction\nEDA Tool Proficiency: Extensive experience with electronic design automation tools (Cadence/Synopsys) and formal verification techniques\nScripting and Automation: Advanced proficiency in Python, Perl, TCL, or Shell scripting for creating sophisticated verification automation frameworks\nTechnical Leadership: Demonstrated ability to influence verification direction, mentor junior engineers, and drive methodology adoption across teams\n\nPreferred Education and Experience\nMS/PhD in Electrical Engineering, Computer Engineering, or related field\n7-10+ years of relevant digital design verification experience, with particular emphasis on mixed-signal verification\n\nWhy You'll Love Working Here\nAt Analog Devices, you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on professional growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world.\nYour expertise will shape the future of technology, and you'll be supported by a culture that values continuous advancement and professional growth. Join us and help create the technologies that bridge the physical and digital worlds, making a tangible difference in how people live, work, and connect.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Staff Engineer – SoC Design Verification", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-05-27", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Staff-Engineer---SoC-Design-Verification_R260901", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nStaff Design Verification Engineer\n\nAbout the Role\nAs a Staff Design Verification Engineer at Analog Devices, you will provide technical leadership in developing verification strategies for our most complex analog and mixed-signal designs. You'll architect sophisticated verification environments, mentor junior engineers, and collaborate across organizational boundaries to ensure product quality and reliability.\nWorking with limited direction, you'll apply your deep technical expertise to solve critical verification challenges while representing ADI in interactions with key customers and industry partners. This senior position involves significant influence on verification methodology adoption and technical decisions that impact crucial organizational objectives.\n\nKey Responsibilities\nStrategic Leadership: Architect and lead verification strategy for complex digital and mixed-signal designs, acting as a key contributor in critical verification environments\nVerification Architecture: Design and implement sophisticated UVM-based verification environments that ensure comprehensive test coverage and design quality\nTechnical Mentorship: Guide and develop junior engineers, serving as a resource for colleagues with less experience while modeling professional behaviors\nCross-Functional Direction: Coordinate work across organizational lines, collaborating with design teams on verification requirements and sign-off criteria\nProblem Resolution: Lead complex debugging efforts across RTL and gate-level simulations with minimal direction, developing resolutions that require in-depth analysis\nCoverage Closure: Drive functional and code coverage closure using advanced verification methodologies to ensure design accuracy\nPost-Silicon Support: Lead post-silicon validation activities, contributing expertise to address critical issues\nCustomer Representation: Serve as principal customer contact on projects, representing ADI's technical excellence and customer commitment\n\nMust Have Skills\nSystemVerilog and UVM Expertise: Expert-level knowledge of SystemVerilog and Universal Verification Methodology for architecting advanced verification environments for complex designs\nTest Planning and Strategy: Demonstrated ability to develop comprehensive verification plans that drive coverage-driven methodologies and verification closure\nMixed-Signal Verification: Deep understanding of mixed-signal design principles and verification methodologies, with experience implementing sophisticated verification approaches\nDebugging Mastery: Advanced debugging skills across multiple design abstractions, with proven ability to resolve complex verification issues with minimal direction\nEDA Tool Proficiency: Extensive experience with electronic design automation tools (Cadence/Synopsys) and formal verification techniques\nScripting and Automation: Advanced proficiency in Python, Perl, TCL, or Shell scripting for creating sophisticated verification automation frameworks\nTechnical Leadership: Demonstrated ability to influence verification direction, mentor junior engineers, and drive methodology adoption across teams\nExposure to SoC Verifications including Usecases and Excellent Debug Skills\nAbility to work with team from diverse domains and achieve the DV quality\n\nPreferred Education and Experience\nMS/PhD in Electrical Engineering, Computer Engineering, or related field\n7-10+ years of relevant digital design verification experience, with particular emphasis on mixed-signal verification\n\nWhy You'll Love Working Here\nAt Analog Devices, you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on professional growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world.\nYour expertise will shape the future of technology, and you'll be supported by a culture that values continuous advancement and professional growth. Join us and help create the technologies that bridge the physical and digital worlds, making a tangible difference in how people live, work, and connect.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Staff Physical Design Engineer", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-05-27", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Staff-Physical-Design-Engineer_R261517", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nRole Overview\nThe Staff Physical Design Engineer is role which combines deep hands-on implementation expertise with technical leadership. This role owns complex block- and/or top-level physical design for advanced-node SoCs and leads a small group of engineers to achieve high-quality, on-time delivery.\n\nKey Responsibilities\nTechnical Ownership\n\nOwn end-to-end physical implementation (floorplanning, power planning, placement, CTS, routing, ECO) for complex blocks or subsystems across advanced technology nodes (e.g., 22nm, 16nm, 7nm, 5nm, 4nm).\nDrive timing closure, congestion resolution, IR/EM, signal integrity, and physical verification (DRC/LVS/antenna) to meet PPA and quality targets.\nDefine and refine hierarchical PNR strategies, IO ring/PG structures, and integration guidelines for large SoCs.\nPerform in-depth analysis and debug of tool issues, timing failures, and physical design anomalies; propose robust, scalable solutions.\n\nMethodology and Automation\n\nDevelop, maintain, and enhance physical design methodologies, scripts, and flows (e.g., for PDN, PG, clock structure, exception handling, signoff automation).\nProactively identify opportunities for flow improvements and standardization to reduce turnaround time and error rates.\nEvaluate EDA tool features and drive best practices in collaboration with CAD/enablement teams.\n\nTechnical Leadership & Team Enablement\n\nProvide technical direction to a small group of physical design engineers, including task breakdown, priority setting, and quality expectations.\nMentor junior engineers and NCGs in PNR, STA and debug practices to build a strong second tier of technical capability.\nReview floorplans, constraints, and implementation choices from team members, giving clear, actionable feedback.\nAct as a go-to technical reference within the PD team.\n\nCross-Functional Collaboration\n\nWork closely with RTL design, STA, DFT, CAD, and packaging teams to converge on implementation-friendly architectures and constraints.\nCommunicate risks, options, and trade-offs clearly to project leads and managers, and help shape mitigation plans.\nParticipate in design reviews and signoff reviews, representing physical design status, risks, and recommendations.\n\nRequired Qualifications\n\nStrong experience in physical design implementation for complex digital SoCs, typically 8–12+ years in physical design or equivalent level of mastery.\nProven hands-on expertise with industry-standard PNR and signoff tools (e.g., Cadence Innovus, Synopsys ICC2, Tempus/PrimeTime, RedHawk, Voltus, etc.).\nDemonstrated success in closing challenging blocks/subsystems on advanced nodes (timing-, IR-, and congestion-critical designs).\nSolid understanding of:\nFloorplanning and partitioning strategies\nPower grid and PDN methodology (including IR/EM mitigation)\nAdvanced clock tree/clock mesh design and constraints\nSTA constraints (modes/corners, exceptions, derates)\nPhysical verification and reliability checks\n\nLeadership Expectations\n\nStrong problem-solving and debugging mindset, with a bias toward scalable, automated solutions.\nClear, concise communication skills—able to explain complex technical issues and options to different audiences.\nDemonstrated commitment to mentoring, knowledge sharing, and raising the capability of the broader team.\nComfortable operating in a dynamic environment with shifting priorities while maintaining quality and accountability.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Staff Physical Verification Engineer", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-05-27", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Staff-Physical-Verification-Engineer_R261683", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nRole  \nWe are seeking a Staff Physical Verification Engineer to own full-chip signoff for advanced SoC/ASIC designs, with end-to-end responsibility from block-level checks to final tape-out. You will lead methodologies and execution for DRC, LVS, PERC and related reliability checks, working closely with Place-n-route, analog/mixed-signal, timing analysis and CAD teams to ensure first-time-right silicon.\nKey Responsibilities  \n- Own full-chip and block-level physical verification signoff, including DRC, LVS, ERC, PERC and antenna/ESD checks for multiple complex SoCs.\n- Drive tape-out readiness: manage PV schedules, track violations, converge to zero/signoff-acceptable errors, and deliver clean GDS.\n- Develop, maintain, and optimize PV flows and scripts (e.g., Calibre, ICV) for performance, robustness, and ease of use.\n- Define and enhance PERC and reliability rule checks (ESD, EOS, EM-related constraints, point-to-point resistance, high current-density paths) in collaboration with reliability, I/O, and analog teams.\n- Own the floorplanning and power grid planning to minimize PV iterations and avoid late-stage violations.\n- Own debugging of complex DRC/LVS/PERC violations, including corner-case connectivity, device recognition, FinFET-specific rules - restrictive spacing, coloring, cut-mask and EUV/multi-patterning constraints\n- Partner with CAD teams to validate and qualify new technology nodes, rule decks, and fill/DFM flows before project adoption.\n- Mentor and guide junior and senior engineers on PV best practices, root-cause analysis methodologies, and signoff criteria.\n- Act as primary technical interface to foundry and EDA vendors for PV and reliability issues, waivers, and methodology improvements.\n\nRequired Qualifications  \n- Bachelor’s or Master’s degree in Electrical/Electronics Engineering or related field.\n- Typically 8-12 years of experience in physical verification for complex ASIC/SoC designs, including several successful production tape-outs as signoff owner.\n- Proven experience owning DRC/LVS/PERC signoff for at least one 5 nm (or sub-7 nm) production tape-out in a FinFET process\n- Deep hands-on expertise with industry-standard PV tools (e.g., Siemens Calibre, Synopsys IC Validator) for DRC, LVS, ERC, PERC and ANT/ESD checks.\n- Hands-on experience with Cadence Virtuoso-PV tool integration( Virtuoso layout to Caliber/ICV for DRC/LVS/PERC)\n- Strong experience with advanced process nodes (e.g., 5 nm and below) and associated design-rule and reliability challenges.\n- Proven track record in driving full-chip PV signoff in digital-on-top, mixed-signal, or multi-voltage SoCs, including hierarchical flows and IP integration.\n- Solid scripting skills in at least one of: Python, Perl, Tcl, or Unix shell, for automation and flow development.\n- Experience with PERC-based reliability flows for ESD, EOS, LUP and current-density-based checks, including setup, customization, and signoff criteria definition.\n- Familiarity with DFM/DFY checks, density/fill strategies, and pattern-matching-driven rule decks\n- Strong understanding of physical design (place & route, timing closure, power integrity) and its interaction with PV signoff.\n- Excellent problem-solving, debug, and communication skills, with demonstrated ability to lead cross-functional technical closure.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Staff Engineer, Digital Design Engineering", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-05-27", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Staff-Engineer--Digital-Design-Engineering_R261333-1", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nEssential Duties and Responsibilities:\nOwnership of developing the specification, micro architecture, and RTL design of modules as per requirements.\nContribute/influence Chip Architecture.\nProvide Technical and managerial  Leadership to Digital  Design Engineers in the Design of IPs and functional blocks.\nGuide Junior design engineers working on the development of timing constraints,  lint checks, synthesis, and Static-timing-analysis.\nCo-work with the verification and PD team for coverage and timing closure respectively.\nLint check and Clock domain crossing analysis\nSanity Synthesis runs.\nSupport post silicon debug activities\nHire , mentor, and guide design engineers technically and managerially.\n \nQualifications:\nMinimum BTech/BE degree in Electrical/Electronics.\n10+ years of solid  digital logic design experience in hands-on and/or technical leadership..\nStrong hands-on RTL coding experience and debugging skills.\nExperience with Lint, CDC, formal equivalence, ECO flows and scripting.\nKnowledge of Audio and/or DSP fundamentals will be an added advantage.\nGood interpersonal, teamwork and communication skills to logically drive the  discussions effectively with teams spread geographically.\nExperience in mentoring junior engineers is desirable\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Senior Engineer-I Design Implementation", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-05-27", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Senior-Engineer-I-Design-Implementation_R1607-26", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nMicrochip Technology Inc. is looking for an experienced engineer to work in a team that is responsible for doing Design Implementation (Synthesis/STA/Timing closure/Formal Equivalence) of 32-bit Microcontroller based products. The role will include optimizing PPA (Power/Performance/Area) metrics during synthesis and performing static timing analysis, design verification/signoff using an industry leading design implementation flow.\n\nJob Requirements:\nKey Responsibilities:\n* Evaluate new tools/features, develop and maintain flows.\n* Execute Synthesis, Formal equivalence, Low Power Checks and Static Timing Analysis using the tools and flows for Microchip’s 32-bit microcontroller product lines.\n* Drive collaterals generation and management, SoC timing budgeting, constraint analysis, optimization, and sign-off timing/power closure.\n* Work alongside architecture, design, verification and physical design teams to support constraint and UPF development, timing debug/fixing and support gate level simulations.\n* Participate in SoC development planning and scheduling.\n* Continuously improve RTL-to-Netlist tool flows and methodologies.\n* Interact with tool vendors and debug tool related or IP related issues\n\nRequirements/Qualifications:\n\n* BSEE minimum, MSEE preferred\n* Minimum 3 to 4 years of relevant experience\n* Good exposure to RTL2GDS flow for digital and mixed signal designs. Hands-on experience with STA, Synthesis, UPF and Functional equivalence. The ability to implement power constraints using UPF/CPF constructs is a plus.\n* Design flow development experience using scripting (TCL/Perl/Python) languages.\n* Good documentation and presentation skills.\n* Demonstrated ability to interact and collaborate well with other team members in a cross functional and cross site team environment.\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Senior Packaging Technical Engineer - Hardware", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-05-27", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Packaging-Technical-Engineer---Hardware_JR2012884", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nWe are now looking for a Senior Packaging Technical Engineer. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing.\n\nWhat you’ll be doing:\nYour responsibilities include defining the chip pad ring, substrate interconnect scheme, and lead the package layout design process.\n\nWe collaborate with large teams consisting of Circuit, Signal Integrity, RTL, Place and Route, substrate layout and system design Engineers and Managers.\n\nWork to define a chip floor plan, pad ring, substrate, and ball out implementing a robust world-class electrical package!\n\nCommunicate effectively with various teams throughout the company\n\nWhat we need to see:\nBSEE or equivalent experience.\n\nMinimum of 8+ years in board/system design. Experience with package design is preferred.\n\nGood understanding of transmission line theory, power delivery and signal integrity is desired.\n\nStrong programming and scripting skills in Perl, Python, Tcl desired, Cadence Skill and EXCEL familiarity are helpful.\n\nEnthusiastic and able to work with a minimum of supervision.\n\nYou seek to solve complex technical problems.\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We welcome you join our team with some of the most hard-working people in the world working together to promote rapid growth. Are you passionate about becoming a part of a best-in-class team supporting the latest in GPU and AI technology? If so, we want to hear from you.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "System IP RTL Design Lead", "company": "Tenstorrent", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-05-26T22:57:59-04:00", "url": "https://job-boards.greenhouse.io/tenstorrent/jobs/5146176007", "is_hardware": true, "platform": "greenhouse", "jd_text": "Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.\n\nWe are seeking an experienced and motivated System IP RTL Design Lead to drive the definition and implementation of complex datacenter class IP for our next-generation semiconductor products. The ideal candidate possesses a deep understanding of System IP and SoC architecture, IP integration challenges, and is adept at leading a design team to deliver high-quality, scalable IP solutions. This role requires strong hands-on technical leadership, excellent communication skills, and a proven track record in the successful delivery of silicon IP.\n\nThis role is hybrid, based out of Bangalore, India.\n\nWe welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.\n\n \n\nWho You Are\n\nA seasoned IP / SoC design leader with 20+ yrs of strong expertise in complex SoC architectures, high-speed protocols, and large-scale IP integration.\n\nSkilled in RTL design and debug (Verilog/SystemVerilog) with hands-on experience using industry-standard tools for simulation, synthesis, lint, CDC, and power analysis on high-frequency designs.\n\nExperienced in driving microarchitecture decisions, authoring design specifications, and performing complex PPA trade-off optimizations.\n\nA proactive problem solver capable of debugging complex logic across hierarchical levels within pre-silicon simulation, emulation, and post-silicon bring-up environments.\n\nA collaborative technical leader who can work seamlessly across architecture, design, verification, physical design, software, firmware and external IP vendors.\n\nStrong communication skills and the ability to mentor and guide engineering teams.\n\n \n\nWhat We Need\n\nLead the technical definition, selection, and integration of internally and third party developed IPs including MMUs, Interrupt controllers, Interconnects, Memory controllers, and peripherals within advanced SoCs.\n\nDefine system-level requirements, IP specifications, interfaces, and integration methodologies to achieve performance, power, and area (PPA) goals.\n\nDrive IP design through sign-off activities while ensuring compliance with functional, security, and quality requirements.\n\nBring deep expertise in protocols and interfaces such as AXI/AHB/APB, PCIe, DDR, and USB, along with scripting and verification methodologies including Python, Tcl, UVM, and formal verification.\n\n \n\nWhat You Will Learn\n\nWork on cutting-edge CPU and AI compute architectures integrating advanced compute, memory, and interconnect technologies.\n\nGain exposure to large-scale system integration challenges spanning RTL, verification, physical design, and silicon bring-up.\n\nInfluence key architectural and microarchitectural decisions that directly impact next-generation product performance and scalability.\n\nCollaborate with highly experienced global engineering teams across multiple domains and disciplines.\n\nContribute to the evolution of scalable IP integration methodologies, verification flows, and best practices for future SoC programs.\n\n \n\nTenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.\nThis offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.  Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).   These requirements apply to persons located in the U.S. and all countries outside the U.S.  As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.  If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.", "jd_status": "stored"}, {"title": "Staff Product Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-05-26T16:26:54.431000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000128544120-staff-product-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "This role will work in our Device and Product Group supporting New Product Introduction (NPI) of our state-of-the-art GaN semiconductor devices as well as other engineering projects. This experienced semiconductor product engineer will work in a cross functional role that involves the ownership of new products from concept to qualification. The role requires coordinating activities across multiple departments (R&D, Design, Epitaxial, Fabrication, Package Assembly, Test and Reliability, etc.).\nDescription\nLead the NPI process and coordinate the power device products definition, design, fabrication, testing and qualification, taking them from tape-out to production release.\nWork closely with the marketing, sales, engineering and manufacturing teams to develop NPI plans.\nNegotiate schedules to align with resources and customer requirements.\nTrack and communicates status, key results, risks, and problems to all stakeholders to ensure alignment of priorities. Schedule and run design review activities.\nMonitor and analyzes testing and qualification results to write engineering reports.\nDevelop screening methods during NPI phase for qualification.\nDrive root cause investigations of performance and qualification issues.\nOwn and support other engineering projects\n\n5-7+ years in semiconductor manufacturing, yield engineering and  power electronics is a plus.\nBS in an engineering or science discipline and/or MS in engineering or science.\nExperience with APQP design review processes, FMEA, NPI and SPC.\nUnderstanding of process and product development, wafer level processing, assembly and test methods.\nExceptional time management skills.\nAbility to take initiative and work effectively in teams.\nExcellent verbal and written communication skills.\nProficiency with MS Office.\nExperience with discrete device testing and semiconductor packaging will be a plus.\nExperience with engineering databases, automation and statistical analysis using software such as JMP.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.", "jd_status": "stored"}, {"title": "Validation Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-26", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010624", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\nAbout the Team\nThis requirement is open for Analog Signal Chain (ASC) -Motor Drives (MD) group at Texas Instruments India. Our charter is to develop drivers for Brushed, Stepper motors and solenoid driver for Automotive and Industrial systems.  These motor drives touch our everyday lives, and the innovation and reliability we bring to these products truly make the world a safer place! We are looking for highly motivated and passionate Validation engineer with background in power electronics and microcontrollers to join this product line. Your expertise will be instrumental in driving the growth of our business.\n\nJob Responsibilities:\n\nJoin our innovative team as a Validation Engineer and drive technical excellence in motor driver and motor control applications. You will be responsible for owning and driving silicon validation for assigned project(s). \n\nWork will involve, \n\nWork with the product definition and design team, before silicon availability to thoroughly understand validation requirements including device level, system level and compliance specifications.\n\nDefine and own validation plan and schedule with coverage of all the use-cases and corner conditions.\n\nDevelopment of test methods and efficient, reusable automation for the setups.\n\nWork with design team to perform Pre Si verification  with the help of FPGA\n\nDrive the development of scalable validation boards meeting signal and power integrity requirements. \n\nParametric data collection across PVT, using automation to execute a comprehensive validation plan.\n\nDrive reviews with extended team for validation boards, test results and debug.\n\nWork with cross functional teams (Systems, Apps, TE, PE, Quality) to support customer issues debug, root cause analysis and solution identification.\n\nOn anomalous behavior observed, perform debug through design of experiments to narrow down the source of the error including but not limited to – error in stimulus, error in hardware, isolating probable “on device” circuit blocks etc. responsible for the behavior.\n\nQualifications\nMinimum requirements:\nMinimum education is bachelor's degree in electrical engineering\nMinimum 2 years of experience.\nPreferred qualifications:\nMaster’s degree in power electronics or work experience in high power product lines is a plus\nGood understanding of semiconductor device fundamentals\nGood analog, power and mixed signal circuit fundamentals\nGood knowledge on test and measurement equipment’s and associated instrumentation\nGood knowledge of software tools like LabView, TestStand, Python scripting, Spotfire etc. \nKnowledge of Microcontrollers and FPGA\nHands-on experience in designing PCBs\nDrive and own complex design and system debugs\nGood oral and written communication skills. \nGood team player, ability to work with systems, design, test and applications engineering. \nAbility to independently carry on device debug by application of basic electrical engineering skills.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Physical Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-26", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010925", "is_hardware": true, "platform": "oracle", "jd_text": "About TI\n\nTexas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world’s brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We’re committed to building a better future – from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. Put your talent to work with us – change the world, love your job! \n\n \n\nAbout the Role:\n\nAre you looking for a career at one of the leading semiconductor companies in the world Texas Instruments (TI) is looking for a Physical design engineer to join the team of enthusiastic engineers who develops highly complex mixed signal devices for audio applications with industry leading performance.\n\nWe are seeking a skilled Digital Physical Design Engineer of 2-5 Year of industry experience  with good RTL design hands-on and understanding. The candidate will be responsible for taking RTL through synthesis, floorplanning, place-and-route, timing closure, power optimization, and physical verification to tape-out. This role demands hands-on expertise in EDA tools, physical design flows, and deep knowledge of digital VLSI concepts.\n\n \n\nKey Responsibilities:\n\nExecute RTL-to-GDSII physical design flow for complex SoC/ASIC blocks.\n\nPerform logic synthesis, floor-planning, placement, clock tree synthesis (CTS), and routing.\n\nDevelop/support/update design constraints.\n\nDrive timing closure across multiple corners and modes using static timing analysis (STA).\n\nGood understanding of digital timing analysis\n\nOptimize for area, power, and performance (PPA) at block and chip level.\n\nConduct physical verification: DRC, LVS, Antenna checks, IR-drop, and EM analysis.\n\nDevelop/support/update constraints.\n\nCollaborate with RTL design, verification, and architecture teams to resolve design and implementation issues.\n\nProvide EDA flow automation support (scripting in TCL/Perl/Python).\n\nContribute to design reviews, documentation, and sign-off processes for successful tape-out.\n\nHighly prefer if additionally able to handle RTL coding, Digital QC(RDC/CDC/Lint). Contribute to digital design reviews and Arch reviews.\n\nQualifications\nRequired Skills & Qualifications:\n\nB.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI, or related field.\n\n2-5 years of hands-on experience in physical design for ASIC/SoC.\n\nStrong knowledge of CMOS, VLSI design fundamentals, and digital circuit concepts.\n\nProficiency in EDA tools such Cadence (Innovus, Tempus,voltus ), or equivalent.\n\nExperience in signoff checks: DRC, LVS, IR drop, EM, noise analysis.\n\nStrong scripting skills (Tcl, Perl, or Python) for flow automation.\n\nExcellent problem-solving, debugging, and analytical skills.\n\nExpertise in timing analysis, floorplanning, placement, CTS, routing, and optimization techniques.\n\nHands-on of cadence simulation tools.\n\nKnowledge of audio signal chain, I2C, ASI/TDM, memory architecture and FPGA is preferred.\n\nExcellent debugging and problem-solving skill.\n\nAdditional preference:\n\nDigital design fundamentals and basic electrical/electronic engineering concepts.\n\nHands-on experience in RTL design coding along with understating of QC (Lint/CDC/RDC) is highly preferred and recommended. \n\nSoft Skills:\n\nStrong communication, presentation and collaboration skills.\n\nAbility to work in a fast-paced, deadline-driven environment.\n\nSelf-motivated and detail-oriented with a commitment to quality.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Principal Engineer, Physical Design", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-05-26", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Principal-Engineer--Physical-Design_R262828", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nKey Responsibilities\nLead  end-to-end RTL-to-GDSII execution  for a given SoC program, driving synthesis, floorplanning, placement, CTS, routing, and signoff to achieve predictable tapeouts.\n Owned timing, power, and physical signoff strategy, including STA, SI, IR/EM analysis, ensuring first-pass silicon success and high design reliability.\n Established and enforced DRC/LVS closure methodologies, led physical verification, and streamlined ECO flows to meet aggressive tapeout schedules.\n Partnered with RTL, DFT, packaging, and system teams to align design, testability, and manufacturability goals across the product lifecycle.\n Defined and deployed automated design methodologies using TCL, Python, and Perl; collaborated with CAD teams to improve flow efficiency and scalability.\n Championed low-power design strategies (UPF/CPF), enabling power-efficient architectures aligned with product requirements.\n\nPosition Requirements\nEducation: B.Tech/M.Tech (or higher) in Electrical/Electronics Engineering or related field.\n Experience: 12+ years in physical design with a proven track record of successful tapeouts of complex, high-performance SoCs across advanced nodes (28nm, 22nm, 16nm, 10nm, 5nm and below).\nTechnical Expertise: Deep expertise in full-chip physical design, including floorplanning, power planning, placement & routing, clock architecture/CTS, extraction, and full signoff methodologies.\nAutomation & CAD Collaboration: Proficiency in TCL, Python, or similar scripting, with a track record of driving automation and partnering with CAD teams for flow enhancements.\nCross-functional Influence: Strong collaboration with RTL, DFT, packaging, product, and system teams to align on design, test, and manufacturing goals.\n Communication & Stakeholder Management: Excellent communication skills with the ability to operate effectively in global, cross-functional environments.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Principal STA Engineer", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-05-26", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Principal-STA-Engineer_R262827", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nJob Description: We are looking for experienced STA engineer to drive the timing convergence of the high performance SoCs. Responsibilities include\n\nSTA setup, convergence, reviews and sign-off for Multi-Mode and Multi-corner Multi voltage domain designs. Timing analysis, and timing closure at Partition/Sub-system/FC level.\nDriving Convergence by  influencing APR, Design teams  stakeholders\nFamiliar with Constraint development and clean up.\nGood understanding of different CTS strategies and providing the feedback to Implementation Team.\nGood at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Prime Time based ECO flows.\nWork on Automation scripts with in STA tools for Methodology development.\nExcellent debugging skills in implementation issues and ability to come up with creative solutions.\nEvaluate multiple timing methodologies/tools on different designs and technology nodes.\nFamiliar with digital design Implementation RTL to GDSII : Synopsys/Cadence tools.\nFamiliar with LVF/POCV variation formats and understanding of deep sub-micron topics especially 28nm and below technology nodes.\nHandson experience on timing closure  industry standard  high speed interfaces like DDR, PCIE, HBM, D2D\n\nQualification :\n12+  Years of relevant Experience After a Bachelor or Master of Engineering degree in Electrical/ Electronic/VLSI Engineering or related field.\nMust have led at least 2 SOCs in capacity of SOC Sign-off lead especially. Solid Expertise in Primetime or Similar timing tools\ngood understanding of overall ASIC Physical Design/DFT, Tools and implication on Timing Convergence\nMust have in-depth understanding of relevant areas of Library / Memory / Other collaterals and dependencies on STA\nMust understand Ultra Submicron issues, Variation aware/Aging Aware Design Sign-off Must understand CTS/Other clock Distribution methodologies well.\nTeamwork / flexibility / ability to thrive in a dynamic environment are very important\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Staff Engineer Physical Design Flow Expert / PD Methodology & Automation", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-05-26", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Staff-Engineer-Physical-Design-Flow-Expert---PD-Methodology---Automation_R262830", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nWe are seeking an experienced Physical Design Flow Expert to enhance and streamline Physical Design methodologies, automation infrastructure, and execution flows across complex SoC programs. This role is focused on improving flow usability, execution efficiency, and automation enablement in close collaboration with CAD, Physical Design, STA teams and methodology teams.\n\nKey Responsibilities\nCollaborate with CAD and implementation teams to enhance and optimize existing Physical Design flows and methodologies.\nIdentify execution bottlenecks and propose practical flow improvements for better QoR, runtime, and scalability.\nDrive automation initiatives across Physical Design stages including FLoorplanning, PnR, STA, ECO execution\nDevelop utilities, scripts, and frameworks using Tcl, Python , Shell & Perl scipring\nWork closely with PD and STA teams to standardize best practices and improve execution consistency.\nSupport MCMM timing closure and signoff tracking across projects.\nDebug flow-related issues and coordinate with CAD teams for fixes and enhancements.\nImprove usability and robustness of implementation flows across multiple designs and technology nodes.\n\nPosition Requirement :\n\nEducation: B.Tech/M.Tech (or higher) in Electrical/Electronics Engineering or related field with 8+ years  experience\nStrong understanding of end-to-end Physical Design flow and signoff methodology.\nHands-on experience with industry-standard tools such as Innovous, FC, Primetime, TempusGood understanding of , STA concepts,  MCMM flows, DRV closure &  Timing/debug methodologies\nStrong scripting and automation skills: Tcl , Python , Unix/Linux shell scripting\n\nExperience in dashboard/report development and data visualization.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Principal Engineer - Implementation", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-05-26", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Principal-Engineer---Implementation_R2010-26-10", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nPrincipal Engineer - Implementation\nCompany Description\nMicrochip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products.\nJob Description\nMicrochip AES Design team in Bangalore is looking for an experienced and motivated Backend Implementation Engineer to perform Synthesis & STA for larger SOCs. As a member of Implementation team, you will be responsible for timing constraints (SDC) generation, timing closure and Low Power checks for multiple blocks and top level. The candidate should have strong experience with STA tools like Tempus/Primetime. The candidate should have in depth knowledge of timing constraints.\nLocation: Bangalore, India\n\nRequirements/Qualifications:\n\nJob Responsibilities:\nThe employee is responsible for implementation activities of multiple large & complex blocks & sub-system implementation from 16nm to 3nm and below technology nodes. The employee is expected to take ownership of Full Chip/Subsystem complex design & flow challenges, which would include:\nPerform Synthesis and STA timing closure for multi-million hierarchical complex designs.\nLead and drive team members to complete Implementation activities.\nComplete timing closure for blocks & top level in advanced nodes.\nDevelop constraints/SDC and perform pre & post-layout timing closure.\nPerform CLP and LEC for both full chip and block level.\nExperience on UPF/CPF would be an added advantage.\nOptimize design performance through timing closure and power optimization.\nDevelop and maintain design constraints and timing models.\nAnalyze and debug timing issues.\nInserting DFT logic for both block and top level.\nAnalyze Physical timing challenges and provide guidance for placement & CTS.\nOccasional travel needed.\nUse metric-driven techniques to help ensure first-pass working silicon.\nCommunicate regularly with the implementation and project team to resolve issues, and communicate status to Project Management.\n\nJob Qualifications:\nThis position requires at least B.E/B.Tech/M.Tech in Electronics with 9+ years of Synthesis & STA experience in a fast-paced environment with following experience.\nExpertise in Implementation activities: Synthesis, STA, LEC, Low Power Checks.\nStatic Timing/Crosstalk Analysis and timing closure\nMust have understanding of DFT insertion.\nExpertise with Synthesis & STA Tools (Genus, Fusion Compiler, Primetime or Tempus).\nExperience on Conformal LEC and CLP will be added advantage.\nStrong programming knowledge in Perl, TCL, and/or Shell and Python Scripting\nExcellent oral and written communications skills to work with teams across the globe\nStrong understanding of timing closure and power optimization techniques\nMust have good understanding of Verilog\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Sr/Staff Engineer, Design Verification,System IP", "company": "Tenstorrent", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-05-25T00:51:44-04:00", "url": "https://job-boards.greenhouse.io/tenstorrent/jobs/5145059007", "is_hardware": true, "platform": "greenhouse", "jd_text": "Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.\n\nWe are looking for a highly skilled and motivated Senior Design Verification Engineer to join our team. In this role, you will be responsible for the end-to-end verification of our IOMMU (Input/Output Memory Management Unit) IP. You will play a critical role in ensuring the functional correctness and performance of the design, taking ownership of the verification process right from the initial specification understanding down to final coverage closure.\n\nThis role is hybrid, based out of Bangalore, India.\n\nWe welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.\n\n \n\nWho You Are\n\nYou have hands-on experience in ASIC or SoC verification using SystemVerilog and UVM.\n\nYou enjoy debugging complex design and verification issues and working closely with cross-functional teams.\n\nYou’re comfortable building verification environments from scratch and driving coverage closure.\n\nYou have familiarity with standard bus protocols and modern verification tools.\n\nWhat We Need\n\nExperience owning block or subsystem-level verification from test planning to sign-off.\n\nStrong understanding of constrained-random verification, coverage analysis, and regression debugging.\n\nFamiliarity with protocols such as AXI, ACE, CHI, or PCIe.\n\nScripting experience in Python, Perl, TCL, or Bash for automation and workflow improvements.\n\nWhat You Will Learn\n\nVerification of advanced CPU and memory-management related IPs used in AI/ML systems.\n\nBuilding scalable UVM environments and improving verification methodologies.\n\nCollaborating across architecture, RTL, and validation teams throughout the development cycle.\n\nUsing Automation and AI-assisted tools to improve productivity and debug efficiency\n\n \n\nTenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.\nThis offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.  Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).   These requirements apply to persons located in the U.S. and all countries outside the U.S.  As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.  If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.", "jd_status": "stored"}, {"title": "Technical Staff Engineer - CAD", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-05-25", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Technical-Staff-Engineer---CAD_R1883-26-7", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nJob Description:\n\nMicrochip CAD is seeking to employ a CAD Engineer to develop and support for Digital and Analog Mixed Signal design flow and methodology for advanced technology nodes.\n\nA successful candidate in this role will be responsible for developing and implementing CAD flow and methodologies as per the design team’s requirements. The successful candidate will possess a thorough knowledge and understanding of the tools and flows required for the design and development of Digital and Mixed Signal designs. He or she will also be knowledgeable about design infrastructure and the implications to environment and work practice.\nHe / She will work closely with various business units across the globe to understand their needs and foster innovative ideas to solve complex problems.\n\nResponsibilities:\nWork closely with Microchip BU teams to ensure Microchip’s digital and mixed signal design flows and tools are robust and reliable.\nProvide front line support for other Microchip staff in the use of these tools and flows\nProvide an interface with external tool vendors and suppliers to resolve issues and provide guidance as needed\nDevelop, test, and release scripts and tools as specified to aid in digital or mixed signal design\nDocument or otherwise archive developed material for future use or re-use\nSuch other comparable duties as may be required by Microchip management\n\nRequirements/Qualifications:\n\nRequirements:\nGood understanding of Analog Mixed Signal(AMS )circuit design (DoT and AoT) methodologies\nMixed Mode Simulation Environments:Cadence VerilogA, Verilog AMS\nSynopsys VCS, VCS-AMS\nSiemens Symphony AMS          \n\nIO and standard cell characterization\nMust be experienced with EDA tools, specifically Cadence Liberate, Liberate-AMS, Synopsys Primelib, Virtuoso, ADE, or their equivalents\nAbility to conduct simulation tools/flows related training and automation preferred\nExperience with Verilog and mixed signal simulations\nMust be experienced with EDA tools, specifically Cadence Xcelium, Siemens Questa, Synopsys VCS or their equivalents\nDesign debugging skills using Verdi, Simvision and Visualizer\nExposure to EDA simulation tools like Primesim, Spectre, SpectreX etc. is preferred\nStrong experience in Design Automation using scripting languages like Perl,TCL, Shell, Python etc. is required\nMust be familiar with Linux OS, grid computing concepts such as LSF\nExcellent organizational skills and strong attention to detail\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Principal Engineer, Digital Design Engineering", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-05-23", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Principal-Engineer--Digital-Design-Engineering_R261841", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\n          \nPrincipal Digital Design Engineer\n\nAbout the Role\nAs a Principal Digital Design Engineer, you will drive technical strategy and innovation for complex digital systems, including System on Chips (SoCs). You'll define product and technology roadmaps, lead architecture for mission-critical projects, and serve as a technical authority within the organization. This position requires exceptional expertise across multiple domains and the ability to influence business direction while mentoring and developing technical talent.\n\nKey Responsibilities\nDefine product and technology strategy for digital design initiatives\nLead architecture development for complex SoCs and digital systems\nDrive innovation and advancement in design methodologies\nMentor and develop technical talent across the organization\nInfluence business direction through technical expertise and market insight\nEngage with customers and industry partners at a strategic level\nRepresent ADI as a technical authority in industry forums\n\nMust Have Skills\nTechnical Strategy: Visionary capability to define and drive technical strategy for digital design\nInnovation Leadership: Exceptional ability to drive innovation in digital design approaches and solutions\nSoC Architecture: Authority in complex SoC architecture design and implementation\nMulti-Domain Expertise: Comprehensive mastery across multiple technical domains\nBusiness Acumen: Strong understanding of business context and ability to align technical strategy with business goals\nIndustry Thought Leadership: Recognized expertise with ability to influence industry direction\n\nPreferred Education and Experience\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent experience\n12+ years of relevant experience in digital design engineering\n\nWhy You'll Love Working Here\nAt Analog Devices, you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on professional growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world.\n\nYour expertise will shape the future of technology, and you’ll be supported by a culture that values continuous advancement and professional growth. Join us and help create the technologies that bridge the physical and digital worlds, making a tangible difference in how people live, work, and connect.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Power and Performance Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-05-21T19:31:00+00:00", "url": "https://global-external-amd.icims.com/jobs/85876/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. MTS Power and Performance Engineer   THE ROLE: AMD’s Computing and Graphics business unit is seeking a technical leader to drive next‑generation power architecture, firmware, algorithms, and software interfaces across AMD client and handheld SoCs. In this highly influential role, you will help define the power‑management architecture for future AMD platforms—driving innovation from early concept and definition, through design execution, and into post‑silicon validation. You will collaborate closely with SoC and platform architects, IP and physical design teams, software and firmware engineering, silicon validation, and packaging teams to deliver breakthrough improvements in power efficiency, performance‑per‑watt, and battery life. This is an opportunity to have a direct and visible impact on AMD’s most advanced products. This senior role will stretch you as you lead architecture teams in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design teams, marketing, and business unit executives. THE PERSON: You are a deep technical thinker with strong problem‑solving and communication skills. You excel at explaining complex concepts through publications, presentations, or executive briefings. You thrive in highly collaborative environments, mentor others naturally, and raise the collective expertise of the teams around you. You combine practical hands‑on skills with system‑level vision, and you are energized by building algorithms and firmware that shape silicon behavior. KEY RESPONSIBILITIES: Algorithm, Firmware & Software Interface Architecture Develop and architect new power algorithms and software features using state‑of‑the‑art techniques, including classfiers, regression models, machine learning approches for CPU/GPU power and performance optimization. Define and implement software interfaces that influence and optimize hardware behavior across the SoC. Prototype and develop new firmware for complex power‑control algorithms throughout the SoC roadmap. Performance & Workload Optimization Profile emerging NN and LLM (Agentic) workloads on client platforms; tune algorithms to optimize power during active, high‑load, and interactive usage scenarios. Analyze power and performance benchmarks to identify opportunities for efficiency improvements. System‑Level Power Architecture Architect, implement, and optimize control software and firmware features to achieve product‑level power targets. Drive cross‑organization alignment for innovative power‑reduction methodologies and ensure convergence across design teams. Collaborate with global architecture and design teams to implement and validate SoC power‑management solutions. Optimize real PC use cases for both absolute power and performance‑per‑watt. Hands‑On Engineering Work directly with development boards to prototype new features and evaluate new power features. Conduct software tracing, firmware debugging, and activity profiling to diagnose issues and drive improvements. PREFERRED EXPERIENCE: Prefer 8+ years of industry experience Experience profiling software workloads on CPUs and GPUs. Knowledge of defining low‑level software interfaces to influence hardware performance and power behavior. Background in SOC hardware design, clock distribution, power delivery and performance Experience profiling and tuning hardware/software stacks to achieve power and performance efficiency on benchmark workloads. Prior algorithm development in C or Python; MATLAB experience preferred. Expertise in algorithm development for predictive systems using regression and classification frameworks for complex datasets. Experience with system and SoC control firmware, including RTOS and bare‑metal development. Familiarity with ACPI, UEFI, and platform‑level power management frameworks. Demonstrated expertise in system and SoC power optimization techniques. Experience with software tracing, firmware debugging, and activity profiling tools. Windows OS and kernel‑level knowledge, including power frameworks, drivers, and system activity tracing. Excellent written and verbal communication skills; ability to lead and influence teams across geographies. Clear, methodical problem solver comfortable driving complex initiatives independently. ACADEMIC CREDENTIALS: PhD or MS in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a related technical field. #LI-AA1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "CPU RTL Design - Sr Eng/Lead/Staff/Sr Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-05-21T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718621803", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nJob Description\n\nGeneral Summary\n\nQualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.\n\nWe are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you will work with chip architects to conceive of the micro-architecture, and also help with architecture/product definition through early involvement in the product life-cycle.\n\nRoles And Responsibilities\n \nPerformance exploration. Explore high performance strategies working with the CPU modeling team.\n\nMicroarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification.\n\nRTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals.\n\nFunctional verification support. Help the design verification team execute on the functional verification strategy.\n\nPerformance verification support. Help verify that the RTL design meets the performance goals.\n\nDesign delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and po\n \n\nPreferred Qualifications\n \nThorough knowledge of microprocessor architecture including expertise in one or more of the following areas: instruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, prefetching, cache and memory subsystems\n\nKnowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools\n\nKnowledge of logic design principles along with timing and power implications\n\nUnderstanding of low power microarchitecture techniques\n\nUnderstanding of high performance techniques and trade-offs in a CPU microarchitecture\n\nExperience using a scripting language such as Perl or Python\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Engineer IP Verification - AMS Verification", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-05-21T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/41982948", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nIn-depth understanding of analog / mixed signal circuits.\n Experience in Analog and Mixed signal Verification , understand the usage of tools like Virtuoso, primesim/ Finseim, Hspice, Xcellium, Simvision, Waveview.\nExperience in debugging complex Analog/Digital/Mixed-Signal circuits is mandatory.\nHands on experience in writing Verilog Models. Verilog A/MS, RVM model writing.\nHands on experience in building SPICE testbenches at Block, Fullchip Level. Hand on experience in building the COSIM/ Mixed signal verification environment.\nHands on experience in SV, UVM based Verification Hands on experience in SV/PSL assertions. Good scripting skills using perl, python is a plus.\nPrevious work experience in DRAM memory related fields and Must possess good communication, debugging skills and ability to work well in a team.\nShould be proactive in exploring and leveraging AI-related tools in day-to-day tasks.\n\nProactively adopt approved AI tools to support verification workflows, scripting, and methodology improvements, maintaining full responsibility for technical decisions.\n\nBachelor’s with 4-6 years of experience or Post Graduate Degree in Electronics Engineering or related engineering field required with 2-4 years of experience.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Lead DSP Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-05-21", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/DSP-Engineer_R-10062153", "is_hardware": true, "platform": "workday", "jd_text": "Role Overview\nWe are seeking a highly motivated DSP Engineer to join our Automotive Ethernet PHY development team. In this role, you will work closely with the DSP Architect to implement and optimize DSP algorithms and architecture for next‑generation automotive-grade Ethernet PHY products. The role requires strong collaboration with System Architecture, DFT, Verification, Validation, IC Integration, and Backend (BE) teams.\nYou will be responsible for DSP design implementation, RTL-level integration, performance validation, and supporting timing closure to ensure high‑quality, production-ready silicon.\n\nKey Responsibilities\nDSP Architecture Implementation\nImplement DSP algorithms and architecture under guidance of the DSP Architect for Automotive Ethernet PHY (e.g., 100/1000BASE-T1 and multi‑gig PHYs).\nTranslate system‑level specifications into optimized DSP RTL design.\nParticipate in algorithm-to-architecture mapping, fixed‑point modeling, and performance tuning.\nDesign & RTL Development\nDevelop synthesizable RTL for DSP datapaths, filters, equalizers, echo cancellation, FFE/DFE, AGC, timing recovery, etc.\nPerform design optimization for area, timing, and power.\nCreate and maintain design documentation, micro‑architecture specs, and implementation notes.\nVerification & Validation Support\nWork closely with the Verification team for test plan development, debug, and coverage closure.\nSupport Validation team during post‑silicon bring‑up, debug, and performance tuning.\nContribute to model correlation between MATLAB/C-model and RTL.\nCross‑Functional Collaboration\nCollaborate with System Architects to refine requirements and improve DSP behavior at system level.\nWork with DFT Architects to ensure testability and seamless integration of DFT structures.\nPartner with IC integrators to define top-level constraints and support SoC integration.\nSupport Backend (BE) teams for timing analysis, timing closure, and physical design iterations.\nPerformance, Tools & Flow\nDevelop and maintain MATLAB/Python models for algorithm validation.\nRun simulations, analyze performance metrics, and support model-to-RTL equivalence.\nContribute to tool flow improvements across DSP modeling, RTL implementation, and validation.\n\nRequired Qualifications\nBachelor’s or Master’s degree in Electrical Engineering, Electronics, Communication Engineering, or related field.\n7+ years of experience in DSP design for communication systems.\nStrong fundamentals in digital signal processing, communication theory, and PHY layer technologies.\nHands-on experience with PHY subsystems such as filtering, equalization, echo cancellation, PLLs, timing recovery, and noise mitigation.\nProficiency in MATLAB, Simulink, Python, or C/C++ for algorithm modeling.\nStrong RTL design skills (Verilog/SystemVerilog).\nFamiliarity with synthesis, linting, CDC, and STA flows.\nExperience supporting verification and post‑silicon debug.\n\nPreferred Qualifications\nExperience in Automotive Ethernet PHY (100BASE‑T1, 1000BASE‑T1, or multi‑gig).\nUnderstanding of EMC/EMI challenges and automotive-grade requirements.\nKnowledge of DFT, ATPG, and scan architectures.\nExposure to backend flows, timing constraints, and timing closure methodologies.\nFamiliarity with formal verification and UVM-based environments.\n\nSoft Skills\nStrong analytical and problem‑solving skills.\nExcellent communication and documentation ability.\nAbility to work effectively in cross‑functional, global teams.\nProactive mindset with the ability to drive tasks to closure.\n\nMore information about NXP in India...\n\n#LI-7013", "jd_status": "stored"}, {"title": "Principal System Software Architect", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-05-21", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Principal-System-Software-Architect_R262578", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).\n          \nPrincipal System Software Architect\n\nAbout the Role\n\nWe are looking for a Principal System Software Architect to join our HW/SW Co-Design team. This is not a role about drawing abstract boxes on slides -- it is about making real, data-driven architecture decisions early in the SoC and IP design cycle by writing code, building virtual platforms, and validating system designs before silicon exists.\n\nYou will work hand-in-hand with a hardware architect counterpart from day one. Your mandate is to ensure that every major design decision -- from IP block selection to data flow topology to accelerator sizing -- accounts for the software developer experience, real-world performance, and customer usability.\n\nThe systems we build ultimately ship to customers whose engineers interact with them through software. You will be the voice of those customers during architecture definition, ensuring that the products we deliver are not only high-performing but also debuggable, straightforward to integrate, have efficient hardware/software interfaces, and have adopted the right ISAs, configurations, and memory sizes.\n\nKey Responsibilities\n\nHardware/Software Tradeoff Analysis: Drive the right balance between hardware complexity, software complexity, performance, and customer usability at the earliest stages of product definition.\nSystem Design Evaluation: Assess system designs, IP blocks, data paths, and device configurations from a software perspective, identifying risks and opportunities before RTL is written.\nCustomer Advocacy: Act as a strong voice and proxy for customers -- particularly their software teams -- who will ultimately interface with the devices we build. Build direct relationships with internal and external customer SW organizations to deeply understand their needs.\nIP & Accelerator Co-Definition: Propose and co-define new IP blocks, hardware accelerators, and device configurations alongside digital and analog hardware design teams to achieve best-possible system performance.\nDebuggability & Observability: Champion best-in-class debuggability and software visibility into devices, both during bringup and in deployed field environments.\nEarly Virtual Platform Development: Build and use SystemC-based functional virtual platforms, or work with early transactional models to validate architecture decisions with real code -- well before silicon availability.\nData-Driven Decision Making: Use early simulation, profiling, and modeling to quantitatively justify sizing, IP selection, and architectural choices rather than relying on intuition alone.\nCustomer Engagement: Meet with technical experts at customer organizations, understand their system-level requirements, and translate those into actionable architectural guidance for internal teams.\n\nRequired Qualifications\n\n12+ years of experience in system software architecture, embedded systems, or SoC platform software\nDemonstrated ability to work at the hardware/software boundary and influence hardware design decisions\nIn-depth experience with AMBA protocols\nExperience with SystemC (TLM 2.0) for virtual platform development and early architecture exploration\nProficiency in C/C++ with experience writing firmware, drivers, or platform-level software\nExperience with early-stage SoC or ASIC development workflows -- architecture definition through silicon bringup\nStrong understanding of computer architecture fundamentals: memory hierarchies, bus protocols (AXI/AHB/APB), DMA, interrupt architectures, and hardware accelerator integration\nAbility to read and understand RTL (Verilog/SystemVerilog) sufficiently to evaluate hardware design intent and debug integration issues\nExcellent communication skills -- able to present complex tradeoffs to both hardware engineers and customer software teams\nTrack record of building relationships with internal and external customers, especially their software/firmware organizations\n\nPreferred Qualifications\n\nFamiliarity with FPGA prototyping workflows and pre-silicon software development\nExperience with hardware emulation platforms (Palladium, etc.)\nKnowledge of signal processing, data converter, or mixed-signal system architectures\nExperience defining or influencing debug/trace infrastructure (e.g., CoreSight, JTAG, embedded trace)\nBackground in performance modeling, system-level benchmarking, or workload characterization\nFamiliarity with RISC-V or Arm architecture and ecosystem tooling\nExperience with Zephyr RTOS and/or Embedded Linux\nExperience with DevOps practices for platform software (CI/CD, automated testing on virtual platforms)\n\nWhat Sets This Role Apart\n\nThis team practices applied architecture. We don't hand off a spec and walk away. We write real code on virtual platforms months or years before tape-out. We measure, profile, and iterate. We sit with hardware designers and debate register maps, buffer depths, and interrupt strategies with data to back up every recommendation.\n\nThis is a deeply hands-on role. Expect to spend days at a time around a table with your hardware and design verification counterparts, working through the details that matter -- interface definitions, timing constraints, configuration trade-offs. It requires attention to detail, the ability to compromise effectively, and the interpersonal skills to build trust with HW, DV and other SW teams whose constraints are different from your own.\nAs requirements evolve and design decisions are tested against reality, you will be there to re-evaluate, adapt, and ensure the end product delivers on its original promise.\n\nIf you've ever been frustrated by poorly designed hardware/software interfaces, missed opportunities to build more efficient and field-debuggable devices, or software that requires hundreds of lines of code to perform what should be a straightforward operation -- you'll thrive in this role. We believe that excessive software complexity to compensate for hardware design gaps is a design failure, and this role exists to prevent exactly that.\n\nEducation\n\nBS/MS/PhD in Computer Engineering, Electrical Engineering, Computer Science, or a related field\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Senior System Software Engineer - HW/SW Co-Design", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-05-21", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Senior-System-Software-Engineer---HW-SW-Co-Design_R262580", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).\n          \nSenior System Software Engineer\n\nWe are looking for a Senior System Software Engineer to join our HW/SW Co-Design team. In this role, you will take ownership of individual IP blocks from a software perspective -- defining, reviewing, and implementing the functionality and the hardware/software interfaces of those blocks in close collaboration with the HW engineer writing the RTL.\n\nYou will work alongside a Principal System Software Architect who sets the broader system-level direction, while you dive deep into the details of specific IP blocks. Your focus is narrower but no less critical: ensuring that each block is well-designed for software consumption, efficiently programmable, debuggable, and consistent with the overall system architecture.\n\nThis is applied engineering, not abstract design work. You will spend 4-6 weeks at a time embedded with a hardware engineer counterpart, iterating together on register maps, data flow, interrupt behavior, configuration schemes, and DMA interfaces -- writing real code against virtual platform models to validate decisions before silicon exists.\n\nKey Responsibilities\n\nIP Block Software Ownership: Own the software perspective for assigned IP blocks end-to-end -- from initial definition through implementation review and pre-silicon validation.\nHW/SW Interface Definition: Work directly with HW engineers to co-define register maps, control/status interfaces, interrupt schemes, and data path configurations that are efficient and straightforward to program.\nVirtual Platform Implementation: Work with the SystemC modeling team to deliver firmware or driver prototypes against virtual platforms to validate IP block designs and catch usability or performance issues early.\nDesign Review Participation: Review RTL specifications and micro-architecture documents, providing actionable feedback from a software integration perspective before RTL is committed.\nDriver & Firmware Prototyping: Develop early driver code and firmware prototypes that exercise IP block functionality, proving out programming models and identifying gaps.\nDebuggability Assessment: Evaluate and influence the debug and observability features of each IP block, ensuring software has adequate visibility during bringup and in the field.\nDocumentation & Handoff: Produce clear programming guides, register descriptions, and usage examples that downstream software teams can use to build production drivers and SDKs.\nCross-Block Integration: Collaborate with peers owning adjacent IP blocks to ensure consistent interfaces, shared conventions, and smooth data flow between blocks.\n\nRequired Qualifications\n\n5+ years of experience in embedded software, firmware development, or SoC platform software\nProficiency in C/C++ with hands-on experience writing device drivers, HALs, or register-level firmware\nStrong understanding of hardware/software interfaces: register maps, memory-mapped I/O, interrupt handling, DMA, and bus protocols (AXI/AHB/APB)\nAbility to read and interpret RTL (Verilog/SystemVerilog) or hardware specification documents\nExperience collaborating directly with hardware design engineers during IP or SoC development\nFamiliarity with SystemC (TLM 2.0) or willingness to develop proficiency quickly for virtual platform work\nAttention to detail -- able to identify subtle interface issues, race conditions, or ambiguities in hardware specifications\nStrong interpersonal skills -- able to work side-by-side with HW engineers for extended periods, negotiate trade-offs constructively, and build trust\n\nPreferred Qualifications\n\nFamiliarity with AMBA protocols\nExperience with SystemC modeling or virtual platform development (e.g., Synopsys Virtualizer, QEMU, or custom TLM platforms)\nFamiliarity with FPGA prototyping or pre-silicon software bring-up workflows\nExperience with Zephyr RTOS and/or Embedded Linux kernel driver development\nKnowledge of RISC-V or Arm architecture, including interrupt controllers, memory protection, and debug infrastructure\nExperience with signal processing, data converter, or mixed-signal IP blocks\nFamiliarity with hardware emulation environments (Palladium, Veloce, etc.)\nBackground in design verification or functional coverage from a software stimulus perspective\nExperience with Verilog/SystemVerilog for co-simulation or design comprehension\n\nWhat Sets This Role Apart\n\nThis is not a downstream software role where you receive a finished data sheet and write a driver. You are part of the design process from the start -- shaping the hardware you will eventually program. When the register map doesn't make sense for software, you have the authority and responsibility to push back and propose alternatives.\n\nExpect to spend weeks at a time working intensively with a single HW engineer on a specific IP block -- whiteboarding interfaces, debating trade-offs, writing prototype code, and iterating until the design is right. This requires patience, attention to detail, and the ability to compromise effectively when hardware constraints conflict with software ideals.\n\nYou will stay with your IP blocks through the full lifecycle: initial concept, specification review, virtual platform validation, silicon bringup, and production driver handoff. If you want deep ownership of the hardware/software boundary at the block level and enjoy the craftsmanship of getting interfaces right, this role is for you.\n\nEducation\n\nBS/MS in Computer Engineering, Electrical Engineering, Computer Science, or a related field\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Chief Architect", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-21", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010559", "is_hardware": true, "platform": "oracle", "jd_text": "We are at a pivotal moment where technology is rapidly evolving, and we have some exciting opportunities within our MCU organization that place us right at the center of this transformation.\n\n \n\nOur current work is focused on developing solutions for high-growth markets such as AI-driven data centers and emerging domains like humanoid systems. These areas are shaping the future of computing, automation, and intelligent systems, and offer a unique chance to work on cutting-edge technologies with real-world impact.\n\n \n\nIf you are passionate about solving complex technical challenges and want to contribute to innovations in these fast-growing segments, I encourage you to come forward and apply. This is an opportunity to be part of a journey that is not only technically rewarding but also strategically significant.\n\n  \n\nLooking forward to seeing many of you take this step\n\n \n\nRole: Chief Architect - SoC / platform\n\nKey Responsibilities\n\nArchitecture vision and strategy\n\nDefine and drive the long-term SoC and platform architecture roadmap across multiple product lines\n\nAlign architecture strategy with business goals, market trends, and customer requirements\n\nEstablish technology direction including compute, connectivity, security, and power architecture\n\nPlatform & Ecosystem Leadership\n\nDefine scalable and reusable platform architectures enabling multiple product variants\n\nDrive IP reuse strategy and ecosystem partnerships (internal and external)\n\nLead decisions on build vs buy vs partner for key technologies\n\nTechnical Governance & Decision Making\n\nOwn architectural decisions across programs ensuring alignment with PPA, cost, and time-to-market goals\n\nEstablish architecture review boards and governance processes\n\nResolve complex cross-functional technical trade-offs\n\nCross-Functional & Executive Collaboration\n\nPartner with product management, business leaders, and customers to translate requirements into architecture strategy\n\nCollaborate with engineering, validation, and software leadership to ensure execution alignment\n\nRepresent architecture in executive forums and customer discussions\n\nInnovation & Future Readiness\n\nIdentify and drive adoption of emerging technologies for competitive advantage\n\nDefine next-generation architecture concepts and incubation initiatives\n\nInfluence industry direction through standards and partnerships\n\nLeadership & Capability Building\n\nMentor senior architects and build high-performing architecture teams\n\nDefine best practices, frameworks, and design methodologies\n\nFoster a culture of innovation, ownership, and technical excellence\n\nQualifications\nExperience\n\n15+ years of experience in SoC architecture, IP design, or chip development\n\nProven track record of successful chip tape-outs and silicon bring-up\n\nExperience defining and meeting PPA (Performance, Power, Area) targets for production chips\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Analog Circuit Design Engineer - AI/ML methodology", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-21", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010677", "is_hardware": true, "platform": "oracle", "jd_text": "About the Opportunity\n\nAre you an engineer who thinks in circuits and code? Texas Instruments is looking for an Analog Design Engineer to join a first-of-its-kind team where classical analog IC design meets artificial intelligence. This is a rare opportunity to be part of a small, high-impact group that is actively shaping how analog products are built at one of the world's leading semiconductor companies.\n\nWhat You Will Work On\n\nAs an Analog Design Engineer, you will create integrated circuit designs that help bring new TI products to life and make our customers' visions a reality. You will define, design, model, implement, and document analog integrated circuits (ICs) across a wide range of end equipment, including audio, imaging, high-speed, interface, clocking, medical, high volume linear, automotive, storage, power supply, battery management, and linear power applications.\n\nYou will work on state-of-the-art wafer processes, learning from and collaborating with industry experts in a unique interdisciplinary team with a fast-paced, startup-like environment. Your day-to-day work will include designing and drawing schematics, simulating for functionality and parametric performance, and assisting in IC layout and post-layout extracted simulations.\n\nBeyond traditional analog design, you will apply AI/ML-enabled tools and flows to accelerate product development and create novel circuits. You will own and drive the adoption of these tools and flows across TI product teams, and you will have the creative freedom to develop novel ideas that can be patented and published. You will also gain exposure to Design Verification and Digital Design through formal learning, projects, and on-the-job experiences that will broaden your knowledge and accelerate your growth at TI.\n\nBring your programming and AI/ML skills to this role and make an impact across the company!\n\nQualifications\nMinimum requirements:\n\nBachelor's in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related field \n\n2 to 5 years experience\n\nCumulative 3.0/4.0 GPA or higher\n\n Preferred qualifications:\n\nStrong fundamentals in analog circuit design concepts with relevant coursework and design projects\n\nCourse project or internship experience in the design, simulation, and layout of one or more analog IPs, such as band-gap reference, ADC, DAC, amplifier, oscillator, comparator, IO cells, and power-management blocks like LDO and DCDC.\n\nFamiliarity with corners, statistical analysis, and post-layout concepts is a plus.\n\nWorking knowledge of Cadence Virtuoso ADE, including Maestro and SPECTRE simulator\n\nFoundational proficiency in Python and one or more packages such as Pandas, PyTorch, TensorFlow, scikit-learn, and Matplotlib\n\nFoundational knowledge of machine learning concepts such as Neural Networks, Graphs, Clustering and Regression techniques, and Decision Trees\n\nStrong verbal and written communication skills\n\nDemonstrated analytical and problem-solving skills, especially in new domains\n\nAbility to work in teams across time zones and collaborate effectively with people in different functions\n\nAbility to take initiative and drive for results in a timely manner\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Analog IC Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-21", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010882", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\nThe Interface Multiplexers group is hiring passionate analog design engineers for their team in Bangalore. You’ll create ultra‑fast (Multi‑GHz) analog multiplexers and switches with NRZ/PAM4 signaling, handling multi‑voltage domains, sub‑Ohm ON resistance (≤1% ΔRₒₙ), nA‑level off‑leakage, ≥30 dB off‑isolation, and 40 V fault tolerance. These high‑speed, low‑loss switches power cutting‑edge data‑center, consumer, medical, test‑and‑measurement, and high‑fidelity audio systems\n\n This is a great opportunity to be part of an established team that's continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electronics, mobile computing and communications.\n\nIn this role, responsibilities may include:\n\nLead an Analog IC design team with product ownership and responsibility from definition to release to manufacturing\n\nDirect, guide and participate in activities of a research or technical design function responsible for designing, developing, modifying and evaluating electronic parts, components, integrated circuits for a variety of applications\n\nMake assignments for team members, providing design guidance as needed, developing schedules and monitoring progress throughout the project\n\nEvaluate intermediate and final results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout\n\nCollaborate with Design Verification teams during the pre-PG phase of a project to ensure completion of all technical tasks before PG\n\nWork with systems engineers, application engineers and marketing to prepare product briefs, datasheets, application notes and assisting in the definition of the product to meet customer needs as well as contributing to roadmap formulation and new concept creation\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nInterface and lead discussions with the customer and/or TI field sales/field applications teams to understand customer designs, problems and support as required\n\nActively participate in hiring, developing and evaluating personnel to ensure efficient operation of the organization and growth of the individuals into leader\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in Electrical Engineering\n\nXX years of relevant experience\n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Analog Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-21", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010759", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\n This is a great opportunity to be part of an established team that's continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electronics, mobile computing and communications.\n\nIn this role, responsibilities may include:\n\nLead an Analog IC design team with product ownership and responsibility from definition to release to manufacturing\n\nDirect, guide and participate in activities of a research or technical design function responsible for designing, developing, modifying and evaluating electronic parts, components, integrated circuits for a variety of applications\n\nMake assignments for team members, providing design guidance as needed, developing schedules and monitoring progress throughout the project\n\nEvaluate intermediate and final results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout\n\nCollaborate with Design Verification teams during the pre-PG phase of a project to ensure completion of all technical tasks before PG\n\nWork with systems engineers, application engineers and marketing to prepare product briefs, datasheets, application notes and assisting in the definition of the product to meet customer needs as well as contributing to roadmap formulation and new concept creation\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nInterface and lead discussions with the customer and/or TI field sales/field applications teams to understand customer designs, problems and support as required\n\nActively participate in hiring, developing and evaluating personnel to ensure efficient operation of the organization and growth of the individuals into leader\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in Electrical Engineering\n\n5 years of relevant experience\n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Design Verification Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-21", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010823", "is_hardware": true, "platform": "oracle", "jd_text": "The RADAR product line is a rapidly expanding business within TI, investing to address the fast-growing segment in Industrial & automotive markets. This product line will enable a scalable portfolio using DSP and ARM multi-cores to support high-end applications in ADAS, body & Chassis and in Industrial space. Radar systems process digital information from sources like digital cameras, lasers, radar and other sensors to perform tasks such as lane departure warning or parking assistance. The processed information can be displayed on screens or announced via acoustical warning signals. The system has multifaceted features such as High precision ADC, extremely accurate chirp, wide range visibility and Faster scene processing abilities. As a Verification Engineer, you will play a pivotal role in ensuring the quality and reliability of our advanced RADAR products. You will be responsible for the verification of IP, Subsystem (SS), and System-on-Chip (SoC) designs, contributing to the development of robust verification methodologies and strategies.\n\nResponsibilities: \n\nComplete ownership of IP/subsystem/SOC DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis. This includes:\n\nActive involvement with architecture team during the spec definition phase \n\nVerification strategy definition along with Verification plan to meet 100% spec to regression traceability along with signoff metrics \n\nIP/SS/SOC verification covering functional and Firmware scenarios in RTL/PARTL, GLS/PAGLS modes. \n\nDV Environment ownership: TB development/enhancements including checkers and coverage monitor definitions along with DV flow updates as per the project needs \n\nActive collaboration with cross functional teams -Architecture, RTL, PD, DFT, Systems, Analog, FW and application teams -to enable the Verification goals for IP/Subsystem/SOC starting from spec definition till post silicon verification closure activities\n\nFinal SoC DV signoff based on Regressions, coverage metrics, DV to spec traceability using C and/or SV-UVM adhering to ISO26262 guidelines\n\nQualifications\nQualifications:\n• 5+ years of  DV experience in IP/SS/SOC/Post silicon DV with a Bachelor or Master’s degree in EE/ECE/CS or related specializations\n \nSkills: \nExperience in one or more of the following areas: C-based SoC design verification (DV), firmware verification exposure, scripting knowledge (Perl/Python/AI/ML based DV), DV flow ownership for functional/firmware verification, deep understanding of UVM/SystemVerilog, Specman, GLS/PAGLS/CPF/UPF based verification, post-silicon verification, etc.\nThorough knowledge of standard protocols, such as AXI, AHB, APB, CAN, Ethernet, I2C, SPI, UART, and high-speed interfaces like CSI and Ethernet.\nWork experience in a C-based environment with complex ARM/DSP multi-processor systems, including power-aware simulations, is a significant plus.\nStrong understanding of digital design fundamentals, computer organization and architectures, and bus protocols.\nExcellent debugging skills with Verilog/VHDL designs.\nGood problem-solving skills.\nExperience with Cadence tools (Xcelium/vManager/Formal JG applications/safety simulator) or similar tools/DV flows.\nProficiency in AMS, CDC digital verification, formal verification, and post-silicon verification, along with familiarity with functional safety and cybersecurity processes, would be advantageous.\nEffective communication skills to interact seamlessly with all stakeholders.\nMust be highly focused and committed to achieving project goals.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Staff SW Systems Design Engineer", "company": "Analog Devices", "location": "India, Bangalore, Nova", "date_posted": "2026-05-21", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-Nova/Staff-SW-Systems-Design-Engineer_R262447", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).\n          \nStaff Engineer – SW Systems Design Engineering \nExperience Required: 7+ Years\nRole Type: Individual Contributor / Technical Leader \n\nPosition Overview\nWe are seeking a Staff Engineer in SW Systems Design Engineering to join Engineering Enablement group. In this high-impact role, you will define and lead the strategy for system-level modeling, virtual prototyping, and early customer enablement. You will also bridge the gap between SoC architecture, hardware design, and software teams, ensuring that our next-generation SoC models and prototypes are performance-optimized and ready for customer engagement well before silicon tape-out. \n\nKey Responsibilities\nCreate high-fidelity virtual platforms that enable internal early SW development and demonstrate ADI capabilities and enable ADI customers in defining and developing their products using models for ADI SoCs. \nDevelop AI skills, tools and environments that ease building and adoption of virtual prototypes for both internal teams and  ADI customers\nTroubleshoot complex system-level issues, serving as the escalation point for pre-silicon customer feedback.\nCollaborate closely with ADI customers and internal product teams to create right virtual platforms.\n\nRequired Qualifications\nExperience: 7+ years of industry experience in SoC design, architecture, or system-level modeling.\nModeling Expertise: Strong hands-on experience in SystemC, TLM 2.0, C/C++ or equivalent high-level modeling, and virtual platforms\nSoftware Proficiency: Expert-level C++ programming skills, with experience in Python and scripting for modeling automation.\nArchitecture Knowledge: Deep understanding of SoC architecture, including CPU subsystems (ARM/RISC-V), bus protocols (AMBA AXI/CHI), and memory hierarchies.\nLeadership: Demonstrated ability to drive technical decisions across cross-functional teams (Architecture, HW, SW, Product Marketing teams). \n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Staff Engineer, CPU Core Verification ", "company": "Tenstorrent", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-05-20T01:24:01-04:00", "url": "https://job-boards.greenhouse.io/tenstorrent/jobs/5140149007", "is_hardware": true, "platform": "greenhouse", "jd_text": "Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.\n\nAt Tenstorrent, we build open, state of the art compute for real workloads and real developers.You will own CPU core‑level verification, shaping how our out‑of‑order RISC‑V CPUs behave in silicon.\n\nThis role is hybrid, based out of Bangalore, India.\n\nWe welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.\n\n \n\nWho You Are\n\nYou bring 8+ years in CPU verification or closely related digital design.\n\nYou know high‑performance out‑of‑order CPU microarchitecture in depth.\n\nYou work comfortably with RTL, waveforms, logs, and complex debug scenarios.\n\nYou communicate clearly across design, DV, emulation, and post‑silicon teams.\n\n \n\nWhat We Need\n\nPlan and drive functional verification for CPU core features and complex microarchitectural scenarios.\n\nDevelop UVM, assembly, and C/C++ based stimulus, functional models, and coverage for ISA, RISC-V extensions, and un-core components.\n\nDebug simulation and emulation regressions using RTL understanding, waveforms, and logs to identify and resolve issues efficiently.\n\nBuild and enhance coverage models, testbenches, and debug infrastructure to improve verification quality and coverage closure.\n\nCollaborate with design, validation, and test teams to support bring-up and delivery of robust CPU cores and clusters.\n\n \n\nWhat You Will Learn\n\nHow Tenstorrent designs and validates high‑performance RISC‑V CPU cores and clusters.\n\nTechniques for spanning pre‑silicon, emulation, and post‑silicon verification with shared stimulus.\n\nWays to scale coverage, debug, and infrastructure across multiple CPU programs.\n\nHow open hardware and software fit into Tenstorrent’s broader compute roadmap.\n\n \n\nTenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.\nThis offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.  Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).   These requirements apply to persons located in the U.S. and all countries outside the U.S.  As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.  If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.", "jd_status": "stored"}, {"title": "Senior Staff Engineer, Physical Design - NoC", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-05-20", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Senior-Staff-Engineer--Physical-Design---NoC_R-101150-1", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nAbout the Role -- \nAt SiFive, we’re redefining the compute landscape with our industry-leading RISC-V compute platforms. As a Sr Staff Physical Design Engineer (NoC/Uncore), you will own and drive the implementation of massive, high-bandwidth interconnects and Uncore subsystems across multiple products from RTL to GDSII. You will be responsible for implementing and collaborating on the co-design of PPA-optimized solutions, focusing on achieving high-performance and power efficiency using the latest technology nodes.\nWhile your primary focus will be physical design, this role requires you to operate fluidly across design-abstraction layers. You will act as a crucial bridge between architecture, RTL, and implementation, relying on deep backend expertise and system-level understanding to influence top-level architecture and micro-architecture. Your work will directly impact the scalability, bandwidth, and quality of our IP, in addition to implementation PPA.\n\nResponsibilities - What you’ll do\nLead NoC Implementation: Drive the complete physical design implementation for complex NoC and Uncore sub-systems, including synthesis, place & route, and signoff.\n\nDrive Cross-Abstraction-Layer Co-Design: Go beyond standard physical design implementation by actively engaging in Architecture/RTL/PD co-design. Understand the IP micro-architecture deeply enough to suggest RTL modifications, pipeline strategies, or architectural tweaks that resolve physical bottlenecks early.\n\nSolve NoC-Specific Challenges: Tackle complex physical bottlenecks unique to interconnects, long-distance timing closure, repeater/pipeline-stage insertion, and top-level clock distribution/methodology across massive die areas.\n\nArchitectural Floorplanning: Drive top-level floorplanning, macro placement, hierarchical partitioning, and pin assignments to optimize data flow between CPU cores, accelerators, and memory boundaries.\n\nAggressive PPA Optimization: Optimize implementation for aggressive PPA goals, managing trade-offs and optimizing design points for various high-performance product lines.\n\nCross-Functional Leadership: Collaborate heavily with architecture, RTL, and power teams to drive co-design closure. Influence micro-architecture decisions early in the design cycle to prevent physical bottlenecks.\n\nDrive Methodology: Architect, support, and significantly improve physical design flows, automation, and methodology for top-level integration and hierarchical implementation across multiple technology nodes.\n\nMentorship: Act as a technical pillar within the team, mentoring junior engineers and leading by example in driving process efficiency and design excellence.\n\nRequirements - What you’ll bring\n10+ years of hands-on experience in physical design implementation. Understanding of design, architecture and PPA tradeoffs are a plus.\n\nCross-Abstraction-Layer Expertise (Highly Desired): A strong understanding of digital logic design, NoC micro-architecture, and system-level data flow is a major plus. You should be comfortable reading RTL; and engineering across abstraction layers to drive PPA optimization through architecture/design/implementation co-design.\n\nNoC/Uncore Expertise: Proven experience in physical design implementation of massive interconnects, coherent hubs, or complex memory subsystems. Familiarity with NoC architectures and the physical implications of high-bandwidth bus routing.\n\nHierarchical Mastery: Deep expertise in top-level physical integration, hierarchical P&R methodologies, and global timing closure.\n\nAdvanced Problem Solving: Proven ability to optimize for aggressive PPA targets using advanced physical design techniques, accompanied by a detail-oriented mindset and clear communication skills.\n\nTool Proficiency: Hands-on knowledge of RTL to GDS implementation with Synopsys and/or Cadence synthesis, PnR and signoff implementation tools.\n\nEducation: Bachelor’s or Master’s in Electrical or Computer Engineering.\n\nWhy join us?\nBe part of the RISC-V movement and help define the future of computing architecture.\n\nWork on industry-leading IP adopted by top customers and shipped in high volumes worldwide.\n\nCollaborate with world-class engineers in a supportive, fast-paced, learning environment.\n\nEnjoy a culture that values innovation, ownership, and technical excellence.\n\nOur large IP portfolio offers opportunities to engineer solutions across multiple IPs and product families over time.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "SRAM Layout Engineer", "company": "Samsung", "location": "SSIR, Goldstone, Bangalore, India", "date_posted": "2026-05-20", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/SSIR-Goldstone-Bangalore-India/SRAM-Layout-Engineer_R117290-1", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.\nRole and Responsibilities\n\n· Must have 4 - 8 years of experience in SRAM Layout in advanced CMOS process\n\n· Should be able to perform SRAM Memory layout development and physical verification activities for complex designs as per provided specifications.\n\n· Should have expertise in layout area and routing optimization, design rules, yield and reliability issues.\n\n· Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.\n\n· Should have adequate knowledge of schematics, interface with circuit designer and CAD team.\n\n· Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,\n\nSkills and Qualifications\n\nExperience – 4 to 8 Years of experience\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "R&D Engineering, Manager", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-05-20", "url": "https://careers.synopsys.com/job/bengaluru/r-and-d-engineering-manager/44408/95324696128", "is_hardware": true, "platform": "talentbrew", "jd_text": "Alternate Job Titles\nR&D Engineering, Manager\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent a decade building and leading teams that turn RTL into silicon that actually works at 2nm, 3nm, and beyond. Not just tapes out, actually works, meeting PPA targets on schedule while navigating the chaos of advanced node bring-up. You know that the hardest part of physical design is not running the tools, it is making the right call when timing is bleeding, power is over budget, and the customer needs an answer by Friday. You have been that person in the room who sees the tradeoff three steps ahead and can explain it to both your team and a VP without losing the thread.\nManaging a team is not about delegation for you, it is about building engineers who can solve problems you have not seen yet. You mentor through real work, not performance reviews. When someone on your team hits a wall with congestion or a tricky multi-corner scenario, you can sit down, look at the floorplan, and help them find the path forward.\nYou are comfortable in the weeds and in the strategy meeting. You can debug a hold violation in the morning and present a project roadmap to a customer in the afternoon. At Synopsys, you will lead the physical implementation of PVT Sensor IP across the most advanced nodes in production, working with a team that takes this work seriously and customers who depend on what you deliver.\nWhat You'll Be Doing\nLead end-to-end physical implementation of PVT Sensor IP digital modules from floorplanning through GDSII across 1.4nm to 7nm foundry nodes, driving timing closure, power optimization, and sign-off\nManage and grow a team of ASIC physical design engineers, setting technical direction, reviewing work, and mentoring engineers through complex multi-corner, multi-mode closure challenges\nWork hands-on when needed, jumping into critical path analysis, congestion fixes, or tricky STA scenarios to unblock your team and keep projects moving\nCollaborate daily with front-end design, verification, and product engineering teams to align RTL quality, design constraints, and implementation strategy from the start\nOwn project planning, resource allocation, and budget management for your team, balancing workload across multiple concurrent programs and node bring-ups\nInterface directly with customers to gather requirements, provide technical updates, resolve design issues, and ensure delivery meets their performance and schedule expectations\nDrive continuous improvement in design flows using Synopsys EDA tools, optimizing methodology for faster convergence, better PPA, and cleaner handoffs to sign-off\nThe Impact You Will Have\nDeliver PVT Sensor IP that ships in high-volume SoCs, enabling real-time temperature, voltage, and process monitoring that directly improves chip performance and reliability for end customers\nSet the technical standard for physical design implementation across advanced nodes, influencing how Synopsys builds and delivers IP at scale\nBuild a team that can take on the next generation of design challenges, creating a culture where engineers grow, solve hard problems, and ship quality work\nStrengthen customer relationships by delivering on commitments, responding quickly to technical concerns, and ensuring IP quality meets production requirements\nReduce time to closure and improve design predictability by refining flows, catching issues earlier, and sharing what works across programs\nContribute to Synopsys IP portfolio competitiveness by ensuring every tapeout meets or exceeds PPA benchmarks and schedule commitments\nShape IP quality and release processes, ensuring what you deliver is not just correct but maintainable and reusable across future projects\nWhat You'll Need\n10+ years in ASIC or IP physical design with proven delivery of complex designs at 7nm or below, including hands-on experience with floorplanning, place and route, clock tree synthesis, and timing closure\nDeep technical expertise across the full design flow from RTL to GDSII, including front-end understanding of synthesis and verification, and back-end mastery of STA, power analysis, and sign-off\nDirect experience managing and mentoring engineering teams, with a track record of developing engineers and delivering projects on time\nStrong working knowledge of Synopsys EDA tools including IC Compiler II, Fusion Compiler, PrimeTime, and StarRC, with experience optimizing tool flows for advanced nodes\nDemonstrated ability to manage project schedules, allocate resources, and handle team budgets in a multi-program environment\nExcellent communication skills, you can present technical content to customers, explain design tradeoffs to cross-functional teams, and write clear status updates that executives actually read\nExperience with IP quality processes, release workflows, or customer-facing IP delivery is a strong plus\nWho You Are\nYou can walk into a design review, spot the issue in a timing report or floorplan in two minutes, and guide your engineer to the fix without taking the keyboard\nWhen a project is slipping, you do not panic or blame, you figure out what is actually blocking progress, re-prioritize, and communicate the plan clearly to your team and stakeholders\nYou care about growing your team, not just hitting milestones. You make time to review work, answer questions, and help engineers learn from mistakes instead of just fixing them\nYou are comfortable saying no or pushing back when a requirement does not make sense, a schedule is unrealistic, or a design decision will create problems downstream\nYou stay organized across multiple projects without losing sight of the details that matter, you know which corners are failing, which engineers need support, and which customers are waiting on updates\nYou treat customer commitments seriously and follow through, even when it means working through a tough problem or having a hard conversation about what is possible\nThe Team You'll Be Part Of\nYou will be joining the PVT Sensor IP team, a group focused on developing embedded sensor IPs that monitor real-time chip conditions like temperature, voltage, and process variation. These sensors are integrated into SoCs across the industry, enabling performance optimization and lifetime health monitoring. The team works closely with cross-functional groups across Synopsys and directly with customers to deliver IP that meets the highest standards for performance, quality, and on-time readiness. As a leader, you will shape the technical direction of physical implementation, mentor engineers, and drive execution across multiple advanced node programs. The team operates out of Bangalore and Bhubaneswar.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Staff Engineer, Low Power Verification & Formal Equivalence", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-05-20", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Staff-Engineer--Low-Power-Verification---Formal-Equivalence_R-101164", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nAbout the Role\n\nWe are seeking a highly skilled Staff Engineer to lead our Low Power Verification and Formal Equivalence signoff methodologies. In this critical role, you will be the ultimate owner of the static low power checks and formal verification flows for our advanced, high-performance designs. You will partner closely with Physical Design and Power teams to ensure robust power intent implementation and flawless logical equivalence throughout the RTL-to-GDSII flow, including managing complex, late-stage engineering changes.\n\nKey Responsibilities\nLow Power Signoff Ownership: Take full ownership of all static low power verification checks across the design hierarchy, ensuring complete coverage and zero low-power structural bugs.\n\nUPF Strategy & Automation: Collaborate closely with Platform Engineering and Power architecture teams to architect, optimize, and automate Unified Power Format (UPF) coding and deployment.\n\nFormal Equivalence Leadership: Own and drive the complete Formal Equivalence Checking flow, acting as the primary authority for ensuring logical equivalence from RTL through post-route, including managing complex Engineering Change Order (ECO) implementations.\n\nCross-Functional Optimization: Leverage your understanding of Physical Design limitations and power architectures to provide highly optimal, implementable UPF and equivalence solutions.\n\nRequired Qualifications\nEducation & Experience: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with 7+ years of relevant industry experience in ASIC/SoC design and verification.\n\nPower Intent Mastery: Deep, authoritative understanding of architecting and coding power intent using the Unified Power Format (UPF).\n\nStatic Power Verification: Proven expertise running, analyzing, and debugging static low power checks on both RTL and post-PNR netlists using industry-standard tools (e.g., Synopsys VC Low Power / VCLP).\n\nFormal Signoff: Extensive, hands-on experience with Logical Equivalence Checking (LEC) and Formal Equivalence tools (e.g., Synopsys Formality), with specific expertise in driving formal ECO flows.\n\nLow Power Libraries: Strong technical understanding of Power Management library cells and their physical/logical implications, including Isolation cells (ISO), Level Shifters (LS), Always-On (AON) cells, and Retention registers.\n\nPreferred Qualifications\nPhysical Design Foundation: Solid foundational knowledge of the backend Physical Design (PD) flow, enabling you to anticipate implementation challenges and bridge the gap between frontend intent and backend realization.\n\nScripting & Automation: Strong scripting proficiency (TCL, Python, or Perl) to drive flow automation, custom rule creation, and methodology improvements.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Staff Engineer, Physical Design - Caches", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-05-20", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Staff-Engineer--Physical-Design---Caches_R-101153", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nAbout the Role -- \nAt SiFive, we’re redefining the compute landscape with our industry-leading RISC-V compute platforms. As a Staff Physical Design Engineer (Caches/Memory Subsystems), you will own the physical implementation of critical memory cache structures and tightly integrated SRAM subsystems, from RTL to GDSII. You will deliver high-performance, dense, and power-efficient memory designs on advanced and legacy process nodes.\nWhile your primary focus will be in physical design, we are looking for engineers capable of operating across design-abstraction layers. Caches are the heart of CPU performance, and you will act as a bridge between the architecture, RTL, and implementation teams. By understanding the underlying design, you will help drive co-design optimizations that directly impact the speed, area, and efficiency of our IP.\n\nResponsibilities - What you’ll do\nOwn Cache Implementation: Drive the physical design implementation for high-performance cache blocks and memory sub-systems, managing synthesis, place & route, and signoff.\n\nEngage in Cross-Abstraction-Layer Co-Design: Go beyond standard implementation by actively participating in Architecture/RTL/Implementation co-design. Understand the cache micro-architecture to suggest RTL tweaks, pipeline strategies, or custom macro arrangements etc. that resolve physical bottlenecks.\n\nSolve Memory-Specific Challenges: Tackle physical bottlenecks unique to cache design, including highly dense SRAM macro placement, complex routing over macros, critical path timing through memory arrays, and strict dynamic/leakage power management.\n\nAggressive PPA Optimization: Optimize block-level implementation for aggressive Power, Performance, and Area (PPA) goals, managing complex trade-offs for various product lines.\n\nCollaborate Cross-Functionally: Work closely with RTL designers, IP vendors, and power teams to close design requirements and ensure efficient integration of memory instances.\n\nEnhance Methodology: Support and improve physical design flows, automation scripts, and methodologies for memory-heavy block implementation.\n\nRequirements - What you’ll bring\n7+ years of hands-on experience in physical design implementation of PPA critical blocks (CPUs, Caches etc.).\n\nCross-Abstraction Awareness: A solid understanding of digital logic design and basic memory architecture. You should be comfortable reading RTL to understand the design intent and collaborate effectively with front-end teams.\n\nStrong Problem Solving: Proven ability to optimize for aggressive PPA targets using industry-standard physical design techniques, accompanied by a detail-oriented mindset.\n\nTool Proficiency: Hands-on knowledge of RTL to GDS implementation with Synopsys and/or Cadence synthesis, PnR and signoff implementation tools. And good scripting skills.Tool Proficiency: Expertise in RTL to GDS flow implementation using Synopsys and/or Cadence tools for synthesis, Place and Route (PnR), and signoff.\n\nEducation: Bachelor’s or Master’s in Electrical or Computer Engineering.\n\nWhy join us?\nBe part of the RISC-V movement and help define the future of computing architecture.\n\nWork on industry-leading IP adopted by top customers and shipped in high volumes worldwide.\n\nCollaborate with world-class engineers in a supportive, fast-paced, learning environment.\n\nEnjoy a culture that values innovation, ownership, and technical excellence.\n\nOur large IP portfolio offers opportunities to engineer solutions across multiple IPs and product families over time.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Post‑Silicon SoC & System‑Level Validation Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-05-19T16:09:00+00:00", "url": "https://global-external-amd.icims.com/jobs/81139/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Role Overview : This role focuses on validating end‑to‑end system behavior, ensuring that multiple SoC subsystems interact correctly under real customer and system‑level use cases. KEY RESPONSIBILITIES:  Own SoC‑level post‑silicon validation, focusing on interaction between multiple subsystems rather than isolated IP testing. Validate end‑to‑end system flows involving CPU cores, on‑chip memories, NoC/interconnect, IOs, power management, and firmware. Ensure correct behavior across boot, runtime, stress, error, and recovery scenarios at the SoC level. Develop validation test cases based on customer use cases (boot flows, IO usage, stress, concurrency, power transitions) into executable validation plans. Debug & root cause analysis: Perform deep SoC‑level debug to isolate failures across hardware, firmware, and system software boundaries Lab execution & characterization: Use engineering lab equipment (oscilloscopes, protocol analyzers, signal generators, etc.) to validate and debug functional behavior Documentation & reporting: Produce clear test plans, execution reports, failure analysis summaries, and status updates; track bugs/issues to closure QUALIFICATIONS: Experience in pre‑silicon and/or post‑silicon SoC validation, with strong ownership in post‑silicon execution. Strong understanding of SoC architecture and subsystem interactions. Experience validating system‑level use cases and customer‑driven scenarios. Familiarity with debug tools, system logs, traces, and lab‑based validation setups Strong understanding of SoC boot flows, firmware, and HW/SW interaction. Lab proficiency: Extensive experience using lab equipment such as oscilloscopes, protocol analyzers, signal generators, etc. Preferred Qualifications : Experience with emulation platforms (Palladium, Protium, Zebu) for pre‑silicon or early validation. Exposure to NoC fabrics, power management, clock/reset architecture, and system controllers. Familiarity with system software stacks (bootloader, Linux, RTOS) and their interaction with silicon. Hands on experience using AI tools #LI-NS2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Staff ASIC Validation Engineer (Chaz/Characterization))", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-05-19T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/41286780", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nKey Responsibilities:\nLead first‑silicon bring‑up, board validation, and early silicon debug.\nDevelop and complete detailed electrical characterization plans covering DC, AC, parametric, and functional measurements.\nCharacterize high‑speed interfaces such as DDR/LPDDR, SerDes, MIPI, UFS, or custom Micron PHYs.\nPerform post‑silicon electrical characterization of ASIC/SoC/Memory products across process, voltage, and temperature (PVT) corners.\nConduct lab measurements using equipment such as Oscilloscopes, BERTs, VNAs, Spectrum analyzers, Waveform generators, and support tools.\nInvolve in Board design activities with team to gather and place custom requirements as per Chaz.\nPerform signal integrity (SI), power integrity (PI), Jitter, Eye‑diagram, and compliance testing.\nDebug silicon issues related to timing, noise, stability, margin loss, and functional failures.\nAnalyze failures and recommend design, firmware, or test fixes.\nDevelop Python/MATLAB-based automation for measurements, data collection, and analysis.\nProcess large volumes of lab and silicon data to extract trends, margins, and correlations.\nGenerate concise characterization reports with clear conclusions and recommendations.\nWork closely with design, pre‑silicon verification, product engineering, firmware, test, and systems teams.\nCorrelate post‑silicon results with simulation and pre‑silicon expectations to identify root causes of gaps.\nWork closely with Design Team & propose enhancements and design changes to tackle next generation challenges.\nContribute to silicon learning documentation and guidelines for comprehensive Chaz activities.\n\nRequired Qualifications:\n6 to 8 years of Industry experience in High Speed Post Silicon Electrical Characterization Domain\nBachelor’s or Master’s degree in Electrical / Electronics or related field.\nStrong understanding of CMOS fundamentals, analog/digital circuits, and high‑speed interfaces.\nHands‑on experience with High-Speed Post‑silicon electrical characterization.\nDeep knowledge of signal integrity, power integrity, timing analysis, jitter, noise coupling, Channel loss & SerDes.\nProficiency in lab equipment operation and debugging methodologies.\nExperience with scripting and automation (Python preferred).\nBackground in (DDR/LPDDR/PCIe), SerDes, or high‑speed PHY characterization.\nFamiliarity with ATE correlation, compliance specs, and JEDEC/PCI-SIG standards.\nExperience owning end‑to‑end characterization of a subsystem or interface.\nProven track record of silicon issue root‑cause analysis and resolution\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Staff Product Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-05-19", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505474", "is_hardware": true, "platform": "oracle", "jd_text": "Job description\n\n \n\nThis opportunity offers a chance to join the Intelligent Sensing Group (ISG) at onsemi within the Product Engineering team, contributing to the bring-up, validation, and mass production of mixed-signal image sensors. Selected candidates will be responsible from driving the product from definition phase to market release.\n\n \n\n#LI-RT1\n\nResponsibilities\nPerformance Objectives:\nDrive development of new products that satisfy demands for cost/performance and development schedule\nSeek new ideas, develop innovation and creativity throughout the team\nWork with NPD teams to develop validation and test plans   \nExecution of product validation requirements by working with cross functional teams, including Design, DFT, and Test Engineers\nTeam oriented with can do attitude, enthusiastic in solving challenging issues\nMust have confidence to act quickly and decisively when required \n#LI-RT1\n\nQualifications\nQualification Requirements:\n \nBachelor or master's degree in Electronics ,Electrical or related discipline; \n5+ years’ relevant industry experience in bench validation or characterization of both analog and digital blocks.\nExperience with statistical tools like JMP, datapower  or equivalent for yield enhancement activities.\ngood communication and written skills and delivering high quality projects on time.\nPrevious work experience with CMOS image sensors is a plus.\nPrevious work on domains other than characterization & validation like board design, analog/digital design, verification, DFT pattern generation is a plus.\nGood understanding of silicon bring-up, production test flows, usage of lab equipment like oscilloscopes, signal generator, logic analyzer, etc.\nExperience with programming languages (e.g. C, VB, Python)\n#LI-RT1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "NPU/AI Processor Architecture (RTL)/Arithmetic Design Engineer - Sr Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-05-18T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446717639038", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nQualcomm’s Hexagon NPU is a proprietary, in-house processor at the heart of our hybrid AI computing capabilities. It powers a wide range of AI use cases across market segments and is central to Snapdragon’s performance\nWe are looking for highly skilled engineers with 5+ years of experience in:\n-   CPU/AI Processor Design & Architecture\nPerformance & Reliability\nDebug & System Integration\nComputer Arithmetic (Floating-Point design, Matrix Multiply engines, Vector Extensions)\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "IP RTL Design Engineer", "company": "Samsung", "location": "SSIR, Goldstone, Bangalore, India", "date_posted": "2026-05-18", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/SSIR-Goldstone-Bangalore-India/IP-RTL-Design-Engineer_R117218", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nAbout Samsung Semiconductor India Research (SSIR)With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more. As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.\nRole and Responsibilities\n\nSamsung Semiconductor India Research (SSIR) is seeking an experienced RTL/Logic Design Engineer to join the Memory PHY IP development team. The role will focus on the development of HBM, LPDDR PHY projects, delivering high‑performance PHY IP for our customers and providing post‑silicon support.\n\nWrite, verify, and maintain synthesizable RTL for LPDDR PHY blocks\n-          Write SDC constraints, synthesize and ensure timing closure.\n-          Setup and run IPXACT, LINT, CDC, SDC, PreSTA, DFT and ATPG checks\n-          Support silicon validation bring-up and debug post-silicon issues\n-          Work closely with internal and external customers to understand requirements and timely deliverables\n\nRequired Qualifications:\n-          4 years of full‑cycle RTL/logic design experience, preferably in memory‑PHY or high‑speed interface IP.\n-          Strong RTL coding background (Verilog/SystemVerilog)\n-          Proficiency with QC tools such as LINT, CDC, DFT, ATPG\n-          Experience in SDC creation, Synthesis & STA\n-          Prior work on LPDDR, HBM PHY projects is preferred\n\nSkills and Qualifications\n\nExperience – 4 to 10 Years of experience\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "IP Design Verification Engineer", "company": "Samsung", "location": "SSIR, Goldstone, Bangalore, India", "date_posted": "2026-05-18", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/SSIR-Goldstone-Bangalore-India/IP-Design-Verification-Engineer_R117217", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nAbout Samsung Semiconductor India Research (SSIR)With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more. As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.\nRole and Responsibilities\n\nDesign & maintain UVM‑based verification environments for high‑speed serial IP blocks (e.g.,56G/112G/224G Gbps SERDES, PCIe Gen4/5, Ethernet MAC/PHY,) and security IP (AES/SHA engines, ECC, secure‑boot, root‑of‑trust).\nDevelop comprehensive test plans and coverage models that capture protocol corner cases, timing jitter, eye‑diagram constraints, and security threat scenarios.\nCreate reusable UVM components (agents, drivers, monitors, scoreboards, and protocol checkers) that can be shared across multiple serial and security projects.\nImplement constrained‑random traffic generators with data‑pattern, error‑injection, and latency‑stress capabilities to validate link reliability and security robustness.\nIntegrate formal verification and assertion‑based checking (SVA) to capture protocol violations, key‑exchange errors, and timing violations early in the flow.\nRun and maintain regression suites on industry‑standard simulators (VCS, Xcelium, Questa) and CI pipelines; monitor functional coverage, protocol coverage, and security‑feature coverage.\nCollaborate closely with design, architecture, and security teams to refine specifications, resolve bugs, and drive design for testability (DfT) and low‑power considerations.\nMentor junior verification engineers, enforce coding standards, and contribute to the IPD verification methodology library.\nParticipate in design reviews, risk assessments, and compliance verification (e.g., PCI‑SIG, IEEE Ethernet, NIST crypto standards). \nRequired Skills & Experience\nSystem Verilog & UVM, Formal Verification expertise – 5–6 years of hands‑on verification on complex IP, with strong understanding of class‑based verification, randomization, coverage, and SVA.\nHigh‑speed serial protocol knowledge – Practical experience verifying PCIe, Ethernet SERDES, or similar high‑throughput interfaces.\nSecurity IP verification – Familiarity with cryptographic engines, secure‑boot flows, authentication protocols, side‑channel analysis, and related test strategies.\nSimulation & automation tools – Proficient with VCS, Xcelium, or Questa; scripting in Tcl/Python for test bench generation and regression management.\nCoverage‑driven verification – Ability to define functional, protocol, and security coverage models and drive them to closure.\nDebugging & root‑cause analysis – Strong waveform analysis, assertion debugging, and use of log‑extraction tools to isolate failures.\nVersion control & CI/CD – Experience with Git and Jenkins/GitLab CI for automated regression runs.\nDigital design fundamentals – Understanding of clock‑domain crossing, reset strategies, and low‑power design considerations for high‑speed blocks.\nEducation – B.E./B.Tech/M.Tech in Electrical/Computer Engineering or equivalent practical experience.\n\nSkills and Qualifications\n\nExperience – 5 to 6 Years of experience\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "RTL Design Engineer", "company": "Samsung", "location": "SSIR, Goldstone, Bangalore, India", "date_posted": "2026-05-18", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/SSIR-Goldstone-Bangalore-India/RTL-Design-Engineer_R117216", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.\nRole and Responsibilities\n\nAt least 6-10 years of experience in Low power RTL design, microarchitecture, synthesis, timing closure, power estimation. Should be proficient in Verilog/System Verilog.\nShould have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with SoC integration, optimization of Arithmetic units, Floating point data path design is a plus. \nShould have experience using ASIC design tools such as VCS, Verdi, Design Compiler, power estimation tools(such as Spyglass, PTPX). Knowledge of scripting languages (Shell, Perl, Python), C language is a plus.\nExperience with signing off RTL, synthesized netlist for Physical Design and eventually tape-out is desirable.\nHands on experience with AXI, APB bus protocols is a must. Experience with PCIe, UCIe protocols is a plus.\nPrior domain experience in Artificial Intelligence and/or Near Memory acceleration is a plus. \nExperience with hardware architecture exploration, performance modeling is desirable.\n*PPA - Power Performance, & Area analysis\n\nSkills and Qualifications\n\nExperience – 6 to 10 Years of experience\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "Sr. Evaluation Engineer", "company": "Analog Devices", "location": "India, Bangalore, Nova", "date_posted": "2026-05-18", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-Nova/Sr-Evaluation-Engineer_R262472", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).\n          \nSenior Design Evaluation Engineer\n\nAbout the Role\nADI’s Consumer Audio Business Unit is looking for a highly motivated and hands-on engineer with strong debugging skills and good understanding of silicon behavior. In this role, you will contribute to bring-up, validation, and characterization of mixed-signal ICs, working closely with cross-functional teams across hardware and software domains.\n\nYou will play a key role in executing validation plans, debugging silicon issues, and supporting product readiness, while growing your technical depth and contributing to team success.\n\nKey Responsibilities\n\nContribute to silicon bring-up, validation, and debug at block and system levels\nExecute validation plans and assist in defining test coverage\nPerform characterization measurements and support silicon performance evaluation\nDebug silicon issues and support root-cause analysis with cross-functional teams\nWork closely with embedded software teams to validate system functionality\nAssist in correlating simulation and silicon behavior\nDocument validation results and contribute to reports and engineering documentation\nSupport resolution of silicon issues impacting product readiness\n\nMinimum Qualifications:\nBSEE/MSEE in Electronics or equivalent degree with 5-8 years of relevant experience.\nExperience in pre and post silicon validation and characterization.\nHands on experience with lab equipment such as oscilloscopes, signal generators, power supplies and logic analyzers etc.\nExperience in validation of analog and mixed signal blocks such as ADC/DAC/amplifiers/Buck/LDO etc.\nWorking Knowledge of embedded systems programming.\nGood debugging and root-cause analysis skills across hardware and mixed-signal systems\nStrong written and verbal communication skills\n\nWhy You’ll Love Working at ADI\nAt Analog Devices, you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on professional growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world.\nYou'll have access to continuous learning opportunities and mentorship from industry experts. Join us and help create the technologies that bridge the physical and digital worlds, making a tangible difference in how people live, work, and connect.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "PD Layout expert", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-18", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010586", "is_hardware": true, "platform": "oracle", "jd_text": "We are at a pivotal moment where technology is rapidly evolving, and we have some exciting opportunities within our MCU organization that place us right at the center of this transformation.\n\n \n\nOur current work is focused on developing solutions for high-growth markets such as AI-driven data centers and emerging domains like humanoid systems. These areas are shaping the future of computing, automation, and intelligent systems, and offer a unique chance to work on cutting-edge technologies with real-world impact.\n\n \n\nIf you are passionate about solving complex technical challenges and want to contribute to innovations in these fast-growing segments, I encourage you to come forward and apply. This is an opportunity to be part of a journey that is not only technically rewarding but also strategically significant.\n\n  \n\nLooking forward to seeing many of you take this step.\n\nQualifications\nMinimum requirements:\n\n5+ years of relevant experience\n\nA thorough understanding of physical design aspects: Floorplan, Congestion analysis, DRC etc.\n\nPreferred qualifications:\n\nDefine and drive layout closure with in innovus and establish correlation with signoff. \n\nDriving SoC layout (FP), Power-grid design, IR drop validation ensuring balanced design utilization, development. \n\nCollaborate with timing, ATD, ESD and physical verification teams to ensure design intent is preserved.\n\nDrive ECO (Engineering Change Order) implementation for DRC and LVS fixes.\n\nDrive correct by construction approach (congestion, NDRs, early DRC/LVS) using advanced EDA tools and methodologies.\n\nDriving SoC layout (FP), Power-grid design, IR drop closure ensuring balanced design utilization\n\nScripting skills in TCL, Perl, or Python for flow automation.\n\nInterest in adopting AI/ML techniques along with flow automations\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Timing closure expert", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-18", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010588", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n In this position, you will be working on high-speed mixed-signal communication circuits using state-of-the art process technology, as well as be involved in the design of high performance digital circuits interfacing to leading edge analog circuitry as part of an overall system.\n\n Your responsibilities will include RTL coding, simulation, synthesis, timing closure, verification, evaluation, debugging of high-speed communication chips both at the circuit level and behavioral level.\n\n As a design engineer, you will prepare test methods and specifications, assist in preparation of application information, data sheets and demo boards. You will develop solutions to complex problems through assessment of various techniques and approaches. You will plan and organize work to ensure timely completion of many independent tasks with general instructions on routine tasks and with detailed instructions on new assignments.\n\n This position involves routine communication with a highly talented team of analog and digital design engineers to solve problems and present information as well as active participation in work groups, providing ideas and collaborative teamwork.\n\nQualifications\nMinimum requirements:\n\n5+ years of relevant experience\n\nA thorough understanding of timing closure aspects\n\nAbility to solve problems using a systematic approach\n\nPreferred qualifications:\n\nDefine and drive SOC timing closure strategy across the flow ( synthesis, placement, CTS and signoff)\n\nCollaborate with architecture, RTL, DFT  and verification teams to ensure design intent is preserved.\n\nDrive ECO (Engineering Change Order) implementation for functional and timing fixes.\n\nAnalyze and resolve PPA trade-offs using advanced EDA tools and methodologies.\n\nKnowledge of DFT (Design for Test) and basic layout aspects\n\nInterest in adopting AI/ML techniques along with flow automations\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Analog IC Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-18", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010714", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n  Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\nThis is a great opportunity to be part of an established team that's continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electronics, mobile computing and communications.\n\nWe are at a pivotal moment where technology is rapidly evolving, and we have some exciting opportunities within our MCU organization that place us right at the center of this transformation.\n\n Our current work is focused on developing solutions for high-growth markets such as AI-driven data centers and emerging domains like humanoid systems. These areas are shaping the future of computing, automation, and intelligent systems, and offer a unique chance to work on cutting-edge technologies with real-world impact.\n\n If you are passionate about solving complex technical challenges and want to contribute to innovations in these fast-growing segments, I encourage you to come forward and apply. This is an opportunity to be part of a journey that is not only technically rewarding but also strategically significant.\n\nOur Analog design team works on spectrum of IPs like BG, Supply monitors, LDO, ADC, Comparator, DAC, PLL, Oscillators etc. \n\nIn this role, responsibilities may include:\n\nLead an Analog IC design team with product ownership and responsibility from definition to release to manufacturing\n\nDirect, guide and participate in activities of a research or technical design function responsible for designing, developing, modifying and evaluating electronic parts, components, integrated circuits for a variety of applications\n\nMake assignments for team members, providing design guidance as needed, developing schedules and monitoring progress throughout the project\n\nEvaluate intermediate and final results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout\n\nCollaborate with Design Verification teams during the pre-PG phase of a project to ensure completion of all technical tasks before PG\n\nWork with systems engineers, application engineers and marketing to prepare product briefs, datasheets, application notes and assisting in the definition of the product to meet customer needs as well as contributing to roadmap formulation and new concept creation\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nInterface and lead discussions with the customer and/or TI field sales/field applications teams to understand customer designs, problems and support as required\n\nActively participate in hiring, developing and evaluating personnel to ensure efficient operation of the organization and growth of the individuals into leader\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in Electrical Engineering\n\n5+ years of relevant experience\n\nPreferred qualifications:\n\nStrong Analog design fundamentals\n\nExperience in silicon data analysis and debug\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Analog IC Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-18", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010808", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\nThis is a great opportunity to be part of an established team that's continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electronics, mobile computing and communications.\n\nWe are at a pivotal moment where technology is rapidly evolving, and we have some exciting opportunities within our MCU organization that place us right at the center of this transformation.\n\n Our current work is focused on developing solutions for high-growth markets such as AI-driven data centers and emerging domains like humanoid systems. These areas are shaping the future of computing, automation, and intelligent systems, and offer a unique chance to work on cutting-edge technologies with real-world impact.\n\n If you are passionate about solving complex technical challenges and want to contribute to innovations in these fast-growing segments, I encourage you to come forward and apply. This is an opportunity to be part of a journey that is not only technically rewarding but also strategically significant.\n\nOur Analog design team works on spectrum of IPs like BG, Supply monitors, LDO, ADC, Comparator, DAC, PLL, Oscillators etc. \n\nIn this role, responsibilities may include:\n\nLead an Analog IC design team with product ownership and responsibility from definition to release to manufacturing\n\nDirect, guide and participate in activities of a research or technical design function responsible for designing, developing, modifying and evaluating electronic parts, components, integrated circuits for a variety of applications\n\nMake assignments for team members, providing design guidance as needed, developing schedules and monitoring progress throughout the project\n\nEvaluate intermediate and final results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout\n\nCollaborate with Design Verification teams during the pre-PG phase of a project to ensure completion of all technical tasks before PG\n\nWork with systems engineers, application engineers and marketing to prepare product briefs, datasheets, application notes and assisting in the definition of the product to meet customer needs as well as contributing to roadmap formulation and new concept creation\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nInterface and lead discussions with the customer and/or TI field sales/field applications teams to understand customer designs, problems and support as required\n\nActively participate in hiring, developing and evaluating personnel to ensure efficient operation of the organization and growth of the individuals into leader\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in Electrical Engineering\n\n3-5 years of relevant experience\n\nPreferred qualifications:\n\nStrong Analog design fundamentals\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "PDK Development Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-18", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010626", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\nAbout The Team\n\n Here's your chance to work as part of a dynamic and challenging engineering team on the latest semiconductor technology within the Analog Technology Development team. The ATD Team creates world-class manufacturing technologies by Developing new process platforms with step-function improvements in performance and cost; Extending roadmap process technologies with new features, models and reduced costs; and Creating innovative, breakthrough technologies for new markets and new products.\n\nAbout The Role\n\nThis position provides an outstanding opportunity to contribute to be a primary differentiator for TI’s Analog and Embedded Process businesses in a key technical contributor role.  Through the integrative nature of this position, the understanding of the full picture (from early development to full production) as well as being a key technical contributor will prepare for multiple future opportunities.  Develop state-of-the-art Process Development Kit (PDK) environments for TI’s advanced semiconductor process technologies. Continually refine the procedures and techniques used to develop these environments to improve quality and product cycle time thus increasing profits.  The position also involves exposure to analog and mixed-signal design, process development, PDK and CAD tools. This job is an excellent opportunity to see the \"big picture\" of the Semiconductor Industry and eventually address project or platform management tasks.\n\nResponsibilities\n\nDeveloping TI PDK Kit capabilities and Quality assurance is the primary responsibility. Developing TI PDK design methodologies and integrating the PDK in Design flows is the core job function. EDA tool / Flow integration with PDK, documenting the PDK contents is also expected out of this role. Automation of the key capabilities for design productivity is add-on responsibility. Interfacing with process integration team, design team, EDA team, other members of PDK team is a day-to-day job function.\n\nQualifications\nQualifications:\n\nBachelor/Master degree in Electronics/VLSI Engineering or equivalent.\n\n2-5 year of work experience in PDK development, customization, integration and QA.\n\nKnowledge of deep sub-micron CMOS processes, device physics and layout design. Familiar with CMOS and/or BiCMOS Process/Fabrication Technologies. \n\nGood Knowledge of UNIX, PERL, Python programming languages.\n\nUnderstanding of Cadence design tools such as schematic capture and layout along with Cadence Skill programming knowledge is desired.\n\nWorking knowledge of revision control software (Synchronicity, Subversion, etc.)\n\nExcellent technical problem-solving skills.\n\nExcellent communication and presentation skills.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Lead Digital Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-18", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010806", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n In this position, you will be working on high-speed mixed-signal communication circuits using state-of-the art process technology, as well as be involved in the design of high performance digital circuits interfacing to leading edge analog circuitry as part of an overall system.\n\n Your responsibilities will include RTL coding, simulation, synthesis, timing closure, verification, evaluation, debugging of high-speed communication chips both at the circuit level and behavioral level.\n\n As a design engineer, you will prepare test methods and specifications, assist in preparation of application information, data sheets and demo boards. You will develop solutions to complex problems through assessment of various techniques and approaches. You will plan and organize work to ensure timely completion of many independent tasks with general instructions on routine tasks and with detailed instructions on new assignments.\n\n This position involves routine communication with a highly talented team of analog and digital design engineers to solve problems and present information as well as active participation in work groups, providing ideas and collaborative teamwork.", "jd_status": "source_unavailable"}, {"title": "PCIe design Architect", "company": "Broadcom", "location": "IND-Bangalore Electronic City - S1", "date_posted": "2026-05-17", "url": "https://broadcom.wd1.myworkdayjobs.com/External_Career/job/IND-Bangalore-Electronic-City---S1/PCIe-design-Architect_R026100", "is_hardware": true, "platform": "workday", "jd_text": "Please Note:\n1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)\n2. If you already have a Candidate Account, please Sign-In before you apply.\n\nJob Description:\n\n·        B.Tech/M.Tech in Electronics/VLSI Engineering with 18+ years of experience in VLSI design and architecture\n·        Strong fundamentals in digital ASIC design, micro-architecture, and best RTL coding methods\n·        Ability to understand product requirements and develop architectures for SoCs and PCIe subsystems\n·        Domain expertise in PCIe Gen6/7 and PIPE protocols\n·        Knowledge of AMBA and serial protocols, DMA, memory organization, processors, and Silicon bring-up sequences\n·        Strong design and Silicon debug skills\n·        Customer support and timely solutions to design problems\n·        Excellent communication and oratory skills\n·        Expertise in Synthesis, constraints, timing closure, and equivalence checks (Formality/Conformal)\n·        Experience in Lint/CDC/RDC tools\n\nBroadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.\n\nIf you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.", "jd_status": "stored"}, {"title": "DFT Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-15", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010578", "is_hardware": true, "platform": "oracle", "jd_text": "We are at a pivotal moment where technology is rapidly evolving, and we have some exciting opportunities within our MCU organization that place us right at the center of this transformation.\n\nOur current work is focused on developing solutions for high-growth markets such as AI-driven data centers and emerging domains like humanoid systems. These areas are shaping the future of computing, automation, and intelligent systems, and offer a unique chance to work on cutting-edge technologies with real-world impact.\n\n \n\nIf you are passionate about solving complex technical challenges and want to contribute to innovations in these fast-growing segments, I encourage you to come forward and apply. This is an opportunity to be part of a journey that is not only technically rewarding but also strategically significant.\n\n  \n\nLooking forward to seeing many of you take this step.\n\nQualifications\nTexas Instruments is seeking an experienced and highly skilled  DFT Lead Engineer to join our silicon design team. In this role, you will serve as a technical leader responsible for defining and driving DFT architecture, methodology, and execution for TI's next-generation semiconductor devices. You will play a pivotal role in mentoring junior engineers, influencing cross-functional design decisions, and ensuring silicon quality and testability at scale.\n\nThis is a high-impact role for someone who thrives at the intersection of design, test, and silicon engineering and is ready to take ownership of end-to-end DFT delivery on low cost MCU platforms.\n\n \n\nResponsibilities\n\nLead DFT architecture definition for complex SoC designs from concept to tape-out\n\nDrive DFT strategy including scan compression, MBIST, JTAG, and hierarchical test\n\nRepresent DFT in cross-functional design reviews and technical forums\n\nOwn scan insertion, ATPG, and MBIST implementation for low cost MCU.\n\nDefine fault coverage targets and ensure test quality standards are met\n\nLead resolution of complex ATPG, scan chain, and GLS violations\n\nInfluence design architecture decisions to improve testability and reduce test cost\n\nLead silicon bring-up including ATE correlation and debug\n\nDevelop and maintain robust DFT automation flows using Tcl, Perl, and Python\n\n \n\nQualifications\n\n5+ years of hands-on DFT engineering experience in the semiconductor industry\n\nExpert-level knowledge in scan insertion, ATPG, MBIST, fault simulation, and DFT sign-off\n\nAdvanced proficiency with Cadence tools — Modus (DFT), Genus (Synthesis), and Xcelium (Simulation)\n\nStrong expertise in Verilog and/or VHDL\n\nAdvanced scripting skills in Tcl, Perl, and/or Python for flow automation\n\nFamiliarity with low-power DFT methodologies including multi-voltage and clock-gated designs\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Design and Verification, MTS", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-05-15", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505313", "is_hardware": true, "platform": "oracle", "jd_text": "About Us\n\nAt onsemi, we help improve lives through silicon solutions every day. Our intelligent power and sensing technologies solve the world’s most complex challenges and lead the way in creating a safer, cleaner, and smarter world. Our group develops MCU and DSP systems as well as hardware accelerators that are used in a large variety of different products and markets.\n\nThe Role\n\nWe are looking for a Verification Manager with experience in the development of verification of MCU/DSP systems, to build and manage a new product verification team, chartered to create a series of mixed-signal compute products, and benchmark such systems for a variety of applications\n\nWhat You’ll Do\n\nDesign and Verification leadership: Form, lead and manage a mixed-signal IP / SoC verification team \n\nProblem solving & innovation: Identify novel solutions for meeting the verification intent with quality and efficiency\n\nTechnical guidance & mentoring: Guide world-wide teams in technical areas, from microarchitecture to productization\n\nInnovation: Define and create design methodology and design flow improvements for efficiency and robustness\n\nWhat Else You May Bring (Experience in some of the following areas is a plus)\n\nExperience in the design of CPU/MCU (sub)systems, compute functions and accelerators\n\nProgramming in Python for automation and C/C++ for embedded software\n\nDefinition of design intent: one or more of specification, microarchitecture, structural / functional assessments (CDC, test readiness), verification methods (formal / simulation), physical design (synthesis, timing/power optimisation), process technology aspects, etc.\n\nExperience in FPGA prototyping and performance testing\n\nAwareness in mixed-signal design \n\nOur commitment to you\n\nAs part of the onsemi team, you will have an opportunity to transform your tomorrow and operate in a diverse, inclusive, and socially responsible environment. If you’re passionate about shaping a better future, join us!\n\n#L1-MK1\n\nResponsibilities\nWhat You’ll Need\nB.Tech / M.Tech in Electrical Engineering or related technical field\nAt least 12 years of strong technical experience across any domain of VLSI design, with strong leadership and team management credentials\nAn extensive technical background in the verification and validation of semiconductor products or sub-components (IPs)\nMixed-signal verification expertise\nPower management verification expertise \nExperience with embedded CPUs, from a hardware and software/firmware perspective\nFunctional and performance verification of signal processing components or processing systems\nStrong communication skills\nAbility to define strategic actions, with appropriate design trade-off analyses\n#L1-LK1\n\nQualifications\nB.Tech / M.Tech in Electrical Engineering or related technical field\n \n#L1-LK1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Sr. Manager Functional Validation Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-05-15", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505331", "is_hardware": true, "platform": "oracle", "jd_text": "About Us\n\nAt onsemi, we help improve lives through silicon solutions every day. Our intelligent power and sensing technologies solve the world’s most complex challenges and lead the way in creating a safer, cleaner, and smarter world. Our group develops MCU and DSP systems as well as hardware accelerators that are used in a large variety of different products and markets.\n\nThe Role\n\nWe are looking for a Silicon Validation Manager with experience in the validation of embedded MCU/DSP systems, to build and manage a new SoC validation team. This team is chartered to deliver a series of differentiated mixed-signal compute products.\n\nWhat You’ll Do\n\nDesign leadership: Build and manage a team to cover pre/post silicon validation of a series of mixed-signal compute products\n\nProblem solving & innovation: Identify novel solutions for delivering differentiation performance and cost\n\nTechnical guidance & mentoring: Guide world-wide teams in technical areas, from architecture to productisation\n\nWhat Else You May Bring (Experience in some of the following areas is a plus)\n\nUnderstanding of signal processing components or processing systems\n\nAwareness in digital design & verification practices and requirements\n\nAwareness of standards and industry expectations for different end-market segments and application areas\n\nOur commitment to you\n\nAs part of the onsemi team, you will have an opportunity to transform your tomorrow and operate in a diverse, inclusive, and socially responsible environment. If you’re passionate about shaping a better future, join us!\n\n \n\n#L1-LK1\n\nResponsibilities\nWhat You’ll Need\n\nB.Tech / M.Tech in Electrical Engineering or related technical field\n\nAt least 12 years of strong technical pre- and post-silicon validation\n\nExperience with prototyping / emulation platforms\n\nExpertise in lab testing practices, test equipment and validation board design aspects\n\nExtensive experience in setting up validation automation for programmable mixed-signal compute products\n\nStrong leadership credentials\n\nAn extensive technical background in the development of semiconductor products or sub-components (IPs)\n\nExperience with mixed-signal validation and product validation requirements\n\nExperience with product life-cycle validation management  \n\nExposure to Safety and industrial product validation practices and standards\n\nStrong communication skills\n\nAbility to define strategic actions, with appropriate design trade-off analyses\n\n#L1-LK1\n\nQualifications\nB.Tech / M.Tech in Electrical Engineering or related technical field\n\n \n\n#L1-LK1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "DFT Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-15", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010579", "is_hardware": true, "platform": "oracle", "jd_text": "We are at a pivotal moment where technology is rapidly evolving, and we have some exciting opportunities within our MCU organization that place us right at the center of this transformation.\n\nOur current work is focused on developing solutions for high-growth markets such as AI-driven data centers and emerging domains like humanoid systems. These areas are shaping the future of computing, automation, and intelligent systems, and offer a unique chance to work on cutting-edge technologies with real-world impact.\n\n \n\nIf you are passionate about solving complex technical challenges and want to contribute to innovations in these fast-growing segments, I encourage you to come forward and apply. This is an opportunity to be part of a journey that is not only technically rewarding but also strategically significant.\n\n  \n\nLooking forward to seeing many of you take this step.\n\nQualifications\nTexas Instruments is seeking a talented and passionate DFT Engineer to join our silicon design team. In this role, you will be responsible for ensuring the testability and quality of TI's next-generation semiconductor devices. You will collaborate with cross-functional teams spanning design, physical design, and product engineering to deliver high-quality, silicon-proven test solutions.\n\nThis is an exciting opportunity to work on low cost MCUs using industry-leading EDA tools in a collaborative and innovation-driven environment.\n\n \n\nResponsibilities\n\nDevelop and execute DFT architecture and scan insertion strategies for low cost MCUs\n\nImplement and validate ATPG test patterns to achieve automotive grade fault coverage\n\nDesign and deploy Memory BIST (MBIST) solutions for embedded memories across SoC designs\n\nEnsure DFT rule compliance throughout the design flow from RTL to tape-out\n\nDebug and resolve complex ATPG, scan, and Gate-Level Simulation (GLS) violations\n\nPerform DFT sign-off checks and ensure test coverage meets product quality targets\n\nDevelop and maintain Tcl, Perl, and Python scripts to automate DFT flows and improve efficiency\n\nContinuously improve DFT methodologies, flows, and best practices within the team\n\n \n\nQualification\n\nExperience with scan compression techniques (e.g., Modus EDT/IJTAG)\n\nFamiliarity with IEEE 1149.1 (JTAG) / IEEE 1500 standards\n\nExposure to low-power DFT methodologies (clock gating, power domain testing)\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Sr Synthesis and Implementation Engineer", "company": "NXP", "location": "Hyderabad", "date_posted": "2026-05-15", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Hyderabad/Sr-Synthesis-and-Implementation-Engineer_R-10063207", "is_hardware": true, "platform": "workday", "jd_text": "We are seeking highly motivated Synthesis & Front-End Implementation Engineer to join our dynamic AI NPU team. In this role, you will be crucial in translating RTL designs into optimized gate-level netlists, ensuring performance, power, and area targets are met for complex IP blocks.\n\nJob Responsibilities\n\nAs a Synthesis & Front-End Implementation Engineer, your responsibilities will include:\n\n* Performing logical and physical synthesis of RTL designs for various digital blocks and sub-systems, including hierarchical synthesis methodologies.\n* Developing and implementing robust timing constraints (SDC) to achieve target frequencies and optimize design performance.\n* Conducting STA, identifying critical paths, and collaborating with design teams for timing closure.\n* Executing formal verification (LEC) to ensure functional equivalency between RTL and synthesized netlists.\n* Analyzing and optimizing power consumption at the front-end stage, utilizing power analysis tools and techniques.\n* Performing area estimation and optimization to meet aggressive PPA requirements.\n* Collaborating closely with RTL designers, DFT engineers, and physical design engineers to ensure seamless integration and hand-off.\n* Developing and maintaining automation scripts (Tcl, Python, Perl) for synthesis flows and design analysis.\n* Evaluating and integrating new CAD tools and methodologies to improve efficiency and design quality.\n* Documenting design constraints, methodologies, and analysis results thoroughly.\n\nJob Qualifications\n\nTo be successful in this role, you should possess following qualifications:\n\n* Bachelor's or Master's degree in VLSI or Electronics Engineering or a related field.\n* 5+ years of relevant experience in digital ASIC/SoC design, with a focus on synthesis and front-end implementation.\n* Proficiency with industry-standard synthesis tools (e.g., Synopsys DC/FC or Cadence Genus).\n* Strong experience with Physical synthesis and floorplanning aspects is a plus.\n* Strong understanding of static timing analysis (STA) concepts and tool (e.g., Synopsys PrimeTime or Cdence Tempus).\n* Experience with formal verification tools (e.g., Synopsys Formality, Cadence Conformal (LEC)).\n* Understanding of upf, low-power design techniques and power analysis concepts.\n* Solid knowledge of Verilog/System verilog for digital design.\n* Familiarity with scripting languages (Tcl, Python, Perl) for automation.\n* Knowledge of DFT (Design for Testability) principles is a plus.\n* Excellent problem-solving skills and attention to detail.\n* Strong communication and interpersonal skills, with the ability to work effectively in a collaborative team environment across multiple time zones.\n\nMore information about NXP in India...\n\n#LI-29f4", "jd_status": "stored"}, {"title": "Digital Design Verification, Principal Engineer / Architect - 17323", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-05-14", "url": "https://careers.synopsys.com/job/bengaluru/digital-design-verification-principal-engineer-architect-17323/44408/95090864144", "is_hardware": true, "platform": "talentbrew", "jd_text": "We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent over a decade in verification, and you have learned that the difference between a verification flow that works and one that collapses under pressure is usually a decision made at the architecture stage. You are the engineer who catches that decision before it becomes technical debt. You think in systems, not scripts. You know that building verification infrastructure is not about assembling tools, it is about creating an environment where teams can move fast without breaking things.\nYou have built verification environments from scratch using VCS, Verdi, VMS Execution Manager, and UVM, and you know where each tool shines and where it does not.\nWhat You'll Be Doing\nArchitect and implement unified verification flows for Synopsys digital IP products using VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs\nBuild scalable verification infrastructure from the ground up, designing environments that support complex IP and SoC projects across global teams\nDefine, document, and propagate verification methodologies and best practices that become the standard across Synopsys digital IP projects\nLead and mentor verification engineers, providing technical guidance on UVM, SystemVerilog, flow optimization, and debugging strategies\nDrive technical initiatives independently, managing high-impact assignments from concept through deployment and adoption\nCollaborate with EDA tool development teams to influence product roadmaps, provide feedback, and optimize verification workflows for real-world use cases\nTroubleshoot and refine verification processes for internal teams and customers, diagnosing flow bottlenecks and delivering solutions that stick\nThe Impact You Will Have\nEstablish verification methodology standards that accelerate time-to-market for Synopsys digital IP and SoC products\nEnable global verification teams to deliver higher quality results faster by providing robust, reusable flows and infrastructure\nShape the verification strategy for next-generation Synopsys IP offerings, directly influencing product quality and customer satisfaction\nReduce verification cycle time and resource overhead across multiple projects by standardizing tooling and best practices\nDevelop the next generation of verification engineers at Synopsys, building a culture of technical excellence and continuous learning\nInfluence the evolution of Synopsys EDA tools by providing critical, field-tested feedback to product teams\nStrengthen Synopsys' leadership position in semiconductor verification by driving adoption of cutting-edge methodologies across the organization\nWhat You'll Need\n10+ years of hands-on experience in IP or SoC verification, with a proven track record of leading technical initiatives and delivering complex verification environments\nDeep expertise with Synopsys verification tools including VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and Verification IP (VIP)\nStrong programming and scripting skills in SystemVerilog, UVM, Tcl, and Python for automation and flow development\nDemonstrated ability to architect verification flows and infrastructure for complex digital designs, from initial concept to production deployment\nBachelor's degree in Electronics, Electrical, or Computer Engineering; advanced degrees are a plus\nExperience managing multiple technical projects independently, balancing priorities and delivering high-quality results on schedule\nAbility to document and communicate technical methodologies clearly across global, cross-functional teams\nWho You Are\nYou can explain a complex verification tradeoff to a product manager in two sentences without losing the nuance, and then turn around and debug a UVM testbench with a junior engineer\nYou take ownership of problems that do not have clear owners, and you see them through to resolution even when it means coordinating across time zones and teams\nYou push back when a methodology does not make sense for the use case, and you do it with data and a better alternative, not just criticism\nYou are organized enough to manage five verification projects at once and strategic enough to know which one needs your attention today\nYou teach by showing, not just telling, and you measure your success by how much your team grows, not just what you deliver personally\nYou stay current with verification trends and tools, and you bring new ideas to the table backed by practical understanding of what will actually work in production\nThe Team You'll Be Part Of\nYou will be a core member of the newly established Digital IP Verification Methodology (COE) team, a group of forward-thinking engineers dedicated to advancing verification excellence at Synopsys. The team collaborates across global sites, driving innovation in methodology, tool integration, and best practices. Together, you will shape the future of digital IP verification, enabling Synopsys and its customers to deliver world-class silicon solutions.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Post Silicon Validation Manager", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-05-13T10:25:00+00:00", "url": "https://global-external-amd.icims.com/jobs/75217/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Roles & Responsibilities: Take responsibility for the Post silicon validation scope and plan for IPs like HSIO, Memory, RAS, Cores, LSIO, Power Management, Multimedia etc. Ensure robust planning at the pre-silicon stage, working with DV or Emulation teams and support the Leads and engineers in framing the relevant test cases Support the team with the right infrastructure at the right time Define the scaling of the teams for Capability and Capacity in line with the BU’s growth Bigger picture planning for roadmaps and process improvements Create a cohesive culture of openness, diversity, technical growth for the team members Act with great resolve during testing times of critical issues, milestones, customer escalations and BU related internal changes Exhibit strong leadership qualities to take the team forward towards growth and achieving the mission of the company Exhibit great technical depth in the post silicon validation to take the right technical decisions for the team Individual requirements: Highly skilled engineering professional with over 15 years of experience. Solid experience in handling high performing, dynamic and a strong technical team. Solid Experience and Knowledge in the post silicon validation of x86 IPs like Cores, Memory, RAS, HSIO. Solid experience in handling the growth charter for growing teams and embrace changes with ease and grace Adept in calling out risks while anticipating issues and coming up with appropriate mitigation plans Experienced in working with the Enablement Manager and Leads, Program Managers, Product Managers, BIOS/FW Managers and other cross functional stakeholders and create a robust alignment setup while running execution. Preferred experience working with cross-functional teams like DV/Silicon Designers/Pre-silicon/Platform/BIOS/FW/ SW. Experience in High Speed I/Os like PCIe (preferably Gen4 and above), Memory (DDR4/DDR5.LPDDR4/LPDDR5), USB4.0/3.2/3.1, USB PD, USB Type C, Display interfaces and Ethernet and high-speed interconnects. Experience in Power Management, Power Delivery, and Power Measurements. Hands-on high speed and board measurement techniques in using high end equipment like Oscilloscopes, Logic Analyzers, Debugger tools, Raspberry PI, Network analyzers, etc. Preferred experience with scripting using TCL, Python Excellent communication, collaboration, articulation, upleveling to senior management and team playing skills. Key responsibilities: Ensuring the team delivers error free and timely delivery of test cases and test reports, meeting or beating the program commitment Synergize with the Pre-silicon and DV teams and other stakeholders for proper interception of milestones and risk callouts. Actively participate in discussions with cross-functional teams in defining and refining test plans and guiding the team for the right path. Be on top of all issues pertinent to Debug & Triage of any functional issues specific across the entire validation cycle Drive meetings for issue closures and actively track schedules and milestone quality metrics Ensure the Best in class Documentation and collateral delivery from the team. Engage with the QA Validation and CAE teams for seamless handing over of test plans or reports, as relevant. #LI-NS2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Robotics Software Usecases Validation Engineer ", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-05-13T06:24:00+00:00", "url": "https://global-external-amd.icims.com/jobs/84985/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Robotics Software Usecases Validation Engineer About the Role Join AMD’s PAVS team as a Robotics Usecases Validation Engineer where you will Validate and Execute diverse Robotics platforms, variants and customer usecases for advanced robotics systems across software, hardware, and integrated platforms. Your work will ensure safety, reliability, and performance through rigorous testing in simulation, Gazebo, Isaac sim, SIL/HIL environments, and real-world deployments. Key Responsibilities Validation Strategy & Usecases : Define Usecases and execute validation plans for robotics software stacks (perception, planning, control) and hardware subsystems. Automation & Frameworks: Develop automated test suites for ROS2 nodes, navigation stack (Nav2), and fleet APIs using Python/C++, pytest, gtest/gmock. Simulation & Scenario Testing: Build simulation environments (Gazebo/Ignition, Isaac Sim) for warehouse layouts; author scenarios for obstacle avoidance, dynamic traffic, and multi-robot coordination. SIL/HIL Validation: Set up Software-in-the-Loop and Hardware-in-the-Loop rigs for AMR controllers, LiDAR emulators, and safety sensors; automate provisioning and logging. Sensor QA: Validate LiDAR, depth cameras, IMU, wheel encoders, and odometry accuracy under varying conditions. Navigation & Fleet QA: Test SLAM, localization robustness, path planning, and fleet orchestration (traffic management, task allocation, VDA5050 compliance). Safety & Compliance: Execute safety protocols for AMRs (emergency stop, zone monitoring, speed limits) aligned with ISO 3691-4, ISO 13849, ANSI/RIA R15.06. Performance & Reliability: Measure latency, throughput, and stability under high-load scenarios; validate battery management and docking behaviors. CI/CD Integration: Embed automated tests into pipelines for continuous validation; monitor KPIs like defect escape rate and scenario coverage. Leadership: Act as a strong individual contributor and mentor for robotics validation teams; collaborate with cross-functional stakeholders to ensure customer experience is prioritized. Required Qualifications 4 to 7 years in QA/Validation, with 4+ years in robotics or AMR systems. Strong Python for automation and C++ for ROS2 integration. Hands-on experience with ROS2, Nav2 stack, colcon, and simulation tools (Gazebo/Ignition, Isaac Sim). Expertise in LiDAR, depth cameras, IMU, odometry, and sensor calibration. Familiarity with fleet management systems, traffic control, and VDA5050 protocol. CI/CD experience with GitHub Actions/GitLab CI/Jenkins; Docker-based test environments. Knowledge of functional safety standards for mobile robots (ISO 3691-4, ISO 13849). Preferred Skills Multi-robot coordination, dynamic obstacle handling, and SLAM algorithms. Robotics AMR safety PLCs, zone scanners, and emergency stop circuits. Warehouse automation workflows, WMS integration, and OPC-UA. Performance benchmarking, reliability testing, and telemetry dashboards. Success Metrics Automated coverage of navigation and fleet scenarios. Reduction in field defect escape rate. Stability and reliability under multi-robot deployments. Compliance with safety standards and successful audits. 🎓 Academic Credentials: Bachelor’s or Master’s degree in Robotics, Electronics, Mechatronics, Computer Science, or a related field. #LI-NR1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Sr Staff Design Engineer", "company": "Lattice", "location": "LPQ", "date_posted": "2026-05-13", "url": "https://latticesemi.wd5.myworkdayjobs.com/latticesemiconductorscareers/job/LPQ/Sr-Staff-Design-Engineer_R-100459", "is_hardware": true, "platform": "workday", "jd_text": "Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\n\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\n\nLattice Semiconductor is seeking a Sr. Staff Physical Design Engineer to join the HW design team focused on IP design and full chip integration.  This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn, innovate and grow.\n\nRole specifics:\nThis is a full-time individual contributor position located in Pune, India.\n\nThe qualified candidate will be implementing and lead RTL to GDSII flow for complex design.\n\nThe qualified candidate will work and lead one or more aspects of physical design including place & route, CTS, routing, floorplanning, powerplanning, timing and physical signoff\n\nThe qualified candidate is expected to have experience in physical design signoff checks, including timing closure, EM/RV and physical verification (DRC, LVS).\n\nThe qualified candidate is expected to drive efficiency and quality of physical design flow and methodology and work together with internal EDA team and external tool vendors \n\nThe qualified candidate is expected to have scripting knowledge or perl /python etc to improve design efficiency and methodology development.\n\nCollaborate with RTL, DFT , verification and full chip teams to ensure robust design implementation.\n\nThe successful candidate will be open and willing to both (a) teach best-known-methods to an existing FPGA team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and a open-minded student.\n\nAccountabilities:\nServe as a key contributor to FPGA design efforts.\n\nDrive physical design closure of key ASIC blocks & full chip and bring best-in-class methodologies to achieve best power, performance, and area.\n\nEnsuring design quality through all physical design quality checks and signoff.\n\nDevelop strong relationships with worldwide teams.\n\nMentor and develop strong partners and colleagues.\n\nOccasional travel as needed.\n\nRequired Skills:\nBS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent.\n\n12+ years of experience in driving physical design activities of ASIC blocks and full chip.\n\nMust have experience of multiple tapeouts\n\nExperience on working with industry standard physical design tools including Innovus, Genus, Tempus, voltus, calibre, conformal etc.\n\nIndependent worker with demonstrated problem-solving abilities.\n\nProven ability to work with multiple groups across different sites and time zones\n\nLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.\n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.\n\nLattice\nFeel the energy.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. \n\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.", "jd_status": "stored"}, {"title": "Senior Staff Application Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-05-13", "url": "https://careers.synopsys.com/job/bengaluru/senior-staff-application-engineer/44408/95049838704", "is_hardware": true, "platform": "talentbrew", "jd_text": "Sr Staff Applications Engineer\nWe Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nYou are a highly skilled engineer with a passion for technology and problem solving.  With over 8 years of experience in the field, you excel at providing technical consultation and guidance to global customers, ensuring the seamless integration and optimal performance of Synopsys Interface IP solutions in SOC systems. Your expertise in high speed protocols, combined with your proficiency in AMBA bus interfaces and ASIC design tools, makes you an invaluable asset to any team. Your excellent communication skills and ability to work effectively with a diverse team of engineers worldwide set you apart as a leader in your field. You thrive in dynamic environments, where your problem-solving abilities and technical acumen can make a significant impact on customer success and product innovation.\nWhat You’ll Be Doing:\nProviding post-sales technical consultation for configuration, integration, simulation, and post-silicon bring-up of AMBA, I3C and other interface IPs.\nWorking with the latest AMBA protocols\nCollaborating with a global team of engineers to deliver expert product knowledge to Synopsys customers.\nConducting detailed technical presentations on the configuration and integration of Synopsys IPs.\nCreating collateral and authoring documentation to improve user experience.\nMaking presentations to customers on Synopsys IP offerings.\nThe Impact You Will Have:\nEnhancing customer satisfaction by providing expert technical support and guidance.\nEnsuring the successful integration and deployment of Synopsys IP solutions in customer projects.\nContributing to the continuous improvement of Synopsys IPs through customer feedback and collaboration.\nDriving innovation by working with the latest high-speed protocols and technologies.\nUtilizing latest AI tools and processes to automate workflows and improve efficiencies\nWhat You’ll Need:\nPrior experience in high-speed protocols such as DDR, PCIe, or Ethernet.\nExperience with AMBA bus interfaces, including AXI.\nProficiency with UNIX and HDL (Verilog/VHDL).\nStrong understanding of ASIC design flow.\nBachelor's or Master's degree in Electronics Engineering or a related field, with a focus on VLSI design.\n5-15 years of relevant experience\nExperience or exposure to AI tools and workflows\nWho You Are:\nExcellent communicator with strong English skills.\nDetail-oriented and highly organized.\nCollaborative team player with a global mindset.\nAdaptable and able to thrive in dynamic environments.\nProactive problem solver with a customer-focused approach.\nThe Team You’ll Be A Part Of:\nYou will be part of a diverse and dynamic global team of engineers dedicated to providing technical support and expertise to Synopsys customers worldwide. This team is focused on delivering high-quality IP solutions and ensuring customer success through collaboration, innovation, and continuous improvement.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Principal Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-05-12", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Design-Engineer_R54526", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Description\nThe Principal AMS Design Engineer will be a key contributor to the HBM PHY team, responsible for the design and development of high-speed analog and mixed-signal circuits for next-generation HBM PHY products. This role includes detailed circuit design based on system and micro-architecture requirements, leadership in analog and layout design reviews, and close collaboration with cross‑functional teams including digital, layout, packaging, and SI/PI. The engineer will take ownership of project execution across development phases and play a critical role in driving new micro‑architecture innovations to meet aggressive performance, power, and area targets for advanced HBM PHY designs.\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "SoC  Validation Engineer, Amazon Devices", "company": "Amazon", "location": "Bengaluru, Karnataka, IND", "date_posted": "2026-05-12", "url": "https://www.amazon.jobs/en/jobs/10417469/soc-validation-engineer-amazon-devices", "is_hardware": true, "platform": "amazon", "jd_text": "The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for an SoC Emulation Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience     through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at   edge.\n\nWork hard. Have fun. Make history.\n\nAs an SoC Validation Engineer, you will be responsible for enabling the pre-silicon and post-silicon validation  verification of next generation SoCs on multiple platforms such as emulation, prototyping and early silicon. You will develop and execute test plans, design test environments and help build emulation and prototype models while working closely with architects, RTL designers, SoC and software development  teams.\n\nIn this role, you will:\n\n- Develop/review subsystem testplans and help create the SoC Verification and Validation plan.\n- Implement tests and scenarios on multiple platforms.\n- Develop and deploy baremetal drivers to configure SoC subsystems\n\nPre-silicon activities:\n- Develop test benches, transactors and monitors to work with Emulation systems (ex. Zebu) and Prototyping systems (ex. HAPs)\n- Develop infrastructure for build and runtime of SoC emulation and prototyping models using vendor tools and Providing training, failure debug support and improving debug capabilities\n- Maximize efficient utilization of the platforms through automation and other innovations\n- Debug and resolve issues, pioneer and deploy new platform capabilities\n\nPost-silicon activities:\n- Continue pre-silicon efforts to seamlessly intersect and bring up early silicon\n- Port emulation and prototyping testplans to post-silicon activities\n- Write tests and infrastructure to ensure Performant and Functional compliance of Silicon\n\nKey job responsibilities\nAs an SoC Validation Engineer, you will be responsible for enabling the pre-silicon and post-silicon validation  verification of next generation SoCs on multiple platforms such as emulation, prototyping and early silicon. You will develop and execute test plans, design test environments and help build emulation and prototype models while working closely with architects, RTL designers, SoC and software development  teams.\n\nBasic qualifications\n- Bachelor's degree in Electrical Engineering or a related field\n- Experience with post-silicon validation\n- Experience with SOC bring-up and post-silicon validation\n- Knowledge of software system interaction with hardware equipment\n- Very strong problem solving, debug and analysis, and automation skills\n- Strong programming skills (assembly, C, Perl/Python)\n- Firsthand experience with silicon bringup, complex system debug, or bare-metal programming.\n\nPreferred qualifications\n- Master's degree in Electrical or Communications Engineering or a related field\n- Experience in a full development cycle from pre-silicon verification to silicon bringup\n- Experience with ARM and various DSP ISA\n- Experience with SOC fabrics, memory controllers, and SOC peripherals\n- Experience with machine learning, computer vision or robotics\n- Excellence in technical communication with peers and non-technical cohorts\n\nOur inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "jd_status": "stored"}, {"title": "Design Verification Engineer, Silicon and Systems Group", "company": "Amazon", "location": "Bengaluru, Karnataka, IND", "date_posted": "2026-05-12", "url": "https://www.amazon.jobs/en/jobs/10417471/design-verification-engineer-silicon-and-systems-group", "is_hardware": true, "platform": "amazon", "jd_text": "As a Design Verification (DV) Engineer, you will be part of an advanced architecture team that is exploring new hardware designs to improve our devices. In this role, you will be responsible for defining the verification methodology and implementing the corresponding test plan for advanced functional blocks. You will participate in the design verification and bring-up of such blocks by writing relevant assertions, debugging code, test benches, test harnesses, and otherwise interacting with the extended team.\n\nYou will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware Engineering, and Software Engineering, to architect and implement complex functional block that enable development of world-class hardware devices. In this role, you will:\n\n· Design world class hardware and software\n· Communicate and work with team members across multiple disciplines\n· Deliver detailed test plans for verification of complex digital design blocks by working with design engineers and architects\n· Create and enhance constrained-random verification environments using SystemVerilog and UVM\n· Identify and write all types of coverage measures for stimulus and corner-cases.\n· Debug tests with design engineers to deliver functionally correct design blocks.\n· Close coverage measures to identify verification holes and to show progress towards tape-out.\n· Participate in test plan and coverage reviews\n·  Integrated 3rd party IPs/VIPs and transactors\n· Perform IP/SOC bringup in simulation, emulation and prototyping environments\n\nThe ideal candidate should have experience with RTL development environments, fluency in modern hardware description languages and verification methodologies. They should have experience verifying complex IP blocks from scratch that have successfully been integrated in SOCs or other such silicon that have been productized in consumer devices. We are looking for a self-driven individual who can work with architects, HW and SW developers and can quickly resolve blocking issues.\n\nBasic qualifications\n- Bachelor's degree in Electrical Engineering or a related field\n- Experience using multiple verification platforms: UVM test bench, FPGA, emulator, software environments, and system testing\n- Experience with test plan development, building the necessary test bench infrastructure, developing tests and verifying the design\n- Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills\n- Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing\n- Experience with industry standard tools and scripting languages (Python or Perl) for automation\n- Experience in English-language communication skills, both written and verbal\n- 7+ years or more of practical semiconductor design verification including System Verilog, UVM, assertions and coverage driven verification.\n- Experience defining verification methodologies\n- Experience with writing directed/constrained-random tests\n\nPreferred qualifications\n- Master's degree in Electrical or Communications Engineering or a related field\n- Experience in system-level debugging\n- Knowledge of SoC architecture\n- Experience with boot-up and bare metal flows for CPU cores\n- Strong programming skills in C and scripting skills in Python and/or Perl\n- Experience with high performance industry standard IO interfaces like AMBA AXI4, USB, MIPI etc.\n- Experience with PCIE Experience with formal verification\n- Experience with transaction level modeling Knowledge of FPGA and emulation platforms\n\nOur inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "jd_status": "stored"}, {"title": "Staff Electrical Engineer", "company": "Skyworks", "location": "Bangalore, KA, IND", "date_posted": "2026-05-12", "url": "https://careers.skyworksinc.com/job-invite/77303/", "is_hardware": true, "platform": "successfactors", "jd_text": "Division: RMI Engineering \n\nEmployment Status: Exempt\n\nSalary Grade: 110\n\nShift: \n\nRequisition ID: 77303 \n\nPlease be aware that if you are selected to formally interview for an internal position you will be required to notify your current manager.  Please refer to the Employee Transfers Guidelines posted on Skylink.\n\nDescription\n\nWe are seeking a Staff RF and/or Analog Design Engineer to design, integrate, and characterize high‑performance RF and analog circuits for next‑generation products. This role requires deep hands‑on expertise, strong system‑level understanding, and the ability to technically perform complex mixed‑signal designs from concept through silicon qualification and production.\n\nYou will work closely with digital, layout, validation, firmware, and product teams to deliver robust, manufacturable solutions for demanding RF and analog applications.\n\nResponsibilities\n\nRF & Analog Design\n\nArchitect, design, and simulate RF and/or analog circuit blocks, including:\n\nLNAs, mixers, VCOs/PLLs\n\nData converters (ADCs/DACs)\n\nBias generation, bandgap references, LDOs\n\nBaseband amplifiers and filters\n\nTranslate system‑level requirements (noise, gain, linearity, power, phase noise) into robust circuit implementations\n\nPerform detailed schematic design, simulation, and optimization across PVT corners\n\nSystem & Architecture Contribution\n\nCollaborate with system architects to define RF signal chains and analog subsystems\n\nDrive tradeoff analysis between performance, power, area, and cost\n\nSupport RF budgeting (NF, IP3, phase noise, jitter, spur analysis)\n\nSilicon Implementation & Signoff\n\nWork closely with layout engineers on:\n\nFloor planning\n\nSensitive routing and matching\n\nEM, IR, and substrate coupling considerations\n\nOwn or support block‑level and top‑level signoff:\n\nAC/DC performance\n\nNoise and linearity\n\nStability and yield margin\n\nValidation & Debug\n\nInvolved in silicon bring‑up, lab characterization, and debug\n\nCorrelate measurement results with simulation\n\nIdentify root causes and drive fixes for silicon issues\n\nSupport yield improvement and production ramp\n\nRequired Experience and Skills\n\nBachelor’s, Master’s, or PhD in Electrical Engineering or related field\n\nTypically 6+ for Masters or PhD, 8+ years for Bachelors of hands‑on RF and/or analog IC design experience\n\nProven track record of tape‑out ownership and silicon success\n\nStrong understanding of:\n\nRF fundamentals (noise, linearity, matching, phase noise)\n\nAnalog circuit design techniques\n\nCMOS/BiCMOS device physics\n\nExperience with industry tools:\n\nCadence Virtuoso, SpectreRF, ADS, EMX or equivalent\n\nComfortable working across process nodes and foundries\n\nDesired Experience and Skills\n\nStrong DSP fundamentals\n\nMixed‑signal integration experience (RF + digital SoC)\n\nHigh‑speed or precision analog experience\n\nExperience supporting volume production\n\nSoft Skills & Mindset\n\nStrong problem‑solving and debugging skills\n\nAbility to communicate complex technical concepts clearly\n\nOwnership mindset with attention to detail\n\nComfortable influencing without formal authority\n\nCollaborative and pragmatic approach to engineering tradeoffs\n\n#LI-CB1\n\nReferral Bonus Program Reward (if eligible): Rs200,000.00", "jd_status": "stored"}, {"title": "Senior Principal - DFT", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-05-12", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505310", "is_hardware": true, "platform": "oracle", "jd_text": "About Us\n\nAt onsemi, we help improve lives through silicon solutions every day. Our intelligent power and sensing technologies solve the world’s most complex challenges and lead the way in creating a safer, cleaner, and smarter world. Our group develops MCU and DSP systems as well as hardware accelerators that are used in a large variety of different products and markets.\n\nThe Role\n\nWe are looking for a Senior Design For Test (DFT) Staff Engineer with experience in handling design for test of embedded MCU/DSP & mixed-signal systems, to build products with the right quality and costs.\n\nWhat You’ll Do\n\nDefine and implement design strategies to maximize test coverage across a breadth of products \n\nProblem solving & innovation: Identify novel solutions for optimizing test cost and coverage\n\nTechnical guidance & mentoring: Guide world-wide teams in technical areas of test strategies all the way to productization\n\n#LI-MK1\n\nQualifications\nWhat You’ll Need\nB.Tech / M.Tech in Electrical Engineering or related technical field\nAt least 10 years of strong technical experience in VLSI design for test, with specific emphasis on mixed-signal products\nStrong technical leadership on state of the art test methods\nAn extensive technical background within the development of semiconductor products or sub-components (IPs)\nExperience with embedded CPUs, from a hardware and software/firmware perspective\nStrong communication skills\nAbility to define strategic actions, with appropriate design trade-off analyses\nWhat Else You May Bring (Experience in some of the following areas is a plus)\nExperience in the design of test for digital and mixed-signal circuits\nAwareness of and experience with testers and tester requirements\nDefinition of design intent in one or more of test intent definition, design vs. test-cost trade-of analysis, EDA tool solutions, analog parameter testing, etc.\nAwareness in analog design practices and requirements\n#LI-MK1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Physical Design Manager", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-05-12", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505311", "is_hardware": true, "platform": "oracle", "jd_text": "About Us\n\nAt onsemi, we help improve lives through silicon solutions every day. Our intelligent power and sensing technologies solve the world’s most complex challenges and lead the way in creating a safer, cleaner, and smarter world. Our group develops MCU and DSP systems as well as hardware accelerators that are used in a large variety of different products and markets.\n\nThe Role\n\nWe are looking for a Physical Design Manager with experience in the implementation of embedded MCU/DSP systems, to build and manage a new analog design team. This team is chartered to deliver a series of differentiated mixed-signal compute products.\n\nWhat You’ll Do\n\nDesign leadership: Build and manage a team to implement and deliver a series of mixed-signal compute products\n\nProblem solving & innovation: Identify novel solutions for delivering differentiation performance and cost\n\nTechnical guidance & mentoring: Guide world-wide teams in technical areas, from architecture to productization\n\n#LI-MK1\n\nQualifications\nWhat You’ll Need\nB.Tech / M.Tech in Electrical Engineering or related technical field\nAt least 12 years of strong technical experience physical design and related areas – timing constraints, synthesis, test implementation, design optimisation, power management, timing closure, electrical / physical verification and packaging\nStrong leadership credentials\nAn extensive technical background in the development of semiconductor products or sub-components (IPs)\nExperience with mixed-signal integration \nStrong communication skills\nAbility to define strategic actions, with appropriate design trade-off analyses\nWhat Else You May Bring (Experience in some of the following areas is a plus)\nUnderstanding of signal processing components or processing systems\nAwareness in digital design & verification practices and requirements\nAnalog circuit design, design modeling, IP characterization, etc.\n#LI-MK1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "FPGA Prototyping Applications Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-05-12", "url": "https://careers.synopsys.com/job/bengaluru/fpga-prototyping-applications-engineer/44408/95049838656", "is_hardware": true, "platform": "talentbrew", "jd_text": "Alternate Job Titles\nFPGA Prototyping Applications Engineer\nSenior Staff Application Engineer, Verification\nHAPS Prototyping Solutions Engineer\nSenior Technical Applications Engineer, FPGA-Based Prototyping\nField Applications Engineer, FPGA Prototyping\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\n\nYou Are\nYou are at your best when the work is real—when the design is enormous, the schedule is unforgiving, and “good enough” isn’t good enough because someone needs the prototype to boot, run, and reveal the truth. You thrive in the messy middle between theory and reality, where success comes from making smart tradeoffs, staying relentlessly organized, and refusing to let details slip through the cracks. You don’t romanticize late nights or fire drills, but you stay steady under pressure and bring a calm, practical energy that helps everyone else keep moving.\nYou approach prototyping like a product, not a one-time stunt. You think constantly about who will use it next—software teams, validation engineers, architects—and you shape decisions around usability, repeatability, and speed of iteration. You’re the person who turns vague goals into crisp plans, sets expectations early, and communicates progress in a way that builds confidence rather than surprise. When something fails, you get curious, not defensive. You narrow the problem, test assumptions, and keep digging until the root cause is understood and the fix is durable.\nYou’re also deeply collaborative. You listen hard, read the room, and adapt your style to the audience—whether you’re guiding a customer through a tough constraint conversation or aligning internal teams around a path forward. You take ownership naturally, you follow through, and you leave people feeling supported, informed, and ready for the next milestone.\nWhat You'll Be Doing\nProvide pre-sale and post-sale technical support for Synopsys HAPS-based prototyping solutions, including HAPS hardware and ProtoCompiler software\nWork directly with customers to prototype multi-million gate ASIC designs, guiding them through design partitioning, FPGA synthesis, system planning, and RTL debug\nLead technical evaluations of HAPS products at customer sites, diagnosing complex design issues, resolving timing closure problems, and optimizing prototyping flows\nDevelop and deliver customer training materials, application notes, and technical articles based on real deployment experience and customer use cases\nCollaborate with R&D teams to escalate product quality issues, propose new features, and contribute to improving quality of results in HAPS tools and flows\nTravel to customer sites as needed to support product deployments, troubleshoot critical issues, and enable successful prototype bring-up\nScript automation solutions in TCL and Python to streamline customer workflows and improve prototype performance\nThe Impact You Will Have\nEnable customers to catch critical bugs in multi-million gate SoCs before tape-out, saving them months of schedule risk and the cost of silicon respins\nAccelerate time-to-market for products across smartphones, network devices, and medical instrumentation by delivering working FPGA prototypes that software teams can develop against\nShape the roadmap of HAPS products by feeding real customer pain points and deployment challenges directly back to engineering teams\nBuild reusable methodologies, flows, and training content that scale across Synopsys's global customer base and reduce time to first prototype\nAct as the technical expert for HAPS within Synopsys, influencing how sales teams position the product and how customers adopt it\nHelp customers navigate the complexity of Xilinx Ultrascale and Versal architectures, turning prototyping from a bottleneck into a competitive advantage\nEstablish long-term technical relationships with the engineering teams at the world's leading chip companies\nWhat You'll Need\nBachelor's degree with 10+ years of relevant experience, or Master's degree with 8+ years\nHands-on experience with FPGA-based prototyping, including taking complex ASIC designs and successfully mapping them to FPGA hardware\nDeep knowledge of digital design fundamentals, VHDL, Verilog, or SystemVerilog, and experience with synthesis and simulation flows\nProven ability to debug FPGA designs and handle complex timing constraints, particularly on Xilinx Ultrascale or Versal device families\nStrong scripting skills in TCL and Python for automation and flow development\nExperience working directly with customers in a technical support, field applications, or consulting capacity is a strong plus\nFamiliarity with Synopsys verification tools such as VCS, Verdi, or VC Formal is a plus\nWho You Are\nYou can walk into a customer meeting, quickly assess where their prototype effort is stuck, and propose a concrete path forward without needing perfect information\nYou are comfortable explaining a complex partitioning tradeoff to a customer architect in a way that makes the technical and business implications clear\nYou do not get rattled when a customer escalation lands on your desk at 4 p.m. on a Friday, you treat it as a puzzle to solve, not a crisis to panic over\nYou write clear, useful documentation because you have been on the receiving end of bad app notes and refuse to inflict that on others\nYou know when to push back on a customer request that will lead them down a dead end, and you do it in a way that builds trust instead of burning it\nYou are organized enough to juggle multiple customer engagements, travel schedules, and internal projects without dropping threads\nThe Team You'll Be Part Of\nYou will join the HAPS Application Engineering team within Synopsys's Go-to-market organization. This team acts as the technical experts for HAPS FPGA-based prototyping products across Synopsys. You will work closely with sales teams during pre-sale evaluations, directly with customers during deployments and support engagements, and with R&D teams to influence product direction. The team supports customers globally, and you will collaborate with application engineers in other regions to share knowledge and solve complex prototyping challenges.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior DFT Engineer - Hardware", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-05-11", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-DFT-Engineer---Hardware_JR2017412", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nAs an NVIDIAN, you’ll be immersed in a diverse, inclusive and supportive environment where everyone is inspired to do their life's best work. The complexity of IOs increased many-fold to support the sophisticated speeds that power our product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. IODFX Engineering team at NVIDIA works on groundbreaking innovations involving crafting creative solutions for IO and interconnect testing for some of the industry's most complex semiconductor chips. Join the team and see how you can make a lasting impact on the world.\n\nWhat you'll be doing:\nPOR to Post Silicon Testing of DFX features for high speed IOs. This includes crafting of test features crucial for manufacturing testability of HighSpeed IOs. Architect, Design & Validate these test features with a robust & scalable testplan development at unit-level and SOC/Full Chip level using verification methodologies like UVM and NVIDIA Internal tools. Pre-Silicon Simulation and Debug of Test functionality using standard Industry tools and sign off on Test coverage for various products using standard coverage metrics.\n\nAbility to work on automation, flow development & improvement, coverage metrics, test execution, bug identification/fix and IO-test productization.\n\nSolve complex Test problems in the mixed-signal world and develop a scalable test solution that works across platforms.\n\nWork with powerful Industry-standard tools for Design and verification methodologies along with SV, UVM, Perl, Python and adapt to NVIDIA custom tools/flows.\n\nPartnering closely with our IP teams for design/verification of IOBIST test-logic, Collaborating with Mixed Signal Circuit design teams to understand the analog design components in an IO cell. Collaborate with other DFX teams, coordinate with Post Silicon Test Engineering and Production Engineering teams for productizing quality test at efficient test cost.\n\nWhat we need to see:\nBtech/BE/BS or Mtech/ME/MS in EE/ECE or equivalent experience\n\nSolid Analytical and Problem Solving skills.\n\nGood understanding and Exposure to Logic design, Architecture & Verification\n\nStrong background in DFT Engineering and Post Si DFX Productization\n\nStrong Coding skills in industry standard scripting languages.\n\n5+ yrs of experience in DFT and/or Industry-standard verification flows like constrained random testing, UVM, coverage metrics, profiling tools, X prop, etc. will be plus.\n\nOutstanding written and oral communication skills with the curiosity to learn.\n\nWith competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us and, due to unprecedented growth, our elite engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Applications Engineer - Motor Control", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-08", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010250", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n  Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\n  Application specific MCU industrial (ASM-IND) product line offers a broad range of high performance, innovative and cost-effective specialized MCUs for a wide range of applications across Motor control and Digital power. We enable powering next generation AI datacenters, provide motor control solutions for Humanoids, robotics, etc., build AI solutions for predictive diagnostics, improve performance, control and optimize energy efficiency.\n\nWe are looking for an application engineer who has the passion and excitement to continuously learn, innovate, take an active role in solving real time control. It is a fast paced, results driven environment requiring Microcontroller knowledge, system level understanding, software development, Motor control algorithms and system hardware skillsets. You will collaborate with worldwide accounts to solve their system challenges, enable them to go to market faster, work with marketing and business leadership to develop strategic technical solutions to enable TI business growth and impact the next generation of products.\n\nKey responsibilities include:\n\nDevelop sensored and sensor less motor control algorithms to enable – faster response, Smoother speed, less acoustic noise\n\nOwn specific IP’s – write technical reference manual, resolve customer issues through E2E platform and field engagement\n\nParticipate in customer calls to understand system requirements and help select the right devices and reference designs\n\nSupport customer design-in activities by: \n\nAdapting our system reference solutions to their custom hardware design.\n\nMeet customer across the globe to promote our technical benefits and resolve technical issues / Debug\n\nSchematic and layout review of customer solutions for our device\n\nHelp with software porting, optimize software to improve performance.\n\nResolve production stop issues for customers\n\nDesign EVM and internal evaluation boards to support evaluation activities of new products.\n\nTrain Field Applications Engineers and customers on ASM Microcontrollers and reference designs\n\nWrite application notes and training collateral that explain features, implementation of motor control on ASM Microcontrollers.\n\nQualifications\nQualifications\n\nMinimum requirements:\n\nMaster’s degree in Electrical Engineering or related degree\n\n3 years of application/system engineering experience\n\nMotor control algorithm development\n\nStrong knowledge of Microcontrollers\n\nExperience in embedded C software development\n\nSolid hardware and software debugging skills\n\nPreferred qualifications:\n\nPHD in Electrical Engineering, Power Electronics, Electrical Drive Systems\n\nHands-on experience working in motor control algorithm development \n\nKnowledge on Matlab, Simulink and Plexim for simulation and model-based code generation\n\nDigital control system design\n\nFamiliarity with field bus communication\n\nPower electronic system design\n\nKnowledge on functional safety, security and artificial intelligence\n\nAbility to review schematics and PCB layout using CAD tools\n\nDemonstrated strong analytical and problem-solving skills\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nDemonstrated ability to build strong, influential relationships\n\nStrong time management skills that enable on-time project delivery\n\nSelf-driven and ability to take initiative and drive for results\n\nContinuous learning mindset\n\nAbility to produce high quality technical documentation\n\nGood communication skillset to interface with customers and Field Applications Engineers\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Architect - GPU Performance", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-05-08", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Architect---GPU-Performance_JR2017247", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.\n\nNVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world. As part of this team, you would be working on projects that will help make our next generation visual computing, automotive, GPU, HPC  systems better. You will get to work on high performance CPU and Memory sub-systems, Next-Gen GPUs , NOC based Interconnect Fabric etc. Make the choice to join us today.\n \nWhat you'll be doing:\nSystem level performance analysis/ bottleneck analysis of complex, high performance GPUs and System-on-Chips (SoCs).\n\nWork on hardware models of different levels of abstraction, including performance models, RTL test benches ,emulators and silicon to analyze performance and find performance bottlenecks in the system.\n\nUnderstand key performance use-cases of the product. Develop  workloads and test suits targeting graphics, machine learning, automotive, video, compute vision applications running on these products.\n\nWork closely with the architecture and design teams to explore architecture trade-offs related to system performance, area, and power consumption.\n\nDevelop required infrastructure including performance models, testbench components, performance analysis and visualization tools.\n\nDrive methodologies for improving turnaround time, finding representative data-sets and enabling performance analysis early in the product development cycle.\n\n \nWhat we need to see:\nBE/BTech, or MS/MTech in relevant area, PhD is a plus, or equivalent experience.\n\n3+ years of experience with exposure to performance analysis and complex system on chip and/or GPU architectures.\n\nStrong understanding of System-on-Chip (SoC) architecture, graphics pipeline, memory subsystem architecture and Network-on-Chip (NoC)/Interconnect architecture.\n\nExpert hands on competence in programming (C/C++) and scripting (Perl/Python). Exposure to Verilog/System Verilog, SystemC/TLM is a strong plus.\n\nStrong debugging and analysis (including data and statistical analysis) skills, including use for RTL dumps to debug failures.\n\nHands on experience developing performance simulators, cycle accurate/approximate models for pre-silicon performance analysis is a strong plus.\n\n \nNVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative, autonomous and love a challenge, we want to hear from you. Come, join our Deep Learning Automotive team and help build the real-time, cost-effective computing platform driving our success in this exciting and quickly growing field. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "RF Validation Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-08", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010649", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\nValidation engineers are said to have a ';break-the-part'; mentality. This means they spend some of their time working to identify the use-cases in which the device will stop working as intended and understand the impact and cause of those failures. Sometimes, those are acceptable failures, but others we may need to mitigate for quality, safety, or other reasons. Plus, we want to ensure that our parts are consistently performing to the specifications that we set in our data sheet, and even to some more conservative limits or as defined in the VVCM (validation/verification compliance matrix). To do this, they must design PCB boards and develop automation software that will increase coverage and reduce data collection time. Validation engineers will also design, develop, and implement necessary methods of measuring device performance and troubleshooting any related systems, equipment or device issues that arise. Validation engineers are often working in a post-silicon lab or on the software programs required to run their measurements.\n\n \n\nTexas Instruments RF Connectivity group is expanding their RF Transceiver Validation Group in Bangalore, India.\n\nThis group develops cutting edge RF Transceiver products (+MCU integrated) for Wireless-LAN (WIFI) and Ultra-Wideband Systems (UWB). The typical transceiver blocks include RF blocks such as LNA, TA, Down-conversion Mixers, Base-band filters, High Speed ADC to send data to the Modem. Reverse Chain namely for Transmitter, starting from DAC, Base-band filter, Up-conversion mixer and Power Amplifier stages to drive the TX Pin. LO system includes Chrystal Oscillator, integer/fractional PLL and LO Distribution systems. Various Calibration modules (AGC, PDET, Gain, Offset, IQMM, etc) to calibrate the Transceiver chain is part of the design. Low Current Mode and Complex Power Management to operate at low LDO input voltage.\n\nThe required skills in the job are:\n\nSystem Level Understanding of Radio Transceiver: Basic operating principles of Transmit & Receiver chains, Modulation and system parameters such as PER/BER/SNR and EVM/RMSEE.\n\nDebug of the RF Transceiver SoC: Fast and Systematic Identification of the issues in the blocks. Observe and identify the root cause. Drive solutions and not just report problems. The debug would involve either Power & Biasing issues, Incorrect register sequence or incorrect values, Board level issues, Semiconductor Process marginalities etc.\n\nRF Measurements: Understanding of each RF, IF and DC measurement. Example in Receiver chain, measurement of Noise Figure & Gain of the chain, Linearity measurements such as P1dB, IIP2, IIP3, IQ gain & Phase error, LO Leakage and DC offsets. DC operating point measurement via Test Mode, DC Voltages and Current Consumption. Similar measurements for TX chain, PLL, Reference Clock.\n\nPCB Board Development:  Development of PCB Schematic and Layout, PCB material selection, stackup, review the design and implement the changes. Working with 3rd party PCB service companies. Familiarity with Altium and Cadence Allegro flows.\n\nTest Automation and Interpretation of Measurements: Person is expected to have proficiency in Coding & Automation of the measurement flows including interfacing of instruments. Processing of the measured data across PVT corners, Visualization and the ability to identify between IC and setup issues. Basic understanding of statistics and sources of error.\n\nInterfaces: Ability to deign and program interfaces such as SPI, UART, UCI.\n\nThe candidate is expected to have strong proficiency in 2 or more of the above list in particular 1-3. A strong team player who is deeply engaged with the Product Development team especially the Radio Design Team.\n\nMinimum expected experience is 6 years. Position is on-site in Bangalore. TI offers attractive compensation and a highly enriching technical environment. Ample opportunities to file Patents and become a Recognised Leader in the respective domain over time.", "jd_status": "source_unavailable"}, {"title": "RTL Design Principal Engineer", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-05-08", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/RTL-Design-Principal-Engineer_2601739", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nAbout Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI,\nautomotive, and carrier architectures, our innovative technology is enabling new possibilities.\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those\nlooking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.\nYour Team, Your Impact\nMarvell Data Centre Engineering (DCE) - Compute & Storage (CCS) BU has been at the forefront of developing and delivering leading-edge, high-\nperformance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast‐growing product lines, Marvell\ntechnology is powering the next‐generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive\nCompute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL\nproduct line.\nWhat You Can Expect\nDefine the sub system architecture, micro-architecture and register specification for highly complex SoCs. Drive and participate in specification\nwriteup\nConduct detailed performance, architectural and design requirement reviews with cross-functional teams, IP Vendors and customers\nImplement a specification using RTL coding techniques and best practices\nWork with third party vendors to define customization requirements of third party IPs (controller, PHY , etc.)\nWork with the physical design teams, reviewing and providing guidance in floorplanning, power analysis, synthesis and timing signoff.\nWork with the verification team on pre-silicon verification tasks such as reviewing the verification test plans, coverage analysis, full-chip simulation\nand emulation, performance and power analysis and debug\nHelp develop and/or evaluate design and verification methodologies and participate in improving existing ones\nCollaborate with and provide guidance to the post silicon and software teams for prototype bring up and performance tuning\nProvide mentorship to the more junior team member\n\nWhat We're Looking For\nBachelor’s or master’s degree and/or PhD degree in Computer Science, Electrical Engineering or related fields and 12+ years of related professional experience.\nExperience in creating architectural, micro-architectural, and register specifications.\nVerilog/System Verilog RTL coding with System Verilog assertions\nWell-versed in all stages of the ASIC design flow (including specification, architecture and design implementation, prototype bring-up)\nShould have worked on Full Chip Integration of Complex SoC design.\nHas worked on complex chips such as network processors, CPUs ,GPUs ,NOCs ,Switches , Machine Learning SoCs etc. owning full chip,\nsubsystem and block level architecture and design\nExpertise in any of the following domains would be a big plus: networking, embedded systems architecture, computer architecture, machine learning\naccelerators\nExperience with scripting in Perl/Python/Shell\n\nAdditional Compensation and Benefit Elements\nWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\n\nInterview Integrity \nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\n\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\n\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n\n#LI-CP1", "jd_status": "stored"}, {"title": "Lead DFx Silicon Design Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-05-07T10:46:00+00:00", "url": "https://global-external-amd.icims.com/jobs/81115/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. THE PERSON: As a DFx Silicon Design Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team! KEY RESPONSIBILITIES: Working with a multi-functional and cross-GEOs team of engineers on DFT (design-for-test) and DFD (design-for-debug) architecture and methodology. Performing design-for-test (DFT) RTL design using architectural specifications and design generation flows Performing DFT RTL integration, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS. Writing and maintain DFT documentation and specifications. Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design. Performing scan insertion, ATPG verification and test pattern generation Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis. PREFERRED EXPERIENCE: Experience in DFT design, integration, verification, ATPG and Silicon Debug experience. Demonstrated technical leadership and works well with cross-functional teams. Excellent communication and interpersonal skills Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design. Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc. Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential. Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations Experience in solving logic design or timing issues with integration, synthesis and PD teams. Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, c-shell, Perl), C++ programming Knowledge in EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis. Knowledge of ATE and digital IC manufacturing test is a plus. Strong problem-solving skills. Team player with strong communication skills. ACADEMIC CREDENTIALS: Bachelor’s or Master’s degree in electrical/Electronic Engineering with 12+Yrs of exp #LI-SR4 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Staff DFT ATPG Engineer, AI Hardware", "company": "Tesla", "location": "Bengaluru, India ; India", "date_posted": "2026-05-07T02:30:00", "url": "https://hire-r1.mokahr.com/social-recruitment/tesla/100004142?#/job/77069236-1dfb-4c29-bcbd-324e4ac5f328", "is_hardware": true, "platform": "mokahr", "jd_text": "The Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life. \n\nTesla's AI hardware team is seeking a highly motivated ASIC RTL Design Engineer with a specialization in the mathematical and computational aspects of custom AI accelerators. You will focus on designing high-performance, power-efficient RTL for math-intensive components that power our AI training and inference systems. This role emphasizes expertise in tensor operations, matrix computations, and optimized data paths for advanced AI workloads. If you are passionate about pushing the boundaries of low-precision arithmetic, quantization techniques, and hardware acceleration for machine learning, this is your opportunity to contribute to revolutionary AI hardware. \n\nOur Silicon Engineering team delivers silicon that meets production quality targets from first tapeout. As a Staff DFT ATPG Engineer, you will own pattern generation, ATE test program development, and DFT timing closure — from pre-Si ATPG through OSAT deployment — ensuring structural test quality and production efficiency at scale. \n\nResponsibilities\nGenerate production-quality ATPG patterns using Tessent for stuck-at, transition delay, path delay, cell-aware, and small delay defect (SDD) fault models \nAchieve and exceed coverage targets (>99% stuck-at, >98% transition) while minimizing pattern count for ATE test time \nDebug low coverage areas — X-state sources, blocking logic, untestable faults, and ATPG abort conditions \nUnderstanding and familiarity of hybrid bonding test concepts \nPerform gate-level pattern simulation to validate pattern integrity \nSupport hierarchical and flat ATPG methodologies for multi-million gate SoC designs \nArchitect and develop comprehensive ATE test programs covering ATPG, MBIST, Repair, Functional, DC, and HSIO \nOwn NPI silicon bring-up for structural tests — debug and root cause failures to closure \nDeploy and optimize test programs at OSATs for yield, quality, reliability, and cost \nDevelop custom test methods for product-specific requirements and contribute to wafer probe and final test hardware design \n\nRequirements\nDegree in Electrical Engineering, Computer Engineering, or related field, or equivalent experience \n10+ years across ATPG, ATE test development, and DFT timing \nExpert-level Tessent proficiency — TestKompress and MemoryBIST \nDeep knowledge of fault models: stuck-at, transition, path delay, cell-aware, and SDD \nATE test program development and OSAT deployment experience \nSDC constraint development for DFT test modes; timing closure using Tempus \nAbility to use agentic AI flows to automate ATPG and ATE test workflows", "jd_status": "stored"}, {"title": "Staff DFT DV Engineer, AI Hardware", "company": "Tesla", "location": "Bengaluru, India ; India", "date_posted": "2026-05-07T02:30:00", "url": "https://hire-r1.mokahr.com/social-recruitment/tesla/100004142?#/job/43f828b6-479b-44d5-b8e2-01773f7cf6fd", "is_hardware": true, "platform": "mokahr", "jd_text": "The Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life. \n\nTesla's AI hardware team is seeking a highly motivated ASIC RTL Design Engineer with a specialization in the mathematical and computational aspects of custom AI accelerators. You will focus on designing high-performance, power-efficient RTL for math-intensive components that power our AI training and inference systems. This role emphasizes expertise in tensor operations, matrix computations, and optimized data paths for advanced AI workloads. If you are passionate about pushing the boundaries of low-precision arithmetic, quantization techniques, and hardware acceleration for machine learning, this is your opportunity to contribute to revolutionary AI hardware.  \n\nOur Silicon Engineering team validates DFT features from RTL through silicon bring-up — ensuring test structures work correctly before the chip reaches the tester. As a Staff DFT DV Engineer, you will own functional verification of all DFT structures at block and SoC level, delivering pre-Si testcases that directly enable silicon debug and ATE correlation. \n\nResponsibilities\nDevelop SystemVerilog/UVM testbenches to verify DFT features — SSN, compressed scan, memory BIST, JTAG, and boundary scan at block and SoC level \nVerify top-level DFT features — power-on self-test, clock observation, clock stop, and scan dump \nRun DV regressions, analyze coverage, triage and debug failures to closure \nIdentify design fixes and validate DFT RTL corrections \nDeliver pre-Si DV testcases for silicon bring-up and ATE correlation \nOwn post-silicon ATE test correlation — root cause discrepancies between pre-Si and silicon behavior \nLeverage agentic AI flows to automate regression execution, coverage analysis, and failure triage \n\nRequirements\nDegree in Electrical Engineering, Computer Engineering, or related field, or equivalent experience \n10+ years of DFT DV experience at block and SoC level \nExpert-level SystemVerilog and UVM testbench development \nHands-on verification of SSN, compressed scan, MBIST, JTAG, and boundary scan, Phy Loopback, PLL testing.\nExperience delivering pre-Si testcases through silicon bring-up and ATE correlation \nAbility to use agentic AI flows to automate DV regression and debug workflows \nPost-silicon debug and ATE correlation experience on server-class SoCs \nFamiliarity with formal verification methods for DFT structural checks \nExperience with power-on self-test and clock control verification", "jd_status": "stored"}, {"title": "Automotive cybersecurity engineer – Senior /Staff Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-05-07T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718416476", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nQualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. Qualcomm is utilizing its traditional strengths in digital wireless technologies to play a central role in the evolution of automotive infotainment and autonomous driving. We are investing in several supporting technologies including 4G, 5G, ADAS, and Deep Learning. The Qualcomm Automotive Security team is engaged in offering optimized solutions built on Safety CPU cores, DSP, computer vision and machine learning algorithms for the Qualcomm ADAS/Autonomy/Infotainment systems architecture.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nWe are seeking experienced engineers with strong expertise in automotive cybersecurity at the system and SoC levels.\nThis position will be a hands-on role to independently perform cybersecurity management system audits and internal product assessment against ISO/SAE 21434 standard as well as driving continuous improvement in Qualcomm hardware cybersecurity development processes.\nThe ideal candidate will have deep knowledge of ISO/SAE 21434 standard, practical experience in applying them to hardware and SoC development, and the ability to independently assess, audit, and influence improvements across cross-functional engineering teams.\n\nResponsibilities shall include the following:\n· Enhancement of hardware development process and related work products meeting cyber security standards as part of continuous improvement.\n· Develop and deliver ISO/SAE 21434training, with emphasis on application of Qualcomm best practices.\n· Facilitate and review TARA (Threat Analysis and Risk Assessment) and VARA (Vulnerability Analysis and Risk Assessment) activities.\n· Independently conduct cybersecurity management system audits and product assessments against ISO/SAE 21434; provide actionable feedback, identify gaps, and track follow-up actions with internal teams.\n· Collaborate closely with SoC design teams, IP teams, third-party IP vendors, software teams, functional safety and cybersecurity managers, Quality teams, and customers to ensure effective deployment of defined cybersecurity processes.\n· Participate in external and customer cybersecurity assessments, including support for corrective and preventive actions.\n· Maintain strong awareness of automotive cybersecurity best practices, emerging standards, and regulatory trends; proactively influence stakeholders with data-driven insights to close gaps in a timely manner.\n· Build and sustain effective working relationships with key stakeholders across Cybersecurity, Functional Safety, and Quality, supporting ongoing internal and external assessments.\n\nMinimum Qualifications:\n· Bachelor’s degree in Electrical/ Electronics and Communications Engineering, Information Systems, Computer Science, or a related field.\n· 8+ years of Systems Engineering/VLSI design or related work experience.\n· Knowledge of product development flow and validation.\n· Experience in leading process audits and product assessments against ISO/SAE 21434 standard\n\nPreferred Qualifications:\n· 5+ years of automotive experience with familiarity in Hardware development in the semiconductor industry, meeting ISO/SAE 21434 standard\n· Familiarity with ISO 26262 and ISO 21448 automotive SOTIF standards is a plus.\n· Lead auditor certification for ISO 9001/IATF 16949 is a plus.\n· Familiarity with ASPICE and software aspects of the Automotive Safety Functions is a plus.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Principal Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-05-07", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Design-Engineer_R54525", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Description\nThe Principal AMS Design Engineer will be a key contributor to the HBM PHY team, responsible for the design and development of high-speed analog and mixed-signal circuits for next-generation HBM PHY products. This role includes detailed circuit design based on system and micro-architecture requirements, leadership in analog and layout design reviews, and close collaboration with cross‑functional teams including digital, layout, packaging, and SI/PI. The engineer will take ownership of project execution across development phases and play a critical role in driving new micro‑architecture innovations to meet aggressive performance, power, and area targets for advanced HBM PHY designs.\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Senior Manager, Analog and Mixed Signal Design Engineering", "company": "Analog Devices", "location": "India, Bangalore, RMZ", "date_posted": "2026-05-07", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Senior-Manager--Analog-and-Mixed-Signal-Design-Engineering_R262171", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).\n          \nAnalog Devices is seeking an experienced analog/mixed-signal IC design technical manager to join the Digital BU, Processor Group. The role leads a small team while serving as the analog technical lead responsible for block definition, design execution, and analog subsystem integration across multiple product domains.\n \nResponsibilities\n\n-          Requirements and architecture: translate system requirements into block-level architectures, specifications, and interface requirements\n-          Analog design ownership: design and review analog circuits/blocks to meet performance, power, area, and robustness targets\n-          Analog integration leadership: drive cross-block alignment and tradeoffs, partner with digital design on integration details, and coordinate validation/silicon debug through bring-up and issue resolution\n-          Modeling for verification: create analog models to support system verification and integration (including mixed-signal modeling in SystemVerilog where appropriate)\n-          People leadership: supervise, mentor, and develop analog design team members; drive execution through priorities, design reviews, and technical decisions\n-          Layout partnership: provide technical guidance to the physical layout team (constraints, matching/noise strategy, floorplan intent, and review)\n-          Test collaboration: collaborate with test engineering to ensure adequate test coverage; analyze ATE characterization data to set test limits and validate performance\n-          Lab validation: evaluate devices in the lab to validate product specifications using standard bench equipment (oscilloscope, spectrum analyzer, logic analyzer, power supplies, etc.)\n-          Customer/application support: interface with customers to understand use cases and issues; collaborate with applications on evaluation boards and application software as needed\n-          Quality/debug: participate in root-cause analysis of customer returns and functional issues\n\nRole scope\n\n-          Analog circuit definition, design, and integration is the core of the role, with regular cross-functional engagement across digital integration, validation, production test, software enablement, and customer support.\n\nWhat success looks like\n\nThe analog subsystem meets spec with clear interfaces, predictable integration, and efficient debug across lab/ATE/customer feedback loops, while the team consistently delivers high-quality blocks on schedule.\n\nMinimum Requirements\n-          BSEE (or equivalent) in Electrical Engineering\n-          12+ years of analog/mixed-signal IC design experience with ownership from architecture through silicon bring-up\n-          4+ years of technical people-management experience with direct reports (hiring, coaching, performance management)\n-          Demonstrated ability to serve as an analog technical lead while managing a team (prioritization, technical direction, design reviews, decision-making)\n-          Ownership of analog integration across the subsystem, including interface definition, requirements alignment across blocks, cross-block tradeoffs, and coordinating validation/silicon debug with partners (without owning top-level AMS verification)\n-          Strong hands-on analog design experience across multiple blocks such as ADCs/DACs, voltage references, op amps, switched-capacitor circuits, regulators, and oscillators\n-          Experience with mixed-signal/system modeling to support architecture, partitioning, and design trade-offs\n-          Working knowledge of ESD protection methodology and design considerations for robust interfaces\n-          Strong understanding of custom IC layout constraints (parasitics, matching, noise coupling) and effective partnership with layout to achieve PPA targets\n-          Strong written and verbal communication skills; comfortable driving alignment across design, layout, validation, and test\n \nPreferred Qualifications\n\n-          FinFET analog/mixed-signal design experience at advanced nodes\n-          Experience with custom digital design supporting mixed-signal IP (e.g., calibration, state machines, control/trim logic, interfaces)\n-          Strong understanding of production test/DFT for analog/mixed-signal (ATE constraints, coverage, trim strategy, characterization)\n-          Experience defining end-user PCB/interface requirements (signal integrity, grounding, filtering, reference/clocking, pinout considerations)\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "SoC Chip Lead", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-07", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010561", "is_hardware": true, "platform": "oracle", "jd_text": "We are at a pivotal moment where technology is rapidly evolving, and we have some exciting opportunities within our MCU organization that place us right at the center of this transformation.\n\n Our current work is focused on developing solutions for high-growth markets such as AI-driven data centers and emerging domains like humanoid systems. These areas are shaping the future of computing, automation, and intelligent systems, and offer a unique chance to work on cutting-edge technologies with real-world impact.\n\n If you are passionate about solving complex technical challenges and want to contribute to innovations in these fast-growing segments, I encourage you to come forward and apply. This is an opportunity to be part of a journey that is not only technically rewarding but also strategically significant.\n\n Looking forward to seeing many of you take this step.\n\nRole Title: SoC Chip Lead / design manager\n\nRole Summary: Own end-to-end delivery of the first T28 industrial ASIC for the MSP M33 Data center business. This role combines full chip ownership with functional team leadership, ensuring first-time-right silicon, scalable architecture, and a strong RTL organization for future platforms.\n\nKey Responsibilities:\n\nOwn SoC execution from spec → architecture → RTL → Silicon → mass production\n\nAct as single technical owner (Chip Lead) for the first T28 industrial ASIC\n\nDrive PPA, quality, cost, and schedule trade-offs\n\nLead execution across RTL, DV, DFT, PD and Validation.\n\nInterface with Architecture, IP, FW/SW, Product, Business teams, PE team.\n\nOwn pre-silicon sign-off and post-silicon bring-up & validation\n\nLead and grow the design team\n\nEnsure high-quality micro-architecture, coding, reuse, and integration\n\nBalance hands-on technical leadership with people management\n\nQualifications\nMinimum Qualifications:\n\nBachelors/Masters in EE or equivalent\n\n12 years experience in complex SoC/ASIC development\n\nLeadership experience in multiple SoC domains.\n\nStrong expertise in: ARM-based systems, interconnects, Low-power design, clock/reset/power architecture\n\nEnd-to-end SoC lifecycle exposure including RTL → PnR → timing closure\n\nStrong pre- and post-silicon debug skills, Multiple successful tape-outs\n\nExcellent communication and cross-team leadership skills\n\nPreferred:\n\nPrior Chip Lead / SoC Lead role\n\nExperience with first-silicon or new-node (T28) programs\n\nIndustrial SoC exposure\n\nPost-silicon bring-up and yield learning experience\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "RTL Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-07", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010582", "is_hardware": true, "platform": "oracle", "jd_text": "We are at a pivotal moment where technology is rapidly evolving, and we have some exciting opportunities within our MCU organization that place us right at the center of this transformation.\n\nOur current work is focused on developing solutions for high-growth markets such as AI-driven data centers and emerging domains like humanoid systems. These areas are shaping the future of computing, automation, and intelligent systems, and offer a unique chance to work on cutting-edge technologies with real-world impact.\n\nIf you are passionate about solving complex technical challenges and want to contribute to innovations in these fast-growing segments, I encourage you to come forward and apply. This is an opportunity to be part of a journey that is not only technically rewarding but also strategically significant.\n\nLooking forward to seeing many of you take this step\n\nQualifications\nMinimum requirements:\n\nB.S. (or M.S.) in Electrical/Electronics/Computer Engineering or related discipline.\n\n5 + years of hands‑on RTL design experience on high‑performance SoCs, preferably MCUs or wireless connectivity devices.\n\nStrong proficiency in SystemVerilog or VHDL; demonstrated ability to write clean, synthesizable, and testable RTL.\n\nDeep understanding of digital design fundamentals: pipelining, state‑machine design, bus protocols (AHB/APB/AXI), FIFO, arbitration, and clock domain crossing.\n\nExperience with synthesis tools (DC, Design Compiler, Innovus) and static timing analysis; ability to meet tight performance and power targets.\n\nProven track record in low‑power RTL techniques (clock gating, power‑domain isolation, dynamic voltage/frequency scaling).\n\nFamiliarity with verification flow (UVM, simulation, coverage) to effectively collaborate with DV teams.\n\nAdvanced scripting/automation skills (tcl, perl, python, Bash) for flow automation and CI/CD pipelines.\n\nExcellent written and verbal communication; strong stakeholder‑management skills across global functional teams.\n\nDemonstrated ability to lead design efforts, meet aggressive schedule milestones, and mentor junior engineers.\n\nPreferred qualifications:\n\nDefine and implement RTL architecture for complex SoCs, selecting appropriate coding styles, clocking strategies, and low‑power techniques.\n\nDevelop and maintain synthesizable SystemVerilog/VHDL code for digital blocks (core, peripherals, interfaces, DMA, etc.).\n\nCreate and own RTL simulation and synthesis testbenches, running regression to verify functional correctness and timing closure.\n\nCollaborate with verification engineers to ensure comprehensive test coverage, resolve RTL bugs, and support pre‑silicon validation.\n\nPerform timing analysis, constraint development (SDC), and STA, iterating on RTL to meet clock‑frequency, setup/hold, and power budgets.\n\nLead power‑aware design techniques (clock gating, power domains, voltage scaling) and ensure compliance with low‑power specifications.\n\nParticipate in design reviews, providing clear documentation of design decisions, trade‑offs, and risk assessments.\n\nDrive RTL quality improvement by establishing coding guidelines, linting policies, and best‑practice checklists.\n\nMentor junior RTL designers, fostering a culture of code quality, continuous learning, and knowledge sharing.\n\nWork with the EDA team to evaluate and integrate new synthesis, place‑and‑route, and static timing tools, improving flow efficiency.\n\nSupport post‑silicon bring‑up and bring‑down activities, assisting software/ROM teams with RTL‑related debug and performance tuning.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Lead DFT Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-07", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010572", "is_hardware": true, "platform": "oracle", "jd_text": "We are at a pivotal moment in the semiconductor industry. Technology is evolving at an unprecedented pace, and Texas Instruments' MCU organization is right at the center of this transformation.\n\nOur current work is focused on developing solutions for high-growth markets — including AI-driven data centers and emerging domains such as humanoid systems. These areas are actively shaping the future of computing, automation, and intelligent systems, offering a rare opportunity to work on cutting-edge technologies with real-world, large-scale impact.\n\nIf you are passionate about solving complex technical challenges and want to contribute to innovations in these fast-growing segments, this is your moment. This role is not only technically rewarding — it is strategically significant.\n\nTexas Instruments is seeking an experienced and driven DFT Lead to lead and shape the test engineering strategy within our MCU organization. In this role, you will direct and guide the activities of a research and technical design function responsible for designing, developing, modifying, and evaluating digital electronic parts, components, and integrated circuitry for electronic equipment and hardware systems.\n\nYou will play a critical leadership role in ensuring that our silicon is not only designed for performance and power efficiency, but also for testability, reliability, and manufacturability — qualities that are essential as we scale into AI and next-generation compute platforms.\n\nQualifications\nKey Responsibilities\n\nLead DFT strategy and execution across complex SoC and MCU designs targeting AI data center and humanoid system applications\n\nDirect and guide a team of DFT engineers in the design, development, and evaluation of test structures including scan chains, BIST, JTAG, boundary scan, and ATPG flows\n\nPrepare and present outcomes of DFT projects, test coverage metrics, and manufacturing test results; make actionable recommendations to achieve desired results\n\nCollaborate cross-functionally with design, verification, physical design, and manufacturing teams to integrate DFT methodologies early in the design cycle\n\nDrive continuous improvement in test coverage, fault detection, and test time reduction across product families\n\nSelect, develop, and evaluate personnel to ensure efficient operation of the DFT function; mentor engineers and foster a culture of technical excellence\n\nMinimum Qualifications\n\nBachelor's degree in Electrical Engineering, Computer Engineering, or related field (Master's or PhD preferred)\n\n5+ years of experience in digital design or DFT engineering\n\nDeep expertise in DFT methodologies: scan insertion, ATPG, BIST (Logic/Memory), JTAG, boundary scan, and test compression\n\nHands-on experience with industry-standard EDA tools (e.g., Synopsys TestMAX, Mentor Tessent)\n\nStrong understanding of SoC/MCU architecture and digital design flows\n\nProven ability to lead cross-functional teams and deliver results in a fast-paced, high-complexity environment\n\nExcellent communication skills — ability to present technical findings and recommendations to both engineering and executive audiences\n\nPreferred Qualifications\n\nBackground in embedded systems or MCU product development\n\nExperience with silicon bring-up, failure analysis, and yield improvement initiatives\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "DFT Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-07", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010573", "is_hardware": true, "platform": "oracle", "jd_text": "We are at a pivotal moment in the semiconductor industry. Technology is evolving at an unprecedented pace, and Texas Instruments' MCU organization is right at the center of this transformation.\n\nOur current work is focused on developing solutions for high-growth markets — including AI-driven data centers and emerging domains such as humanoid systems. These areas are actively shaping the future of computing, automation, and intelligent systems, offering a rare opportunity to work on cutting-edge technologies with real-world, large-scale impact.\n\nIf you are passionate about solving complex technical challenges and want to contribute to innovations in these fast-growing segments, this is your moment. This role is not only technically rewarding — it is strategically significant.\n\nTexas Instruments is seeking an experienced and driven DFT engineer to execute and shape the test engineering strategy within our MCU organization. In this role, you will direct and guide the activities of a research and technical design function responsible for designing, developing, modifying, and evaluating digital electronic parts, components, and integrated circuitry for electronic equipment and hardware systems.\n\nYou will play a critical leadership role in ensuring that our silicon is not only designed for performance and power efficiency, but also for testability, reliability, and manufacturability — qualities that are essential as we scale into AI and next-generation compute platforms.\n\nQualifications\nKey Responsibilities\n\nExecute DFT strategy and execution across complex SoC and MCU designs targeting AI data center and humanoid system applications\n\nCollaborate cross-functionally with design, verification, physical design, and manufacturing teams to integrate DFT methodologies early in the design cycle\n\nDrive continuous improvement in test coverage, fault detection, and test time reduction across product families\n\nSelect, develop, and evaluate personnel to ensure efficient operation of the DFT function; mentor engineers and foster a culture of technical excellence\n\nMinimum Qualifications\n\nBachelor's degree in Electrical Engineering, Computer Engineering, or related field (Master's or PhD preferred)\n\n3+ years of experience in digital design or DFT engineering\n\nExpertise in DFT methodologies: scan insertion, ATPG, BIST (Logic/Memory), JTAG, boundary scan, and test compression\n\nHands-on experience with industry-standard EDA tools (e.g., Synopsys TestMAX, Mentor Tessent)\n\nUnderstanding of SoC/MCU architecture and digital design flows\n\nPreferred Qualifications\n\nBackground in embedded systems or MCU product development\n\nExperience with silicon bring-up, failure analysis, and yield improvement initiatives\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Design Verification Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-07", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010595", "is_hardware": true, "platform": "oracle", "jd_text": "We are at a pivotal moment in the semiconductor industry. Technology is evolving at an unprecedented pace, and Texas Instruments' MCU organization is right at the center of this transformation.\n\nOur current work is focused on developing solutions for high-growth markets — including AI-driven data centers and emerging domains such as humanoid systems. These areas are actively shaping the future of computing, automation, and intelligent systems, offering a rare opportunity to work on cutting-edge technologies with real-world, large-scale impact.\n\nIf you are passionate about solving complex technical challenges and want to contribute to innovations in these fast-growing segments, this is your moment. This role is not only technically rewarding — it is strategically significant.\n\nTexas Instruments is seeking an experienced and driven DV engineer to shape the engineering strategy within our MCU organization.\n\nQualifications\nResponsibilities:\n\nResponsible for driving verification strategy, writing Test Plan, developing/modifying Test Bench.\n\nWorking on SoC DV signoff using C and/or SV-UVM.\n\nReuse of IP DV UVM components like agent, driver, monitor and score board at SoC.\n\nDefine and meet all structural and functional coverage goals\n\nSoC verification (including low power verification) in RTL, GLS & AMS.\n\nActively collaborate with IP/Architecture and RTL teams to enable meeting Verification goals for the SoC\n\n \n\nQualifications :\n\n3+ Years’ experience working on SoC/IP DV with a Bachelor or Master’s degree in EE/ECE/CS or related specializations\n\n \n\nSkills:\n\nStrong in digital design fundamentals, computer organization & architectures and bus protocols\n\nExcellent debugging and problem solving skill\n\nExperience in one or many of the following : UVM/System Verilog/C/C++/scripting, Simulation, Formal verification, or post Silicon validation\n\nThorough knowledge of standard protocols. Ex: AHB, APB, CAN, USB, I2C, SPI, UART, etc.\n\nExposure to AMS and/or Low Power Verification is a plus.\n\nEffective communication skills to interact with all stakeholders.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Mask Technology Scribe Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-07", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010591", "is_hardware": true, "platform": "oracle", "jd_text": "About the team\nThis position is on TI’s Advanced Technology Development (ATD) Mask Technology and Pattern Generation (MTPG) team.\nWe support mask building, reticle generation, scribe array generation, layout generation & verification methodologies. \n \nMask Technology Scribe Engineer \n \nSeeking motivated Scribe Development engineer \n \nSupporting Scribe Layout (KERF) Development and Support across various process nodes\n \n \nJob description:\nDevelopment and Support of Tech/fab-specific scribe recipe development & maintenance to generate reticle floorplan databases\nUnderstanding of ETEST structures, fab alignment structures and photolithography\nCollaborate with & guide various teams within Advanced Technology Development (process development, PDK), EDA and business units to ensure the necessary information is available to complete the tapeout process.\nEnsure consistent application of methodologies and best practices\n\nQualifications\nRequired Key Skills\n\n \n\nUnderstanding of Layout and basics of fabrication process (FEOL/BEOL) \n\nReal exposure to Mask Data Preparation tools like Cadence Mask Compose  \n\nKnowledge of Mask data tools like Cadence Virtuoso, (Pegasus designrev / Mentor calibredrv \n\nMaintain a high standard for cycle time and quality\n\nExcellent scripting skills with atleast one of PERL, Python, TCL or Cadence skill with special focus on layout automation and geometry processing algorithms \n\n \n\n \n\nEducational Qualifications\n\n \n\nBachelors / Master’s degree in Computer Science, \n\nElectrical/Electronic Engineering or related field with (2-5) years of Hardware Engineering or related work experience.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Design Verification Manager", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-07", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010581", "is_hardware": true, "platform": "oracle", "jd_text": "We are at a pivotal moment where technology is rapidly evolving, and we have some exciting opportunities within our MCU organization that place us right at the center of this transformation.\n\nOur current work is focused on developing solutions for high-growth markets such as AI-driven data centers and emerging domains like humanoid systems. These areas are shaping the future of computing, automation, and intelligent systems, and offer a unique chance to work on cutting-edge technologies with real-world impact.\n\n If you are passionate about solving complex technical challenges and want to contribute to innovations in these fast-growing segments, I encourage you to come forward and apply. This is an opportunity to be part of a journey that is not only technically rewarding but also strategically significant.\n\nLooking forward to seeing many of you take this step\n\nQualifications\nMinimum requirements:\n\nYou will be responsible for driving SoC DV and AVnV (Pre/Post silicon, FPGA, Palladium)\n\nSupport verification/validation leads for power aware verification, GLS, AMS flows, Palladium and FPGA activities\n\nRTL and GLS regression and follow-up with tracking of the various activities. Run coverage and meet the defined coverage(coverage & functional) goals\n\nResult driven attitude who can work with dynamically evolving requirements\n\nAbility to participate and conduct design reviews\n\nAbility to mentor the team members\n\nAbility drive results from team even without having complete command on domain\n\nGood interaction with cross site teams of Digital Design team, s/w team, Analog Designers, and rest of the team\n\nInnovate & drive new and improved design verification methodologies where needed, work with the EDA team to upgrade tools and flows\n\nInteracting with Test/Silicon Validation/Application Engineering team to ensure successful use of products and support customer applications debug/analysis\n\nPreferred qualifications:\n\nBachelors or Masters degree in Electrical / Electronics Engineering\n\nMinimum of 8+ years of experience\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nAbility to support Software & ROM team on silicon bring-up, debug etc\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Senior Principal Engineer, RTL ASIC Design", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-05-07", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Senior-Principal-Engineer--RTL-ASIC-Design_2601747", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nAbout Marvell\n\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.\n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.\n\nYour Team, Your Impact\n\nThe Custom and Compute Solutions Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up.\nWhat You Can Expect\nMethodology Development\nDesign and implement robust workflows for design, verification, and automation.\nEstablish best practices, standards, and documentation for methodology adoption.\nContinuously evaluate and refine methodologies to improve efficiency and scalability.\nAI Integration\nApply machine learning and AI techniques to optimize design flows, resource allocation, and problem‑solving.\nDevelop predictive models and intelligent tools to assist engineers in decision‑making.\nCollaborate with cross‑functional teams to identify opportunities for AI‑driven improvements.\nTool & Infrastructure Management\nWork with CAD/EDA teams to integrate methodologies into existing toolchains.\nAutomate repetitive tasks using scripting languages (Python, Perl, TCL, Shell).\nEnsure compatibility and interoperability across tools and platforms.\nCollaboration & Support\nPartner with design, verification, and CAD teams to deploy methodologies effectively.\nProvide training and support to engineers on new workflows and AI tools.\nAct as a liaison with vendors and research partners for tool evaluation and innovation.\nInnovation & Research\nStay updated on emerging AI/ML techniques and industry trends.\nPropose and prototype new approaches to enhance design productivity.\nContribute to long‑term strategy for AI adoption in engineering methodologies.\n\nWhat We're Looking For\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.\n18+ years of experience in design automation, methodology development, or AI/ML applications in engineering.\nStrong programming and scripting skills (Python, TCL, Shell, C++).\nHands‑on experience with EDA tools and design flows (front‑end and back‑end).\nSolid understanding of machine learning concepts and practical applications.\nExcellent problem‑solving, communication, and collaboration skills.\nPreferred Skills\n\nKnowledge of semiconductor design processes (RTL‑to‑GDSII, verification, DFM).\nFamiliarity with cloud computing and distributed systems.\nExposure to data analytics and visualization tools.\nStrong programming and scripting skills (Python, TCL, Shell, C++).\nHands‑on experience with EDA tools and design flows (front‑end and back‑end).\nSolid understanding of machine learning concepts and practical applications.\nExcellent problem‑solving, communication, and collaboration skills.\n\nAdditional Compensation and Benefit Elements\nWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\n\nInterview Integrity \nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\n\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\n\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n\n#LI-CP1", "jd_status": "stored"}, {"title": "Lead Digital Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-07", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010574", "is_hardware": true, "platform": "oracle", "jd_text": "We are at a pivotal moment in the semiconductor industry. Technology is evolving at an unprecedented pace, and Texas Instruments' MCU organization is right at the center of this transformation.\n\nOur current work is focused on developing solutions for high-growth markets — including AI-driven data centers and emerging domains such as humanoid systems. These areas are actively shaping the future of computing, automation, and intelligent systems, offering a rare opportunity to work on cutting-edge technologies with real-world, large-scale impact.\n\nIf you are passionate about solving complex technical challenges and want to contribute to innovations in these fast-growing segments, this is your moment. This role is not only technically rewarding — it is strategically significant.\n\nTexas Instruments is seeking an experienced and driven DFT Lead to lead and shape the test engineering strategy within our MCU organization. In this role, you will direct and guide the activities of a research and technical design function responsible for designing, developing, modifying, and evaluating digital electronic parts, components, and integrated circuitry for electronic equipment and hardware systems.\n\nYou will play a critical leadership role in ensuring that our silicon is not only designed for performance and power efficiency, but also for testability, reliability, and manufacturability — qualities that are essential as we scale into AI and next-generation compute platforms.", "jd_status": "source_unavailable"}, {"title": "Manager, Analog Design ", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-05-06T13:29:29.142000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000124904959-manager-analog-design-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Looking for a 10+ years experienced Engineering Manager with in-depth understanding of Analog concepts, experience of design of complex Analog I/Ps & sub-blocks, integrating I/Ps and sub systems and ownership, experience of fully owning smaller ICs (Point of loads, Single Converters) and owning major I/Ps in large PMICs, to join the 2.6B$ Power Business Unit. The candidate will get to work on a wide range of exciting products such as PMICs, Linear and Switching DC-DC converters powering the next generation of Renesas processors. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas’s massive Power product portfolio. \nEssential Functions: \nMust be proficient in designing and owning complex I/Ps like +ve/-ve Charge Pumps, Buck Converters, Source-Sink LDOs, Ultra-low power Oscillators (including Relaxation type), Temperature Sensor, Current Sense, SAR ADCs, Protection (Thermal, Under-Voltage, Over-Voltage, Over Current etc) and analog blocks including Bandgap references, V2I, Analog Buffers, Op-Amps, Comparators, High speed level shifters etc.  \n\nMust have in-depth Understanding of and should be able to implement & compensate the Control Loops, Analog feedback loops and should know trade-offs between various compensation strategies. \n\nShould be able to build/support Block level spec break down from Top level chip requirements and independently own, design complete switching converter e.g. Buck, Boost, Buck-Boost etc and LDOs. Must be able to do block level error budgeting depending on the block requirements. \n\nMust be aware of relative differences of various control loop architectures (Constant Freq, Constant ON/OFF Time, Current mode etc) and decide/implement the best option to meet converter level performance specifications and other system requirements. \n\nMust be able to bring in innovative ideas to improve designs to meet challenging specifications. \n\nShould have in-depth knowledge of Analog layouts and be able to work closely with layout lead from floor planning till Chip Top completion and verification and do trade-offs based on desired performance \n\nMust be conversant with the standard design, extraction and simulation flows & tools, speed, convergence, accuracy trade-offs and should be able to optimize setups based on Pre/Post (with/without) Parasitic using simulator options, debug and navigate through tool related challenges. \n\nShould be able to setup design flows and methodologies including checklists, reviews to ensure quality designs and take them all the way to Silicon success. \n\nShould be able to mentor Freshers and Junior engineers for upscaling their technical skills as well as other skills needed for better efficacy. \n\nShould have experience of end-to-end IC development flow, Silicon debugs, and taking ICs to production \n\nShould be able to lead/manage a small group of Engineers and navigate through all stages of IC development while handling and mitigating challenges, ensuring high quality silicon while adhering to the schedules based on business needs. \n\nShould have in-depth understanding of ESD, LU and other IC level issues and be able to define protection for the I/O ring for the IC \n\nBachelor’s or master’s degree in electrical engineering  \n\n10+ years in Analog Circuit Design, minimum 2 years of managerial experience.  \n\nSolid understanding and design experience of complex analog designs with full ownership.  \n\nChip design, Verification, Silicon validation, debugs, Qual support and taking ICs to production.  \n\nMust be a technical leader and natural team player, mentor and should strive towards fostering a highly creative and productive working environment  \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nWe have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning.", "jd_status": "stored"}, {"title": "Lead Logic Design Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-05-06", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/Lead-Logic-Design-Engineer_R-10063177", "is_hardware": true, "platform": "workday", "jd_text": "Responsibilities\nTranslate System Level Requirements into hardware block level specifications\nDigital design and RTL coding for the High-Speed data paths and control blocks\nWork with the verification team and Physical Design teams toward successful verification and implementation\nReview test plans\n \nRequirements\nStrong experience of micro architecting and design of high-speed products\nGood Protocol exposure to either USB3.2, Display Port, MIPI, Ethernet\nStrong at Datapath designs, Aggregation and FSMs\nGood grasp on Digital design flows covering Low power using UPF, CDC, synthesis, DFT, P&R, Timing \nPower Estimations at the RTL level\n \nSkills/Experience\n7+ years’ experience in High Speed Datapath designs\nRTL design using Verilog, System Verilog\nKnowledge of complete RTL to GDS design implementation flow\nBachelors/Masters in Electronics Engineering\n\nMore information about NXP in India...\n\n#LI-7013", "jd_status": "stored"}, {"title": "Software Database Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-05-06", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010421", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\nThis position is on TI’s Advanced Technology Development (ATD) Mask Technology and Pattern Generation (MTPG) team. Primary responsibilities may vary according to the candidate’s experience and expertise and could include: design and development of new software tools, scripts, and interfaces for use in the PG process; participating in coordinated efforts within the ATD-MTPG team to ensure consistent application of methodologies and best practices; and helping to implement and drive efficiency improvements and changes in those methodologies.\n\nQualifications\nBasic Qualifications\n\nBachelor's degree in Software Engineering or related field.\n\nThis engineer must have strong communication skills (verbal and written).\n\nProficiency in software development is required.\n\nWe’re searching for a detail-oriented individual with the ability to balance multiple critical path and time sensitive jobs on a regular basis.\n\n \n\nPreferred Qualifications & Skills \n\nThe ideal candidate will have an understanding of the basics of semiconductor mask design, and a general knowledge about the use of masks in the manufacture of semiconductor devices.\n\nExperience and proficiency in the following areas is also preferred: Cadence design environment (schematic & layout); advanced programming experience with PERL, Ruby, Oracle, and Unix Shell.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Frontend  infrastructure CAD/tools  Engineer", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-05-06", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Frontend--infrastructure-CAD-tools--Engineer_2503845", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nThe Switch Business Unit in Marvell designs and develops the next generation datacenter and enterprise System-On-Chip switch processors on leading edge process technology. We develop the architecture, collaborate on IP development, create the physical design, develop switching solutions and work with the world’s leading data center and enterprise companies to bring next generation networking to reality.\nWhat You Can Expect\nDevelop and support EDA/home grown tools automation using Python and Perl.\nDevelop AI integration to existing tool  and Integrate existing AI tools.\nSupport and develop source control (Git/GitHub), Unix setup and LSF grid scripting. \nUnderstand end-to-end Frontend development EDA flow like Simulators, Waveforms, Linting and more.\n\nWhat We're Looking For\nWe are seeking a highly motivated Frontend infrastructure CAD/tools Engineer to join our team.\nThe candidate will be responsible for developing and supporting the frontend infrastructure tools used for development of VLSI chips. The Frontend infrastructure consist of tools and automation to support EDA tools/flows as well as home grown application , Unix environment configuration and Git/Github source control.\nThe role involve hand-on work with Python, Perl scripting, AI integration using LLM and RAG and integration of existing AI tools and IDE like DVT, Euclide and VScode.  \n\nQualifications:\nB.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related field.\n5+ years in tools development and automation, Advantage for EDA flow development experience .\nHands-on experience in automation development in Python, Perl.  Advantage for  JavaScript, C/C++ and Web/PHP.\nAbility to effectively develop and utilize AI tools and technologies and integrate them into existing flows/tools.\nKnowledge of Pre Silicon frontend EDA flows is an advantage.\nKnowledge and experience in Verification, UVM and SV is an advantage.\nExcellent problem-solving skills, great debug abilities and attention to details.\nStrong communication skills and ability to work in a cross-functional team environment.\n\nAdditional Compensation and Benefit Elements\nWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\n\nInterview Integrity \nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\n\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\n\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n\n#LI-RV1", "jd_status": "stored"}, {"title": "R&D Engineering, Architect - DDR", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-05-06", "url": "https://careers.synopsys.com/job/bengaluru/r-and-d-engineering-architect-ddr/44408/94778510224", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\n\nYou Are:\nYou are a seasoned expert in high-speed interface principles with a deep understanding of mixed-signal design and off-chip signaling. You have a proven track record of generating and supporting comprehensive documentation through written specifications and possess exceptional communication skills to convey these specifications within a design team and to external customers. You are adept at custom analog design, simulation, test planning, and verification of complex integrated circuit components. With at least 12 years of relevant experience, you have honed your skills in troubleshooting and debugging mixed-signal interfaces. You thrive in a collaborative, multi-site team environment and are passionate about translating customer desires into innovative product design features and functions. Your expertise will be pivotal in driving the development of next-generation DDR and HBM PHYs in the Synopsys IP portfolio.\n\nWhat You’ll Be Doing:\nUnderstanding marketing and customer desires for Synopsys’ DDR and HBM PHY interface performance and functionality.\nTranslating those desires into a set of product design features and functions.\nGuiding the custom analog designers.\nOptimizing the design for performance, power, and area.\nInteracting and communicating with design teams performing logical design, logical verification, analog circuit design and verification, and layout design.\nSupporting customers in their implementation of the product.\nTracking industry developments through standards committees, representing Synopsys in these committees.\n\nThe Impact You Will Have:\nDrive the innovation and development of high-performance DDR and HBM PHY interfaces.\nEnsure Synopsys’ products meet and exceed market and customer expectations.\nEnhance the functionality and performance of Synopsys’ IP portfolio through cutting-edge design and optimization.\nStrengthen Synopsys’ presence and influence in standards committees and industry developments.\nFacilitate seamless integration and implementation of Synopsys products for customers worldwide.\nContribute to the overall success and technological advancement of Synopsys.\n\nWhat You’ll Need:\nDeep understanding of high-speed interface principles, such as mixed-signal design and off-chip signaling.\nExpertise in generating and supporting documentation through written specifications.\nProficiency in custom analog design, simulation, test planning, and verification of complex integrated circuit components.\nStrong troubleshooting and debugging skills for mixed-signal interfaces.\nMinimum of 12 years of related experience.\n\nWho You Are:\nYou are a collaborative team player with excellent communication skills and the ability to work across multi-site teams. You are detail-oriented, highly analytical, and capable of addressing complex and multi-dimensional issues. Your extensive experience and mastery-level knowledge position you as a pre-eminent expert in your field. You are driven by innovation and have a strategic mindset that aligns with Synopsys’ goals and objectives.\n\nThe Team You’ll Be A Part Of:\nYou will join a collaborative, multi-person engineering team engaged in similar activities on related DDR and HBM PHY development projects. This team is dedicated to planning and executing the design for the next-generation DDR and HBM PHYs in the Synopsys IP portfolio, ensuring that Synopsys remains at the forefront of technological innovation.", "jd_status": "stored"}, {"title": "Sr Staff Application Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-05-05T16:58:19.674000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000124706191-sr-staff-application-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "We are seeking a Sr. Staff  Applications Engineer with deep expertise in power electronics and power management systems to support Renesas’ India‑focused growth initiatives. This role is hands‑on, customer‑facing, and technically authoritative. \nThe successful candidate will act as the technical backbone between customers, field teams, and internal design groups, owning application architecture, reference designs, competitive analysis, validation methodology, and critical customer debug. This role strongly influences product P&L or roadmap decisions through real system insight. \nYou will be expected to operate autonomously, mentor other applications engineers, and represent Renesas as a trusted technical authority at key customer engagements \nResponsibilities :\nCustomer‑Facing Applications Leadership \n\nServe as the primary technical interface for key customers in power-related applications (industrial, automotive light EV, inverter/UPS, consumer power, energy storage). \n\nLead design‑in, bring‑up, and debug activities at customer sites or Renesas labs. \n\nDiagnose complex system‑level issues across power stage, control loop, sensing, firmware interaction, EMI/thermal behaviour. \n\nProvide structured technical feedback to product and design teams based on real customer usage. \n\nReference Designs & Application Enablement \n\nArchitect and develop reference designs, evaluation platforms, and application demonstrators using Renesas power products (e.g., MOSFETs, DC/DC, PMICs, gate drivers, BMS ICs). \n\nOwn schematic review, component selection, PCB guidance, and layout best‑practice recommendations. \n\nGenerate application notes, design guides, and technical collateral that materially improve customer adoption. \n\nDefine validation plans that reflect real-world corner cases, not just datasheet conditions. \n\nSystem‑Level Technical Expertise \n\nUnderstand and analyse full power system behaviour, including:  \n\nControl loop stability and transient response \n\nThermal and efficiency trade‑offs \n\nProtection mechanisms and fault behaviour \n\nInteraction with MCUs/SoCs and firmware \n\nPerform and guide system modelling and simulation (SIMPLIS, PLECS, SPICE). \n\nEvaluate design trade‑offs and clearly articulate why one solution works better than another keeping BOM cost in mind \n\nLab Ownership & Technical Depth \n\nHands‑on operation of lab equipment: oscilloscopes, Bode/network analysers, electronic loads, power supplies, thermal setups. \n\nDevelop automation scripts (Python/C) to accelerate validation and characterization. \n\nSupport failure analysis and root cause investigation for field issues and RMA trends. \n\nTechnical Leadership & Mentorship \n\nAct as a technical mentor for junior and mid‑level applications engineers. \n\nHelp define best practices, review standards, and debug methodologies across the power applications team. \n\nInfluence hiring by helping assess deep technical capability (not surface‑level\n\nRequired skills & Qualifications:\nComfort and ability to collaborate and be effective in an entrepreneurial (fast-paced and ambiguous) environment  \n\nExcellent interpersonal, communication and presentation skills and comfort in presenting to a wide range of audiences. Capable to communicate issues in a concise and effective way. \n\nDesire and drive to interact with, as well as ability to build and maintain excellent relationships with internal and external stakeholders.  \n\nProduct ownership mentality \n\n12+ years of experience in power management space, ideally including customer facing technical problem solving with semiconductor companies  \n\nTravel will be required \n\nBachelor or Masters of Electronics Engineering related discipline  \n\nAbility to build a strong team and motivate individuals to work out of their comfort zone \n\nSelf-driven, strongly motivated individual capable to take full ownership of their activities, and to involve other functions in the company or management when needed to bring them to a successful outcome. \n\nUnderstanding of power management applications and products. \n\nTechnical proficiency :\nDeep understanding of Power topologies (e.g., buck, boost, buck boost, isolated where relevant), Control loop theory and compensation, Thermal design and power loss modelling (using FEA tools), and EMI/EMC considerations at board and system level \n\nHands-on experience and ability in lab debugging, probing and characterizing circuit and silicon using a mixture of custom-made and standard equipment such as power supplies, e-load, digital oscilloscopes, spectrum analyzers, etc. \n\nSIMPLIS or similar ckt simulator  \n\nProgramming proficiency Python or C for automation and data analysis \n\nExpertise in board level analog and digital circuit design expertise and PCB schematic design using PCB CAD tools \n\nProficiency with a full complement of lab equipment including network analysers, oscilloscopes and waveform generators.  Experience with automation of lab testing. \n\nData analysis using Excel or JMP  \n\nUnderstanding of AECQ / IATF /ISO26262 (FuSa) (At least basic level) \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nWe have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning.", "jd_status": "stored"}, {"title": "Senior Staff Engineer Systems", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-05-05T08:27:03+00:00", "url": "https://jobs.infineon.com/careers/job/563808970646434", "is_hardware": true, "platform": "eightfold", "jd_text": "As a member in WLAN MAC Coex systems team you will play a key role spanning from development, implementation and analyse results for BT-WLAN coexistence\n\nYour Role\n\nKey responsibilities in your new role\n Development      experience on Wi-Fi, Bluetooth and Zigbee technologies.\n Good      understanding of BT, WLAN and ZigBee protocols are added advantage.\n Sound      basics in wireless communication systems and embedded system design /      programming.\n Hands      on experience of programming in Assembly language, C\n Good      debugging skills in C, using gdb, analysing crashes using stack trace are      essential\n Fair      understanding of WiFI debugging tools using Wireshark etc\n Understanding      of Bluetooth sniffer logs are added advantage.\n Familiarity      with IEEE 802.11 standards is desirable.\n Knowledge      of Tcl/Python/System C would be plus.\n Ability      to work with large, global, cross functional team.\n Good      communication and presentation skills.\n\nYour Profile\n\nQualifications and skills to help you succeed\n\nAs a member in WLAN MAC Coex systems team you will play a key role spanning from development, implementation and analyse results for BT-WLAN coexistence.\n  Your      key responsibilities in would be\n      a. Design, analysis, development & maintenance of WLAN-BT-ZigBee      coexistence.\n      b. Pre-Si design verification of Coex interfaces using scripting languages      like TCL/python and validate in simulation environment.\n      c. Working with various Cross functional teams like WL MAC, PHY systems,      Firmware development, BT Stack, BT Firmware team and Hardware design teams\n      d. Hands on silicon bring-up\n      e. Debugging and solving cross layer customer issues – working across      boundaries of WLAN MAC, BT sniffer analysis – while staying focused on the      underlying problem.\n      f. Understanding and modifying switch control logics between WLAN and BT.\n      g. Identifying issues and proposing design and methodology improvements      while driving compliance of existing design flow\n      h. Mentoring and training other team members as necessary\n      i. Creating collateral for internal and external use as necessary.\n\nContact:\n    AnandNarendrakumar.Rawal@infineon.com\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\nThis means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.\nPlease let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.\nClick here for more information about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Senior Engineer, Analog Layout", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-05-05T04:13:46+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000124555759-senior-engineer-analog-layout", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Looking for a 3+ years experienced Engineer with good understanding of analog layout, passion to apply knowledge and build ICs and well versed with layout related flows, to join the 2.6B$ Power Business Unit where in the candidate will get to work on a wide range of exciting products such as PMICs, Linear and Switching DC-DC converters powering the next generation of most sought after phones and hand held devices. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas’s massive Power product portfolio.\nEssential Functions:\nDrive and use best practice for floor plan development. Ensure collaboration with designers and layout colleagues to accurately capture requirements, and review floor plan prior to routing to ensure cell dimensions, device placement and pin location are optimal for performance and area.\nUse state-of-the-art layout techniques for matching accuracy, parasitic reduction and yield optimization.\nStrong use of automation to improve turn around times, including skill programming, TCL, PERL etc.\nRouting and verification (DRC, ERC, LVS) of block and circuit level layout.\nOrganize layout reviews and ensure management is well informed of time scale estimates, progress against project plans and any arising issues.\nDemonstrate, and continue to develop, expertise in layout using deep submicron CMOS processes\nDemonstrate, and continue to develop, expertise in the required CAD tools (Virtuoso XL / Calibre DRC, LVS & PEX / VCAR / VSR /PVS / R3D).\nMentor junior layout engineers whilst working on more complex tasks.\nFollow methodology guidelines to ensure easy portability of IP across designs.\nHelp resolve issues (CAD / PDK / process) alongside colleagues in corporate engineering.\nSuggest improvements to methodology and procedures.\nTake proactive approach to driving own development plan, utilizing team members and internal development opportunities.\n\nMinimum Requirements:\nBachelor’s or Master’s degree in Electrical engineering\n3+ years in Analog Layout design and associated flows.\nMust be a natural team player and strive towards fostering a highly creative and productive working environment\nWork indepdnently on straightforward tasks, with little direction from manager.\nCan exercise judgement within defined procedures to determine best action.\nCross cultural awareness and sensitivity.\nResults-oriented and able to deliver on-time under tight schedule .\nAbility to work both independently and part of a team.\nFlexible to undertake occasional international travel at short notice.\nExcellent command of verbal and written English.\nAbility to propose innovative solutions.\nConcise and precise communication and presentation skills within multisite and multicultural environment.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nWe have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning.", "jd_status": "stored"}, {"title": "DFT Engineer ", "company": "Tesla", "location": "Bengaluru, India ; India", "date_posted": "2026-05-05T02:30:00", "url": "https://hire-r1.mokahr.com/social-recruitment/tesla/100004142?#/job/b2bb984c-0211-4d19-b7df-097d54fd6568", "is_hardware": true, "platform": "mokahr", "jd_text": "About the Role:\nTesla’s Silicon Development Group is seeking a DFT Engineer to drive Design-for-Test across the design-to-production lifecycle for custom ASICs. In this role, you will own testability from design through silicon bring-up and high-volume manufacturing. You will advance state-of-the-art methodologies in test, debug, and safety to achieve high coverage, exceptional quality, and ultra-low DPPM—while optimizing test cost at scale.\n\nResponsibilities:\nDefine and implement DFT features at RTL and gate levels using in-house flows\nPartner with physical design teams to achieve timing and design closure with DFT constraints\nExecute block-level scan insertion, ATPG, coverage analysis, and simulations\nPerform full-chip pattern retargeting, validation, and sign-off\nDrive design improvements to enhance test coverage and diagnosability\nCollaborate with test and product engineering on pattern delivery, silicon bring-up, debug, and characterization\n\nRequirements:\nStrong understanding of DFT methodologies including compressed scan, MBIST, loopback, and boundary scan across digital logic, embedded memory, and IO/PHY domains\nSolid knowledge of JTAG, IEEE 1500, and IEEE 1687; familiarity with BSDL, ICL, and PDL is a plus\nProven expertise in ATPG, coverage analysis, and both zero-delay and SDF-based simulations\nExperience with industry-standard DFT tools such as Cadence Modus/Genus or Siemens Tessent\nStrong foundation in Verilog, digital logic design, circuit fundamentals, and timing analysis\nProficiency in scripting (TCL, Python, or Perl)\nExperience with MBIST implementation, repair algorithms, and memory test strategies is a plus\nExposure to SerDes and mixed-signal DFT techniques (e.g., IOBIST, loopbacks) is a plus\nPost-silicon experience including pattern conversion, bring-up, debug, and characterization is a plus\nBachelor’s or Master’s degree in Electrical or Computer Engineering (or equivalent experience)", "jd_status": "stored"}, {"title": "NPU/AI Processor Synthesis - Principal Engineer/Manager", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-05-05T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446704787413", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nRole Overview\nThe NPU Synthesis Lead will be responsible for driving synthesis and timing closure for Neural Processing Unit (NPU) IP and subsystems in cutting-edge SoCs. This role involves leading synthesis flows, optimizing for PPA (Performance, Power, Area), and collaborating with architecture, RTL, and physical design teams to ensure high-quality netlists for advanced technology nodes.\nKey Responsibilities\nSynthesis OwnershipLead RTL-to-gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler, Cadence Genus).\nDevelop and maintain synthesis scripts and flows for hierarchical and flat designs.\n\nTiming ClosureDrive pre-layout and post-layout timing closure across multiple voltage and process corners.\nCollaborate with STA teams to resolve setup/hold violations.\n\nPower & Area OptimizationApply physical-aware synthesis techniques to meet aggressive PPA targets.\nImplement low-power strategies using UPF/CPF flows.\n\nConstraint ManagementValidate and maintain SDC constraints for clocks, I/O delays, multi-cycle paths, and false paths.\n\nCross-Functional CollaborationWork closely with RTL design, DFT, and physical design teams for seamless handoff.\nProvide feedback to architecture and RTL teams for QoR improvements.\n\nQuality ChecksPerform LEC (Logical Equivalence Check), CLP (Clock/Power checks), and linting.\n\nFlow InnovationExplore advanced synthesis methodologies and EDA tool capabilities for better QoR.\n\nTeam LeadershipMentor junior engineers and drive best practices across synthesis and timing teams.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nRequired Skills\nTechnical ExpertiseStrong knowledge of ASIC design flow: RTL → Synthesis → STA → P&R.\nProficiency in synthesis tools (Design Compiler, Genus) and STA tools (PrimeTime).\n\nLow-Power DesignExperience with UPF/CPF-based flows and multi-voltage designs.\n\nScriptingAdvanced skills in Tcl, Perl, Python for automation.\n\nEDA ToolsFamiliarity with Spyglass, Lint, CDC tools, and power analysis tools.\n\nLeadershipAbility to lead synthesis teams and coordinate with cross-functional groups.\n\nEducationBachelor’s/Master’s in Electrical Engineering, Computer Engineering, or related field.\n\nExperience15+ years in ASIC synthesis and timing closure, with at least 3 years in NPU or AI processor design.\n\nPreferredExperience with advanced nodes (5nm/3nm), hierarchical synthesis, and physical-aware flows.\nPrior tape-out experience for NPU or DSP cores.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SoC Validation Associate, SSG", "company": "Amazon", "location": "Bengaluru, Karnataka, IND", "date_posted": "2026-05-05", "url": "https://www.amazon.jobs/en/jobs/10411580/soc-validation-associate-ssg", "is_hardware": true, "platform": "amazon", "jd_text": "The team that built the innovative Silicon IP AZ1 Neural Edge powering the latest generation of Echo devices is looking for an SoC Lab Validation Technician to support post-silicon validation and lab operations as we continue to innovate on behalf of our customers.\n\nWe are part of Amazon Lab126 that revolutionized reading with Kindle and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge.\n\nWork hard. Have fun. Make history.\n\nKey job responsibilities\nPerform board-level rework on SoC development and validation platforms, including component soldering, desoldering, wire modifications, and connector replacements\nSet up and operate lab equipment such as DC power supplies, oscilloscopes, logic analyzers, multimeters, and signal generators for silicon validation and debug\nExecute pre-defined test scripts and validation test plans on emulation, prototyping, and early silicon platforms\nAssist in silicon bringup activities including power sequencing verification, clock measurement, and basic functional checkout\nBuild, configure, and maintain lab test setups and prototype hardware platforms\nPerform board-level debug under the guidance of senior validation engineers, including probing signals, capturing waveforms, and documenting observations\nMaintain lab inventory, manage equipment calibration schedules, and ensure lab safety compliance\nDocument test results, rework procedures, and debug findings in a clear and structured manner\nSupport automation of repetitive lab tasks using basic scripting (Python, shell scripts)\n\nBasic qualifications\n- 3+ years of hardware development, test lab, space/aerospace maintenance or hands-on engineering environment experience\n- Experience in motherboard design, PCB design including schematic capture, stackup and circuit board layout\n- Knowledge of tools and measurement devices (oscilloscope, frequency analyzer, or equivalent)\n- Experience developing high quality test plans, test designs, test strategies, and test execution\n- Knowledge of concepts like system architecture, optimization, system dynamics, system analysis, statistical analysis, reliability analysis, electronic system design, and decision making\n- Experience in reading and understanding schematics and building drawings\n- Experience that includes strong analytical skills, attention to detail, and effective communication abilities, or experience troubleshooting and debugging technical systems\n- Experience in automation via Bash/shell scripting and Perl/Python programming\n- Diploma or Bachelor's degree in Electronics, Electrical Engineering, Electronics & Communication, or a related discipline\n\nPreferred qualifications\n- Experience with post-silicon validation\n- Familiarity with ARM-based development boards or embedded platforms\n- Experience with JTAG, SWD, UART, I2C, SPI, or other common debug/communication interfaces\n- Exposure to thermal testing, power measurement, or reliability testing setups\n- Experience with version control systems (Git) and issue tracking tools\n- Familiarity with bare-metal firmware loading and basic boot flow debug\n- Knowledge of ESD-safe handling procedures and cleanroom/lab protocols\n- Strong written and verbal communication skills for documenting procedures and collaborating across teams\n\nOur inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.", "jd_status": "refreshed"}, {"title": "Staff Validation Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-05-05", "url": "https://careers.synopsys.com/job/bengaluru/staff-validation-engineer/44408/94739576336", "is_hardware": true, "platform": "talentbrew", "jd_text": "Staff Validation EngineerWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou thrive on seeing silicon work in the lab, not just in simulation. You dig into waveforms, logs, and protocol traces until the root cause is crystal clear. You trust your scripts more than your manual test cases, and you automate the boring parts so you can focus on the real puzzles—like why a Gen4 link won’t train or what’s behind that intermittent BER spike at 25Gbps. You jump at the chance to use Python and MATLAB to make sense of messy data, and you’re just as comfortable getting hands-on with oscilloscopes and protocol analyzers as you are reading code. You don’t shy away from gnarly bring-up bugs or cross-team debug calls because you know the right questions to ask and you collaborate until the issue is nailed. You care about compliance as much as performance, and you’re the one who double-checks the test plan against the latest PCIe or IEEE spec. If you’ve ever stayed late to correlate a lab measurement with a simulation, or built a tool because nothing off-the-shelf was good enough, you’ll fit right in.\nWhat You'll Be Doing\nCarrying out pre-silicon and post-silicon validation for high-speed SerDes, PCIe (Gen3/4/5), and multi-speed Ethernet IP, driving real bring-up and debug on advanced silicon platforms.\nCreating, executing, and automating validation test plans using Python and C, ensuring protocol compliance, robust error handling, and peak IP performance.\nBuilding SDK-driven test environments to validate firmware-controlled features and software-configurable parameters, automating regressions, stress tests, and recovery scenarios.\nUsing MATLAB to analyze simulation and silicon data, including eye diagrams, jitter, BER, and validating signal processing algorithms.\nDebugging protocol and system-level issues across hardware, RTL, firmware, and software, leveraging custom tools, internal scripts, and hands-on lab equipment.\nCollaborating with RTL, architecture, firmware, and emulation teams to solve tough debug challenges and improve validation methodologies.\nMentoring junior engineers and contributing to silicon readiness reviews and customer-facing debug/support activities.\nThe Impact You Will Have\nCatching issues in the lab and in simulation before they reach customers, directly improving the quality and reputation of Synopsys Interface IP.\nEnabling industry-leading SoCs to hit aggressive performance, power, and compliance targets in networking, data center, automotive, and compute markets.\nDriving automation that increases test coverage and repeatability, freeing the team to focus on innovation instead of repetition.\nAccelerating time-to-silicon by correlating simulation, emulation, and silicon results, reducing costly debug cycles.\nRaising the bar on validation methodology and protocol debug, making the team more effective with every project.\nSupporting customer teams with deep technical insight, ensuring successful silicon integration and adoption.\nSharing your technical know-how, you’ll help build a stronger, more capable validation team.\nWhat You'll Need\nM.Tech or B.Tech in Electronics, Electrical, or related engineering field.\n5+ years hands-on experience in pre-silicon and post-silicon validation or verification of high-speed interface IP (SerDes, PCIe, or Ethernet).\nStrong scripting and automation skills in Python; solid C programming for low-level and SDK-based validation.\nPractical experience with MATLAB for data postprocessing, signal analysis, and algorithm validation.\nDirect experience with lab equipment: high-speed oscilloscopes, BERTs, protocol analyzers, and custom evaluation boards.\nExperience with protocol debug at the transaction, link, and physical layer (PCIe, Ethernet, or similar).\nFamiliarity with industry standards/specs like PCI-SIG and IEEE Ethernet is a plus.\nWho You Are\nYou turn ambiguous failures into actionable debug plans and don’t stop until you know why something broke.\nYou automate first and ask “why are we doing this by hand?” in every validation cycle.\nYou move fluidly between scripting, lab work, and cross-team collaboration, adapting your approach to the problem at hand.\nYou can explain a protocol-level bug or spec compliance gap to design, firmware, or customer teams—without losing the technical nuance.\nYou keep your test plans and analysis rooted in real-world spec compliance, not just “happy path” scenarios.\nYou lift up junior engineers, sharing your process and tools so the whole team levels up.\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "ENGR STAFF, ANALOG; DSGN ", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-05-04", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505349", "is_hardware": true, "platform": "oracle", "jd_text": "We are seeking a highly motivated Analog Design Engineer with 5–8 years of experience in non-volatile memory (NVM) design, including EEPROM, Flash, or emerging memories such as ReRAM. The candidate will contribute to the design and development of high-performance, reliable memory IPs for advanced applications, including automotive and industrial systems.\n\nRequired Qualifications\n\nBachelor’s or Master’s degree in Electrical Engineering or related field\n\n5–8 years of experience in analog/mixed-signal IC design\n\nStrong experience in NVM technologies such as EEPROM, Flash, or ReRAM\n\nSolid understanding of:\n\nDevice physics and reliability (e.g., breakdown, aging, retention)\n\nHigh-voltage analog design techniques\n\nProficiency in industry-standard tools (e.g., Cadence Virtuoso, Spectre, APS)\n\nExperience with layout collaboration and parasitic-aware design\n\nStrong debugging and problem-solving skills\n\n#L1-LK1\n\nResponsibilities\nKey Responsibilities\n\nDesign and develop analog and mixed-signal circuits for NVM IPs (EEPROM, Flash, ReRAM)\n\nArchitect and implement key building blocks such as:\n\nCharge pumps, voltage regulators, bandgaps, oscillators\n\nSense amplifiers, reference circuits, and biasing schemes\n\nCollaborate with digital, layout, and validation teams to deliver silicon-proven designs\n\nPerform circuit simulations (DC, AC, transient, Monte Carlo, corner analysis) to ensure robustness across PVT conditions\n\nDrive design reviews, failure analysis, and silicon debug activities\n\nSupport test vehicle development and participate in characterization and qualification\n\nEnsure compliance with reliability and automotive standards (e.g., AEC-Q100 where applicable)\n\nContribute to design methodology improvements and documentation\n\n#L1-LK1\n\nQualifications\nBachelor’s or Master’s degree in Electrical Engineering or related field\n\n \n\n#L1-LK1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "ENGR STAFF, ANALOG; DSGN", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-05-04", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505350", "is_hardware": true, "platform": "oracle", "jd_text": "Role Overview\n\nWe are seeking a highly motivated Analog Design Engineer with 5–8 years of experience in non-volatile memory (NVM) design, including EEPROM, Flash, or emerging memories such as ReRAM. The candidate will contribute to the design and development of high-performance, reliable memory IPs for advanced applications, including automotive and industrial systems.\n\nRequired Qualifications\n\nBachelor’s or Master’s degree in Electrical Engineering or related field\n\n5–8 years of experience in analog/mixed-signal IC design\n\nStrong experience in NVM technologies such as EEPROM, Flash, or ReRAM\n\nSolid understanding of:\n\nDevice physics and reliability (e.g., breakdown, aging, retention)\n\nHigh-voltage analog design techniques\n\nProficiency in industry-standard tools (e.g., Cadence Virtuoso, Spectre, APS)\n\nExperience with layout collaboration and parasitic-aware design\n\nStrong debugging and problem-solving skills\n\n#L1-LK1\n\nResponsibilities\nKey Responsibilities\n\nDesign and develop analog and mixed-signal circuits for NVM IPs (EEPROM, Flash, ReRAM)\n\nArchitect and implement key building blocks such as:\n\nCharge pumps, voltage regulators, bandgaps, oscillators\n\nSense amplifiers, reference circuits, and biasing schemes\n\nCollaborate with digital, layout, and validation teams to deliver silicon-proven designs\n\nPerform circuit simulations (DC, AC, transient, Monte Carlo, corner analysis) to ensure robustness across PVT conditions\n\nDrive design reviews, failure analysis, and silicon debug activities\n\nSupport test vehicle development and participate in characterization and qualification\n\nEnsure compliance with reliability and automotive standards (e.g., AEC-Q100 where applicable)\n\nContribute to design methodology improvements and documentation\n\n#L1-LK1\n\nQualifications\nBachelor’s or Master’s degree in Electrical Engineering or related field\n\n \n\n#L1-LK1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Staff Application Engineer – Physical Implementation", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-05-04", "url": "https://careers.synopsys.com/job/bengaluru/staff-application-engineer-physical-implementation/44408/94448919552", "is_hardware": true, "platform": "talentbrew", "jd_text": "Alternate Job Titles:\nStaff Application Engineer – Physical Implementation\nSenior Implementation Solutions Engineer\nStaff Engineer – RTL-GDS Flow\nCustomer Success Engineer – EDA Tools\nTechnical Application Engineer – AI/ML Implementation\nWe Are:\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are:\nYou are energized by the hard problems—the ones where constraints collide, priorities shift, and the “right” answer depends on making smart, explicit tradeoffs. You thrive in fast-moving environments because you bring structure without slowing momentum: you clarify the goal, identify the true blockers, and keep the work anchored to outcomes that matter. You don’t wait for direction when you see a gap. You step in, propose a path, and invite others into a shared plan that’s clear, realistic, and measurable.\nYou operate with a customer-first instinct that shows up in how you listen and how you act. You seek to understand the intent behind a request, not just the words, and you’re comfortable challenging assumptions when it protects the end result. You communicate with purpose—direct, calm, and tailored to your audience—so engineers get actionable detail while stakeholders get crisp decisions and timelines. When pressure rises, you stay steady and pragmatic, breaking complex issues into solvable pieces and keeping progress visible so trust stays high.\nYou’re a natural connector across teams. You enjoy translating between different perspectives, aligning people around shared definitions of success, and turning feedback into forward motion. You balance attention to detail with an instinct for the big picture, and you care as much about repeatable methodology as you do about the immediate win. Above all, you take ownership: you follow through, you close loops, and you leave things better than you found them.\nWhat You’ll Be Doing:\nSolving complex PPA (Performance, Power, Area) challenges using Synopsys’ latest implementation technologies, including AI/ML Implementation, Physical Synthesis RTL-GDS, Multi Source CTS, and Indesign Fusion.\nBenchmarking Synopsys solutions against competitors to displace alternative implementation flows and demonstrate superior results.\nDeveloping, debugging, and optimizing RTL-GDS implementation methodologies and flows for emerging semiconductor technologies.\nProviding technical solutions by identifying design and EDA tool issues and delivering actionable resolutions for customers.\nTranslating technical findings into requirements for R&D, driving tool enhancements and adaptive long-term solutions.\nDeploying new technology features in the latest EDA tool versions and enabling customer migration for best-in-class PPA.\nProactively identifying customer pain points and proposing innovative solutions to address them.\nCollaborating closely with Synopsys R&D and product development teams to shape future technology directions.\nActing as a customer advocate during internal discussions and as a brand ambassador when engaging externally.\nThe Impact You Will Have:\nElevating customer success by delivering robust technical solutions and enabling optimal tool utilization.\nDriving Synopsys’ competitive advantage by displacing rival implementation flows and showcasing superior PPA outcomes.\nContributing to the enhancement of Synopsys products by providing critical feedback and requirements to R&D.\nAccelerating customer adoption of new technology nodes and EDA tool versions to achieve best-in-class results.\nStrengthening Synopsys’ reputation as the industry leader in physical implementation and innovation.\nFostering long-term customer relationships through proactive engagement and continuous support.\nWhat You’ll Need:\nAt least 5+ years of experience in Physical Implementation (RTL-GDS), with proven ability to debug and resolve synthesis & PnR challenges.\nStrong exposure to methodology changes aimed at achieving targeted PPA metrics for complex designs.\nProficiency in Synopsys implementation tools and flows is highly advantageous.\nAdvanced scripting skills (TCL, Unix, Perl) for automation and debugging.\nExcellent communication skills, including the ability to interface effectively with customers and internal teams.\nWho You Are:\nSelf-motivated and dedicated, with a passion for continuous learning and improvement.\nStrong analytical thinker with outstanding debug skills and attention to detail.\nCollaborative team player who thrives in dynamic, fast-paced environments.\nCustomer-centric, always advocating for the best outcomes and solutions.\nResilient and adaptable, able to manage multiple priorities and deliver results.\nThe Team You’ll Be A Part Of:\nJoin our Application Engineering team in Bangalore, where you’ll work directly with industry pioneers and innovators. The team’s mission is to solve critical design challenges, enhance quality-of-results metrics, and empower customers to achieve best-in-class performance. Collaboration with R&D and product development is central, ensuring that customer needs drive future technology advancements. Together, we set the standards for excellence in semiconductor design and implementation.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior Staff Engineer Verification", "company": "Infineon", "location": "Bangalore BTP (India)", "date_posted": "2026-04-30T03:37:44+00:00", "url": "https://jobs.infineon.com/careers/job/563808970577854", "is_hardware": true, "platform": "eightfold", "jd_text": "#WeAreIn to make sure that our circuits are designed to perfection.​ Are you in?\n\nYour Role\n\nKey responsibilities in your new role\n\nVerification of complex SoCs / IPs and provide technical leadership to the team while creating test plans and test bench architecture.\nDevelopment of constraint-random verification environment at both sub-system and SoC level.\nDevelop expertise in multiple areas of verification – RTL, Gate level and Power aware simulations\nDrive verification closure on complex modules and SoCs using SV/UVM based methodology.\nSchedule management and handling cross functional team interactions\nShould be a good mentor and guide for junior engineers in the team\n\nYour Profile\n\nQualifications and skills to help you succeed\n\nB.E./B.Tech/M.E./M.Tech in Electrical/Electronics Engineering Bachelor's - 9 to 11 years’ experience, Master’s - 8 to 10 years’ experience\nIn depth understanding of ASIC verification concepts and techniques. Ability to architect complex module / sub system / full chip testbenches and build verification infrastructure in SV/UVM.\nShould be a good mentor and guide the junior engineers in the team.\nExperience in ARM based SoC verification covering RTL, Power Aware and Gate level simulations is a plus.\nGood knowledge in industry standard protocols is preferable\n\nContact:\n    Keerthini.Gowda@infineon.com\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\nThis means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.\nPlease let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.\nClick here for more information about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "LPDDR IP Design Principle Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-04-30", "url": "https://careers.synopsys.com/job/bengaluru/lpddr-ip-design-principle-engineer/44408/94561854112", "is_hardware": true, "platform": "talentbrew", "jd_text": "Synopsys is at the heart of all the advanced silicon design, we supply the essential tools and intellectual properties to enable the semiconductor design, verification, and production. We’re powering all state-of-the-art design market with the world’s most advanced technologies for chip design and software security.\n \nLPDDR PHY IP is a staple of the mixed-signal IP market, and Synopsys is the leading provider of LPDDR PHY IP products.  All current and next-generation technologies are being developed by the LPDDR PHY IP team, both digital and analog components, complement each other in creating a high-performance, high-bandwidth, low-latency and low-power products.\n \nWe are looking for Sr. Staff ASIC Digital Design Engineer to join Synopsys LPDDR PHY IP team to innovate and develop the latest world-class market-leading DesignWare LPDDR PHY IP solution. Be part of a global diverse team that pushes boundaries on LPDDR PHY IP development and solution, your passion and expertise will shape the next generation of product innovation, performance, and efficiency.\n \n \nJob Description\n \nIn this role, you will be in a leadership role to contribute to all phases of designs of DDR PHY IP from design specification to productization, including certain level of customer support into their SoCs.\nDesigning and micro-architecting LPDDR PHY IP writing Verilog and SystemVerilog code and design specification\nConduct simulation and analysis of designs working with Verification, Timing, DFT, and Power team members\nAnalyzing and fixing Lint, CDC/RDC, DFT, Timing, and power issues\nMaintain and improve design automating flow and process\n \nRequired Skills\n \nBS in Electrical Engineering and a minimum of 10 years of experience in complex technical development \nExperience with synthesizable Verilog and System Verilog design concepts, coding, and implementation\nExperience with front-end design flows such as linting, synthesis, timing investigation and closure, cross-domain clocking, DFT, and power optimization techniques\nExhibit excellent communication skills and be self-motivated\nUnderstanding of memory and memory PHY architecture is a plus", "jd_status": "stored"}, {"title": "System Modelling Engineer", "company": "Intel", "location": "India, Bangalore", "date_posted": "2026-04-30", "url": "https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/System-Modelling-Engineer_JR0283512-1", "is_hardware": true, "platform": "workday", "jd_text": "Job Details:\n\nJob Description: \nThe Role and Impact:\n\nAs an Analog and Mixed Signal IP Architect, you will play a pivotal role in shaping the future of Intel's cutting-edge technologies. You will be responsible for driving innovative architectures and algorithms that define the next generation of System-on-Chip (SoC) independent analog and mixed signal IPs.\nWe are seeking an experienced SerDes PHY System Modeling Engineer to lead and support the architecture, modeling, and performance analysis of 224Gbps SerDes IP. This role focuses on endtoend PHY system modeling, including electrical channel, transmitter (TX), receiver (RX), equalization strategies, clocking, and jitter/noise analysis, enabling robust silicon implementation for nextgeneration ASICs and SoCs.\n\nKey Responsibilities:\nSystem Architecture and Modeling: Develop endtoend behavioral models for 224Gbps SerDes PHYs across TX, channel, and RX. Build statistical and timedomain system models to evaluate BER, eye margins, and link robustness\nDefine PHY performance budgets (jitter, noise, ISI, crosstalk, insertion loss)\nModel and optimize PAM4 signaling at very high data rates\n\nChannel and Equalization Analysis: Model electrical channels including packages, PCBs, connectors, and crosstalk. Develop and tune TX FIR, RX CTLE, DFE, and adaptive equalization algorithms\nPerform Swept channel analysis to ensure compliance across worstcase conditions\nSupport cooptimization of channel, package, and PHY architecture\n\nClocking, Jitter and Noise Analysis: Model PLL/DLL behavior, phase noise, and jitter transfer functions\nPerform jitter decomposition (RJ, DJ, PJ, SJ) and bathtub curve analysis\nAnalyze CDR performance, loop dynamics, and tolerance to jitter/noise sources\n\nCompliance and Standards Support: Support modeling and interpretation of industry standards (IEEE, OIF, etc.), including 224Grelated efforts\nDefine channel and compliance test methodologies\nAlign system models with compliance test specifications and silicon validation strategies\n\nWork closely with circuit designers, DSP/algorithm teams, package/PCB engineers, and validation teams\nTranslate systemlevel requirements into blocklevel and circuitlevel specs\nSupport silicon bringup and debug through correlation of lab data with system models\n\nQualifications:\nMinimum Qualifications:\n\n- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related specialized field, and 12+ years of relevant experience; or Master's degree and 8+ years of relevant experience; or PhD and 4+ years of relevant experience.\n- Proficiency in analog circuit design, including TX/RX blocks and system-level understanding.\n- Expertise in architecture modeling and high-speed design techniques.\n- Demonstrated ability to model, simulate, and optimize performance, power, and area for analog and mixed signal IPs.\n\nPreferred Qualifications:\n\n- Strong leadership and collaboration skills with experience in influencing cross-functional technology roadmaps.\n- Solid analytical and problem-solving abilities with a track record of delivering innovative solutions.\n- Effective communication skills to articulate architectural features and tradeoffs to design teams and stakeholders.\n- A passion for advancing technology and contributing to Intel's mission of innovation and excellence.\n\nTake the next step in your career by applying today. Join us in shaping the future of analog and mixed signal IP and making a lasting impact on the semiconductor industry.\n\n          \n\nJob Type:\nExperienced Hire\n\nShift:\nShift 1 (India)\n\nPrimary Location: \nIndia, Bangalore\n\nAdditional Locations:\n\nBusiness group:\nThe Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.\n\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.\n*\n\nADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.", "jd_status": "stored"}, {"title": "Formal Verification Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-04-30", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Formal-Verification-Engineer_JR2017178", "is_hardware": true, "platform": "workday", "jd_text": "We are currently seeking an experienced Formal Verification Engineer with strong CPU/GPU and verification fundamentals to work in NVIDIA's Central Formal team based in Bangalore. NVIDIA builds CPUs and GPUs  that powering up the next generation AI and HPC workloads. This position will have you crafting and optimizing formal verification flows across CPU/GPU projects and resolving tool issues for design teams with tool vendors. Additionally, you'll verify the micro-architecture using formal verification tools to employ the latest model checking and equivalence checking techniques. You will be expected to understand the design & implementation, define the verification scope, and ensure design correctness. You will use advanced formal techniques to obtain full proofs, or sufficient bounded proofs, of the design while working with architects, designers, pre- and post-silicon verification teams to accomplish your tasks.\n\nWhat you’ll be doing:\nThe specification, implementation, and maintenance of an integrated end-to-end formal verification flow for the formal verification team.\n\nDeveloping scripts to automate the verification process.\n\nReview formal setups and proofs with design and verification teams.\n\nMaintain and extend assertion libraries, including support for both simulation and FV.\n\nIdentifying key behaviours for verification of DUT and creating a verification plan.\n\nDeveloping verification environment including environment assumptions, assertions and cover properties in context of the verification plan.\n\nApplying various FV techniques to prove correctness of digital designs.\n\nDebugging RTL to identify causes of failure scenarios.\n\nWhat we need to see:\nBachelors/Masters in Electronics & Communications or Computer Science or electrical engineering from a reputed engineering college.\n\nMinimum 1+ years of industry experience on formal techniques for verification.\n\nStrong analytical skills to tackle hard problems.\n\nExcellent command of scripting.\n\nStrong knowledge of architectures of CPU designs and digital logic.\n\nGood understanding of abstraction techniques for effective verification.\n\nHands-on experience with HDLs such as Verilog / System Verilog.\n\nUnderstanding of temporal logic assertions.\n\nPreferable experience with a variety of Formal Verification Tools\n\nStrong communication skills are required along with the ability to work in a dynamic product oriented team and collaborate effectively across sites.\n\nWays to stand out from the crowd:\nWorked on various pieces of CPU/GPU unit/microarchitecture verification\n\nBackground with complex verification projects that had used formal techniques for closure.\n\nExperience of collaborating with geographically diverse cross-functional teams\n\nA history of mentoring junior engineers and interns a huge plus.\n\nWith competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us and, due to unprecedented growth, our elite engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.", "jd_status": "stored"}, {"title": "Validation Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-04-29", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010142", "is_hardware": true, "platform": "oracle", "jd_text": "About TI\nTexas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world’s brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We’re committed to building a better future – from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. In TI’s Power Products, we’re developing breakthrough technology to power the world’s future innovations as well. Put your talent to work with us – change the world, love your job!\n\nWhy Mid-Vin Buck (MVB):\n\nEnterprise, Industrial, Personal Electronics, Artificial Intelligence and Autonomous Driving are just a few of the trends driving the need for high current mid-voltage regulators. The Mid-Vin Buck product line is focused on bringing to market the optimized power package solution for improved performance, reliability, and throughput. The Mid-Vin Buck team actively collaborates with TI’s advanced technology, packaging, and research and development teams to deliver the highest power density solutions for the power level.  \n\nAbout the job\nAt TI, Validation Engineers leverage strong technical knowledge working hands-on to bring differentiated power solutions to our customers globally. Validation Engineers also partner closely with Design, Test, Systems and Application engineers to ensure our power solutions are both meeting customer and market requirements and are technically and cost-wise optimized. The validation engineer in MVB has to evaluate the system-level performance also for enterprise computing.\n\nAbout the role and team:\n\nDevelop validation board, schematics and layout, matching it with customer use-case & applications. The validation boards include - modularization of the Val board for generic flow, solving mixed-signal challenges, scalability of HW for a large number of setups and most importantly closeness to the customer EVMs. \n\nBuild, design, and document the full validation plan. The validation plan needs a detailed understanding of not only the device but also the system environment.\n\nDefine the Validation Strategy in terms of Hardware, Software and Instrumentation\n\nBuilding Validation test cases and implementing them on different scripting languages. (i.e. Python, Test stand, Labview etc.)\n\nBring the device on the bench; Perform system level and parametric test on the bench with a strong break-the-part mentality.\n\nWork with design and Firmware team to support customer needs, and implement custom features in FW. Close collaboration with FW and application teams to understand the device issues and bugs and find the FW-level workaround for the fix.\n\nDebug device and setup-related issues and drive the issue to closure independently\n\nEngaging on customer issues and fixes with application engineers, to help them understand the device better, help to fix the issues and provide modifications if any tweaks are needed. This is done in collaboration with application engineers. \n\nTeam leading skillset along with mentoring and guiding junior engineers in the team.\n\nQualifications\nMinimum requirements:\n\nBachelor’s degree in Electrical Engineering or related field of study\n\n5+ years of relevant experience; 8+ preferred.\n\nPreferred qualifications:\n\nExperience in validation engineering of analog products\n\nDemonstrates hardware debugging skills.\n\nExcellent time management; Strong written and verbal communication skills\n\nExperience in simulating and designing inverters and/or DCDC converters\n\nKnowledge of semiconductor power switches like MOSFET, IGBT, and SiC MOSFET\n\nExpertise in tools e.g. Simplis, Matlab, Altium, PSPICE, LabView, Python\n\nSchematic and PCB layout design in Altium.\n\nPhysical layout management, signal grounding and routing tradeoffs, optimization\n\nMust budget time, manage schedule and complete complex design tasks on time\n\nMust have depth of experience and meticulous approach to ensure high-quality results\n\nMust account for limitations of system-level specifications, testability, and debug\n\nMust work well with colleagues and customers to foster a highly creative, interesting, productive, and fun working environment\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Design Verification Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-04-29", "url": "https://careers.arm.com/job/bengaluru/design-verification-engineer/33099/94510175888", "is_hardware": true, "platform": "talentbrew", "jd_text": "Design Verification Engineer\nThe Architecture and Technology Group (ATG) at Arm develops technologies that shape Arm’s future architecture roadmap. As new architecture specifications evolve, compliance testing, verification of the architectural features using random instruction sequencing tools and early RTL prototypes running on simulation/FPGA/emulation platforms are critical for evaluating architectural features for performance and functionality.\nRole Overview\nThe Architecture and Technology Group (ATG) is seeking a talented Design Verification Engineer to join the verification enablement team. In this role, you will verify the new Arm architectural features using inhouse random instruction simulators supporting a variety of internal and external partners with their design verification. You will also verify RTL prototypes implementing upcoming features in the ARM architecture, ensuring both new functionality and existing features meet architectural requirements. Features under test may span any part of the ARM architecture, so adaptability and the ability to work across multiple functional units are essential. A strong will to learn, coupled with a growth mindset to refine and adapt verification strategies, is key to success in this role.\nDo you want to shape the future of the Arm compute technologies that will enable the next revolution in computing? Here is an opportunity to contribute and learn immensely while at it.\n \nKey Responsibilities\nCollaborate closely with the tools teams, design verification and the RTL prototyping team in different geography\nUnderstanding the complex inhouse RIS tools and the utilities surrounding this and create meaningful stimulus with the help of these tools to uncover corner case bugs in the partner environments\nDevelop new verification environments and enhance existing verification environments, including stimulus generators, and checkers\nVerify new ARM architecture features function as specified and do not impact existing functionality\nExecute verification strategies in partnership with other verification engineers\nContribute to continuous improvement in verification methodology based on learnings\n \n \nRequired skills and qualifications\nGood university Degree in Microelectronics, Electrical Engineering or Computer Engineering. Other Science graduates would be considered if they have relevant experience.\n3-6 years of proven experience in an IP/SOC product development environment\nStrong understanding of Computer Architecture concepts, including out-of-order CPU execution, caches, memory etc.  ARM A-profile architecture experience is a plus.\nStrong communication skills to collaborate with cross-functional and geographically distributed teams to accomplish tasks\nExcellent problem-solving skills and attention to detail\nDesire and flexibility to learn a variety of verification especially RIS methodologies, RTL designs under test, architecture features, familiarity with testbench development for verifying RTL using any standard verification methodology\nGood to have skills and qualifications\nPrior experience verifying micro-architecture of IPs/sub-systems, such CPUs/GPUs, interconnects etc. is a plus.\nExperience with Verilog/System Verilog  HDLs, C/C++ is strongly recommended\nAssembly language experience, such as with ARM or x86 is preferred\nExperience with RTL verification using UVM methodology is desired\nExperience with industry standard simulation tools like VCS, Questa is desired.\nExperience with common scripting languages such as Perl or Python\nExperience with developing/reviewing test plans to verify micro-architecture and executing the plan in a predictable manner to meet objectives\nExperience with test generators, toolkits for ARM CPU validation such as Raven/ACK is a plus\nExperience with running and debugging workloads on FPGA platforms or silicon is a bonus\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Test Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-04-29", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010140", "is_hardware": true, "platform": "oracle", "jd_text": "Lead Test Engineer  – Switching Regulator \n\n \n\nAbout TI\nTexas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world’s brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We’re committed to building a better future – from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. In TI’s Power Products, we’re developing breakthrough technology to power the world’s future innovations as well. Put your talent to work with us – change the world, love your job!\n\nWhy Mid-Voltage Regulators\n\nEnterprise, Industrial, Personal Electronics, Artificial Intelligence and Autonomous Driving are just a few of the trends driving the need for high current mid-voltage regulators. The Mid-Vin Buck product line is focused on bringing to market the optimized power package solution for improved performance, reliability, and throughput. The Mid-Vin Buck team actively collaborates with TI’s advanced technology, packaging, and research and development teams to deliver the highest power density solutions for the power level.  \n\nAbout the job\nAt TI, Test Engineers leverage strong technical knowledge working hands-on to bring differentiated power solutions to our customers globally. Test Engineers also partner closely with Design, Validation, Systems and Application engineers to ensure our power solutions are both meeting customer and market requirements, and are technically and cost-wise optimized.\n\nAbout the role and team:\n\nWork with design team to understand design specifications\n\nGenerate test plan, create test and char program, design ATE hardware interface boards\n\nDebug & characterize silicon on ATE, correlate results with bench data\n\nAnalyze silicon results, supporting failure analysis tasks\n\nPerform statistical analysis of yield fallout, debug and fix yield issues; optimize test time\n\nWork with production team to release products to volume production\n\nTest strategy definition and implementation for new DCDC converter products\n\nATE (Automatic Test Equipment) test hardware and software knowledge base\n\nSilicon qualification & characterization including qual hardware development\n\nComprehensive device debugging, design validation and failure analysis\n\nDrive for robust and cost-effective test solutions while being accountable for product quality", "jd_status": "source_unavailable"}, {"title": "Senior Verification Engineer", "company": "MediaTek", "location": "Bangalore", "date_posted": "2026-04-28T16:00:00+00:00", "url": "https://careers.mediatek.com/en/jobs/MTB120260429001", "is_hardware": true, "platform": "mediatek", "jd_text": "Description\n•\tImplement Verification plans from Design specification\n•\tAbility to Innovate and contribute new ideas to improve and enhance the design & flow\n•\tAbility to create IPCRV environments\n•\tAbility to comprehend Complicated Specifications\n•\tUnderstanding of 3GPP standards or Serdes is a plus\nAcademic Requirement\n\tMasters or Bachelor Degree in Electronics or Communication related stream\n\t4 to 10 years of Digital Hardware Verification Experience", "jd_status": "stored"}, {"title": "Principal Physical Design Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-04-28", "url": "https://careers.synopsys.com/job/bengaluru/principal-physical-design-engineer/44408/94499266080", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nYou are an accomplished engineer with a passion for physical design and a drive to solve complex challenges in advanced semiconductor technology. With 12+ years of hands-on experience in the complete RTL-to-GDS flow, you thrive on collaborating with customers and internal teams to deliver innovative, high-value solutions. Your expertise spans advanced nodes, synthesis, design planning, and place & route, complemented by a strong command of timing closure, power reduction methodologies, DRC rules, and formal verification. You are adept at leveraging industry-leading EDA tools such as Fusion Compiler, PrimeTime, PrimeClosure, Formality, DSO.ai, FusionAI, ICV, StarRC, and RTLA, and you are well versed with AI/ML applications, building and deploying AI Agents.\nWhat You’ll Be Doing:\nEngaging directly with Synopsys customers to understand their design goals, challenges, and requirements, building tailored solutions that maximize their productivity and success.\nDemonstrating the unique advantages and capabilities of Synopsys’ industry-leading physical design tools, including Fusion Compiler, PrimeTime, and DSO.ai, through hands-on support and customer enablement activities.\nCollaborating closely with Synopsys R&D and Product Engineering teams to influence tool development, provide feedback from the field, and drive enhancements that address real-world design challenges.\nDelivering technical presentations, workshops, and training sessions to empower customers and internal teams with best practices in synthesis, place & route, timing closure, and power optimization.\nDiagnosing and resolving complex design issues, providing expert guidance on advanced node challenges, DRC closure, ECO flows, and formal verification methodologies.\nContributing to the productivity and growth of the Application Engineering team by sharing expertise, developing technical collateral, and mentoring junior engineers.\n\nThe Impact You Will Have:\nAccelerate customer success by ensuring smooth adoption and optimal use of Synopsys’ physical design solutions across advanced technology nodes.\nDrive innovation in EDA tool development by channeling customer feedback and real-world requirements directly to Synopsys R&D teams.\nEnhance the industry’s most advanced chip design flows, enabling customers to achieve faster time-to-market and higher quality silicon.\nPosition Synopsys as a trusted partner and thought leader in physical design, strengthening long-term customer relationships and industry reputation.\nFacilitate knowledge transfer and skill development within the team, raising the overall competency and effectiveness of the Applications Engineering group.\nContribute to Synopsys’ business growth by showcasing the value and differentiation of Synopsys tools in competitive engagements and benchmark evaluations.\n\nWhat You’ll Need:\nBachelor’s and/or Master’s degree in Electrical Engineering or a related field.\n15+ years of experience with the complete RTL-to-GDS physical design flow, including advanced nodes.\nProficiency with industry-standard EDA tools: Fusion Compiler, PrimeTime, PrimeClosure, Formality, DSO.ai, FusionAI, ICV, StarRC, RTLA, and familiarity with Innovus, Genus, Tempus, Quantus, Cerebrus.\nIn-depth understanding of synthesis, design planning, place & route, timing closure, power reduction, DRC rules, static timing analysis, and ECO methodologies.\nExperience with LLMs, GPT models, and other generative AI techniques.\nStrong analytical and problem-solving skills, with the ability to diagnose and resolve complex design and tool issues.\nWho You Are:\nInnovative, resourceful, and proactive in driving technical solutions and continuous improvement.\nExcellent communicator, able to clearly articulate technical concepts to diverse audiences.\nCollaborative team player who thrives in a fast-paced, cross-functional environment.\nCustomer-focused mindset with a passion for delivering exceptional support and building lasting relationships.\nEffective mentor and knowledge sharer, committed to uplifting the team and advancing organizational goals.\nThe Team You’ll Be A Part Of:\nYou will join a high-impact Applications Engineering team focused on enabling customer success with Synopsys’ most advanced physical design solutions. This collaborative group works at the intersection of technology development and customer engagement, driving innovation and excellence in chip design across global semiconductor leaders. The team values knowledge sharing, mentorship, and continuous learning, fostering a supportive environment where everyone can make a significant impact.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Engineering, Principal Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-04-28", "url": "https://careers.synopsys.com/job/bengaluru/engineering-principal-engineer/44408/94499266224", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nYou are an accomplished engineer with a passion for physical design and a drive to solve complex challenges in advanced semiconductor technology. With 12+ years of hands-on experience in the complete RTL-to-GDS flow, you thrive on collaborating with customers and internal teams to deliver innovative, high-value solutions. Your expertise spans advanced nodes, synthesis, design planning, and place & route, complemented by a strong command of timing closure, power reduction methodologies, DRC rules, and formal verification. You are adept at leveraging industry-leading EDA tools such as Fusion Compiler, PrimeTime, PrimeClosure, Formality, DSO.ai, FusionAI, ICV, StarRC, and RTLA, and you are well versed with AI/ML applications, building and deploying AI Agents.\nWhat You’ll Be Doing:\nEngaging directly with Synopsys customers to understand their design goals, challenges, and requirements, building tailored solutions that maximize their productivity and success.\nDemonstrating the unique advantages and capabilities of Synopsys’ industry-leading physical design tools, including Fusion Compiler, PrimeTime, and DSO.ai, through hands-on support and customer enablement activities.\nCollaborating closely with Synopsys R&D and Product Engineering teams to influence tool development, provide feedback from the field, and drive enhancements that address real-world design challenges.\nDelivering technical presentations, workshops, and training sessions to empower customers and internal teams with best practices in synthesis, place & route, timing closure, and power optimization.\nDiagnosing and resolving complex design issues, providing expert guidance on advanced node challenges, DRC closure, ECO flows, and formal verification methodologies.\nContributing to the productivity and growth of the Application Engineering team by sharing expertise, developing technical collateral, and mentoring junior engineers.\nThe Impact You Will Have:\nAccelerate customer success by ensuring smooth adoption and optimal use of Synopsys’ physical design solutions across advanced technology nodes.\nDrive innovation in EDA tool development by channeling customer feedback and real-world requirements directly to Synopsys R&D teams.\nEnhance the industry’s most advanced chip design flows, enabling customers to achieve faster time-to-market and higher quality silicon.\nPosition Synopsys as a trusted partner and thought leader in physical design, strengthening long-term customer relationships and industry reputation.\nFacilitate knowledge transfer and skill development within the team, raising the overall competency and effectiveness of the Applications Engineering group.\nContribute to Synopsys’ business growth by showcasing the value and differentiation of Synopsys tools in competitive engagements and benchmark evaluations.\nWhat You’ll Need:\nBachelor’s and/or Master’s degree in Electrical Engineering or a related field.\n15+ years of experience with the complete RTL-to-GDS physical design flow, including advanced nodes.\nProficiency with industry-standard EDA tools: Fusion Compiler, PrimeTime, PrimeClosure, Formality, DSO.ai, FusionAI, ICV, StarRC, RTLA, and familiarity with Innovus, Genus, Tempus, Quantus, Cerebrus.\nIn-depth understanding of synthesis, design planning, place & route, timing closure, power reduction, DRC rules, static timing analysis, and ECO methodologies.\nExperience with LLMs, GPT models, and other generative AI techniques.\nStrong analytical and problem-solving skills, with the ability to diagnose and resolve complex design and tool issues.\nWho You Are:\nInnovative, resourceful, and proactive in driving technical solutions and continuous improvement.\nExcellent communicator, able to clearly articulate technical concepts to diverse audiences.\nCollaborative team player who thrives in a fast-paced, cross-functional environment.\nCustomer-focused mindset with a passion for delivering exceptional support and building lasting relationships.\nEffective mentor and knowledge sharer, committed to uplifting the team and advancing organizational goals.\nThe Team You’ll Be A Part Of:\nYou will join a high-impact Applications Engineering team focused on enabling customer success with Synopsys’ most advanced physical design solutions. This collaborative group works at the intersection of technology development and customer engagement, driving innovation and excellence in chip design across global semiconductor leaders. The team values knowledge sharing, mentorship, and continuous learning, fostering a supportive environment where everyone can make a significant impact.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Principal Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-04-27", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Design-Engineer_R54156", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Title: Principal Design Engineer\nLocation: Bangalore\n\nJob Summary:\nWe are looking for a candidate with excellent communication skills and ability to ramp up on new technologies quickly and independently. This position requires the technical expertise in DDR memory protocols such as DDR, LPDDR and particularly HBM. This an excellent opportunity to work in a supportive and friendly work environment, where we are vested in each other’s success, and are passionate about technology and innovation.\n\nPosition Description:\nFunctional Verification Engineer role for DDR Subsystem Verification team. Position is based in Bangalore.\n\nThe role would include functional verification of the DDR Subsystem that comprises of DDR Memory Controller and PHY IP solution of Cadence.\n\nThe work involved will be working with the existing functional verification environment, addition of new features into the verification environment, ensuring various customer configurations are clean as part of verification regressions, supporting customers in case of any issues with using the verification environment, and functional and code coverage.\n\nAs a part of delivery criteria, the engineer would need to provide Demosim testbench with standard test patterns that aid as a reference for customer for seamless integration of our IP’s.\n\nThe engineer would be responsible to ensure that the design is in line with the technical and quality requirements set for the team – particularly with respect to functional and code coverage.\n\nParticipate in technical discussions and represent verification team in all the discussions with internal and external customers.\n\nReview all technical deliverables from team members and guide team members to meet quality and the schedule.\n\nFully accountable for quality design verification as per the schedule.\n\nTrack the verification progress, identify potential risks, and mitigation plan.\n\nMentor and provide technical guidance to team working in the projects.\n\nContribute to verification process and methodology improvements to boost efficiency and productivity.\n\nPosition Requirements:       \nBE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.\n\n8+ years of Design Verification experience with SV/UVM\n\nStrong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.\n\nDesign Verification experience verifying complex designs and leading projects from concept to verification closure.\n\nShould have knowledge on all aspects of verification components & verification metrics.\n\nStrong hands-on UVM and System Verilog coding experience and functional verification environment development is required.\n\nPrior RTL Design experience using Verilog is a must – so that the verification engineer is self-sufficient for most aspects of debugging.\n\nPrior experience in IP verification of memory IP (DDR/HBM/LPDDR) would be an added advantage.\n\nBehavioral skills required:\nMust possess strong written, verbal and presentation skills.\n\nGood communication and interpersonal skills, demonstrate teamwork and collaboration skills.\n\nAbility to establish a close working relationship with both customer peers and management.\n\nExplore what’s possible to get the job done, including creative use of unconventional solutions\n\nWork effectively across functions and geographies\n\nPush to raise the bar while always operating with integrity\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "RTL Design Graduate Intern", "company": "Tesla", "location": "Bengaluru, India ; India", "date_posted": "2026-04-27", "url": "https://hire-r1.mokahr.com/social-recruitment/tesla/100004142?#/job/588675e7-29ae-4595-a88e-3df52b810e7e", "is_hardware": true, "platform": "mokahr", "jd_text": "The Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities.\n\nHardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life.\n\nThe Tesla AI Hardware team is looking for a RTL Design Graduate Intern to work on industry leading AI accelerators. Candidate is expected to implement and document microarchitecture specifications, define system-level functional requirements, and deliver high quality design to achieve project targets.\n \nWhat You’ll Do\n\nMicro-architecture specification and design.\nDeliver Performance, Area and Power-efficient RTL design.\nSpecification, microarchitecture, and RTL design of complex subsystems and SOC.\nWork with the architecture and software teams to achieve design targets.\nBalance performance, power, safety, and cost requirements.\nTrade-off functional, physical and performance requirements.\nWork with cross-functional teams, including implementation, verification, and performance engineers.\nDesign for synthesis.\n\nWhat You’ll Bring\nHigh performance (low latency, high bandwidth) design techniques\nArea and power-efficient complex RTL design\nLow power microarchitecture techniques\nVerilog RTL logic design.\nExperience with simulators and waveform debug tools.\nKnowledge of logic design principles, including timing and power implications.\nDegree in Electrical Engineering, Computer Engineering, or equivalent experience.\nFresh Graduates are welcome\nRelevant internship experience is a plus\nFamiliarity with relevant IEEE standards and hardware interfaces is a plus.\nExperience with high speed SERDES or SOC design is a plus.", "jd_status": "stored"}, {"title": "SOC Verification Graduate Intern", "company": "Tesla", "location": "Bengaluru, India ; India", "date_posted": "2026-04-27", "url": "https://hire-r1.mokahr.com/social-recruitment/tesla/100004142?#/job/0bfd3a4a-7a32-4ebd-84f3-d47152284f32", "is_hardware": true, "platform": "mokahr", "jd_text": "What to Expect\n\nThe Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities.\n\nHardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life.\n\nThe AI Hardware team is looking for a SOC Verification Graduate Intern who will be responsible for pre-silicon RTL verification of block and top-level SOC. With a strong knowledge of SOC architecture and SOC verification methodologies, you will interact with multiple teams and build a metric-driven, configurable, and flexible verification environment. \n\nWhat You’ll Do\n\nWork with team members to define and set up a SOC-level verification environment.\nArchitect highly reusable UVM based test benches and integrate complex multi-instance VIPs, sub-system test benches, and test suites at the SOC level.\nWork with Design, Architecture, SW, FW and external IP delivery teams to efficiently integrate and verify the design.\nCreate coverage driven verification plans from specifications.\nExecute, review, and refine to achieve coverage targets.\nDefine and review verification and validation test plans created by other members of the team.\nAssist with Post-silicon validation and SOC bring-up.\nUnderstand details of High Efficiency SOC - Architecture, standard SOC peripherals and I/O (e.g. DDR, PCIe, USB), DMA, memory management schemes, multi-processor systems, Memory Controller Sub.\nSystems, PLL, power up and Secured Boot schemes.\n\nWhat You’ll Bring\nFresh Graduates are welcome, hands-on DV experience would be a plus.\nRelevant internship experience is a plus.\nStrong programming skills in UVM, C/C++, Python/Perl.\nExperience verifying CPU/GPU integration at the SOC level.\nCoherency verification at the SOC level.\nEmulation experience, working on available platforms such as Palladium, or Zebu.\nExperience in SOC bring-up and post-silicon verification.\nPost-silicon validation and SOC bring-up.\nHW/FW interaction verification.\nReset and power verification.", "jd_status": "stored"}, {"title": "Principal Engineer - PCIe RTL Design", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-04-27", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Principal-Engineer---PCIe-RTL-Design_2601483", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nMarvell Data Centre Engineering (DCE) - Compute & Storage (CCS) BU has been at the forefront of developing and delivering leading-edge, high performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast‐growing product lines, Marvell Technology is powering the next‐generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line\nWhat You Can Expect\nOwn and drive PCIe/CXL subsystem micro architecture definition, RTL implementation, and integration\nCollaborate closely with Architecture teams to translate requirements into robust RTL designs\nWork with Design Verification teams on test‑plan reviews, debug, and coverage closure\nPartner with Physical Design and DFT teams to ensure PD‑friendly and DFT‑ready RTL\nSupport silicon bring‑up and post‑silicon debug, working with firmware and validation teams\nDrive design quality improvements, coding best practices, and reuse across projects\nParticipate in design reviews, milestone reviews, and cross‑functional technical discussions\nMentor junior designers and provide technical leadership within the PCIe/CXL design domain\n\nWhat We're Looking For\nMaster’s/Bachelor’s degree in Electronics/Electrical Engineering with 18+ years of relevant experience in RTL design\nExperience on end‑to‑end PCIe/CXL subsystem RTL design execution and sign‑off\nProven experience delivering complex PCIe/CXL IP or subsystems from architecture through RTL closure\nStrong hands‑on experience in SystemVerilog / Verilog RTL development\nExpertise in PCIe protocol architecture including link, transaction, and PHY interaction layers\nStrong understanding of CXL.io, CXL.cache, and CXL.mem architectures\nDeep knowledge of ARM‑based SoC integration and AMBA protocols (AXI‑4, CHI, ACE)\nExperience designing high‑performance, low‑latency data paths and handling ordering, coherency, and error mechanisms\nSolid grasp of Clocking, Resets, CDC/RDC, low‑power techniques, and performance optimization\nExperience supporting lint, CDC/RDC, synthesis, and design sign‑off flows\nProficient in debugging functional and performance issues at subsystem and SoC levels\nExperience using industry‑standard EDA tools from Synopsys, Cadence, Mentor/Siemens\nProficient in scripting languages such as Tcl / Perl / Python\nExperience with version control systems such as GIT, SVN, etc.\n\nAdditional Compensation and Benefit Elements\nWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\n\nInterview Integrity \nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\n\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\n\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n\n#LI-CP1", "jd_status": "stored"}, {"title": "Staff Engineer - Analog Layout", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-04-23T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/41519371", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nKey Responsibilities\n\nTechnical Ownership\nLead full‑custom layout for complex Analog / Mixed‑Signal IP blocks, including but not limited to:Bandgap references, LDOs and regulators, Charge pumps (positive/negative)\nPLLs, delay lines, oscillators, IO & PHY‑related analog blocks\nTemperature sensors, bias circuits\nESD protection devices and clamps\n\nOwn layout quality from floor‑planning to tape‑out, ensuring:Device matching and symmetry, noise isolation and substrate strategies\nRobust power/ground planning\nYield, reliability, and DFM compliance\n\nWork closely with circuit designers to translate performance goals into layout strategies, especially in noise‑sensitive mixed‑signal environments.\n\nAdvanced Technology Expertise\nStrong experience in advanced FinFET nodes such as TSMC 3nm, 5nm, including:Fin quantization awareness\nMulti‑Vt, multi‑fin strategies\nAdvanced metal stack planning\n\nSolid background in planar CMOS technologies (e.g., 40nm, 65nm, 90nm) for analog robustness and legacy IP support.\nDeep understanding of foundry PDKs, layout‑dependent effects (LDEs), and process variability.\n\nLayout Verification & Signoff\nDrive and close DRC, LVS, ERC, ANTENNA, and reliability checks.\nReview and address issues related to:EM/IR, latch‑up, ESD window compliance\nDevice stress and matching degradation\n\nInterface with foundry and CAD teams for waiver management and signoff convergence.\n\nLeadership & Mentorship\nProvide technical guidance and design reviews for junior and mid‑level layout engineers.\nEstablish and document best‑known methods (BKMs) for AMS layout across nodes.\nDrive IP reuse, layout template development, and methodology improvements.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "Staff Engineer - Analog Layout", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-04-23T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/41519450", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nKey Responsibilities\n\nTechnical Ownership\nLead full‑custom layout for complex Analog / Mixed‑Signal IP blocks, including but not limited to:Bandgap references, LDOs and regulators, Charge pumps (positive/negative)\nPLLs, delay lines, oscillators, IO & PHY‑related analog blocks\nTemperature sensors, bias circuits\nESD protection devices and clamps\n\nOwn layout quality from floor‑planning to tape‑out, ensuring:Device matching and symmetry, noise isolation and substrate strategies\nRobust power/ground planning\nYield, reliability, and DFM compliance\n\nWork closely with circuit designers to translate performance goals into layout strategies, especially in noise‑sensitive mixed‑signal environments.\n\nAdvanced Technology Expertise\nStrong experience in advanced FinFET nodes such as TSMC 3nm, 5nm, including:Fin quantization awareness\nMulti‑Vt, multi‑fin strategies\nAdvanced metal stack planning\n\nSolid background in planar CMOS technologies (e.g., 40nm, 65nm, 90nm) for analog robustness and legacy IP support.\nDeep understanding of foundry PDKs, layout‑dependent effects (LDEs), and process variability.\n\nLayout Verification & Signoff\nDrive and close DRC, LVS, ERC, ANTENNA, and reliability checks.\nReview and address issues related to:EM/IR, latch‑up, ESD window compliance\nDevice stress and matching degradation\n\nInterface with foundry and CAD teams for waiver management and signoff convergence.\n\nLeadership & Mentorship\nProvide technical guidance and design reviews for junior and mid‑level layout engineers.\nEstablish and document best‑known methods (BKMs) for AMS layout across nodes.\nDrive IP reuse, layout template development, and methodology improvements.\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "SOC Engineering, Principal Engineer (STA)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-04-23", "url": "https://careers.synopsys.com/job/bengaluru/soc-engineering-principal-engineer-sta/44408/100672041152", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence—from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\n\nYou Are:\nYou are a passionate and execution-focused Static Timing Analysis (STA) engineer with strong fundamentals in timing closure and signoff methodologies. You bring 8+ years of hands-on experience in STA and timing/power closure for advanced nodes (e.g., 16/12/10/7nm; exposure to 5nm is a plus). You are comfortable owning key timing deliverables for blocks and contributing to full-chip closure in collaboration with physical design, synthesis, and verification teams.\n\nYou have solid experience across the timing closure lifecycle—constraints development and validation, STA signoff, power analysis, and ECO support—and you enjoy solving complex timing issues under aggressive schedules. You communicate clearly, work effectively with global teams, and are motivated to improve productivity through scripting/automation (TCL/Python/Perl).\n\nWhat You’ll Be Doing:\nOwn and execute block-level STA signoff and contribute to full-chip timing closure for advanced process nodes.\nPerform STA debugging and closure (setup/hold, recovery/removal, clock gating, CDC-related timing assumptions as applicable) and drive issue resolution with design/PD teams.\nDevelop, validate, and maintain timing constraints (SDC) including clocks, generated clocks, exceptions, IO constraints, and mode/corner coverage.\nRun and analyze power signoff/support flows (PrimePower / PT-PX) and correlate timing/power impacts of ECOs.\nSupport timing and power ECO generation, and validate fixes through signoff checks and regressions.\nWork with synthesis/implementation teams to ensure tool correlation and correct interpretation of constraints and physical effects (parasitics, SI awareness, AOCV/POCV, derates).\nUse Synopsys tools such as PrimeTime, PrimePower/PT-PX, PrimeClosure/Tweaker (as applicable) to meet PPA targets.\nBuild/maintain automation in TCL/Python/Perl to improve STA productivity, reporting, and regression quality.\nContribute to improving STA methodologies, checklists, and best practices; mentor junior engineers informally as needed.\n\nThe Impact You Will Have:\nEnable predictable and high-quality timing closure for high-performance, low-power silicon.\nImprove first-pass success through robust constraints, clean signoff, and disciplined closure practices.\nStrengthen team execution by contributing to repeatable STA flows, automation, and cross-team alignment.\nSupport successful project milestones through timely analysis, crisp communication, and ownership of deliverables.\n\nWhat You’ll Need:\nBachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics/Electrical Engineering or related field.\n10+ years of relevant experience in STA / timing closure (block ownership expected; full-chip exposure preferred).\nStrong hands-on experience in:\nConstraints development/validation (SDC)\nSTA signoff across modes/corners, including MMMC concepts\nTiming closure debugging and ECO validation\nPower analysis/support (PrimePower / PT-PX exposure preferred)\nProficiency with Synopsys tools such as PrimeTime (required); PrimePower/PT-PX, PrimeClosure/Tweaker (preferred).\nWorking knowledge/exposure to Fusion Compiler/ICC2 or DC, parasitic extraction concepts (e.g., StarRC), and signoff correlation (preferred).\nStrong scripting skills in TCL (required) and Python/Perl (preferred).\nUnderstanding of low-power and high-frequency design considerations (UPF awareness is a plus).\n\nWho You Are:\nSelf-driven, accountable, and comfortable working with minimal supervision on defined deliverables.\nStrong analytical and debugging skills with attention to detail.\nClear communicator and effective collaborator across design, PD, and verification.\nOpen to learning, improving flows, and sharing knowledge within the team.\n\nThe Team You’ll Be A Part Of:\nYou’ll join a team of backend and STA engineers focused on delivering robust timing and power closure solutions for leading silicon designs. The team values technical rigor, collaboration, and continuous improvement—working closely with experts across domains to help customers achieve their silicon goals.\n\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share details on compensation and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior validation engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-04-23", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505214", "is_hardware": true, "platform": "oracle", "jd_text": "We are seeking a highly motivated Senior Post-Silicon Validation Engineer to drive silicon bring-up, characterization, validation, and debug activities for mixed-signal image sensor products. The ideal candidate will possess strong expertise in bench validation, silicon debugging, validation automation, and cross-functional collaboration to ensure successful product qualification and release.\n\n \n\n#L1-LK1\n\nResponsibilities\nLead post-silicon bring-up, validation, characterization, and debug of mixed-signal and image sensor products. \nDevelop and execute validation plans to ensure product functionality, performance, and reliability. \nBuild and maintain validation platforms, test setups, and automation frameworks. \nPerform root cause analysis and drive resolution of silicon, hardware, firmware, and system-level issues. \nCollaborate with cross-functional teams including Design, Verification, Firmware, Product Engineering, and Manufacturing. \nAnalyze validation results, document findings, and provide recommendations for product improvements. \nContribute to validation methodology, automation, and process improvements. \nDrive innovation, technical excellence, and continuous improvement within the team. \nSupport product qualification and customer issue investigations as needed\n#L1-LK1\n\nQualifications\nBachelor's or master’s degree in electrical Engineering , Electronics Engineering, or a related field. \n5+ years of relevant industry experience in post-silicon validation, characterization, or bench validation of semiconductor products, including analog, digital, and mixed-signal blocks. \nStrong understanding of silicon bring-up, debug methodologies, and root cause analysis. \nHands-on experience with laboratory equipment such as oscilloscopes, signal generators, logic analyzers, spectrum analyzers, power supplies, and digital multimeters. \nExperience developing and executing validation and characterization plans to verify product functionality, performance, and reliability. \nProficiency in Python scripting for test automation, data collection, analysis, and validation workflow development. \nExperience working with common hardware interfaces and protocols such as I2C, SPI, UART, GPIO, MIPI, USB, or similar interfaces. \nStrong analytical, debugging, and problem-solving skills with the ability to independently drive issues to closure. \nDemonstrated ability to seek new ideas, drive innovation, and contribute to continuous improvement of validation methodologies, tools, and processes. \nExperience with image sensor validation, characterization, and debug is preferred. \nKnowledge of CMOS image sensor architecture, MIPI CSI-2, image quality characterization, sensor calibration, and optical validation is a plus. \nExposure to pre-silicon activities such as design verification, FPGA prototyping, or emulation is an added advantage. \nFamiliarity with validation automation frameworks, statistical data analysis, and characterization across voltage, process, and temperature corners is preferred. \nStrong communication, documentation, and technical leadership skills, including the ability to mentor junior engineers.\n#L1-LK1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Senior DFT Verification Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-04-23", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-DFT-Verification-Engineer_JR2011411", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.\n\nJoin NVIDIA, where we push the boundaries of what's possible! As a DFT Verification Engineer, you will be part of a team that is at the forefront of innovation in AI and accelerated computing. This role offers you the chance to contribute to groundbreaking projects while collaborating with some highly skilled professionals in the industry. Based in Bangalore, Karnataka, you will play a crucial role in ensuring the flawless execution of our dynamic projects. If you're ambitious and passionate about making an impact, this is the perfect opportunity for you!\n\nWhat you'll be doing:\nAs a valued member of our team, you will take end-to-end ownership of DFX verification, pattern development, and silicon bring-up for a range of test features—including JTAG, boundary scan, security mechanisms, reliability tests like HTOL/IDDQ and test clocking—across various test modes, including multiple ATPG configurations in multi-die environments.\n\nWork closely with various DFX teams, CAD, and methodology teams to improve the flows and processes.\n\nIn addition, you will help develop and deploy DFT methodologies for our next-generation products.\n\nBe a part of innovation to strive to improve the quality of DFT methods and AI deployment in the processes.\n\nYou will also need to work with multi-functional teams to incorporate DFT features into the chip.\n\nWhat we need to see:\nBSEE or MSEE from reputed institutions or equivalent experience with 3+ years of experience.\n\nYou should be proficient in static timing analysis, ECO, ASIC/Logic Design Flow, HDL, and Digital logic design.\n\nExperience in RTL and Gates verification, simulation, and silicon bring-up.\n\nYou need to be familiar with BIST architecture and JTAG/IEEE1149.1/1500/1687/1838.\n\nStrong DFT knowledge in Scan ATPG, compression techniques, and memory test.\n\nStrong analytical and problem-solving skills with good scripting knowledge (either Perl/Python).\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "SOC Engineering, Principal Engineer (STA)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-04-23", "url": "https://careers.synopsys.com/job/bengaluru/soc-engineering-principal-engineer-sta/44408/98572441696", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\n \nYou Are:\nYou are a passionate and driven STA Expert with a strong technical leadership and execution skills in Static Timing Analysis and design timing & power closure flows and methodologies. You have a proven ability to lead and deliver complex designs to tapeout. With at least 12 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges.\n \nYour expertise spans the entire timing closure spectrum—from constraints development, validation, static timing analysis (STA), power analysis, Timing & power ECO generation. You may also have good understanding and working experience of synthesis, and Formal verification. You have experience in both block-level and full-chip expertise, and you’re adept at developing and validating timing constraints and closing timing on aggressive schedules. Your toolset includes industry-leading Synopsys solutions like PrimeTime, PrimePower, PT-PX, PrimeClosure, Tweaker allowing you to deliver optimal solutions for high-frequency, low-power designs.\n \nBeyond your technical skills, you are a collaborative team player who communicates effectively across global teams, valuing diversity of thought and experience. You are motivated by problem-solving, have a keen analytical mindset, and are always seeking opportunities to automate and optimize workflows using Python, PERL, TCL, or other scripting languages. You take ownership of your work and pride yourself on delivering high-quality, robust solutions that drive organizational success. If you are excited about contributing to leading-edge silicon design and want to make a tangible impact, Synopsys is the place for you.\n \nWhat You’ll Be Doing:\nIndependently own and drive signoff static timing analysis and timing closure for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.\nExecute static timing analysis (STA), power analysis, synthesis and timing/power closure to meet stringent performance and power targets.\nDevelop and validate timing constraints at block-level or Full SoC level.\nKnowledge of synthesis, clock tree structures, implementation and STA tool correlation, impact of constraints on physical implementation, parasitic extraction, and formal verification will be preferred.\nCollaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.\nUtilize and optimize Synopsys EDA tools, including PrimePower, PT-PX, PrimeClosure, and Tweaker to deliver state-of-the-art silicon solutions.\nDevelop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.\nContribute to the continuous improvement of static timing analysis flows and methodologies and best practices, sharing insights and mentoring junior engineers as needed.\n \nThe Impact You Will Have:\nAccelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.\nEnable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.\nDrive technical excellence and best practices within the team, influencing the future direction of static timing analysis and timing closure methodologies at Synopsys.\nFoster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.\nContribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.\nSupport strategic customer engagements and help expand Synopsys' presence in the semiconductor ecosystem through successful project outcomes.\n \nWhat You’ll Need:\nBachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.\n12+ years of relevant experience in static timing analysis, particularly in advanced technology nodes (7nm/5nm/3nm).\nComprehensive hands-on experience of constraints development, validation, static timing analysis (STA), power analysis, Timing and power ECO generation.\nProficiency with Synopsys EDA tools such as PrimeTime, PT-PX, PrimeClosure, Tweaker.\nWorking experience with Synopsys tools like Fusion Compiler, Design Compiler, Formality, and StarRC.\nStrong scripting and automation skills using Python, PERL, TCL, or similar languages.\nSolid understanding of timing constraints development, validation, static timing analysis and closure, for both block-level and full-chip designs.\nExposure to high-frequency design and low-power design methodologies.\n \nWho You Are:\nProactive, self-motivated, and driven to achieve technical excellence.\nExceptional problem-solving and analytical skills with a keen attention to detail.\nExcellent communication and interpersonal abilities, comfortable working in diverse and global teams.\nCollaborative team player who values knowledge sharing and mentoring others.\nAdaptable and open to learning new technologies and methodologies in a rapidly evolving field.\n \nThe Team You’ll Be A Part Of:\nYou’ll join a world-class team of backend and static timing analysis engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry.\n \nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\n \nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.", "jd_status": "stored"}, {"title": "Senior Staff Engineer, Digital Design", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-04-21T08:11:10.377000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000121964937-senior-staff-engineer-digital-design", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Job Description\nPrincipal Accountabilities:\nDesign of optimized digital blocks meeting functional, cost and low power constraints and ensure spec compliance.\nDevelop TCL scripts and design constraints to perform synthesis, DFT insertion and static timing analysis.\nSupport DFT strategy and implementation.\nVerification planning, feature extraction and verification test case development.\nInterface with P & R for digital hand-off and post layout verification.\nDevelop test vectors for production test.\nPerform physical silicon device evaluation where necessary.\nProduce high quality documentation for own blocks.\nDevelop work-around solutions where necessary to overcome device errata including documentation.\nAll other tasks as deemed reasonable by your manager some of which will be set during annual performance review.\n\n10+ years of relevant experience in Logic design /micro-architecture / RTL coding.\nMust have hands on experience with Power product design, synthesis and timing analysis for complex Analog Circuits.\nExperience in Verilog/System-Verilog is a must.\nExperience working in semiconductor ideally PMIC or Audio with focus on mixed signal integrated circuits\nHands on experience developing block and top-level timing constraints for STA and P & R sign off\nKnowledge of scan insertion and ATPG generation\nUnderstanding of design constraints and synthesis scripts\nWork independently on straightforward tasks, with little direction from manager\nAbility to propose innovative solutions\nResults-oriented and able to deliver on-time under a tight schedule\nCross cultural awareness and sensitivity\nProactive attitude about own role and contribution to company goals\nAbility to work both independently and part of a team\nFlexible to undertake occasional international travel at short notice\nExcellent command of verbal and written English\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nWe have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning.", "jd_status": "stored"}, {"title": "Senior Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-04-21", "url": "https://careers.arm.com/job/bengaluru/senior-engineer/33099/94206086192", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Overview:\n\nExperience: 3 – 15 years\n \nResponsibilities:\nVerification engineer with a knowledge of IP verification or SoC integration verification\nExperience in SoC scenario verification, SoC performance verification, CHI/DDRx/LPDDRx integration verification in SoC RTL.\nExperience in architecting and implementing SV/UVM testbenches, create and maintain reusable verification components\nExperience in formal verification strategy for complex IP blocks—defining properties, driving proofs and coverage closure\nYour key responsibilities will include writing test plans, defining test methodologies, SystemVerilog/Verilog testbench development, developing UVM or C based software tests, and debugging of test failures and issues.\nWorking with project management and leads on planning tasks, schedules, and reporting progress \nCollaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA and board development\nRequired Skills and Experience :\nProven understanding of digital hardware verification language Verilog/Systemverilog HDL\nExperience in SoC verification using Embedded Low-level programming including C/C++ tests and assembly language(preferably ARM)\nExperienced in one or more of various verification methodologies – UVM/OVM, Formal(jasper), power aware verification, emulation\nExposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support\nGood Problem Solving and Debugging skills.\nKnowledge of IP or SoC Verification Flow and strategy.\nExperience with ARM-based designs and/or ARM System Architectures.\nPorting peripheral driver software\nClock Domain Crossing verification\nExperienced in GLS, DFT/DFD, \nExperienced in UPF Power Aware verification\nExperience in embedded operating systems, device drivers, microprocessor and embedded system hardware architectures.\nAutomation experience with shell programming/scripting (g. Tcl, Perl, Python etc.)\n\n#LI-PS2\n \nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\n\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Architecture Verification Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-04-20", "url": "https://careers.arm.com/job/bengaluru/architecture-verification-engineer/33099/94163828576", "is_hardware": true, "platform": "talentbrew", "jd_text": "Architecture Verification Engineer\nThe Architecture and Technology Group (ATG) at ARM develops technologies and products for ARM’s future architecture roadmap. As part of the evolution of new architecture specifications, modeling is an integral and essential element that enables evaluation of the key architecture features in terms of performance and functionality. The modelling team works alongside the leading architects in their field to develop new models and design performance studies to evaluate and craft new architecture features.\nThe role also contributes to architecture compliance verification using embedded software-style test development, where CPU architecture knowledge, strong C programming, assembly programming, automation, and low-level debug are used to validate architecture behavior across implementations.\nJob Description\nUnderstand architecture definitions, carry out investigations and feasibility studies, develop verification strategy and contribute to development of compliance product.\nDesign verification testcases/scenarios in assembly/C/HVL and higher abstraction languages using automation techniques as needed.\nDevelop architecture compliance tests using C and assembly to validate CPU behavior, architecture features, low-level execution flows, and system-level compliance scenarios.\nContribute to automation, debug flows, and reusable compliance test infrastructure for validating architecture specifications across different implementations.\nExcellent verbal and written communication skills.\nSelf-motivated and willing to take up additional responsibilities to contribute to the team’s success.\nRequired Skills and Experience\nBtech/B.S. or MTech/M.S./PhD in Computer Engineering/Computer Science or Electronics Engineering.\n3-8 Years of engineering experience CPU/sophisticated IP verification\nStrong analytical and debugging skills for architecture compliance, CPU behavior, and low-level software execution issues.\nStrong understanding of Computer Architecture concepts, including out-of-order CPU execution, caches, memory etc.  ARM A-profile   \narchitecture experience is a plus.\nStrong communication skills to collaborate with cross-functional and geographically distributed teams to accomplish tasks\nExcellent problem-solving skills and attention to detail\nDesire and flexibility to learn a variety of verification especially RIS methodologies, RTL designs under test, architecture features, familiarity with         \ntestbench development for verifying RTL using any standard verification methodology\nGood to have skills and qualifications\nPrior experience verifying micro-architecture of IPs/sub-systems, such CPUs/GPUs, interconnects etc. is a plus.\nExperience with Verilog/System Verilog  HDLs, C/C++ is strongly recommended\nAssembly language experience, such as with ARM or x86 is preferred\nExperience with RTL verification using UVM methodology is desired\nExperience with industry standard simulation tools like VCS, Questa is desired.\nExperience with common scripting languages such as Perl or Python\nExperience with developing/reviewing test plans to verify micro-architecture and executing the plan in a predictable manner to meet objectives\nExperience with test generators, toolkits for ARM CPU validation such as Raven/ACK is a plus\nExperience with running and debugging workloads on FPGA platforms or silicon is a bonus\nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Analog Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-04-20", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009926", "is_hardware": true, "platform": "oracle", "jd_text": "About Ultra-Wide-Band (UWB):\n\nUltra-Wide-Band (UWB) is an emerging high growth Connectivity technology. Short pulses <3-4ns is used to communicate between a Key Fob and a Car for secure ranging. The short nature of the pulse along with very low duty cycle and advanced data encryption makes it a secure communication approach. Radio operates around microwave frequency band of 7-10GHz and uses 500MHz bandwidth. UWB technology is growing exponentially with Cell Phone Manufacturers such as Apple and Samsung integrating it in the phone and Car OEM’s such as BMW, BYD, Tesla et al integrating UWB based anchors inside car. Besides communication, UWB is perfect for sensing/radar applications. For example, in child safety where UWB based Radar can detect periodic muscle movement such as breathing or general human presence. UWB Radar can also detect various movements around the Car such as kick to open the trunk, an intruder or an occupied seat.\n\nAbout RF Transceiver Group in Connectivity:\n\n Texas Instruments RF Connectivity group is expanding their RF Transceiver Design group. This group develops cutting edge RF Transceiver products (+MCU integrated) for Wireless-LAN (WIFI) and Ultra-Wideband Systems (UWB). The candidate will join in the UWB Design group. Candidate gets to experience Block Architecture Phase, Concept Design and take the design through the various design phases such as Schematic, Layout, Extracted simulations and Test and Verification. The role is primarily in Analog/RF class of circuit design to meet the overall System & Product requirements. The typical blocks include RF blocks such as LNA, TA, Down-conversion Mixers, Base-band filters, High Speed ADC to send data to the Modem. Reverse Chain namely for Transmitter, starting from DAC, Base-band filter, Up-conversion mixer and Power Amplifier stages to drive the TX Pin. LO system design including Chrystal Oscillator, integer/fractional PLL and LO Distribution systems. Various Calibration modules (AGC, PDET, Gain, Offset, IQMM, etc) to calibrate the Transceiver chain is part of the design. Low Current Mode and Complex Power Management to operate at low LDO input voltage etc. The Design Engineer in RF Connectivity gets introduced to a Holistic view of the product including, Radio Silicon Design, Packaging and PCB and solution design.\n\nAbout the Role:\n\nWe are hiring one lead level IC Design Engineer with demonstrated design cycle experience. Some of the possible roles are:\n\nPLL & Clock System Design\n\nIF filter and VGA Design\n\nTransmitter Design\n\nADC Design\n\nCandidate should have gone through 1 complete design cycle of an RF transceiver: namely Architecture, Schematic Design, Layout Design, Tape Out, Test & Validation and identifying design fixes for subsequent Tape Out.\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in Electrical Engineering\n\n2 years of relevant experience\n\nCandidate should have gone through 1 complete design cycle of an RF transceiver: namely Architecture, Schematic Design, Layout Design, Tape Out, Test & Validation and identifying design fixes for subsequent Tape Out.\n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "ESD Lead", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-04-20", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009750", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n   \n\nAs an Analog ESD Product Specialist, you will have the opportunity to work with TI’s industry-leading analog products for precision analog, power management, imaging, audio, high-speed converter and interface applications. You will be exposed to a variety of technologies from deep-submicron, analog CMOS, to high-voltage BiCMOS. \n\n \n\nThis position provides an excellent view of the entire commercial semiconductor flow from technology development to productization support and circuit design, to product qualification; yielding a platform for strong interaction with technology development, product, and reliability groups. \n\n \n\nThe primary purpose of the Analog ESD Product Specialist is to improve design quality and eliminate unwanted design iterations caused by ESD-induced failures, while continually improving ESD protection effectiveness and area efficiency. Responsibilities include but are not limited to:\n\nDesign, develop and implement ESD protection structures for analog products using TI’s analog processes \n\nPerform ESD reviews on TI analog products\n\nPerform ESD troubleshooting on TI analog products that fail internal, or customer, qualification requirements. \n\nAssist with the design and development of test structures for ESD assessment of TI’s analog process technologies. \n\nMaintain ESD protection structure libraries and ESD design guideline documents to be used by TI design engineers and I/O cell developers.\n\n \n\nThe ideal candidate will have a Ph.D. with 10 years of experience or MSEE with 15 years of experience in the field of Analog ESD Design support. As an Analog ESD Product Specialist, you will be expected to have a strong understanding of the following: \n\n \n\nAnalog and digital circuit operation\n\nDiode, resistor, bipolar and FET high current device physics\n\nTypical CMOS and Analog silicon process flows and the underlying process physics\n\nHigh Voltage ESD Design (>20V)\n\n \n\nAdditionally, strong “hands-on” lab experience and excellent problem solving skills are a must.\n\nThis position requires a high level of attention to details and self-organization. It is extremely important to be self-directed, pro-active, and innovative. You must have both the ability to manage multiple tasks within a single job and the ability to manage multiple jobs, to meet required deadlines.\n\n \n\nExcellent verbal and written communication skills are essential.\n\nQualifications\nMinimum requirements:\n\nThe ideal candidate will have a Ph.D. with 10 years of experience or MSEE with 15 years of experience in the field of Analog ESD Design support. \n\nPreferred qualifications:\n\nAs an Analog ESD Product Specialist, you will be expected to have a strong understanding of the following: \n\nAnalog and digital circuit operation\n\nDiode, resistor, bipolar and FET high current device physics\n\nTypical CMOS and Analog silicon process flows and the underlying process physics\n\nHigh Voltage ESD Design (>20V)\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Analog ESD Product Specialist", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-04-20", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010251", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n  \n\nAs an Analog ESD Product Specialist, you will have the opportunity to work with TI’s industry-leading analog products for precision analog, power management, imaging, audio, high-speed converter and interface applications. You will be exposed to a variety of technologies from deep-submicron, analog CMOS, to high-voltage BiCMOS. \n\n \n\nThis position provides an excellent view of the entire commercial semiconductor flow from technology development to productization support and circuit design, to product qualification; yielding a platform for strong interaction with technology development, product, and reliability groups. \n\n \n\nThe primary purpose of the Analog ESD Product Specialist is to improve design quality and eliminate unwanted design iterations caused by ESD-induced failures, while continually improving ESD protection effectiveness and area efficiency. Responsibilities include but are not limited to:\n\nDesign, develop and implement ESD protection structures for analog products using TI’s analog processes \n\nPerform ESD reviews on TI analog products\n\nPerform ESD troubleshooting on TI analog products that fail internal, or customer, qualification requirements. \n\nAssist with the design and development of test structures for ESD assessment of TI’s analog process technologies. \n\nMaintain ESD protection structure libraries and ESD design guideline documents to be used by TI design engineers and I/O cell developers.\n\n \n\nThe ideal candidate will have a Ph.D. with 3 years of experience or MSEE with 5 years of experience in the field of Analog ESD Design support. As an Analog ESD Product Specialist, you will be expected to have a strong understanding of the following: \n\n \n\nAnalog and digital circuit operation\n\nDiode, resistor, bipolar and FET high current device physics\n\nTypical CMOS and Analog silicon process flows and the underlying process physics\n\nHigh Voltage ESD Design (>20V)\n\n \n\nAdditionally, strong “hands-on” lab experience and excellent problem solving skills are a must.\n\nThis position requires a high level of attention to details and self-organization. It is extremely important to be self-directed, pro-active, and innovative. You must have both the ability to manage multiple tasks within a single job and the ability to manage multiple jobs, to meet required deadlines.\n\n \n\nExcellent verbal and written communication skills are essential.\n\nQualifications\nMinimum requirements:\n\nThe ideal candidate will have a Ph.D. with 3 years of experience or MSEE with 5 years of experience in the field of Analog ESD Design support.\n\nPreferred qualifications:\n\nAs an Analog ESD Product Specialist, you will be expected to have a strong understanding of the following:\n\nAnalog and digital circuit operation\n\nDiode, resistor, bipolar and FET high current device physics\n\nTypical CMOS and Analog silicon process flows and the underlying process physics\n\nHigh Voltage ESD Design (>20V)\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Lead Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-04-19", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Design-Engineer_R54171-1", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nDesign verification of ASICs  for Palladium.\nPosition is based in Bangalore\nWill have to work at IP, Sub-System and SOC level verification.\nTest plan creation, functional coverage plan and coding of functional coverage bins.\nWill be involved in post silicon validation/bring up.\nJob Requirements:\nStrong expertise in Verilog, HVL( SV/Specman e) with UVM/OVM/eRM methodology.\nExperience in functional coverage/code coverage/assertions development and closure.\nExperience in test plan creation.\nExposure to PCIe and LPDDR verification.\nStrong debug skills\nShould be process oriented and have a passion for scripting/automation.\nShould be a good team player\nEffective cross-team communication and documentation skill is strongly preferred.\nMinimal qualification requires BS/MS degree ECE or CS with 4+ years of experience in related fields.\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Principal Engineer Design", "company": "Infineon", "location": "Bangalore BTP (India)", "date_posted": "2026-04-17T06:32:09+00:00", "url": "https://jobs.infineon.com/careers/job/563808970361335", "is_hardware": true, "platform": "eightfold", "jd_text": "#WeAreIn to transform theoretical concepts into real hardware designs. Are you in?\n\nYour Role\n\nDrive and manage as technical lead a self-contained DFT team which is responsible for:\nThe DFT implementation of the latest Infineon microcontroller products\nScan insertion, ATPG, LBIST and MBIST\nVerification of the DFT implementation and Test pattern delivery for production testing\nSupport the Silicon bring-up activities to guarantee the highest stability of the test pattern\nContribute to the overall microcontroller DFT methodology\nCoordination of DFT work packages and hands-on work, status reporting\nInterfacing with project management, layout team and test engineering\n\nYour Profile\n\nA university degree in Electrical Engineering, Microelectronics, Physics, or a similar field.\nProfound knowledge about semiconductor products.\nAt least 10 years of experience in DFT of highly complex SoCs\nExpert Knowledge of DFT methods for state-of-the-art MPU/MCU products.\nWorking knowledge of the test concept or the DFT concept definition.\nStrong track record of scan insertion and ATPG\nVery good knowledge of DFT RTL insertion, including MBIST and SRAM repair\nExperience in debugging test pattern issues\nProgramming or scripting experience\nVery good soft skills and experience in leading\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\nThis means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.\nPlease let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.\nClick here for more information about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Senior Pre Silicon GPU Kernel Driver Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-04-17T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446718113341", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Systems Engineering\nGeneral Summary:\nGeneral Summary:\nAdreno GPU has been the leading mobile graphics solution in the industry and has been the dominating GPU in today’s smart phone market. Our power efficient GPU solution is fundamental to enable the exciting new markets like VR, IoT, AI, drone, autonomous driving etc. We are looking for talented Graphics System engineers to create world class GPU products to enable high performance graphics and compute with low power consumption.\nPosition involves Kernel mode drivers design and development on Adreno GPU, interactions/collaboration with software, hardware, and systems teams to develop/maintain optimized KMD drivers for Mobile/XR/IoT devices running on pre-Sil environment.\n\nResponsibilities:\nWork with cross teams to develop pre-silicon Kernel Mode GPU driver.\nWork on features in upcoming premium and mid-tier GPUs.\n\nClosely work with Design and DV teams to analyze and identify bottlenecks and implement fixes/optimizations.\n\nEnable and support other teams that use supported features.\n\nIdentify and support core set of tools for assisting driver development, debug and support\n\nMinimum Qualifications:\n•    Bachelor’s degree in engineering, Information Systems, Computer Science, or related field and 4+ years of Software Engineering or related work experience.\nOR\nMaster’s degree in engineering, Information Systems, Computer Science, or related field and 2+ year of Software Engineering or related work experience.\nOR\nPhD in Engineering, Information Systems, Computer Science, or related field.\n• 2+ years of academic or work experience with Programming Language such as C or C++.\n• Experience working with GPU's or CPU's Linux kernel or Linux Device Drivers or RTOS (Real Time Operation Systems), \n• Strong Debugging and communication skill.\n\nSkills/experience:\nExcellent knowledge of OS fundamentals, data structure.\n\nExcellent programming skills and expert level knowledge of C\n\nSpecific experience and expertise in any of kernel subsystems – core kernel, device drivers, memory, SMMU or firmware development.\n\nWell versed with development tools like tool chain, version control, debugger etc.\n\nBackground experience in kernel mode GPU driver is a plus.\n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.\n                                                                    OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience.\n                                                                    OR\nPhD in Engineering, Information Systems, Computer Science, or related field.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "DSP Engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2026-04-17", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/DSP-Engineer_R-10062134", "is_hardware": true, "platform": "workday", "jd_text": "We are looking for a DSP Engineer to join our Automotive Ethernet PHY team. You will work closely with the DSP Architect to implement DSP algorithms, contribute to PHY architecture realization, and support verification, validation, and backend teams throughout the product lifecycle.\nKey Responsibilities\nImplement and optimize DSP architecture for Automotive Ethernet PHY (100/1000BASE‑T1, Multi‑Gig).\nDevelop high‑quality RTL for DSP datapath blocks (filters, EQ, echo canceller, FFE/DFE, AGC, timing recovery).\nWork with Verification/Validation for debugging, coverage closure, and model correlation.\nCollaborate with DFT, System Architecture, IC Integration, and Backend teams for constraints and timing closure.\nDevelop MATLAB/Python models and support system‑level analysis.\nRequired Skills\nStrong DSP and communication systems fundamentals.\nHands‑on experience with PHY‑layer DSP blocks.\nRTL design expertise (Verilog/SystemVerilog).\nMATLAB, Simulink, Python, C/C++ modeling experience.\nUnderstanding of synthesis, STA, CDC, linting flows.\nGood to Have\nExperience with Automotive Ethernet PHY development.\nKnowledge of DFT, post‑silicon bring‑up, and backend timing closure.\nExposure to UVM environments and formal verification.\nIf you're passionate about building next‑generation automotive PHY solutions, we’d love to talk!\n\nMore information about NXP in India...\n\n#LI-7013", "jd_status": "stored"}, {"title": "R&D Engineering, Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-04-17", "url": "https://careers.synopsys.com/job/bengaluru/r-and-d-engineering-staff-engineer/44408/100768195936", "is_hardware": true, "platform": "talentbrew", "jd_text": "Alternate Job Titles:\nCAD Automation Engineer\nWe Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nYou are a passionate and highly skilled engineer who thrives on solving complex challenges in the Electronic Design Automation (EDA) domain. With a solid foundation in digital design, synthesis, and automation, you possess a keen analytical mindset and an unwavering commitment to engineering excellence. Your expertise in C/C++ and scripting languages like Tcl or Python allows you to seamlessly develop and optimize robust software solutions. You have a deep understanding of front-end design flows, timing constraints, and the intricate interactions between synthesis, place & route, and analysis tools. You take ownership of your work, showing accountability and technical leadership in every project. Your collaborative spirit shines through as you engage with globally distributed teams and actively contribute to technical discussions, code reviews, and roadmap planning. You are motivated by continuous learning and knowledge sharing, and you enjoy mentoring junior engineers to build a strong team culture. Flexible and adaptable, you excel in fast-paced, multi-project environments, balancing independent problem-solving with effective teamwork. Your clear communication skills enable you to articulate complex technical concepts to colleagues and customers alike. Above all, you are driven by the desire to make a tangible impact on industry-leading EDA solutions, ensuring quality, scalability, and customer satisfaction at every step.\n\nWhat You’ll Be Doing:\nDesigning, developing, and enhancing logic synthesis features and automation flows for advanced EDA tools.\nOwning and maintaining synthesis capabilities with direct impact on timing, area, power, and Quality of Results (QoR) optimization.\nDeveloping and debugging solutions across end-to-end EDA flows, understanding interactions between synthesis, place & route, STA, and power analysis tools.\nAnalyzing and resolving complex customer and internal issues related to timing constraints (SDC), synthesis behavior, and flow integration.\nCollaborating with architecture, verification, QA, and product management teams to deliver integrated, production-quality EDA solutions.\nParticipating actively in technical design discussions, code reviews, and roadmap planning to shape the future of Synopsys’ tools.\nEnsuring high engineering quality through unit testing, regression support, and adherence to best development practices  \nContributing to internal documentation, knowledge sharing, and mentoring junior engineers to foster growth and innovation within the team.\n\nThe Impact You Will Have:\nDriving the evolution of Synopsys’ industry-leading EDA solutions in IP packaging and subsystem assembly.\nEnhancing the efficiency and scalability of design flows for leading semiconductor and system companies worldwide.\nEmpowering customers to achieve optimal timing, area, and power results, accelerating their product development cycles.\nResolving critical technical challenges, enabling seamless integration of synthesis and automation in complex design environments.\nContributing to the creation of robust, production-quality tools that set new standards in the EDA industry.\nFacilitating knowledge transfer and technical growth within the R&D organization through mentorship and documentation.\nSupporting customer success by providing innovative solutions and responsive issue resolution.\nShaping the roadmap and future direction of Synopsys’ automation frameworks and design technologies.\n\nWhat You’ll Need:\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.\n4–6 years of industry experience in EDA tools, CAD automation, or system-level software development.\nStrong proficiency in C/C++ for large-scale software development and optimization.\nExperience with Tcl, Python, or similar scripting languages for flow automation and customization.\nHands-on expertise in front-end EDA flows, including RTL design, logic synthesis, and timing constraints (SDC authoring/debugging).\nSolid understanding of digital design fundamentals and ASIC/SoC design methodology.\nComfortable working in Linux/UNIX development environments.\nExcellent debugging, analytical, and problem-solving skills.\n\nWho You Are:\nStrong sense of ownership, accountability, and technical leadership.\nClear and effective written and verbal communication skills.\nAbility to work independently on complex problems while collaborating across teams.\nComfort operating in a fast-paced, multi-project R&D environment.\nAdaptable, proactive, and eager to learn and share knowledge.\nCollaborative team player with a customer-centric mindset.\nDetail-oriented with a focus on delivering high-quality, scalable solutions.\nThe Team You’ll Be A Part Of:\nYou’ll join Synopsys’ dynamic R&D organization in Bengaluru, working with a diverse team of engineers focused on developing industry-leading EDA tools and automation frameworks. The team collaborates globally, engaging with architecture, verification, QA, and product management experts to deliver integrated, high-impact solutions for semiconductor and system companies. Together, you’ll drive innovation in IP packaging and subsystem assembly, shaping the future of chip design and verification.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Lead Software Engineer ( Verification )", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-04-17", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Software-Engineer---Verification--_R53272", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Title: Verification ( SV , UVM & VHDL )\n\nCadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.\n\nThe Cadence Advantage\nThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.\nCadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.\nThe unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success.\nMultiple avenues of learning and development available for employees to explore as per their specific requirement and interests.\nYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.\n\nJob Summary:\n\nWe are looking for a candidate with excellent communication skills and ability to ramp up on new technologies quickly and independently. This position requires the technical expertise in protocol and formal verification methodologies.\n\nThis an excellent opportunity to work in a supportive and friendly work environment, where we are vested in each other’s success, and are passionate about technology and innovation.\n\nWork location: Bangalore\nExperience : 5 - 8 Years or equivalent relevant experience\nEducation : M.E./MTech (Electronics or similar) or B.E/BTech. (Electronics or similar)\n\nJD\nPosition Description:\n\nWe’re looking for talented SW engineer to join us and be part of a team that is responsible for developing Cadence SW driven verification Solutions.\nDuties will include active development and support of verification libraries for different architectures-based systems and other IPs.\nThe candidate must have background in verification and verification methodologies, very strong problem-solving skills and written and verbal communication skills.\n\nSW Engineers are expected to\n\nDevelop verification products based on the multiple customer requirements\nAnalyze customer requirements and translate them to product enhancements bringing their technical understanding of the customer needs and issues\nProvide active support and guidance to customer issues\nCollaborate with other team members and different functions in the organization such as PV and field\n\nPosition Requirements:\n\n- B.Tech/B.E/M.tech/M.E in Electronics and communication\n- Strong programming skills (OOP)\n- Background in developing IP, Sub-system, SoC level verification environment with both UVM and SW-driven (embedded c)\n- Excellent verbal and written communications skills\n- Strong interest and understanding of design and verification methodologies\n- Strong problem solving and analytical skills\n- UNIX shell scripting\n\nStrong Plus:\n\nExperience with System Verilog, Specman e, VHDL, Verilog\nWorking knowledge of embedded c\nKnowledge of protocols such as AMBA, PCI-E, USB, Ethernet, 10 Gig, NVMe etc.\nUnderstanding of verification methodologies (UVM)\nPrior experience in metric driven functional verification\n\nRegards\nMadhu\nkmadhup@cadence.com\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Solutions Engineering, Sr Staff Engineer (DFT, RTL Design product Engineer)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-04-17", "url": "https://careers.synopsys.com/job/bengaluru/solutions-engineering-sr-staff-engineer-dft-rtl-design-product-engineer/44408/99430984224", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nYou are a dynamic engineer with working experience in RTL implementation, DFT/BIST, verification, flow automation and understanding of hierarchical SoC architectures and IEEE1149/1500 and 1687 standards and pattern porting. You should have a passion for working with the best of the brains in the industry in developing end-to-end solutions and deploying them in our premier customer base. Your technical excellence and analytical skills, coupled with strong communication and interpersonal skills, make you an asset to any team. You excel in communication, teamwork, and multitasking, and have experience working in cross-functional, multi-site environments.\nWhat You’ll Be Doing:\nWorking closely with a world-class R&D team, you’ll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM) built over a robust DFT framework.\nWorking closely with customers, you will bring detailed requirements into the factory to enable R&D for strong, robust, and successful product development.\nWorking closely with product development team, you will validate an end-to-end solution both internally (before shipment) as well as in customer environment.\nDriving the deployment and smooth execution of SLM and Test solutions into customers’ projects.\nEnabling customers to realize the value of silicon health monitoring using a robusta DFT framework throughout the lifecycle of silicon bring-up, validation, through in-field operations.\nThe Impact You Will Have:\nEnhancing Synopsys’ Silicon Lifecycle Management (SLM) and DFT IP portfolio and end-to-end solution.\nDriving the adoption of Synopsys’ SLM and DFT solutions at premier customer base worldwide.\nInfluencing the development of next-generation SLM IPs and solutions.\nWhat You’ll Need:\nBSEE/MSEE in Electrical Engineering, Computer Engineering, or related field.\n8 years of hands-on experience with DFT/BIST insertion, RTL design, and functional verification.\nGood exposure to JTAGIEEE 1149.1, IEEE 1687/1500, Testdata access mechanism.\nKnowledge on memory defectivities soft errors and reliability.\nFamiliarity with error correcting codes such as Hamming and Hsiao\nHands-on experience in dealing withhierarchicalSoCs,1149.1/1500/1687 standards and pattern porting\n\nFamiliarity with either Synopsys TestMAX Tool chain or competitive offerings\nDebugging abilities to identify and resolve issues in functional verification in UVM environment.\nHands on experience inflow automation.\nKnowledge of Synthesis is a must with understanding of timing constraints (SDC).\nKnowledge of Lint, CDC, RDC is a plus.\nKnowledge of physical implementation is not a must, but good to have.\nAbility to evaluate technical suggestions from customers and work with internal teams (product management/R&D) to make decisions\nCustomer facing experience is a plus – educating/guiding customer on technical details of a solution \nGood to have: \nHands-on bring-up and debug experience of silicon is a plus\nArchitecture/micro-architecture experience\nUnderstanding ofGenAI and Agentic AI workflows.\n#TPG", "jd_status": "stored"}, {"title": "R&D Engineering, Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-04-17", "url": "https://careers.synopsys.com/job/bengaluru/r-and-d-engineering-staff-engineer/44408/94055936112", "is_hardware": true, "platform": "talentbrew", "jd_text": "Alternate Job Titles:\nCAD Automation Engineer\nWe Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nYou are a passionate and highly skilled engineer who thrives on solving complex challenges in the Electronic Design Automation (EDA) domain. With a solid foundation in digital design, synthesis, and automation, you possess a keen analytical mindset and an unwavering commitment to engineering excellence. Your expertise in C/C++ and scripting languages like Tcl or Python allows you to seamlessly develop and optimize robust software solutions. You have a deep understanding of front-end design flows, timing constraints, and the intricate interactions between synthesis, place & route, and analysis tools. You take ownership of your work, showing accountability and technical leadership in every project. Your collaborative spirit shines through as you engage with globally distributed teams and actively contribute to technical discussions, code reviews, and roadmap planning. You are motivated by continuous learning and knowledge sharing, and you enjoy mentoring junior engineers to build a strong team culture. Flexible and adaptable, you excel in fast-paced, multi-project environments, balancing independent problem-solving with effective teamwork. Your clear communication skills enable you to articulate complex technical concepts to colleagues and customers alike. Above all, you are driven by the desire to make a tangible impact on industry-leading EDA solutions, ensuring quality, scalability, and customer satisfaction at every step.\n\nWhat You’ll Be Doing:\nDesigning, developing, and enhancing logic synthesis features and automation flows for advanced EDA tools.\nOwning and maintaining synthesis capabilities with direct impact on timing, area, power, and Quality of Results (QoR) optimization.\nDeveloping and debugging solutions across end-to-end EDA flows, understanding interactions between synthesis, place & route, STA, and power analysis tools.\nAnalyzing and resolving complex customer and internal issues related to timing constraints (SDC), synthesis behavior, and flow integration.\nCollaborating with architecture, verification, QA, and product management teams to deliver integrated, production-quality EDA solutions.\nParticipating actively in technical design discussions, code reviews, and roadmap planning to shape the future of Synopsys’ tools.\nEnsuring high engineering quality through unit testing, regression support, and adherence to best development practices  \nContributing to internal documentation, knowledge sharing, and mentoring junior engineers to foster growth and innovation within the team.\n\nThe Impact You Will Have:\nDriving the evolution of Synopsys’ industry-leading EDA solutions in IP packaging and subsystem assembly.\nEnhancing the efficiency and scalability of design flows for leading semiconductor and system companies worldwide.\nEmpowering customers to achieve optimal timing, area, and power results, accelerating their product development cycles.\nResolving critical technical challenges, enabling seamless integration of synthesis and automation in complex design environments.\nContributing to the creation of robust, production-quality tools that set new standards in the EDA industry.\nFacilitating knowledge transfer and technical growth within the R&D organization through mentorship and documentation.\nSupporting customer success by providing innovative solutions and responsive issue resolution.\nShaping the roadmap and future direction of Synopsys’ automation frameworks and design technologies.\n\nWhat You’ll Need:\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.\n4–6 years of industry experience in EDA tools, CAD automation, or system-level software development.\nStrong proficiency in C/C++ for large-scale software development and optimization.\nExperience with Tcl, Python, or similar scripting languages for flow automation and customization.\nHands-on expertise in front-end EDA flows, including RTL design, logic synthesis, and timing constraints (SDC authoring/debugging).\nSolid understanding of digital design fundamentals and ASIC/SoC design methodology.\nComfortable working in Linux/UNIX development environments.\nExcellent debugging, analytical, and problem-solving skills.\n\nWho You Are:\nStrong sense of ownership, accountability, and technical leadership.\nClear and effective written and verbal communication skills.\nAbility to work independently on complex problems while collaborating across teams.\nComfort operating in a fast-paced, multi-project R&D environment.\nAdaptable, proactive, and eager to learn and share knowledge.\nCollaborative team player with a customer-centric mindset.\nDetail-oriented with a focus on delivering high-quality, scalable solutions.\nThe Team You’ll Be A Part Of:\nYou’ll join Synopsys’ dynamic R&D organization in Bengaluru, working with a diverse team of engineers focused on developing industry-leading EDA tools and automation frameworks. The team collaborates globally, engaging with architecture, verification, QA, and product management experts to deliver integrated, high-impact solutions for semiconductor and system companies. Together, you’ll drive innovation in IP packaging and subsystem assembly, shaping the future of chip design and verification.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior Verification Engineer - Audio and Auxiliary CPU Sub-Systems", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-04-16", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer---Audio-and-Auxiliary-CPU-Sub-Systems_JR2016426", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people.\nToday, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.\nWe are seeking enthusiastic, driven, and imaginative individuals to join our automotive verification group. As the owner of Audio or Auxiliary CPU Sub-Systems unit, cluster and SOC level verification, you will contribute to projects crafting the future of automotive chips and systems. You will gain direct experience of an SOC working with high-performance CPU, memory sub-systems, NOC-based interconnect fabric, high-speed I/Os, and various advanced technologies used in our Tegra chips.\n \nWhat you'll be doing:\nYou will develop UVM-based verification test benches and methodologies for unit level, write verification components and API's for cluster and system level test benches. These will verify dedicated CPU sub-systems targeted for Audio processing, Functional Safety, RAS, BOOT and power management.\nDuring the course of a project, you will drive the following aspects of verification for your unit:\nArchitect the testbenches and craft verification environment using SV, UVM and C/C++ methodology\n\nDefine test plans, tests and verification infrastructure for clusters and systems\n\nBuild efficient and reusable bus functional models, monitors, checkers, scoreboards, API's and encapsulated components\n\nImplement functional coverage and own unit, cluster and SOC level verification closure\n\nWork with architects, designers, FPGA, and post-silicon teams to ensure that your unit is robust and feed back and bug escapes driven improvements to your setup\n\nWhat we need to see:\nBTech or MTech in ECE, EE, CSE, or an equivalent degree is required. Candidates should have over 5 years of experience in verification closure of complex units, sub-systems, or SOC level verification.\n\nProven experience in RISCV, ARM or DSP core based CPU sub-systems.\n\nExperience in the latest verification methodologies like SV and UVM\n\nGood debugging and analytical skills with exposure to industry-standard verification tools for simulation and debug\n\nGood interpersonal skills, ability to work as a diligent teammate, and excellent communication skills to collaborate with cross-cultural global teams and work in a matrix organization\n\nWays to stand out from the crowd:\nExposure on using AI (like Claude and Cursor) extensively for code development would be a big plus\n\nA mentality towards constant improvement and looking to build a multiplier effect through your work and automation\n\nExposure to Formal verification would be excellent\n\nAn exposure to Audio functions, safety and reliability features and BOOT, power management features experience could serve as a differentiator\n\nWe have some of the most experienced and dedicated people in the world working at NVIDIA. If you're creative and independent, with a genuine passion for adopting the newest technology, we want to hear from you. Join us and be part of something outstanding!\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.\nWidely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior ASIC Design Engineer - NOC IP", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-04-16", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-ASIC-Design-Engineer---NOC-IP_JR1998309", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking passionate, highly motivated, and creative senior design engineers to be part of its Graphics team working on the design of state of the art memory subsystem components used in their industry-leading Graphics Processors. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n\nIn this position, you will be expected to make architectural trade-offs based on features, performance requirements and system limitations, come up with micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. You will work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and backend teams to accomplish your tasks.\n\nWhat you’ll be doing:\nOwn micro-architecture and RTL development of design modules.\n\nMicro-architect features to meet performance, power and area requirements.\n\nWork with HW architects to define critical features.\n\nCollaborate with verification teams to verify the correctness of implemented features.\n\nCo-operate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable.\n\nInteract with FPGA and S/W teams to prototype the design and ensure that S/W is tested.\n\nWork on post-silicon verification and debug.\n\nWhat we need to see:\nBS / MS or equivalent experience.\n\n7+ years of design experience.\n\nExperience in RTL design of complex design units for at least two or three projects.\n\nExposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).\n\nDeep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.\n\nExpertise in Verilog.\n\nWays to stand out from the crowd:\nDesign experience in memory subsystem or network interconnect IP.\n\nGood debugging and problem solving skills.\n\nScripting knowledge (Python/Perl/shell).\n\nLeadership experience in leading small 2-3 member teams.\n\nGood interpersonal skills and ability & desire to work as a part of a team.\n\nNVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.\n\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Analog ESD Product Specialist", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-04-16", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009752", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n  \n\nAs an Analog ESD Product Specialist, you will have the opportunity to work with TI’s industry-leading analog products for precision analog, power management, imaging, audio, high-speed converter and interface applications. You will be exposed to a variety of technologies from deep-submicron, analog CMOS, to high-voltage BiCMOS. \n\n \n\nThis position provides an excellent view of the entire commercial semiconductor flow from technology development to productization support and circuit design, to product qualification; yielding a platform for strong interaction with technology development, product, and reliability groups. \n\n \n\nThe primary purpose of the Analog ESD Product Specialist is to improve design quality and eliminate unwanted design iterations caused by ESD-induced failures, while continually improving ESD protection effectiveness and area efficiency. Responsibilities include but are not limited to:\n\nDesign, develop and implement ESD protection structures for analog products using TI’s analog processes \n\nPerform ESD reviews on TI analog products\n\nPerform ESD troubleshooting on TI analog products that fail internal, or customer, qualification requirements. \n\nAssist with the design and development of test structures for ESD assessment of TI’s analog process technologies. \n\nMaintain ESD protection structure libraries and ESD design guideline documents to be used by TI design engineers and I/O cell developers.\n\n \n\nThe ideal candidate will have a Ph.D. with 3 years of experience or MSEE with 5 years of experience in the field of Analog ESD Design support. As an Analog ESD Product Specialist, you will be expected to have a strong understanding of the following: \n\n \n\nAnalog and digital circuit operation\n\nDiode, resistor, bipolar and FET high current device physics\n\nTypical CMOS and Analog silicon process flows and the underlying process physics\n\nHigh Voltage ESD Design (>20V)\n\n \n\nAdditionally, strong “hands-on” lab experience and excellent problem solving skills are a must.\n\nThis position requires a high level of attention to details and self-organization. It is extremely important to be self-directed, pro-active, and innovative. You must have both the ability to manage multiple tasks within a single job and the ability to manage multiple jobs, to meet required deadlines.\n\n \n\nExcellent verbal and written communication skills are essential.\n\nQualifications\nMinimum requirements:\n\nThe ideal candidate will have a Ph.D. with 3 years of experience or MSEE with 5 years of experience in the field of Analog ESD Design support.\n\nPreferred qualifications:\n\nAs an Analog ESD Product Specialist, you will be expected to have a strong understanding of the following:\n\nAnalog and digital circuit operation\n\nDiode, resistor, bipolar and FET high current device physics\n\nTypical CMOS and Analog silicon process flows and the underlying process physics\n\nHigh Voltage ESD Design (>20V)\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Senior Verification Engineer - HSIO Cluster and SOC", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-04-16", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer---HSIO-Cluster-and-SOC_JR2016434", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people.\nToday, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.\nWe are seeking enthusiastic, driven, and imaginative individuals to join our automotive verification group. As the owner of HSIO IP's cluster and SOCV level verification, you will contribute to projects crafting the future of automotive chips and systems. You will gain direct experience of chip working with high-performance CPU and memory sub-systems, NOC-based interconnect fabric, high-speed I/Os, and various advanced technologies used in our Tegra chips.\n \nWhat you'll be doing:\nYou will develop verification components and API's for cluster and system level test benches. These will verify complex rapid data transfer IO IPs and sub-systems such as USB, UFS, MPHY, Ethernet, and MACSEC.\nDuring the course of a project, you will drive the following aspects of verification for your unit:\nArchitect the testbenches and craft verification environment using SV, C/C++ methodology\n\nDefine test plans, tests and verification infrastructure for clusters and systems\n\nBuild efficient and reusable bus functional models, monitors, checkers, and scoreboards\n\nImplement functional coverage and own SOC level verification closure\n\nWork with architects, designers, FPGA, and post-silicon teams to ensure that your unit is robust\n\nWhat we need to see:\nBTech or MTech in ECE, EE, CSE, or an equivalent degree is required. Candidates should have over 4 years of experience in verification closure of complex units, sub-systems, or SOC level verification.\n\nProven experience in High Speed IO verification (UFS/PCIE/XUSB), knowledge of 10G/1G Ethernet MAC and Switch\n\nExperience in the latest verification methodologies like SV and UVM\n\nGood debugging and analytical skills with exposure to industry-standard verification tools for simulation and debug\n\nGood interpersonal skills, ability to work as a diligent teammate, and excellent communication skills to collaborate with cross-cultural global teams and work in a matrix organization\n\nWays to stand out from the crowd:\nExposure on using AI (like Claude or Cursor) extensively for code development would be a big plus\n\nA mentality towards constant improvement and looking to build a multiplier effect through your work and automation\n\nExposure to Formal verification would be excellent\n\nWe have some of the most experienced and dedicated people in the world working at NVIDIA. If you're creative and independent, with a genuine passion for adopting newest technology, we want to hear from you. Join us and be part of something outstanding!\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.\nRecognized as one of the most sought-after employers in the technology sector, NVIDIA provides highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Sr Principal Product Engineer", "company": "Cadence", "location": "NOIDA", "date_posted": "2026-04-15", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/NOIDA/Sr-Principal-Product-Engineer_R54219", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nAbout Us Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. With the integration of ChipStack, we are redefining the industry by bringing agentic AI capabilities directly into the silicon development lifecycle. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nPosition Overview We are seeking a dynamic and commercially minded Product Engineer to drive the Go-To-Market (GTM) strategy and manage customer engagements for our groundbreaking agentic AI product suite. In this role, you will act as the critical nexus between our cutting-edge technology and our customers' most pressing business needs. You are highly technical—capable of deeply understanding AI-driven chip design and verification flows—yet highly business-savvy, with a talent for positioning complex products in the market. You will collaborate closely with Research & Development (R&D) and Field Application Engineers (FAEs) to orchestrate successful product evaluations, secure technical wins, and accelerate widespread adoption of our AI solutions.\nKey Responsibilities * Own and manage end-to-end customer engagements, acting as the primary GTM driver for our agentic AI and LLM-driven EDA products.\nServe as the strategic bridge between customers, Field Application Engineers (FAEs), and R&D, ensuring that technical evaluations are executed flawlessly and feedback is operationalized.\nBlend deep technical knowledge of semiconductor design with strong business acumen to articulate product value propositions, ROI, and competitive differentiation to engineering leaders and executives.\nEngage directly with early adopters and key customers to understand their specific design workflows, translating their requirements into actionable roadmaps for the R&D team.\nDevelop high-impact technical collateral, product presentations, and deployment playbooks to empower the sales and FAE teams in the field.\nMaintain current knowledge of advancements in AI-powered hardware design, EDA trends, and market dynamics to actively participate in shaping the product's strategic direction.\nRequired Qualifications * Bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related technical field (an MBA or equivalent business experience is a strong plus) with 12+ Years experience.\nProven expertise in a Product Engineering, Technical Marketing, or Field Application Engineering (FAE) role within the semiconductor or Electronic Design Automation (EDA) industry.\nSolid technical foundation in ASIC design flows, hardware verification (Verilog, SystemVerilog), and an understanding of modern ML/LLM technologies.\nDemonstrated track record of managing complex technical customer engagements and successfully executing Go-To-Market (GTM) initiatives.\nExceptional communication and presentation skills, with the unique ability to translate dense, highly technical concepts into compelling business value.\nSelf-motivated, with a proactive approach to cross-functional collaboration, problem-solving, and driving projects forward in a fast-paced environment.\nThe Cadence Advantage * The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.\nCadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.\nThe unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success.\nMultiple avenues of learning and development available for employees to explore as per their specific requirement and interests.\nYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Principal RTL Design Engineer, Interconnect IP (PCIe digital design and architecture)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-04-15", "url": "https://careers.synopsys.com/job/bengaluru/principal-rtl-design-engineer-interconnect-ip-pcie-digital-design-and-architecture/44408/93996748480", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Title:Principal Digital Design Engineer, PCIe\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years deep in the details of PCIe digital design, and somewhere along the way you became the person others come to when a design decision matters or when something complex needs untangling. You know PCIe architecture not just from specs but from living through silicon bring-up, debugging corner cases at 2 a.m., and watching designs either hold up or fall apart under real-world conditions. That experience shaped how you think about micro-architecture, trade-offs, and what actually ships.\nYou are technical first. You still review RTL. You still care about how a clock domain crossing is handled or whether a state machine will scale to the next generation. But you have also learned how to lead without needing to own every line of code. You set direction, you make the hard calls on architecture, and you help engineers work through problems that do not have obvious answers.\nYou do not wait for perfect clarity. You work with what you have, ask the right questions, align across verification and physical design and firmware, and move the design forward. At Synopsys, you will work on PCIe IP that powers silicon across commercial, enterprise, and automotive customers, and the technical decisions you make will matter.\nWhat You'll Be Doing\nOwn the PCIe digital architecture and drive RTL design execution across block, subsystem, and IP integration levels, staying directly involved in design decisions and reviews\nDefine micro-architecture, design specifications, and implementation strategies for high-performance, power-efficient, and scalable PCIe IP\nLead end-to-end digital design activities from architecture definition through RTL development, debug, design convergence, and post-silicon support\nServe as the technical authority for PCIe design, resolving complex issues and making critical design trade-offs that affect current and next-generation IP\nMentor ASIC digital design engineers through design reviews, technical feedback, and hands-on problem solving\nCollaborate with verification, physical design, formal, emulation, firmware, and system teams to ensure seamless IP integration and silicon success\nDrive design quality through rigorous reviews, coding standards, and maintainability practices that raise the bar across the team\nThe Impact You Will Have\nDeliver industry-leading PCIe digital IP that powers silicon for customers building next-generation products across commercial, enterprise, and automotive markets\nStrengthen the technical foundation and execution quality of PCIe designs used by leading semiconductor companies\nInfluence the technical strategy and roadmap for Synopsys PCIe and interconnect IP, shaping architecture decisions that affect multiple product generations\nRaise the technical capability of the team through mentorship, design leadership, and knowledge sharing that builds long-term strength\nImprove design predictability, quality, and execution efficiency through strong architectural leadership and disciplined engineering practices\nDrive Synopsys' position as a leader in high-speed interface IP by delivering robust, scalable, and silicon-proven solutions\nEnable faster time-to-market for customers by delivering PCIe IP that integrates cleanly and performs reliably in complex SoC environments\nWhat You'll Need\nBachelor's degree in Electrical Engineering with 12+ years of ASIC digital design experience, or Master's degree with 10+ years\nDemonstrated experience as a technical lead or principal engineer driving complex ASIC digital design projects\nDeep expertise in PCIe digital design and architecture, with direct ownership of RTL design and micro-architecture definition\nStrong understanding of ASIC design fundamentals including clocking, resets, low-power techniques, and design for test\nProven ability to drive designs from concept through silicon, including post-silicon debug and support\nExperience with CXL, DDR, AMBA, UCIe, or related high-speed interconnect protocols is highly desirable\nFamiliarity with AI-driven design tools, scripting languages like Perl, TCL, or Python for design automation is a plus\nWho You Are\nYou lead through technical depth, not just delegation. You review RTL, you understand the trade-offs, and you help engineers navigate decisions that do not have clean answers\nYou communicate clearly across disciplines. You can explain a complex PCIe architecture decision to a verification lead, a physical design engineer, and a program manager without losing the thread\nYou care about design quality and maintainability. You push back when a shortcut will create problems three months from now, and you build designs that the next engineer can actually work with\nYou are collaborative and direct. You work well across global teams, you give clear feedback, and you build trust through follow-through and technical credibility\nThe Team You'll Be Part Of\nYou will join the DesignWare Digital IP R&D organization at Synopsys, focused on architecting and delivering world-class PCIe IP. The team spans multiple global sites and works closely with verification, analog, system, and platform teams to deliver silicon-proven solutions for next-generation semiconductor products.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process", "jd_status": "stored"}, {"title": "Senior HW Validation Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-04-14T09:05:14.410000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000120643157-senior-hw-validation-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Role Overview\nThe Sr Hardware Validation engineer serves as embedded hardware domain expert, driving product and platform design quality, evaluation and validation objectives, and technical execution while collaborating closely with systems, firmware/software, validation, and platform develop teams.\nKey Responsibilities\nLead hardware validation planning and execution of embedded products, applications and solutions utilizing a wide portfolio of Renesas products\nDrive hardware technical decisions, ensuring robustness, usability and completeness of hardware platforms\nOwn hardware execution from ideation, validation through qualification and production readiness.\nCollaborate closely with systems, firmware/software, validation, and product engineering teams to ensure seamless hardware‑software integration.\nIdentify and mitigate hardware‑related technical risks, ensuring highest user experience\nPlanning and execution of new product prototype bring-up, bench-testing, and evaluation. \nSupport creation and review of technical documentation (Datasheets, User Manuals/Guides, Application Notes etc)\nFeedback findings, issues, potential improvements to product development teams\nContribute to reference designs, development platforms, and documentation to enable broad customer adoption.\nAct as a technical mentor, influencing best practices and raising the bar for hardware design excellence.\n\nB. Tech/M. Tech in Electrical Engineering, Electronics, Computer Engineering, with at least 5- 7 years of experience\n5-7 years of experience in embedded hardware and system design and validation encompassing microcontrollers, power management and analog/mixed-signal products\nStrong understanding of SoC architecture, ARM cores (A/M series), peripherals, power/clock/reset, and low-power design techniques.\nExperience validating high-speed interfaces (e.g., DDR, USB, PCIe, MIPI, Ethernet) and standard protocols (SPI, I2C, UART, CAN, etc.).\nKnowledge of  C/C++ or embedded programming for firmware development\nHands-on experience with lab tools (oscilloscopes, logic analyzers, power analyzers, thermal sensors).\nFamiliarity with validation frameworks, debug utilities (JTAG, Lauterbach, OpenOCD), and issue tracking systems (JIRA, Bugzilla).\nStrong leadership, communication, and collaboration skills.\nHands‑on experience with Signal Integrity (SI) and Power Integrity (PI) analysis for high‑speed digital, mixed‑signal, and power‑dense designs.\nApplying best practices in schematic design, PCB layout, stack‑up definition, decoupling strategies, and grounding.\nProven experience delivering embedded hardware designs from concept through production.\nPreferred qualifications\nExperience supporting embedded development platforms or reference designs with broad customer adoption across Industrial IoT, Home/Building Automation and Automotive segments\nExecute validation of boot flows, power/clock/reset, memory subsystems, interconnects, and interfaces across stress, corner, and fault scenarios.\nDrive system bring‑up on evaluation boards, emulation/FPGA platforms, and silicon validation setups.\nPerform hands‑on silicon hardware and root‑cause analysis, working closely with design, DV, firmware, and software teams to drive closure.\nAnalyse validation data and logs, track issues through structured closure, and contribute to quality metrics.\nMentor junior engineers and provide technical guidance within the validation team.\nExcellent verbal and written communication skills, including executive-level messaging and presentations.\nAbility to work effectively in a multicultural, cross-functional environment.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nWe have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning.", "jd_status": "stored"}, {"title": "Director - Pre-silicon Emulation / Post Silicon Validation", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-04-14T09:01:00+00:00", "url": "https://global-external-amd.icims.com/jobs/75326/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Director - Embedded X86 SOC Pre-silicon Emulation / Post Silicon Validation Core responsibilities SOC Emulation – Lead the pre-silicon emulation and work closely with SOC design teams to validate the new silicon features Silicon bring-up: Lead the initial bringing up of new silicon and work closely with software and firmware teams to support their work. SOC Feature Enablement - Work with IP and SOC Design to define the enablement sequence and define specs SOC Electrical and Functional valdation - Validate the SOC for Functional and Electrical correctness Cross-functional collaboration: Work with design, verification, and software teams to resolve problems and meet project goals. Test development and execution: Design, develop, and execute validation tests in C/C++ to functionally test the silicon on physical hardware or emulators. Debugging and root cause analysis: Use lab equipment like logic analyzers, oscilloscopes, and protocol analyzers to debug issues, root-cause silicon failures, and verify fixes. Automation: Develop and build automated test suites and validation frameworks to improve efficiency. Reporting: Report on project status and provide feedback to the architecture and design teams. Required skills and experience System-on-Chip (SoC) and ASIC validation: Experience with SoC architecture, pre-silicon emulation, and post-silicon ASIC validation. Programming: Proficient in C/C++ and scripting languages like Python or Perl. Lab equipment: Hands-on experience with lab instruments such as oscilloscopes, logic analyzers, and signal generators. Test development: Experience writing and reviewing validation test plans and developing directed, random, and pseudo-random diagnostics. System integration: Ability to bring up and debug systems on various platforms using tools like JTAG. Problem-solving: Strong analytical and debugging skills to find and resolve complex issues. Automation tools: Experience with creating and building automation suites and test automation tools. #LI-LV1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": " Field Applications Engineer, EDA", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-04-14T05:49:00.907000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000120602347--field-applications-engineer-eda", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "About the role: \nWe are seeking an enthusiastic and motivated individual to join our Field Application Engineering Team in the Digital Channel. The goal of this team is to provide top-level technical service and support to prospects and customers, with a focus on PCB Design and Data Management. We believe that providing a uniquely helpful experience can improve product adoption, long-term customer retention, and grow revenue by increasing the positive perception of the Altium brand.\nRoles &Responsibilities:\nA day in the life of our FAE: \nPerform technical discovery engagements, technical sales presentations, and product (value prop) demonstrations\nCreate and deliver (both live and on-demand) quality technical content to assist sales & marketing campaigns and initiatives\nQuickly grasp client technical and business challenges while establishing personal and company credibility with prospects, customers, and partners\nAs a technical expert, reduce the sales cycle by helping the Sales Team drive the sales process for the assigned opportunities and accounts\nExpand sales pipeline within targeted accounts and serve as the main technical liaison\nParticipate in strategic/tactical planning related to the driving and closing of sales/business opportunities\nDrive adoption and values behind Altium’s product portfolio by increasing subscription commitments, renewal, and Altium brand loyalty\nConstantly expand technical knowledge proactively by exploring technical content and the Altium product roadmap\nRequires knowledge of competitor products, features, different technologies, and business sense in order to place Altium product capabilities strategically to prospects and customers\n\nBachelor’s degree in Electrical, Electronics, or the field of engineering\nLooking for 10+ experience  and must have the desire to work in a fast-paced, ever-changing environment with passion and enthusiasm for Altium Corporate Goals, Visions, Products, and Solutions\nMust be proficient with Altium Designer\nMust be experienced in technical content creation, technical demonstrations and presenting technical materials\nMust possess excellent group and interpersonal communication skills\nA solid understanding of PCB Design, Data Management, and Cloud Solutions,MCAD.\nExperience with PCB Simulation & Analysis (SPICE, Signal Integrity, Power Integrity) is desirable\nAbility to match the business needs and drivers with the correct technical solution\nAbility to perform mid-level Application Engineering, Support, and Sales functions as needed\nAbility to prioritize and perform required tasks and initiatives proactively without direct supervision\nWillingness and ability to travel with short notice\n\nWhy Altium?\nJoin a global leader in design and technology, working with cutting-edge platforms and tools in an exciting and growing industry. This is an opportunity to play a key role in the global education ecosystem, supporting the next generation of innovators while working in a collaborative and dynamic environment\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nWe have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning.", "jd_status": "stored"}, {"title": "Validation/Characterization Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-04-14", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010139", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\nValidation engineers are said to have a 'break-the-part' mentality. This means they spend some of their time working to identify the use-cases in which the device will stop working as intended and understand the impact and cause of those failures. Sometimes, those are acceptable failures, but others we may need to mitigate for quality, safety, or other reasons. Plus, we want to ensure that our parts are consistently performing to the specifications that we set in our TRM and data sheet, and even to some more conservative limits or as defined in the VVCM (validation/verification compliance matrix). \n\nCandidate should also have knowledge of HDL and be hands-on with Palladium to execute the tests and debug along with having automation mindset. Validation engineers will also design, develop, and implement necessary methods of measuring device performance and troubleshooting any related systems, equipment or device issues that arise. Validation engineers are often working in a post-silicon lab or on the software programs required to run their measurements.\n\nExpected knowledge on : Device boot, Arm-Cortex-M0P, communication peripherals (I2C/SPI/UART) and IDE (CCS/IAR). Knowledge on FPGA builds and Microcontroller", "jd_status": "source_unavailable"}, {"title": "CPU Verification Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-04-13", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/CPU-Verification-Engineer_JR2015980", "is_hardware": true, "platform": "workday", "jd_text": "At NVIDIA, we take pride in pushing the edge of computer graphics, PC gaming, and accelerated computing. As a CPU Verification Engineer, you will be involved in development of latest ARM architecture-based CPUs that are engineered for AI execution and are a key component of the Agentic AI hardware stack. This position presents a valuable opportunity to work on pioneering CPU projects with experts in the field. If you strive for innovation and excellence, this is where you belong!\n\nWhat you'll be doing:\nResponsible for verification of ARM architecture-based CPU cores\n\nDevelop and execute thorough unit-level verification plans and create new testbench components\n\nCollaborate closely with design and architecture teams to verify architectural and microarchitectural features\n\nDevelop stimulus using external and in-house RIS tools for end-to-end verification of features\n\nAnalyze and improve existing verification strategies by incorporating AI accelerated workflows to enhance efficiency and effectiveness\n\nWhat we need to see:\nBachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.\n\nAt least 2 years of experience in CPU verification.\n\nProven expertise in ARM architecture and/or CPU microarchitecture verification.\n\nStrong understanding of verification methodologies and tools.\n\nOutstanding problem-solving skills and attention to detail.\n\nExcellent communication and teamwork abilities.\n\nWays to stand out from the crowd:\nDetailed understanding of ARM v9 architecture and/or cache coherency concepts \n\nExposure to unit level (Branch-Predictor/Frontend/Load-Store) verification of high-performance CPU cores\n\nExposure to stimulus generation using RIS tools\n\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status.\n\nWith competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and passionate people in the world working for us and, due to unprecedented growth, our elite engineering teams are rapidly growing. If you're a creative and independent engineer with a real passion for technology, we want to hear from you.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Principal Engineer- Emulation/Validation- PCI/CXL/DDR/Ethernet", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-04-13", "url": "https://careers.synopsys.com/job/bengaluru/principal-engineer-emulation-validation-pci-cxl-ddr-ethernet/44408/88126393648", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Title:\nPrincipal Engineer-High Speed Interface Pre-Silicon Validation/Verification\n \nWe Are:\n \n At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\n \n You Are:\n \n You are a driven and insightful Emulation Expert, passionate about pushing the boundaries of what's possible in ASIC digital design. With a deep understanding of IP interfaces--especially PCIe and DDR--you are skilled in leveraging advanced emulation platforms like Zebu to accelerate verification and product development. Your career is marked by a proven ability to deliver robust, production-ready IP through rigorous emulation and verification cycles. You thrive in highly collaborative, matrixed, and international environments, bringing together diverse teams and perspectives to solve complex challenges.\n \n Your hands-on approach and proactive attitude make you a go-to resource for bridging gaps between Emulation IP and Design IP, ensuring seamless integration and verification of both Controller and PHY components. You have a keen eye for detail and are committed to right-first-time development, always ensuring traceability and completeness across verification requirements. You stay ahead of industry trends, standards, and evolving technologies, and are adept at translating these into actionable insights for your teams. As an excellent communicator and natural collaborator, you are comfortable working with multiple stakeholders and driving change within the organization. Your adaptability, resilience, and commitment to continuous learning set you apart as a leader in your field.\n \n What You'll Be Doing:\n \n  * Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.\n  * Reporting key metrics and driving continuous improvement initiatives in Emulation IP quality and performance.\n  * Providing technical leadership and expertise to define requirements for Emulation IP, ensuring its correct implementation and deployment within verification strategies.\n  * Staying ahead of evolving industry standards, interpreting future changes, ECNs, and specification errata, and integrating this knowledge into Emulation and Design IP teams.\n  * Reviewing and validating test plans for both Emulation IP and Design IP, guaranteeing best-in-class function, feature coverage, and product quality.\n * Collaborating cross-functionally to optimize workflows, standardize methodologies, and ensure compliance with organizational goals.\n  * Mentoring and guiding junior engineers, fostering a culture of innovation and continuous improvement.\n \n The Impact You Will Have:\n \n * Enhancing cross-functional collaboration to elevate product quality and end-customer satisfaction.\n * Transforming the approach to Emulation IP usage in validating cutting-edge digital designs and system architectures.\n  * Driving innovation by defining and refining requirements for IP product development, particularly in emulation contexts.\n  * Championing the adoption of best-in-class verification methodologies across the organization.\n  * Standardizing and optimizing verification workflows to boost efficiency, traceability, and compliance.\n  * Influencing the next generation of emulation and verification solutions, positioning Synopsys as an industry leader.\n * Accelerating time-to-market for high-performance silicon solutions through advanced emulation strategies.\n \n What You'll Need:\n \n  * 10-15 years of relevant experience in emulation, verification, or IP product development.\n  * Expert-level knowledge of PCIe/ DDR / Ethernet interfaces, including protocol and verification strategies.\n  * Extensive hands-on experience with Zebu or similar emulation platforms, particularly for IP verification.\n  * Demonstrated track record in leading IP product development initiatives with a focus on emulation.\n * Strong background in cross-functional collaboration, with an ability to drive consensus and deliver results.\n  * Outstanding communication skills, with the ability to influence and inspire change across diverse teams.\n  * Adaptability and comfort working in a fast-paced, matrixed, and international environment.\n \n Who You Are:\n \n  * A proactive and collaborative problem-solver with a passion for excellence.\n  * Innovative thinker who embraces change and seeks out opportunities for continuous improvement.\n  * Strong communicator, able to articulate complex technical concepts to diverse audiences.\n  * Resilient and adaptable, thriving in dynamic environments and embracing new challenges.\n  * Committed to mentoring others and fostering an inclusive, team-oriented culture.\n \n The Team You'll Be a Part Of:\n \n You will join a dynamic, high-performing engineering team focused on IP development, emulation, and verification at the forefront of semiconductor innovation. Our team is collaborative, cross-functional, and globally distributed, working together to solve complex challenges and deliver industry-leading solutions. You will have the opportunity to collaborate with experts across multiple domains, drive impactful initiatives, and shape the future of digital design and verification at Synopsys.\n \n Rewards and Benefits:\n \n  We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process", "jd_status": "stored"}, {"title": "Staff DFT Solutions Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-04-13", "url": "https://careers.synopsys.com/job/bengaluru/staff-dft-solutions-engineer/44408/93979726384", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nYou are an inventive and detail-oriented engineer with a strong foundation in Computer Science or Electronics, and a passion for advancing the frontiers of Design for Test (DFT) technology. With 3+ years of hands-on experience in DFT, scripting, and software automation, you are eager to take on complex challenges in the rapidly evolving semiconductor industry. You excel in both independent and collaborative environments, thriving in project-oriented settings where you can develop, automate, and validate sophisticated DFT flows and methodologies. Your curiosity and drive for continuous learning make you adept at keeping up with the latest advancements in Autonomous Transportation, Mission Critical AI, High Performance Computing, and Mobile Networking.\n\nAs a candidate, you possess a keen analytical mindset and enjoy problem solving, particularly when it comes to troubleshooting and root cause analysis. You are comfortable working closely with cross-functional teams, providing valuable feedback, and contributing to product readiness. Your experience with scripting languages, RTL coding, and a variety of DFT technologies enables you to deliver scalable solutions tailored to customer architectures and methodologies. You embrace the opportunity to work with cutting-edge tools, including AI-enabled agents, and take pride in producing high-quality documentation and pragmatic solutions. Your exceptional communication and networking skills allow you to bridge gaps between engineering and R&D, ensuring the highest standards in test solutions.\nWhat You’ll Be Doing:\nDeveloping detailed test plans, incorporating new features into test cases, and executing/automating these test cases using Verilog, System Verilog, or VHDL.\nReviewing specifications and test plans from other teams, offering feedback to ensure feature completeness and product readiness. \nCollaborating with Product Engineering and R&D teams to create in-house test cases and implement scalable DFT solutions based on customer requirements. \nPerforming Quality of Results (QOR) analysis, troubleshooting, and root cause analysis to resolve complex technical issues across multiple aspects of the ASIC flow.\nFocusing on tool features such as DFT compression, ATPG for various fault models (SSAF, Transition Delay Fault, Cell-aware faults), and architecting solutions for Memory and Logic BIST.\nConducting diagnostics analysis and debugging to enhance tool reliability and performance.\nWorking with AI agents to review and create assistive or generative AI documentation for test products. \nManaging performance, installation, and license testing to ensure seamless customer experience.\n\nThe Impact You Will Have:\nElevate the quality and performance of Synopsys’ industry-leading DFT tools, directly contributing to customer success and business growth.\nEnable customers to implement robust test methodologies that improve silicon quality and accelerate time-to-market for advanced chips.\nDrive innovation in DFT automation, making cutting-edge solutions accessible across diverse industry segments, from AI to mobile networking.\nStrengthen Synopsys’ reputation as a trusted partner in delivering scalable, reliable, and high-performance test solutions.\nFacilitate cross-team knowledge sharing by providing actionable feedback and creating comprehensive documentation.\nAdvance the adoption of AI-driven testing and automation, keeping Synopsys at the forefront of technological advancement.\nSupport the seamless integration of new features and methodologies, ensuring Synopsys products remain competitive and future-ready.\n\nWhat You’ll Need:\nBachelor’s, Master’s, or MTech in Electrical/Electronics Engineering, Computer Science, or a related field with 3+ years of relevant experience.\nHands-on expertise in DFT technologies such as JTAG, MBIST, Scan, and related test architectures.\nProficiency in RTL coding using Verilog, System Verilog, and/or VHDL.\nAdvanced scripting skills in Perl, Tcl/Tk, Python, or similar languages for automation and tool integration. \nFamiliarity with change management tools (e.g., Perforce) for collaborative development and version control.  \nSolid understanding of ASIC design flow, including design planning, synthesis, physical design, and sign-off verification tools.\n\nWho You Are:\nAnalytical thinker with exceptional problem-solving skills and a passion for troubleshooting complex technical challenges.\nEffective communicator who excels in cross-functional team environments and can articulate technical concepts to varied audiences.\nCollaborative team player who values diverse perspectives and actively contributes to group success.\nProactive and adaptable, with a strong desire to learn and innovate in a fast-paced, evolving technological landscape.\nDetail-oriented and organized, able to manage multiple priorities and deliver high-quality results on schedule.\n\nThe Team You’ll Be A Part Of:\nYou’ll join the Synopsys Test Group, a dynamic team focused on developing cutting-edge Design for Test (DFT) solutions. The team is composed of passionate engineers and innovators who collaborate across product engineering and R&D to create industry-leading methodologies and tools. Together, you will address challenges in diverse domains such as autonomous systems, AI, high-performance computing, and mobile networking, driving the next wave of silicon innovation.\n#TPG", "jd_status": "stored"}, {"title": "Analog Design - Senior Principal Engineer", "company": "Marvell", "location": "Bangalore", "date_posted": "2026-04-13", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Bangalore/Analog-Design---Senior-Principal-Engineer_2601256", "is_hardware": true, "platform": "workday", "jd_text": "About Marvell\nMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. \n\nAt Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. \n\nYour Team, Your Impact\nMarvell is seeking an experienced Senior Principal Analog Engineer to join our Central Engineering organization - the core innovation hub that develops foundational IP leveraged across all Marvell product lines.\nIf you imagine Marvell as a wheel, Central Engineering is the hub, enabling and accelerating innovation across every spoke. In this highly visible role, you will become a key member of an elite analog design team, delivering critical technologies that shape the future of Marvell’s optical and silicon photonics platforms.\nIn this position, you will drive the design and delivery of cutting edge silicon photonics analog circuits that play a pivotal role in next-generation optical interconnect solutions. Your work will directly influence products deployed across CPO, LPO, and advanced 2.5D/3D packaging systems, helping define Marvell’s long-term technology roadmap.\nYou will design, own, and validate complex analog macros used to control, calibrate, and monitor silicon photonics components such as Micro-Ring Modulators (MRMs), Coupled Ring Resonators (CRRs), heaters, and monitor photodiodes.\nWhat You Can Expect\nLead architecture definition and circuit design for high-performance analog and mixed-signal IP used in silicon photonics and optical products.\n· Design and own ADCs, DACs, Regulators, DLLs, PLLs, CTLEs, and Bandgap circuits supporting silicon photonics components such as MRMs, CRRs, heaters, and monitor photodiodes.\n· Drive analog solutions optimized for power, performance, area, cost, and reliability across advanced packaging platforms.\n· Collaborate with cross-functional teams (system, RTL, firmware, verification, DFT, physical design, and packaging) to ensure successful integration.\n· Provide technical leadership from concept through tape-out, post-silicon validation, qualification, and mass production.\n· Support post-silicon bring-up, debug, characterization, and customer‑facing issue resolution.\n· Mentor junior engineers and guide layout activities to ensure design quality and robustness.\n\nWhat We're Looking For\nMaster’s degree in Electrical, Electronics & Communication Engineering (or related field) with 15+ years of experience,\n\nPhD in Electrical, Electronics & Communication Engineering (or related field) with 12+ years of experience\nSpecialization in Microelectronics or Analog/Mixed-Signal Design preferred.\nExperience & Technical SkillsDemonstrated expertise in high-speed and low-power analog design on advanced CMOS technologies.\nProven track record of multiple successful tape-outs into production.\nDeep understanding of CMOS process technology, device physics, and the impact of process variation.\nStrong hands-on experience with EDA tools (Cadence, Synopsys, Mentor Graphics) for schematic capture, simulation, layout, and verification.\nProficiency in post-silicon validation and lab-based debugging of analog and mixed-signal circuits.\n\nLeadership & Collaboration\nExcellent communication and teamwork skills, with experience collaborating across diverse engineering disciplines.\n\nAbility to technically lead projects and coordinate the work of junior engineers.\nStrong problem-solving skills with the ability to analyze and resolve complex design challenges.\n\nAdditional Compensation and Benefit Elements\nWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.\n\nInterview Integrity \nTo support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.\n\nThese tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.\n\nThis position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.\n\n#LI-RV1", "jd_status": "stored"}, {"title": "Design Verification Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-04-10", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010143", "is_hardware": true, "platform": "oracle", "jd_text": "IP Design Verification Engineer (2–5 Years Experience)\n\nAre you passionate about Design Verification and excited about building next-generation automotive connectivity solutions?\n\nOur team at Texas Instruments is expanding! We have been driving innovation in low-power BLE solutions, and now we are stepping into the exciting UWB (Ultra-Wideband) domain. If you want to work on cutting-edge IP development that powers real-world automotive applications, this is your opportunity.\n\nQualifications\nExperience: 2–5 Years\n\nRequired Skillset:\n\nStrong understanding of hardware description languages Verilog/ SystemVerilog / VHDL\n\nHands-on experience with UVM and building DV environments from scratch along with coding block functional models (BFM)\n\nTest plan creation and execution\n\nSolid understanding of fundamentals of CDC / RDC\n\nKnowledge of constrained random verification techniques \n\nUnderstanding of formal verification methodologies\n\nAdditional Advantage:\n\nExperience in CPF / UPF low-power verification\n\nKnowledge of AHB / APB bus protocols\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Design Verification Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-04-10", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010144", "is_hardware": true, "platform": "oracle", "jd_text": "IP Design Verification Engineer (5+ Years Experience)\n\nAre you passionate about Design Verification and excited about building next-generation automotive connectivity solutions?\n\nOur team at Texas Instruments is expanding! We have been driving innovation in low-power BLE solutions, and now we are stepping into the exciting UWB (Ultra-Wideband) domain. If you want to work on cutting-edge IP development that powers real-world automotive applications, this is your opportunity.", "jd_status": "source_unavailable"}, {"title": "LPDDR IP Design Senior Staff Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-04-09", "url": "https://careers.synopsys.com/job/bengaluru/lpddr-ip-design-senior-staff-engineer/44408/93763201616", "is_hardware": true, "platform": "talentbrew", "jd_text": "Synopsys is at the heart of all the advanced silicon design, we supply the essential tools and intellectual properties to enable the semiconductor design, verification, and production. We’re powering all state-of-the-art design market with the world’s most advanced technologies for chip design and software security.\n \nLPDDR PHY IP is a staple of the mixed-signal IP market, and Synopsys is the leading provider of LPDDR PHY IP products.  All current and next-generation technologies are being developed by the LPDDR PHY IP team, both digital and analog components, complement each other in creating a high-performance, high-bandwidth, low-latency and low-power products.\n \nWe are looking for Sr. Staff ASIC Digital Design Engineer to join Synopsys LPDDR PHY IP team to innovate and develop the latest world-class market-leading DesignWare LPDDR PHY IP solution. Be part of a global diverse team that pushes boundaries on LPDDR PHY IP development and solution, your passion and expertise will shape the next generation of product innovation, performance, and efficiency.\n \n \nJob Description\n \nIn this role, you will be in a leadership role to contribute to all phases of designs of DDR PHY IP from design specification to productization, including certain level of customer support into their SoCs.\nDesigning and micro-architecting LPDDR PHY IP writing Verilog and SystemVerilog code and design specification\nConduct simulation and analysis of designs working with Verification, Timing, DFT, and Power team members\nAnalyzing and fixing Lint, CDC/RDC, DFT, Timing, and power issues\nMaintain and improve design automating flow and process\n \nRequired Skills\n \nBS in Electrical Engineering and a minimum of 6 years of experience in complex technical development \nExperience with synthesizable Verilog and System Verilog design concepts, coding, and implementation\nExperience with front-end design flows such as linting, synthesis, timing investigation and closure, cross-domain clocking, DFT, and power optimization techniques\nExhibit excellent communication skills and be self-motivated\nUnderstanding of memory and memory PHY architecture is a plus", "jd_status": "stored"}, {"title": "Design Verification Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-04-09", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010087", "is_hardware": true, "platform": "oracle", "jd_text": "About Group:\n\nPart of the ATD – Advanced Technology Group group of TI. We are a Team working on High-Density Flash Memory. The flash memory is used in various Connectivity, Industrial, Automotive and Application specific control applications. You will be a part of Flash Controller IP Design Verification Team, working on verification of the flash memory controller.\n\nQualifications\nWhat will you be doing in this role? (Responsibilities)\n\nOwn part of IP DV from verification strategy to sign-off\n\nCoverage strategy & coverage closure (Functional, Code & Assertion coverage)\n\nDevelop Test plans, verification strategy, test cases\n\nUse the right Verification strategy: Simulation, Formal, etc.\n\nDevelop UVM components like agents, drivers, monitors and scoreboards\n\nWrite assertion checks for DUT\n\nUse Formal apps like Connectivity, COV, UNR, FPV, etc.\n\nDebug the failures & report RTL bugs/Fix testbench\n\nOwn the regressions for IP \n\nImprove the existing flows using latest methodologies/technologies\n\nBachelors/Masters in VLSI or related field\n\n5-10 yrs. Of Digital Design Verification\n\nStrong command in System Verilog & UVM\n\nCreating DV environment or tests for IP-level digital DV/SoC level\n\nDeveloping DV testbenches, tests, assertion checking for DUT\n\nExperience in Verification tools like: Xcelium, JasperGold or similar\n\nExperience in Function & Code analysis & Closure\n\nExcellent debugging skills\n\nRTL Coding experience is a plus\n\nExperience in embedded memory verification is a plus\n\nMixed digital/analog simulation (Verilog, AMS) is a plus\n\nFormal Verification experience is a plus\n\nShould be able to work with US Team \n\n \n\nWhat do we expect from you? (Mini Qualifications)\n\nBachelors/Masters in VLSI or related field\n\n5-10 yrs. Of Digital Design Verification\n\nStrong command in System Verilog & UVM\n\nCreating DV environment or tests for IP-level digital DV/SoC level\n\nDeveloping DV testbenches, tests, assertion checking for DUT\n\nExperience in Verification tools like: Xcelium, JasperGold or similar\n\nExperience in Function & Code analysis & Closure\n\nExcellent debugging skills\n\nRTL Coding experience is a plus\n\nExperience in embedded memory verification is a plus\n\nMixed digital/analog simulation (Verilog, AMS) is a plus\n\nFormal Verification experience is a plus\n\nShould be able to work with US Team\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Senior Staff Engineer, Static Timing Analysis (STA) Lead", "company": "SiFive", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-04-09", "url": "https://sifive.wd1.myworkdayjobs.com/sifivecareers/job/Bengaluru-Karnataka-India/Senior-Staff-Engineer--Static-Timing-Analysis--STA--Lead_R-101129", "is_hardware": true, "platform": "workday", "jd_text": "About SiFive\n\nAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.\n\nAt SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  \n\nOur constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. \n\nAre you ready?  \n\nTo learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.\n\nJob Description:\n \nAbout the Role We are seeking a highly experienced STA Engineer to serve as the primary technical authority and owner for all timing-related aspects of our next-generation, high-speed data center scale CPUs. In this role, you will define sign-off criteria, drive advanced timing methodologies, and spearhead innovation to accelerate timing closure for massive, high-performance compute architectures at cutting-edge process nodes (N3/N2).\n\nKey Responsibilities\nTechnical Leadership: Act as the primary point of contact and subject matter expert for all STA and timing-related items across the high-speed CPU design team.\n\nMethodology Innovation: Develop and deploy \"correct-by-construction\" methodologies to proactively drive timing convergence early in the design cycle.\n\nPlatform Development: Architect and maintain advanced tracking platforms to monitor and analyze timing convergence metrics across complex data center CPU blocks.\n\nConstraint Management: Lead SDC quality assurance. Collaborate closely with cross-functional partners to ensure pristine, high-quality SDCs through our internal flows\n\nRequired Qualifications\nTiming Signoff & Tools: Deep, authoritative understanding of the complete Timing Signoff process (defining criteria, margins, and closure). Expertise in Synopsys PrimeTime is a must.\n\nAdvanced Node Experience: Proven, hands-on experience taping out complex designs at the 3nm (N3) process node.\n\nPhysical Design Flow: Strong working knowledge of the physical design flow, specifically transitioning from Synthesis through Place and Route (P&R).\n\nSDC Proficiency: Extensive experience in developing, managing, and debugging complex SDCs for massive SoC or CPU designs.\n\nAdvanced Clocking: Strong understanding of Clock Tree Synthesis (CTS) architectures, including Mesh and Multi-Source CTS (MSCTS).\n\nEducation Qualification: A bachelor's or master's in E&E, ECE, CS, VLSI, or PhD is required with 10+ years of experience.\n\nPreferred Qualifications\nHigh-Performance Compute: Direct, proven experience driving timing closure specifically for high-speed, data center scale CPUs.\n\nNext-Gen Nodes: Exposure to or active experience with 2nm (N2) technology nodes is highly preferred.\n\nAdvanced EDA Tools: Hands-on experience with Synopsys FusionCompiler is highly preferred.\n\nAI/ML Integration: Knowledge of Machine Learning (ML)-based timing prediction techniques to reduce design iterations and accelerate sign-off cycles.\n\nAdditional Information:\n\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndia\nAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.\n\nSiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.", "jd_status": "stored"}, {"title": "Test Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-04-08", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009834", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\nTest is a crucial time in an IC development process; if you find a bug or an issue, it is a good time to fix it, but every additional second of testing we do, is additional cost when you scale a device into production. So, test engineers must identify the critical points of the device where testing is most necessary and the points where we may want to take some risk. It is a precise balance, that has the potential to save our businesses millions of dollars!\n\nTest engineers spend a good amount of time in the lab and when they're not there, they are designing test hardware using software tools like cadence and building test programs on an ATE simulator, or troubleshooting – the programs or the device.\n\nWhy Multiphase Processor Power (MPP):\n\nBig Data, Artificial Intelligence, and data centers are just a few of the trends driving the need for high-current multiphase switching power in the Enterprise market. The Multiphase Processor Power product line is focused on bringing to market the multiphase controllers and Smart Power Stage (driver plus power FETs with integrated sensing) solutions for enterprise computing and other ASICs that are power hungry and require very high currents (can be 1000A+).  The MPP team actively collaborates with TI’s advanced technology, packaging and research and development teams to deliver the highest power density solutions for the power level.  \n\nAbout the job\nAt TI, Test Engineers leverage strong technical knowledge working hands-on to bring differentiated power solutions to our customers globally. Test Engineers also partner closely with Design, Test, Systems and Application engineers to ensure our power solutions are both meeting customer and market requirements and are cost-wise optimized. The MPP product line is working on complex multiphase buck controllers and the world’s breakthrough technology to develop the high-power density power stages. \n\nAbout the role and team:\n\nWork with the design team to understand design specifications and system challenges\n\nGenerate test plan, create test and char program, design ATE hardware interface boards\n\nDebug characterizing silicon on ATE, and correlate results with bench data\n\nAnalyze silicon results, supporting failure analysis tasks\n\nPerform statistical analysis of yield fallout, debug and fix yield issues; optimize test time\n\nWork with the production team to release products to volume production\n\nTest strategy definition and implementation for multiphase controller and power stage devices\n\nSilicon qualification, including the qual program development\n\nComprehensive device debugging, design validation, and failure analysis\n\nDrive for robust and cost-effective test solutions while being accountable for product quality\n\nWork with the design and Firmware team to support customer needs, implement custom features in FW. Close collaboration with FW and validation teams to understand the device issues and bugs and find the FW level workaround for the fix.\n\nEngaging with customers with application engineers, to help them understand the device better, help to fix the issues, and provide modifications if any tweaks are needed. This is done in collaboration with Application engineers.\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in Electrical Engineering\n\n5+ years of relevant experience\n\nATE experience on Teradyne Eagle or equivalent analog ATE (iFlex, LTX, VLCT), although Eagle experience is preferred and is a differentiator\n\nCharacterization test program and hardware development experience, Production test program and hardware development experience\n\nStrong technical knowledge of electronic devices and circuits, and Analog test techniques\n\nData analysis skills using Spotfire, dataPower or equivalent tool based on STDF\n\nExperienced with various lab equipment such as scopes, power supplies, sourcemeters, loads etc.\n\nExperience with product engineering activities such as yield improvement and test time reduction\n\nStrong understanding of the IC product development process, from concept to volume production\n\nPreferred qualifications:\n\nMixed signal test techniques and experience with developing mixed-signal tests on TI roadmap testers\n\nExperienced with test program and hardware offload to TI offshore manufacturing sites\n\nProficiency in programming/scripting in C++, Python, C#\n\nStrong fundamentals in electronics: RC networks, operational amplifiers, ADCs, DACs, DC-DC buck converters \n\nExperience to define the test flow, test list and plan to create a test-architecture strategy. \n\nExperience in silicon bring-up and debug, and characterization on the Eagle tester platform \n\nExpertise in schematic design for Hardware/Device Interface Board (HIB/DIB) \n\nExperience in writing test plan and designing test cases \n\nShould be able to lead a project from planning to production release\n\nDemonstrated strong analytical and problem-solving skills\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nStrong time management skills that enable on-time project delivery\n\nDemonstrated ability to build strong, influential relationships\n\nAbility to work effectively in a fast-paced and rapidly changing environment\n\nAbility to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Analog EDA Frontend Lead Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-04-08", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010048", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\nAs an Analog EDA Lead in the team, you will be working on below EDA solutions.\nWork with cross-functional teams within EDA and internal customers and stakeholders in IP and SoC design teams to define, evaluate, and ensure support new EDA solutions\nCollaborate with vendors (Cadence, Synopsys etc) in technical tool evaluations, intersect TI methodologies with vendor roadmaps and offer best solutions to worldwide TI teams.\nInterface between TI ATD teams, TI Foundry services team and external Foundry customers towards successful TI PDKs usage in Foundry design executions.\n\nQualifications\nMinimum Requirements:\nBachelor’s/Master’s degree in Electronics, Electrical Engineering or related field of study\n4-10 years of relevant EDA/CAD experience combined with a passion for automation\n2-3 years of having lead a team of EDA/CAD team\nPreferred Qualifications:\nGood CMOS circuits basics, analog circuits simulation and layout experience\nDemonstrated strong analytical and problem solving skills\nAbility to work in teams and collaborate effectively with people in different functions\nAbility to work effectively in a fast-paced and rapidly changing environment\nAbility to take the initiative and drive to results\nSkills to manage time, delegate and multi-task at work\nStrong verbal and written communication skills\nTeam-work is imperative in this role\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "SOC Physical Design and STA Methodology Engineer", "company": "Samsung", "location": "SSIR, Goldstone, Bangalore, India", "date_posted": "2026-04-08", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/SSIR-Goldstone-Bangalore-India/SOC-Physical-Design-and-STA-Methodology-Engineer_R116203", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.\nRole and Responsibilities\n\nRoles and Responsibilities\n\nExpert in scripting for EDA automation: **Python** (preferred), Tcl, Perl, UNIX shell\nDeep hands-on experience with PnR and Signoff tools: Synopsys (Fusion Compiler, PrimeTime, ICV, Formality) and/or Cadence (Innovus, Genus, Voltus, Tempus)\nDeveloped production-grade PnR flows for partition and Chip Top level designs including power planning, placement, optimization, and routing\nStrong STA fundamentals: Constraints (SDC) development, timing debug, OCV/POCV derates, PVT corners, and ECO flows\nExperience in low power and multi-voltage designs: UPF, power gating, voltage islands\nBuilt automation utilities for PnR execution, signoff analysis, and ECO implementation\nSolid understanding of libraries, cell architectures, and technology files for optimization and ECO stages.\nExperience with AI-driven optimization tools (DSO.ai, Cerebrus)\nAdvanced ECO tool expertise (Tweaker, PrimeClosure)\nFormal verification (LEC) methodology experience\nHierarchical STA and chip-top integration experience\nDTCO and advanced node (3nm, 2nm) exposure\nDebug, enhance, and release PnR and STA signoff flows for multiple projects and process nodes\nDevelop utilities and automation to improve PPA, runtime, and ease of use for design teams\nSupport partition and full-chip design teams on complex convergence issues, timing closure, and DRC fixing\nExplore and deploy new EDA capabilities and PPA optimization recipes to production flows\nDocument flows, create regression tests, and train design teams on methodology best practices\n\nSkills and Qualifications\n\nExperience – 5 to 8 Years\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "Staff DFT Product Engineer - (MBIST, DFT)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-04-08", "url": "https://careers.synopsys.com/job/bengaluru/staff-dft-product-engineer-mbist-dft/44408/93750516640", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:\n At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\n You are a highly skilled and innovative engineer who thrives in dynamic, project-oriented environments. Your expertise spans across digital IC design, with a strong emphasis on Design for Test (DFT), Memory BIST (MBIST), and silicon bring-up. You are passionate about solving complex technical challenges and possess a deep understanding of memory architectures, fault models, and industry standards. You enjoy collaborating with cross-functional teams, engaging directly with customers, and influencing the adoption of next-generation test solutions. Your technical excellence is matched by your ability to communicate clearly and effectively, making you a trusted advisor both within Synopsys and to our clients. You are motivated by continuous learning, eager to prototype new methodologies, and excited by the opportunity to drive innovation in AI-enabled DFT solutions. You bring a customer-centric mindset, always seeking to help others succeed and to optimize their experience with Synopsys products. Whether leading early-adopter customer engagements or partnering with feature development teams, your leadership, adaptability, and drive for excellence make you a valuable member of the Product Engineering Team. If you are ready to make a meaningful impact on the semiconductor industry and help shape the future of test technologies, this role is for you.\n\nWhat You’ll Be Doing:\nProviding deep technical expertise in test solutions across design planning, implementation, and validation of Synopsys Test products.\nLeading MBIST (Memory Built-In Self-Test) implementation and validation, including BIST architecture definition, memory grouping, pattern generation, and silicon bring-up diagnostics analysis and debug.\nDriving, prototyping, and developing next-generation DFT methodologies and test suites to validate Synopsys SMS (Memory BIST) tool features.\nCollaborating with internal stakeholders to define, develop, and deliver innovative capabilities within Synopsys tools.  \nLeading early-adopter customer engagements, coordinating design methodology alignment, flow reviews, and technical readiness.  \nPartnering closely with feature development teams to drive the delivery of AI-enabled DFT solutions.\nProviding technical support, training, and account management to ensure customer success and satisfaction.\nAssessing customer methodologies and flows, gathering requirements, and proposing tailored solutions.\n\nThe Impact You Will Have:\nAccelerate customer adoption of Synopsys DFT and MBIST technologies, enabling successful silicon bring-up and robust test solutions.  \nEnhance the quality and scalability of Memory BIST solutions for complex SoCs with heterogeneous IP integration.  \nDrive innovation in next-generation test methodologies, contributing to the evolution of Synopsys SMS tool features.  \nStrengthen Synopsys’ leadership in AI-enabled DFT and automotive-grade MBIST designs. \nFoster strong customer relationships through technical excellence, problem resolution, and proactive engagement. \nEmpower cross-functional teams with your technical insights, influencing the development and productization of new test technologies.  \nEnsure customer satisfaction and retention through hands-on support, training, and solution delivery.  \nWin new customers by demonstrating Synopsys product advantages via competitive benchmarking and product evaluations.\n\nWhat You’ll Need:\nBachelor’s degree with 7+ years of relevant industry experience, or MS with 5+ years in Electrical Engineering, Computer Engineering, or a closely related discipline.  \nTechnical excellence and hands-on expertise in RTL design, DFT insertion, ATPG, and end-to-end MBIST solution development.\nDeep understanding of memory architectures and test principles, including fault models, MBIST algorithms, and repair strategies (hard/soft, eFuse-based repair flows).\nProven track record of delivering Memory BIST solutions for large, complex SoCs with heterogeneous IP integration.\nExperience or exposure to automotive-grade MBIST designs and in-system test (IST) environments is highly desirable.\nStrong working knowledge of industry test and debug standards: IEEE 1149.1 (JTAG), IEEE 1500, IEEE 1687 (IJTAG).\nExcellent communication and collaboration skills, with the ability to influence teams and engage effectively with customers.\n\nWho You Are:\nInnovative thinker with a passion for solving complex technical challenges.\nCustomer-centric, always seeking ways to help clients succeed.\nEffective communicator and collaborator, able to influence and lead cross-functional teams.\nAdaptable and eager to learn new technologies and methodologies.\nProactive, detail-oriented, and results-driven.\nLeadership qualities with a strong sense of ownership and accountability.\n\nThe Team You’ll Be A Part Of:\n You will join the Product Engineering Team under the Test Group at Synopsys, a dynamic and innovative group dedicated to delivering comprehensive DFT solutions. The team works closely with Solution Architects, feature development teams, and customer-facing engineers to develop and productize next-generation test technologies. Together, you will drive technical excellence and customer success, playing a pivotal role in shaping the future of semiconductor testing.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\n#TPG", "jd_status": "stored"}, {"title": "Staff DFT Product Engineer - (DFT/ MBIST)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-04-08", "url": "https://careers.synopsys.com/job/bengaluru/staff-dft-product-engineer-dft-mbist/44408/93750516656", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nYou are a highly skilled and innovative engineer who thrives in dynamic, project-oriented environments. Your expertise spans across digital IC design, with a strong emphasis on Design for Test (DFT), Memory BIST (MBIST), and silicon bring-up. You are passionate about solving complex technical challenges and possess a deep understanding of memory architectures, fault models, and industry standards. You enjoy collaborating with cross-functional teams, engaging directly with customers, and influencing the adoption of next-generation test solutions. Your technical excellence is matched by your ability to communicate clearly and effectively, making you a trusted advisor both within Synopsys and to our clients. You are motivated by continuous learning, eager to prototype new methodologies, and excited by the opportunity to drive innovation in AI-enabled DFT solutions. You bring a customer-centric mindset, always seeking to help others succeed and to optimize their experience with Synopsys products. Whether leading early-adopter customer engagements or partnering with feature development teams, your leadership, adaptability, and drive for excellence make you a valuable member of the Product Engineering Team. If you are ready to make a meaningful impact on the semiconductor industry and help shape the future of test technologies, this role is for you.\n\nWhat You’ll Be Doing:\nProviding deep technical expertise in test solutions across design planning, implementation, and validation of Synopsys Test products.\nLeading MBIST (Memory Built-In Self-Test) implementation and validation, including BIST architecture definition, memory grouping, pattern generation, and silicon bring-up diagnostics analysis and debug.\nDriving, prototyping, and developing next-generation DFT methodologies and test suites to validate Synopsys SMS (Memory BIST) tool features.\nCollaborating with internal stakeholders to define, develop, and deliver innovative capabilities within Synopsys tools.  \nLeading early-adopter customer engagements, coordinating design methodology alignment, flow reviews, and technical readiness.  \nPartnering closely with feature development teams to drive the delivery of AI-enabled DFT solutions.\nProviding technical support, training, and account management to ensure customer success and satisfaction.\nAssessing customer methodologies and flows, gathering requirements, and proposing tailored solutions.\n\nThe Impact You Will Have:\nAccelerate customer adoption of Synopsys DFT and MBIST technologies, enabling successful silicon bring-up and robust test solutions.  \nEnhance the quality and scalability of Memory BIST solutions for complex SoCs with heterogeneous IP integration.  \nDrive innovation in next-generation test methodologies, contributing to the evolution of Synopsys SMS tool features.  \nStrengthen Synopsys’ leadership in AI-enabled DFT and automotive-grade MBIST designs. \nFoster strong customer relationships through technical excellence, problem resolution, and proactive engagement. \nEmpower cross-functional teams with your technical insights, influencing the development and productization of new test technologies.  \nEnsure customer satisfaction and retention through hands-on support, training, and solution delivery.  \nWin new customers by demonstrating Synopsys product advantages via competitive benchmarking and product evaluations.\n\nWhat You’ll Need:\nBachelor’s degree with 7+ years of relevant industry experience, or MS with 5+ years in Electrical Engineering, Computer Engineering, or a closely related discipline.  \nTechnical excellence and hands-on expertise in RTL design, DFT insertion, ATPG, and end-to-end MBIST solution development.\nDeep understanding of memory architectures and test principles, including fault models, MBIST algorithms, and repair strategies (hard/soft, eFuse-based repair flows).\nProven track record of delivering Memory BIST solutions for large, complex SoCs with heterogeneous IP integration.\nExperience or exposure to automotive-grade MBIST designs and in-system test (IST) environments is highly desirable.\nStrong working knowledge of industry test and debug standards: IEEE 1149.1 (JTAG), IEEE 1500, IEEE 1687 (IJTAG).\nExcellent communication and collaboration skills, with the ability to influence teams and engage effectively with customers.\n\nWho You Are:\nInnovative thinker with a passion for solving complex technical challenges.\nCustomer-centric, always seeking ways to help clients succeed.\nEffective communicator and collaborator, able to influence and lead cross-functional teams.\nAdaptable and eager to learn new technologies and methodologies.\nProactive, detail-oriented, and results-driven.\nLeadership qualities with a strong sense of ownership and accountability.\n\nThe Team You’ll Be A Part Of:\n You will join the Product Engineering Team under the Test Group at Synopsys, a dynamic and innovative group dedicated to delivering comprehensive DFT solutions. The team works closely with Solution Architects, feature development teams, and customer-facing engineers to develop and productize next-generation test technologies. Together, you will drive technical excellence and customer success, playing a pivotal role in shaping the future of semiconductor testing.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\n#TPG", "jd_status": "stored"}, {"title": "FPGA IP Prototyping", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-04-07", "url": "https://careers.synopsys.com/job/bengaluru/fpga-ip-prototyping/44408/101119413984", "is_hardware": true, "platform": "talentbrew", "jd_text": "IP Prototyping Staff Engineer\n\nWe Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nSynopsys is seeking a creative and talented engineer to fill a FPGA Validation role in Bengaluru, India. The environment presents stimulating, challenging, and rewarding work within an excellent work environment with positive career development opportunities.\nFPGA Design and Verification IP Prototyping team is responsible to build FPGA-based hardware prototypes of Synopsys Controllers and PHY Interface IPs and test them to verify their compliance with leading edge industry standards. We play a vital role on supporting Synopsys IP business by validating key features, and mitigating ASIC potential faults early on, in a prototype.\nResponsibilities\nDesign, implement, and verify FPGA-based systems for a variety of applications\nValidate FPGA-based IP prototype 'Device Under Test' against real-world devices, Test Equipment and other hardware systems\nCreate and maintain comprehensive technical documentation\nElaborate and execute test plans and test routines\nDetect, troubleshoot, debug, and investigate potential ASIC issues up front\nEstablish and maintain relationships with cross-functional teams, internal and external customers\nKey Qualifications\nBachelor's or master's degree in electrical engineering\n5+ years of experience in FPGA design and development\nDesign and simulate integrated circuitry using Verilog, System Verilog\nExpertise with industry-standard scripting languages such Tcl, Python, Perl and Bash\nExpertise with industry-standard interfaces and protocols such as AMBA AXI or APB.\nExperience with FPGA development tools such as XILINX Vivado. Familiarity with Synopsys Synplify or Protocompiler is a plus\nExperience in digital design methods such as floor planning, timing constraints definition, and static timing analysis\nExcellent verbal and written communication skills in English\n\nPreferred Experience\nExpertise with HAPS-100,HAPS-80 Boards and Protocompiler Flows\nFamiliarity with peripheral interfaces like SD/eMMC and (LP)DDR\nFamiliarity with simulation tools such as VCS\nFamiliarity with laboratory equipment such as Oscilloscopes, Protocol-Analyzers\n\nTravelling\nAs a worldwide organization there is sometimes short term travel maybe required.\n\nThe Team You’ll Be a Part Of:\nYou will be joining the FPGA Design and Verification IP Prototyping team, a group of innovative engineers dedicated to building FPGA-based hardware prototypes of Synopsys Controllers and PHY Interface IPs. The team plays a pivotal role in supporting Synopsys' IP business by validating key features, mitigating ASIC potential faults early, and ensuring compliance with industry standards. Collaboration and continuous learning are at the heart of the team, offering a stimulating, challenging, and rewarding environment with positive career development opportunities.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Analog Flash Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-04-07", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25010077", "is_hardware": true, "platform": "oracle", "jd_text": "Position Overview: \n\nAnalog and Mixed Signal Designer (Embedded Flash Memory)\n\nWe are seeking a highly skilled and experienced Analog and Mixed Signal Designer to contribute to the development of cutting-edge embedded Flash Memory IPs, which are comprised of analog and mixed-signal circuits. The ideal candidate will have a strong analog/mixed-signal background, hands-on experience in relevant design areas, and a deep understanding of underlying device physics. This is an Individual Contributor (IC) role focused on technical execution and collaborative innovation.\n\n \n\nKey Responsibilities:\n\n1. Technical Execution and Design:\n\nExecute the design, development, and verification of analog and mixed-signal circuits for flash memory development, including charge pumps, voltage regulators, sense amplifiers, and memory interfaces.\n\nAnalyze and review circuit architectures to optimize performance, power, and area (PPA) under the guidance of technical leads.\n\nDrive assigned technical tasks to address industry challenges in scaling, performance, and reliability for flash.\n\nCollaborate with world-wide cross-functional teams, including layout, process, test engineering, and product teams.\n\nEnsure designs meet technical specifications, project timelines, and quality standards.\n\nIdentify and mitigate design risks, ensuring robust circuit performance under process, voltage, and temperature (PVT) variations.\n\n \n\n2. Collaboration and Communication:\n\nWork closely with flash bit-cell architecture and product teams to align circuit design with system-level requirements.\n\nInterface with Process teams (Process Integration Engineers) to optimize technology for flash/NVM applications.\n\nPresent project updates, technical reviews, and status reports to stakeholders and senior management.\n\n \n\n3. Innovation and Best Practices:\n\nStay updated on industry trends, emerging technologies, and best practices in embedded flash and analog design.\n\nContribute to the continuous improvement of design methodologies, tools, and workflows.\n\nQualifications\nQualifications:\n\n1. Education:\n\nBachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or a related field.\n\n \n\n2. Experience:\n\n3+ years of experience in analog/mixed-signal circuit design, with demonstrated focus on relevant embedded flash development concepts.\n\nExperience with complex designs and ownership of key circuit blocks.\n\n \n\n \n\n \n\n3. Technical Skills:\n\nDeep understanding of NVM/embedded flash operation principles, including programming, reading, and reliability considerations.\n\nWorking experience with various analog building blocks, such as current mirrors, operational amplifiers, sense amplifiers, charge pumps, oscillators, and LDOs.\n\nProficient in design and simulation tools (e.g., Cadence Virtuoso, SPICE simulators, extraction tools).\n\nFamiliarity with process technology and layout considerations for relevant advanced nodes (e.g., 28nm).\n\nDevice physics knowledge, particularly related to reliability and device behavior over PVT.\n\nProficiency in scripting languages such as PERL or Python.\n\n \n\n4. Desirable:\n\nExperience in silicon bring-up, debug, and characterization.\n\nKnowledge of reliability challenges such as endurance, retention, and soft errors in flash/NVM.\n\nDemonstrated strong analytical and problem-solving skills.\n\nStrong verbal and written communication skills.\n\nAbility to work in teams and collaborate effectively with people in different functions.\n\nStrong time management skills that enable on-time project delivery.\n\nAbility to work effectively in a fast-paced and rapidly changing environment.\n\nAbility to take the initiative and drive for results.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Principal Engineer- DEG Layout", "company": "Micron", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-04-06T00:00:00+00:00", "url": "https://micron.eightfold.ai/careers/job/40862780", "is_hardware": true, "platform": "eightfold", "jd_text": "Our vision is to transform how the world uses information to enrich life for all.\nMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.\n\nRole and Responsibilities\nResponsible for layout design and development of critical analog, mixed-signal, custom digital block, standard cells  and full chip level.\nPerform layout verification like LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem checks,  quality check and documentation.\nResponsible for development of digital block layouts using auto placement and route tools\nResponsible for basic understanding of skill coding and automation\nResponsible for on-time delivery of block-level layouts with acceptable quality.\nDemonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/breakthroughs in multiple project environment.\nGuide team members in their execution of Sub block-level layouts & review their work\nEffectively communicating with Global engineering teams to assure the success of layout project.\nResponsible for the reducing the layout effort by using AI\n\nAbout Micron Technology, Inc.\nWe are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.\n\nTo learn more, please visit micron.com/careers\n\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.\n\nTo request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com\n\nMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.\n\nMicron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.\n\nAI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.   \n\nFraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.", "jd_status": "stored"}, {"title": "System-On-Chip Architect (SOC)", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-04-06", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009980", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n  \n\nIn this position, you will be architecting mixed-signal microcontroller systems featuring ARM Cortex-M0+/M33/RISC-V processors, as well as defining the overall system architecture for integrated platforms that combine high-performance analog peripherals with advanced digital communication interfaces  as part of comprehensive SoC solutions.\n\nYour responsibilities will include system partitioning, architectural modeling, power domain optimization &  interface specification development of microcontroller systems supporting multiple operating modes. \n\nAs a system architect, you will define architectural requirements and specifications for devices & IP. You will develop innovative system-level solutions to complex integration challenges through evaluation of various processing approaches and power management techniques. You will lead cross-functional architectural initiatives to ensure timely delivery of platform specifications with strategic oversight on routine architectural decisions and detailed technical guidance on next-generation embedded system innovations.\n\nThis position involves extensive collaboration with a highly talented team of analog designers, digital circuit engineers, embedded software architects, and applications engineers to solve complex system integration challenges and present architectural vision, as well as active leadership in technical working groups driving innovation in microcontroller platforms and industrial automation solutions.\n\nQualifications\n## Minimum Requirements:\n\n \n1. 10+years of relevant experience in system architecture or digital design\n2. Deep understanding of ARM Cortex processor architectures and embedded system design \n3. Thorough knowledge of system-on-chip (SoC) architecture and subsystem integration methodologies\n4. Strong problem-solving skills with ability to analyze complex system-level challenges and develop innovative solutions\n5. Solid foundation in digital design principles and hardware/software interface design\n\n \n## Preferred Qualifications:\n\n \n1. Proven track record of translating system requirements into implementable architectural specifications\n2. Demonstrated expertise in architecture trade-off analysis \n3. Experience with Cortex-M families and their ecosystem\n4. Strong analytical and critical thinking skills for resolving multi-disciplinary technical challenges\n5. Ability to work in teams and collaborate effectively with people in different functions\n6. Ability to adapt quickly to evolving requirements in a fast-paced environment\n7. Excellent verbal and written communication skills\n\n \n## Additional Technical Competencies:\n\n \n1. Ability to look at end to end solutions & derive system requirements.\n1. Ability to evaluate and convert high level requirement into a HW and/or SW features.\n2. Assess high level market requirements for cost, power, security, safety implications.\n3. Work with estimation tools (simulators, spreadsheets, Python tools, matlab models, etc) to model performance of design choices.\n4. Work with design-oriented tools and outputs (xml, sims, waveforms, etc)\n5. Ability to make good judgements based on early / partial data\n6. Ability to do \"what if\" thinking to make sure that IP/SOC definitions are not missing opportunities or falling behind.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Staff Engineer- Design", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-04-02T17:58:39+00:00", "url": "https://jobs.infineon.com/careers/job/563808970100893", "is_hardware": true, "platform": "eightfold", "jd_text": "Design Implementation and a solid understanding of SoC Design/Integration who can own and drive SoC /Synthesis and Front End Signoff topics.\n\nYour Role\n\nKey responsibilities in your new role\n\nBe responsible for defining state-of-the-art SoC integration for mixed signal designs, including participation in related tool evaluations\n•Own and drive SoC Integration/Synthesis and Front End Signoff topics.\n•Drive best practices and lessons learnt from evaluations/benchmarks and customer interactions back into Methodology development\n•Share knowledge with other analog/digital integration experts and contribute to Methodology Expert Groups.\n•Closely cooperate with analog circuit and physical design engineers, as well as with the digital design counterparts.\n\nYour Profile\n\nQualifications and skills to help you succeed\nA university degree in Electrical Engineering, Microelectronic or comparable\n•A strong understanding of SOC Design and Low power, CDC/LINT tools.\n•5 to 8+ years of experience of direct Industry experience.\n•Experience with Cadence or Synopsys tools in Digital Implementation and Verification (Synthesis, PnR, STA)\n•Hands on with Analog Block Integration at SoC .\n•In-depth knowledge of Low Power Implementation and UPF.\n•Strong experience in scripting skills (PERL, TCL, Python).\n\nContact:\n    VidhiAshok.Thakkar@infineon.com\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\nThis means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.\nPlease let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.\nClick here for more information about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Validation Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-04-02", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009947", "is_hardware": true, "platform": "oracle", "jd_text": "We are expanding our team in the Connectivity BU and looking for passionate engineers to join us!\n\nAbout the Team:\n\nOur team has been working on BLE products and is responsible for pre-silicon and post-silicon functional validation of SoCs (including peripherals and ROM FW).\n\nWe are now planning to expand into the exciting UWB domain.\n\nAdditionally, the team plays a key role in collecting FPGA requirements from various teams (SW, ROM, PE, etc.) and delivering quality-checked FPGA builds to stakeholders.\n\n Experience Required:\n\n5+ years\n\nQualifications\nWhat We Expect from Candidates:\n\nGood understanding of ARM core-side debug architecture\n\nComfortable working with TI CCS tools\n\nExperience in developing test plans and test suites from scratch for pre and post silicon validation\n\nStrong debugging skills on Cadence Palladium and FPGA boards\n\nDebug experience on silicon using HW scopes\n\nHas experience of building FPGA bit file of SOC\n\nStrong understanding of serial protocols like I2C, I2S, CAN, SPI, UART (added advantage)\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "AMS Verification Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-04-02", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009962", "is_hardware": true, "platform": "oracle", "jd_text": "About TI \nTexas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world’s brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We’re committed to building a better future – from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. Put your talent to work with us – change the world, love your job! \nWho are we and what do we do?\nThe advanced circuits and power solution business is known for delivering industry leading custom IC system solutions including display and touch power products, charger power products, camera PMICs, power path devices, sensing devices and high-performance communication interface products. Our products integrate precision signal-chain and highly efficient power components in ultra-small form factors that enable TI’s best-in-class customer to translate their ideas to high value products that revolutionize the personal electronics market. \n\nIn this team, you will get to work with, and learn from incredibly talented technical leaders, who have influenced TI technology, productivity and way of working in a creative and impactful way. You will get to directly interact with one of TI’s valued and high-volume customers, by way of intense technical reviews and architecture discussions! \n\nBy enabling designs that are highly impactful to TI revenue and working with a critical customer on a versatile set of products, you will find yourself on an accelerated career path. \n\n \nAbout the job \nIf you are looking to join an ingenious, vigorous & ambitious team that consistently delivers groundbreaking technologies into the custom mobile electronics world, here is an opportunity for you!   \nSenior Analog Mixed-Signal (AMS) Verification Engineer\nLocation: Bangalore, India\nExperience: 3–10 Years\nWhat will you be doing in this role?\nVerification Strategy: Develop detailed coverage-driven Verification Plans by collaborating closely with System, Application, and Design teams.\nModelling & Simulation: Create high-fidelity analog behavioural models using Verilog-A, Verilog-AMS, Wreal (RNM) or EENet to enable efficient top-level simulation.\nEnvironment Development: Build and enhance mixed signal testbenches using a combination of schematic, models, and RTL.\nCheckers & Assertions: Implement real-time analog checkers and post-processing checker strategies to ensure functional correctness.\nFull-Cycle Verification: Execute RTL and Gate Level Simulations (GLS), running regressions and tracking functional coverage goals until tape-out.\nCollaboration: Work with Digital DV, Analog Designers, and Post-Silicon Validation teams to debug complex issues and ensure successful product delivery.\n\nQualifications\nBasic Requirements (Must-Haves)\n\nEducation: Bachelor’s or Master’s degree in Electrical Engineering (EE) or Electronics and Communication Engineering (ECE) \n\nExperience: Minimum 3 years of hands-on experience in Analog Mixed-Signal (AMS) design verification.  \n\nModelling Skills: Proficiency in analog behavioural modelling using Verilog-AMS, Verilog-A, or Wreal.  \n\nVerification Flow: Direct experience with mixed-signal verification involving a combination of schematic, behavioural models, and RTL.  \n\nTool: Strong command of Cadence Virtuoso/AMS Designer toolsets and debug environments or other standard mixed-signal simulation tools\n\nCommunication: Clear ability to present technical analysis and conclusions to internal stakeholders and business leaders.  \n\nPreferred Skills & \"Good to Have\" (Innovation & Automation)\n\nAdvanced DV: Knowledge of SystemVerilog (SV) and UVM, as the top-level environments are built on these frameworks.  \n\nAutomation: Proficiency in scripting (Python, Perl, or Shell) to automate simulation flows and data analysis. Exposure and interest in building AI-driven verification methodologies. \n\nDomain Expertise: Experience in signal processing, PMICs, or high-speed communication interfaces.  \n\nSilicon Interaction: Experience in silicon debug and working alongside silicon validation teams. \n\nStandard protocols exposure: Verification experience with I2C, SPI, UART, ASI etc.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Senior Layout Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-04-02", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009965", "is_hardware": true, "platform": "oracle", "jd_text": "About TI\n\n Texas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world’s brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We’re committed to building a better future – from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. Put your talent to work with us – change the world, love your job! Who are we and what do we do?\nThe advanced circuits and power solution business is known for delivering industry leading custom IC system solutions including display and touch power products, charger power products, camera PMICs, power path devices, sensing devices and high-performance communication interface products. Our products integrate precision signal-chain and highly efficient power components in ultra-small form factors that enable TI’s best-in-class customer to translate their ideas to high value products that revolutionize the personal electronics market. \n\nIn this team, you will get to work with, and learn from incredibly talented technical leaders, who have influenced TI technology, productivity and way of working in a creative and impactful way. You will get to directly interact with one of TI’s valued and high-volume customers, by way of intense technical reviews and architecture discussions! \n\nBy enabling designs that are highly impactful to TI revenue and working with a critical customer on a versatile set of products, you will find yourself on an accelerated career path. \n\n   \nAbout the job If you are looking to join an ingenious, vigorous & ambitious team that consistently delivers groundbreaking technologies into the custom mobile electronics world, here is an opportunity for you!   Senior Analog Layout Engineer\nLocation: Bangalore, India\n\nExperience: 3–10 Years\n\n \n\nRoles and responsibilities:\n\nFrame the layout schedule, effort estimation, risk and mitigation plan of layout activities for all layout engineers in the project\n\nWork closely with designers to understand the architecture and key requirements for the IC\n\nStrike right balance of area, performance and schedule during layout development by collaborating with design, packaging and process teams\n\nWork closely with Process development team to carry out PDK, P-cell and Design rule updates\n\nWork closely with Packaging engineer to develop custom lead-frames for various packages \n\nAnalysis and closure of Electro Migration, Thermal gradients, ESD/LU performance and layout parasitic\n\nRoutinely develop test vehicles for new process & package technology development\n\nMentor and guide junior layout engineers/contract engineers, review their work and provide feedback to meet the quality and schedule norms \n\nResponsible for the final layout which meets the design expectations and layout checklist.\n\nIdentify improvements needed in process/ quality/ cycle time and take up necessary initiatives\n\nQualifications\nKnowledge and skills:\n\nFull chip layout experience from definition through release of IC to production\n\nStrong LVS, DRC, ERC, and antenna debug skills\n\nProficient in analog and mixed-signal layout techniques and verification process including Device Matching, Power Bus design, avoiding Cross-talk, ESD/LU protection techniques\n\nGood understanding about all layout parasitics (R, C, diodes, BJTs)\n\nGood understanding of device physics and semiconductor fabrication process\n\nMust have worked on some of the Technologies like: 40nm, 65nm, 90nm, 130nm, 180nm, BiCMOS, BCD\n\nShould be well versed with tools such as Virtuoso XL/Assura /PVS/Voltas\n\nAbility to quickly ramp up on new tools/ process and mentor LEs\n\nExperience in automation/ SKILL coding for reducing cycle time/ quality checks will be an added advantage\n\nRequires excellent teamwork, good communication, strong problem-solving and documentation skills.\n\nStrong time management skills for on-time project delivery\n\nAbility to take initiatives and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Validation Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-04-02", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009948", "is_hardware": true, "platform": "oracle", "jd_text": "We are expanding our team in the Connectivity BU and looking for passionate engineers to join us!\nAbout the Team:\n\nOur team has been working on BLE products and is responsible for pre-silicon and post-silicon functional validation of SoCs (including peripherals and ROM FW).\nWe are now planning to expand into the exciting UWB domain.\nAdditionally, the team plays a key role in collecting FPGA requirements from various teams (SW, ROM, PE, etc.) and delivering quality-checked FPGA builds to stakeholders.\n \nWhat's in it for you? \nEnd-to-End Silicon Exposure : \nBe part of the complete SoC lifecycle — from early design discussions with Architecture and Design teams to seeing fabricated silicon reach end customers.\n\nHands-on Pre & Post-Silicon Experience : Work on module validation during the pre-silicon phase using FPGA and Palladium platforms, and gain post-silicon bring-up experience with TI silicon.\nCross-Functional Collaboration : Collaborate closely with Architecture, Design, Validation, and System teams, building a strong understanding across domains.\nReal Impact, Real Products : Contribute directly to products that move from concept to reality, giving you unmatched industry-relevant experience\n \n \n \nExperience Required:\n\n2 to 5 years\n\nQualifications\nWhat We Expect from Candidates:\n\nGood understanding of ARM core-side debug architecture\n\nComfortable working with TI CCS tools\n\nExperience in developing test plans and test suites from scratch for pre and post silicon validation\n\nStrong debugging skills on Cadence Palladium and FPGA boards\n\nDebug experience on silicon using HW scopes\n\nStrong understanding of serial protocols like I2C, I2S, CAN, SPI, UART (added advantage)\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Digital Mixed Signal DV Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-04-02", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009964", "is_hardware": true, "platform": "oracle", "jd_text": "About TI \nTexas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world’s brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We’re committed to building a better future – from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. Put your talent to work with us – change the world, love your job! \nWho are we and what do we do?\nThe advanced circuits and power solution business is known for delivering industry leading custom IC system solutions including display and touch power products, charger power products, camera PMICs, power path devices, sensing devices and high-performance communication interface products. Our products integrate precision signal-chain and highly efficient power components in ultra-small form factors that enable TI’s best-in-class customer to translate their ideas to high value products that revolutionize the personal electronics market. \n\nIn this team, you will get to work with, and learn from incredibly talented technical leaders, who have influenced TI technology, productivity and way of working in a creative and impactful way. You will get to directly interact with one of TI’s valued and high-volume customers, by way of intense technical reviews and architecture discussions! \n\nBy enabling designs that are highly impactful to TI revenue and working with a critical customer on a versatile set of products, you will find yourself on an accelerated career path. \n\n \nAbout the job \nIf you are looking to join an ingenious, vigorous & ambitious team that consistently delivers groundbreaking technologies into the custom mobile electronics world, here is an opportunity for you!   \nDigital Design Verification (DV) Engineer\nLocation: Bangalore, India\nExperience: 3–6 Years\nWhat will you be doing in this role?\nVerification Strategy: Drive the verification strategy, create detailed Test Plans, and develop comprehensive Test Benches for Chip Top levels.\nUVM Architecture: Responsible for grounds-up development of the DV environment, including coding UVM components like agents, drivers, monitors, and scoreboards.\nFull-Cycle Execution: Execute RTL and Gate Level Simulations (GLS), running regressions and tracking functional and code coverage (Block, Expression, Toggle, FSM) to achieve 100% closure. Worked on standard communication protocols like I2C, ASI, SPI, UART etc.\nTechnical Debugging: Utilize excellent debugging and problem-solving skills to resolve complex design and testbench issues.\nPost-Silicon Support: Interact with Product and Application Engineering teams to support ATE functional pattern generation and silicon characterization.\nCross-Functional Collaboration: Work closely with Architecture, Design, and Firmware teams to ensure successful product execution.\n\nQualifications\nBasic Requirements (Must-Haves)\n\nEducation: Bachelor’s or Master’s degree in Electrical Engineering (EE) or Electronics and Communication Engineering.\n\nExperience: Minimum 3 years of experience in IP-level and SoC-level Digital Design Verification.\n\nCore Competencies: Strong expertise in SystemVerilog (SV) and UVM methodologies.\n\nTools: Proficiency with Cadence simulation tools and environments (e.g., Xcelium, Vmanager).\n\nCommunication: Effective communication and interpersonal skills to interact with worldwide cross-functional experts and stakeholders.\n\nPreferred Skills & \"Good to Have\" (Innovation & Automation)\n\nFormal Verification (FV): Experience with Formal property verification (FPV), Connectivity checks, and Unreachability (UNR) analysis for top-level sign-off.\n\nClock & Reset Domain: Understanding of CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) assertions, with the ability to write and debug them.\n\nLow Power Verification: Specific experience with UPF (Unified Power Format) for low-power verification and power-aware simulations.\n\nAutomation Mindset: Ability to automate verification flows and repetitive tasks using Python, Perl, or Shell scripting.\n\nMixed-Signal Exposure: Basic knowledge or exposure to AMS (Analog Mixed-Signal) verification environments is an added advantage.\n\nMethodology Innovation: Ability to innovate and drive improved verification methodologies and work with EDA teams to upgrade tools. Exposure to building AI-driven verification methodologies.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Lead Analog Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-04-02", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009958", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n  Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\n  This is a great opportunity to be part of an established team that's continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electronics, mobile computing and communications.\n\nWho are we and what do we do?\n\nThe advanced circuits and power solution business is known for delivering industry leading custom IC system solutions including display and touch power products, charger power products, camera PMICs, power path devices, sensing devices and high-performance communication interface products. Our products integrate precision signal-chain and highly efficient power components in ultra-small form factors that enable TI’s best-in-class customer to translate their ideas to high value products that revolutionize the personal electronics market. \n\nIn this team, you will get to work with, and learn from incredibly talented technical leaders, who have influenced TI technology, productivity and way of working in a creative and impactful way. You will get to directly interact with one of TI’s valued and high-volume customers, by way of intense technical reviews and architecture discussions! \n\nBy enabling designs that are highly impactful to TI revenue and working with a critical customer on a versatile set of products, you will find yourself on an accelerated career path. \n\n   \nAbout the job If you are looking to join an ingenious, vigorous & ambitious team that consistently delivers groundbreaking technologies into the custom mobile electronics world, here is an opportunity for you!   Senior Analog Design Engineer\nLocation: Bangalore, India\n\nExperience: 5+ Years\nWhat will you be doing in this role?\n\nAnalog Chip/Sub-section/IP architect and design with complete ownership and responsibility from definition to release to manufacturing.\n\nDirect, guide and participate in activities of a research or technical design function responsible for designing, developing, modifying and evaluating electronic parts, components, integrated circuits for a variety of applications.\n\nProviding design guidance to team members as needed, developing schedules and monitoring progress throughout the project.\n\nEvaluate intermediate and final results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives.\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout.\n\nCollaborate with Design Verification teams during the pre-PG phase of a project to ensure completion of all technical tasks before PG.\n\nWork with systems engineers, application engineers and assisting in the definition of the product to meet customer needs.\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production.\n\nInterface and lead discussions with the customer and/or TI field sales/field applications teams to understand customer designs, problems and support as required.\n\nActively participate in hiring, developing and evaluating personnel to ensure efficient operation of the organization and growth of the individuals into leader.", "jd_status": "source_unavailable"}, {"title": "Analog Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-04-02", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009946", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\n This is a great opportunity to be part of an established team that's continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electronics, mobile computing and communications.\n\nIn this role, responsibilities may include:\n\nDesigning state of the art NVM memories -- EEPROM, EPROM, Poly-Fuse, Fuse, Anti-fuse etc for commercial, automotive, and industrial applications\n\n   -        Designing peripheral analog IPs for memories like high voltage generators, Voltage, and current references, LDO, Oscillators etc.\n\n   -        Working with World-wide Technology and Process development owners to influence best in class NVM component development  \n\n   -        Design Verification to ensure design robustness. This includes running PVT verification, statistical simulations as well as analyzing the impact of extracted parasitics.  \n\n   -        Collaborating with validation, product engineering, and test engineering teams to enable successful transfer to production.", "jd_status": "source_unavailable"}, {"title": "Senior Staff Engineer Design", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2026-04-01T10:00:39+00:00", "url": "https://jobs.infineon.com/careers/job/563808970264607", "is_hardware": true, "platform": "eightfold", "jd_text": "Experience in Spec extraction, Architecture/Microarchitecture definition, Digital IP/Subsystem Design/Integration, Mixed signal IP Integration, SoC Integration.\n\nYour role\nKey responsibilities in your new role\n\nArchitecture Definition: Must be able to extract requirements from Specs, Partition requirements, define Architecture/microarchitecture.\nDigital Lead: Must be able to act as a Digital functional lead for execution lead of IP/Sub-System or an SoC.\nTechnical Expert: Must be able to provide Technical expertise on Digital Design, Architecture & Front-End flow.\nCross Functional Collaboration: Must be able to engage with various cross functional teams including Verification, Analog, Back-End, Marketing, Validation to ensure alignment on product objectives.\n\nYour profile\nQualifications and skills to help you succeed \n\nBachelor's or Master's degree in a relevant field, such as Electronics, Digital Design, VLSI, SoC Design.\n10 to 15 years of experience in Spec extraction, Architecture/Microarchitecture definition, Digital IP/Subsystem Design/Integration, Mixed signal IP Integration, SoC Integration.\nStrong technical knowledge of Front-End flows including Linting, CDC,RDC, Timing Constraints, Power intent, Synthesis, DFT, ATPG, Fault Grading, LEC, MVRC.\nGood Understanding of Back-End flows including PNR, STA.\nStrong Communication skills to interact with Cross functional teams and lead execution teams.\nGood understanding of serial protocols like I2C, SPI, UART, PMBUS\nExposure to Point of Load converters, Gate driver controllers, PMICs etc.\nPreferable understanding of Automotive Functional Safety standards.\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nVidhi Thakkar", "jd_status": "stored"}, {"title": "Staff Software Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-04-01", "url": "https://careers.synopsys.com/job/bengaluru/staff-software-engineer/44408/93498496944", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are\nYou are a passionate and driven R&D Engineer with a deep understanding of data structures, algorithms, and their applications. You have a strong background in software development, particularly with C/C++ on UNIX/Linux platforms, and are eager to tackle complex, large-scale software code-based tool development. With a minimum of 8 years of related experience, you have honed your analytical, debugging, and problem-solving skills. You thrive in both self-directed and collaborative environments and are committed to continuous learning and exploration of new technologies. Your excellent communication skills in English enable you to effectively collaborate with team members and present your ideas clearly.\nWhat You’ll Be Doing\nSupporting the existing functionality of our tools and continually enhancing their versatility, performance, and memory utilization while improving software quality.\nApplying extensive knowledge of algorithms and data structure design to develop robust and efficient implementations that improve tool performance and customer adoption.\nInteracting with other Synopsys R&D members and customers to understand their needs and product goals.\nContributing to the development of complex software code-based tools in a multi-person product development environment with high dependencies and tight schedules.\nExercising judgment in developing methods, techniques, and evaluation criteria to meet project goals.\nCollaborating with a team of enthusiastic and creative engineers to drive innovation and excellence.\nThe Impact You Will Have\nEnhancing the performance and quality of our verification tools, leading to increased customer satisfaction and adoption.\nDriving continuous improvement in software development processes and practices.\nContributing to the development of cutting-edge technologies that power innovations in various industries.\nHelping Synopsys maintain its leadership position in the market by delivering high-performance solutions.\nInfluencing the direction and success of our hardware verification tools through your expertise and innovation.\nFostering a collaborative and innovative work environment that encourages growth and learning.\nWhat You’ll Need\nA Bachelor’s degree in Electrical/Electronics/Computer-Science Engineering with a minimum of 5 years of related experience, or a Master’s degree with 3 years of relevant experience.\nIn-depth understanding of data structures, algorithms, and their applications.\nExcellent software development experience with C/C++ on UNIX/Linux platforms.\nExposure to Python, TCL, and shell scripting languages is preferable.\nExposure to HDL languages like Verilog or System Verilog is desirable, with a willingness to learn their nuances.\nDemonstrated history of good analytical, debugging, and problem-solving skills.\nExperience with complex and large software code-based tool development.\nWho You Are\nYou are a motivated and enthusiastic engineer who excels in both independent and collaborative settings. You have a solid desire to learn and explore new technologies, and you exercise good judgment in developing methods and techniques to meet project goals. Your excellent written and oral communication skills in English enable you to collaborate effectively and present your ideas clearly. Special consideration will be given to candidates with a background in hardware functional verification and/or synthesis techniques, as well as knowledge of software specification, design processes, and regression testing.\nThe Team You’ll Be A Part Of\nYou will join the Hardware Assisted Verification team at Synopsys, a group of dedicated and innovative engineers focused on developing and enhancing our verification tools. Our team is committed to pushing the boundaries of technology and delivering high-performance solutions that meet the needs of our customers. We work in a collaborative and dynamic environment, where creativity and innovation are encouraged and valued.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\n\n#TPG", "jd_status": "stored"}, {"title": "Lead Test Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-04-01", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009817", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\nAbout TI\n\n Texas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world’s brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We’re committed to building a better future – from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. In TI’s Power Products, we’re developing breakthrough technology to power the world’s future innovations as well. Put your talent to work with us – change the world, love your job!\n\nWhy Multiphase Processor Power (MPP):\n\nBig Data, Artificial Intelligence, and data centers are just a few of the trends driving the need for high-current multiphase switching power in the Enterprise market. The Multiphase Processor Power product line is focused on bringing to market the multiphase controllers and Smart Power Stage (driver plus power FETs with integrated sensing) solutions for enterprise computing and other ASICs that are power hungry and require very high currents (can be 1000A+).  The MPP team actively collaborates with TI’s advanced technology, packaging and research and development teams to deliver the highest power density solutions for the power level.  \n\nAbout the job\n\n At TI, Test Engineers leverage strong technical knowledge working hands-on to bring differentiated power solutions to our customers globally. Test Engineers also partner closely with Design, Test, Systems and Application engineers to ensure our power solutions are both meeting customer and market requirements and are cost-wise optimized. The MPP product line is working on complex multiphase buck controllers and the world’s breakthrough technology to develop the high-power density power stages. \n\nAbout the role and team:\n\nWork with the design team to understand design specifications and system challenges\n\nGenerate test plan, create test and char program, design ATE hardware interface boards\n\nDebug characterizing silicon on ATE, and correlate results with bench data\n\nAnalyze silicon results, supporting failure analysis tasks\n\nPerform statistical analysis of yield fallout, debug and fix yield issues; optimize test time\n\nWork with the production team to release products to volume production\n\nTest strategy definition and implementation for multiphase controller and power stage devices\n\nSilicon qualification, including the qual program development\n\nComprehensive device debugging, design validation, and failure analysis\n\nDrive for robust and cost-effective test solutions while being accountable for product quality\n\nWork with the design and Firmware team to support customer needs, implement custom features in FW. Close collaboration with FW and validation teams to understand the device issues and bugs and find the FW level workaround for the fix.\n\nEngaging with customers with application engineers, to help them understand the device better, help to fix the issues, and provide modifications if any tweaks are needed. This is done in collaboration with Application engineers.\n\nQualifications\nMinimum requirements:\n\nBachelor’s degree in Electrical Engineering or related field of study\n\n5+ years of relevant experience\n\nPreferred qualifications:\n\nExperience: Greater than 5 years \n\nStrong fundamentals in electronics: RC networks, operational amplifiers, ADCs, DACs, DC-DC buck converters \n\nExperience to define the test flow, test list and plan to create a test-architecture strategy. \n\nExperience in silicon bring-up and debug, and characterization on the Eagle tester platform \n\nExpertise in schematic design for Hardware/Device Interface Board (HIB/DIB) \n\nExperience in writing test plan and designing test cases \n\nShould be able to lead a project from planning to production release\n\nDemonstrated strong analytical and problem-solving skills\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nStrong time management skills that enable on-time project delivery\n\nDemonstrated ability to build strong, influential relationships\n\nAbility to work effectively in a fast-paced and rapidly changing environment\n\nAbility to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.", "jd_status": "stored"}, {"title": "Validation/Characterization Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-04-01", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009835", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\nValidation engineers are said to have a 'break-the-part' mentality. This means they spend some of their time working to identify the use-cases in which the device will stop working as intended and understand the impact and cause of those failures. Sometimes, those are acceptable failures, but others we may need to mitigate for quality, safety, or other reasons. Plus, we want to ensure that our parts are consistently performing to the specifications that we set in our data sheet, and even to some more conservative limits or as defined in the VVCM (validation/verification compliance matrix). To do this, they must design PCB boards and develop automation software that will increase coverage and reduce data collection time. Validation engineers will also design, develop, and implement necessary methods of measuring device performance and troubleshooting any related systems, equipment or device issues that arise. Validation engineers are often working in a post-silicon lab or on the software programs required to run their measurements.\n\nWhy Multiphase Processor Power (MPP):\n\nBig Data, Artificial Intelligence, and Autonomous Driving are just a few of the trends driving the need for high current multiphase switching power in the Enterprise, Data Center, Communications and Automotive markets.  The Multiphase Processor Power product line is focused on bringing to market driverless multiphase controllers and Smart Power Stage (driver plus power FETs with integrated sensing) solutions to attach to enterprise computing and other ASICs that require currents from 100A to greater than 1000A.  The MPP team actively collaborates with TI’s advanced technology, packaging and research and development teams to deliver the highest power density solutions for the power level.  \n\nAbout the job\nAt TI, Validation Engineers leverage strong technical knowledge working hands-on to bring differentiated power solutions to our customers globally. Validation Engineers also partner closely with Design, Test, Systems and Application engineers to ensure our power solutions are both meeting customer and market requirements and are technically and cost-wise optimized. The MPP product line is working on complex multiphase buck controllers and the world’s breakthrough technology to develop high-power density power stages. The validation engineer in MPP has to evaluate the system-level performace also for enterprise computing.\n\nAbout the role and team:\n\nDevelop validation board, schematics and layout, matching it with customer use-case & applications. The validation boards include - modularization of the Val board for generic flow, solving mixed-signal challenges, scalability of HW for a large number of setups and most importantly closeness to the customer EVMs. \n\nBuild, design, and document the full validation plan. The validation plan needs a detailed understanding of not only the device but also the system environment.\n\nDefine the Validation Strategy in terms of Hardware, Software and Instrumentation\n\nBuilding Validation test cases and implementing them on different scripting languages. (i.e. Python, Test stand, lab view etc)\n\nDefine, build the automation strategies and implement them through methodology, circuit, script and hardware innovations.   \n\nBring the device on the bench; Perform system level and parametric test on the bench with a strong break-the-part mentality.\n\nWork with design and Firmware team to support customer needs, and implement custom features in FW. Close collaboration with FW and application teams to understand the device issues and bugs and find the FW-level workaround for the fix.\n\nDebug device and setup-related issues and drive the issue to closure independently\n\nEngaging on customer issues and fixes with application engineers, to help them understand the device better, help to fix the issues and provide modifications if any tweaks are needed. This is done in collaboration with Application engineers.\n\nQualifications\nMinimum requirements:\n\nBachelor’s degree in Electrical Engineering or related field of study\n\n5+ years of relevant experience\n\nPreferred qualifications:\n\nExperience in validation engineering of analog products\n\nDemonstrates hardware debugging skills, schematic and PCB layout design.\n\nExcellent time management; Strong written and verbal communication skills\n\nExperience in simulating and designing inverters and/or DCDC converters\n\nKnowledge of semiconductor power switches like MOSFET, IGBT, and SiC MOSFET\n\nExpertise in tools e.g. Simplis, Matlab, Altium, PSPICE. \n\nProficient in different scripting languages. (i.e. Python, Test stand, lab view etc)\n\nSchematic generation and layout performed in Altium\n\nPhysical layout management, signal grounding and routing tradeoffs, optimization\n\nMust budget time, manage schedule and complete complex design tasks on time\n\nMust have depth of experience and meticulous approach to ensure high-quality results\n\nMust account for limitations of system-level specifications, testability, and debug\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nMust work well with colleagues and customers to foster a highly creative, interesting, productive, and fun working environment\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Senior Engineer, Product Eval", "company": "Analog Devices", "location": "India, Bangalore, Nova", "date_posted": "2026-04-01", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-Nova/Senior-Engineer--Product-Eval_R261709", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).\n          \nJob profile: Senior, Design Evaluation Engineering\nThis technical lead role will lead the Bench Eval (Validation) activities on any new product development of ASIC and SOC products developed in the newly formed Digital ASIC Business Unit of Analog Devices.  The role will work with the Bench Eval team that drive the post-silicon phase of the product development from first silicon bring-up to validation across PVT.  The ideal candidate will be technically strong and will have the experience in validation aspects for both Digital & Mixed Signal Products, working with cross functional teams like Design, Product & Test..etc with ability to collaborate with ADI global teams.\n\nResponsibilities:\nDesign of innovative, reliable and efficient bench hardware and software solutions for digitally complex SoCs.\nPlay a key role in DFT definition & development, through direct involvement with the Design team early in the New Product Development, to improve debug and testability.\nExecution of the Eval development phase of projects including silicon functionality, characterization, debug, by closely working with the Test teams to come-up with an overall silicon characterization/measurement plan.\nTechnically guide and participate in hiring Eval team members needed for the new product development.\n\nQualifications:\nHave a degree in Electrical/Electronic Engineering\nHave 6-7 years of hands-on experience in high-speed digital validation of MCUs like ARM cortex, DSPs & NPUs\nHave experience in characterization of high-speed interfaces like DDR3, PCIe, USB, HDMI..etc\nHave experience in validating protocols like I²C, I³C, SPI and similar serial interfaces\nHave experience in running performance benchmarks at system level for power & speed for MCUs, DSPs & NPUs\nHave experience in schematic design and layout review for evaluation boards.\nHave experience in validating and characterizing mixed-signal analog blocks.\nHave ability to interact with the Applications team and carve out system level usecase scenarios for bench validation\nHave knowledge of the bench software development and working knowledge of IAR, Keil and other tool chains\nHave good analytical & statistical skills and knowledge of python programming\nBe well versed with the usage of bench equipment such as Oscilloscope, VI meter, Signal generator and analyzers\nBe capable of working with the test engineers/test team to plan out the overall product characterization between Eval & Test\nBe self-motivated, and willing to accept responsibility\nHave the ability to mentor and train the junior engineers as required\nPossess strong interpersonal communication skills and be a team player\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Analog IC Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-03-31", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009925", "is_hardware": true, "platform": "oracle", "jd_text": "About Ultra-Wide-Band (UWB):\n\nUltra-Wide-Band (UWB) is an emerging high growth Connectivity technology. Short pulses <3-4ns is used to communicate between a Key Fob and a Car for secure ranging. The short nature of the pulse along with very low duty cycle and advanced data encryption makes it a secure communication approach. Radio operates around microwave frequency band of 7-10GHz and uses 500MHz bandwidth. UWB technology is growing exponentially with Cell Phone Manufacturers such as Apple and Samsung integrating it in the phone and Car OEM’s such as BMW, BYD, Tesla et al integrating UWB based anchors inside car. Besides communication, UWB is perfect for sensing/radar applications. For example, in child safety where UWB based Radar can detect periodic muscle movement such as breathing or general human presence. UWB Radar can also detect various movements around the Car such as kick to open the trunk, an intruder or an occupied seat.\n\nAbout RF Transceiver Group in Connectivity:\n\n Texas Instruments RF Connectivity group is expanding their RF Transceiver Design group. This group develops cutting edge RF Transceiver products (+MCU integrated) for Wireless-LAN (WIFI) and Ultra-Wideband Systems (UWB). The candidate will join in the UWB Design group. Candidate gets to experience Block Architecture Phase, Concept Design and take the design through the various design phases such as Schematic, Layout, Extracted simulations and Test and Verification. The role is primarily in Analog/RF class of circuit design to meet the overall System & Product requirements. The typical blocks include RF blocks such as LNA, TA, Down-conversion Mixers, Base-band filters, High Speed ADC to send data to the Modem. Reverse Chain namely for Transmitter, starting from DAC, Base-band filter, Up-conversion mixer and Power Amplifier stages to drive the TX Pin. LO system design including Chrystal Oscillator, integer/fractional PLL and LO Distribution systems. Various Calibration modules (AGC, PDET, Gain, Offset, IQMM, etc) to calibrate the Transceiver chain is part of the design. Low Current Mode and Complex Power Management to operate at low LDO input voltage etc. The Design Engineer in RF Connectivity gets introduced to a Holistic view of the product including, Radio Silicon Design, Packaging and PCB and solution design.\n\nAbout the Role:\n\nWe are hiring one lead level IC Design Engineer with demonstrated design cycle experience. Some of the possible roles are:\n\nPLL & Clock System Design\n\nIF filter and VGA Design\n\nTransmitter Design\n\nCandidate should have gone through 1 complete design cycle of an RF transceiver: namely Architecture, Schematic Design, Layout Design, Tape Out, Test & Validation and identifying design fixes for subsequent Tape Out.\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in Electrical Engineering\n\n5 years of relevant experience\n\nCandidate should have gone through 1 complete design cycle of an RF transceiver: namely Architecture, Schematic Design, Layout Design, Tape Out, Test & Validation and identifying design fixes for subsequent Tape Out.\n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Analog IC Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-03-31", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009927", "is_hardware": true, "platform": "oracle", "jd_text": "About RF Transceiver Group in Connectivity:\n\n Texas Instruments RF Connectivity group is expanding their RF Transceiver Design group. This group develops cutting edge RF Transceiver products (+MCU integrated) for Wireless-LAN (WIFI) and Ultra-Wideband Systems (UWB). The candidate will join in the UWB Design group. Candidate gets to experience Block Architecture Phase, Concept Design and take the design through the various design phases such as Schematic, Layout, Extracted simulations and Test and Verification. The role is primarily in Analog/RF class of circuit design to meet the overall System & Product requirements. The typical blocks include RF blocks such as LNA, TA, Down-conversion Mixers, Base-band filters, High Speed ADC to send data to the Modem. Reverse Chain namely for Transmitter, starting from DAC, Base-band filter, Up-conversion mixer and Power Amplifier stages to drive the TX Pin. LO system design including Chrystal Oscillator, integer/fractional PLL and LO Distribution systems. Various Calibration modules (AGC, PDET, Gain, Offset, IQMM, etc) to calibrate the Transceiver chain is part of the design. Low Current Mode and Complex Power Management to operate at low LDO input voltage etc. The Design Engineer in RF Connectivity gets introduced to a Holistic view of the product including, Radio Silicon Design, Packaging and PCB and solution design.\n\nAbout the Role:\n\nWe are hiring one lead level IC Design Engineer with demonstrated design cycle experience. Some of the possible roles are:\n\nPLL & Clock System Design\n\nIF filter and VGA Design\n\nTransmitter Design\n\nADC Design\n\nCandidate should have gone through 1 complete design cycle of an RF transceiver: namely Architecture, Schematic Design, Layout Design, Tape Out, Test & Validation and identifying design fixes for subsequent Tape Out.\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in Electrical Engineering\n\n5 years of relevant experience\n\nCandidate should have gone through 1 complete design cycle of an RF transceiver: namely Architecture, Schematic Design, Layout Design, Tape Out, Test & Validation and identifying design fixes for subsequent Tape Out.\n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Analog IC Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-03-31", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009928", "is_hardware": true, "platform": "oracle", "jd_text": "About RF Transceiver Group in Connectivity:\n\n Texas Instruments RF Connectivity group is expanding their RF Transceiver Design group. This group develops cutting edge RF Transceiver products (+MCU integrated) for Wireless-LAN (WIFI) and Ultra-Wideband Systems (UWB). The candidate will join in the UWB Design group. Candidate gets to experience Block Architecture Phase, Concept Design and take the design through the various design phases such as Schematic, Layout, Extracted simulations and Test and Verification. The role is primarily in Analog/RF class of circuit design to meet the overall System & Product requirements. The typical blocks include RF blocks such as LNA, TA, Down-conversion Mixers, Base-band filters, High Speed ADC to send data to the Modem. Reverse Chain namely for Transmitter, starting from DAC, Base-band filter, Up-conversion mixer and Power Amplifier stages to drive the TX Pin. LO system design including Chrystal Oscillator, integer/fractional PLL and LO Distribution systems. Various Calibration modules (AGC, PDET, Gain, Offset, IQMM, etc) to calibrate the Transceiver chain is part of the design. Low Current Mode and Complex Power Management to operate at low LDO input voltage etc. The Design Engineer in RF Connectivity gets introduced to a Holistic view of the product including, Radio Silicon Design, Packaging and PCB and solution design.\n\nAbout the Role:\n\nWe are hiring one lead level IC Design Engineer with demonstrated design cycle experience. Some of the possible roles are:\n\nPLL & Clock System Design\n\nIF filter and VGA Design\n\nTransmitter Design\n\nADC Design\n\nCandidate should have gone through 1 complete design cycle of an RF transceiver: namely Architecture, Schematic Design, Layout Design, Tape Out, Test & Validation and identifying design fixes for subsequent Tape Out.\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in Electrical Engineering\n\n2 years of relevant experience\n\nCandidate should have gone through 1 complete design cycle of an RF transceiver: namely Architecture, Schematic Design, Layout Design, Tape Out, Test & Validation and identifying design fixes for subsequent Tape Out.\n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Analog Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-03-31", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009929", "is_hardware": true, "platform": "oracle", "jd_text": "About RF Transceiver Group in Connectivity:\n\n Texas Instruments RF Connectivity group is expanding their RF Transceiver Design group. This group develops cutting edge RF Transceiver products (+MCU integrated) for Wireless-LAN (WIFI) and Ultra-Wideband Systems (UWB). The candidate will join in the UWB Design group. Candidate gets to experience Block Architecture Phase, Concept Design and take the design through the various design phases such as Schematic, Layout, Extracted simulations and Test and Verification. The role is primarily in Analog/RF class of circuit design to meet the overall System & Product requirements. The typical blocks include RF blocks such as LNA, TA, Down-conversion Mixers, Base-band filters, High Speed ADC to send data to the Modem. Reverse Chain namely for Transmitter, starting from DAC, Base-band filter, Up-conversion mixer and Power Amplifier stages to drive the TX Pin. LO system design including Chrystal Oscillator, integer/fractional PLL and LO Distribution systems. Various Calibration modules (AGC, PDET, Gain, Offset, IQMM, etc) to calibrate the Transceiver chain is part of the design. Low Current Mode and Complex Power Management to operate at low LDO input voltage etc. The Design Engineer in RF Connectivity gets introduced to a Holistic view of the product including, Radio Silicon Design, Packaging and PCB and solution design.\n\nAbout the Role:\n\nWe are hiring one lead level IC Design Engineer with demonstrated design cycle experience. Some of the possible roles are:\n\nPLL & Clock System Design\n\nIF filter and VGA Design\n\nTransmitter Design\n\nADC Design\n\nCandidate should have gone through 1 complete design cycle of an RF transceiver: namely Architecture, Schematic Design, Layout Design, Tape Out, Test & Validation and identifying design fixes for subsequent Tape Out.", "jd_status": "source_unavailable"}, {"title": "Senior Staff Design Verification Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-03-30T10:16:09.218000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000117608837-senior-staff-design-verification-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Principal Accountabilities: (the 6-8 main areas of responsibility)\n· Develop verification plan based on chip specifications.\n· Setting up of Digital Verification flow for Full Chip, from scratch and ensure Spec Compliance.\n· Design and develop verification systems, decomposition and hardware/software partitioning with focus on reuse and scalability\n· Design of optimized digital blocks/verification components meeting functional, cost and low power constraints and ensure spec compliance.\n· Develop TCL scripts and design constraints to perform synthesis, DFT insertion and static timing analysis.\n· Support DFT strategy and implementation.\n· Verification planning, feature extraction and verification test case development.\n· Interface with P & R for digital hand-off and post layout verification.\n· Develop test vectors for production test.\n· Perform physical silicon device evaluation where necessary.\n· Produce high quality documentation for own blocks.\n· Develop work-around solutions where necessary to overcome device errata including documentation.\n· Mentor and train digital verification engineers\n· All other tasks as deemed reasonable by your manager some of which will be set during annual performance review.\n\n10+ Years of experience in Digital Verification and UVM.\n· Experience in Logic design /micro-architecture / RTL coding.\n· Must have hands on experience with Power product design, synthesis and timing analysis for complex Analog Circuits.\n· Experience in Verilog/System-Verilog is a must.\n· Knowledge of verification methodologies, platforms and techniques, i.e. Functional Verification, ABV, Formal Verification, regression frameworks, UVM, FPGA is required.\n· Experience working in semiconductor ideally PMIC or Audio with focus on mixed signal integrated circuits\n· Hands on experience developing block and top-level timing constraints for STA and P & R sign off\n· Knowledge of scan insertion and ATPG generation\n· Understanding of design constraints and synthesis scripts\n· Work independently on straightforward tasks, with little direction from manager\n· Ability to propose innovative solutions\n· Results-oriented and able to deliver on-time under a tight schedule\n· Cross cultural awareness and sensitivity\n· Proactive attitude about own role and contribution to company goals\n· Ability to work both independently and part of a team\n· Flexible to undertake occasional international travel at short notice\n· Excellent command of verbal and written\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nWe have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning.", "jd_status": "stored"}, {"title": "Lead SOC DFT Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-03-30", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009875", "is_hardware": true, "platform": "oracle", "jd_text": "Define testability. Deliver quality.\n\nWe are looking for a Senior SoC DFT Engineer with 4-5 years of experience to join our Connectivity team within the Embedded Processing Division. You will be responsible for implementing and validating DFT strategies throughout the product development cycle, ensuring the testability and quality of our semiconductor designs. You'll work alongside a team of enthusiastic DFT engineers, apply your expertise and deliver robust and reliable products.\n\nQualifications\nRequirements:\n\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.\n\nAround 4-5 years of experience in DFT, with focus on digital and mixed signal designs.\n\nStrong proficiency in DFT tools like Cadence Modus, Genus, etc.\n\nExperience with ATPG, scan insertion and test pattern generation for high complexity designs.\n\nHands-on experience with DFT-related EDA tools and methodologies, including scan compression, boundary scan, memory BIST, JTAG, etc.\n\nFamiliarity with silicon bring-up and post-silicon debug is desirable.\n\nStrong knowledge of DFT techniques, methodologies, and industry standards, such as IEEE 1149.1.\n\nExperience in scripting languages, such as Perl or Python, for automation and data analysis is desirable.\n\nStrong analytical and problem-solving skills, with the ability to identify and address DFT-related issues and challenges.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Analog Validation Manager", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-03-30", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009894", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\nTexas Instruments is seeking a Digital Design Manager. In this role, you will direct and guide the activities of a research or technical design function responsible for designing, developing, modifying and evaluating digital electronic parts, components or integrated circuitry for electronic equipment and other hardware systems. You may also evaluate final results of research and development projects to assure accomplishment of technical objectives. In addition, job functions include preparing and presenting reports outlining the outcome of technical projects and making recommendations for actions necessary to achieve desired results. As a Digital Design Manager, you may also select, develop, and evaluate personnel to ensure the efficient operation of the function.\n\nQualifications\nPosition Overview\n\n • Lead analog validation engineering team and drive validation strategies for TI's cutting-edge wireless connectivity products\n\n • Combine deep technical expertise with people management responsibilities\n\n • Oversee validation of complex RF and analog systems on advanced technology nodes\n\nMinimum Requirements:\n\n • Bachelor's degree in Electrical/Electronics Engineering (Master's preferred)\n\n • 5+ years of relevant experience in analog/RF validation engineering\n\n • 2+ years of people management or team leadership experience\n\n • Proven track record of leading complex validation projects from concept to completion\n\nWhat You Will Gain from This Role:\n\n • Lead validation initiatives for wireless connectivity products on TI's latest technology node T28\n\n • Strategic exposure to worldwide connectivity teams including Architecture, Business, Systems Engineering, RF/Analog Design, Si Validation, and PTE\n\n • Opportunity to shape validation methodologies and mentor the next generation of validation engineers\n\n • Experience managing cross-functional teams and driving organizational excellence\n\n • Influence product roadmaps and validation strategies across multiple product lines\n\nAbout the Role:\n\n• Define and implement comprehensive validation strategies encompassing Hardware, Software, and Instrumentation across the analog validation portfolio\n\n • Oversee development of RF validation boards, schematics, and layouts, ensuring alignment with customer use-cases and applications\n\n • Drive system-level and parametric testing methodologies with a rigorous \"break-the-part\" approach\n\n • Partner strategically with Analog Design, RF Design, Modem Design, PTE, SoC, and Digital teams\n\n • Lead, mentor, and develop a team of validation engineers, fostering technical growth and career advancement\n\n • Establish team goals, performance metrics, and development plans aligned with business objectives\n\n • Drive hiring decisions and talent acquisition strategies for the validation team\n\n • Create an inclusive, collaborative environment that promotes innovation and excellence\n\n • Manage multiple validation projects simultaneously, ensuring on-time delivery and quality standards\n\n • Establish and optimize validation processes, tools, and methodologies\n\n • Drive continuous improvement initiatives and best practice adoption\n\n • Coordinate with program management and business teams on project planning and resource allocation\n\nPreferred Qualifications:\n\n • Advanced degree in Electrical Engineering or related field\n\n • Extensive experience in validation engineering of analog/RF products, particularly wireless connectivity solutions\n\n • Demonstrated expertise in hardware debugging and failure analysis\n\n • Proficiency in schematic and PCB layout design using Altium/Allegro or similar tools\n\n • Strong background in RF measurements, test automation, and validation instrumentation\n\n • Experience with low-power MCU validation and debugging\n\n • Proven ability to establish and maintain strong relationships with internal and external stakeholders\n\n • Exceptional verbal and written communication skills with ability to present to executive leadership\n\n • Demonstrated capability to quickly adapt to new systems, processes, and technologies\n\n • Strong analytical, problem-solving, and decision-making skills\n\n • Experience working in cross-functional, global teams with diverse stakeholders\n\n • Track record of driving initiatives and delivering results in fast-paced environments\n\n • Excellent time management and organizational skills enabling successful multi-project delivery\n\n • Experience with semiconductor validation tools and industry-standard test equipment\n\nAdditional Desired Skills:\n\n • Knowledge of wireless communication standards (BLE, Wi-Fi, etc.)\n\n • Familiarity with statistical analysis and data-driven validation approaches\n\n • Experience with validation software frameworks and automation tools\n\n • Understanding of semiconductor manufacturing and test processes\n\n • Project management certification (PMP, Agile, etc.) preferred\n\nWhy Join TI:\n\n • Excellent opportunity for a seasoned validation professional to take their career to the next level\n\n • Make significant impact on TI's wireless connectivity product portfolio\n\n • Work with cutting-edge technology and industry-leading teams\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Validation/Characterization Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-03-30", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009857", "is_hardware": true, "platform": "oracle", "jd_text": "Texas Instruments RF Connectivity group is expanding their RF Transceiver Validation Group in Bangalore, India.\n\n This group develops cutting edge RF Transceiver products (+MCU integrated) for Wireless-LAN (WIFI) and Ultra-Wideband Systems (UWB).\n\n The RF Validation group primarily focusses on the following aspects:\n\n Debug of The Transceiver SoC: Fast and Systematic Identification of the issues in the blocks. Observe and identify the root cause. Drive solutions and not just report problems. The debug would involve either Power & Biasing issues, Incorrect register sequence or incorrect values, Board level issues etc.\n\n RF Measurements: Understanding of each RF, IF and DC measurement. Example in Receiver chain, measurement of Noise Figure & Gain of the chain, Linearity measurements such as P1dB, IIP2, IIP3, IQ gain & Phase error, LO Leakage and DC offsets. DC operating point measurement via Test Mode, DC Voltages and Current Consumption. Similar measurements for TX chain, PLL, Reference Clock.\n\nPCB Board Development: Development of PCB Schematic and Layout, PCB material selection, stackup, review the design and implement the changes. Working with 3rd party PCB service companies. Familiarity with Altium and Cadence Allegro flows.\n\nTest Automation and Interpretation of Measurements: Person is expected to have proficiency in Coding & Automation of the measurement flows including interfacing of instruments. Processing of the measured data across PVT corners, Visualization, and ability to identify between IC and setup issues. Basic understanding of statistics and sources\n\nInterfaces: Ability to deign and program interfaces such as SPI, UART, UCI.\n\nQualifications\nMinimum requirements:\n\nMinimum education (ie bachelor's degree in electrical engineering)\n\n2+years of experience with RF validation and debug of RF IPs\n\nUnderstanding of Rf systems and key instruments\n\nThe candidate is expected to have proficiency in 2 or more of the list.\n\n Debug of The Transceiver SoC:\n\n RF Measurements: \n\nRF PCB Board Development:\n\nTest Automation and Interpretation of Measurements: \n\nInterfaces:\n\n A strong team player who is deeply engaged with the Product Development team especially the Radio Design Team.\n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nMinimum expected experience is 2 years. Position is on-site in Bangalore. TI offers attractive compensation and a highly enriching technical environment. Ample opportunities to file Patents and become a Recognized Leader in the respective domain over time.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Analog Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-03-30", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009721", "is_hardware": true, "platform": "oracle", "jd_text": "About TI - Change the world. Love your job. \n\n Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\nAnalog Design Engineer (Lead) for Connectivity Products:\n\nConnectivity SoC’s with Radio & Micro controllers are widely used in Automotive, Industrial and Medical Applications. Some of the examples are BLE based Glucose Monitor patches and Tyre Pressure Monitors; UWB based access control KeyFobs for Cars. We are looking for an Analog Design Lead with complete design cycle experience in Architecture, Design, Schematic, Layout, Verification and SoC Integration and Debug. Some of the Analog / Mixed-signal designs that we are exploring include ADC, DAC, PLL, PGA, Filters, Crystal Oscillators, Temperature sensors, LDO, bandgap reference, DC-DC converters, Comparators etc. You will be part of the Central Analog team of Texas Instruments EP BU that is heading the Analog / Mixed-signal designs to be embedded into the SoC.\n\nIn this role, responsibilities may include:\n\nDesign analog circuits with IP level ownership and responsibility from definition to release to manufacturing\n\nDirect, guide and participate in activities of a research or technical design function responsible for designing, developing, modifying and evaluating electronic parts, components, integrated circuits for a variety of applications\n\nMake assignments for team members, providing design guidance as needed, developing schedules and monitoring progress throughout the project\n\nEvaluate intermediate and final results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout\n\nCollaborate with Design Verification teams during the pre-PG phase of a project to ensure completion of all technical tasks before PG\n\nWork with systems engineers, application engineers and marketing to prepare product briefs, datasheets, application notes and assisting in the definition of the product to meet customer needs as well as contributing to roadmap formulation and new concept creation\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nInterface and lead discussions with the customer and/or TI field sales/field applications teams to understand customer designs, problems and support as required\n\nActively participate in hiring, developing and evaluating personnel to ensure efficient operation of the organization and growth of the individuals into leader\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in Electrical Engineering\n\n2-5 years of relevant experience\n\nPreferred qualifications:\n\nAbility to take on challenging problems in analog/mixed-signal development for SoC and drive development of innovative solutions\n\nAbility to take the initiative and drive for results\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Lead STA Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-03-30", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009879", "is_hardware": true, "platform": "oracle", "jd_text": "Senior STA and Synthesis Engineer / STA Lead - Texas Instruments\nAbout the Role: Join Texas Instruments' Connectivity engineering team as a Senior STA and Synthesis Engineer / STA Lead, where you'll play a critical role in delivering high-performance wireless connectivity solutions that power next-generation IoT, automotive, and industrial applications.\nWhat You'll Do: Drive timing closure and synthesis optimization for advanced connectivity SoCs, ensuring our wireless solutions meet stringent performance, power, and area requirements across diverse market applications.\nTechnical Focus:\nMulti-Technology Expertise: Work on synthesis and timing analysis across various wireless connectivity standards and protocols\nFull Flow Ownership: Drive synthesis, timing analysis, and optimization from RTL to layout handoff\nPerformance Leadership: Ensure timing closure for complex mixed-signal connectivity designs\n \nKey Responsibilities:\nPerform static timing analysis and synthesis for connectivity SoCs\nCollaborate with design teams to optimize RTL for timing, power, and area\nWrite SDC constraints across functional and DFT modes and validate the constraints through industry standard constraints checker tools\nDrive timing closure through physical design flow coordination\nDevelop and maintain synthesis and STA methodologies and scripts\n \nGrowth Opportunities:\nWork on both established connectivity platforms and breakthrough wireless technologies\nContribute to multiple tape-outs annually across different process nodes\nInfluence next-generation connectivity architecture decisions\nMentorship opportunities with junior engineers and cross-functional collaboration\n \nWhy This Role:\nDirect impact on TI's wireless connectivity portfolio performance\nExposure to diverse wireless standards and emerging technologies\nOpportunity to work with state-of-the-art EDA tools and methodologies\nBe part of innovation initiatives including new wireless technologies for TI\n \nTechnical Environment:\nMultiple process technology nodes and design rule sets\nComplex mixed-signal connectivity SoC designs\nAutomated flow development and optimization\n \nReady to Drive Connectivity Performance? Join our team and help optimize the wireless technologies that connect our world.", "jd_status": "source_unavailable"}, {"title": "Validation Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-03-30", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009893", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n In this position, you will be working on high-speed mixed-signal communication circuits using state-of-the art process technology, as well as be involved in the design of high performance digital circuits interfacing to leading edge analog circuitry as part of an overall system.\n\n Your responsibilities will include RTL coding, simulation, synthesis, timing closure, verification, evaluation, debugging of high-speed communication chips both at the circuit level and behavioral level.\n\n As a design engineer, you will prepare test methods and specifications, assist in preparation of application information, data sheets and demo boards. You will develop solutions to complex problems through assessment of various techniques and approaches. You will plan and organize work to ensure timely completion of many independent tasks with general instructions on routine tasks and with detailed instructions on new assignments.\n\n This position involves routine communication with a highly talented team of analog and digital design engineers to solve problems and present information as well as active participation in work groups, providing ideas and collaborative teamwork.", "jd_status": "source_unavailable"}, {"title": "DFT Design Engineer", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-03-27T10:45:00+00:00", "url": "https://global-external-amd.icims.com/jobs/80645/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. SENIOR SILICON DESIGN ENGINEER THE ROLE: AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. THE PERSON: As a DFx Silicon Design Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team! KEY RESPONSIBILITIES: Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications. Perform DFT RTL design integration, insertion, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS, ATPG and Scan GLS. Work with multi-functional teams and handling schedules Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design. Performing scan insertion, ATPG verification and test pattern generation Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis. PREFERRED EXPERIENCE: Knowledge of DFT techniques such as JTAG/IEEE standards, SSN, Scan and ATPG, memory BIST/repair or Logic BIST Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential. Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl) Familiar with Verilog design language, Verilog simulator and waveform debugging tools Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus. Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc. is a plus Strong problem-solving skills. Team player with strong communication skills. ACADEMIC CREDENTIALS: Bachelor’s or Master’s degree in electrical/Electronic Engineering with 5+Yrs #LI-SR4 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Staff Engineer – Validation & Characterization (DDR5)", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-03-27T06:40:44.531000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000117213777-staff-engineer-validation-characterization-ddr5-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "This position is for a hands-on validation and characterization engineer with solid experience across multiple product iterations. The ideal candidate has strong expertise in DDR5/high-speed memory interfaces and is comfortable working at the bench as well as collaborating closely with design and global validation teams. Experience with buffer chips and server/enterprise memory applications is highly desirable\nComponent Bench Characterization\nPerform detailed bench characterization of high-speed memory devices using best-known measurement techniques and test methodologies.\nApply de-embedding, high-impedance probing, noise mitigation, and signal integrity best practices to resolve complex measurement challenges at increasing data rates.\nSupport Design and Validation teams in the characterization of key electrical and performance parameters.\nWork collaboratively with Designers and other cross functional teams to debug and optimize performance using open-ended tests not solely driven by specifications.\nValidation Infrastructure Development\nDevelop new test infrastructure to support effective characterization and validation of high-speed memory interfaces.\nDesign and implement custom test procedures, scripts, and automation to improve test coverage and efficiency.\nIdentify cycle-time and cost improvements, including automation, to improve validation efficiency.\nData Analysis and Reporting\nSynthesize results and identify the next set of relevant experiments to fully understand issues.\nGenerate consistent, well-written, and easily understandable reports and presentations tailored to different audiences.\nDevelop and validate creative uses of LLM/AI techniques to analyze large validation datasets, generate effective visualizations, and reduce cycle time to final reports.\nTechnical Communication\nEffectively document test methodologies and procedures to ensure reproducible and accurate results.\nExplain complex topics at an appropriate level of detail for each stakeholder.\nWork effectively with Validation Engineers across diverse regions, languages, and technical backgrounds.\n\nRequired Qualifications:\nBachelor's / Master’s degree in Electrical Engineering, Computer Engineering, or a related field.\n6+ years of hands-on experience in characterizing high-speed interfaces, particularly memory-related applications.\nStrong understanding of memory interface architecture and operation, preferably DDR5.\nIn-depth knowledge of memory interface protocols and standards (e.g., JEDEC specifications).\nExpertise in using typical high speed interface test equipment (BERT, Scope, Compliance S/W).\nProficiency in scripting languages (e.g., Python, Perl) for test automation and analysis.\nExcellent analytical and problem-solving skills.\nStrong communication and interpersonal skills.\n\nPreferred Qualifications:\nMaster's degree in Electrical Engineering or a related field.\nExperience with advanced signal integrity measurements and applications for Design correlation.\nExperience with modern software tools for data visualization, analysis, and reporting; in particular dynamic interactive tools – including LLMs\n\n \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nWe have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning.", "jd_status": "stored"}, {"title": "Staff System Validation Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-03-27", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2504590", "is_hardware": true, "platform": "oracle", "jd_text": "Staff Post-Silicon System Validation Engineer\n\nPosition Summary\n\nThe Staff Post-Silicon System Validation Engineer is responsible for defining and executing system-level validation strategies for Power Management Devices (PMD), ensuring robust product performance and quality from first silicon through production release. This individual contributor role requires deep expertise in semiconductor validation, power electronics, automation, characterization, and silicon debug.", "jd_status": "source_unavailable"}, {"title": "Lead Engineer Senior - Performance Modeling", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-03-26T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446715941404", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Systems Engineering\nGeneral Summary:\nQualcomm is the world's leading developer of next-generation of always connected Edge-AI processing technology and is committed to building a world-class organization that will lead the industry.\n\nBe part of the team developing next generation Audio and Always On / Edge AI subsystems and platforms.  The ASIC Audio/Edge AI Systems Engineer is responsible for system architecture definition activities supporting a sophisticated multimedia Low Power Audio/Edge AI subsystem across a broad range of mobile, XR, compute, and automotive products.\n\nCandidates will be responsible for all aspects of the ASIC hardware architecture definition/validation including the following:\nOwning end to end system architecture\nCapturing detailed technology requirements working closely with product, hardware and software engineering teams\nDeveloping detailed ASIC system architectures to support requirements and authoring subsystem hardware specifications\nDefining architecture validation plans and reviewing development results\nOptimization and debug via modelling, system simulation and testing across key criteria including power and performance.\nCollaborating, reviewing and enabling design and system teams to execute on dependent specifications\nPost-silicon commercialization support and customer engineering documentation\nDefining and patenting novel architectures that drive industry leadership.\n\nJob Function:\nOversees hardware architecture for ASIC systems development for a variety of products.\nDetermines architecture design, and validation via system simulation.\nDefines module interfaces/formats for simulation.\nEvaluates all aspects of the HW architecture flow from high-level development to validation and review.\nAnalyzes equipment to establish operation data, conducts experimental tests, and evaluates results.\nUses System tools, such as, MathWorks MATLAB, SIMULINK, VISIO and other toolboxes.\nUses language such as HDL, C/C++, System C, Perl, Python.\nProvides technical expertise for next generation initiatives.\n\nMinimum Qualifications:\nBachelor's degree in Science, Engineering, or related field and 10+ years of ASIC design, verification, or related work experience.\nOR\nMaster's degree in Science, Engineering, or related field and  8+ years of ASIC design, verification, or related work experience.\nOR\nPhD in Science, Engineering, or related field.\n\nPrincipal Duties and Responsibilities:\nLeverages experience in DSP, machine learning algorithms, SoC hardware and computer architecture concepts to develop proposals to address system audio and edge-AI requirements using processor, memory, bus and low-power design techniques.\nUses expertise in low-power design methodology, optimization and validation using various CAD tools and design techniques to optimize system power.\nLeverages experience in digital system performance analysis and systems modelling to ensure performance goals met.\nLeverages Verilog/VHDL and digital hardware design tools such as Synopsys/Cadence/Mentor ASIC design and simulation tool sets, power analysis and simulation, scripting languages (Python, Perl, TCL, C, etc.) to optimize system.\nEffectively utilizes advanced problem solving and ASIC engineering practices to resolve complex architecture, design, or verification problems.\nWrites technical documentation and provides technical expertise for design or project reviews and project meetings.\nActs as a tech lead on small to large projects and owns team deliverables of the project.\n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience.\n                                                                    OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.\n                                                                    OR\nPhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RTL Design -Staff/Sr Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-03-25T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446717655197", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nPreferred Qualifications:\n\n•    Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. \n•    12+ years of Hardware Engineering or related work experience.\n•    3+ years of experience with circuit/logic design/validation (e.g., digital, analog, RF).\n•    3+ years of experience utilizing schematic capture and circuit stimulation software.\n•    3+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.\n•    1+ year in a technical leadership role with or without direct reports.\n\nPrincipal Duties and Responsibilities:\n•    Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test highly critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.\n•    Participates in or leads the implementation of advanced design rules and processes for electronic hardware, equipment, and/or integrated circuitry.\n•    Conducts highly complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.\n•    Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.\n•    Evaluates, characterizes, and develops novel manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules.\n•    Evaluates reliability of highly critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity.\n•    Advises and leads engineers in the development of complex hardware designs, evaluating various design features to identify potential flaws or issues.\n•    Writes detailed technical documentation for highly complex Hardware projects; reviews technical documentation for junior engineers.\n\nLevel of Responsibility:\n•    Works independently with minimal supervision.\n•    Provides supervision/guidance to other team members.\n•    Decision-making is significant in nature and affects work beyond immediate work group.\n•    Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. \n•    Has a moderate amount of influence over key organizational decisions.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff - Pre-Silicon System Performance", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-03-25T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446715656563", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Systems Engineering\nGeneral Summary:\nThe Senior Staff Engineer in the Server SoC Performance Team is a technical leader responsible for owning end-to-end system performance strategy, methodology, and sign-off for complex server-class SoCs. This role drives architecture-level performance insights and influences product and architecture decisions.\n\nKey Responsibilities\n- Own system-level performance sign-off across multiple subsystems and use cases.\n- Define and drive performance methodology and benchmarks for pre-silicon and early silicon platforms.\n- Lead deep-dive investigations involving CPU, memory, NoC, IO, and power-performance trade-offs.\n- Translate architecture features into quantitative performance projections and risks.\n- Influence architecture and design trade-offs.\n- Mentor engineers and act as a technical authority.\n\nMinimum Qualifications\n- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.\n\n- 10+ years of industry experience in SoC/System performance, architecture, or validation.\n\n- Strong expertise in SoC micro-architecture, memory systems, and interconnects.\n\nPreferred Qualifications\nMaster’s degree or PhD (or equivalent experience).\n\nExtensive experience with RUMI/emulation-based performance sign-off.\n\nPreferred experience in Server-class / Data Center SoC architecture, including cache-coherent interconnects (e.g., CHI/ACE-class fabrics), scalable memory hierarchies, and high-bandwidth IO subsystems (PCIe/CXL-class), with ability to translate architecture features into performance sign-off metrics and system-level debug.\n\nMinimum Qualifications:\n•    Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Systems Engineering or related work experience.\n                                                                    OR\nMaster's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Systems Engineering or related work experience.\n                                                                    OR\nPhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.\n\nLevel of Responsibility\n- Works independently with significant impact on product performance and program success.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior Verification Engineer, PCIE", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-03-25", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer--PCIE_JR2015245", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science.\n\nThe GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nBe responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nExpected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.\n\nYou will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech or equivalent experience\n\n5+ years of relevant experience\n\nExperience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog\n\nExpertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)\n\nExperience in developing and working in functional coverage based constrained random verification environments\n\nBackground in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nExcellent knowledge of PCIE protocol - Gen3 and above\n\nGood understanding of the system level architecture of PCIE/CXL-based designs\n\nPerl, Python or similar scripting and SW programming language experience\n\nGood debugging and analytical skills\n\nGood interpersonal skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior Formal Verification Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-03-25", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Formal-Verification-Engineer_JR2015243", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nAs a Formal Verification Engineer at NVIDIA, you will be responsible for formally verifying complex designs. NVIDIA has developed a strong functional formal verification methodology that not only enables hardware design and verification engineers to use lightweight FV tools and techniques successfully but also allows FV engineers to use advanced property proving techniques on complex and/or critical RTL logic. The job involves very close interaction with the design team, architecture team, with other validation teams, and with NVIDIA's internal FV R&D group that develops functional verification tools using formal verification technology.\n\nWhat you'll be doing:\nYou will help decide on the best applications of formal verification techniques to various parts of the design.\n\nReview functional and micro-architectural specifications, define the scope for formal verification, and create high-quality formal verification testplans to sign-off on the corresponding design implementation.\n\nBuild formal verification testbenches, code assertions and constraints, and apply abstraction techniques to converge the targeted properties or to achieve reasonable proof-depth.\n\nApply formal coverage techniques for analyzing over-constraints and for measuring functional coverage.\n\nDesign and develop functional verification flows that involve both vendor and internally developed formal tools.\n\nWhat we need to see:\nB.Tech./ M.Tech. with 5+ years of relevant experience.\n\nGood understanding of hardware micro-architecture and design.\n\nConversant with formal verification technologies, including complexity reduction techniques.\n\nFormal property verification experience on multiple complex units.\n\nProficiency in creating high quality testplans, building formal testbenches, and root-causing counter-examples.\n\nWays to stand out from the crowd:\nGood debugging and problem solving skills\n\nScripting knowledge (Python/Perl/shell)\n\nGood interpersonal and communication skills and dream to work as a great team member\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.\n\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Sr Principal Product Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-03-24", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Sr-Principal-Product-Engineer_R53758-4", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nCadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.\nAt Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\n\nThe Cadence Advantage\nThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.\nCadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.\nThe unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success\nMultiple avenues of learning and development available for employees to explore as per their specific requirement and interests\nYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.\n\nPosition Description \nCadence is looking for a Product Engineer to join the team behind Perspec, Cadence’s Portable Stimulus solution used by leading semiconductor companies to solve complex SoC and system-level verification.\nFocus: Deploying Portable Stimulus (PSS) in large SoC verification environments and solving complex generation and solver problems in collaboration with semiconductor customers and Cadence R&D.\nChallenges.\nThis role sits at the intersection of verification methodology, system architecture, and EDA product engineering. You will work directly with advanced verification teams at major semiconductor companies to deploy Portable Stimulus (PSS) in real production environments and help drive the evolution of Perspec.\nThe work spans formal languages, simulation, emulation, virtual platforms, firmware-driven verification, and post-silicon reuse, and increasingly involves AI-assisted verification workflows.\nWhat You Will Do\nWork directly with semiconductor design and verification teams to deploy Portable Stimulus methodologies in complex SoC programs.\nHelp debug difficult generation and solver issues involving constraints, resources, execution ordering, and scenario realization.\nInvestigate real-world modeling challenges that arise in large system-level PSS environments.\nCollaborate closely with Cadence R&D to diagnose tool issues, influence new features, and improve PSS standard\nHelp define and refine methodologies for scalable system-level verification.\nDevelop reference models, internal knowledge, and best practices used by both customers and Cadence field teams.\nSupport advanced system-level verification use cases including:\n->software-driven verification\n->device programming flows\n->reuse between simulation, emulation, and post-silicon\n->integration with virtual platforms and firmware environments\nContribute to emerging AI-assisted verification flows built around PSS models.\n\n Required Background\n12+ years of experience in SoC verification, validation, or verification methodology\nStrong hands-on experience with SystemVerilog and UVM or embedded / bare metal environments\nSolid understanding of constrained-random verification and system-level test generation\nExperience debugging complex verification environments\nStrong programming or scripting skills (C/C++/Python or similar)\nAbility to work directly with engineering teams to solve difficult technical problems\n\nHelpful Experience\nExposure to Portable Stimulus (PSS) or interest in learning it\nExperience with Perspec or other PSS tools\nExperience working with complex SoC subsystems and protocols such as PCIe, DDR, networking, or ARM-based SoCs\nExperience with embedded software programming and bare-metal environments\nFamiliarity with emulation, virtual platforms, or post-silicon validation\nExperience developing verification methodology or reusable verification libraries\nWhy This Role Is Interesting\nPortable Stimulus is changing how system-level verification is done.\nIn this role you will work on real verification problems at scale, interacting with some of the most advanced verification teams in the industry and helping shape how hardware/software co-verification is done across simulation, emulation, and silicon.\nIf you enjoy deep technical problem solving, modeling complex systems, and working close to both customers and EDA tool development, this is a unique role.\nPosition Requirements   \nEDUCATION: MS in Electrical/Electronics/Computer Engineering with 12+ year experience or BE/BTech in Electrical/Computer/Electronics Engineering.\nBehavioral skills required:\n\nMust possess strong written, verbal and presentation skills.\nGood communication and interpersonal skills, demonstrate teamwork and collaboration skills.\nAbility to establish a close working relationship with both customer peers and management.\nExplore what’s possible to get the job done, including creative use of unconventional solutions\nWork effectively across functions and geographies\nPush to raise the bar while always operating with integrity\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Applications Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-03-23", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009777", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \n\n Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\n Our business has very high growth in TI and is in a segment where the market is fast growing. We are looking for an application engineer who has the passion and excitement to grow, innovate, take an active role in solving controller & Power stage technical challenges, create novel reference material for various CPU/ASIC power solutions, provide top-notch applications support to customers for various applications, defining next Gen multiphase controller & Power stage for Enterprise Computing/Datacenter market. This is a fast paced, results driven environment that requires broad knowledge, creativity and excellent interpersonal skills on a daily basis. They then collaborate with the full IC development team (design, test, product engineers) to deliver products to the market which are compelling, competitive, cost-conscious, manufacturable, and importantly, successful in growing TI's business\n\nIn this role, you will be part of a strong and fast-moving team with opportunities to:\n\nDesign and build evaluation modules for Multiphase Controller & Power stage\n\nDeeply involvement in the new product development with cutting edge of new Gen CPU/AI server power architecture. \n\nActively participate in hiring, developing and evaluating new hires / interns to develop their leadership skills\n\nCollaborate with design, marketing and product teams to provide high value to customers\n\nProvide technical support to assist customers to design with TI's Multiphase Controller & Power stage Power solutions \n\nWrite technical documents such as Datasheets, Application notes, etc.\n\nContribute to the next generation Multiphase Controller & Power stage specs definition by engaging with leading CPU solution vendors. Assess IC development tradeoff with design team and creating competition benchmarking. \n\nKey responsibilities include:\n\nAnswer customer questions and support design-in activities for released products by: \n\nDebug of customer problems by re-creating issues in our evaluation boards and/or customer boards\n\nOn-site support for customer boards as required\n\nSchematic and Layout Review of customer application\n\nForum and email questions from customers\n\nClosed work with CPU vendors to qualify the parts to PASS various AVL evaluation. \n\nGenerate SIMPLIS or PSPICE Models for the Multiphase Controller & Power stage products\n\nPerform Bench Characterization for new product developments (NPDE), including bench automation, hardware design and develop test techniques, such as\n\nParticipate in new silicon testing from an application perspective to ensure robustness of the product (i.e. destructive testing)\n\nProvide product recommendations, competitive position and analysis for customers\n\nParticipate in datasheet reviews to ensure completeness of datasheets in development by Systems Engineers\n\nDesign EVM and internal evaluation boards to support correlation and evaluation activities of new products\n\nTrain/Maintain the FAE's team knowledge of Multiphase Controller & Power stage in order to provide local timely support.\n\nWrite application notes and training collateral that explain different use cases, implementation and/or flexibility of multi-phase controller & Power Stage products\n\nQualifications\nMinimum requirements \n\n• Masters/PhD degree in Electrical Engineering, ECE \n\n • 1+ years of application/system experience\n\n • Experience in applications support of power products\n\n • Strong technical background, with the ability to produce high quality technical documentation\n\n Preferred qualifications \n\nHands-on experience working on multi-phase controller & Power Stage product and solid understanding of power topology, such as DCAP+\n\nAbility to create schematics using OrCAD or Altium; experience in developing PCB design with parasitic analysis a plus\n\nDemonstrated strong modeling skill\n\nSoftware skills in any major programming language (e.g. Python, C#, LabView, etc.)\n\nMaster’s degree in Electrical Engineering, ECE or related field\n\nDemonstrated strong analytical and problem-solving skills\n\nStrong verbal and written communication skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\n Strong time management skills that enable on-time project delivery\n\n Demonstrated ability to build strong, influential relationships\n\n Ability to take the initiative and drive for results\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "MTS SR, ANALOG; DSGN", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-03-20", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2504944", "is_hardware": true, "platform": "oracle", "jd_text": "Job Description: onsemi is hiring a highly motivated and self-driven senior analog R&D design manager. This is an exciting opportunity that will broaden and enhance one’s skill and challenge the candidate throughout their career.  You will be interfacing with some of the most senior technical experts within the organization solving complex design challenges. This opportunity is for those who are technically focused and thrive on solving complex design challenges and cooperating in global teams to create competitive products and intellectual property for onsemi. \n\n \n\nAs senior analog R&D design manager, your primary role is to set up and manage a small local team of analog R&D design engineers and drive your team to enable the new product development teams with the most competitive solutions for their products. You work with your team on advanced analog and mixed-signal circuit designs to solve complex design problems in support of onsemi’s future product roadmap. Typically, you will work on analog/mixed-signal circuit design challenges which have not yet been successfully addressed or solved before in onsemi but which are critical for onsemi’s product roadmap. Besides hands-on advanced circuit design, your contributions can vary from product and IP definition support towards deep-dive design reviews and design support for complex technical problems.  \n\n \n\nThe successful candidate will have the opportunity to:\n\nWork with product definers, customers, technologists, business unit representatives, circuit designers, application engineers, sales, reliability, and other teams on a global basis to define solutions for the future analog and mixed signal products which meets the cost, performance, manufacturing, timeline and reliability goals.\n\nUnderstand detailed customer requirements and verify latest technologies and architectures meet or exceed all expectations.\n\nCreate and manage a local team (target ~ 5 engineers in 1-2 years) to address the most complex and most urgent mixed-signal circuit design challenges for onsemi’s product roadmap\n\n#L1-LK1\n\nResponsibilities\nProven experience in managing or coaching electrical engineers\n\nProven know-how in mixed-signal design in CMOS and BCD technologies\n\nProven know-how in deep-submicron (<130nm) CMOS and BCD process architectures\n\nGood understanding of CMOS and BCD device physics\n\nProven experience in definition for new products/IP\n\nProven know-how in translating requirements into efficient product/IP architectures\n\nDemonstrated strength in leveraging innovation to provide solutions \n\nStrong communication skills and leadership skills \n\nBusiness- and results oriented in a team environment \n\nEager to work in a highly competitive field and a multicultural environment. \n\nTravel, combination of international and domestic, up to 20% \n\nFluency (written and oral) in English \n\n#L1-LK1\n\nQualifications\nMS degree in Electrical Engineering,  Ph.D. degree is an asset\n\n15+ years’ experience in analog circuit design and semiconductor processes\n\n#L1-LK\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Architect MTS", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-03-20", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2504894", "is_hardware": true, "platform": "oracle", "jd_text": "Senior Principal Engineer, Platform Architect – Digital Compute, Analog & Mixed Signal Products\n\nAbout Us\n\nAt onsemi, we help improve lives through silicon solutions every day. Our intelligent power and sensing technologies solve the world’s most complex challenges and lead the way in creating a safer, cleaner, and smarter world. Our group develops compute subsystems containing MCUs, DSPs, and accelerators, for a large variety of different products and markets.\n\nThe Role\n\nThis role presents an exciting opportunity to define the design architecture and methodologies for a new platform of digital compute and analog/mixed-signal products. As Senior Principal Engineer, you will define the design platform, targeting a large variety of different products. Your responsibilities will include architecture definition, design specification, RTL modeling and performance analysis. Also, you will get to define the design methodologies spanning the entire scope of chip design. You will have a central role within the organization, and you have the opportunity to interact with many product and design teams.\n\nWhy Join Us\n\nWe create a diverse set of world-class products in a friendly and team-oriented atmosphere. We provide an environment of continual learning and growth opportunities and support volunteer & charitable programs. We offer a competitive benefit package and a great place to work to build a career.\n\nWhat You’ll Do\n\nTechnical leadership: Define the architecture and methodology for a new design platform targeting a broad spectrum of products, covering elements of hardware and software\n\nProblem solving: Identify novel solutions when architecting product functionality and/or with design methodologies\n\nTechnical guidance & mentoring: Guide world-wide teams in technical areas, from microarchitecture to productisation\n\nInnovation: Define and create design methodology and design flow improvements for efficiency and robustness", "jd_status": "source_unavailable"}, {"title": "Lead Software Engineer - RTOS Lead", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-03-18", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009764", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\nAbout the Role\n\nTexas Instruments (TI) Jacinto Software Team is seeking an experienced Lead Software Engineer - RTOS Lead to join our innovative team developing embedded software for next-generation System-on-Chip (SoC) devices that power automobiles, factories, robotics, and more worldwide.\n\nAs a technical leader, you will architect, design, and develop embedded programs for Jacinto SoC devices while leading a talented engineering team. You'll have opportunities to present at international conferences, contribute to patents, and shape the future of embedded systems technology.\n\nKey Responsibilities\n\nTechnical Leadership:\n\nLead and mentor a team of 4-5 engineers developing peripheral drivers, bootloaders, and platform software for multiple SoCs\n\nDrive technical architecture and design decisions, influencing system architecture through deep technical expertise\n\nOwn technical components end-to-end, including release planning and delivery\n\nDesign, develop, and optimize complex drivers with CI/CD-based workflows\n\nDebug and enhance existing software systems using JTAG, trace analyzers, and logic analyzers\n\nProject & Quality Management:\n\nServe as Sprint Leader and Release Manager, ensuring code quality standards across the team\n\nManage sprint execution, track tasks, and maintain up-to-date project status\n\nCollaborate with cross-functional leads, PMO, and senior management\n\nHandle multiple projects effectively while meeting delivery commitments\n\nEnsure compliance with ISO 26262 standards and maintain required documentation\n\nInnovation & Process Improvement:\n\nDevelop automation solutions and leverage AI/ML tools to enhance execution efficiency\n\nApply best practices in software development processes and methodologies\n\nPartner with business stakeholders, R&D, and program management to define requirements and effort estimates\n\nAnalyze and resolve complex customer and internal technical issues\n\nProvide training, work sessions, and technical guidance to the global team\n\nQualifications\nMinimum Qualifications\n\nEducation: Bachelor's degree in Computer Science, Electronics, Electrical Engineering, or related field\n\nExperience: 10+ years of embedded software development\n\nTechnical Skills:\n\nExpert proficiency in C programming and embedded systems development\n\nHands-on experience reading and implementing datasheets and specifications\n\nStrong understanding of memory architecture, embedded SoCs, and common IP blocks\n\nIn-depth knowledge of Real-Time Operating Systems (RTOS), particularly FreeRTOS\n\nExperience with large-scale distributed architectures\n\nPreferred Qualifications\n\nTechnical Expertise:\n\nExpert-level proficiency in C, assembly language, and low-level embedded programming\n\nDeep understanding of embedded real-time systems, firmware development, and engineering principles\n\nExperience with ARM cores, DSP cores, and hardware accelerators\n\nProficiency debugging critical embedded systems using JTAG, trace, and logic analyzer tools\n\nSDK/application driver development for popular SoCs and embedded systems\n\nProcess & Quality:\n\nStrong knowledge of software development lifecycles, including unit testing, integration, and qualification\n\nExperience with ISO 26262 functional safety standards and compliance documentation\n\nProficiency with static analysis and code coverage tools (e.g., LDRA)\n\nLeadership & Soft Skills:\n\nProven ability to mentor junior engineers and drive projects with increasing responsibility\n\nStrong initiative and results-driven mindset\n\nExcellent collaboration skills across cross-functional teams\n\nAbility to thrive in interrupt-driven, fast-paced, and rapidly changing environments\n\nDemonstrated customer service orientation with strong ownership of issue resolution\n\nWhy Join TI?\n\nWork on cutting-edge technology that impacts millions of lives globally. Contribute to innovations in automotive, industrial, and robotics applications while growing your career with a world-class team.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Lead Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-03-17", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Design-Engineer_R52477-1", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nProficient in RTL coding, datapath designs, complex FIFO design Strong knowledge on complete design flows and rigorous checks before delivery to other teams or customers ex- LINT, SDC, CDC, DFT, CLP, Synth and trial PnR Good experience of micro architecture, design, synthesize for a complex SerDes IP in various technology nodes. Desired Protocols knowledge – USB, PCie, MIPI(DPHY), HDMI/Display Work closely with Analog design teams to co-develop algorithms, feedback design loops as well as high speed critical digital circuits Good understanding of working with signal processing IPs in terms of knowing calibrations, plls, dividers.\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Lead Analog IC Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-03-17", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009710", "is_hardware": true, "platform": "oracle", "jd_text": "About TI - Change the world. Love your job. \n\n Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\nAnalog Design Engineer (Lead) for Connectivity Products:\n\nConnectivity SoC’s with Radio & Micro controllers are widely used in Automotive, Industrial and Medical Applications. Some of the examples are BLE based Glucose Monitor patches and Tyre Pressure Monitors; UWB based access control KeyFobs for Cars. We are looking for an Analog Design Lead with complete design cycle experience in Architecture, Design, Schematic, Layout, Verification and SoC Integration and Debug. Some of the Analog / Mixed-signal designs that we are exploring include ADC, DAC, PLL, PGA, Filters, Crystal Oscillators, Temperature sensors, LDO, bandgap reference, DC-DC converters, Comparators etc. You will be part of the Central Analog team of Texas Instruments EP BU that is heading the Analog / Mixed-signal designs to be embedded into the SoC.\n\nIn this role, responsibilities may include:\n\nLead an Analog IC design team with product ownership and responsibility from definition to release to manufacturing\n\nDirect, guide and participate in activities of a research or technical design function responsible for designing, developing, modifying and evaluating electronic parts, components, integrated circuits for a variety of applications\n\nMake assignments for team members, providing design guidance as needed, developing schedules and monitoring progress throughout the project\n\nEvaluate intermediate and final results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout\n\nCollaborate with Design Verification teams during the pre-PG phase of a project to ensure completion of all technical tasks before PG\n\nWork with systems engineers, application engineers and marketing to prepare product briefs, datasheets, application notes and assisting in the definition of the product to meet customer needs as well as contributing to roadmap formulation and new concept creation\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nInterface and lead discussions with the customer and/or TI field sales/field applications teams to understand customer designs, problems and support as required\n\nActively participate in hiring, developing and evaluating personnel to ensure efficient operation of the organization and growth of the individuals into leader\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in Electrical Engineering\n\n6 years of relevant experience\n\nPreferred qualifications:\n\nAbility to take on challenging problems in analog/mixed-signal development for SoC and drive development of innovative solutions\n\nAbility to take the initiative and drive for results\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Trainee Engineer", "company": "Infineon", "location": "Bangalore (India)", "date_posted": "2026-03-16T10:00:43+00:00", "url": "https://jobs.infineon.com/careers/job/private?pid=563808970057480", "is_hardware": true, "platform": "eightfold", "jd_text": "#WeAreIn to make sure that our circuits are designed to perfection. Are you in?\nWe\nare seeking a highly motivated, talented individual to join our Silicon\nEngineering team as a Trainee Engineer - Digital Design Verification. In this\nrole, you will work on Graphics /Security IP, helping to ensure the functional\ncorrectness of complex, next-generation architecture. You will learn from\nindustry experts and gain hands-on experience building advanced simulation and\nemulation testbenches using industry-standard methodologies. \n\nYour role\nKey responsibilities in your new role\n\n \nTestbench  Development: Assist in developing, maintaining, and enhancing block-level  and chip-level simulation testbenches (TB)\nUVM  Architecture: Write scalable verification components, including drivers,  monitors, predictors, and scoreboards using SystemVerilog (SV) and UVM.  \nEmulation  Platforms: Collaborate with senior engineers to bring up emulation  testbenches for hardware-accelerated verification and pre-silicon  validation.  \nGraphics  IP Verification: Learn the intricate architecture of Graphics IPs  (pipelines, shaders, or memory controllers) and map out comprehensive  verification plans.  \nDebug  & Coverage: Run regressions, debug hardware failures using waveform  viewers, and write functional coverage covergroups to achieve 100% verification closure.\n\nYour profile\nQualifications and skills to help you succeed \n\nEducation:  Bachelor’s or master’s degree in Electronics Engineering, Computer  Engineering, Computer Science, or a related field (Graduation date within     the last 12 months).  \nLanguages:     Strong foundational knowledge of SystemVerilog (SV).  \nMethodology:  Exposure to UVM (Universal Verification Methodology) through university  coursework, lab projects, or internships.  \nCore  Concepts: Solid understanding of digital logic design, computer  architecture, and FIFO/arbitration mechanisms. \n\nScripting:  Basic proficiency in scripting languages like Python, Perl, or Bash for  automation.\n\nPreferred Qualifications (Bonus)\nPrior  internship experience in ASIC/FPGA design or verification.\nDirect  project experience involving Graphics IP, GPU architectures, or  high-throughput data pipelines.\nFamiliarity  with hardware emulation platforms (e.g., Palladium, Zebu, Veloce)  or FPGA prototyping.\nExperience  with EDA tools from Synopsys, Cadence, or Siemens (e.g., VCS, Questa,  Xcelium)\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\n\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. \nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\n\nGagandeep Kaur", "jd_status": "stored"}, {"title": "Sr Mask Design Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-03-13T14:18:29.385000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000114673788-sr-mask-design-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Job Responsibilities: \nLayout high performance Analog and Mixed Signal circuits using the latest Cadence Design Suite  \n\nPerform IP level layout tasks including device placement, routing, matching techniques, shielding, guard rings, and parasitic-aware layout practices.  \n\nWork at multiple levels of hierarchy, from macro level (block level) to Top-level (ESD/Pad frame) \n\nVerify connectivity and design rules with Assura, Calibre, PVS \n\nUse QRC extraction to analyze and reduce noisy/sensitive coupling \n\nUse third party tools to analyze IR drops and p2p resistance \n\nLiaise closely with analog designers on specific circuit requirements, e.g. power, matching, sensitivity, latch-up, ESD, etc. \n\nWork with CAD and CAE engineers to improve processes or features \n\nJob Requirements: \nBE/BTech in Electrical or Electronic Engineering is preferred.  A minimum of two to five years industry experience working on analog, power or mixed signal IC layouts  \n\nA good working knowledge of Analog IC layout and verification tools \n\nExperience in “routing” using latest IC617 Virtuoso tools, i.e. wires, busses, pin-to-trunk, etc. \n\nAdherence to a formal layout methodology that is both robust and compatible with existing IP, thereby creating further re-useable IP blocks \n\nGood working knowledge of constraints-driven layout is useful but not essential \n\nPrevious experience with BCD technology is a plus \n\nExperience in VSR and VCAR auto routing a plus \n\nExperience in schematic driven layout design, e.g. Modgens, Clones. \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nWe have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning.", "jd_status": "stored"}, {"title": "Staff / Sr. Staff Engineer, Android HAL, SOC Automotive Embedded SW ", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-03-13T13:16:28.148000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000114655494-staff-sr-staff-engineer-android-hal-soc-automotive-embedded-sw-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Lead Developer for Android HAL and middleware for Automotive SoCs. \nYou will develop highly optimized software for Renesas R-Car Gen5 series devices. Strong working knowledge of Android and RTOS environment for multi-core heterogenous SoCs is a key requirement. You will implement requirements for the next-generation IVI/ADAS products that comprise tools, software, and hardware. Your main responsibilities will be in the following areas: \nRelevant working experience \nRCAR Gen5 Android (AAOS/GKI) HAL & Middleware ownership—from bring-up to certification \n\nDrive AAOS enablement on R-Car Gen5 variants and align to the platform Android roadmap (A16/A17…)  \n\nEnsure compatibility readiness (xTS/CTS/VTS) and support pre-cert / validation flows as part of BSP deliverables \n\nDeliver production-grade components for SDK releases (docs, changelogs, release notes, packaging expectations)  \n\nAndroid HAL expertise (AIDL/HIDL) for automotive peripherals & SoC IP \n\nImplement/extend HALs for display, audio, camera, sensors, power/thermal, boot-time optimizations, and device-specific features \n\nIntegrate vendor drivers and expose stable interfaces to Framework/AAOS (permissions, SELinux, init/ueventd, VINTF manifests) \n\nDebug across layers (kernel↔driver↔HAL↔framework) using traces/logs (systrace/perfetto, logcat, ftrace) and root-cause systematically \n\nMiddleware & Framework integration for IVI/cockpit stacks \n\nBuild/maintain native services (binderized daemons), framework extensions, and vendor middleware to meet automotive UX/perf needs \n\nSupport long-term maintenance strategy (major upgrades + security/maintenance releases) with clean branching and backport discipline  \n\nCollaborate with partner stacks and “standard framework” integration expected in the Gen5 software model (BSP↔middleware↔apps)  \n\nVirtualization-ready design (Xen / multi-domain) and performance isolation \n\nEnable Android as native or guest (Xen-based) with VirtIO-style device exposure where applicable; debug GVM boundaries  \n\nAddress multi-domain constraints (timing, memory, I/O partitioning), and support fast-boot/boot KPI topics relevant to Gen5 programs  \n\nWork with security/TEE/boot-chain expectations typical of Gen5 platform packaging and delivery model  \n\nQuality, compliance, and delivery mindset (automotive-grade) \n\nOwn CI-friendly implementation: build reproducibility, automated tests, and regression triage across Android releases  \n\nDrive certification readiness: CTS/VTS execution, bug fixing, and evidence capture aligned to GAS/compatibility commitments  \n\nCommunicate crisply with global stakeholders, document decisions, and support customer issue analysis and releases \n\nEducation and Background: \nBachelors or Masters graduate (Electronics or Computer Science) \n\nOver 8+ years of embedded SW development on Android/FreeRTOS \n\nExpected role in Renesas \nDevelop advanced proof of concepts and SDK deliverables for customers. \n\nWork on latest open source software and adapt for Renesas Gen5 platforms. \n\nRelevant Experiences (Combination of good-to-have and must-have):  \nRelevant industry experience in embedded software development with a proven track record in translating complex use cases requirements into design, system specifications, standards, and software solutions. Focus shall be on open source software. \n\nAbility to work independently with strong motivation towards meeting deadlines with efficiency and focus \n\nArchitecture \n\nSystem architecture experience for heterogeneous / multi-core embedded SoC computing platforms. \n\nDevelopment \nEmbedded system software development experience including low level firmware, kernel, and user space components on an SoC product comparable to the Renesas R-Car family \n\nAbility to develop and debug on both real hardware as well as simulation and emulation environments \n\nDebug:  \nAbility to debug complex system level use cases involving hardware and software elements such as bandwidth/QoS knobs. \n\nSoftware debugging including CLI, PCB, and application level debug techniques  \n\nAbility to debug high speed communication interfaces including HW/SW co-debug \n\nCollaboration: \nAbility to collaborate with sales, marketing, architecture, customer, partners, and other groups to create best in class reference solutions, solve problems, and enable customer success  \n\nAbility to expand upon existing solutions in collaboration with architects and prior design teams \n\nAbility to work independently as well as in small teams \n\n​​​​​​​Communication: \nExcellent written and verbal communication due to frequent customer and internal communications; ability to provide direct, efficient, and clear customer communications under pressure \n\nFamiliarity with global business cultures (Japan, Europe, US, India) and strong cross cultural sensitivity \n\nFamiliarity with verbal and written Japanese (nice to have) \n\nTravel: \nFlexibility to manage occasional international travel on short notice to support customer success or internal initiatives \n\nAdditional notes: \nLocation : Bangalore \n\nReporting to Senior Manager of Engineering \n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nWe have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning.", "jd_status": "stored"}, {"title": "Sr Principal Verification Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-03-12", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2504895", "is_hardware": true, "platform": "oracle", "jd_text": "Principal Verification Engineer – Digital Compute, Analog & Mixed Signal Products\n\n   \n\nAbout Us\n\n  At onsemi, we help improve lives through silicon solutions every day. Our intelligent power and sensing technologies solve the world’s most complex challenges and lead the way in creating a safer, cleaner, and smarter world. Our group develops MCU and DSP systems as well as hardware accelerators that are used in a large variety of different products and markets.\n\n  The Role\n\n  We are looking for a Principal Verification Engineer and Manager with experience in the verification of embedded MCU/DSP systems, to build and manage a new product verification team, chartered to create a series of mixed-signal compute products, and benchmark such systems for a variety of applications.\n\n  What You’ll Do\n\n  •    Verification leadership: Lead and manage a mixed-signal verification team \n\n  •    Problem solving & innovation: Identify novel solutions for meeting the verification intent with quality and efficiency\n\n  •    Technical guidance & mentoring: Guide world-wide teams in technical areas, from microarchitecture to productisation\n\n#LI-VS1\n\nResponsibilities\nWhat Else You May Bring (Experience in some of the following areas is a plus)\n•    Experience in the design of CPU/MCU (sub)systems, compute functions and accelerators\n•    Development of signal processing components or processing systems\n•    Programming in Python for automation and C/C++ for embedded software\n•    Definition of design intent in one or more of specification, microarchitecture, structural / functional assessments (CDC, test readiness), verification methods (formal / simulation), physical design (synthesis, timing/power optimisation), process technology aspects, etc.\n•    Experience in FPGA prototyping\n•    Awareness in analog design practices and requirements\n \nOur commitment to you\nAs part of the onsemi team, you will have an opportunity to transform your tomorrow and operate in a diverse, inclusive, and socially responsible environment. If you’re passionate about shaping a better future, join us!\n#LI-VS1\n\nQualifications\nWhat You’ll Need\n•    B.Tech / M.Tech in Electrical Engineering or related technical field\n•    At least 12 years of strong technical experience in VLSI design verification, with specific emphasis on mixed-signal products\n•    Strong leadership and team management credentials\n•    An extensive technical background within the development of semiconductor products or sub-components (IPs)\n•    Experience with embedded CPUs, from a hardware and software/firmware perspective\n•    Strong communication skills\n•    Ability to define strategic actions, with appropriate design trade-off analyses\n#LI-VS1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "SOC Engineering, Sr Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-03-12", "url": "https://careers.synopsys.com/job/bengaluru/soc-engineering-sr-engineer/44408/99446435200", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\n \nYou Are:\nYou are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges. Your expertise spans the entire physical design spectrum—from synthesis, place & route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules. Your toolset includes industry-leading Synopsys solutions like Design Compiler, IC Compiler II, and PrimeTime, allowing you to deliver optimal results for high-frequency, low-power designs. \n \n Beyond your technical skills, you are a collaborative team player who communicates effectively across global teams, valuing diversity of thought and experience. You are motivated by problem-solving, have a keen analytical mindset, and are always seeking opportunities to automate and optimize workflows using Python, PERL, TCL, or other scripting languages. You take ownership of your work and pride yourself on delivering high-quality, robust solutions that drive organizational success. If you are excited about contributing to leading-edge silicon design and want to make a tangible impact, Synopsys is the place for you.\n \nWhat You’ll Be Doing:\nIndependently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.\nExecute synthesis, place & route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets.\nPerform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.\nCollaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.\nUtilize and optimize Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.\nDevelop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.\nContribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.\n \nThe Impact You Will Have:\nAccelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.\nEnable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.\nDrive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.\nFoster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.\nContribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.\nSupport strategic customer engagements and help expand Synopsys' presence in the semiconductor ecosystem through successful project outcomes.\n \nWhat You’ll Need:\nBachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.\n2+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).\nComprehensive hands-on experience with RTL2GDSII flows, including synthesis, place & route, CTS, timing optimization, STA, EMIR, and physical verification.\nProficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime.\nStrong scripting and automation skills using Python, PERL, TCL, or similar languages.\nSolid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs.\nExposure to high-frequency design and low-power design methodologies.\n \nWho You Are:\nProactive, self-motivated, and driven to achieve technical excellence.\nExceptional problem-solving and analytical skills with a keen attention to detail.\nExcellent communication and interpersonal abilities, comfortable working in diverse and global teams.\nCollaborative team player who values knowledge sharing and mentoring others.\nAdaptable and open to learning new technologies and methodologies in a rapidly evolving field.\n \nThe Team You’ll Be A Part Of:\nYou’ll join a world-class team of physical design engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry.", "jd_status": "stored"}, {"title": "NPU/AI Processor Architecture (RTL) design- Staff/Sr Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-03-11T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446717332051", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nQualcomm's Hexagon NPU Team is hiring for the various positions in Bangalore (India) location for the development of high-performance, energy-efficient CPU and AI processors. Hexagon NPU is an in-house built Qualcomm proprietary processor which is the center of Qualcomm's hybrid AI computing capability targeted for broad spectrum of AI use cases across market segments.\n\nWe are seeking highly skilled engineers with over 5+ years of experience and a strong knowledge in CPU/AI processor micro-architecture, architecture, RTL design, debug architecture, RAS, power-management and circuit designers to join our team.\n\nVarious positions are open across the broad spectrum of CPU/AI processor design :\n- RTL Design of high-performance CPU/AI processors\n- RTL coding, micro-architecture and architecture \n- Computer Arithmetic\n- Floating-Point design\n- Matrix Multiply engines\n- Vector Extensions\n- Memory sub-systems, Load/store, caches, atomics, coherence and consistency\n- Branch prediction, out-of-order, dispatch, schedulers\n- Multi-processor and multi-threaded systems\n- RISC-V \n- Power, performance and Area (PPA) optimizations\n- CPU sub-system Logic Design\n- Reliability, Availability, Serviceability (RAS)\n- Power management architecture and design, circuits, flows and systems \n- Di/Dt, voltage-noise, peak-currents and thermal mitigation\n- Functional safety (FUSA)\n- System and Silicon Debug\n\nJoin us to build IP blocks that power Snapdragon processors and AI inference engines.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Design Manager", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-03-11", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2504896", "is_hardware": true, "platform": "oracle", "jd_text": "About Us\n\nAt onsemi, we help improve lives through silicon solutions every day. Our intelligent power and sensing technologies solve the world’s most complex challenges and lead the way in creating a safer, cleaner, and smarter world. Our group develops MCU and DSP systems as well as hardware accelerators that are used in a large variety of different products and markets.\n\nThe Role\n\nWe are looking for a Design Manager with experience in the development of embedded MCU/DSP systems, to build and manage a new product design team. You will develop a series of digital compute products, and benchmark such systems for a variety of applications and driving the necessary improvements for differentiation\n\n \n\n#LI-MK1\n\nResponsibilities\nWhat You’ll Do\nDesign leadership: Lead and manage the team to create of a wide range of compute-focused products\nProblem solving: Identify novel solutions when architecting product functionality and/or with design methodologies\nTechnical guidance & mentoring: Guide world-wide teams in technical areas, from microarchitecture to productisation\nInnovation: Define and create design methodology and design flow improvements for efficiency and robustness\n#LI-MK1\n\nQualifications\nWhat You’ll Need\nB.Tech / M.Tech in Electrical Engineering or related technical field\nAt least 12 years of strong technical experience across any domain of VLSI design, with strong leadership and team management credentials\nAn extensive technical background within the development of semiconductor products or sub-components (IPs)\nExperience with embedded CPUs, from a hardware and software/firmware perspective\nStrong communication skills\nAbility to define strategic actions, with appropriate design trade-off analyses\nWhat Else You May Bring (Experience in some of the following areas is a plus)\nExperience in the design of CPU/MCU (sub)systems, compute functions and accelerators\nDevelopment of signal processing components or processing systems\nProgramming in Python for automation and C/C++ for embedded software\nDefinition of design intent: one or more of specification, microarchitecture, structural / functional assessments (CDC, test readiness), verification methods (formal / simulation), physical design (synthesis, timing/power optimisation), process technology aspects, etc.\nExperience in FPGA prototyping\nAwareness in mixed-signal design and verification\n#LI-MK1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Principal Analog Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-03-11", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2504904", "is_hardware": true, "platform": "oracle", "jd_text": "At onsemi, we help improve lives through silicon solutions every day. Our intelligent power and sensing technologies solve the world’s most complex challenges and lead the way in creating a safer, cleaner, and smarter world. Our group develops MCU and DSP systems as well as hardware accelerators that are used in a large variety of different products and markets.\n\nThe Role\n\nWe are looking for a Principal Analog Design Engineer with experience in the verification of embedded MCU/DSP systems, to build and manage a new analog design team. This team is chartered to deliver differentiated analog circuits to a series of mixed-signal compute products.\n\nOur commitment to you\n\nAs part of the onsemi team, you will have an opportunity to transform your tomorrow and operate in a diverse, inclusive, and socially responsible environment. If you’re passionate about shaping a better future, join us!\n\n#LI-RG1\n\nResponsibilities\nWhat You’ll Do\nDesign leadership: Create and deliver a series of analog circuits relevant for the mixed-signal products\nProblem solving & innovation: Identify novel solutions for delivering differentiation in circuit performance, quality, efficiency\nTechnical guidance & mentoring: Guide world-wide teams in technical areas, from architecture to productisation\nWhat Else You May Bring (Experience in some of the following areas is a plus)\nExperience in interfacing to embedded CPUs and accelerators\nUnderstanding of signal processing components or processing systems\nAwareness in digital design practices and requirements\n#LI-RG1\n\nQualifications\nWhat You’ll Need\nB.Tech / M.Tech in Electrical Engineering or related technical field\nAt least 12 years of strong technical experience in analog design, across a breadth of functions, and across technologies\nStrong leadership credentials\nAn extensive technical background within the development of semiconductor products or sub-components (IPs)\nExperience with analog test/productization \nStrong communication skills\nAbility to define strategic actions, with appropriate design trade-off analyses\n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Senior IP Design Verification Engineer - XBAR IP", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-03-11", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-IP-Design-Verification-Engineer---XBAR-IP_JR2014546", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of memory subsystem units for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n\nThe GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nYou will be responsible for verifying the ASIC design, architecture and micro-architecture of memory sub-systems/units using advanced verification methodologies.\n\nUnderstand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.\n\nComing up come up with test plans, tests and verification infrastructure for complex IPs/sub-systems.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nWork on advanced verification methodologies like SV/UVM.\n\nPerform functional coverage driven verification closure.\n\nWorking with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech., or equivalent experience.\n\n4+ years of relevant experience.\n\nExperience in verification of complex IPs/units and sub-systems.\n\nBackground in verification using random stimulus along with functional coverage and assertion-based verification methodologies.\n\nExpertise in Verilog.\n\nKnowledge in SystemVerilog or similar HVL / UVM or VMM.\n\nWays to stand out from the crowd:\nExperience in memory subsystem or network interconnect IP verification.\n\nDebugging and analytical skills with sound scripting knowledge.\n\nGood communication and excellent team player.\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Lead Analog Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-03-10", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25002373", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job. \nTexas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future — from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.\n\nThis is a great opportunity to be part of an established team that's continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electronics, mobile computing and communications.\n\nIn this role, responsibilities may include:\n\nLead an Analog IC design team with product ownership and responsibility from definition to release to manufacturing\n\nDirect, guide and participate in activities of a research or technical design function responsible for designing, developing, modifying and evaluating electronic parts, components, integrated circuits for a variety of applications\n\nMake assignments for team members, providing design guidance as needed, developing schedules and monitoring progress throughout the project\n\nEvaluate intermediate and final results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout\n\nCollaborate with Design Verification teams during the pre-PG phase of a project to ensure completion of all technical tasks before PG\n\nWork with systems engineers, application engineers and marketing to prepare product briefs, datasheets, application notes and assisting in the definition of the product to meet customer needs as well as contributing to roadmap formulation and new concept creation\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nInterface and lead discussions with the customer and/or TI field sales/field applications teams to understand customer designs, problems and support as required\n\nActively participate in hiring, developing and evaluating personnel to ensure efficient operation of the organization and growth of the individuals into leader", "jd_status": "source_unavailable"}, {"title": "Senior CPU Verification Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-03-09", "url": "https://careers.arm.com/job/bengaluru/senior-cpu-verification-engineer/33099/92560422256", "is_hardware": true, "platform": "talentbrew", "jd_text": "CPU Random Tools Engineer – Grade 4\n \nIntroduction to Arm\nYou know us. With 125 Arm-powered products shipped every second, we'll be in over a trillion smart devices by 2035. Your smartphone, award-winning VR gaming, the world's fastest supercomputer – our engineers are crafting the sophisticated core processors leading the race towards a connected, autonomous, hyper-performance future.\nARM designs the technology that is at the heart of sophisticated digital products, from wireless, networking and consumer entertainment solutions to imaging, automotive, security and storage devices. ARM improves people’s lives by enabling the intelligence in affordable, easy-to-use electronic products that transform the way we live and work. We work in partnership with a global network of leading technology companies which are using our smart low-power technology. Together we are enabling the future of a better world. \nARM is well recognized as the market leader in the CPU and System IP industry and this has been achieved by consistently delivering reliable and high quality IP products. The cost of design and manufacturing is high and that warrants “right first time” approach for all IP and System products. Time-to-market is essential for our partners to take care of steadfast competition in the marketplace, being first would enable them to get premium value from the end products. In this context, Design Verification of CPU IPs is an exciting challenge requiring an engineering abilities that is both broad and deep.\nSo, we promise you endless exciting opportunities to experiment and go even further in CPU IP design!\n \nJob Description: Role and Responsibilities\nAs an Engineer responsible for CPU Random Tools for stress verification, you will work on a sophisticated Random Instruction Sequences (RIS) tool. With a combination of techniques, the tool verifies the functionality of our CPU cores, being designed in Austin (US), Cambridge (UK) or Sophia Antipolis (FR). The existing team ensures addition of new architecture features, its customization to specific CPU cores, and provides support.\nYou will be based in Arm’s Bangalore design centre in India.\nAs Senior Verification Engineer, your role will cover the development of the tool from development to deployment, and accountable for:\nUnderstanding the intricacies of the CPU micro-architecture and defining how to push the test boundaries;\nArchitect and develop solutions to improve the generation of stimuli to produce programs to stress our next generation CPUs;\nImplementing and supporting the tool, from the early stages of CPU development to product maturity.\n \nJob Requirements\nProblem Ownership and ability to work from abstract requirements\nGood communication and presentation skills\nSelf-motivated and willing to take up additional responsibilities\nQuick learner with a strong desire to learn and develop new skills\n \nQualification and Experience\nB.Tech/B.S. or MTech/M.S. in Computer/Electronics Engineering or Computer Science from a reputed institute\n5-10 years of stable proven experience with significant project contributions\n \nCrucial Skills\nYou hold experience in software design, and should be comfortable working with low-level hardware\nYou have good solid understanding of programming languages, such as C and Python\nYou are knowledgeable about CPU architecture and micro-architecture concepts\nYou are able to understand assembly language (ASM)\nYou have strong interpersonal skills and ability to work well as part of a team with the willingness to tackle varied technical challenges.\nDesirable Skills\nFundamentals of Processor Architecture.\nBasics of ARM Architecture.\nFamiliarity with EDA tools and Hardware Design Verification.\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Design Verification Architect (Sr staff or above)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-03-06T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446717294511", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nRole Overview\nWe are looking to hire a strong technical leader to architect and overhaul the testbench environment for state-of-the-art interconnect IPs.\n\nResponsibilities\n• In-depth knowledge of state-of-the-art DV methodology\n• Drive testbench architecture and development to verify complex interconnect and subsystem designs while working with the wider engineering team\n• Ensure a scalable, reusable DV environment is built and deployable across different tiers of products\n• Work with all stakeholders to ensure program success\n\nMinimum Qualifications\n• Bachelor’s or Master’s degree in Engineering, Electronics, Information Systems, Computer Science, or a related field\n• 12+ years of hardware engineering experience or related work experience\n\nPreferred Qualifications\nRequired Skill Set:\n• Strong debugging skills; experience with UVM, SystemVerilog, and UPF\n• Understanding of specifications and standards, and development of relevant test plans\n• Experience with monitors, scoreboards, sequencers, and sequences that utilize scripts, SystemVerilog, UVM, and methodologies to increase the rate at which bugs are found and resolved\n• Post-silicon bring-up and HW–SW debug experience is a plus; knowledge and exposure to silicon debug toolchains is an added advantage\n• Thorough understanding of digital design concepts\n• Thorough understanding of DV and power DV methodologies and tools\n• Good understanding of ARM CPU architecture and ARM-based SoC architecture\n• Understanding of bus protocols such as AHB, AXI, ACE, ACE-Lite, and CHI\n\n• Understanding of multi-core ARMv8 CPU architecture, coherency protocols, and virtualization\n\nEducational Requirements\n• Bachelor’s degree in Engineering, Electronics, Information Systems, Computer Science, or a related field\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "IP Design Verification Director ", "company": "Astera Labs", "location": "Bengaluru, Karnataka, India", "date_posted": "2026-03-05T16:50:48-05:00", "url": "https://job-boards.greenhouse.io/asteralabs/jobs/4670099005", "is_hardware": true, "platform": "greenhouse", "jd_text": "Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\n\n \n\nJob Title: Director of Design Verification\n\nOverview\n\nWe are seeking a seasoned Director of Design Verification with 20+ years of experience to lead verification for a flagship product in our portfolio. This is a hands-on leadership role where you will define the verification strategy, oversee execution, and ensure first-pass silicon success for complex SoC designs in server, storage, and networking domains.\n\nKey Responsibilities\n\nOwn and drive the end-to-end verification methodology for a specific product line.\n\nLead, mentor, and grow a team of engineers, fostering technical excellence and innovation.\n\nGuide verification of industry-standard protocols such as PCIe and CXL across Physical, Link, and Transaction layers.\n\nChampion advanced methodologies (UVM, formal verification, AI-augmented flows) to accelerate coverage closure and improve efficiency.\n\nCollaborate closely with RTL design, architecture, and software teams to debug, refine, and optimize verification processes.\n\nRepresent verification in executive reviews, customer engagements, and industry forums.\n\nShape workforce transformation by building hybrid skill sets and preparing the team for AI-driven verification challenges of the 2030s.\n\nQualifications\n\nBachelor’s degree in Electrical or Computer Engineering (Master’s preferred).\n\n15+ years of experience in design verification, with a proven track record of leading teams and delivering complex SoC/silicon products.\n\nDeep expertise in PCIe/CXL protocols (Gen3 and above) and experience with third-party Verification IPs.\n\nStrong background in UVM-based test plan development, assertions, coverage analysis, and abstraction layer design.\n\nDemonstrated ability to manage priorities, engage with stakeholders, and drive organizational success.\n\nRequired Experience\n\nHands-on expertise with Verification IPs for PCIe/CXL (Gen3 and above).\n\nDeep experience in UVM-based test plan development, sequence generation, and coverage analysis.\n\nStrong background in writing assertions, cover properties, and analyzing coverage data.\n\nExperience in developing VIP abstraction layers to simplify and scale verification deployments.\n\nPreferred Experience\n\nExpertise in verifying PCIe/CXL Physical, Link, and Transaction layers, including compliance for EP/RC.\n\nExperience with buffering, queuing, and QoS in complex NoC-based SoCs.\n\nSystem-level performance analysis on switching fabrics.\n\nFamiliarity with AI-driven verification methodologies and workforce transformation strategies.\n\n \nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.", "jd_status": "stored"}, {"title": "Sr Staff engineer- Hardware Development", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-03-05T13:15:29.339000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000112926103-sr-staff-engineer-hardware-development", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Role Overview\nThis role is responsible for technical leadership and execution of hardware development for the RH850 Motor Control and Automotive Application Platform.\nThe Sr. Staff Engineer serves as a hardware domain expert, driving architecture, design quality, and technical execution while collaborating closely with systems, firmware/software, validation, and platform leadership teams.\nKey Responsibilities\nLead hardware architecture, design, and implementation for RH850 motor control and automotive application platforms.\nDrive hardware technical decisions, ensuring robustness, scalability, cost effectiveness, and alignment with platform requirements.\nOwn hardware execution from concept, design, and validation through qualification and production readiness.\nCollaborate closely with systems, firmware/software, validation, and product engineering teams to ensure seamless hardware‑software integration.\nSupport regulatory compliance, qualification, and Global Market Access (GMA) readiness for hardware deliverables.\nIdentify and mitigate hardware‑related technical risks, ensuring predictable execution and high quality.\nContribute to reference designs, development platforms, and documentation to enable broad customer adoption.\nAct as a technical mentor, influencing best practices and raising the bar for hardware design excellence.\n\nB. Tech/M. Tech in Electrical Engineering, Electronics, Computer Engineering, or related field with 12+ years of experience.\nHands‑on experience with Signal Integrity (SI) and Power Integrity (PI) analysis for high‑speed digital, mixed‑signal, and power‑dense designs. Applying SI/PI best practices in schematic design, PCB layout, stack‑up definition, decoupling strategies, and grounding.\nDeep expertise in embedded hardware design, including MCU‑based systems, motor control circuits, and power electronics.\nProven experience delivering embedded hardware designs from concept through production.\nPreferred qualifications\nExperience supporting embedded development platforms or reference designs with broad customer adoption.\nExposure to regulatory compliance and Global Market Access (GMA) requirements for global automotive markets.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nWe have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning.", "jd_status": "stored"}, {"title": "IP RTL Design Engineer", "company": "Samsung", "location": "SSIR, Goldstone, Bangalore, India", "date_posted": "2026-03-05", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/SSIR-Goldstone-Bangalore-India/IP-RTL-Design-Engineer_R115142", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centres outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.\nRole and Responsibilities\n\nRoles and Responsibilities\n\nThis position is for a Senior IP Design Engineer role at Samsung Semiconductor India Bangalore, where you will be involved in RTL design, synthesis and verification of various complex IP modules of Image Sensor products. You will be associated in the design development life cycle to support spec to tape-out defined by specific assignment. You will also be responsible for providing technical inputs or guidance to improve and adhere to hardware development and quality processes necessary to ensure the design consistently meets the required functionality, re-usability, reliability, performance and power targets to ensure Samsung Image Sensors meet their design targets.\n\n• Architecture, Design and RTL development for Image Processing IP's.\n• Technically lead various RTL modules development\n• Interfacing with cross-functional teams like Algorithm, Verification and Physical Implementation\n. Ensuring quality of design using Lint and CDC checks.\n• Synthesis, Area and power optimization.\n\n Necessary Skills / Attributes\n\n• Working experience in complex IP Design\n• Experience in designing and RTL coding using Verilog /System Verilog/VHDL and verifying design with module level test bench or with formal techniques.\n• Design QC using lint/CDC/DFT • Compile, elaboration and simulations for QC. Experience with Xcellium/VCS, Verdi, and Spyglass.\n• Understanding of image processing basics, Peripherals, Buses/Interconnects and Power Management.\n• Experience in writing functional design doc and/or functional specifications.\n• Experience in synthesis (Synopsys DC, RTL-A) and developing timing constraints (SDC) and Timing analysis. Experience in low power design methodologies and related power estimations, power measurements during implementation.\nExperience in developing/understanding of ECOs\n• Working experience in teams with collaboration of effort between Verification, Validation, Physical Design and DFT Additional Qualifications (preferred)\n• Experience in RTL integration tools like Magillem is added advantage.\n• Working experience in HLS tools like Stratus/Catapult would be added advantage.\nTeam player, can-do attitude is desirable. Passion for working on innovative technologies, eager to learn and ability to be analyse/debug designs are highly desirable.\n\nSkills and Qualifications\n\nExperience – 6+ years\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "SOC DV Emulation Engineer", "company": "Samsung", "location": "SSIR, Goldstone, Bangalore, India", "date_posted": "2026-03-05", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/SSIR-Goldstone-Bangalore-India/SOC-DV-Emulation-Engineer_R115139", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centres outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.\nRole and Responsibilities\n\nRoles and Responsibilities\nExperience in building and delivering emulation models from scratch. \nWorking experience in building emulation models for SOCs with LPDDR5/HBM3/PCIE/UFS/CSI/UCIE. \nHands on experience on Zebu Emulator. Palladium experience is a plus. \nExperience with using and integration various Transcators, AVIPS in emulation. \nExperience in Verilog, System Verilog, C/C++ coding for test bench creation. \nExperience at waveform debugging with Verdi, Trace32, Low Speed IPs is a must.   \nExperience using scripting is a plus. \nGood to Have Skills: \nARM based SOC architecture.\nDV Acceleration using Emulation. \nProtocol knowledge of UART, SPI, I2C. \nTransactor API integration of High-Speed IPs like PCIE, Ethernet, CSI, UFS, CAN\n\nSkills and Qualifications\n\nExperience – 4 to 7 years\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "SOC Design Verification Engineer", "company": "Samsung", "location": "SSIR, Goldstone, Bangalore, India", "date_posted": "2026-03-04", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/SSIR-Goldstone-Bangalore-India/SOC-Design-Verification-Engineer_R115109", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centres outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.\nRole and Responsibilities\n\nWill be involved in SOC verification and responsible for verifying one or more IP(s)/Block(s) from test plan development to GLS sign-off with code/functional coverage closure. He/she will work closely work with cross-domains team (PD, RTL, DFT) for reviews, debug and for technical discussions. \n\nSkills and Qualifications\n\nExperience – 4 to 7 years\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "SOC RTL Design Engineer", "company": "Samsung", "location": "SSIR, Goldstone, Bangalore, India", "date_posted": "2026-03-04", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/SSIR-Goldstone-Bangalore-India/SOC-RTL-Design-Engineer_R115108", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centres outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.\nRole and Responsibilities\n\nWill be part System Architecture and Design team and primarily responsible for IP/BLK level RTL integration and design of IP/glues/wrappers which involves complex high-speed protocol integration and support cross-functional teams (DV, DFT, PD). \nShall be responsible for handling the collaterals/reviews of cross-functional teams such as (but not limited to) i) Test plan/coverage reviews ii) Synthesis/Constraints QC iii) DFT insertion, HIP, SCAN strategies and QC at RTL level et al\n\nRequired Skills:\n\nSkills and Qualifications\n\nExperience – 4 to 7 years\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "Senior Analog IC Designer - Audio Converters", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-03-04", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25008864", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n Texas Instruments is seeking an Analog Design Manager. In this role, you will direct and guide the activities of a research or technical design function responsible for designing, developing, modifying and evaluating analog and mixed signal electronic parts, components or integrated circuitry for electronic equipment and other hardware systems. You may also evaluate final results of research and development projects to assure accomplishment of technical objectives. In addition, job functions include preparing and presenting reports outlining the outcome of technical projects and making recommendations for actions necessary to achieve desired results. As an Analog Design Manager, you may also select, develop, and evaluate personnel to ensure the efficient operation of the function.\n\n \n\nAbout The Job\n\nYou will be part of the team with charter to develop new Audio converters catering to PE, Automotive and Industrial market segment. Team has complete charter of end to end development of Audio ADCs, DACs, Codecs including devices with Class D integration. These devices are highly integrated mixed signal devices with on chip digital signal processing capabilities\n\nAs part of this role you will get opportunity to interface with various engineering teams within the product line including digital design, layout, firmware, verification, validation, test, systems, applications and marketing to successfully execute new products from concept to volume production and subsequent support.\n\nYou will be a core member in a design team driving flawless execution, while finding innovative design architecture and solutions to customers’ problems through “out of the box thinking” to deliver highly differentiated products.\n\nIn this role, responsibilities may include:\n\nAnalog design lead / chip lead of mixed signal audio products with product ownership and responsibility from definition to release to manufacturing\n\nDirect, guide and participate in activities of a research or technical design function responsible for designing, developing, modifying and evaluating electronic parts, components, integrated circuits for a variety of applications\n\nMake assignments for team members, providing design guidance as needed, developing schedules and monitoring progress throughout the project\n\nEvaluate intermediate and final results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout\n\nCollaborate with Design Verification teams during the pre-PG phase of a project to ensure completion of all technical tasks before PG\n\nWork with systems engineers, application engineers and marketing to prepare product briefs, datasheets, application notes and assisting in the definition of the product to meet customer needs as well as contributing to roadmap formulation and new concept creation\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nInterface and lead discussions with the customer and/or TI field sales/field applications teams to understand customer designs, problems and support as required\n\nActively participate in hiring, developing and evaluating personnel to ensure efficient operation of the organization and growth of the individuals into leader\n\nQualifications\nMinimum requirements:\n\nBachelor's degree in Electrical Engineering\n\n> 6 Years of Analog Design experience\n\n> 2 Years of hands on experience in Sigma Delta ADC or DAC\n\nKnowledge of Clocking (PLL, OSC), Reference, Power Management Designs\n\nExperience of leading full project (Chip lead) Or Analog design lead \n\nStrong understanding of signal processing, Analog design principles, including low-noise, low-distortion, and high-efficiency circuits\n\nProven record of nurturing talent\n\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\n\nStrong verbal and written communication skills\n\nAbility to quickly ramp on new systems and processes\n\nDemonstrated strong interpersonal, analytical and problem-solving skills\n\nAbility to work in teams and collaborate effectively with people in different functions (Digital, Test & Val, Firmware, Layout etc)\n\nAbility to communicate project status, challenges, and solutions to senior management and stakeholders\n\nAbility to take the initiative and drive for results\n\nStrong time management skills that enable on-time project delivery\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Staff Digital Verification Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-03-03T08:19:15.060000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000112354079-staff-digital-verification-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Experience: A minimum of 8+ years in state-of-the-art verification methodologies, specifically in the verification of IP/SoCs. Due to the complexity of our designs .\nComplex Design Adaptability: The candidate must quickly adapt and understand complex environments with minimal guidance from our team ,Knowledge of PMIC is an added advantage,\nIndividual Contributor: We require a self-motivated individual contributor who can manage several tasks, including environment updates, implementing checkers, and adding test cases.\nTechnical Skills:\nExpertise in System Verilog for verification, preferably using UVM, RAL, and implementing these methodologies.\nProficient in assertion-based verification and knowledge of GLS (Gate-Level Simulation) is a plus.\nSkilled in constraint random-driven verification with strong debugging abilities.\nFluent in Verilog RTL coding and ASIC design methodologies.\nCommunication: The candidate must possess concise, proactive communication skills.\nAccountability: Demonstrates ownership of solutions, ensuring their implementation and success.\n\nBachelor's degree in Computer Science, Computer Engineering, Electronics, or related field (Master's degree preferred)\nMinimum 8 years of professional experience in digital verification and ASIC design verification\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nWe have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning.", "jd_status": "stored"}, {"title": "Physical Design Engineer", "company": "MediaTek", "location": "Bangalore", "date_posted": "2026-03-02T16:00:00+00:00", "url": "https://careers.mediatek.com/en/jobs/MTB120240202001", "is_hardware": true, "platform": "mediatek", "jd_text": "What You Will Do:\n\n•Own planning, execution & closure of ~4 blocks in parallel, including highly complex blocks (high congestion & tight timing)\n•Drive block-level floorplanning, placement, CTS, routing & ECO closure using Cadence Innovus\n•Lead timing closure — Setup/Hold, MMMC, constraints/exceptions & QoR improvement\n•Debug congestion & routability issues — macro placement, pin access, blockages & density\n•Ensure block signoff readiness — DRC/LVS, SI-aware optimization & IR/EM closure\n•Drive clear metrics & closure actions across all assigned blocks\n•Coordinate with STA/DFT/Synthesis/CAD teams for seamless tapeout execution", "jd_status": "stored"}, {"title": "SOC / System Validation Architect", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-02-27T10:47:00+00:00", "url": "https://global-external-amd.icims.com/jobs/79488/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. SOC / System Validation Architect Roles & Responsibilities: 1. Validation Architecture & Strategy Define end‑to‑end SoC validation architecture spanning pre‑silicon (simulation, emulation, FPGA) and post‑silicon validation. Drive validation strategy alignment with SoC architecture, use‑cases, and product requirements. Architect coverage models (functional, scenario, performance, power, security, RAS). Define shift‑left validation methodologies to uncover system issues early. 2. Pre‑Silicon Validation Leadership Lead validation architecture using: Simulation (UVM‑based, hybrid environments) Emulation / acceleration platforms FPGA‑based prototyping Enable system‑level use‑case validation involving CPU, GPU, accelerators, IOs, memory, and fabrics. Guide complex cross‑IP and cross‑subsystem debug (RTL, firmware, software interactions). 3. Post‑Silicon & Silicon Bring‑Up Architect post‑silicon validation frameworks, diagnostics, and automation. Drive early silicon bring‑up, debug, and characterization. Ensure validation of performance, power, thermals, security, and RAS features. Partner with manufacturing and product teams to support production readiness. 4. Cross‑Functional Technical Leadership Act as a technical authority across validation, influencing design decisions upstream. Collaborate with: SoC Architects IP owners Firmware / BIOS teams System software and OS teams Represent validation in architecture reviews, tape‑out readiness, and exec forums. THE PERSON: A successful candidate will work with senior silicon design and validation engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. Required Qualifications 15+ years of experience in SoC validation, or system architecture. Deep expertise in SoC validation methodologies (pre‑ and post‑silicon). Strong understanding of: CPU/GPU architectures Interconnects and fabrics (NoC) Memory subsystems (DDR, HBM, cache coherency) High‑speed IOs (PCIe, Ethernet, USB, CXL, etc.) Hands‑on experience with emulation platforms. Proven strength in complex system‑level debug across HW/FW/SW boundaries. Excellent communication and technical influence skills. PREFERRED EXPERIENCE: Experience validating server, datacenter, automotive, or high‑performance SoCs. Expertise in RAS, security, and safety validation. Experience with production silicon ramp and yield learning. Prior role as technical architect or fellow‑level contributor. Publications, patents, or industry leadership contributions are a plus. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-NS1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Wireless R&D IP Verification Sr Lead/Sr Engineer/Engineer", "company": "Qualcomm", "location": "Hyderabad, Telangāna, India", "date_posted": "2026-02-27T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446715896462", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nKey Responsibilities\nContribute to flagship Wireless IP development covering WAN, WLAN, GNSS, and Bluetooth technologies.\n\nOwn end-to-end IP-level verification, including:\nDesign analysis and verification planning.\n\nDeveloping test benches and writing test cases using SystemVerilog/UVM.\n\nWriting assertions, running simulations, and achieving coverage goals.\n\nExplore and implement advanced DV methodologies (formal, simulation) to improve efficiency and quality.\n\nDebug RTL and testbench issues using industry-standard tools.\n\nCollaborate with design, architecture, and cross-functional teams to meet project milestones.\n\nMaintain and enhance verification environments for scalability and reuse.\n\nSkills & Experience\nStrong expertise in SystemVerilog/UVM and coverage-driven verification methodologies.\n\nProven experience building and maintaining medium-to-complex SV/UVM environments.\n\nProficiency in writing efficient constraint-random tests and achieving coverage closure.\n\nStrong debugging skills using tools like Verdi or similar.\n\nExposure to wireless IPs (Wi-Fi, Modem PHY, DSP blocks) is a plus.\n\nFamiliarity with formal/static verification techniques.\n\nPower-aware verification and Gate-Level Simulation (GLS) experience is highly desirable.\n\nScripting skills (Python, Perl) for automation.\n\nQualifications\nEducation: Bachelor’s or Master’s or PhD in Electrical/Electronics/Computer Science from a reputed institution.\n\nExperience:  1- 6 years\n\nSoft Skills\nGood communication and interpersonal skills.\n\nFlexibility to work with global teams.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "WIFI PHY Senior Design Verification Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-02-27T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446715437728", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nGeneral Summary:\nQCT's Bangalore Wireless R&D (WRD) HW team in Bangalore is looking for experienced Wireless HW design verification engineers to work on Qualcomm’s best in class chipsets for mobile phones, wearables and IOT . Candidate will be working with ASIC designs on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies.  In this role of WRD Verification Engineer, you will be verifying Wifi and/or Modem from both TX and RX perspective.\n \nThe responsibilities will majorly include:\nUnderstanding of Wireless systems PHY TX and RX design paths, Algorithms that control the various aspects of wireless systems.\n\nOwn complete IP/Block/SS level DV.\n\nOwn end to end DV tasks from design analysis, Verification Plan development , Coding Test bench and test cases, write assertions, running simulations and achieving all coverage goals.\n\nExplore innovative DV methodologies (formal, simulation and emulation based) to continuously improve the quality and efficiency of test benches.\n\nSuccessful candidate will be required to collaborate with worldwide design, architecture teams and other stake holder to achieve all project goals. Hence, strong communication skills are a must.\n\n \nSkills/Experience:\n2-4 years of strong experience in design verification\n\nStrong knowledge of System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodology\n\nProven experience of building or maintaining a medium to complex SV/UVM environments\n\nProven experience of writing efficient constraint random tests\n\nPrior Experience in verifying WIFI, Modem PHY layer is a strongly desirable.\n\nStrong debugging and analytical skills and independent problem-solving ability\n\nProficient in debugging RTL/TB issues using Verdi or similar tools\n\nExperience in formal / static verification methodologies will be a plus\n\nGood understanding of Wireless protocols, Modem/Wifi Standards is a plus\n\nExperience with Power Aware verification, GLS, and scripting languages such as Perl, Python is a plus.\n\nExperience in formal / static verification methodologies will be a plus\n\n \n \nPreferred Qualifications:\nUnderstanding of Wireless protocols, Modem/Wifi Standards\n\nExperience in IP verification of DSP related HW blocks.\n\nKnowledge on scripting languages such as Perl and(or) Python\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "SMMU Senior Lead Design Verification Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-02-27T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446716018918", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nGeneral Summary:\n\nOwnership of System Memory Management [SMMU] IP test bench and collaterals for the next generation System-on-chip (SoC) for smartphones, tablets and other product categories. System Memory Management Unit does virtual to physical address translation, dynamic allocation and access control of DDR memory, designed as per ARM SMMU architecture spec.\n \nJob responsibilities include\nOwnership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage)\nDevelop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench\nWork closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure\nDebug of regression signatures and identifying bug fixes\nDeveloping/Deploying scripts/tools for validation (Certitude, VC Formal, Fishtail)\nDebug and root cause post silicon issues in collaboration with Design, SW and test teams\nWork with SoC level performance modeling team on latency, bandwidth analysis\n\nRequired skillset include\nStrong debugging, Analytical and problem-solving skills\nExpertise on UVM, System Verilog coding\nKnowledgeable about ARM bus protocols (AXI, AHB, APB, CHI), Virtual Memory concepts, SoC system architecture\nExperience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved\nPost-si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage\nCommunication and collaboration skills to work with a large world-wide design organization\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "CPU Emulation Sr Lead Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-02-27T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446715581779", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nJob Description\nJob Overview:\nAs a CPU Emulation Engineer, you will work as part of CPU verification team to deliver emulation-based solutions for CPU team. You will work closely with all disciplines of CPU team to help verify and validate high performance CPUs.\nRole and Responsibilities\nWork closely with CPU RTL, performance, verification and SW teams to deliver emulation-based solutions.\nArchitect and develop test bench infrastructure in C/C++ and Systemverilog for enabling CPU emulation across different platforms.\nDevelop verification methodology, ensuring scalable and portable environment across simulation and emulation.\nDebug emulation performance and area issues to efficiently use emulation resources.\nDevelop environment to run verification test cases, OS boot, performance benchmarks and other vectors.\nDevelop debugging methodology to enable efficient debug and root causing of CPU functional and performance issues.\nDevelop and maintain emulation environment to collect metrics related to emulation environment.\nWork closely with emulation CAD team to resolve infrastructure issues and ensure productivity on emulation models.\nExecute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures.\nPreferred Qualifications\n5+ years of experience with emulation platforms – Palladium, Zebu, Veloce, FPGAs.\nExperience with synthesizing and optimizing designs and verification components developed in synthesizable Verilog.\nExperience with C/C++ DPI transactors and monitors.\nExperience in scripting using Perl, Python or shell scripts. Experience with packaging workloads for cloud.\nExperience with debugging ARM CPU based designs. Knowledge on ARM ISA and programmers’ model is a plus.\nExperience with Linux boot and firmware aspects is a plus.\nExperience with CPU architecture and micro-architecture is a plus.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Device Modeling Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-02-27", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009337", "is_hardware": true, "platform": "oracle", "jd_text": "About TI\n\n Texas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world’s brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We’re committed to building a better future – from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. Put your talent to work with us – change the world, love your job!\n\nAbout the Job\n\n Join TI's elite SPICE Modeling Group and drive cutting-edge semiconductor innovation. You'll extract and optimize compact (SPICE) models for next-generation devices while collaborating with world-class engineers across analog, digital, and mixed-signal design and process technology teams. This position is based in TI's Bangalore, India office.\n\nWhat You'll Do: \n\nExtract compact models for advanced semiconductor devices (MOS, LDMOS, DEMOS, BJT, Passives, GaN, RF, Sensors, NVM, RAM)\n\nPartner with designers and technologists to deploy modeling solutions for breakthrough circuit topologies\n\nDevelop innovative model formulations for emerging device technologies\n\nAutomate modeling infrastructure to accelerate technology development\n\nDevelop AI/ML-enhanced models and parameter extraction methodologies\n\nValidate models through comprehensive measurement and analysis\n\nThe person performing this role must be capable to plan effectively, drive schedules, meet critical deadlines on multiple tasks in parallel, lead technical discussions in their area of expertise, and work effectively across organizational boundaries. They must be able to clearly communicate project status and actions. Additionally, they must be able to interface with multiple organizations and work well on a diverse team to accomplish goals.\n\nWhy This Role Matters: \n\n Your modeling expertise will directly impact TI's next-generation products, from automotive to industrial to embedded applications. You will work at the intersection of process, device physics, and circuit design, solving complex challenges and delivering cutting edge solutions.\n\nReady to model the future? Apply today.\n\nQualifications\nMinimum requirements:\n\nPh.D. in Electrical Engineering or related field\n\n5+ years in compact (SPICE) modeling and semiconductor technology\n\nPreferred qualifications: \n\nExpert-level experience with models (BSIM, MEXTRAM, HICUM, MVSG-GAN, ASM) and parameter extraction tools (ICCAP, BSIMPROPLUS, MBP)\n\nDeep understanding of semiconductor physics and circuit analysis\n\nProficiency in EDA tools (Cadence), SPICE simulators (Spectre), and Verilog-A\n\nStrong programming skills in MATLAB/Python\n\nStatistical analysis of large datasets\n\nAI/ML expertise and TCAD experience highly valued\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "SOC Verification Engineer", "company": "Tesla", "location": "Bengaluru, India ; India", "date_posted": "2026-02-26T02:30:00", "url": "https://hire-r1.mokahr.com/social-recruitment/tesla/100004142?#/job/ea0e7118-211b-46d2-82b6-1b94c1c3dcbe", "is_hardware": true, "platform": "mokahr", "jd_text": "What to Expect\nThe Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI\nHardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life.\n\nThe AI Hardware team is looking for a SOC Verification Engineer who will be responsible for pre-silicon RTL verification of block and top-level SOC. With a strong knowledge of SOC architecture and SOC verification methodologies, you\nwill interact with multiple teams and build a metric-driven, configurable, and flexible verification environment. \n\nWhat You’ll Do\nWork with team members to define and set up a SOC-level verification environment.\nArchitect highly reusable UVM based test benches and integrate complex multi-instance VIPs, sub-system test benches, and test suites at the SOC level.\nAchieve targeted coverage and work with Design.\nArchitecture, SW, FW and external IP delivery teams to efficiently integrate and verify the design.\nCreate coverage driven verification plans from specifications.\nExecute, review, and refine to achieve coverage targets.\nDefine and review verification and validation test plans created by other members of the team.\nPost-silicon validation and SOC bring-up.\nUnderstand details of High Efficiency SOC.\nArchitecture, standard SOC peripherals and I/O (e.g. DDR, PCIe, USB), DMA, memory management schemes, multi-processor systems, Memory Controller Sub.\nSystems, PLL, power up and Secured Boot schemes.\n\nWhat You’ll Bring\n1+ years of dedicated/hands-on DV experience.\nStrong programming skills in UVM, C/C++, Python/Perl.\nExperience verifying CPU/GPU integration at the SOC level.\nCoherency verification at the SOC level.\nEmulation experience, working on available platforms such as Palladium, or Zebu.\nExperience in SOC bring-up and post-silicon verification.\nPost-silicon validation and SOC bring-up.\nHands-on verification experience with at least three of the following: NOC, PCIe, Bus Fabric, AHB, AXI, based bus architecture in UVM environment.\nExperience working on UPF integration, boot-up,\nHW/FW interaction verification.\nReset and power verification.", "jd_status": "stored"}, {"title": "ASIC RTL Design Engineer", "company": "Tesla", "location": "Bengaluru, India ; India", "date_posted": "2026-02-26T02:30:00", "url": "https://hire-r1.mokahr.com/social-recruitment/tesla/100004142?#/job/fa4c4628-32c0-43e0-9364-d47b3f3f43c4", "is_hardware": true, "platform": "mokahr", "jd_text": "The Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI\nHardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized\narchitectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life.\n\nThe Tesla AI Hardware team is looking for a ASIC RTL Design Engineer to work on industry leading AI accelerators. Candidate is expected to implement and document microarchitecture specifications, define system-level functional\nrequirements, and deliver high quality design to achieve project targets.\n \nWhat You’ll Do\nMicro-architecture specification and design.\nDeliver Performance, Area and Power-efficient RTL design.\nSpecification, microarchitecture, and RTL design of accelerators, memory and network subsystems.\nWork with the architecture and software teams to achieve design targets.\nBalance performance, power, safety, and cost requirements.\nTrade-off functional, physical and performance requirements.\nWork with cross-functional teams, including implementation, verification, and performance engineers.\nDesign for synthesis.\n\nWhat You’ll Bring\nHigh performance (low latency, high bandwidth) design techniques\nArea and power-efficient complex RTL design\nLow power microarchitecture techniques\nVerilog RTL logic design.\nExperience with simulators and waveform debug tools.\nKnowledge of logic design principles, including timing and power implications.\nDegree in Electrical Engineering, Computer.\nScience, or equivalent experience.\n5 or more years of industry experience.\nExperience with IEEE floating point is a plus.\nExperience with high speed SERDES or SOC design is a plus.", "jd_status": "stored"}, {"title": "Linux BSP Engineer", "company": "Samsung", "location": "SSIR, Goldstone, Bangalore, India", "date_posted": "2026-02-26", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/SSIR-Goldstone-Bangalore-India/Linux-BSP-Engineer_R114954", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.\nRole and Responsibilities\n\nSSIR Foundry System SW Team in india owns software development for SOCs which are built using advanced FAB technologies like 2nm to 7nm having HW IPs (LPDDR5x,HBM3,HBM4,PCIe, MIPI-CSI, USB, Multimedia Codec Accelerators), Graphical Processors (Mali GPUs), General purpose processors (All ARM profiles, RISC-V). Software development of the team involves developing Firmware, Bootloaders, Linux/RTOS device drivers, Power/Peformance Optimizations for customer use case, Development of Firmware used for screening of Silicon in FAB process (SLT). \n\nRequired Skills: \nSystem level understanding of ARM based SOC. \nHands on experience in bare metal programming and firmware code development. \nExpert in LPDDR5 & HBM3 bring up in pre-silicon and post-silicon envirnoment. \nWorking experience on Zebu Emulation.  \nVery good understanding of caching, coherency, Interleaving and trustzone. . \nWorking experience in post-silicon board bring up. \nStrong debugging skills based on trace32, waveform, verdi. \n\nGood to Have Skills: \nRISC-V based SOC architecture.\nProtocol knowledge of UART, SPI, I2C. \nUnderstanding of emulation transactors of low speed & high speed IPs\n\nSkills and Qualifications\n\nExperience -  4 to 12 years\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "Principal DFT Engineer", "company": "NXP", "location": "Pune", "date_posted": "2026-02-26", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Pune/Principal-DFT-Engineer_R-10061685", "is_hardware": true, "platform": "workday", "jd_text": "We are looking for a Principal HW DFT Engineer who will architect, implement, and validate in-vehicle networking devices as part of NXP’s Automotive grade products.  You will be responsible for advanced test strategies and implementation, verification and validation of pre/post tapeout of DFT features, overall test coverage improvements, and work closely with RTL and physical team on DFT timing constraints and closures. \n\nMain Job Tasks and Responsibilities:\n\nArchitecture & Strategy: Define and implement advanced DFT strategies, including Scan Architecture, JTAG, Memory BIST (MBIST), and Logic BIST (LBIST)\n\nImplementation & Verification: Lead the integration of digital subsystems, perform scan insertion, and generate ATPG (Automatic Test Pattern Generation) patterns while ensuring high fault coverage.\n\nSilicon Support: Drive post-silicon validation and debug activities to root cause failures and improve manufacturing test efficiency.\n\nCollaboration: Coordinate with physical design and test engineering teams to ensure timing closure and that test patterns are operational immediately upon silicon arrival.\n\nMinimum Required Qualifications\nEducation: B.S./M.S. Electrical/Computer Engineering (or similar degrees)\n\nExperience: Typically requires 10+ years of industry experience in SoC DFT implementation, verification, static timing closure,  test coverage analysis and improvement, and silicon bring-up on ATE\n\nTool Expertise: Proficiency with industry-standard EDA tools from Mentor Graphics/Siemens (Tessent), Cadence, or Synopsys\n\nTechnical Skills:\n\nDFT - Scan insertion and architecture, ATPG: Proficiency in generating test vectors to detect manufacturing faults like stuck-at, transition, and advanced faults, Built-In Self-Test (BIST): Integration of Memory BIST (MBIST) for embedded SRAM/ROM and Logic BIST (LBIST) for autonomous logic testing, Boundary Scan & JTAG, Test Compression: Implementing techniques to reduce test data volume and application time, which is critical for large System-on-Chip (SoC) designs.\n\nHardware Design & Implementation - HDL Proficiency: Strong command of Verilog or SystemVerilog for modifying RTL to insert test logic and writing test wrappers.  Timing & Constraints: Knowledge of Static Timing Analysis (STA) and creating DFT-specific timing constraints (SDC files) to ensure test logic does not degrade functional performance. \n\nVerification & Debug - Simulation: Conducting gate-level simulations (GLS) and verifying DFT logic for correctness before fabrication.  Post-Silicon Debug: Analyzing silicon data from Automated Test Equipment (ATE) to diagnose failures and improve manufacturing yield. \n\nSoftware & Tool Proficiency - EDA Tool Suites: Mastery of industry-standard tools such as Synopsys TestMAX/DFT Compiler, Mentor Graphics Tessent, and Cadence Modus. Scripting & Automation: Expertise in Tcl, Python, or Perl to automate test insertion flows, run simulations, and parse coverage reports.\n\nMore information about NXP in India...\n\n#LI-7013", "jd_status": "stored"}, {"title": "SOC Engineering, Sr Staff Engineer (EMIR)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-02-26", "url": "https://careers.synopsys.com/job/bengaluru/soc-engineering-sr-staff-engineer-emir/44408/100672041216", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\n\nYou Are:\nYou are a passionate and driven EMIR Engineer with a strong foundation in EMIR analysis and signoff flows, PDN implementation, and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges. Your expertise spans the entire Power Integrity spectrum—from PDN design, Static & Dynamic Signal/Power EM & IR Drop analysis with or without simulation vectors, Peak Current Analysis, EMIR ECO generation, and full SoC Power Integrity signoff. You have experience in block-level, Sub-system level and full-chip level EMIR signoff with aggressive schedules. Your toolset includes industry-leading Synopsys solutions like Redhawk, Redhawk-SC, PrimeRail, and PrimePower.\n\nBeyond your technical skills, you are a collaborative team player who communicates effectively across global teams, valuing diversity of thought and experience. You are motivated by problem-solving, have a keen analytical mindset, and are always seeking opportunities to automate and optimize workflows using Python, PERL, TCL, or other scripting languages. You take ownership of your work and pride yourself on delivering high-quality, robust solutions that drive organizational success. If you are excited about contributing to leading-edge silicon design and want to make a tangible impact, Synopsys is the place for you.\n\nWhat You’ll Be Doing:\nIndependently own and drive full EMIR analysis and signoff closure for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.\nExecute PDN implementation, Static & Dynamic Signal/Power EM & IR Drop analysis with or without vectors, Peak Current Analysis, EMIR ECO generation, and full SoC Power Integrity signoff to meet stringent performance and power targets. Perform block-level, sub-system level and full-chip PDN implementation, EMIR analysis, and trade-off between EMIR signoff closure and timing closure activities. Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.\nUtilize and optimize Synopsys EDA tools, including Redhawk, Redhawk-SC, PrimeRail and PrimePower, to deliver state-of-the-art silicon solutions.\nDevelop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.\nContribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.\n\nThe Impact You Will Have:\nAccelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.\nEnable Synopsys customers to achieve first-pass silicon success through robust and innovative PDN implementation, EMIR analysis & signoff closure.\nDrive technical excellence and best practices within the team, influencing the future direction of EMIR signoff methodologies at Synopsys.\nFoster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.\nContribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.\nSupport strategic customer engagements and help expand Synopsys' presence in the semiconductor ecosystem through successful project outcomes.\n\nWhat You’ll Need:\nBachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.\n5+ years of relevant experience in EMIR analysis & signoff closure, and particularly in advanced technology nodes (7nm/5nm/3nm). PDN implementation experience will be preferred. Comprehensive hands-on experience with EMIR flows, including PDN design, Static & Dynamic Signal/Power EM & IR Drop analysis with or without vectors, Peak Current Analysis, EMIR ECO generation, and full SoC Power Integrity signoff.\nProficiency with Synopsys EDA tools such as Redhawk, Redhawk-SC, PrimeRail, and PrimePower.\nStrong scripting and automation skills using Python, PERL, TCL, or similar languages.\nSolid understanding of EMIR, power integrity, reliability concepts, and power-planning techniques for both block-level and full-chip designs.\nExposure to high-frequency design and low-power design methodologies.\n\nWho You Are:\nProactive, self-motivated, and driven to achieve technical excellence.\nExceptional problem-solving and analytical skills with a keen attention to detail.\nExcellent communication and interpersonal abilities, comfortable working in diverse and global teams.\nCollaborative team player who values knowledge sharing and mentoring others.\nAdaptable and open to learning new technologies and methodologies in a rapidly evolving field.\n\nThe Team You’ll Be A Part Of:\nYou’ll join a world-class team of Backend Engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry.\n\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior Staff SOC Engineer (Physical Design)", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-02-26", "url": "https://careers.synopsys.com/job/bengaluru/senior-staff-soc-engineer-physical-design/44408/99336131552", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\n\nYou Are:\nYou are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges. Your expertise spans the entire physical design spectrum—from synthesis, place & route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules. Your toolset includes industry-leading Synopsys solutions like Design Compiler, IC Compiler II, and PrimeTime, allowing you to deliver optimal results for high-frequency, low-power designs. \n\nBeyond your technical skills, you are a collaborative team player who communicates effectively across global teams, valuing diversity of thought and experience. You are motivated by problem-solving, have a keen analytical mindset, and are always seeking opportunities to automate and optimize workflows using Python, PERL, TCL, or other scripting languages. You take ownership of your work and pride yourself on delivering high-quality, robust solutions that drive organizational success. If you are excited about contributing to leading-edge silicon design and want to make a tangible impact, Synopsys is the place for you.\n\nWhat You’ll Be Doing:\nIndependently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.\nExecute synthesis, place & route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets.\nPerform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.\nCollaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.\nUtilize and optimize Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.\nDevelop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.\nContribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.\n\nThe Impact You Will Have:\nAccelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.\nEnable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.\nDrive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.\nFoster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.\nContribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.\nSupport strategic customer engagements and help expand Synopsys' presence in the semiconductor ecosystem through successful project outcomes.\n\nWhat You’ll Need:\nBachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.\n5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).\nComprehensive hands-on experience with RTL2GDSII flows, including synthesis, place & route, CTS, timing optimization, STA, EMIR, and physical verification.\nProficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime.\nStrong scripting and automation skills using Python, PERL, TCL, or similar languages.\nSolid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs.\nExposure to high-frequency design and low-power design methodologies.\n\nWho You Are:\nProactive, self-motivated, and driven to achieve technical excellence.\nExceptional problem-solving and analytical skills with a keen attention to detail.\nExcellent communication and interpersonal abilities, comfortable working in diverse and global teams.\nCollaborative team player who values knowledge sharing and mentoring others.\nAdaptable and open to learning new technologies and methodologies in a rapidly evolving field.\n\nThe Team You’ll Be A Part Of:\nYou’ll join a world-class team of physical design engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry.\n\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Embedded Linux & Firmware Developer (Staff/Sr Staff) – Custom CPU Post-Silicon Team", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-02-24T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446716288578", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nQualcomm’s Custom CPU Post-Silicon team is seeking an experienced Embedded Linux and Firmware Developer to help shape the future of high-performance computing. In this role, you will design, develop, and maintain bare-metal firmware and Linux-based software stacks for our next-generation custom CPU platforms.\n\nWhat You’ll Work On\nFirmware & Kernel Development: Design, implement, optimize and maintain Linux kernel modules, device drivers, bootloaders, and bare-metal firmware for custom CPU-based embedded hardware and emulation platforms.\n\nBoard Support Packages (BSP): Develop and maintain BSPs for new and existing hardware platforms, including bootloaders, kernel configuration and  device tree\n\nHardware Bring-Up: Collaborate with hardware engineers to enable software stack on silicon and emulation platforms, debug hardware-software interactions, and ensure seamless integration.\n\nSystem Optimization: Analyze and resolve issues related to system performance, memory usage, power consumption, and reliability.\n\nDebug & Troubleshoot: Diagnose complex technical issues across embedded Linux OS, drivers, and high-level operating systems (Ubuntu, Android, Yocto).\n\nOpen-Source Strategy: Provide architectural guidance and establish processes for open-source software delivery, including CI/CD pipelines and testing frameworks.\n\nContinuous Innovation: Stay current with Linux development trends and emerging open-source technologies.\n\nDocumentation: Create clear technical documentation for designs, code, and test procedures.\n\nCross-Functional Collaboration: Work closely with hardware, software, and product teams to define requirements and deliver high-quality integrated solutions.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nWhat You Bring\nEducation: Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related field.\nExperience: Strong (10+ years) in embedded bare-metal and Linux development.\nTechnical Expertise:\nStrong proficiency in C/C++ for embedded systems.\n\nExperience with Python, shell scripting, CMake, and embedded toolchains.\n\nSolid understanding of ARM SoC/CPU architecture.\n\nDeep knowledge of Linux internals (drivers, kernel modules, device tree, scheduler, DVFS, power management).\n\nExperience with embedded Linux distributions and build systems (Yocto, Android, Ubuntu).\n\nHands-on experience with debugging tools (GDB, JTAG, oscilloscopes).\n\nAbility to interpret hardware schematics and datasheets.\n\nKnowledge of hardware interfaces (I2C, SPI, UART, USB, Ethernet, CAN, GPIO).\n\nExperience with Git, GitHub/GitLab, CI/CD, Docker.\n\nStrong technical documentation skills. \n\nNice to Have\nExperience with Linux kernel upstream process.\n\nChip/SoC bring-up on silicon, emulation, and simulation platforms.\n\nARMv8/ARMv9 architecture and ARM assembly language expertise.\n\nExposure to RISC-V architecture.\n\nFamiliarity with open-source bootloaders and firmware (UEFI EDK2, coreboot, U-Boot, LK, TF-A, Zephyr RTOS). \n\nWhy Join Qualcomm?\nYou’ll work on cutting-edge CPU platforms, collaborate with world-class engineers, and contribute to innovations that power modern computing. If you thrive on solving complex technical challenges and shaping next-generation embedded systems, we want you on our team.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Senior GPU Memory Subsystem Architect", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-02-21", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-GPU-Memory-Subsystem-Architect_JR2012902-1", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.\n\nNVIDIA is seeking a motivated memory subsystem architects with great analytical skills and a deep understanding of system architecture and performance, to work with a team to model, debug and analyze performance issues in the Memory subsystem.\n\nWhat you will be doing:\nContribute to advancing GPU Architecture and Simulators, GPU testing infrastructure, metrics, and/or compilers.\n\nPerformance modeling and simulation of features to improve memory system efficiency.\n\nDevelop test plans and testing infrastructure.\n\nDebug tests on architecture simulators.\n\nPerformance analysis/ bottleneck analysis of sophisticated, Memory subsystem units and features.\n\nWork on hardware models of different levels of extraction, including performance models, RTL test benches and emulators to find performance bottlenecks in the system.\n\nWorking with various multi functional teams like ASIC design and verification..\n\nWhat we need to see:\nMaster/Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering or related field (or equivalent experience).\n\n3+ years experience dealing with system level architecture and performance issues.\n\nStrong programming ability in C, C++. Exposure to Verilog/System Verilog is a strong plus.\n\nGood understanding of Memory subsystem architecture, caches , MMU, memory controller, NOC / interconnects, computer architecture.\n\nDebugging and analysis, including use of RTL dumps to debug failures.\n\nExposure to performance simulators, cycle accurate/approximate models or emulators for pre-silicon performance analysis is a plus.\n\nStrong communication and interpersonal skills are required along with the ability to work in a dynamic, product oriented, distributed team.\n\nWays to stand out from the crowd:\nKnowledge of the memory system, caching, interconnects, DRAM controller, Memory management unit, performance modeling and analysis.\n\nWidely considered to be one of the technology world’s most desirable employers. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, perform essential job functions, and receive other benefits and privileges of employment.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "NPU / AI Processor RTL Design - Sr Staff", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-02-19T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446714455327", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nThis position is for RTL designer role in DSP processor team. The position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced technologies. The successful candidate will possess detailed understanding of RTL design, synthesis, static timing analysis, formal verification, PLDRC, clock domain crossing, and low power techniques. Knowledge and experience of microprocessor integration is a definite advantage.\n \nSkills/Experience \n \nMust have 3 to 15 years of practical experience with details of RTL development (VHDL and/or Verilog) including:\nfunctional and structural RTL design, design partitioning,\nsimulation and regression, collaboration with design verification team. Must have good familiarity with latest RTL languages and tools, including: simulation systems (e.g. Modelsim, VCS), synthesis tools (e.g. Design Compile), static timing tools (e.g. Prime Time), Linting tools, CDC tools, UPF, code coverage, System Verilog Assertion, etc.\n\nExperience with the following area is highly desirable:\nStrong processor architecture knowledge\n\nMicroarchitecture implementation\n\nMicroprocessor integration\n\nLow power design\n\n \nResponsibilities \n \nDevelop RTL for multiple logic blocks of a DSP core\nRun various frontend tools to check for linting, clock domain crossing, synthesis, etc.\nWork with physical design team on design constrain and timing closure\nWork with power team on power optimization\nWork with verification team to collaborate on test plan, coverage plan, and coverage closure\n\nMinimum Qualifications:\n•    Bachelor's degree in Electrical/Electronics Engineering, Computer Engineering, or related field and 3+ years of Hardware Applications Engineering or Hardware Design experience or related work experience.\n                                                                    OR\nMaster's degree in Electrical/Electronics Engineering, Computer Engineering, or related field and 2+ years of Hardware Applications Engineering or Hardware Design experience or related work experience.\n                                                                    OR\nPhD in Electrical/Electronics Engineering, Computer Engineering, or related field and 1+ year of Hardware Applications Engineering or Hardware Design experience or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Sr Principal Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-02-19", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Sr-Principal-Design-Engineer_R53284", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nBE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer\n\n12+ years of Design Verification experience with SV/UVM\n\nStrong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.\n\nDesign Verification experience verifying complex designs and leading projects from concept to verification closure.\n\nStrong hands-on UVM and System Verilog coding experience and functional verification environment development is required.\n\n   Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantag\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Sr Principal Design Engineer", "company": "Cadence", "location": "PUNE 04", "date_posted": "2026-02-19", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/PUNE-04/Sr-Principal-Design-Engineer_R53296", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nExperience: 10- 15 years\nLocation - Bangalore/Pune/\nResponsibilities:\n· Complete DFT ownership of projects including:\nTest architecture definition.\n\nIdentifying and implementing RTL changes for DFT.\n\nPerforming scan insertion, LEC checks, low power CLP checks.\n\nDeveloping timing constraints for test mode timing closure.\n\nScan and ATPG for different fault models.\n\nBoundary scan, ACJTAG, IEEE 1500 implementation and verification.\n\nIEEE1687 (iJTAG) compliant ICL/PDL for functional manufacturing tests.\n\nRunning zero delay and timing simulations and debugging on all the above aspects.\n\nSupporting post silicon bring up.\n\nInteracting with customers on DFT aspects and support Marketing & Pre-Sales team.\n\nExperience working on very high speed and low power designs.\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Lead Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-02-19", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Design-Engineer_R52854", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nBE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.\n4+ years of Design Verification experience with SV/UVM\nStrong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.\nDesign Verification experience verifying complex designs and leading projects from concept to verification closure.\nStrong hands-on UVM and System Verilog coding experience and functional verification environment development is required.\nPrior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Design Verification Manager", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-02-19", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009245", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\nThe MSP design team, part of Embedded Processing (EP), develops cutting-edge system-on-chips (SoCs) that are affordable and ultra-low-power, featuring integrated high-performance digital and analog peripherals for a wide range of applications in the industrial, automotive, and embedded sectors. The team is responsible for architecting and developing differentiated intellectual properties (IPs) and SoCs that minimize power consumption while delivering superior analog and computing performance. The team’s responsibilities include designing low-power SoC architectures, hardware accelerators, safety and security infrastructure, and application-specific control and communication peripherals. They also oversee the integration of these IPs into SoCs, along with implementation, tape-out, and post-silicon release-to-market enablement. \n\nAs a Verification Manager, you will play a crucial role in ensuring the quality and reliability of our advanced MSP products. Your duties will include verifying IPs, SoC designs, and assisting with customer debugging, while also contributing to the development of robust verification methodologies and strategies in accordance with ISO 26262/ISO 21434 standards.\n\n \n\nResponsibilities:\n\nEnd-to-End ownership of IP/subsystem/SOC DV/Post silicon debugs ownership right from spec definition till the post silicon verification and solving the customer issues. This includes:\n\nTechnical: \n\nActively collaborate with the architecture team during the specification definition phase. \n\nDefine the verification strategy along with a plan to ensure 100% traceability between specifications and regression, including standard signoff metrics. \n\nConduct IP, SubSystem, and SoC verification, covering both functional and firmware scenarios in RTL/PARTL and GLS/PAGLS modes.\n\nIP/SS/SOC verification covering functional and Firmware scenarios in RTL/PARTL, GLS/PAGLS modes. \n\nOwn the DV environment, which includes defining and developing test benches, enhancing UVC integration, updating checkers and coverage monitors, and adapting the DV flow as needed for the project.\n\nProficient in analog and mixed-signal (AMS) verification, clock domain crossing (CDC) digital verification, formal verification, and post-silicon verification. \n\nWork closely with cross-functional teams - including Architecture, RTL, PD, DFT, Systems, Analog, Firmware, and Application teams - to achieve verification goals for IP, subsystem, and SoC from specification definition through to post-silicon verification closure.\n\nProvide final SoC DV signoff based on regression results, coverage metrics, and DV to specification traceability using C and/or SV-UVM, while adhering to ISO 26262/ISO 21434 guidelines. \n\nActively participate in customer reviews and certification processes (ISO 26262/ISO 21434).\n\nQualifications\nMinimum requirements:\n\nEducation: Bachelor’s or Master’s degree in EE/EC/EI/CS, or related specializations.\n\nExperience: A minimum of 8-12 years in relevant fields.\n\nPreferred Skillset:\n\nExperience in C-based System-on-Chip (SoC) design verification (DV), with exposure to firmware verification and deep understanding of UVM/SystemVerilog, Specman, GLS/PAGLS/UPF based verification, post-silicon verification, etc.\n\nProficient in scripting languages such as Perl and Python, and knowledgeable in AI/ML-based DV. \n\nIn-depth understanding of various standard protocols, including AHB, CAN, I2C, SPI, UART, USB.\n\nWork experience in a C-based environment involving ARM systems, particularly with power-aware simulations, is a significant advantage.\n\nStrong grasp of digital design fundamentals, computer organization and architecture, and bus protocols.\n\nExcellent debugging skills with Verilog and VHDL designs.\n\nSolid problem-solving abilities.\n\nFamiliarity with Cadence tools (such as Xcelium, vManager, Formal JG applications, and safety simulators) or similar tools and DV flows.\n\nDemonstrate excellent verbal and written communication skills, enabling the development of strong relationships and seamless interaction with key internal and external stakeholders.\n\nProven ability to manage, lead, and collaborate with cross-functional teams while taking the initiative to drive projects forward. \n\nFamiliarity with functional safety and cybersecurity processes\n\nProactively improve daily operations by keeping up with the latest technical trends and actively participating in both internal and external technology forums and conferences.\n\nDemonstrate strong interpersonal and analytical skills to effectively address complex problems and navigate organizational challenges.\n\nQuickly adapt to new systems and processes while managing time effectively to ensure on-time delivery.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Peripherals Design Verification -Sr Staff Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-02-18T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446716930413", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nAs a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\n8+ years’ experience in unit and IP level verification.\nWorked on coverage driven constraint random verification.\n\nKnowledge of standard protocols such as PCIe, CXL, USB, Ethernet.\n\nStrong in System Verilog, UVM, Test planning\n\nSound experience in testbench (stimulus, agent, monitor, checker) development.\n\nWorked in the verification having c based reference model inside the testbench\n\nExposure in scripting(perl, Python).\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "STA Synthesis Engineer", "company": "Samsung", "location": "SSIR, Goldstone, Bangalore, India", "date_posted": "2026-02-18", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/SSIR-Goldstone-Bangalore-India/STA-Synthesis-Engineer_R114597", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.\nRole and Responsibilities\n\nRoles and Responsibilities\n\n·         Complete ownership of timing constraint at image sensor full chip and sub system levels. This includes:\no    Timing constraint (Hierarchical, Flat) development and release for Synthesis/PD work\no    Timing constraint validation using various EDA tools\no    Analysis of pre-layout and post-layout timing reports and debug\no    Incremental update of constraint as and when it is required\no    Working with RTL,  DFT and PD teams independently and driving in timing closure both at sub system and full  chip level.\n·         RTL PPA analysis (physical and power aware) at sub system levels for power, performance, area trade-off. This includes:\no    Running relevant EDA tool and generate reports\no    Analysing the reports\no    Working with RTL , PD teams to improve the quality of RTL and Physical implementation\n·         Development of necessary scripts in TCL, Perl and/or Python for efficiency improvement\n\nRequired Skill Set:\n·         Strong understanding in STA fundamentals, AOCV/POCV, signal integrity, cross-talk noise, process variation, timing ECO generation etc.\n·         Hands-on experience in writing timing constraints at full chip and/or sub system level\n·         Hands on experience in timing constraint validation and clean up at full chip and/or sub system level\n·         Hands-on experience in pre and post layout timing analysis (both flat and hierarchical) and debug\n·         Experience in driving timing convergence at full chip and/or sub system level.\n·         Hands-on experience with STA tools: PrimeTime and/or Tempus\n·         Experience in both physical and UPF aware synthesis using Industry standard EDA tools\n·         Good understanding of UPF basics, different power optimization techniques\n·         Experience in UPF based static low power check (RTL, Netlist) at full chip and/or sub system level is a plus\n·         Experience in power analysis at full chip and/or sub system level is a plus\n·         Knowledge of ASIC Back End flows and relevant Tools\n·         Good automation skill using  TCL, Python and/or Perl\n·         Ability to handle multiple project execution\n·         Ability to work with multiple stakeholders independently\n·         Good analytical and problem solving skills\n\nExperience – 4 to 7 Years of Experience\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nSkills and Qualifications\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "MBIST Diagnostics Engineer - Sr Staff/Staff Engineer", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2026-02-17T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446716914413", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nWe are seeking an experienced and innovative professional to lead the development of advanced memory diagnostic methodologies and tools for next-generation SoCs. This role involves driving cutting-edge solutions in DRAM testing, failure analysis, and AI/ML-based pattern recognition to improve memory yield and reliability across high-volume manufacturing environments.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nMinimum Qualifications:\nExperience in developing diagnostic tools for emerging memory technologies.\n\nExposure to data analytics platforms for large-scale failure analysis.\n\nBachelor’s or Master’s degree in Electrical engineering, Computer Engineering, or related field.\n\nPreferred Qualifications:\n8+ years of experience in memory diagnostics, DRAM test, and failure analysis in advanced SoC environments.\n\nDeep understanding of fault isolation, redundancy schemes, fault models and memory test algorithms.\n\nExperience with AI/ML techniques applied to pattern recognition or data analytics in semiconductor test or yield domains.\n\nProficiency in Python, Perl, TCL and data visualization tools.\n\nExperience with HTOL, RMA debug, and high-volume manufacturing diagnostics.\n\n Knowledge of memory redundancy, error correction, and self-repair mechanisms.\n\nKnowledge of implementation of MBIST solutions using industry-standard tools (e.g., Mentor Tessent, Synopsys etc).\n\nStrong analytical and problem-solving skills with a data-driven mindset.\n\nExcellent communication and collaboration skills in a cross-functional, global environment\n\nKey Responsibilities:\nDevelop and enhance memory diagnostic methodologies including DRAM-specific diagnostics.\n\nDefine and develop memory test and repair algorithms (BIRA, ECC, redundancy analysis)\n\nIsolate failing memory locations and analyze failure signatures to support yield improvement, RMA, and HTOL debug.\n\nEvaluate and improve memory yield through data analysis and test coverage enhancements.\n\nDesign and implement AI/ML-based pattern recognition tools to enable advanced bitmapping and failure characterization beyond the capabilities of current tools.\n\nCollaborate with silicon validation, product engineering, and yield analysis teams to correlate diagnostics with silicon behavior.\n\nDrive innovation in diagnostic algorithms and tool development to support future technology nodes and memory architectures.\n\nProvide technical leadership and mentorship to junior engineers and cross-functional partners\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "RTL Design Lead Engineer", "company": "Samsung", "location": null, "date_posted": "2026-02-17", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/RTL-Design-Lead-Engineer_R109851", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nRole and Responsibilities\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products. \n\nRoles and Responsibilities\n• Technically managing design and development of Storage IPs. Prepare project plan, risk management plan, schedule tracking of state of the art, cutting edge designs, ensuring quality by sticking to company defined process. Architecture, Design and RTL development for storage controller IP's based on NVMe, UFS, and high speed peripheral bus standards such as PCIe and CXL. \n• Interfacing with cross-functional teams like Verification, Validation. SoC  and FW .\n• Ensuring quality of design using Lint and CDC checks.\n• Synthesis, Area and power optimization.\n• Developing the timing constraints ( SDC) and ECO scripts.\n Necessary Skills / Attributes\n.• Project Management. Working experience in complex IP Design  to meet market leading PPA metrics\n• Experience in designing and RTL coding using Verilog /System Verilog/VHDL.\n• Design QC using lint/CDC/DFT\n• Compile , elaboration and simulations for QC. Experience with VCS/NCsim, Verdi, and Spyglass.\n• Understanding of storage controller Architectures, Peripherals, Buses/Interconnects and Power Management.\n• Understanding of Bus Architectures (AXI/AHB), NOC (Network-on-Chip ) and ARM CPU Architectures.\n• Experience in writing functional design doc and/or functional specifications.\n• Experience in synthesis using Synopsys Design Compiler ( DC) and developing timing constraints ( SDC) and Timing analysis.\n• Experience in developing/understanding of ECOs\n• Working experience in teams with collaboration of effort between Verification, SoC integration, Physical Design and DFT Additional Qualifications (preferred)\n• Experience in RTL integration tools like Magillem is added advantage.\n• Working experience in High speed serial protocols like PCIe,  NVMe, UFS Familiarity with FPGA based development is additional plus\n• Team player, can-do attitude is desirable. Passion for working on cutting edge technologies and ability to debug is highly desirable.\n\nExperience – 14 to 20 Years\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\nSkills and Qualifications\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "Analog Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-02-17", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009195", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\nAbout Texas Instruments\nAs a global semiconductor company, we design, manufacture, test and sell analog and embedded processing chips to nearly 100,000 customers. Our products enable electronics everywhere and in things you experience every day - from health care, smart homes and connected cars to drones, smart phones and more. Our passion to create a better and more sustainable world by making electronics more affordable through semiconductors drives us to make our technology smaller, more efficient, more reliable and more affordable.\n \nAnalog Design Engineer for DCC/DAC team\nDesign analog blocks and IPs for precision DAC products in High-voltage, precision process nodes like HPA9.\nPrior experience of designing and simulating (one or more) analog IPs like band-gap reference, DAC, amplifier, oscillator, comparator, power-management blocks like POR, BOR is required.\nShould have handled post layout parasitic back-annotation in addition to design.\nStrong understanding of analog concepts. Strong analytical and problem-solving skills.\nWorking knowledge of Cadence Virtuoso and Spectre. \nMust be highly focused and remain committed towards project goals. \nGood team player with an attitude and thirst for continuous learning.\n\nQualifications\nExperience and Qualification \n3-5 years of analog design experience with Bachelors in Electrical or Electronics Engineering.\nDesign analog blocks and IPs for precision DAC products in High-voltage, precision process nodes like HPA9.\nPrior experience of designing and simulating (one or more) analog IPs like band-gap reference, DAC, amplifier, oscillator, comparator, power-management blocks like POR, BOR is required.\n \nAnalog Design Engineer for DCC/DAC team\nDesign analog blocks and IPs for precision DAC products in High-voltage, precision process nodes like HPA9.\nPrior experience of designing and simulating (one or more) analog IPs like band-gap reference, DAC, amplifier, oscillator, comparator, power-management blocks like POR, BOR is required.\nShould have handled post layout parasitic back-annotation in addition to design.\nStrong understanding of analog concepts. Strong analytical and problem-solving skills.\nWorking knowledge of Cadence Virtuoso and Spectre. \nMust be highly focused and remain committed towards project goals. \nGood team player with an attitude and thirst for continuous learning.\nExperience and Qualification \n3-5 years of analog design experience.\nBachelors / Masters degree in Electrical / Electronics Engineering.\n \nWhy TI?\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours.  Meet the people of TI\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "CAD Layout Design Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-02-13", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/CAD-Layout-Design-Engineer_JR2013307", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nWe are now looking for a CAD Layout Design Engineer!\n\nWhat you'll be doing:\nYou will be part of the groundbreaking \"Layout Methodology\" team with a charter to speed up layout creation, productivity and improve time to market of Nvidia digital IP like SRAM layouts and other custom Analog layout blocks.\nBe the first to conduct an in-depth study of new technology and enable the rest of the design teams to seamlessly start off on new/advanced layout technology.\nResponsible for creating digital IP to enable layout work in new technology: PCELL creation, SRAM leaf cells, Productivity Scripts.\nCoordinate analysis of new technology and translating into guidelines for EMIR, DFM, SRAM layout guidelines etc.\nInvestigate next generation tools for layout creation.\nInvestigate the applications of Machine Learning / Deep Learning / LLM techniques for layout creation.\n\nWhat we need to see:\nBE/M-Tech in Electrical & Electronics or equivalent experience.\n5+ years of experience.\nProven project cycle and tape out experience in SRAM/Analog layout design.\nExperience in advanced technology nodes like 5,3 or 2 nanometers is a must.\nSolid proficiency / expertise in the Cadence SKILL language is a requirement for this job.\nExperience with PCELL development is a big requirement.\nSolid scripting skills in Python, Perl, Shell is a requirement.\nGood social skills and be an excellent teammate.\nExcellent presentation and influencing skills and ability to communicate new ideas/tools to other groups.\n\nWe are an equal opportunity employer and value diversity at our company. With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us and, due to unprecedented growth, our elite engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you.", "jd_status": "stored"}, {"title": "Digital Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-02-13", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25002182", "is_hardware": true, "platform": "oracle", "jd_text": "Texas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world’s brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We’re committed to building a better future – from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. Put your talent to work with us – change the world, love your job! \n\nAre you looking for a career at one of the leading semiconductor companies in the world. Texas Instruments (TI) is looking for a Digital Design Engineer to join the team of enthusiastic engineers who develops highly complex mixed signal devices for audio applications with industry leading performance. These audio products are truly mixed-signal devices with highly integrated digital circuits such as a DSP core for digital filters and audio signal processing blocks, hardware processing blocks, analog controllers, various serial interfaces and  digital blocks like clock-generation, registers map, Fault handlers & Interrupts etc. \n\nThis is a great opportunity to be part of an established team that’s continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electronics and industrial markets.\n\n \n\nWhat can you expect to learn in this role/Opportunity?\n\nTo work with the best experts in the industry.\n\nTo develop capability to work effectively in a technically challenging fast-paced and rapidly changing environment.\n\nTo innovate on core technology in design methodologies & influence decisions that have wide business impact across many products & teams.\n\nTo work on cutting edge industry leading products.\n\nTo learn overall product development Process and directly influence the features, differentiation & quality of the product.\n\nTo learn and develop business insights, drive open discussions with business & technology leaders and drive decisions impacting product & technology execution.\n\nTo build strong, influential relationships with domain experts.\n\nTo develop good communication, interpersonal skills while interacting with worldwide cross functional experts.\n\nTo learn identifying risks across domains and adapt to support changing priorities.\n\nTo present analysis and conclusions to internal customers and business leaders in a comprehensive and effective manner.\n\nTo work closely with cross-domain experts other engineers and interns.\n\nQualifications\nBasic Qualifications: Bachelor's/Master's Degree in EE/ECE\n\nMinimum Requirements:\n\nBachelor’s degree in Electrical/Electronics Engineering.\n\n2-5 years of Digital Design experience.\n\nBasic Requirement:\n\nStrong digital design fundamentals and basic electrical/electronic engineering concepts.\n\nExperience in building RTL micro architectures development.\n\nHands on experience in RTL coding.\n\nExperience with Verilog/VHDL/System Verilog language.\n\nShould be good knowledge on lint, CDC, RDC, constraint development, synthesis.\n\nGood understanding of digital timing analysis. \n\nExpert in using simulation tools (preferably Cadence).\n\nBasic scripting knowledge using shell/python/perl is preferred. \n\nKnowledge of audio signal chain, I2C, ASI/TDM, memory architecture and FPGA is preferred.\n\nExcellent debugging and problem-solving skill.\n\nGood communication, presentation skills and teamwork.\n\nPrimary Responsibilities:\n\nDesign and Development of digital logic circuits including signal chain, clocking circuits, fault & interrupt handler, memory management and FPGA.\n\nDetailed documentation preparation and knowledge sharing of design architecture and implementation with other domains along with conducting Arch and design Reviews\n\nWork with analog and firmware design domains on integration of system level specification. \n\nWork closely with other design and systems teams to review/close spec gaps and design bugs, as they arise. \n\nHandle Design QCs like lint, CDC, RDC\n\nDeveloping constraint development and synthesis. \n\nSupport physical design team and work closely on timing closure.\n\nSupport DV and silicon validation team with testplan support, design debugs, root cause analysis and workaround.\n\nReview verification coverage and sign off on waivers. \n\nInnovate & drive new and improved methodologies where needed, work with the EDA team to upgrade tools and flows. \n\nConducting design reviews and creating the necessary design and product documentation. \n\nInteracting with Test/Silicon Validation/Application Engineering team to ensure successful use of products and support customer applications debug/analysis.\n\nExcellent teamwork, adapting to situations and ability to guide, help other team members.\n\nCommunication of design status, issues, and concerns.\n\nPreferred Skills:\n\nDemonstrated strong analytical and problem-solving skills.\n\nEffective communication skills to interact with all stakeholders.\n\nAbility to work in teams and collaborate effectively with people in different functions.\n\nStrong time management skills that enable on-time project delivery.\n\nAbility to work effectively in a fast-paced and rapidly changing environment.\n\nAbility to take the initiative and drive for results.\n\nAbility to build strong, influential relationships with cross-functional teams.\n\nAdded Advantage:\n\nExperience/know-how in Physical design concepts.\n\nExperience in audio signal processing and understanding of audio systems/applications. \n\nExperience in silicon debug along with silicon validation team.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Software Engineering Manager", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-02-13", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009055", "is_hardware": true, "platform": "oracle", "jd_text": "About the Role\n\n \n\nWe are looking for an Audio Algorithm Development Manager to lead the design and deployment of high-performance audio algorithms for next-generation of audio enabled multimedia  platforms. This role combines audio/DSP expertise with people leadership, owning audio algorithm development from concept and modeling through validation and product release.\n\n \n\nYou will work at the heart of audio solutions balancing audio quality, latency, power, and compute constraints, while collaborating closely with hardware, firmware, and product teams.\n\n \n\n⸻\n\n \n\nKey Responsibilities\n\n \n\nTechnical Leadership\n\n•          Lead development of audio algorithms including (but not limited to):\n\n•          Equalization, Dynamic Range Control (DRC), loudness management\n\n•          Speaker protection\n\n•          Spatial audio, stereo widening, crosstalk cancellation\n\n•          Noise suppression\n\n•          Psychoacoustic tuning and perceptual optimization\n\n•          Drive algorithm performance under real-time, low-power, and fixed-point constraints.\n\n•          Guide modeling, simulation, and objective/perceptual evaluation of audio quality.\n\n•          Review and approve algorithm architectures, trade-offs, and optimizations.\n\n \n\n⸻\n\n \n\nTeam & People Management\n\n•          Build, manage, and mentor a team of audio algorithm engineers.\n\n•          Set technical direction and enforce best practices in DSP design and implementation.\n\n•          Conduct design reviews, code reviews, and performance evaluations.\n\n•          Support career growth and technical depth within the team.\n\n \n\n⸻\n\n \n\nCross-Functional Collaboration\n\n•          Work closely with architects, hardware designers, firmware teams, and silicon validation.\n\n•          Collaborate with product management and OEM partners on audio requirements and tuning targets.\n\n•          Support post-silicon bring-up, debugging, and field issue resolution.\n\n \n\n \n\nExecution & Delivery\n\n•          Own audio algorithm roadmaps, schedules, and risk assessments.\n\n•          Ensure on-time delivery of production-ready audio algorithms.\n\n•          Drive documentation, IP reuse, and scalability across product generations.\n\n \n\nWhy Join Us\n\n•          Lead audio innovation that ships in millions of consumer devices.\n\n•          Work at the intersection of acoustics, DSP, and silicon.\n\n•          Influence product direction from early architecture to final tuning.\n\n•          Collaborative, engineering-driven culture with strong growth opportunities\n\nQualifications\nRequired Qualifications\n\n•          Bachelor’s or Master’s degree in Electrical Engineering, Signal Processing, Acoustics, or related field.\n\n•          8+ years of experience in audio algorithm or DSP development for embedded or semiconductor systems.\n\n•          2+ years of experience in technical leadership or people management.\n\n•          Strong foundation in digital signal processing and audio fundamentals.\n\n•          Hands-on experience with fixed-point implementation and real-time constraints.\n\n•          Proficiency with MATLAB, Python, and C/C++ for algorithm development and validation.\n\n \n\n⸻\n\n \n\nPreferred Qualifications\n\n•          PhD / Masters in Audio DSP, Acoustics, or related discipline.\n\n•          Experience with mobile, laptop, wearable, automotive, or smart speaker audio systems.\n\n•          Familiarity with objective and subjective audio evaluation methods.\n\n•          Experience with SoC audio pipelines, DSP cores, or hardware accelerators.\n\n•          Exposure to audio interfaces like I2S, TDM, Soundwire, Slimbus etc.\n\n \n\n⸻\n\n \n\nKey Skills\n\n•          Audio DSP & psychoacoustics\n\n•          Algorithm optimization under power and memory constraints\n\n•          Fixed-point and real-time system design\n\n•          Technical leadership and mentoring\n\n•          Cross-functional communication\n\n•          Audio quality tuning and validation\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Physical Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-02-13", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25009023", "is_hardware": true, "platform": "oracle", "jd_text": "Texas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world’s brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We’re committed to building a better future – from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. Put your talent to work with us – change the world, love your job! \n\nAre you looking for a career at one of the leading semiconductor companies in the world. Texas Instruments (TI) is looking for a Digital Design Engineer to join the team of enthusiastic engineers who develops highly complex mixed signal devices for audio applications with industry leading performance. These audio products are truly mixed-signal devices with highly integrated digital circuits such as a DSP core for digital filters and audio signal processing blocks, hardware processing blocks, analog controllers, various serial interfaces and  digital blocks like clock-generation, registers map, Fault handlers & Interrupts etc. \n\nThis is a great opportunity to be part of an established team that’s continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electronics and industrial markets.\n\n \n\nWhat can you expect to learn in this role/Opportunity?\n\nTo work with the best experts in the industry.\n\nTo develop capability to work effectively in a technically challenging fast-paced and rapidly changing environment.\n\nTo innovate on core technology in design methodologies & influence decisions that have wide business impact across many products & teams.\n\nTo work on cutting edge industry leading products.\n\nTo learn overall product development Process and directly influence the features, differentiation & quality of the product.\n\nTo learn and develop business insights, drive open discussions with business & technology leaders and drive decisions impacting product & technology execution.\n\nTo build strong, influential relationships with domain experts.\n\nTo develop good communication, interpersonal skills while interacting with worldwide cross functional experts.\n\nTo learn identifying risks across domains and adapt to support changing priorities.\n\nTo present analysis and conclusions to internal customers and business leaders in a comprehensive and effective manner.\n\nTo work closely with cross-domain experts other engineers and interns.", "jd_status": "source_unavailable"}, {"title": "Staff Test Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-02-11T05:26:07.650000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000108685515-staff-test-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Renesas’ Analog and Connectivity Business Unit (A&C) is seeking an experienced Test Engineer to join our team. This role offers a unique and exciting opportunity to work on the development of state-of-the-art Memory Interface Devices. You will be part of a cross-functional team, driving the product from conception to volume production.\nKey Responsibilities:\nDevelop test programs for characterization, production, and wafer sort using mFlex and Advantest 93K platform.\nDesign test hardware for PMIC, Temp Sensor and I3C applications.\nParticipate in testability reviews with DFT/DFM teams to enhance yield and test methodologies.\nImplement best practices for robust test solutions, including GR&R, HTOL, and Characterization procedures.\n\nTest Engineer with 10+ Years experience developing hardware and software at Wafer Sort and Final Test for PMIC, Temp Sensors and I3C products.\nTest Lead experience preferred.\n10+ Years of experience on mFLEX, Advantest 93K, SPEA or equivalent tester.\nExperience using I2C, I3C, and SPI protocol as well as trim implementations for power IC products\nStrong analytical and problem-solving skills.\nEffective communication and teamwork abilities.\nSelf-starter, motivated, and able to work independently.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nWe have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning.", "jd_status": "stored"}, {"title": "Staff Verification Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-02-11", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2504621", "is_hardware": true, "platform": "oracle", "jd_text": "We are seeking an experienced Staff ASIC Verification Engineer to join our dynamic team. As a verification engineer, you will play a crucial role in ensuring the quality and reliability of our cutting-edge semiconductor designs. If you thrive in a collaborative environment and have a passion for solving complex challenges, this role is for you.\n\nResponsibilities:\n\nVerification Planning and Execution:\n\nDevelop and execute comprehensive verification plans.\n\nClose verification with coverage closure, ensuring high-quality results.\n\nApply standard ASIC verification techniques, including test planning, testbench creation, code and functional coverage, directed and random stimulus generation, and assertions.\n\nTestbench Development:\n\nCreate and enhance testbenches using SystemVerilog (OVM/UVM) or other standard testbench languages.\n\nImplement reusable Verification IP (VIP) components.\n\nCollaborate with third-party VIP providers.\n\nMethodology and Flows:\n\nDemonstrate a solid understanding of ASIC design and verification methodologies.\n\nApply object-oriented programming principles effectively.\n\nImplement constraint random verification methodology.\n\nTechnical Skills:\n\nProficiency in SystemVerilog (OVM/UVM) and other relevant languages (C/C++, Perl, Tcl, Python, Verilog PLI).\n\nFamiliarity with industry standards (e.g., I2C/SPI).\n\nExperience with low-power verification using UPF (Unified Power Format) is a plus.\n\nKnowledge of formal verification techniques is advantageous.\n\nCollaboration and Communication:\n\nWork effectively with internal teams and external customers.\n\nStrong written and verbal communication skills.\n\nInitiative, analytical problem-solving abilities, and adaptability within a diverse team environment.\n\n#LI-RG1\n\nResponsibilities\nResponsibilities:\n\nVerification Planning and Execution:\n\nDevelop and execute comprehensive verification plans.\n\nClose verification with coverage closure, ensuring high-quality results.\n\nApply standard ASIC verification techniques, including test planning, testbench creation, code and functional coverage, directed and random stimulus generation, and assertions.\n\nTestbench Development:\n\nCreate and enhance testbenches using SystemVerilog (OVM/UVM) or other standard testbench languages.\n\nImplement reusable Verification IP (VIP) components.\n\nCollaborate with third-party VIP providers.\n\nMethodology and Flows:\n\nDemonstrate a solid understanding of ASIC design and verification methodologies.\n\nApply object-oriented programming principles effectively.\n\nImplement constraint random verification methodology.\n\nTechnical Skills:\n\nProficiency in SystemVerilog (OVM/UVM) and other relevant languages (C/C++, Perl, Tcl, Python, Verilog PLI).\n\nFamiliarity with industry standards (e.g., I2C/SPI).\n\nExperience with low-power verification using UPF (Unified Power Format) is a plus.\n\nKnowledge of formal verification techniques is advantageous.\n\nCollaboration and Communication:\n\nWork effectively with internal teams and external customers.\n\nStrong written and verbal communication skills.\n\nInitiative, analytical problem-solving abilities, and adaptability within a diverse team environment.\n\n#LI-RG1\n\nQualifications\nBachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or related fields.\n\n7 Years experience in design verification using SV/UVM based test-benches\n\nProven track record in complex ASIC verification.\n\nPassion for solving challenging problems and ensuring product reliability.\n\n#LI-RG1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Staff Analog Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-02-11", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2504580", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Staff Analog design Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following\n\n#LI-VS1", "jd_status": "source_unavailable"}, {"title": "DIR, ANALOG ENGRG; DSGN", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-02-11", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2504593", "is_hardware": true, "platform": "oracle", "jd_text": "Responsibilities: \n\nOnSemi is seeking a Director, Analog design, in Power Management group, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following: \n\n \n\nManage, hire, and mentor a diverse team of experienced and junior Analog IC design engineers \n\nLead, motivate, provide training, and create career growth opportunities for the team \n\nCollaborate with overseas design and systems teams on technical aspects, IP development, sharing of know-how \n\nProvide technical leadership in driving architecture design and circuit design based on high-level specifications \n\nOwn technical outcome of design, verification, implementation, and execution of Power Management ICs with complexities that can span from simple regulators to complex designs, control loops, and digital interfaces \n\nDefine the overall product strategy and roadmap in alignment with the company's objectives, market trends, and customer needs \n\nUnderstand technical aspects, best practices, and design methodologies for power management IC designs \n\nUnderstand project goals, create a realistic schedule and resource plan, track execution schedule to plan, monitor progress, and provide full clarity to the team on the goals and objectives \n\nCollaborate closely with the Systems team to understand system requirements and specification tradeoffs \n\nWork with cross-functional teams on program management, technology, product, test, packaging, and applications teams at all project phases \n\nIdentify, recommend, and implement new systems, tools, processes, and technologies to improve design, reuse organizational processes and decision-making\n\n \n\nQualifications: \n\nSolid track record of releasing complex ICs to market \n\nExtensive knowledge of engineering processes, principles, and methodologies \n\nGoal and outcome-focused with the ability to handle multiple projects within the team \n\nAbility to attract and retain key engineering talent\n\nExperience in simplifying complex problems into smaller problems and solving them as a team \n\nAbility to clearly articulate issues, challenges, and concerns to all levels of management \n\nSolid understanding of various Power Converters such as multiphase converter, current sense amplifier, SAR ADC, Buck, Boost, LDOs, and relevant Analog building blocks \n\nSolid understanding of topologies and architectures for Constant-on-time, Peak, and Valley Current/Voltage Mode control mechanism, Hysteretic, Multi-Phase Controllers, and Smart Power Stages \n\nStrong Analog IC design skills, debug of complex silicon problems using simulations and/or bench testing \n\nFamiliarity with advanced Bipolar, CMOS, and High Voltage BCD technology, Process, Device Physics, Semiconductor Manufacturing processes, and their impact on Analog performance \n\nunderstanding of large power transistor (LDMOS) Design, Layout, and Robustness \n\nProficiency in leading-edge design and verification tools such as Simplis or MATLAB for architectural simulations, Cadence Spectre for schematic capture, simulation, layout, and tape-out \n\nSolid understanding of DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC devices and SiC drivers\n\n \n\n#L1-LK1", "jd_status": "source_unavailable"}, {"title": "Principal Digital Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-02-11", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2504595", "is_hardware": true, "platform": "oracle", "jd_text": "Responsibilities: \n\nOnSemi is seeking a Prin Digital design engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following: \n\n \n\nThe candidate will lead the digital design architecture, digital RTL, low power design, synthesis and timing analysis, and behavioral coding teams for the power management chips as well as executing various tool flows for IP quality control\n\nThe candidate will be able to work as part of a large and focused team of engineers and will be able to collaborate successfully as needed with design architects, digital verification, project management, and digital and analog design teams in multiple worldwide geographies\n\nDrive architecture to micro-architecture to RTL implementation with the refining of features requirements throughout the design process\n\nSupport the bring-up of various features at a system level in various pre-silicon platforms like SOCV, Emulation, FPGA.\n\nKnowledge of development of digital control peripherals, MCU systems\n\nOwn technical outcome of design, verification, implementation, and execution of Power Management ICs with complexities that can span from simple regulators to complex designs, control loops, and digital interfaces \n\nIdentify, recommend, and implement new systems, tools, processes, and technologies to improve design, reuse organizational processes and decision-making\n\nSupport post-silicon validation activities for your designs.\n\nBS in Electrical Engineering or related + 10 years of experience, or MS + 8 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments\n\nThe ideal candidate should have thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status\n\nSolid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF and system Verilog (assertion)\n\nSolid understanding of Verilog, TCL and Perl/Python/XML programming languages\n\nExperience in developing ASIC/Mixed signal ICs for various Power Converters such as multiphase converter, DC-DC PMIC/POL, AC-DC converters, LED drivers \n\nGood understanding of topologies and architectures for Constant-on-time, Peak, and Valley Current/Voltage Mode control mechanism, Hysteretic, Multi-Phase Controllers, and Smart Power Stages\n\nUnderstanding of digital architecture trade-offs for power, performance, and area\n\nMust have good written and verbal cross-functional communication skills\n\nBE/BTech in Electrical Engineering or related + 10 years of experience, or MTech + 8 years of experience\n\n#LI-RT1\n\n \n\nQualifications: \n\nBS in Electrical Engineering or related + 10 years of experience, or MS + 8 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments\n\nThe ideal candidate should have thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status\n\nSolid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF and system Verilog (assertion)\n\nSolid understanding of Verilog, TCL and Perl/Python/XML programming languages\n\nExperience in developing ASIC/Mixed signal ICs for various Power Converters such as multiphase converter, DC-DC PMIC/POL, AC-DC converters, LED drivers \n\nGood understanding of topologies and architectures for Constant-on-time, Peak, and Valley Current/Voltage Mode control mechanism, Hysteretic, Multi-Phase Controllers, and Smart Power Stages\n\nUnderstanding of digital architecture trade-offs for power, performance, and area\n\nMust have good written and verbal cross-functional communication skills\n\nBE/BTech in Electrical Engineering or related + 10 years of experience, or MTech + 8 years of experience", "jd_status": "source_unavailable"}, {"title": "Principal Verification engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-02-11", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2504592", "is_hardware": true, "platform": "oracle", "jd_text": "We are seeking an experienced Principal ASIC/SoC Verification Engineer to join our dynamic and fast‑paced engineering team. In this role, you will be responsible for ensuring the functional correctness, robustness, and overall quality of our cutting‑edge semiconductor and SoC designs. If you thrive in a collaborative environment and enjoy solving complex technical challenges, this opportunity is an excellent fit.\n\nResponsibilities\n\n1. Verification Planning and Execution\n\nDevelop and execute comprehensive SoC/IP‑level verification plans aligned with design specifications and project goals.\n\nDrive verification closure through functional, code, and assertion coverage, ensuring high‑quality deliverables.\n\nApply industry‑standard ASIC/SoC verification techniques including test planning, testbench creation, constrained‑random and directed stimulus, assertions, and coverage‑driven verification.\n\nPerform SoC integration verification, validating interactions across subsystems, interfaces, and power/performance domains.\n\n2. Testbench & Environment Development\n\nArchitect, develop, and enhance SystemVerilog UVM/OVM‑based testbenches for IP and SoC‑level verification.\n\nBuild and integrate reusable Verification IP (VIP) and scalable verification components.\n\nCollaborate with internal teams and third‑party VIP providers to ensure seamless integration and compliance.\n\nDevelop checkers, scoreboards, monitors, and coverage models to support robust verification.\n\n3. Methodology, Flows & Best Practices\n\nDemonstrate strong understanding of ASIC/SoC design and verification methodologies, including constraint‑random verification and object‑oriented programming principles.\n\nContribute to verification methodology improvements, automation, and flow optimization.\n\nEnsure adherence to best practices in UVM architecture, reuse, and maintainability.\n\n4. Advanced Verification Skills\n\nPerform Gate‑Level Simulation (GLS) including SDF annotation, timing verification, and debug of post‑synthesis/post‑layout issues.\n\nExecute power‑aware verification using UPF/CPF, validating power modes, isolation, retention, and sequencing.\n\nDebug complex SoC‑level issues involving multiple clock domains, resets, and power states.\n\nApply formal verification techniques where appropriate to complement simulation‑based verification.\n\n5. Technical Skills\n\nStrong proficiency in SystemVerilog (UVM/OVM) and scripting languages such as Python, Perl, Tcl, C/C++, and Verilog PLI.\n\nFamiliarity with standard protocols and interfaces (e.g., I2C, SPI, UART, AXI/AHB/APB).\n\nExperience with simulation, debug, and coverage tools from major EDA vendors (Synopsys, Cadence, Siemens).\n\nKnowledge of CI/regression automation, version control, and workflow tools is a plus.\n\n6. Collaboration & Communication\n\nWork effectively with design, architecture, DV, validation, and firmware teams to drive verification to completion.\n\nCommunicate technical concepts clearly through documentation, reviews, and cross‑functional discussions.\n\nDemonstrate initiative, strong analytical problem‑solving skills, and adaptability in a diverse team environment.\n\n#LI-RG1", "jd_status": "source_unavailable"}, {"title": "Sr Principal Digital Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-02-11", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2504602", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Sr. Principal Digital design, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products, LED drivers, SiC drivers, smart-Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following: \n\n \n\nWork with different product lines for SoC RTL implementation of power driver digital controls for LED/SiC/smartFET/Efuse application, peripherals like I2C, SPI, LIN, CAN protocols \n\nThe candidate will work on digital design architecture, digital RTL, low power design, synthesis and timing analysis with PD engg, Physical Design (PD) interface for the power management chips \n\nThe candidate will be able to work as part of a large and focused team of engineers and will be able to collaborate successfully as needed with design architects, digital verification, project management, and digital and analog design teams in multiple worldwide geographies\n\nDefine and implement micro-architecture to RTL implementation with the refining of features requirements throughout the design process\n\nSupport the bring-up of various features at a system level in various pre-silicon platforms like SOCV, Emulation, FPGA.\n\nOwn technical outcome of design, verification, implementation, and execution of Power Management ICs with complexities that can span from simple regulators to complex designs, control loops, and digital interfaces  \n\nUnderstand project goals, execute with realistic schedule, report status of progress  and understand clarity of project details and milestones \n\nLead and support Customer issues, Production issues, FW and System development, Failure Analysis\n\nSupport post-silicon validation activities for your designs.\n\n#LI-RT1", "jd_status": "source_unavailable"}, {"title": "Sr Principle Analog Designer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-02-11", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2504583", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Senior Principal Analog design Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including LED drivers, SiC/MOS/IGBT/motor/GAN drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following\n\nMentor junior Analog IC design engineers  \n\nLead multiple analog IPs with IP ownership and responsibility from definition, IP execution to release to manufacturing\n\nAble to resolve complex analog problem and propose and implement the solution\n\nProvide design guidance as needed, developing schedules and monitoring progress throughout the project\n\nEvaluate intermediate and results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout\n\nCollaborate with Design Verification teams during the pre-tapeout phase of a project to ensure completion of all technical tasks before tapeout\n\nWork with systems engineers, application engineers and marketing assisting in the definition of the product to meet customer needs as well as contributing to roadmap formulation and new concept creation\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nProvide technical leadership in driving architecture design and circuit design based on high-level specifications \n\nOwn technical outcomes of design, verification, implementation, and execution of power management ICs with complexities that can span from simple regulators to complex mixed-signal designs and control loops \n\nUnderstand project goals, create a realistic schedule and resource plan, track execution schedule to plan, monitor progress, and provide full clarity to the team on the goals and objectives.\n\n#LI-RG1", "jd_status": "source_unavailable"}, {"title": "Staff Analog Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-02-11", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2504585", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Staff Analog design Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including LED drivers, SiC/MOS/IGBT/motor/GAN drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following\n\nDesign and develop an analog IP block from definition to IP delivery\n\nDesign and simulation at the block/IP level during execution phase, present the block results to review team in timely manner.\n\nWork with and provide guidance to layout engg and monitors the progress of IP block layout\n\nWork with validation, product engineering and test engineering teams to enable them to measure Si performance\n\nOwn technical outcomes of design, verification, implementation, and execution of power management IPs with complexities that can span from simple regulators to complex mixed-signal designs and control loops \n\nAble to plan and execute the work in timely manner aligning with full chip schedule.\n\n#LI-RG1", "jd_status": "source_unavailable"}, {"title": "MTS Analog Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-02-11", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2504586", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Senior MTS Analog design Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including SiC drivers, MOS/IGBT drivers, LED drivers, smart Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following\n\nMentor a diverse team of experienced and junior Analog IC design engineers  \n\nLead an Analog IC design team with product ownership and responsibility from definition to release to manufacturing\n\nMake assignments for team members, providing design guidance as needed, developing schedules and monitoring progress throughout the project\n\nEvaluate intermediate and final results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives\n\nWork with and provide guidance to physical designers and monitors the progress of IC layout\n\nWork with systems engineers, application engineers and marketing assisting in the definition of the product to meet customer needs as well as contributing to roadmap formulation and new concept creation\n\nDefine IP test plan and execution working along with product and test engineer.\n\nDefine and develop IP for both industrial and automotive applications\n\nCollaborate with validation, product engineering and test engineering teams to enable successful transfer to production\n\nInterface and lead discussions with the customer and/or ONsemi field sales/field applications teams to understand customer designs, problems and support as required\n\nActively participate in hiring, developing and evaluating personnel to ensure efficient operation of the organization and growth of the individuals into leader\n\nLead, motivate, provide technical mentorship to the team \n\nCollaborate with overseas design and systems teams on technical aspects, IP development, sharing of know-how \n\nProvide technical leadership in driving architecture design and circuit design based on high-level specifications \n\nOwn technical outcome of design, verification, implementation, and execution of given products with complexities at the SoC level \n\nUnderstand project goals, create a realistic schedule and resource plan, track execution schedule to plan, monitor progress, and provide full clarity to the team on the goals and objectives\n\n#LI-RG1", "jd_status": "source_unavailable"}, {"title": "NAND BM IP RTL Design Engineer", "company": "Samsung", "location": null, "date_posted": "2026-02-09", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/NAND-BM-IP-RTL-Design-Engineer_R114267", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.\nRole and Responsibilities\n\nSamsung Semiconductor India Research (SSIR) is looking for a bright RTL Design Engineer who will be responsible for performing concept and specification study of Samsung Memory (Flash, DRAM).\nProviding high quality RTL design in terms of performance, emulation compatibility and area utilization. Writing detailed design specification and micro architecture documents. Memory team, SSIR Bangalore plays a key role in maintaining this leadership by continuous innovation and applying it to a real life products. We provide the opportunities for you to share and build up your knowledge and expertise, and collaborate to drive innovation forward. At Samsung, you will witness your ideas come to life in new products and solutions that shape the future.\n\nExperience: 6+ years\n\nRTL design using Verilog or System Verilog. Strong RTL coding practices.\nDesign of complex state machines, data paths and arbitration.\nExposure to emulation and emulation compatible RTL design.\nAbility to verify functionality with Unit level TB.\nModelling and performance simulation.\nPrior experience on memory design is a plus.\nKnowledge on area optimization techniques on Emulation platform would be an asset.\nStrong Problem solving and RTL debugging skills\nWriting detailed design specification and micro architecture documents.\nExperience in FPGA based prototypes development\nIndividual should be self-driven, adaptable, flexible, creative, and capable of working independently.\nThe candidate needs to be solution-orientated, quality-driven and focused on timely deliverables\n\nSkills and Qualifications\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "NAND BM IP DV Engineer", "company": "Samsung", "location": null, "date_posted": "2026-02-09", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/NAND-BM-IP-DV-Engineer_R114266", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.\nRole and Responsibilities\n\nSamsung Semiconductor India Research (SSIR) is looking for a bright Design Verification Engineer who will be responsible for developing test environment, test bench development, bus protocol checking, transaction level checking and constraint random verification for Samsung memory. Memory team, SSIR Bangalore plays a key role in maintaining this leadership by continuous innovation and applying it to a real life products. We provide the opportunities for you to share and build up your knowledge and expertise, and collaborate to drive innovation forward. At Samsung, you will witness your ideas come to life in new products and solutions that shape the future.\n\nExperience: 6+ years\n\nExperience in advanced verification languages such as UVM, System Verilog is desirable.\nPrior experience on memory design is a plus.\nCreate new and improve existing verification environment\nApply Universal Verification Methodology (SystemVerilog/UVM) and define verification plan as well as setup verification metrics in digital environments\nExecute tests in these environments on RTL .Good debugging skills and Independent to work\nClosely cooperate with designers and team members.\nGood knowledge of System Verilog, Verilog\nKnow-how of Unix programming languages such as Shell, TCL, Perl/Python etc\nIndividual should be self-driven, adaptable, flexible, creative, and capable of working\nIndependently.\nThe candidate needs to be solution-orientated, quality-driven and focused on timely deliverables.\n\nSkills and Qualifications\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "Principal Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2026-02-06", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Design-Engineer_R52740", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Description\n\nThis is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols.  The successful candidate will be a highly motivated self-starter who is able to work independently and collaboratively to complete tasks within required project timelines with high quality.  The candidate will contribute to digital architecture, digital RTL, low power design, synthesis and timing analysis, and behavioral coding for all IPs in the SerDes physical IP portfolio as well as executing various tool flows for IP quality control.  The candidate will be able to work as part of a small and focused team of engineers and will be able to collaborate successfully as needed with design architects, digital verification, project management, and digital and analog design teams in multiple worldwide geographies. \n\nThis includes but is not limited to: \nDigital architecture that has an understanding of the trade-offs for power, performance, and area\n\nDrive architecture to micro-architecture to RTL implementation with the refining of features/requirements throughout the design process\n\nUnderstanding of synthesis, constraint generation, power management and DFT\n\nUnderstanding of low-power designs and features (power islands, state retention, isolation)\n\nWork with verification team to specify coverage points, testing strategy, corner conditions and stimulus creation\n\nFamiliarity with uC Based subsystems and their architecture\n\nQualifications\n7+ Years’ experience in working with Digital Design and Architecture.\n\nMust have good written and verbal cross-functional communication skills.\n\nProven experience in most of the following:\nDesign Architecture\n\nDesign implementation\n\nEmbedded uC Designs\n\nSynthesis and SDC Creation\n\nScripting of design automation\n\nDebugging verification test cases / SVA’s to cover the design\n\nKnowledge of existing Serial standards such as PCIE, USB, Ethernet, etc.\n\nMust be comfortable interacting across the IPG development team including the ability to work with Mixed-signal, Verification and Analog teams\n\nKnowledge of multiple programming languages. System Verilog, Python, C/C++, etc, are a plus\n\nWorking knowledge of revision control tools such as Perforce, Git, SVN is a plus\n\nEducation Level: Bachelor's Degree (MSEE Preferred)\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Sr Physical Design Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-02-05T11:21:26.316000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000107496476-sr-physical-design-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Be part of the Renesas Memory Group,  we are seeking a smart Junior Physical Design Engineer with strong expertise in RTL-to-GDSII implementation and experience working on complex STA timing closure. The role demands in-depth knowledge of industry-standard EDA tools and a solid grasp of timing closure and physical verification processes.\n\nKey Responsibilities:\nExecute full RTL-to-GDSII flow: Synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off.\nPerform Static Timing Analysis (STA) and ensure timing closure across all design corners.\nExecute EM IR and physical verification checks (LVS, DRC).\nCollaborate closely with cross-functional teams (RTL, STA, Circuit, and DFT).\nHandle complex designs on 12nm and below technology nodes.\n \n\nMust-Have Skills:\n3-5 years of experience in VLSI physical design.\nStrong hands-on experience with tools: Innovus, Genus, Primetime, Calibre.\nPhysical Design Methodologies: Floorplanning, Placement, MultiTap-CTS, Routing, STA.\nTcl, tool scripting\nDDR design knowledge is plus.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nWe have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning.", "jd_status": "stored"}, {"title": "Sr Principal ASIC / RTL Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-02-05", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2504657", "is_hardware": true, "platform": "oracle", "jd_text": "Job Summary\n\nWe are seeking a skilled and motivated Senior Digital IC Design Engineer with over 5 years of experience in digital design and proven expertise in memory IP integration (SRAM, ROM, EEPROM, OTP/NVM). The candidate will play a key role in the development, integration, and verification of memory subsystems in advanced SoC platforms.\n\nKey Responsibilities\n\nOwn and drive the integration of memory IPs into larger digital subsystems and SoC platforms.\n\nCollaborate with memory IP teams to understand interface requirements, timing constraints, and test features.\n\nPerform RTL design, lint, CDC, and synthesis for digital logic blocks interacting with embedded memories.\n\nDefine and execute design verification plans in coordination with the verification team.\n\nInterface with physical design and validation teams to ensure successful implementation and bring-up.\n\nSupport post-silicon debug for memory interface-related issues.\n\nContribute to technical reviews, architecture discussions, and documentation of design flows\n\n#LI-VS1", "jd_status": "source_unavailable"}, {"title": "Senior Signal Integrity Engineer", "company": "Lumilens", "location": "Bengaluru, India", "date_posted": "2026-02-04T21:45:21.770000+00:00", "url": "https://jobs.ashbyhq.com/lumilens/e9285a8f-df83-4680-96be-9aa566d18f94", "is_hardware": true, "platform": "ashby", "jd_text": "Signal Integrity Engineer –1.6T OSFP Board Design\nBengaluru, Karnataka, India / Onsite\nABOUT LUMILENS\nAt Lumilens we are building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new era of computing faster, cooler, and massively more efficient.\nWe’re a well-funded startup backed by Mayfield and led by veterans who’ve built And scaled some of the most transformative technologies in the industry. This isn’t incremental innovation, it’s a ground-floor opportunity to rethink the optical layer from the silicon up. You’ll work alongside a team of world-class engineers solving some ofthe hardest challenges in optics, systems, and scale. Every line of code, every design decision, every breakthrough you help deliver will shape the infrastructure of tomorrow.\nIf you're looking for mission, momentum, and the chance to make an outsized impact jump on the rocket ship. We’re just getting started.\n\nRole Overview\nWe are seeking a senior SI Engineer with 15–20 years of experience to lead board‑level high‑speed electrical design and validation for 1.6T DR8 (200G/lane) OSFP optical modules, including technical leadership across multiple projects and mentoring of the SI team.\n\nKey Responsibilities:\nOwn SI/PI architecture and strategy for 1.6T DR8 OSFP modules: define channel budgets, interface architectures, and design rules for 200G PAM4 lanes from ASIC/DSP to front‑panel.\n\nLead pre‑ and post‑layout SI/PI simulations and reviews (S‑parameters, eye/PAM4 analysis, COM, crosstalk, jitter, PDN impedance) and sign‑off multi‑lane channels on dense module PCBs.\n\nDefine PCB stack‑ups, materials (e.g., ultra‑low‑loss laminates), via and breakout strategies, connector selections, and routing guidelines to meet performance, cost, and manufacturability targets.\n\nDrive cross‑functional technical decisions with hardware, optics, mechanical, FW, and test teams, balancing SI/PI requirements against thermal, mechanical, and system constraints.\n\nLead lab correlation and validation plans: fixture/board design, TDR/VNA/BERT/oscilloscope measurements, de‑embedding strategies, and sign‑off criteria for engineering builds and production.\n\nProvide technical leadership for SI‑related debug on proto and field issues, driving structured root‑cause analysis and design/process improvements across products.\n\nEstablish and maintain company‑wide SI/PI design methodologies, checklists, and documentation for current and future OSFP/QSFP‑class platforms.\n\nMentor and coach junior and mid‑level SI/hardware engineers; review and approve their simulations, reports, and design decisions.\n\nRequired Qualifications:\nB.E/B.Tech or M.E/M.Tech (or equivalent) in Electrical/Electronics Engineering with 15–20 years of relevant high‑speed SI/PI and board‑level design experience.\n\nDeep expertise in very high‑speed SerDes (≥56G, strongly preferred 100G/200G PAM4) including channel modeling, equalization strategies, jitter/crosstalk analysis, and margining.\n\nExtensive hands‑on experience with leading SI/PI tools (e.g., Sigrity, ADS, HFSS, SIwave, HSPICE or equivalents) and scripting/automation for simulation and report generation.\n\nProven track record bringing complex high‑speed hardware or optical modules from concept through production, including multiple design spins and volume manufacturing support.\n\nStrong lab expertise with high‑bandwidth scopes, VNAs, BERTs, and TDRs, including correlation of measurements to simulations and management of external labs/vendors when needed.\n\nDemonstrated ability to lead cross‑functional design reviews, influence architecture, and communicate complex SI/PI concepts clearly to both technical and non‑technical stakeholders.\n\nPreferred Qualifications:\nDirect experience with OSFP/OSFP‑XD/QSFP‑DD optical transceiver designs at 800G/1.6T or similar data‑center interconnects, including familiarity with co‑packaged optics or line‑card interfaces.\n\nKnowledge of IEEE 802.3 DR8/FR8/LR8‑class electrical/optical standards and relevant MSAs/OIF specifications and their implications on channel design and testing.\n\nBackground in EMI/EMC, mechanical and thermal considerations for pluggable modules and how they impact SI/PI trade‑offs.\n\nExperience managing or technically leading small SI/PI or hardware teams, including setting roadmaps, reviewing performance, and guiding career development.\n\nWhat we offer\nCompetitive salary commensurate with experience\n\nComprehensive benefits package including health insurance\n\nProfessional development opportunities and certification support\n\nAccess to cutting-edge technology and cloud platforms\n\nCollaborative work environment with cross-functional teams\n\n*Lumilens is an equal opportunity employer. All qualified applicants will receive consideration without regard to race, color, religion, gender, identity, orientation, veteran status, disability, or any other legally protected status.", "jd_status": "stored"}, {"title": "Signal Integrity Engineer-1.6 OSFP Board Design", "company": "Lumilens", "location": "Bengaluru, India", "date_posted": "2026-02-04T21:34:44.259000+00:00", "url": "https://jobs.ashbyhq.com/lumilens/7798d00c-e4e3-48d6-a43e-065d41bc1c5e", "is_hardware": true, "platform": "ashby", "jd_text": "Signal Integrity Engineer –1.6T OSFP Board Design\nBengaluru, Karnataka, India / Onsite\nABOUT LUMILENS\nAt Lumilens we are building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new era of computing faster, cooler, and massively more efficient.\nWe’re a well-funded startup backed by Mayfield and led by veterans who’ve built And scaled some of the most transformative technologies in the industry. This isn’t incremental innovation, it’s a ground-floor opportunity to rethink the optical layer from the silicon up. You’ll work alongside a team of world-class engineers solving some ofthe hardest challenges in optics, systems, and scale. Every line of code, every design decision, every breakthrough you help deliver will shape the infrastructure of tomorrow.\nIf you're looking for mission, momentum, and the chance to make an outsized impact jump on the rocket ship. We’re just getting started.\nRole Overview\nWe are seeking a Signal Integrity (SI) Engineer with 6–10 years of experience to own board-level high‑speed electrical design for 1.6T DR8 (200G/lane) OSFP optical modules, from pre‑layout simulations through validation and production support.\nKey Responsibilities:\nOwn SI/PI design for 1.6T DR8 OSFP module host and line‑side interfaces, including 200G PAM4 lanes, DSP/ASIC interfaces, retimer/gearbox and connector transitions on the module PCB\n\nPerform pre‑ and post‑layout SI simulations (time and frequency domain) for very high‑speed channels: insertion/return loss, crosstalk, impedance, eye diagrams, COM and bathtub analysis.\n\nDefine PCB stack‑up, materials, via technology, routing rules and design constraints to meet loss budgets and margin targets at 200G per lane within OSFP mechanical constraints.\n\nGenerate clear SI/PI design guidelines for schematic and layout engineers; review schematics and layout (diff‑pair routing, reference transitions, stitching, breakouts) and sign off on SI.\n\nCollaborate closely with optical, mechanical, firmware and test teams on overall 1.6T module architecture, pin‑outs, power partitioning and control interfaces.\n\nPlan and execute lab bring‑up and correlation: TDR, VNA/S‑parameter measurements, eye/PAM4 analysis, jitter decomposition and de‑embedding to validate and refine models.\n\nDrive SI‑related root‑cause debug on proto and production builds, propose design changes and work with manufacturing/NPI to ensure robust, repeatable performance.\n\nContribute to technical documentation: SI test plans, simulation reports, design guidelines, and lessons‑learned for future OSFP generations.\n\nRequired Qualifications:\n⁠B.E/B.Tech or M.E/M.Tech in Electrical/Electronics Engineering (or equivalent) with 6–10 years of experience in high‑speed board‑level design/SI for networking, server or optical module products.\n\nStrong hands‑on experience with pre/post‑layout SI simulations on SerDes links ≥56G, ideally 100G/200G PAM4, using tools such as Sigrity, ADS, HFSS, SIwave, HSPICE or similar.\n\nProven track record defining PCB stack‑ups, materials (e.g., low‑loss laminates), via structures and routing rules for multi‑hundred‑Gbps interfaces on dense form‑factor modules or line cards.\n\nStrong understanding of: transmission lines, S‑parameters, equalization (FFE/DFE/CTLE), jitter, crosstalk, return path design, reference plane design and power distribution networks.\n\nSolid lab skills with high‑bandwidth scopes, VNAs, BERTs and TDRs, including fixture design/de‑embedding and correlation of measurements to simulations.\n\nExperience working with cross‑functional teams (layout, optics, mechanical, FW, test, manufacturing) on complex hardware projects through multiple prototype spins.\n\nGood written and verbal communication to clearly document constraints, justify design decisions and review results with stakeholders.\n\nPreferred Qualifications:\nExperience specifically with OSFP/QSFP‑DD/OSFP‑XD optical transceiver modules at 800G/1.6T or similar data‑center interconnect products.\n\nFamiliarity with high‑speed optical components and interfaces: drivers, TIAs, CDRs/DSPs, laser/photodiode sub‑assemblies, and their electrical constraints.\n\nExposure to relevant standards and ecosystems (e.g., IEEE 802.3 DR8/FR8/LR8‑class interfaces, OIF/OTN, common management interfaces) is a plus.\n\nBasic understanding of EMI/EMC, thermal constraints and mechanical limitations for pluggable modules, and how they interact with SI/PI decisions.\n\nWhat we offer\nCompetitive salary commensurate with experience\n\nComprehensive benefits package including health insurance\n\nProfessional development opportunities and certification support\n\nAccess to cutting-edge technology and cloud platforms\n\nCollaborative work environment with cross-functional teams\n\n*Lumilens is an equal opportunity employer. All qualified applicants will receive consideration without regard to race, color, religion, gender, identity, orientation, veteran status, disability, or any other legally protected status.", "jd_status": "stored"}, {"title": "Lead Design Engineer", "company": "Cadence", "location": "PUNE", "date_posted": "2026-02-04", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/PUNE/Lead-Design-Engineer_R51051-1", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nCadence Tensilica CPU/DSP Processor Team is hiring senior engineers to join our R&D teams in Pune, Bangalore and Noida. This is an amazing opportunity to work in an impactful job at a world leader in computational software, semiconductor design IP, and system verification hardware.  Come be part of this great Processor team where you can make an impact that is visible.   \n\nLead Engineer positions are for one of the two roles: \n(a)    Perform as a member of the Logic Design Team for Xtensa processors. Responsible for the RTL implementation of microprocessor cores, multiprocessor sub-systems and their peripherals. Implement the micro-architecture in Verilog RTL, simulate and debug its functions and run synthesis, place & route and other Electronic Design Automation scripts to meet timing, area, and power goals. Assist with developing test plans; writing functional diagnostics; debugging failures; and analyzing coverage information. Work closely with various Design Verification and Electronic Design Automation teams.\n(b)    Perform as a member of the Design Verification Team for Xtensa processors. Responsible for verification of microprocessor cores, multiprocessor sub-systems and their peripherals. Assist with developing test plans, writing functional assembly diagnostics, UVM/SVA monitors, debugging failures, and analyzing coverage information. Work closely with various RTL Design and Electronic Design Automation teams.\n\nRequired Skills and Experience: \n4+ years of Design or Design Verification experience\nBS/MS in EE/Computer Engineering or a similar major.\nDeep understanding of Digital Design and/or Design Verification fundamentals\nExperience in working as part of a team, or guiding/mentoring junior engineers\nExcellent knowledge of computer architecture/micro-architecture and design verification fundamentals\nExpertise with Verilog and popular EDA simulation, SystemVerilog assertions and functional coverage\nGood working knowledge of scripting languages like Python, Perl, Tcl, Unix shell or similar languages\nKnowledge of technical safety concepts and requirement specifications according to ISO 26262\nProficient with C language and assembly language \nExcellent written and oral communication skills necessary\nExposure to debugging netlist/gate level simulation.\nGeneral understanding of embedded SW.\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Staff Design Verification Engineer", "company": "Analog Devices", "location": "CLOSED-India, Bangalore, Aveda Meta", "date_posted": "2026-02-04", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/CLOSED-India-Bangalore-Aveda-Meta/Staff-Design-Verification-Engineer_R260298", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).\n          \nStaff Design Verification Engineer\n\nAbout the Role\nAs a Staff Design Verification Engineer at Analog Devices, you will provide technical leadership in developing verification strategies for our most complex analog and mixed-signal designs. You'll architect sophisticated verification environments, mentor junior engineers, and collaborate across organizational boundaries to ensure product quality and reliability.\nWorking with limited direction, you'll apply your deep technical expertise to solve critical verification challenges while representing ADI in interactions with key customers and industry partners. This senior position involves significant influence on verification methodology adoption and technical decisions that impact crucial organizational objectives.\n\nKey Responsibilities\nStrategic Leadership: Architect and lead verification strategy for complex digital and mixed-signal designs, acting as a key contributor in critical verification environments\nVerification Architecture: Design and implement sophisticated UVM-based verification environments that ensure comprehensive test coverage and design quality\nTechnical Mentorship: Guide and develop junior engineers, serving as a resource for colleagues with less experience while modeling professional behaviors\nCross-Functional Direction: Coordinate work across organizational lines, collaborating with design teams on verification requirements and sign-off criteria\nProblem Resolution: Lead complex debugging efforts across RTL and gate-level simulations with minimal direction, developing resolutions that require in-depth analysis\nCoverage Closure: Drive functional and code coverage closure using advanced verification methodologies to ensure design accuracy\nPost-Silicon Support: Lead post-silicon validation activities, contributing expertise to address critical issues\nCustomer Representation: Serve as principal customer contact on projects, representing ADI's technical excellence and customer commitment\n\nMust Have Skills\nSystemVerilog and UVM Expertise: Expert-level knowledge of SystemVerilog and Universal Verification Methodology for architecting advanced verification environments for complex designs\nTest Planning and Strategy: Demonstrated ability to develop comprehensive verification plans that drive coverage-driven methodologies and verification closure\nMixed-Signal Verification: Deep understanding of mixed-signal design principles and verification methodologies, with experience implementing sophisticated verification approaches\nDebugging Mastery: Advanced debugging skills across multiple design abstractions, with proven ability to resolve complex verification issues with minimal direction\nEDA Tool Proficiency: Extensive experience with electronic design automation tools (Cadence/Synopsys) and formal verification techniques\nScripting and Automation: Advanced proficiency in Python, Perl, TCL, or Shell scripting for creating sophisticated verification automation frameworks\nTechnical Leadership: Demonstrated ability to influence verification direction, mentor junior engineers, and drive methodology adoption across teams\n\nPreferred Education and Experience\nMS/PhD in Electrical Engineering, Computer Engineering, or related field\n7-10+ years of relevant digital design verification experience, with particular emphasis on mixed-signal verification\n\nWhy You'll Love Working Here\nAt Analog Devices, you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on professional growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world.\nYour expertise will shape the future of technology, and you'll be supported by a culture that values continuous advancement and professional growth. Join us and help create the technologies that bridge the physical and digital worlds, making a tangible difference in how people live, work, and connect.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Power Integrity Engineer", "company": "Lumilens", "location": "Bengaluru, India", "date_posted": "2026-02-03T22:40:58.640000+00:00", "url": "https://jobs.ashbyhq.com/lumilens/dd6bfb9e-43fe-4093-82c6-c4ed1384c55b", "is_hardware": true, "platform": "ashby", "jd_text": "ABOUT LUMILENS\nAt Lumilens we are building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new era of computing faster, cooler, and massively more efficient.\nWe’re a well-funded startup backed by Mayfield and led by veterans who’ve builtAnd scaled some of the most transformative technologies in the industry. This isn’t incremental innovation, it’s a ground-floor opportunity to rethink the optical layer from the silicon up. You’ll work alongside a team of world-class engineers solving some of the hardest challenges in optics, systems, and scale. Every line of code, every design decision, every breakthrough you help deliver will shape the infrastructure of tomorrow.\nIf you're looking for mission, momentum, and the chance to make an outsized impact jump on the rocket ship. We’re just getting started.\n\nRole Overview\nWe are seeking a skilled Power Integrity (PI) Engineer to optimize power distribution networks for OSFP transceiver designs. You will collaborate with cross-functional teams to ensure robust, low-noise power delivery for high-speed silicon photonics, DSPs, and retimers, minimizing PDN impedance and electromagnetic interference in dense 800G+ modules.\n\nKey Responsibilities:\n⁠Perform PI simulations using tools like Ansys SIwave, Keysight ADS, or Cadence Sigrity to model and optimize PDN for OSFP modules, targeting <1mΩ target impedance across 10kHz-100MHz bandwidth.\n\nAnalyze and mitigate power rail decoupling, VRMs, and bypass capacitor placement for multi-rail supplies (0.8V core, 1.8V I/O, 3.3V aux) in high-current OSFP designs up to 100W+.\n\n⁠Collaborate on PCB stackups, via optimization, and plane splitting to reduce simultaneous switching noise (SSN) and ground bounce in 112G PAM4 SerDes environments.\n\nValidate designs through lab measurements using VNA, oscilloscopes, and power analyzers; correlate simulations with hardware prototypes.\n\n⁠Support signal integrity co-optimization, thermal-PD synergy (e.g., integrating TIMs with PDN), and compliance to IEEE 802.3ck/802.3df standards.\n\nDocument PI reports, contribute to design reviews, and mentor junior engineers on best practices for hyperscale OSFP deployments.\n\n⁠Bachelor’s or Master’s in Electrical/Electronics Engineering, with focus on RF/mixed-signal design.\n\nRequired Qualifications:\n⁠Bachelor’s or Master’s in Electrical/Electronics Engineering, with focus on RF/mixed-signal design.\n\n5+ years in PI for high-speed transceivers (OSFP, QSFP-DD, or CDFP preferred); hands-on with 50G+ SerDes.\n\n⁠Proficiency in PI tools (Ansys, HyperLynx, Sigrity) and scripting (Python/MATLAB) for automation.\n\n⁠Strong understanding of power converter topologies (Buck/Buck-Boost), ESL modeling, and EMI/EMC mitigation.\n\n⁠Experience with OSFP mechanical constraints, flex-rigid PCBs, and multi-die integration (e.g., co-packaged optics).\n\nPreferred Skills\n\nFamiliarity with thermal co-simulation (e.g., Ansys Icepak integration) for heat-affected PDN performance.\n\nKnowledge of advanced materials like low-Dk dielectrics or embedded passives for PDN miniaturization.\n\nPrior work on 1.6T OSFP or CPO (Co-Packaged Optics) prototypes.\n\nWhat we offer\nCompetitive salary commensurate with experience\n\nComprehensive benefits package including health insurance\n\nProfessional development opportunities and certification support\n\nAccess to cutting-edge technology and cloud platforms\n\nCollaborative work environment with cross-functional teams\n\n*Lumilens is an equal opportunity employer. All qualified applicants will receive consideration without regard to race, color, religion, gender, identity, orientation, veteran status, disability, or any other legally protected status.", "jd_status": "stored"}, {"title": "Software Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-02-03", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25008954", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\n\n   \n\nThe Radar Firmware group in Bangalore is seeking a talented and experienced Embedded Firmware Engineer to join our team developing cutting-edge, safety-certified firmware for TI's industry-leading mmWave Radar portfolio. This role offers the opportunity to work on mission critical radar systems that power next-generation automotive ADAS/autonomous driving features and transformative industrial sensing on drones and other defense applications.\n\nAs an Embedded Firmware Engineer, some of your key responsibilities include:\n\nDesign and develop ISO 26262 ASIL-D and IEC 61508 SIL-3 compliant embedded firmware for TI's mmWave radar sensors and processors.\n\nImplement real-time radar control firmware for configuration, calibration and high speed data acquisition on TI's mmWave radar sensors.\n\nDevelop firmware using fault-tolerant, fail-safe architectures with comprehensive diagnostic coverage and safety mechanisms.\n\nDevelop customer RF evaluation applications, tools, and RF test firmware for production tests.\n\nDevelop easy-to-use and scalable interface libraries to abstract and simplify customer usage of our sensors.\n\nCollaborate with hardware teams to define firmware-hardware interfaces from a software usage, compatibility, performance, and reuse potential perspectives\n\nDevelop automated testing frameworks and contribute to CI/CD pipelines\n\nSupport customer engagements and provide technical expertise for product integration\n\nSupport safety audits and assessments with TÜV/external certification bodies\n\nQualifications\nMinimum Requirements:\n\nMin 1 year of experience in the domain of embedded systems firmware development. \n\nGood understanding of embedded real time systems firmware programming and engineering principles. \n\nHighly competent with C, assembly language, compilers and linkers.\n\nExperience with bare-metal firmware development.\n\nExperience in scripting languages like python, perl, lua, etc. \n\nExposure to debugging critical embedded software systems issues with JTAG, trace and logic analyzer tools.\n\nExposure to SW development life cycles, unit, integration and qualification of the FW. \n\n \n\nPreferred Qualifications:\n\nExperience with mixed signal analog and digital SOC and ROM firmware development.\n\nExperience with analog circuit FW driver development and calibrations algorithms.\n\nElectronics engineering graduate with firmware development background.\n\nAbility to work effectively in a fast-paced and rapidly changing environment\n\nAbility to take the initiative and drive for results\n\nAbility to work in teams and collaborate effectively with people in different functions\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "DFT STA Lead", "company": "MediaTek", "location": "Bangalore", "date_posted": "2026-02-02T16:00:00+00:00", "url": "https://careers.mediatek.com/en/jobs/MTB120260203000", "is_hardware": true, "platform": "mediatek", "jd_text": "At MediaTek, Candidate will be responsible for end-to-end DFT STA including SDC creation in all modes, SDC sanity checks, CCD, DFT CTS sanity clean up and DFT all mode timing closure both top and block.\nIn long term, individual will build and lead the DFT STA team for quality execution and delivery.", "jd_status": "stored"}, {"title": "Analog Design Engineer - CMOS Image Sensors", "company": "Samsung", "location": null, "date_posted": "2026-01-29", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/Analog-Design-Engineer---CMOS-Image-Sensors_R113773", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nPosition: Analog Design Engineer - CMOS Image Sensors\nTeam: Sensor\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.\nRole and Responsibilities\n\nRoles and Responsibilities\n\nSamsung is a lead provider of CMOS image sensors for mobile and automotive markets. Samsung Semiconductor India R&D (SSIR) is responsible for end-to-end sensor SoC design, firmware and solutions including algorithm optimizations on application processor for mobile products.\nRole and Responsibilities\n\nAt least 6 to 11 years circuit design experience on commercialized chips\n\n. Analog circuit design expertise, such as ADC, DAC, PLL, Charge Pump, LDO and BGR\n\n. Solid leadership experience leading circuit designers, demonstrating excellent engineering judgment.\n\n. Solid knowledge of deep submicron process and circuit design issues, design for manufacturability and reliability issues\n\n. Expertise in chip design flows (EMIR/Noise), tools and overall methodologies, IP integration, library cells, lvs, drc.\n\n. Design experience of Full Chip is good to have\n\n. Should be able to work in a dynamic environment with multiple products & product lines.\n\nExperience – 6 to 11 years\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\nSkills and Qualifications\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "Engagement Applications Engineer, Staff", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2026-01-29", "url": "https://careers.synopsys.com/job/bengaluru/engagement-applications-engineer-staff/44408/91168885744", "is_hardware": true, "platform": "talentbrew", "jd_text": "We Are: \nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. \nYou Are: \nYou are a highly motivated Staff Engagement Applications Engineer with over 4+ years of hands-on experience in synthesis or place and route (P&R). You have a robust understanding of the most advanced CPU/GPU/NPU designs and are eager to work closely with R&D on driving product development and developing advanced HPC reference flow. Your technical expertise allows you to demonstrate differentiated PPA results on the most advanced IP cores to win benchmarking and deploy HPC methodologies to our worldwide key customers to accelerate business growth. You thrive in dynamic environments and possess excellent communication skills, including a strong command of English. Your background in EE/CS, coupled with your experience with EDA tools like DC, ICC2, and Fusion Compiler, makes you an ideal fit for this role. \nWhat You’ll Be Doing: \nCollaborating with R&D teams to drive product development and advanced HPC reference flow development for wide deployment.\nDemonstrating differentiated PPA results on CPU/GPU/NPU designs to showcase our technology's superiority.\nProviding technical support to key global customers to address PPA bottlenecks and design challenges on the most advanced HPC designs.\nAggressively engaging in worldwide critical benchmarks and deployments to ensure the highest quality and performance of designs.\nUtilizing scripting languages such as Perl and Tcl for automation and optimization tasks.\nStaying updated with the latest advancements in ASIC design flow, VLSI, and CAD development to continually improve processes.\nThe Impact You Will Have: \nEnhancing the performance and efficiency of advanced CPU, GPU, and NPU designs.\nDriving innovations that contribute to the success of Synopsys' cutting-edge technologies.\nProviding critical support that helps key customers overcome their PPA challenges.\nContributing to the development of new features that keep Synopsys at the forefront of the industry.\n\nImproving the overall quality and reliability of our products through meticulous design and optimization.\nFostering strong relationships with global customers, reinforcing Synopsys' reputation as a leader in chip design and software security.\nWhat You’ll Need: \nBS/MS in Electrical Engineering or Computer Science with 4+ years of relevant experience.\nHands-on experience with synthesis and place and route (P&R) tools.\nProficiency with EDA tools such as DC, ICC2, and Fusion Compiler.\nKnowledge of advanced placement and routing rules.\nExperience with scripting languages like Perl and Tcl.\nStrong understanding of ASIC design flow, VLSI, and CAD development.\nNever give-up attitude and flexibility in supporting worldwide engagements.\nWho You Are: \nExcellent communicator with strong command of English.\nHighly motivated and self-driven.\nDetail-oriented with a focus on quality and performance.\nA team player who thrives in collaborative environments.\nAdaptable and eager to learn new technologies and methodologies.\n\nThe Team You’ll Be A Part Of: \nYou will join a dynamic and innovative team focused on developing and optimizing advanced HPC designs. Our team collaborates closely with R&D to drive technological advancements and provide top-tier support to our global customers. We are passionate about pushing the boundaries of what's possible in chip design and software security, and we are looking for like-minded individuals to join us on this exciting journey. \nRewards and Benefits: \nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Staff Digital Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-01-29", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2504486", "is_hardware": true, "platform": "oracle", "jd_text": "Description for Internal Candidates\n \n\n     \n\nJob Description details:\n\n \n\nonsemi (Nasdaq: ON) is driving technology breakthroughs that deliver on the promise of a sustainable future focusing on the automotive and industrial markets. The intelligent sensor group, ISG, focuses on image and time of flight sensors. Our sensors are improving people’s lives through improved safety and automation where our products are used in imaging for information applications like scanning, factory automation, smart office, intelligent appliances, and safety/autonomous systems for automotive. We are market leaders in sensors for automotive and machine vision.\n\n \n\nResponsibilities\n\nWe are looking for engineers to join our team working on some of our most innovative and successful products.\n\n \n\nWhat you would work on\n\nMicro architect, implement and verify the digital processing blocks which are part of a CMOS Image Sensor.\n\nInteract with multiple cross functional teams on requirements and deliverables.\n\n \n\n \n\n#LI-RT1\n\n \n\n \n\n \n\n \n\n \n\n        \n\n \n\n          \n\n \n\n        \n\n         \n\n \n\n   \n\nResponsibilities for Internal Candidates\n \n\n     \n\nWhat you need\n\nBE/ME in electronics or related technical field.\n\nAt least 6 years of relevant experience in semiconductor product development.\n\nExperience going through full ASIC development cycle including concept, specification, design, verification and documentation.\n\nExperience in working on data path elements, control logic, design for synthesis, multi clock domain designs, low power design techniques and behavioural modelling.\n\nKnowledge of System Verilog and scripting and familiarity with C modelling.\n\nShould have good analytical skills for debug work needed during verification.\n\nGood written and verbal communication skills.\n\n#LI-RT1\n\n   \n\nQualifications for Internal Candidates", "jd_status": "source_unavailable"}, {"title": "Staff Physical Design Engineer", "company": "Analog Devices", "location": "CLOSED-India, Bangalore, Aveda Meta", "date_posted": "2026-01-27", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/CLOSED-India-Bangalore-Aveda-Meta/Staff-Physical-Design-Engineer_R260294", "is_hardware": true, "platform": "workday", "jd_text": "About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).\n          \nRole Overview\nThe Staff Physical Design Engineer is role which combines deep hands-on implementation expertise with technical leadership. This role owns complex block- and/or top-level physical design for advanced-node SoCs and leads a small group of engineers to achieve high-quality, on-time delivery.\n\nKey Responsibilities\nTechnical Ownership\n\nOwn end-to-end physical implementation (floorplanning, power planning, placement, CTS, routing, ECO) for complex blocks or subsystems across advanced technology nodes (e.g., 22nm, 16nm, 7nm, 5nm, 4nm).\nDrive timing closure, congestion resolution, IR/EM, signal integrity, and physical verification (DRC/LVS/antenna) to meet PPA and quality targets.\nDefine and refine hierarchical PNR strategies, IO ring/PG structures, and integration guidelines for large SoCs.\nPerform in-depth analysis and debug of tool issues, timing failures, and physical design anomalies; propose robust, scalable solutions.\n\nMethodology and Automation\n\nDevelop, maintain, and enhance physical design methodologies, scripts, and flows (e.g., for PDN, PG, clock structure, exception handling, signoff automation).\nProactively identify opportunities for flow improvements and standardization to reduce turnaround time and error rates.\nEvaluate EDA tool features and drive best practices in collaboration with CAD/enablement teams.\n\nTechnical Leadership & Team Enablement\n\nProvide technical direction to a small group of physical design engineers, including task breakdown, priority setting, and quality expectations.\nMentor junior engineers and NCGs in PNR, STA and debug practices to build a strong second tier of technical capability.\nReview floorplans, constraints, and implementation choices from team members, giving clear, actionable feedback.\nAct as a go-to technical reference within the PD team.\n\nCross-Functional Collaboration\n\nWork closely with RTL design, STA, DFT, CAD, and packaging teams to converge on implementation-friendly architectures and constraints.\nCommunicate risks, options, and trade-offs clearly to project leads and managers, and help shape mitigation plans.\nParticipate in design reviews and signoff reviews, representing physical design status, risks, and recommendations.\n\nRequired Qualifications\n\nStrong experience in physical design implementation for complex digital SoCs, typically 8–12+ years in physical design or equivalent level of mastery.\nProven hands-on expertise with industry-standard PNR and signoff tools (e.g., Cadence Innovus, Synopsys ICC2, Tempus/PrimeTime, RedHawk, Voltus, etc.).\nDemonstrated success in closing challenging blocks/subsystems on advanced nodes (timing-, IR-, and congestion-critical designs).\nSolid understanding of:\nFloorplanning and partitioning strategies\nPower grid and PDN methodology (including IR/EM mitigation)\nAdvanced clock tree/clock mesh design and constraints\nSTA constraints (modes/corners, exceptions, derates)\nPhysical verification and reliability checks\n\nLeadership Expectations\n\nStrong problem-solving and debugging mindset, with a bias toward scalable, automated solutions.\nClear, concise communication skills—able to explain complex technical issues and options to different audiences.\nDemonstrated commitment to mentoring, knowledge sharing, and raising the capability of the broader team.\nComfortable operating in a dynamic environment with shifting priorities while maintaining quality and accountability.\n\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.\n\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\n\nJob Req Type: Experienced          \nRequired Travel: Yes, 10% of the time          \nShift Type: 1st Shift/Days", "jd_status": "stored"}, {"title": "Senior Principal Digital IC Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-01-27", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2504436", "is_hardware": true, "platform": "oracle", "jd_text": "Senior Principal Digital IC Design Engineer - Digital Compute Team About Us\n\nAt onsemi, we help improve lives through silicon solutions every day. Our intelligent power and sensing technologies solve the world’s most complex challenges and lead the way in creating a safer, cleaner, and smarter world. Our group develops MCU and DSP systems as well as hardware accelerators that are used in a large variety of different products and markets.\n\nThe Role\n\nWe are expanding the team to India and are looking for a Senior Principal IC Design Engineer with experience in the development of embedded MCU/DSP systems. You will develop and benchmark such systems for a variety of processor cores and consult the product integration teams during the integration of these solutions into semiconductor products.\n\nStrong ability to translate Specifications to Microarchitecture \n\nStrong understanding of core digital design concepts: FSM, Timing diagrams, Combination/ sequential circuits, timing analysis\n\nProficiency in Verilog/Systemverilog\n\nFamiliarity with tools like Lint,  CDC, RDC, DC (Design Compiler)\n\nExperience with standard interfaces:\n\nAPB, AHB, AXI\n\nSPI, I2C, DMA\n\nExperience in MCU/CPU subsystems like ARM processor\n\nExperience is design techniques like\n\nPipelining, Low latency, Power optimization\n\nExperience in Technical documentation for specification, design,  waveform\n\nScripting/Automation languages: \n\nPython, PERL\n\nHave also some experiences in mentoring younger engineers and leading small projects or methodology aspects\n\nWriting specifications based on high-level requirements\n\n \n\nNice to Have: \n\nUnderstanding of DFT, FuSa, Cryptography, Security\n\nLow Power design techniques\n\n#LI-VS1", "jd_status": "source_unavailable"}, {"title": "DFT Engineer (Staff/Senior Staff Level)", "company": "MediaTek", "location": "Bangalore", "date_posted": "2026-01-24T16:00:00+00:00", "url": "https://careers.mediatek.com/en/jobs/MTB120260125000", "is_hardware": true, "platform": "mediatek", "jd_text": "Job Description\nAs a member of DFT engineering team, the candidate will develop methodologies and implement DFT for pre/post-silicon DFT flow and contribute to SOC/Automotive/RISC-V product test quality.\nWork with senior engineers across disciplines (DE, IMP, PE, TE) to meet low cost and high quality DFT deliverables.", "jd_status": "stored"}, {"title": "Senior ASIC Verification Engineer", "company": "NVIDIA", "location": "India, Hyderabad", "date_posted": "2026-01-24", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Hyderabad/Senior-ASIC-Verification-Engineer_JR2011237", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking a passionate, highly motivated, and creative software engineer to be part of its CPU Infrastructure team. We develop methodologies and craft tools to streamline the design/verification of NVIDIA's CPU and SOC designs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have created a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. Come, join us today!\n\nWhat you’ll be doing:\nSet up scalable verification flows for large IP’s  that caters to multiple projects and variants.\n\nImprove continuous integration processes across multiple branches for various IP versions and projects.\n\nContinuous improvement of the speed of build and simulation flows.\n\nSet up automated metrics and dashboards to monitor health of the infrastructure flows and resources.\n\nSet up processes to identify suboptimal areas, and help in improving verification efficiency for the large team of HW engineers.\n\nRemove inefficiency wherever you can find it!\n\nArchitect and develop tools, user interfaces, and reports for chip development, data visualization, resource management, etc.\n\nAnalyze performance bottlenecks, improve data analytics and visualizations of day to day workflows\n\nDebug interesting, complex, and important problems that impact the team\n\nWhat we need to see:\nB.Tech./ M.Tech or equivalent experience with 5+ years of relevant experience\n\nExperience with Linux shell scripting, Makeppfiles, and Perl/Python or equivalent\n\nBackground with ASIC EDA tool flows, simulators, waveform debug tools, and equivalent\n\nExperience with LSF, compute farms, filers, and networks\n\nExperience with setup, configuration, and maintenance of Jenkins build servers\n\nBackground with Web development (HTML/JavaScript/REST) and databases\n\nWays to stand out from the crowd:\nA desire to constantly grow and learn new things. In this team you will constantly be exposed to new technologies and new problems. Your ability to assimilate new ideas and handle tough problems as they arise will be the key to your success.\n\nExposure to RTL design/verification tools (VCS or equivalent simulation tools, debug tools like Verdi) and computer architecture\n\nExposure to source control systems (Perforce/Git) and continuous integration systems (Jenkins)\n\nNVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.", "jd_status": "stored"}, {"title": "Senior Pre-silicon Validation Engineer - Emulation", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-01-22T06:54:00+00:00", "url": "https://global-external-amd.icims.com/jobs/77403/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. MTS SYSTEMS DESIGN ENGINEER    THE ROLE:  We are looking for a dynamic, energetic Lead / Senior Systems Design Engineer to join our growing team. As a key contributor to the success of AMD’s product, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The Systems Design Engineering team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.    THE PERSON:  As a Systems Design Engineer, you will drive balanced, scalable, and automated solutions. In this high visibility position, your software systems engineering expertise will be necessary towards product development, definition, and root cause resolution.    KEY RESPONSIBILITIES:  Driving technical innovation to improve AMD’s capabilities across validation, including tool and script development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives Debugging issues found during the process, bring-up, validation, and production phases of SOC programs  Working with multiple teams, and tracking test execution to make sure all features are validated and optimized on time Working closely with supporting technical teams Engaging in other software/hardware modeling frameworks Leading collaborative approach with multiple teams   PREFERRED EXPERIENCE:  Significant 7+ years of relevant experience in complex SoC verification & Validation Prior hands-on experience with FPGA and/or emulation platforms (Veloce, Palladium, ZEBU, HAPs, Protium) Developing C/C++/Uefi based test content. Validating hardware features for at least 3 or more projects in a pre-silicon environment Debugging failures using waveform viewers, log files and microcode trace dumps Knowledge of low power design emulation/verification and power management fundamentals Knowledge of UEFI, Windows Operating Systems Knowledge of x86 and/or ARM SoC Architecture Knowledge of Memory subsystem, high speed IO peripherals like PCIe, USB, NPU, SoC & IP level Power Management flow, Security protocols. Knowledge of one or more protocols; SPI, DDR, SATA, USB, AXI, PCI, PCIe, MIPI. Good to have Post Silicon Validation Experience on CPU/Power Management/HSIO -PCIe/USB using Embedded C and BIOS Extensive knowledge of system architecture, technical debug, and validation strategy Strong analytical/problem-solving skills and pronounced attention to details Must be a self-starter, and able to independently drive tasks to completion   ACADEMIC CREDENTIALS:  Bachelors or Masters degree in electrical or computer engineering #LI-PK2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior Engineer I - Design", "company": "Microchip", "location": "India - Bangalore", "date_posted": "2026-01-22", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Bangalore/Senior-Engineer-I---Design_R2806-25", "is_hardware": true, "platform": "workday", "jd_text": "Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.\n\nPeople come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.\n\nOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.\n\nVisit our careers page to see what exciting opportunities and company perks await!\n\nJob Description:\n\nThe Wireless Solutions Group is seeking an experienced Senior Engineer I - Design for our next generation high-performance, low-power wireless SoC and attach solutions. In this role, you will be responsible for the design of System-on-Chip (SOC) solutions for wireless applications. You will collaborate closely with cross-functional teams, including verification, analog, validation, and software engineers, to deliver high-quality products. Successful candidate requires strong collaboration across sites and functions, excellent communication, and the ability to thrive in a fast-paced, dynamic environment.\n\nKey Responsibilities:\nContribute to SOC design from concept to tape-out.\nImplement SOC designs according to micro-architecture specifications and design documentation, performing RTL coding, synthesis, timing analysis, and executing the SOC design flow to ensure IC qualification meets required standards.\nCollaborate with verification teams to ensure thorough design verification according to test plans.\nWork with physical design teams to ensure successful integration and implementation.\nParticipate in design reviews to ensure compliance with design standards and project requirements.\nSupport the validation team in qualifying silicon ICs and debugging potential issues.\nContribute to the development and optimization of low-power design techniques and power estimation methodologies.\nInterfacing with external vendors and IP sources to resolve problems.\nAbility to work well in a team and excellent problem solving, verbal and written communication skills.\nWorking with members from international design and implementation teams\n\nRequirements/Qualifications:\n\nBachelor's or master’s degree in computer engineering, electrical engineering, or related field.\nMinimum 7+ years of experience in digital SOC design, with a focus on low-power design.\nProficient in RTL design (Verilog/System Verilog), Low-power design, synthesis, timing constraint (SDC) and timing analysis.\nExperience with ASIC design flow including LINT, Formal, CDC/RDC, power estimations, MBIST/DFT concepts, and low-power design techniques.\nStrong understanding of SOC architecture (ARM/MIPS), bus protocols (AMBA, AXI, etc.), and peripheral IPs (USB, Ethernet, I2C, SPI, etc).\nExperience with Bus Matrix design.\nExperience with script Language such as TCL, Perl, and Python.\nExcellent English reading, writing and verbal communication skills.\nStrong analytical and problem-solving skills.\nWe are looking for candidates who are self-motivators, energetic, and team players.\n\nPreferred Skills and Experience:\nKnowledge of Bluetooth/BLE/Wi-Fi communication theory and standard specifications.\nKnowledge of security features and principles of functional safety–compliant design.\nExperience with verification methodologies (UVM/OVM).\nExperience with validation methodologies, including debugging on FPGA and silicon IC boards.\n\nTravel Time:\n\n0% - 25%\nTo all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.", "jd_status": "stored"}, {"title": "Senior DFT Engineer - Hardware", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-01-22", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-DFT-Engineer---Hardware_JR2011562", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nAs an NVIDIAN, you’ll be immersed in a diverse, inclusive and supportive environment where everyone is inspired to do their life's best work. The complexity of IOs increased many-fold to support the sophisticated speeds that power our product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. IODFX Engineering team at NVIDIA works on groundbreaking innovations involving crafting creative solutions for IO and interconnect testing for some of the industry's most complex semiconductor chips. Join the team and see how you can make a lasting impact on the world.\n\nWhat you'll be doing:\nPOR to Post Silicon Testing of DFX features for high speed IOs. This includes crafting of test features crucial for manufacturing testability of HighSpeed IOs. Architect, Design & Validate these test features with a robust & scalable testplan development at unit-level and SOC/Full Chip level using verification methodologies like UVM and NVIDIA Internal tools. Pre-Silicon Simulation and Debug of Test functionality using standard Industry tools and sign off on Test coverage for various products using standard coverage metrics.\n\nAbility to work on automation, flow development & improvement, coverage metrics, test execution, bug identification/fix and IO-test productization.\n\nSolve complex Test problems in the mixed-signal world and develop a scalable test solution that works across platforms.\n\nWork with powerful Industry-standard tools for Design and verification methodologies along with SV, UVM, Perl, Python and adapt to NVIDIA custom tools/flows.\n\nPartnering closely with our IP teams for design/verification of IOBIST test-logic, Collaborating with Mixed Signal Circuit design teams to understand the analog design components in an IO cell. Collaborate with other DFX teams, coordinate with Post Silicon Test Engineering and Production Engineering teams for productizing quality test at efficient test cost.\n\nWhat we need to see:\nBtech/BE/BS or Mtech/ME/MS in EE/ECE or equivalent experience\n\nSolid Analytical and Problem Solving skills.\n\nGood understanding and Exposure to Logic design, Architecture & Verification\n\nStrong Coding skills in industry standard scripting languages.\n\n3+ yrs of experience in DFT and/or Industry-standard verification flows like constrained random testing, UVM, coverage metrics, profiling tools, X prop, etc. will be plus.\n\nOutstanding written and oral communication skills with the curiosity to learn.\n\nWith competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us and, due to unprecedented growth, our elite engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Staff Digital Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-01-22", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2504470", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Principal Digital Design Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following \n\n#LI-VS1\n\nResponsibilities\nIn this role, you will focus on the following \nOwnership of deploying platform front end tool flow\nCollaborate with cross-functional teams for seamless integration within the overall platform\nThe candidate will work on digital design architecture, digital RTL, low power design, synthesis and timing analysis, Physical Design interface using state of the art RTL2GDS flows for IPs and full chip design \nThe candidate will be able to work as part of a large and focused team of engineers and will be able to collaborate successfully as needed with design architects, digital verification, project management, and digital and analog design teams in multiple worldwide geographies \nImplement micro-architecture to RTL implementation with the refining of features requirements throughout the design process\nWork with methodology development teams to establish, streamline and enhance new and existing development methods, coding process and integration flows\n#LI-VS1\n\nQualifications\nQualifications\nBE in Electrical Engineering or related +12 years of experience, or MS + 10 years of experience in RTL Design/development  \nExperience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments \nThe ideal candidate should have thorough understanding of the end-to-end digital design flow to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status \nSolid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF and system Verilog (assertion) \nSolid understanding of Verilog, TCL and Perl/Python/XML programming languages \nExperience in platform-based development \nExcellent communication skills with a collaborative and team-oriented mindset \nAbility to quickly ramp on new systems and processes\n#LI-VS1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "ENGR PRIN, ANALOG; DSGN", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-01-22", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2504521", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Principal Analog Mixed Signal Verification Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following \n\n \n\nComplete AMS verification ownership of a Product (Define and execute) \n\nHands-on verification of Analog Mixed-Signal simulations. \n\nParticipate with Design team to Enable the Behavioral Modeling requirements  \n\nCollaborate with cross-functional teams for seamless integration within the overall system \n\nCome up with methods to improve efficiency in verification processes. \n\nContribute to the overall success of the team by actively participating in debugging sessions, providing valuable insights, and maintaining effective communication within the team. \n\nWork in methodology development team to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows \n\n \n\n#L1-LK1\n\nQualifications\nBE in Electrical Engineering or related +10 years of experience, or MS + 8 years of experience in AMS verification \n\nExpert-level knowledge in Analog Mixed-Signal simulations \n\nExpert-level modeling of Analog blocks using SV Real Modeling / Verilog-AMS /Verilog-A  \n\nProficient on using design and verification languages: Verilog, System Verilog, and System Verilog Assertions (SVA). \n\n Proficient on Design Verification development process, from specification to test plan, to configurable test bench, drivers and checkers setup, to test suite building to meet functional and code coverage goals  \n\nExperience in verifying Power Management Blocks  \n\nProficiency in scripting languages such as PERL, TCL, Python \n\nExcellent communication skills with a collaborative and team-oriented mindset \n\nAbility to quickly ramp on new systems and processes  \n\n \n\n#L1-LK1\n\nAbout the company\nonsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.\n\nMore details about our company benefits can be found here:\n\nhttps://www.onsemi.com/careers/career-benefits\n\nAbout the organization\nWe are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.", "jd_status": "stored"}, {"title": "Senior Analog Design Engineer", "company": "onsemi", "location": "BENGALURU, Karnataka, IN", "date_posted": "2026-01-22", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2504567", "is_hardware": true, "platform": "oracle", "jd_text": "OnSemi is seeking a Sr Analog design Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including WBG Drivers (SiC, GaN), LED drivers, Switches/efuses/Hotswap controllers, DC-DC PMIC/POL, Multiphase controllers, Dr. MOS for consumer, industrial and automotive applications. In this role, you will focus on the following.\n\n \n\nDesign and develop an analog IP block from definition to IP delivery\n\nDesign and simulation at the block/IP level during execution phase, present the block results to review team in timely manner.\n\nWork with and provide guidance to physical designers and monitors the progress of IP block layout\n\nWork with validation, product engineering and test engineering teams to enable them to measure Si performance\n\nOwn technical outcomes of design, verification, implementation, and execution of power management IPs with complexities that can span from simple regulators to complex mixed-signal designs and control loops \n\nAble to plan and execute the work in timely manner aligning with full chip schedule\n\n#LI-RT1", "jd_status": "source_unavailable"}, {"title": "Senior Custom SOC IP Verification Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2026-01-20", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Custom-SOC-IP-Verification-Engineer_JR2011519", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA needs a Senior Custom SOC/IP Verification Engineer for next-gen solutions. Seeking hard-working individuals to build life-changing custom SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n\nWhat you'll be doing:\nLead ASIC design verification for various processing blocks in a SOC, including planning, execution, Coverage and methodology development.\n\nCollaborate with multiple teams (Architecture, SW/FW, Design, Modeling, Emulation, Post-Silicon Validation) to ensure comprehensive verification plans.\n\nSupport engineering teams in delivering solutions for purpose-built ASICs and collaborate with IP development teams for IP identification, selection, and licensing.\n\nAnalyze SOC and IP architecture, develop verification plans, and establish performance metrics.\n\nWork with partners in a co-development environment during development, debug, and bringup.\n\nPlan tests, achieve coverage closure, and enable customer TB infrastructure.\n\nValidate use cases for power-on and boot requirements.\n\nWhat We Need To See:\nProficient in design verification tools like Synopsys VCS, Cadence Xcelium Simulator, Verdi, JasperGold, and VC Formal.\n\nConsistent track record of first-pass success in ASIC Development.\n\nHolds a B.S. or M.S. degree in Computer Engineering or Electrical Engineering, with 5+ years of experience in ASIC, IP, or SoC design verification.\n\nSkilled in handling mixed language UVM and C++ testbenches, interpreting functional specs, and building comprehensive test plans.\n\nExperienced in developing tools and infrastructure using Perl or Python, with a strong background in AMBA protocols (AXI, ACE, CHI, ATB).\n\nHands-on experience with subsystems in new technologies like ARM CPU, LPDDR, HBM, GPUs, DLA, PCIe, and Network on chip, including performance verification.\n\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Validation/Characterization Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-01-19", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25008799", "is_hardware": true, "platform": "oracle", "jd_text": "Texas Instruments RF Connectivity group is expanding their RF Transceiver Validation Group in Bangalore, India.\n\nThis group develops cutting edge RF Transceiver products (+MCU integrated) for Wireless-LAN (WIFI) and Ultra-Wideband Systems (UWB). The typical transceiver blocks include RF blocks such as LNA, TA, Down-conversion Mixers, Base-band filters, High Speed ADC to send data to the Modem. Reverse Chain namely for Transmitter, starting from DAC, Base-band filter, Up-conversion mixer and Power Amplifier stages to drive the TX Pin. LO system includes Chrystal Oscillator, integer/fractional PLL and LO Distribution systems. Various Calibration modules (AGC, PDET, Gain, Offset, IQMM, etc) to calibrate the Transceiver chain is part of the design. Low Current Mode and Complex Power Management to operate at low LDO input voltage.\n\nThe required skills in the job are:\n\nSystem Level Understanding of Radio Transceiver: Basic operating principles of Transmit & Receiver chains, Modulation and system parameters such as PER/BER/SNR and EVM/RMSEE.\n\nDebug of the RF Transceiver SoC: Fast and Systematic Identification of the issues in the blocks. Observe and identify the root cause. Drive solutions and not just report problems. The debug would involve either Power & Biasing issues, Incorrect register sequence or incorrect values, Board level issues, Semiconductor Process marginalities etc.\n\nRF Measurements: Understanding of each RF, IF and DC measurement. Example in Receiver chain, measurement of Noise Figure & Gain of the chain, Linearity measurements such as P1dB, IIP2, IIP3, IQ gain & Phase error, LO Leakage and DC offsets. DC operating point measurement via Test Mode, DC Voltages and Current Consumption. Similar measurements for TX chain, PLL, Reference Clock.\n\nPCB Board Development:  Development of PCB Schematic and Layout, PCB material selection, stackup, review the design and implement the changes. Working with 3rd party PCB service companies. Familiarity with Altium and Cadence Allegro flows.\n\nTest Automation and Interpretation of Measurements: Person is expected to have proficiency in Coding & Automation of the measurement flows including interfacing of instruments. Processing of the measured data across PVT corners, Visualization and the ability to identify between IC and setup issues. Basic understanding of statistics and sources of error.\n\nInterfaces: Ability to design and program interfaces such as SPI, UART, UCI.\n\nThe candidate is expected to have strong proficiency in 2 or more of the above lists in particular 1-3. A strong team player who is deeply engaged with the Product Development team especially the Radio Design Team.\n\nMinimum expected experience is 6 years. Position is on-site in Bangalore. TI offers attractive compensation and a highly enriching technical environment. Ample opportunities to file Patents and become a Recognized Leader in the respective domain over time.\n\nQualifications\nMinimum requirements:\n\nMinimum education (ie bachelor's degree in electrical engineering)\n\n3 years of experience.\n\nThe required skills in the job are:\n\nSystem Level Understanding of Radio Transceiver: Basic operating principles of Transmit & Receiver chains, Modulation and system parameters such as PER/BER/SNR and EVM/RMSEE.\n\nDebug of the RF Transceiver SoC: Fast and Systematic Identification of the issues in the blocks. Observe and identify the root cause. Drive solutions and not just report problems. The debug would involve either Power & Biasing issues, Incorrect register sequence or incorrect values, Board level issues, Semiconductor Process marginalities etc.\n\nRF Measurements: Understanding of each RF, IF and DC measurement. Example in Receiver chain, measurement of Noise Figure & Gain of the chain, Linearity measurements such as P1dB, IIP2, IIP3, IQ gain & Phase error, LO Leakage and DC offsets. DC operating point measurement via Test Mode, DC Voltages and Current Consumption. Similar measurements for TX chain, PLL, Reference Clock.\n\nPCB Board Development:  Development of PCB Schematic and Layout, PCB material selection, stackup, review the design and implement the changes. Working with 3rd party PCB service companies. Familiarity with Altium and Cadence Allegro flows.\n\nTest Automation and Interpretation of Measurements: Person is expected to have proficiency in Coding & Automation of the measurement flows including interfacing of instruments. Processing of the measured data across PVT corners, Visualization and the ability to identify between IC and setup issues. Basic understanding of statistics and sources of error.\n\nInterfaces: Ability to design and program interfaces such as SPI, UART, UCI.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Validation Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2026-01-19", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25008802", "is_hardware": true, "platform": "oracle", "jd_text": "Texas Instruments RF Connectivity group is expanding their RF Transceiver Validation Group in Bangalore, India.\n\nThis group develops cutting edge RF Transceiver products (+MCU integrated) for Wireless-LAN (WIFI) and Ultra-Wideband Systems (UWB). The typical transceiver blocks include RF blocks such as LNA, TA, Down-conversion Mixers, Base-band filters, High Speed ADC to send data to the Modem. Reverse Chain namely for Transmitter, starting from DAC, Base-band filter, Up-conversion mixer and Power Amplifier stages to drive the TX Pin. LO system includes Chrystal Oscillator, integer/fractional PLL and LO Distribution systems. Various Calibration modules (AGC, PDET, Gain, Offset, IQMM, etc) to calibrate the Transceiver chain is part of the design. Low Current Mode and Complex Power Management to operate at low LDO input voltage.\n\nThe required skills in the job are:\n\nSystem Level Understanding of Radio Transceiver: Basic operating principles of Transmit & Receiver chains, Modulation and system parameters such as PER/BER/SNR and EVM/RMSEE.\n\nDebug of the RF Transceiver SoC: Fast and Systematic Identification of the issues in the blocks. Observe and identify the root cause. Drive solutions and not just report problems. The debug would involve either Power & Biasing issues, Incorrect register sequence or incorrect values, Board level issues, Semiconductor Process marginalities etc.\n\nRF Measurements: Understanding of each RF, IF and DC measurement. Example in Receiver chain, measurement of Noise Figure & Gain of the chain, Linearity measurements such as P1dB, IIP2, IIP3, IQ gain & Phase error, LO Leakage and DC offsets. DC operating point measurement via Test Mode, DC Voltages and Current Consumption. Similar measurements for TX chain, PLL, Reference Clock.\n\nPCB Board Development:  Development of PCB Schematic and Layout, PCB material selection, stackup, review the design and implement the changes. Working with 3rd party PCB service companies. Familiarity with Altium and Cadence Allegro flows.\n\nTest Automation and Interpretation of Measurements: Person is expected to have proficiency in Coding & Automation of the measurement flows including interfacing of instruments. Processing of the measured data across PVT corners, Visualization and the ability to identify between IC and setup issues. Basic understanding of statistics and sources of error.\n\nInterfaces: Ability to design and program interfaces such as SPI, UART, UCI.\n\nThe candidate is expected to have strong proficiency in 2 or more of the above lists in particular 1-3. A strong team player who is deeply engaged with the Product Development team especially the Radio Design Team.\n\nMinimum expected experience is 6 years. Position is on-site in Bangalore. TI offers attractive compensation and a highly enriching technical environment. Ample opportunities to file Patents and become a Recognized Leader in the respective domain over time.", "jd_status": "source_unavailable"}, {"title": "Principal SOC Modeling Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2026-01-16", "url": "https://careers.arm.com/job/bengaluru/principal-soc-modeling-engineer/33099/90647570576", "is_hardware": true, "platform": "talentbrew", "jd_text": "Principal SOC Modeling Engineer \n \nThe Software (CE-SW) group is responsible for developing and improving the software ecosystem around Arm's next generation architectures and systems. This means working with processors and other hardware technology not yet available to the public. You will join a team of Software Engineers who share a passion for leaving their mark on the future of computing.\nWe are looking for software engineers to join the Arm Fast Models team responsible for building high-performance software models of Arm-based systems. These models enable early software development, architecture exploration, and system validation before silicon is available. Members of the modelling team transform hardware designs and specifications into high-performance software representations of hardware systems and components.\nIn this role, you will develop functional models of CPUs, system IP, and complete Arm's reference platforms using C++ and SystemC, working closely with hardware and software teams across Arm.\nIf you are similarly passionate about innovative technologies, then we would love to hear from you!\nKey responsibilities include:\nDevelop, test, and maintain high-performance functional models of Arm system-level IP using C++ and SystemC.\nBuild virtual platforms representing complete Arm’s reference platforms to enable early firmware, OS, and application development before silicon availability.\nCollaborate with hardware architects and RTL designers to understand IP specifications and ensure accurate behavioral modelling.\nWork with open-source and software engineering teams to enable software bring-up on virtual platforms and diagnose system-level issues.\nIntegrate multiple IP models to create scalable system-level simulations.\nParticipate in planning and execution of development roadmaps, working with project managers and global engineering teams.\nRequired Skills and Experience\nMinimum 15-20  years of proven experience.\nStrong C/C++ programming skills with experience in developing large-scale software systems.\nExperience in SoC or IP modelling using C++, SystemC, or TLM.\nGood understanding of computer architecture, microarchitecture, and SoC design concepts.\nExperience with software development practices including debugging, testing, and performance optimization.\nExperience using version control systems such as Git/Gerrit.\nUnderstanding of RISC-based architectures and familiarity with CPU instruction sets.\nAbility to work effectively independently and within distributed global teams.\nStrong interpersonal skills, excellent written and spoken English.\nNice to Have\nExperience with Programmer’s View (PV) modelling and SystemC TLM-2.0 methodologies.\nKnowledge of Arm architecture or Arm system IP (CPU, interconnects, GIC, SMMU, etc.).\nExperience building SoC virtual platforms or full-system simulators.\nBackground in low-level software, firmware, bare-metal programming, or device drivers.\nExperience in supporting to large-scale multi-site software projects.\nWhy Join Us\nWork on modern virtual platforms used across the Arm ecosystem.\nExperience with hardware validation labs and test farms.\nCollaborate with world-class engineers across global Arm teams.\nA clear path for career progression, with scope to evolve into technical leadership or management roles.\n \nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Senior Engineer, Analog Circuit Design ", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2026-01-07T01:02:26.854000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000101974916-senior-engineer-analog-circuit-design-", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Looking for an Engineer with good understanding of basic analog blocks, exposure to power FET technology and high voltage design rules. Candidate must be passionate to learn and lead the evolving topologies in power delivery applications across wide range of market. The candidate will join the 2.6B$ Power Business Unit where he/she will get to work on a wide range of high voltage products like isolated gate driver, HV Gan power stages, LV GaN drivers and power stages, powering the next generation of servers, motor drives solar inverters, EV traction inverters and chargers. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas’s massive Power product portfolio.\nEssential Functions:\nUnderstanding of MOS, Diodes and power FETs (LDMOS) in terms of characteristics, device physics and operating modes is an advantage.\nMust have conceptual understanding of basic analog building blocks like Schmitt Trigger, Level Shifter, Bandgap References, Current Mirrors, Amplifiers, Comparators etc. Knowing common transistor level architectures will be advantageous. \nGood understanding of Analog design concepts like mismatch, noise, gain, offset etc and/or understanding of transistor layout/fabrication process will be advantageous.\nDeep understanding of Statistics and Statistical Distributions e.g. Normal, Uniform etc, Mismatch and Monte Carlo analysis will be advantageous.\nGood understanding of ESD protection circuits for CMOS IC.    \n\nMinimum Requirements:\nBachelor’s or Master’s degree in electrical engineering\n2-5 years of hands-on experience in analog circuit design.\nProven record of executing full-chip execution.\nShould be able to handle full chip execution for devices like gate drivers\nCourses in Analog Circuit Design, Simulation and Verification\nSchematic generation, simulation and verification using modern CAD tools available in public domain e.g. PSPICE\nMust be a natural team player and strive towards fostering a highly creative and productive working environment\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nWe have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning.", "jd_status": "stored"}, {"title": "Manager – Post silicon Validation", "company": "AMD", "location": "Bangalore, India", "date_posted": "2026-01-06T09:33:00+00:00", "url": "https://global-external-amd.icims.com/jobs/77008/login", "is_hardware": true, "platform": "jibe", "jd_text": "WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. MANAGER – Post Silicon SoC Validation and Power/Performance THE ROLE: As Manager-Post Silicon IP Validation in Embedded Group, you will own strategic planning, execution, and leadership for SoC enablement/validation, and power/performance attainment for highly leveraged embedded products. By managing both internal and external deliverables, you will work to ensure all embedded new products are executed and delivered on time. This critical and highly visible role provides an excellent growth opportunity for high performing individuals looking to make a difference and deliver a stand-out experience to customers of AMD.   THE PERSON: A successful candidate will have the ability to establish and drive to goals including plan of record, timelines, budget, scope, performance, and quality. A candidate must be self-motivated, must have a passion for working with a diverse team of creative engineers and senior executives, must be able to deftly manage both internal and external dependencies and ensure all embedded products are delivered on time. This role requires strong technical expertise in semiconductor systems, cross-functional collaboration, people management skills, and proven leadership in managing complex silicon validation programs. The candidate must be a team player with a commitment to meeting deadlines and an aptitude to thrive in a fast paced, multi-tasking environment.   KEY RESPONSIBILITIES: SoC Enablement/Validation/Debug Activities Drive post-silicon IP enablement and functional/electrical validation activities Identify and drive compliance activities with internal central teams and external labs Ensure appropriate validation coverage across the IPs at various temperature range Oversee critical debug and triage towards any Silicon related issues SoC Power and Performance Attainment Drive the teams for the bounding box attainment and ensuring validation for power/performance across PVT conditions Oversee EDC/TDC tuning, CaC validation, and comprehensive power and thermal characterization Leadership & Team Development Build and mentor a high-performing team across the various domains Define team goals, priorities, and meet execution plans aligned with program milestones Plan headcount and allocate resources effectively Collaborate with multi-functional leaders to drive AMD’s success Risk Management & Issue Resolution: Identify and mitigate risks related to feature enablement and validation coverage; ensure timely triage and resolution of blocking issues Lead triage and resolution of blocking issues in coordination with architecture, validation, and debug teams. Stakeholder Communication: Provide crisp progress updates to management and stakeholders. Maintain dashboards on status and issues for projects and deliverables in Confluence and use Jira/MS Project to track all the engineering work PREFERRED EXPERIENCE: Technical background in semiconductor industry with 5 years hands on work in Pre-Silicon activities, 5 years of program management experience and an overall industry experience of 15+ years Good understanding of SoC architecture, RTL integration, and platform-level validation functions Working experience handling Post-Silicon IP level enablement and validation activities Hands-on with debug, triage, and validation procedures for all the interfaces and subsystems Good exposure with resource and budget management for the team Strong mentoring and coaching skills Prior experience managing and leading engineering teams Proven project & program management experience in dynamic and competitive industry Ability to manage complex programs with multiple cross-functional dependencies. Proficiency in planning tools (JIRA, Confluence, Sharepoint, MS Project) and reporting dashboards Ability to structure and execute complex analysis, draw insights, and communicate summary findings/recommendations to senior management. Ability to network, build relationships, and drive effective decision-making across multiple functions and levels within the organization Highly organized, able to prioritize, and juggle multiple work streams to tight deadlines Flexible working schedule to manage global (Asia and North America) program execution teams Strong analytical and problem-solving skills ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Engineering degree with 15+ years of industry experience Excellent communication and inter-personal skills. #LI-NR1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.", "jd_status": "stored"}, {"title": "Senior ASIC Engineer, Switch SoC", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2025-12-23", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-ASIC-Engineer--Switch-SoC_JR2010151", "is_hardware": true, "platform": "workday", "jd_text": "We are currently seeking ASIC Engineer with strong verification fundamentals to work in Switch Silicon group. You'll join a group of hardworking engineers to craft and implement the next generation innovative Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing best high-speed communication devices, delivering the highest throughput and lowest latency! The Networking Chip Design team in India is a new team which is growing at a fast pace.\n\nWhat you'll be doing:\nVerify Switch design's architecture and micro-architecture using advanced methodologies.\n\nBuild reference models, verify and simulate chip blocks/entities according to specifications.\n\nWork closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW.\n\nYou are encouraged to understand the design and implementation, define the verification scope, develop the verification infrastructure, test plans and tests and verify the correctness of the design at SOC level.\n\nUse sophisticated verification methodologies like e-specman, SV-UVM etc.\n\nWhat we need to see:\nBS (or equivalent experience) / MS\n\n4+ years of experience in design verification.\n\nExposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.).\n\nPerl/python scripting language experience desirable.\n\nWays to stand out from the crowd:\nPrior experience of Ethernet or InfiniBand Switches, and/or smartNICs or DPUs, and/or high-speed interconnects.\n\nStrong debugging, problem-solving and analytical skills.\n\nScripting knowledge (Python/Perl/shell).\n\nGood social skills and ability & desire to work as an excellent teammate.\n\nWidely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com\n\nNVIDIA is committed to encouraging a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Design Verification Engineer- Display Interface Protocol Specialist", "company": "MediaTek", "location": "Bangalore", "date_posted": "2025-12-21T16:00:00+00:00", "url": "https://careers.mediatek.com/en/jobs/MTB120251222002", "is_hardware": true, "platform": "mediatek", "jd_text": "We are seeking a highly skilled Design Verification Engineer with more than 5 years of experience, specializing in Display Interface protocols – specifically Display Port (DP/eDP) IP and subsystem verification, to join our innovative team. The ideal candidate will have a strong background in verification methodologies, expertise in System Verilog (SV) programming & UVM Methodology, excellent problem-solving skills, and the ability to work collaboratively in a fast-paced environment.\nKey Responsibilities:\nDevelop and implement comprehensive verification plans for DP/eDP and DP Tunnelling over USB4 IP and Subsystems.\nCreate and maintain testbenches using System Verilog and UVM methodology.\nPerform functional verification of RTL designs, including simulation, debugging, and coverage analysis.\nCollaborate with designers and other cross-functional teams to understand design specifications and requirements for IP and subsystems.\nIdentify and resolve design and verification issues, ensuring high-quality and robust designs.\nGenerate and analyze verification metrics to track progress and ensure coverage goals are met.\nParticipate in design and verification reviews, providing technical expertise and insights.\nStay updated with the latest verification technologies and methodologies and apply them to improve verification efficiency and effectiveness.\nMentor junior verification engineers and provide technical guidance.", "jd_status": "stored"}, {"title": "Digital Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2025-12-19", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25007095", "is_hardware": true, "platform": "oracle", "jd_text": "Job Title : RTL Digital Design Engineer \n\nWe are looking for a passionate RTL Design Engineer with 3–5 years of hands-on experience in digital design for ASICs or SoCs. The candidate will work on cutting-edge semiconductor designs from specification to tape-out, collaborating with cross-functional teams including architecture, verification, and physical design.\nKey Responsibilities: \nRTL Coding and microarchitecture: \nDesign and implementation of digital logic at the RTL level using Verilog, VHDL, System verilog. \nCollaborate with system architects and other cross functional teams to ensure efficient design implementation and its verification. \nOptimize designs for performance, area, and power targets\nContribute to system architecture. \n\nProblem Solving and Quality: \nParticipate in pre-silicon and post-silicon debug. \nContribute to design reviews and improvements. \nWork closely with verification engineers to define test plans.\nCoordinate with physical design teams for timing closure and synthesis constraints.\n\nQualifications\nMinimum Requirements:\nExperience : 3 to 5 years\nExperience with RTL Coding and microarchitecture\nDesign and implementation of digital logic at the RTL level using Verilog, VHDL, System Verilog\nExperience in Verilog, VHDL, System Verilog.\nExperience with System-on-Chip (SoC) architectures specifically with ARM cortex-M cores and AMBA protocols (AHB and APB).\n \nPreferred Skills and Experience:\nProficiency in Verilog, VHDL, System Verilog. \nExperience with System-on-Chip (SoC) architectures specifically with ARM cortex-M cores and AMBA protocols (AHB and APB). \nStrong understanding of digital logic design principles, including finite state machines, combinational and sequential circuits. \nUnderstanding of power saving methodologies, lint, CDC, synthesis processes, timing constraints and analysis, DFT. \nFamiliarity with verification techniques and tools. \nStrong written and verbal communication skills.\n\nAbout the company\nWhy TI?\n\nEngineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.\n\nWe're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI\n\nBenefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here\n\nAbout Texas Instruments\n\n   Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.\n\n     Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.\n\n     If you are interested in this position, please apply to this requisition.\n\nAbout the organization\nTI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.", "jd_status": "stored"}, {"title": "Hardware Engineer, Senior", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2025-12-18T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446715936414", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\n\nQualcomm is developing an exciting new product line for machine learning inference acceleration in the cloud with industry leading performance/watt. As part of this project Qualcomm is seeking an experienced power electronics engineer. The role will cover all aspects of product development including (but not limited to) specifying board level power design, power management products and voltage regulator (VR) selection, development, programming, debug, as well as post-silicon board/SoC test validation and power correlation ensuring system-level performance and power metrics are met.\n\nRequires expertise in one or more of the following engineering disciplines: power electronics (switch mode and linear), power management, high bandwidth/low latency control interfaces, thermal analysis, power distribution networks, PCB layout and construction and industry standard interfaces (e.g. SPI/I2C, AVS, PMBus, etc).\nExpertise with multi-phase buck, boost, intermediate bus converters, LDO regulators as well as eFuse, hot-swap controllers, voltage level-translators, differential amplifiers, voltage and current sensing telemetry.\nUses design and simulation tools such as SIMPLIS, MATLAB, or other common industry VR simulation tools.\nWork with power, system, board architecture, and other cross-organization colleagues to ensure board meets requirements to our SoC.\nProvide schematic/layout guidance to CAD team and conduct design reviews following internal and industry established guidelines.\nHelp drive internal simulation teams to ensure board design meets signal and power integrity (SI/PI) including (but not limited to) impedance analysis, IR drop analysis, transient droop/overshoot for all rails.\nEspecially critical to be able to work with a degree of abstraction and ambiguity.\nDerive, document, and execute board validation test plans pre/post-silicon in our lab. Bring-up and test prototypes utilizing typical lab test equipment (oscilloscopes, multi-meters, electronic loads, passive/active/power probes, T32 debuggers, etc.) Run power stress type workloads to analyze voltage regulator performance.\nDrives triage of problems at the system-level to determine root cause. Analyze test results ensuring sufficient design margins have been achieved. Provide feedback to teams to implement changes as required.  Support SoC, software and firmware teams during development.\nTracks industry technology trends, interacts with other technology teams. Provides technical expertise for next generation initiatives.\n\nPreferred Qualifications: Master’s degree in Electrical Engineering\nEducation Requirements Bachelor’s degree in Electrical Engineering.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Staff DFT Solutions Engineer – Chip Methodology & Automation (CMA)", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2025-12-16", "url": "https://careers.arm.com/job/bengaluru/staff-dft-solutions-engineer-chip-methodology-and-automation-cma/33099/89574732224", "is_hardware": true, "platform": "talentbrew", "jd_text": "About the Team\nThe Chip Methodology & Automation (CMA) team within Arm’s Solutions Engineering organization develops scalable methodologies, flows, and automation that enable efficient deployment of Arm-based SoCs across internal teams, customers, and ecosystem partners.\nThe Role\nWe are seeking an experienced Senior/Lead DFT Solutions Engineer to define, develop, and deploy DFT methodologies and flow solutions for Arm-based SoCs. You will drive alignment across engineering teams, integrate DFT into broader implementation flows, and lead the adoption of scalable, reusable, and automated solutions.\nKey Responsibilities\nDevelop and maintain DFT methodologies, flows, automation, and reference solutions for Arm-based SoCs.\nDrive alignment and integration of DFT flows within end-to-end RTL-to-GDS and silicon enablement methodologies.\nCollaborate with architecture, implementation, CAD, product engineering, customers, and ecosystem partners to ensure successful deployment.\nEvaluate and enable new capabilities with EDA vendors and technology partners.\nLead technical reviews, resolve complex integration challenges, and drive methodology improvements.\nMentor engineers and contribute to the DFT and automation roadmap within CMA.\nRequired Skills & Experience\nStrong industry experience in DFT implementation, methodology development, and flow integration for complex SoCs.\nDeep understanding of scan, compression, ATPG, MBIST/LBIST, JTAG/IEEE 1149.x, IEEE 1687, and hierarchical DFT methodologies.\nExperience integrating DFT into implementation, verification, and signoff flows.\nHands-on expertise with industry-standard DFT EDA tools.\nStrong automation and scripting skills (Python, Tcl, Shell, or similar).\nExcellent debugging, communication, and stakeholder management skills.\nProven ability to influence technical direction across cross-functional teams.\nPreferred Qualifications\nExperience with advanced-node SoC development.\nFamiliarity with chiplet or multi-die architectures.\nExperience developing CAD, methodology, or automation infrastructure.\nKnowledge of automotive, safety, or production test requirements.\nEducation\nBS/MS in Electrical Engineering, Computer Engineering, or related discipline, or equivalent industry experience.\nThis version is closer to the style Arm typically uses internally: concise, outcome-focused, and avoiding detailed technical lists in both responsibilities and skills. The responsibilities describe what the person owns, while the skills describe what they need to know.\n \n#LI-SC2\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Design Verification DDR Lead", "company": "MediaTek", "location": "Bangalore", "date_posted": "2025-12-11T16:00:00+00:00", "url": "https://careers.mediatek.com/en/jobs/MTB120251212000", "is_hardware": true, "platform": "mediatek", "jd_text": "Key Responsibilities:\n1.\tDevelop and implement comprehensive verification plans for HBM4/4e IP and Subsystem.\n2.\tCreate and maintain testbenches, test cases, and verification environments using System verilog and UVM methodology.\n3.\tPerform functional verification of RTL designs, including simulation, debugging, and coverage analysis.\n4.\tCollaborate with design engineers to understand design specifications and requirements for IP and subsystems.\n5.\tIdentify and resolve design and verification issues, ensuring high-quality and robust designs.\n6.\tGenerate and analyze verification metrics to track progress and ensure coverage goals are met.\n7.\tParticipate in design and verification reviews, providing technical expertise and insights.\n8.\tStay updated with the latest verification technologies and methodologies and apply them to improve verification efficiency and effectiveness.\n9.\tMentor junior verification engineers and provide technical guidance.", "jd_status": "stored"}, {"title": "Applications Engineering, Principal Engineer", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2025-12-10", "url": "https://careers.synopsys.com/job/bengaluru/applications-engineering-principal-engineer/44408/98890913520", "is_hardware": true, "platform": "talentbrew", "jd_text": "Senior Applications Engineer – Interface IP\n\nWe Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nYou are a highly motivated, customer-focused engineering professional with a passion for enabling next-generation semiconductor solutions. You thrive in dynamic, collaborative environments and are energized by solving complex technical challenges. With a thorough understanding of ASIC and SoC design flows, you bring hands-on experience in integrating cutting-edge interface IPs, including DDR/LPDDR and PCI Express, into advanced silicon products. Your technical acumen is matched by your communication skills, allowing you to translate intricate engineering concepts to diverse audiences, from internal teams to external customers. You are comfortable working independently and as part of a broader team, demonstrating adaptability, resourcefulness, and a continuous learning mindset.\n\nYou excel in managing multiple priorities, delivering high-quality results within tight deadlines, and approaching new protocols and technologies with curiosity and rigor. Your organizational skills help you keep projects on track, while your customer-centric approach ensures you build trusted relationships. You appreciate opportunities to engage with industry leaders and are enthusiastic about contributing to the success of Synopsys' customers by guiding them through the integration and validation of our world-class Interface IP. If you are seeking a role where your technical expertise and interpersonal skills will have a direct impact on the industry’s most innovative products, this is the perfect opportunity for you.\nWhat You’ll Be Doing:\nProviding technical guidance and hands-on support to customers integrating Synopsys Interface IP (PCI Express and High Speed SerDes design) into their ASIC SoC/systems\nConducting detailed integration reviews at key customer milestones and troubleshooting complex integration challenges throughout the SoC design flow.\nCollaborating with customers to resolve technical issues related to RTL simulation, synthesis, floorplanning, timing closure, and silicon/system bring-up.\nSupporting silicon bring-up and characterization in system environments, ensuring successful deployment of Synopsys IP in customer products.\nDocumenting best practices, developing application notes, and delivering training to enable customer success with Synopsys solutions.\nParticipating in cross-functional teams to relay customer feedback, contribute to product improvements, and stay current with the latest interface protocols and industry standards.\nOccasionally traveling to customer sites for on-site support, integration reviews, and system bring-up activities.\nThe Impact You Will Have:\nAccelerate customer product development cycles by ensuring seamless integration of Synopsys Interface IP into complex SoC designs.\nDrive customer success and satisfaction, resulting in repeat business and long-term partnerships.\nEnhance the quality and reliability of customer silicon by identifying and resolving integration and bring-up challenges.\nInfluence the evolution of Synopsys IP products and solutions through direct feedback and collaboration with R&D teams.\nEstablish Synopsys as a trusted advisor and technical leader in the semiconductor industry.\nContribute to the adoption of the latest industry protocols and standards in real-world applications.\nSupport the delivery of innovative products that power applications from AI and 5G to automotive and consumer electronics.\nWhat You’ll Need:\nMasters with 10+yrs of Industry experience or equivalent\nAt least 10+ years of experience in IP design, ASIC/SoC integration, or related customer-facing engineering roles (exceptional candidates with strong silicon debug and academic background considered).\nSolid understanding of ASIC design flows, including simulation/verification, RTL synthesis, floorplanning, physical design, and timing closure.\nHands-on expertise in integration and validation of High Speed SerDes IPs for PCIe, USB, SATA\nProficient in RTL and gate-level simulation debugging, with familiarity in front-end tools like Design Compiler, Fusion Compiler, and PrimeTime.\nExperience with silicon bring-up and system-level characterization in lab environments.\nDomain knowledge of PCI Express and SERDES and their implementation flows.\nWho You Are:\nExcellent communicator, able to engage effectively with customers and cross-functional teams.\nOrganized and detail-oriented, with a track record of meeting tight schedules and managing multiple projects simultaneously.\nResourceful problem-solver who adapts to new challenges and technologies with enthusiasm.\nCustomer-focused, proactive, and collaborative in approach.\nCommitted to continuous learning and professional growth.\nThe Team You’ll Be A Part Of:\nJoin a dynamic, highly skilled team of Applications Engineers and IP integration specialists at Synopsys Bangalore. The team partners closely with customers across the globe, providing technical expertise and integration support for industry-leading Interface IP. Collaboration, knowledge sharing, and a passion for innovation are at the core of our team culture. Together, we enable our customers to deliver breakthrough semiconductor solutions that set new benchmarks for performance and reliability.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Principal ASIC Digital Verification Engineer- IP Development", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2025-11-27", "url": "https://careers.synopsys.com/job/bengaluru/principal-asic-digital-verification-engineer-ip-development/44408/87859219360", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Title:ASIC Digital Verification- Principal Engineer\nWe Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nYou are a highly experienced ASIC Verification professional, passionate about solving complex engineering challenges and driving technological excellence. With over 15 years of hands-on experience, you bring a deep understanding of functional verification methodologies, particularly in RTL-based IP Cores that power mission-critical applications in industries such as AI, automotive, and cloud infrastructure. Your technical acumen is matched by your ability to architect robust verification environments, make strategic decisions, and lead teams across global locations.\n\nYou thrive in dynamic, fast-paced settings, where collaboration and innovation are at the forefront. Your expertise spans across protocols like DDR, PCIe, AMBA, Ethernet, USB, and MIPI, and you are well-versed in UVM/VMM/OVM methodologies. You are not only proficient in SystemVerilog and object-oriented verification, but you also leverage scripting and programming languages (C/C++, TCL, Perl, Python) to drive productivity and efficiency. Your commitment to quality is unwavering, and you have a keen eye for detail, ensuring coverage-driven verification processes and assertion-based checks are meticulously implemented.\n\nAs a Principal Engineer, you are a natural mentor and technical leader, adept at guiding teams, making architectural decisions, and communicating complex ideas with clarity. You value continuous learning, embrace new challenges, and are motivated by the opportunity to work on cutting-edge IP Cores that define the next generation of smart devices. Your experience with functional safety standards (ISO26262, FMEDA) further strengthens your ability to deliver reliable and secure solutions for Synopsys’ global clientele.\nWhat You’ll Be Doing:\nArchitecting and making strategic decisions on test bench design for IP Core verification.\nDeveloping comprehensive verification plans and specifications based on functional requirements.\nImplementing robust test bench infrastructure and authoring advanced test cases using UVM/VMM/OVM.\nDriving a coverage-driven verification methodology to ensure thorough validation of IP functionality.\nLeading technical aspects of the verification team, mentoring junior engineers and collaborating internationally.\nProviding innovative verification solutions to enhance productivity, performance, and throughput.\nEngaging in assertion-based verification and coverage closure to guarantee high-quality deliverables.\nCollaborating with cross-functional teams on functional safety and compliance standards, such as ISO26262 and FMEDA.\nThe Impact You Will Have:\nEnable Synopsys to deliver world-class, high-performance IP Cores to global customers in AI, automotive, and cloud sectors.\nEnhance the robustness and reliability of verification processes, ensuring top-tier quality for end-customer applications.\nAccelerate time-to-market for Synopsys IP products through optimized verification methodologies and best practices.\nDrive collaboration and knowledge sharing across international teams, fostering a culture of innovation and excellence.\nSupport functional safety initiatives, contributing to the development of secure and compliant solutions for automotive and mission-critical domains.\nInfluence architectural decisions and technical strategies that shape the future of semiconductor verification.\nWhat You’ll Need:\nExtensive hands-on experience (15+ years) in ASIC/RTL verification for complex IP Cores.\nDeep knowledge of protocols such as DDR, PCIe, AMBA (AXI, CHI), SD/eMMC, Ethernet, USB, and MIPI.\nProficiency in verification methodologies: UVM, VMM, OVM; and SystemVerilog-based, object-oriented coding.\nStrong skills in scripting/programming languages: C/C++, TCL, Perl, Python.\nExperience in developing test environments, planning, coverage closure, and assertion-based verification.\nExposure to functional safety standards (ISO26262, FMEDA) is highly advantageous.\nWho You Are:\nInnovative thinker with strong problem-solving skills and attention to detail.\nEffective communicator and collaborator, comfortable working in global, cross-functional teams.\nNatural leader and mentor, capable of guiding technical teams and driving project success.\nSelf-motivated, able to work independently and proactively seek new solutions.\nAdaptable and resilient in fast-paced, challenging environments.\nThe Team You’ll Be A Part Of:\nYou will join the Solutions Group at our Bangalore Design Center, collaborating with a diverse and talented team of architects, designers, and verification engineers across Synopsys’ global sites. The team is focused on developing advanced functional verification solutions for industry-leading IP Cores, supporting a wide range of applications from server farms and AI/machine learning to automotive systems. Together, you will drive innovation, quality, and scalability in every project.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior Verification Engineer - Hardware", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2025-11-21", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer---Hardware_JR2007924", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nWe are now looking for passionate, highly motivated and creative individuals to be part of our automotive verification team. As a verification owner, you will work on projects that will define the next generation of automotive chips and systems. You will get firsthand exposure to high performance CPU and Memory sub-systems, NOC based Interconnect Fabric, High speed IO's and many other leading technologies deployed in our Tegra chips.\n\nWhat you will be doing:\nYou will be responsible for creation of \"state of the art\" UVM based verification test benches and methodologies to verify complex IP's and Sub-systems. You will also get to work on System level verification using C/C++. During the course of a project you would end up driving the following aspects of verification for your unit:\nArchitect the testbenches and craft verification environment using UVM methodology\n\nDefine test plans, tests and verification infrastructure for modules, clusters and system\n\nBuild efficient and reusable bus functional models, monitors, checkers and scoreboards\n\nImplement functional coverage and own verification closure\n\nWork with architects, designers, FPGA and post-silicon teams to ensure that your unit is robust\n\nWhat we need to see:\nYou should be BTech/MTech with 5+ years of experience in verification closure of complex Unit, Sub-system or SOC level verification. If you have experience in at least a few of the following domains, we will have an excellent match for our needs:\nCPU verification, Memory controller verification, Interconnect verification\n\nHigh Speed IO verification (UFS/PCIE/XUSB)\n\n10G/1G Ethernet MAC and Switch\n\nBus protocols (AXI/APB)\n\nSystem functions like Safety, Security, Virtualization and sensor processing\n\nExperience in the latest verification methodologies like UVM/VMM\n\nExposure to industry standard verification tools for simulation and debug is a requirement\n\nExposure to Formal verification would be excellent\n\nGood debugging and analytical skills.\n\nGood interpersonal skills, ability to work as an excellent teammate with excellent communication skills to collaborate with cross-cultural teams and work in a matrix organization\n\nWith highly competitive salaries and a comprehensive benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you're creative and independent, with a genuine real passion for technology, we want to hear from you.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior Verification Engineer - Hardware", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2025-11-21", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer---Hardware_JR2007925-1", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nWe are now looking for passionate, highly motivated and creative individuals to be part of our automotive verification team. As a verification owner, you will work on projects that will define the next generation of automotive chips and systems. You will get firsthand exposure to high performance CPU and Memory sub-systems, NOC based Interconnect Fabric, High speed IO's and many other leading technologies deployed in our Tegra chips.\n\nWhat you will be doing:\nYou will be responsible for creation of \"state of the art\" UVM based verification test benches and methodologies to verify complex IP's and Sub-systems. You will also get to work on System level verification using C/C++. During the course of a project you would end up driving the following aspects of verification for your unit:\nArchitect the testbenches and craft verification environment using UVM methodology\n\nDefine test plans, tests and verification infrastructure for modules, clusters and system\n\nBuild efficient and reusable bus functional models, monitors, checkers and scoreboards\n\nImplement functional coverage and own verification closure\n\nWork with architects, designers, FPGA and post-silicon teams to ensure that your unit is robust\n\nWhat we need to see:\nYou should be BTech/MTech with 5+ years of experience in verification closure of complex Unit, Sub-system or SOC level verification. If you have experience in at least a few of the following domains, we will have an excellent match for our needs:\nCPU verification, Memory controller verification, Interconnect verification\n\nHigh Speed IO verification (UFS/PCIE/XUSB)\n\n10G/1G Ethernet MAC and Switch\n\nBus protocols (AXI/APB)\n\nSystem functions like Safety, Security, Virtualization and sensor processing\n\nExperience in the latest verification methodologies like UVM/VMM\n\nExposure to industry standard verification tools for simulation and debug is a requirement\n\nExposure to Formal verification would be excellent\n\nGood debugging and analytical skills.\n\nGood interpersonal skills, ability to work as an excellent teammate with excellent communication skills to collaborate with cross-cultural teams and work in a matrix organization\n\nWith highly competitive salaries and a comprehensive benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you're creative and independent, with a genuine real passion for technology, we want to hear from you.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Director / Senior Principal AI SoC Validation (Bring-up lead)", "company": "Graphcore", "location": "Bengaluru, India", "date_posted": "2025-11-19T10:42:09-05:00", "url": "https://job-boards.greenhouse.io/graphcore/jobs/8286166002", "is_hardware": true, "platform": "greenhouse", "jd_text": "Graphcore\n\nSenior Principal AI SoC Validation (Bring-up lead)\n\nGraphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  \n\nAs part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing.  \n\nWe are developing the next generation of AI compute, a large-scale system-on-chip (SoC) designed to power future high-performance AI systems. As the SoC Validation Lead, you will be responsible for enabling pre-production software to run reliably on new silicon quickly and efficiently, before showing that the silicon meets the highest standards of quality, reliability and functionality, ready for production deployment.\n\nYou will lead a team delivering post-silicon validation across the full AI SoC, working across silicon, firmware, and platform levels. The role requires a deep technical understanding, strong hands-on debug experience, and the ability to collaborate effectively with hardware, software, and systems engineering teams.\n\nKey responsibilities\n\nDefine and lead post-silicon validation strategy\nDevelop and refine the overall post-silicon validation approach for our AI SoCs, ensuring reliable and timely delivery of validated silicon, architectural correctness, feature robustness, and at-scale system reliability.\n\nDrive cross-domain debug and issue resolution\nLead investigation and resolution of complex issues spanning silicon, firmware, operating systems, and platform interactions. Ensure that fixes are effective and sustainable.\n\nPromote collaboration and shared understanding\nWork closely with design, software, and validation teams to align on quality objectives and debug priorities. Use data-driven insights and clear communication to maintain focus and alignment across teams.\n\nAdvance automation and scalable validation\nEncourage the use of emulation, prototyping, and large-scale validation infrastructure to improve coverage and reduce time to debug.\n\nSupport continuous improvement\nFoster a culture that values learning, transparency, and improvement in validation methods, automation, and analysis.\n\nEngage with leadership and customers\nProvide clear and concise updates on validation progress, risks, and quality indicators to executive teams and key partners. Contribute to product readiness assessments and roadmap decisions.\n\nAbout you\n\nA systems thinker comfortable working across hardware, software, and integration boundaries.\n\nA collaborative leader who builds trust and alignment across diverse teams.\n\nSkilled in technical problem solving and debugging complex post-silicon issues.\n\nA clear communicator who can simplify complexity and support sound decision-making in fast-paced environments.\n\nCommitted to developing people and promoting an inclusive, high-performing team culture.\n\nQualifications\n\nBachelor’s degree in Electronic Engineering or equivalent; Master’s preferred.\n\n15 - 20 years in silicon, system, or platform validation, including 5-10 years in technical leadership.\n\nProven experience leading post-silicon validation and bring-up for complex SoCs (AI, GPU, or CPU).\n\nStrong understanding of SoC architecture, coherency protocols, power management, and interconnects.\n\nExpertise in debug tools, DFT infrastructure, and validation automation frameworks.\n\nProficient in C/C++, Python, and Linux-based environments; experience with large-scale validation clusters is an advantage.\n\nExcellent communication, collaboration, and stakeholder management skills.\n\nWhy Join Us\n\nThis is an opportunity to play a central role in developing an advanced AI compute platform that pushes the boundaries of performance and efficiency. You will be part of a highly skilled and motivated team, working on technology that will have a significant impact across future AI systems.", "jd_status": "stored"}, {"title": "Principal Silicon Verification Engineer - Bengaluru", "company": "Graphcore", "location": "Bengaluru, India", "date_posted": "2025-11-13T02:19:51-05:00", "url": "https://job-boards.greenhouse.io/graphcore/jobs/8288720002", "is_hardware": true, "platform": "greenhouse", "jd_text": "About us \n\nGraphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.    \n\nAs part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. \n\nJob Summary  \nWorking within the Silicon verification team, the silicon verification engineer is responsible for a wide range of tasks within the silicon verification team. This person is responsible for verification activities within Graphcore, helping the silicon team meet the company objectives for quality silicon delivery.  \n\nThe Team \n\nThe verification team sits within the Silicon design team. We are responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon.  \n\nResponsibilities and Duties \n \n\nVerification activities within the verification team \n\nEnsuring good communication between sites \n\nVerification planning, specification and closure of functional coverage \n\nProviding feedback to architects \n\nTest generation and failure diagnosis/triage \n\nContributing to shared verification infrastructure \n\nCandidate Profile \n\nEssential: \n \n\nverification experience in relevant industry \n\nProven leadership and planning skills \n\nBe highly motivated, a self starter, and a team player \n\nAbility to work across teams and programming languages to find root causes of deep and complex issues \n\nAbility to research along with the knowledge to solve complex problems \n\nPresents technical and functional knowledge to design experiments/ projects that contribute to overall direction of team \n\nExercises independent judgment in developing methods, techniques and evaluation criteria for obtaining results \n\nHighly influential on colleagues with ability to explain difficult concepts \n\nExperience of the verification process applied in CPU and/or ASIC environments \n\nSystem Verilog, Python, C++, Linux  \n\n12 – 14 years-experience in engineering background \n\nDesirable \n\nUVM \n\nSVA \n\nAssembly languages \n\nLLVM, GCC \n\nDVCS e.g. Git \n\nSGE or other DRMS \n\nXML and XPath/XSLT \n\nWeb programming – HTML/DOM, Javascript, SQL", "jd_status": "stored"}, {"title": "RTL Design(Turing-AI/ML)-Sr Engineer/Sr Lead", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2025-11-10T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446715378561", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nIn this role\nYou will be interacting closely with the product definition and architecture team.\n\nDeveloping implementation (microarchitecture and coding) strategies to meet quality, and PPAS (Performance Power Area Schedule) goals for Sub-system.\n\nDefine various aspects of the block level design such as block diagram, interfaces, clocking, transaction flow, pipeline, low power etc.\n\nPerform as well as lead a team of engineers on RTL coding for Sub-system/SOC integration, function/performance simulation debug.\n\nDrive Lint/CDC/FV/UPF checks to ensure design quality.\n\nDevelop Assertions as part of white-box testing-coverage.\n\nWork with stakeholders to discuss the right collateral quality and identify solutions/workarounds.\nWork towards delivering with key design collaterals (timing constraints, UPF etc.).\n\nDesired Skillset:\n\nGood understanding of low power microarchitecture techniques and AI/ML systems.\n\nThorough knowledge of Computer system architecture, including design aspects of AI/ML designs.\n\nExperience in high performance design techniques and trade-offs in a Computer microarchitecture.\n\nGood understanding of principals of NoC Design\n\nDefine Performance (Bandwidth, Latency) and Bus transactions sizing based on usecases across Voltage/Frequency corners\n\nWorking with Power and Synthesis teams on usecases, dynamic power and datapath interactions\n\nKnowledge of Verilog / System Verilog. Experience with simulators and waveform debugging tools\n\nWorking with SOC DFT and PD teams as part of collaterals exchanges\n\nKnowledge of logic design principles along with timing and power implications.\n\nPreferred Qualifications:\nMaster's or Bachelor's degree in Electronics or Electrical Engineering or equivalent.\n\nAt least 2+ years of experience working on multiple designs.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Modem design/RTL (Sr Staff)", "company": "Qualcomm", "location": "Bangalore, India", "date_posted": "2025-11-07T00:00:00+00:00", "url": "https://qualcomm.eightfold.ai/careers/job/446715312020", "is_hardware": true, "platform": "eightfold", "jd_text": "Company:\nQualcomm India Private Limited\nJob Area:\nEngineering Group, Engineering Group > Hardware Engineering\nGeneral Summary:\nRoles and Responsibilities\nQualcomm modem team is looking for world-class RTL design engineers looking to work on cutting edge wireless technology, which will be deployed worldwide in our industry leading devices.\nYou will be contributing to and leading a team for RTL design and integration of one or more flagship modem core IPs. Responsibilities include:\nMicroarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification.\n\nRTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals\n\nWorking collaboratively with block designers, verification, architecture, implementation, and post-silicon teams to resolve issues and ensure timely project execution.\n\nCollaborating with cross-functional teams, debugging and identifying issues, providing workarounds, and making recommendations on bug fixes.\n\nLeading and mentoring a team of engineers, providing technical guidance to the team\n\nLeading overall project planning efforts and execution.\n\nSkillset required \nThe candidate must have at least 10 years of front-end ASIC RTL design experience. The candidate must be strong in design micro-architecture and RTL coding (SystemVerilog / Verilog / VHDL).\nExperience in Logic design /micro-architecture / RTL coding is a must.  \n\nMust have hands on experience with SoC design and integration for SoCs. \n\nExperience in Verilog/System-Verilog is a must. \n\nShould have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC.  \n\nOther requirements include:\nHands-on experience with multi-clock designs.\n\nExposure to synthesis and STA.\n\nAwareness of low power and high-speed design.\n\nKnowledge of industry-standard front-end tool flows (lint, CDC, etc.).\n\nStrong critical thinking, problem-solving, and debugging skills.\n\nExcellent leadership, communication and interpersonal skills. Flexible to work with multi-geo teams.\n\nAbility to thrive in a fast-paced, dynamic environment and manage multiple priorities.\n\nMinimum Qualifications:\n•    Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.\n                                                                    OR\nMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.\n                                                                    OR\nPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.\n\nApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).\n\nQualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.\n\nTo all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nIf you would like more information about this role, please contact Qualcomm Careers.", "jd_status": "stored"}, {"title": "Principal Engineer-High Speed Interface Pre-Silicon Validation/Verification", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": "2025-10-30", "url": "https://careers.synopsys.com/job/bengaluru/principal-engineer-high-speed-interface-pre-silicon-validation-verification/44408/87868266560", "is_hardware": true, "platform": "talentbrew", "jd_text": "Job Title:\n * Principal Engineer-High Speed Interface Pre-Silicon Validation/Verification\n \n We Are:\n \n At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\n \n You Are:\n \n You are a driven and insightful Emulation Expert, passionate about pushing the boundaries of what's possible in ASIC digital design. With a deep understanding of IP interfaces--especially PCIe and DDR--you are skilled in leveraging advanced emulation platforms like Zebu to accelerate verification and product development. Your career is marked by a proven ability to deliver robust, production-ready IP through rigorous emulation and verification cycles. You thrive in highly collaborative, matrixed, and international environments, bringing together diverse teams and perspectives to solve complex challenges.\n \n Your hands-on approach and proactive attitude make you a go-to resource for bridging gaps between Emulation IP and Design IP, ensuring seamless integration and verification of both Controller and PHY components. You have a keen eye for detail and are committed to right-first-time development, always ensuring traceability and completeness across verification requirements. You stay ahead of industry trends, standards, and evolving technologies, and are adept at translating these into actionable insights for your teams. As an excellent communicator and natural collaborator, you are comfortable working with multiple stakeholders and driving change within the organization. Your adaptability, resilience, and commitment to continuous learning set you apart as a leader in your field.\n \n What You'll Be Doing:\n \n * Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.\n * Reporting key metrics and driving continuous improvement initiatives in Emulation IP quality and performance.\n * Providing technical leadership and expertise to define requirements for Emulation IP, ensuring its correct implementation and deployment within verification strategies.\n * Staying ahead of evolving industry standards, interpreting future changes, ECNs, and specification errata, and integrating this knowledge into Emulation and Design IP teams.\n * Reviewing and validating test plans for both Emulation IP and Design IP, guaranteeing best-in-class function, feature coverage, and product quality.\n * Collaborating cross-functionally to optimize workflows, standardize methodologies, and ensure compliance with organizational goals.\n * Mentoring and guiding junior engineers, fostering a culture of innovation and continuous improvement.\n \n The Impact You Will Have:\n \n * Enhancing cross-functional collaboration to elevate product quality and end-customer satisfaction.\n * Transforming the approach to Emulation IP usage in validating cutting-edge digital designs and system architectures.\n * Driving innovation by defining and refining requirements for IP product development, particularly in emulation contexts.\n * Championing the adoption of best-in-class verification methodologies across the organization.\n * Standardizing and optimizing verification workflows to boost efficiency, traceability, and compliance.\n * Influencing the next generation of emulation and verification solutions, positioning Synopsys as an industry leader.\n * Accelerating time-to-market for high-performance silicon solutions through advanced emulation strategies.\n \n What You'll Need:\n \n * 8+ years of relevant experience in emulation, verification, or IP product development.\n * Expert-level knowledge of PCIe or DDR interfaces, including protocol and verification strategies.\n * Extensive hands-on experience with Zebu or similar emulation platforms, particularly for IP verification.\n * Demonstrated track record in leading IP product development initiatives with a focus on emulation.\n * Strong background in cross-functional collaboration, with an ability to drive consensus and deliver results.\n * Outstanding communication skills, with the ability to influence and inspire change across diverse teams.\n * Adaptability and comfort working in a fast-paced, matrixed, and international environment.\n \n Who You Are:\n \n * A proactive and collaborative problem-solver with a passion for excellence.\n * Innovative thinker who embraces change and seeks out opportunities for continuous improvement.\n * Strong communicator, able to articulate complex technical concepts to diverse audiences.\n * Resilient and adaptable, thriving in dynamic environments and embracing new challenges.\n * Committed to mentoring others and fostering an inclusive, team-oriented culture.\n \n The Team You'll Be a Part Of:\n \n You will join a dynamic, high-performing engineering team focused on IP development, emulation, and verification at the forefront of semiconductor innovation. Our team is collaborative, cross-functional, and globally distributed, working together to solve complex challenges and deliver industry-leading solutions. You will have the opportunity to collaborate with experts across multiple domains, drive impactful initiatives, and shape the future of digital design and verification at Synopsys.\n \n Rewards and Benefits:\n \n We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.", "jd_status": "stored"}, {"title": "Senior Staff Engineer Verification", "company": "Infineon", "location": "Ahmedabad (India)", "date_posted": "2025-10-29T09:35:17+00:00", "url": "https://jobs.infineon.com/careers/job/563808967680070", "is_hardware": true, "platform": "eightfold", "jd_text": "In depth understanding of ASIC verification concepts and techniques . Ability to architect complex module / sub system / full chip testbenches and build verification infrastructure in SV/UVM.\n\nYour Role\n\nKey responsibilities in your new role:\nVerification of complex SoCs / IPs and provide technical leadership to the team while creating test plans and Verification Infrastructure\nAdopt state of art Verification methods. Develop expertise in multiple areas of verification – Formal/Gate level/Power aware Verification\nDrive Verification closure of complex IPs and SoCs using SV/UVM based methodology\nDeveloping C models for DSP and Verification\nSchedule management and handling cross functional team interactions\nMentoring and guiding the team to keep Verification execution on track.\n\nYour Profile\n\nQualifications and skills to help you succeed:\nEducation: B.E./B.Tech/M.E./M.Tech\nExperience: Bachelor's - 9 to 11 years or Master’s - 8 to 10 years\nIn depth understanding of ASIC verification concepts and techniques. Ability to architect complex module / sub system / full chip testbenches and build verification infrastructure in SV/UVM.\nShould be a good mentor and guide the junior engineers in the team. Experience in ARM based SoC verification covering RTL, Power Aware and Gate level simulations is a plus.\nKnowledge on Ethernet (IEEE 802.3), MIPI protocols, DisplayPort is highly preferable. Should have the experience in building C models for DSP and Verification\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\nThis means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.\nPlease let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.\nClick here for more information about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Staff Silicon Logical Design Engineer - Bengaluru, Multiple Vacancies", "company": "Graphcore", "location": "Bengaluru, India", "date_posted": "2025-10-28T05:54:31-04:00", "url": "https://job-boards.greenhouse.io/graphcore/jobs/8221170002", "is_hardware": true, "platform": "greenhouse", "jd_text": "About Us\n\nGraphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. \n\nAs part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies.\n\nJob Summary\n\nWorking within the logical design team, the silicon logical design engineer is responsible for a wide range of logical design tasks. The team is responsible for delivering the Microarchitecture and RTL design to implement the chip architecture specification for Graphcore Silicon, working closely with other engineers within the Silicon team. The successful candidate will be responsible for helping the team deliver high quality micro-architecture and RTL for Graphcore chips, working within the logical design team and with the broader Silicon team to ensure we meet the company objectives for Silicon delivery. \n\n Responsibilities and Duties\n\nIntegrate IP and subsystems into top-level SoC designs\n\nDevelop and maintain build and configuration environments\n\nPerform synthesis, linting, CDC/RDC, and timing checks at the SoC level\n\nSupport verification and physical design teams through clean interface hand-offs\n\nDebug and resolve integration-related issues across multiple hierarchies\n\nContribute to the continuous improvement of integration flows and automation\n\nProducing high quality microarchitecture and other documentation\n\nEnsure good communication between sites to maintain consistent working practises\n\nCandidate Profile\n\nEssential skills:\n\nLogical design experience in relevant industry\n\nExperience range 8-12 years in Semiconductor Industry/Product development exposure.\n\nBe highly motivated, a self-starter, and a team player\n\nAbility to work across teams and debugging issues seen to find root causes\n\nDegree in Computer Science, Engineering or related subject\n\nAbility to script in Python and/or TCL for automation and to solve design issues\n\nSystemVerilog\n\nKnowledge of digital design flows\n\nDesirable skills:\n\nProcessor design\n\nApplication specific blocks\n\nHigh-speed serial interfaces\n\nComplex third-party IP integration\n\nArithmetic pipeline design\n\nFloating-point design\n\nDesign for test\n\nSynthesis\n\nTiming Analysis\n\nProject Planning\n\nPower Integrity\n\nSilicon transistor\n\nBenefits:\n\nIn addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.", "jd_status": "stored"}, {"title": "STA Lead Engineer", "company": "Samsung", "location": null, "date_posted": "2025-10-14", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/STA-Lead-Engineer_R109848", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nRole and Responsibilities\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products. \n\nRoles and Responsibilities\n\nLooking for bright ASIC design engineer with excellent analytical and technical skills. This role provides opportunity to participate in the ASIC development, with emphasis in synthesis, timing closure, low power, place and route.\nResponsibilities include:\n·         Oversee and mentor a team of STA engineers, ensuring timely project execution for a Chip and Subsystems\n·         Develop constraints, run synthesis, perform low power, timing and equivalence checks and closure\n·         Work closely with RTL designer, physical design, low power teams to optimize performance, area and power\n·         Generate, review and validate design constraints to achieve timing closure of high speed design\n·         Develop floor-planning and CTS guidelines for layout\n·         Analyze pre-layout and post-layout timing, generate Timing and Power ECOs, and work closely with layout engineers to achieve critical high speed path timing closure  \n·         Perform in-house quality check before P&R and after P&R\n·         Constraint management tool and Verilog coding experience\n·         Mentor juniors, support periodic training sessions, work with teams across sites and cross-functional teams and lead by examples\n·         Improve existing process and enhance team  work efficiency\n\nMust have BSEE or MSEE in EE with 12+ years of relevant experience in the following areas:\n·         Must be hands-on technical expert\n·         Strong written and oral communication skills\n·         Good understanding of Deep Sub Micron topics and their associated issues\n·         Good Experience in Top/Block DCT/DCG based Synthesis, Equivalence checks\n·         Experience in leading Hard-IP/HardBlocks/SOC timing closure with deep technical knowledge in all\n·         Should be able to comprehend architecture and associated limitations with respect to synthesis and STA perspective and be able to predict the schedule, amount of task and personnel involved\n·         Good experience with functional and test mode constraints and developing IOs and IP constraints, optimization, STA setup with associated automation, cross-talk noise/delay, STA signoff, GCA, VCLP  \n·         Good understanding of Low Power Management and experience with its implication on synthesis and STA\n·         Should have ability to develop good understanding of a design and associated IPs\n·         Very good in understanding and defining constraints and critical high speed path timing closure working with BE teams\n·         Perl/Tcl scripting is required\n·         Good understanding of the APR flows is desired\n\nExperience – 14 to 20 Years\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\nSkills and Qualifications\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "Design Verification Engineer", "company": "Samsung", "location": null, "date_posted": "2025-10-14", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/Design-Verification-Engineer_R109853", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nRole and Responsibilities\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products. \n\nRoles and Responsibilities\n\nBe an integral part of a diverse Foundry IP Digital Development team that pushes boundaries developing IP's that power the future of Samsung's Products.\n\nYou'll contribute to the verification behind the IP's. Your expertise will share the next generation hardware experiences delivering unparalleled performance, efficiency and integration. \n\nLooking for smart,adept DV engineers with 3-8 years of experience in IP/Sub-system Verification\nDesign and implement reusable DV components for High Speed Interfaces,Security, Memory Technologies\nCreate and utilize verification components using industry-standard methodologies (Eg.SV-UVM),Formal, \nDefine and track key coverage metrics to ensure thorough verification and identify potential design flaws \nHaving working experience in High Speed Interface Protocols like PCIe,Gigabit Ethernet, UNIPRO,MPHY,LPDDR,HBM\nHaving working experience using AMBA Bus protocols like APB,AHB and AXI \nHaving experience using automation scripting and tools [Python,Perl]\n\nExperience – 4 to 8 Years\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\nSkills and Qualifications\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "DFT Design Engineer", "company": "Samsung", "location": null, "date_posted": "2025-10-14", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/DFT-Design-Engineer_R109852", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nRole and Responsibilities\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products. \n\nRoles and Responsibilities\n\n- Preferably 12 to 20 years of relevant experience with exposure on end-to-end activities on DFT (Concept, implementation to silicon bring up)\n- Strong fundamentals on Scan Architectures, MBIST Architectures and Custom BIST\n- Hands-on experience on Implementation, Verification scenario development, testbench coding, Verification at various abstractions (RTL, GLS with UD and SDF)\n- Hands-on experience on SDC development\n- Exposure to post-silicon issue debug\n- Good problem solving skills\n- Experience in working with cross-functional teams.\n- Attention to details, quality reviews and resk management\n\nExperience – 12 to 20 Years\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\nSkills and Qualifications\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "Physical Verification and EMIR Signoff Lead", "company": "Samsung", "location": null, "date_posted": "2025-10-14", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/Physical-Verification-and-EMIR-Signoff-Lead_R109845", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nRole and Responsibilities\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products. \n\nRoles and Responsibilities\nOwn and execute \"PV (Physical Verification)\" and EMIR (Electromigration and IR drop) activities including DRC, LVS, ERC, DFM, ESD, Antenna, PERC, Static IR, Dynamic IR, Signal/Power EM, ESR and Jitter checks at chip, Subsystem and block level\nGood understanding of Physical Design Verification and EMIR methodology to analyse, debug, find optimal solution using Calibre/ICV, Redhawk/Voltus, Innovus and FC tools\nShould have worked on low technology nodes 8nm/5nm/3nm/2nm\nDevelop and manage automated verification flow and scripts in unix, perl, phyton and TCL for high quality and on-time tapeouts.\nCollaborate closely in PD engineers, Design/DfT engineers, FNDRY, Package and Technology experts on PV and EMIR issues and sign-off challenges\nProvide technical Leadership to juniors and keep process and methodology improvements\n\nExperience – 11 to 18 Years\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\nSkills and Qualifications\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "SOC IP RTL Development Engineer", "company": "Samsung", "location": null, "date_posted": "2025-10-14", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/SOC-IP-RTL-Development-Engineer_R109842", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nRole and Responsibilities\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products. \n\nRoles and Responsibilities\nHands on experience in Front end RTL design, architecture, coding at IP Level. \nDomain Experience in the field of High Speed Serdes design is prefered. \nThe domains include USB/PCIE/UCIE/DPTX/EUSB/eDP/DPHY/CPHY/Ethernet PHY IPS. \nKnowledge on Tools LINT/CDC/SYNTHESIS essential. \nAdditional tool knowledge on AFL/XPROP/DFT added advantage.\nPrior experience with silicon debug is a plus\nShould have worked with Cross function teams like SOC team and DV in terms of verification support and coverage closure.\nExperience in mentoring junior team members\nGood scripting skills - Perl, Python, Tcl, bash etc. is a plus\nAbility to work independently and in team environment\n\nExperience – 8 to 11 Years\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\nSkills and Qualifications\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "Lead SOC RTL Design Engineer", "company": "Samsung", "location": null, "date_posted": "2025-10-13", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/Lead-SOC-RTL-Design-Engineer_R109821", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nRole and Responsibilities\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products. \n\nRoles and Responsibilities\n\n·        9-12 years of solid experience in SoC IP design & SoC Subsystem Designs\n·        Experience with High Speed & Low Speed Protocol concepts\n·        Experience with SPI/I2C/I3C/UART/PWM all Low Speed IP’s and design\n·        Added advantage for experience in either UCIe/ Ethernet/ UFS IP’s (Host Controller, Unipro, MPHY) Architecture and protocol\n·        Experience in managing and lead teams of 4-5 Engineers\n·        Architectural level experienced with defining block, sub-system at SOC level\n·        Understanding of interconnect protocols like AXI/AHB/APB concepts\n·        Working knowledge of Lint, CDC, UPF, VCLP, DFT, Power and Clock Flow\n·        Good understanding of the design timing closure and verification debug\n·        Manage SoC dependencies, planning and tracking of all front-end design related tasks\n·        Should possess effective communication and leadership skills \n\nExperience – 9 to 12 Years\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\nSkills and Qualifications\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "Lead Analog Design Engineer", "company": "Samsung", "location": null, "date_posted": "2025-10-13", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/Lead-Analog-Design-Engineer_R109818", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nRole and Responsibilities\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products. \n\nRoles and Responsibilities\n\n·        13 – 22 years of experience in designing custom Analog circuits for SerDes based Architectures.\n·        Strong Analog design background with experience in design and developing  of high speed Analog & Mixed signal blocks including transmitters,receivers,clocking,Equalizer,serializer/deserializer for PHY IP's like UCIe, PCIe,  in advanced process technologies(FINFET and GAA)\n·        Experience in Analog circuit design for high speed serial interface application like Die-to-Die, UA Link or experience in high speed architectures (56/112/224 GbpS) is preferred.\n·        Experience in PAM4 based architectures for Ethernet SerDes is plus.\n·        Experience in SerDes in design with silicon bring-up is plus but not a must.\n·        Experience in mentoring junior team members.\n·        Design experience of Full Chip is good to have.\n·        Experience in Silicon testing/Debug is a plus.\n·        Should be able to work in a dynamic environment with multiple products & product lines.\n\nExperience – 8 to 12 Years\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\nSkills and Qualifications\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "Sr Staff Test Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2025-10-10T14:23:33.263000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000087141695-sr-staff-test-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Renesas’ Analog and Connectivity Business Unit (A&C) is seeking an experienced Test Engineer to join our team. This role offers a unique and exciting opportunity to work on the development of state-of-the-art Memory Interface Devices. You will be part of a cross-functional team, driving the product from conception to volume production.\nKey Responsibilities:\nDevelop test programs for characterization, production, and wafer sort using mFlex and Advantest 93K platform.\nDesign test hardware for PMIC, Temp Sensor and I3C applications.\nParticipate in testability reviews with DFT/DFM teams to enhance yield and test methodologies.\nImplement best practices for robust test solutions, including GR&R, HTOL, and Characterization procedures.\n\nTest Engineer with 10+ Years experience developing hardware and software at Wafer Sort and Final Test for PMIC, Temp Sensors and I3C products.\nTest Lead experience preferred.\n10+ Years of experience on mFLEX, Advantest 93K, SPEA or equivalent tester.\nExperience using I2C, I3C, and SPI protocol as well as trim implementations for power IC products\nStrong analytical and problem-solving skills.\nEffective communication and teamwork abilities.\nSelf-starter, motivated, and able to work independently.\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nWe have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning.", "jd_status": "stored"}, {"title": "Lead Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2025-10-10", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Design-Engineer_R51342", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Description\nBe part of the Cadence DDR PHY IP Front End Design team responsible for -\n•             Develop firmware for DDR5 PHY using microcontrollers\n•             Developing firmware in C typically involving bare-metal programming and developing low-level APIs on Microcontrollers.\n•             Responsible for collaborating with hardware designers and memory subsystem architects to derive training algorithms and implement them.\n•             Responsible for collaborating with the verification team to deduce firmware-hardware co-verification plan.\n•             Develop and Debug firmware in RTL based hardware simulations (C +Verilog simulations)\n•             Develop and Debug on Silicon bring-up boards.\nRequired Skills:\n•             Good Knowledge of DDR5 JEDEC spec, knowledge of different DIMM configurations and specifications.\n•             Relevant experience in developing bare-metal firmware for High-speed SerDes or Memory interface Physical Layer blocks.\n•             Good Knowledge of C programming language for embedded software development and use of relevant IDE.\n•             Comfortable debugging RTL simulations involving firmware and microcontroller subsystem.\n•             Good knowledge of Shell/Perl/Python/TCL scripting\n•             Good experience on Verification EDA Tools like simulators and waveform viewers\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Physical Design Engineer - SOC", "company": "Samsung", "location": "SSIR, Goldstone, Bangalore, India", "date_posted": "2025-10-08", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/SSIR-Goldstone-Bangalore-India/Physical-Design---SLSI_R54639-2", "is_hardware": true, "platform": "workday", "jd_text": "Position Summary\n\nRole and Responsibilities\n\nAbout Samsung Semiconductor India Research (SSIR)\n\nWith a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.\n\nAs one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products. \n\nRoles and Responsibilities\n\nComplex SOC Top Physical Implementation for next generation SOCs in area of mobile application processors, modem sub-systems and connectivity chips by means of Synthesis , Place and Route, STA , timing and physical signoffs\n\nHands on experience doing physical design and timing closure of complex blocks and full-chip designs.\nExperience in top level floor planning including partition shaping and sizing, pin placement, channel planning, high speed signal and clock planning and feed-through planning is a plus.\nShould have strong understanding of timing, power and area trade-offs and optimization of PPA.\nPower user of industry standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities.\nShould have solid understanding of scripting languages such as Perl/Tcl and implementation flows.\nExperience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ .\nExpertise in block level and full-chip SDC clean up, Synthesis optimization , Low Power checking and logic equivalence checking.\nFamiliar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling).\nFamiliar with typical SOC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.\nFamiliar in hierarchical design, top-down design, budgeting, timing and physical convergence.\nGood understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.\nShould have gone through recent successful SOC tape-outs.\n\nExperience – 5+ Years of experience\n\nQualifications\nB.Tech/B.E/M.Tech/M.E\n\nDisclaimer\nSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.\n\nSkills and Qualifications\n\n* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.", "jd_status": "stored"}, {"title": "Senior SOC Modeling Engineer", "company": "Arm", "location": "Bangalore, Karnataka, India", "date_posted": "2025-09-19", "url": "https://careers.arm.com/job/bengaluru/senior-soc-modeling-engineer/33099/86309347216", "is_hardware": true, "platform": "talentbrew", "jd_text": "SENIOR SOFTWARE ENGINEER\n\n \n\nThe Software (CE-SW) group is responsible for developing and improving the software ecosystem around Arm's next generation architectures and systems. This means working with processors and other hardware technology not yet available to the public. You will join a team of Software Engineers who share a passion for leaving their mark on the future of computing.\nWe are looking for software engineers to join the Arm Fast Models team responsible for building high-performance software models of Arm-based systems. These models enable early software development, architecture exploration, and system validation before silicon is available. Members of the modelling team transform hardware designs and specifications into high-performance software representations of hardware systems and components.\nIn this role, you will develop functional models of CPUs, system IP, and complete Arm's reference platforms using C++ and SystemC, working closely with hardware and software teams across Arm.\nIf you are similarly passionate about innovative technologies, then we would love to hear from you!\nKey responsibilities include:\nDevelop, test, and maintain high-performance functional models of Arm system-level IP using C++ and SystemC.\nBuild virtual platforms representing complete Arm’s reference platforms to enable early firmware, OS, and application development before silicon availability.\nCollaborate with hardware architects and RTL designers to understand IP specifications and ensure accurate behavioral modelling.\nWork with open-source and software engineering teams to enable software bring-up on virtual platforms and diagnose system-level issues.\nIntegrate multiple IP models to create scalable system-level simulations.\nParticipate in planning and execution of development roadmaps, working with project managers and global engineering teams.\nRequired Skills and Experience\nMinimum 4+ years of proven experience.\nStrong C/C++ programming skills with experience in developing large-scale software systems.\nExperience in SoC or IP modelling using C++, SystemC, or TLM.\nGood understanding of computer architecture, microarchitecture, and SoC design concepts.\nExperience with software development practices including debugging, testing, and performance optimization.\nExperience using version control systems such as Git/Gerrit.\nUnderstanding of RISC-based architectures and familiarity with CPU instruction sets.\nAbility to work effectively independently and within distributed global teams.\nStrong interpersonal skills, excellent written and spoken English.\nNice to Have\nExperience with Programmer’s View (PV) modelling and SystemC TLM-2.0 methodologies.\nKnowledge of Arm architecture or Arm system IP (CPU, interconnects, GIC, SMMU, etc.).\nExperience building SoC virtual platforms or full-system simulators.\nBackground in low-level software, firmware, bare-metal programming, or device drivers.\nExperience in supporting to large-scale multi-site software projects.\nWhy Join Us\nWork on modern virtual platforms used across the Arm ecosystem.\nExperience with hardware validation labs and test farms.\nCollaborate with world-class engineers across global Arm teams.\nA clear path for career progression, with scope to evolve into technical leadership or management roles.\nOur 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset\nAccommodations at Arm\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working at Arm\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities at Arm\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.", "jd_status": "stored"}, {"title": "Staff Product Engineer", "company": "Renesas", "location": "Bengaluru, KA, India", "date_posted": "2025-09-18T13:06:58.968000+00:00", "url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000082674705-staff-product-engineer", "is_hardware": true, "platform": "smartrecruiters", "jd_text": "Full PE product lifecycle ownership from concept to end of life with a focus on ensuring the delivery of the highest quality products to our end customers\n• Definition of ATE test, qualification and manufacturing plans\n• Product release into manufacturing with adherence to stringent tier 1-customer requirements\n• Datasheet and automotive compliance reports\n• Real time customer support for design, product and quality related issues\n• Temperature/Voltage/Process characterization and production limit setting\n• Product new product introduction and yield ownership\n• Product BOM release and maintenance\n• Excursion management for both suppliers and customers\n• Use commercially available yield tools for yield improvement and monitoring, generate weekly reports and review with PE teams\n• KPI achievement in product related deliverables including NPI execution and velocity, product cost (Gross margin improvements), product quality performance and failure analysis cycle times\n• PAT, SYL, SBL, SPC limit and disposition optimizations to protect quality without excessive waste\n \nREQUIREMENTS:\n• 7+ years experience in product engineering.  A strong analog circuit background is a must. Familiarity with power management IC testing would be a plus\n• Familiarity with ATE tester platforms (eg. Teradyne J750, Advantest 93K)\n• Knowledge of analog and mix-signal circuitry and the common building blocks, device physics, test methodology and DFT knowledge\n• Experience with common lab test equipment (DC power supply, oscilloscope, multi-meters etc). Bench characterization experience is a plus\n• Familiarity with JEDEC/AEC qualification standards and stress test conditions. Experience with qual hardware/software development would be preferred\n• Experience in yield management tools such as PDF Exensio, JMP. Apply statistical analysis to isolate the issue and make data-driven decisions\n• Ability to managing supplier excursions and customer escalations through problem solving\n• Knowledge of Semiconductor Failure Analysis is preferable\n• Strong verbal and written communication skills\n• A good team player. Effective in fast paced, dynamic work environment\n\n• BS in Electrical/Electronic Engineering\n• MS in Electrical/Electronic Engineering is preferred\n\nRenesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.\n\n \n\nWith a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     \n\n \n\nAt Renesas, you can: \nLaunch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  \nMake a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. \nMaximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    \nAre you ready to own your success and make your mark?  \nJoin Renesas. Let’s Shape the Future together.  \nRenesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.\nWe have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning.", "jd_status": "stored"}, {"title": "Sr Principal Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2025-09-17", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Sr-Principal-Design-Engineer_R50692", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Summary\nWe are seeking a highly skilled RTL Design Engineer with deep expertise in PCIe protocol (Gen4/Gen5/Gen6) to join our PCIe Controller IP development team. The candidate will be responsible for designing, implementing, and verifying RTL for PCIe controllers and related subsystems, ensuring compliance with protocol standards and performance targets.\n\nKey Responsibilities\nArchitect and implement RTL for PCIe IP blocks\nCollaborate with system architects to define micro-architecture and design specifications.\nResponsible for the quality of Design Quality. Expertise in LINT/CDC, Synthesis is Must.\nWork closely with verification teams to develop testbenches and validate functionality.\nParticipate in interoperability testing\nContribute to performance, power, and area optimization in advanced nodes.\nInterface with cross-functional teams including PHY, software, and validation.\n\nRequired Skills\nStrong hands-on experience in RTL design using Verilog/SystemVerilog.\nDeep understanding of PCIe protocol stack and transaction layers.\nExperience with AXI & PXC interfaces, DMA engines, and MSI interrupt handling,\nFamiliarity with CDC design principles and asynchronous FIFO implementation.\nProficiency in synthesis, linting, and static timing analysis.\nExposure to formal verification and assertion-based design methodologies.\nExperience with simulation tools and waveform debugging.\n\nEducation\nBachelor’s or Master’s degree in Electronics /Electrical Engineering , or related field.\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "STA Lead Engineer", "company": "MediaTek", "location": "Bangalore", "date_posted": "2025-09-03T16:00:00+00:00", "url": "https://careers.mediatek.com/en/jobs/MTB120250904000", "is_hardware": true, "platform": "mediatek", "jd_text": "Job Responsibilities:\n\n-Work in the full STA cycle, from initial constraints validation to final GDS sign-off\n-Perform STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage SoC and subsystem designs\n-Manage timing ECOs (DMSA, tweaker, PrimeClosure) and conduct logical equivalence checks (RTL to Netlist)\n-Validate and debug timing across multiple PVT conditions using tools such as PrimeTime and Tempus\n-Work closely with RTL, Synthesis, and Physical Design teams to influence floorplanning and CTS strategies for timing-optimized layouts\n-Partner with design, DFT, synthesis, technology, CAD, and physical implementation teams", "jd_status": "stored"}, {"title": "Sr Principal Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2025-09-01", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Sr-Principal-Design-Engineer_R50560", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\n12-14 yrs of work experiences in VLSI domain with Master’s/bachelor’s degree in engineering Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology Expertise in assertions development/closure, constraint randomization, functional and code coverages, formal verification Expertise in test-bench development Strong RTL and GLS (w/ or w/o SDF) sim debug skills Should be able to manage project schedule and delivery independently\n\nShould be good in Perl/Tcl scripting and automation\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Sr Principal Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2025-09-01", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Sr-Principal-Design-Engineer_R50559", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\n12-14 yrs of work experiences in VLSI domain with Master’s/bachelor’s degree in engineering Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology Expertise in assertions development/closure, constraint randomization, functional and code coverages, formal verification Expertise in test-bench development Strong RTL and GLS (w/ or w/o SDF) sim debug skills Should be able to manage project schedule and delivery independently\n\nShould be good in Perl/Tcl scripting and automation\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Sr Principal Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2025-09-01", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Sr-Principal-Design-Engineer_R50558", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\n12-14 yrs of work experiences in VLSI domain with Master’s/bachelor’s degree in engineering Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology Expertise in assertions development/closure, constraint randomization, functional and code coverages, formal verification Expertise in test-bench development Strong RTL and GLS (w/ or w/o SDF) sim debug skills Should be able to manage project schedule and delivery independently\n\nShould be good in Perl/Tcl scripting and automation\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Synthesis Engineer", "company": "MediaTek", "location": "Bangalore", "date_posted": "2025-08-31T16:00:00+00:00", "url": "https://careers.mediatek.com/en/jobs/MTB120250831001", "is_hardware": true, "platform": "mediatek", "jd_text": "Synthesis Engineer: (5+ Years)\nKey Responsibilities:\nSynthesis Environment setup\nValidating synthesis SDC quality\nUtilize Synthesis tool variables and methodologies to extract the best area/power achievable for the process node.\nChecking the synthesis DEF quality\nAnalyze critical timing violation groups and congestion – solve them by finetune floorplan or placement constraints.\nCompare area/power with previous projects and check current project results.\nDFT Insertion and debugging basic DFT issues.\nDiscuss directly with Design teams & Physical design teams to get the best synthesis results.", "jd_status": "stored"}, {"title": "STA Engineer", "company": "MediaTek", "location": "Bangalore", "date_posted": "2025-08-31T16:00:00+00:00", "url": "https://careers.mediatek.com/en/jobs/MTB120250831000", "is_hardware": true, "platform": "mediatek", "jd_text": "STA Engineer (5-10 Years)\n\nKEY RESPONSIBILITIES:\nResponsible for Multi Voltage domain STA environment setup, execution and timing closure\nDrive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks\nEnsuring timing correlation between PnR <-> STA and timely feedbacks to PD team\nGenerating block level HS session and using Top context from SoC for Block-SoC Interface timing closure.\nGenerating timing ECO using Tweaker/PrimeClosure.", "jd_status": "stored"}, {"title": "Design Verification Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2025-07-25", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25000993", "is_hardware": true, "platform": "oracle", "jd_text": "Change the world. Love your job.\nTexas Instruments is seeking Design Verification Engineer. In this role you will confirm the accuracy of designs for analog and mixed signal electronic parts, components, or integrated circuitry for analog and mixed signal electronic equipment and other hardware systems before pattern generation/mask development. The role will require working independently from the product development team who designed the devices to confirm adherence to known design rules, procedures, and best practices. Additional job functions include analyzing equipment to establish operating data and conducting experimental tests and evaluating results to confirm the device meets all requirements in the specifications. You may also run software simulations, selecting components and equipment based on analysis of specifications and reliability. As a Design Verification Engineer you may also review vendor capability to support product development. Requires a BS degree or equivalent experience in the design of equipment, components or circuitry.\n\nAbout ASM Auto:\n\nASM (Application specific Microcontroller) business powers automotive and industrial MCU across multiple applications. ASM is now working on next generation Automotive MCU platform for all kind of vehicle applications e.g. Traction motor control, Charging, Lighting and Heating control, IC Engine management etc. This platform will churn out multiple differentiated products for Zonal networking in Software defined Vehicles (SDV) and superior real time control for EV Cars. Great opportunity to be part of this grounds up platform development across process nodes, IPs and SoCs.\n\nhttps://www.ti.com/applications/automotive/overview.html\n\nResponsibilities:\n\nComplete ownership of IP/subsystem/SOC DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis. This includes:\n\n·       Active involvement with architecture team during the spec definition phase\n\n·       Verification strategy definition along with Verification plan to meet 100% spec to regression traceability along with signoff metrics\n\n·       SubSystem/SOC verification covering functional and Firmware scenarios in RTL/PARTL, GLS/PAGLS modes.\n\n·       DV Environment ownership: TB development/enhancements including checkers and coverage monitor definitions along with DV flow updates as per the project needs\n\n·       Active collaboration with cross functional teams -Architecture, RTL, PD, DFT, Systems, Analog, FW and application teams -to enable the Verification goals for IP/Subsystem/SOC starting from spec definition till post silicon verification closure activities\n\n·       Final SoC DV signoff based on Regressions, coverage metrics, DV to spec traceability using C and/or SV-UVM adhering to ISO26262 guidelines", "jd_status": "source_unavailable"}, {"title": "Analog Mixed-Signal Design Verification Engineer", "company": "MediaTek", "location": "Bangalore", "date_posted": "2025-07-17T16:00:00+00:00", "url": "https://careers.mediatek.com/en/jobs/MTB120250718000", "is_hardware": true, "platform": "mediatek", "jd_text": "Job Function\nWork on functional verification of analog and mixed-signal IPs, including SERDES, sensors, and beyond. The candidate will collaborate with IP design teams and other verification teams, utilizing and enhancing both established and emerging digital verification methodologies and processes. Responsibilities span the full verification lifecycle—from understanding specifications and developing test plans, to achieving coverage closure and supporting post-silicon debug—to ensure high-quality and efficient pre-silicon verification, ultimately delivering robust silicon products.\nSkills/Experience\n•\tQuick learner with strong critical thinking and creative problem-solving skills.\n•\tSolid knowledge in ASIC verification flow, digital design, and UVM-based design verification methodologies.\n•\tProficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA).\n•\tProficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc.\n•\tKnowledge on Design Verification development process, from specification to test plan, to configurable test bench, drivers, and checkers development, to test suite building to meet functional and code coverage goals,\n•\t3+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal IPs or SERDES IPs, such as USB, UFS, PCIe, DDR-PHY, MIPI etc.\n•\tPower-aware simulations and gate level simulations is a plus.\n•\tScripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., Perforce, ClearCase, etc.) is a plus.\n•\tKnowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus.\n•\tFamiliar with programming languages: C, C++, and/or SystemC is a plus.", "jd_status": "stored"}, {"title": "Principal Engineer-SystemC", "company": "Infineon", "location": "Bangalore BTP (India)", "date_posted": "2025-07-17T10:44:59+00:00", "url": "https://jobs.infineon.com/careers/job/563808961229918", "is_hardware": true, "platform": "eightfold", "jd_text": "12+ years of progressive experience in system engineering, with a strong focus on algorithms, system modeling, and power estimation in complex hardware/software systems.\n\nJob Description\nIn your new role you will:\n\nSystem-Level Power Estimation & Optimization: Lead the research,development, and implementation of advanced methodologies and tools foraccurate system-level power estimation (pre-silicon and post-silicon).Drive the identification and recommendation of power optimization strategies across hardware and software components.\nAlgorithm Development & Integration: Define, design, and optimize algorithms that are critical for system performance, power efficiency, and functionality. This includes, but is not limited to, algorithms for power management, resource allocation, performance optimization, and various domain-specific functionalities.\nSystem Modeling & Architecture: Develop comprehensive system-levelmodels (e.g., performance, power, functional) to enable early designspace exploration, trade-off analysis, and architectural validation.Drive the definition of system architectures that align withperformance, power, and cost targets.\nMethodology Development: Pioneer and implement novel system engineeringmethodologies, tools, and best practices to enhance the efficiency andeffectiveness of the design and development lifecycle.\nTechnical Leadership & Mentorship: Provide technical leadership andguidance to cross-functional teams (hardware design, softwaredevelopment, validation, etc.). Mentor junior engineers, fostering aculture of technical excellence and continuous learning.\nResearch & Innovation: Stay abreast of industry trends, emergingtechnologies, and academic research in system engineering, algorithms,and power management. Proactively identify opportunities for innovationand apply cutting-edge techniques to solve complex challenges.\nCross-Functional Collaboration: Collaborate extensively with various product teams, research groups, and external partners to understand requirements, integrate solutions, and drive adoption of developed methodologies and models.\nStrategic Influence: Influence long-term technology roadmaps and strategic initiatives by providing expert insights into system capabilities, limitations, and future directions.\n\nYour Profile\nYou are best equipped for this task if you have:\n\nMaster's or Ph.D. in Electrical Engineering, Computer Science, Systems Engineering, or a related field\n12+ years of progressive experience in system engineering, with a strong focus on algorithms, system modeling, and power estimation in complex hardware/software systems.\nDemonstrated expertise in developing and implementing system-level poweranalysis and optimization techniques.\nProven track record of designing, developing, and optimizing complex algorithms for embedded systems or high-performance computing.\nExtensive experience with various system modeling approaches (e.g.,analytical models, simulation, hardware/software co-simulation) and associated tools (e.g., SystemC, MATLAB/Simulink, Python-based modeling frameworks).\nDeep understanding of system architecture, hardware-software interfaces, and performance bottlenecks.\nStrong programming skills in languages such as C/C++, Python, and/orMATLAB.\nExcellent analytical, problem-solving, and critical thinking skills.\nExceptional communication (written and verbal) and interpersonal skills,with the ability to articulate complex technical concepts to diverse audiences.\nDemonstrated ability to lead technical initiatives, influence stakeholders, and work effectively in a highly collaborative R&Denvironment.\nPreferred Qualifications:\nExperience with specific domains such as AI/ML hardware acceleration,high-performance computing, or low-power embedded systems.\nFamiliarity with industry-standard power estimation tools and methodologies (e.g., power profilers, power models from IP vendors).\nExperience with hardware description languages (Verilog, VHDL) and digital design flows.\nContributions to patents, publications, or open-source projects related to system engineering, algorithms, or power management.\n\nContact:\n    Mh.external2@infineon.com\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\nThis means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.\nPlease let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.\nClick here for more information about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Lead Product Engineer - MIPI Protocol", "company": "Cadence", "location": "BANGALORE", "date_posted": "2025-06-26", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Product-Engineer---MIPI-Protocol_R48745-2", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Title: Lead Product Engineer\nLocation: Bangalore/Ahmedabad\n\nCadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.\n\nThe Cadence Advantage\nThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.\nCadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.\nThe unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success\nMultiple avenues of learning and development available for employees to explore as per their specific requirement and interests\nYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.\n\nJob Summary:\nDrives development of products and technologies and has material responsibility for the success of that product/technology. VIP PE is expected to be an expert in MIPI domain of Verification IP family- protocol and product-wise. PE main role is to help accelerate VIP portfolio adoption at Cadence’s top tier customers by supporting pre-sales technical activities. To ensure that, one must have strong verification expertise and understand customer design and verification flows. As an MIPI VIP and protocol expert, PE drives product knowledge transfer across our field engineers and customer, providing training and developing collaterals. The PE will also need to translate high-level requirements from customers into a technical spec and drive the product definition that fits the customer needs. PE is expected to work independently and collaborate with other team members (R&D, Marketing, support) to ensure all dimensions of the product are aligned. This role requires approximately 20% travel on average.\n\nJob responsibilities: (edit as per the requirement)\nLeads projects with high resource, risk and/or complexity\nDevelops and leads large and multiple cross-functional and cross-organizational programs, initiatives, and activities with high resource requirements, risk and/or complexity\nContinually evaluates technology effectiveness/data interoperability of complex systems\nManages issue resolution with vendors on tech/product quality and functionality and influences vendor roadmap and direction of products\nCommunicates highly-complex ideas, anticipates potential objections and persuades others, often at senior levels, to adopt a different point of view.\n\nExperience and Technical Skills required:\n\nAt least 7 + to 12 years of experience with Verification and Design\nWorking knowledge with MIPI(CSI2/DSI/I3C/PHY) protocols is a must\nExperience with Developing Verification environments using System Verilog\nWorking knowledge and experience with the UVM methodology\nGood experience on solving complex problems where analysis of situations or data requires an in-depth evaluation of various factors. \nExercises judgment within broadly defined practices and policies in selecting methods, techniques, and evaluation criteria for obtaining results. \nExcellent problem-solving and debugging skills\n\nBehavioral skills required\nMust possess strong written, verbal and presentation skills\nAbility to establish a close working relationship with both customer peers and management\nExplore what’s possible to get the job done, including creative use of unconventional solutions\nWork effectively across functions and geographies\nPush to raise the bar while always operating with integrity\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Senior Verification Engineer, Memory Subsystem", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2025-06-26", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer--Memory-Subsystem_JR1999089-1", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.\n\nNVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nWhat you’ll be doing:\nResponsible for verifying the ASIC design, architecture and micro-architecture using advanced verification methodologies.\n\nExpected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.\n\nCome up with test plans, tests and verification infrastructure for complex IPs/sub-systems.\n\nResponsible for performance and deadlock verification of the GPU memory subsystem unit.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nPerform functional coverage driven verification closure.\n\nWorking with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech. with 4+ years of relevant experience\n\nExperience in verification of complex IPs/units and sub-systems\n\nVerification experience using random stimulus along with functional coverage and assertion-based verification methodologies\n\nExpertise in Verilog\n\nKnowledge in SystemVerilog or similar HVL\n\nFamiliarity with verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug\n\nWays to stand out from the crowd:\nExperience in memory subsystem or network interconnect IP verification\n\nGood debugging and analytical skills\n\nScripting knowledge (Python/Perl/shell)\n\nGood communication skills & dream to work as a great teammate\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior SRAM Circuit Design Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2025-06-12", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-SRAM-Circuit-Design-Engineer_JR1997200", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nThe Digital IP (DIP) group at NVIDIA is an organization of circuit design and CAD engineers that creates a wide variety of IP for the chips NVIDIA designs. This group works closely with internal SOC design, silicon testing, and productization teams that turn our IP into products that change the world. One of the roles fulfilled by the DIP group is to develop sophisticated SRAM compilers that are used extensively by our SOC design partners. We are looking to hire a skilled and creative SRAM circuit designer to help achieve these goals in a high-visibility position.\n\nWhat you'll be doing:\nEmbedded SRAM design: Transistor-level circuit design, supervising layout implementation, physical and logical verification, and debug of SRAM macros.\n\nSRAM compiler development: Envisioning, defining, and coding more efficient ways to automate the simultaneous assembly and validation of multiple unique SRAM macros using NVIDIA's extensive compute resources.\n\nAdvanced development: Exploring the potential of future process nodes and developing techniques to achieve optimal power, performance, and area characteristics.\n\nGuiding SOC design, silicon test, and productization efforts: Collaborate with SOC design partners to help them achieve their overall performance and cost goals, guide the silicon test and characterization efforts, and working with productization teams to prepare new silicon for the demanding requirements of real-world applications.\n\nWhat we need to see:\nBSEE minimum (or equivalent experience), MSEE or PhD preferred\n\n3+ years of SRAM design experience with a strong background in digital circuit design, layout, and validation on advanced FinFET processes\n\nPrior design experience in single-port, dual-port, or register file SRAM-based macros required, including complex circuits like self-timed logic and sense-amplifiers\n\nPython scripting ability to parse data and automate tasks\n\nSuccessful track record of delivering designs to production\n\nWays to stand out from the crowd:\nSelf-motivation, attention to detail, and good written, verbal, and presentation skills are needed to success in this role\n\nA high degree of scripting expertise in Python\n\nFamiliarity with Cadence schematic and layout capture tools\n\nSilicon testing/debug experience\n\nNVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice, join our diverse team today!\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Analog Design Engineer", "company": "MediaTek", "location": "Bangalore", "date_posted": "2025-06-09T16:00:00+00:00", "url": "https://careers.mediatek.com/en/jobs/MTB120240509000", "is_hardware": true, "platform": "mediatek", "jd_text": "•\tArchitecture study and evaluation of advanced SerDes topologies\n•\tSerDes design and verification of different high speed analog and mixed signal blocks including, but not limited to: drivers, front end circuits, samplers, comparators, ADCs, DACs, PLLs, clock distribution, etc.\n•\tEvaluate, measure, and debug silicon until it reaches high volume production.\n•\tWork with cross functional teams to optimize the designs.", "jd_status": "stored"}, {"title": "Senior IP DV Engineer - NOC IP", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2025-06-03", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-IP-DV-Engineer---NOC-IP_JR1998310-1", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of memory subsystem units for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\n\nThe GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”\n\nWhat you’ll be doing:\nYou will be responsible for verifying the ASIC design, architecture and micro-architecture of memory sub-systems/units using advanced verification methodologies.\n\nUnderstand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.\n\nComing up come up with test plans, tests and verification infrastructure for complex IPs/sub-systems.\n\nBuild reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.\n\nWork on advanced verification methodologies like SV/UVM.\n\nPerform functional coverage driven verification closure.\n\nWorking with architects, designers, and pre and post silicon verification teams to accomplish your tasks.\n\nWhat we need to see:\nB.Tech./ M.Tech., or equivalent experience.\n\n5+ years of relevant experience.\n\nExperience in verification of complex IPs/units and sub-systems.\n\nBackground in verification using random stimulus along with functional coverage and assertion-based verification methodologies.\n\nExpertise in Verilog.\n\nKnowledge in SystemVerilog or similar HVL / UVM or VMM.\n\nWays to stand out from the crowd:\nExperience in memory subsystem or network interconnect IP verification.\n\nGood debugging and analytical skills with sound scripting knowledge.\n\nGood communication and excellent team player.\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.\n\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "STA methodology engineer", "company": "NXP", "location": "Bangalore", "date_posted": "2025-05-27", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Bangalore/STA-methodology-engineer_R-10058550", "is_hardware": true, "platform": "workday", "jd_text": "Job Title: STA Methodology Engineer\nTeam: CTO-DE-FDIP-Logic Libraries\nLocation: Bengaluru\nExperience Level: 10–12 Years\nEmployment Type: Full-Time\n\nRole Overview:\nWe are seeking a highly skilled and experienced STA Methodology Engineer to join our CTO-DE-FDIP-Logic Libraries team. In this role, you will be responsible for benchmarking various logic libraries across multiple technology nodes (40nm, 14nm, 10nm, 7nm, 5nm) using synthesis and PNR-based flows on real-world chips and blocks. You will collaborate closely with Timing Methodology and Signoff teams to ensure robust and efficient STA methodologies.\nKey Responsibilities:\nBenchmark logic libraries across advanced technology nodes using synthesis and PNR flows.\nCollaborate with cross-functional teams to validate and refine timing constraints.\nDevelop and maintain benchmarking frameworks for constraint validation and STA methodology evaluation.\nPerform comprehensive STA including timing analysis, DRCs, annotation issues, multivoltage flow enablement, noise and crosstalk analysis using Logic Libraries Integration flow checks.\nContribute to the development and automation of STA flows and methodologies.\nRequired Qualifications:\nBachelor’s or Master’s degree in Electrical or Electronics Engineering.\n10–12 years of hands-on experience in STA, with proven tape-out experience as a block owner or lead.\nDeep understanding of STA concepts, timing constraints, and closure methodologies at both block and SoC levels.\nProficient in handling timing-related issues such as DRCs, annotation, multivoltage flows, noise, and crosstalk.\nStrong collaboration skills and ability to work across teams to drive methodology improvements.\nPreferred Skills:\nProficiency in Python scripting.\nOverview/understanding of AI/GenAI would be added advantage.\nExperience in developing or enhancing STA flow automation.\nFamiliarity with industry-standard EDA tools and flows.\nSoft Skills:\nSelf-motivated with a proactive approach to problem-solving.\nStrong communication and interpersonal skills.\nAbility to work independently and as part of a global team.\n\nMore information about NXP in India...\n\n#LI-f91b", "jd_status": "stored"}, {"title": "Senior SRAM Circuit Design Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2025-05-13", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-SRAM-Circuit-Design-Engineer_JR1996865", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.\n\nNVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nThe Digital IP (DIP) group at NVIDIA is an organization of circuit design and CAD engineers that creates a wide variety of IP for the chips NVIDIA designs. This group works closely with internal SOC design, silicon testing, and productization teams that turn our IP into products that change the world. One of the roles fulfilled by the DIP group is to develop sophisticated SRAM compilers that are used extensively by our SOC design partners. We are looking to hire a skilled and creative SRAM circuit designer to help achieve these goals in a high-visibility position.\n\nWhat you'll be doing:\nEmbedded SRAM design: Transistor-level circuit design, supervising layout implementation, physical and logical verification, and debug of SRAM macros.\n\nSRAM compiler development: Envisioning, defining, and coding more efficient ways to automate the simultaneous assembly and validation of multiple unique SRAM macros using NVIDIA's extensive compute resources.\n\nAdvanced development: Exploring the potential of future process nodes and developing techniques to achieve optimal power, performance, and area characteristics.\n\nGuiding SOC design, silicon test, and productization efforts: Collaborate with SOC design partners to help them achieve their overall performance and cost goals, guide the silicon test and characterization efforts, and working with productization teams to prepare new silicon for the demanding requirements of real-world applications.\n\nWhat we need to see:\nBSEE minimum (or equivalent experience), MSEE or PhD preferred\n\n5+ years of SRAM design experience with a strong background in digital circuit design, layout, and validation on advanced FinFET processes\n\nPrior design experience in single-port, dual-port, or register file SRAM-based macros required, including complex circuits like self-timed logic and sense-amplifiers\n\nPython scripting ability to parse data and automate tasks\n\nSuccessful track record of delivering designs to production\n\nWays to stand out from the crowd:\nSelf-motivation, attention to detail, and good written, verbal, and presentation skills are needed to success in this role\n\nA high degree of scripting expertise in Python\n\nFamiliarity with Cadence schematic and layout capture tools\n\nSilicon testing/debug experience\n\nNVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice, join our diverse team today!\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior SRAM Circuit Design Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2025-05-13", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-SRAM-Circuit-Design-Engineer_JR1997193", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.\n\nNVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nThe Digital IP (DIP) group at NVIDIA is an organization of circuit design and CAD engineers that creates a wide variety of IP for the chips NVIDIA designs. This group works closely with internal SOC design, silicon testing, and productization teams that turn our IP into products that change the world. One of the roles fulfilled by the DIP group is to develop sophisticated SRAM compilers that are used extensively by our SOC design partners. We are looking to hire a skilled and creative SRAM circuit designer to help achieve these goals in a high-visibility position.\n\nWhat you'll be doing:\nEmbedded SRAM design: Transistor-level circuit design, supervising layout implementation, physical and logical verification, and debug of SRAM macros.\n\nSRAM compiler development: Envisioning, defining, and coding more efficient ways to automate the simultaneous assembly and validation of multiple unique SRAM macros using NVIDIA's extensive compute resources.\n\nAdvanced development: Exploring the potential of future process nodes and developing techniques to achieve optimal power, performance, and area characteristics.\n\nGuiding SOC design, silicon test, and productization efforts: Collaborate with SOC design partners to help them achieve their overall performance and cost goals, guide the silicon test and characterization efforts, and working with productization teams to prepare new silicon for the demanding requirements of real-world applications.\n\nWhat we need to see:\nBSEE minimum (or equivalent experience), MSEE or PhD preferred\n\n5+ years of SRAM design experience with a strong background in digital circuit design, layout, and validation on advanced FinFET processes\n\nPrior design experience in single-port, dual-port, or register file SRAM-based macros required, including complex circuits like self-timed logic and sense-amplifiers\n\nPython scripting ability to parse data and automate tasks\n\nSuccessful track record of delivering designs to production\n\nWays to stand out from the crowd:\nSelf-motivation, attention to detail, and good written, verbal, and presentation skills are needed to success in this role\n\nA high degree of scripting expertise in Python\n\nFamiliarity with Cadence schematic and layout capture tools\n\nSilicon testing/debug experience\n\nNVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice, join our diverse team today!\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Senior SRAM Circuit Design Engineer", "company": "NVIDIA", "location": "India, Bengaluru", "date_posted": "2025-05-13", "url": "https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-SRAM-Circuit-Design-Engineer_JR1997194-1", "is_hardware": true, "platform": "workday", "jd_text": "NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.\n\nNVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\n\nThe Digital IP (DIP) group at NVIDIA is an organization of circuit design and CAD engineers that creates a wide variety of IP for the chips NVIDIA designs. This group works closely with internal SOC design, silicon testing, and productization teams that turn our IP into products that change the world. One of the roles fulfilled by the DIP group is to develop sophisticated SRAM compilers that are used extensively by our SOC design partners. We are looking to hire a skilled and creative SRAM circuit designer to help achieve these goals in a high-visibility position.\n\nWhat you'll be doing:\nEmbedded SRAM design: Transistor-level circuit design, supervising layout implementation, physical and logical verification, and debug of SRAM macros.\n\nSRAM compiler development: Envisioning, defining, and coding more efficient ways to automate the simultaneous assembly and validation of multiple unique SRAM macros using NVIDIA's extensive compute resources.\n\nAdvanced development: Exploring the potential of future process nodes and developing techniques to achieve optimal power, performance, and area characteristics.\n\nGuiding SOC design, silicon test, and productization efforts: Collaborate with SOC design partners to help them achieve their overall performance and cost goals, guide the silicon test and characterization efforts, and working with productization teams to prepare new silicon for the demanding requirements of real-world applications.\n\nWhat we need to see:\nBSEE minimum (or equivalent experience), MSEE or PhD preferred\n\n3+ years of SRAM design experience with a strong background in digital circuit design, layout, and validation on advanced FinFET processes\n\nPrior design experience in single-port, dual-port, or register file SRAM-based macros required, including complex circuits like self-timed logic and sense-amplifiers\n\nPython scripting ability to parse data and automate tasks\n\nSuccessful track record of delivering designs to production\n\nWays to stand out from the crowd:\nSelf-motivation, attention to detail, and good written, verbal, and presentation skills are needed to success in this role\n\nA high degree of scripting expertise in Python\n\nFamiliarity with Cadence schematic and layout capture tools\n\nSilicon testing/debug experience\n\nNVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice, join our diverse team today!\n\n#LI-Hybrid", "jd_status": "stored"}, {"title": "Staff Engineer Design", "company": "Infineon", "location": "Bangalore BTP", "date_posted": "2025-04-28T12:04:50+00:00", "url": "https://jobs.infineon.com/careers/job/563808957686763", "is_hardware": true, "platform": "eightfold", "jd_text": "Drive and manage as technical lead a self contained DFT team which is responsible of The DFT implementation of latest Infineon microcontroller products, Scan insertion, ATPG, LBIST and MBIST\n\nJob Description\nIn your new role you will:\n\nDrive and manage as technical lead a self contained DFT team which is responsible of:The DFT implementation of latest Infineon microcontroller products\nScan insertion, ATPG, LBIST and MBIST\n\nVerification of the DFT implementation and Test pattern delivery for production testing\nSupport the Silicon bringup activities to guarantee highest stability of the test pattern\nContribute to the overall microcontroller DFT methodology\nCoordination of DFT workpackages and hands-on work, status reporting\nInterfacing with project management, layout team and test engineering\n\nYour Profile\nYou are best equipped for this task if you have:\n\nAt least 6+ years of experience in DFT of highly complex SoCs\nA university degree in Electrical Engineering, Microelectronics, Physics or a similar field.\nProfound knowledge about semiconductor products.\nExpert Knowledge of DFT methods for state-of-the-art MPU/MCU products.\nWorking knowledge of test concept or DFT concept definition.\nStrong track record of scan insertion and ATPG\nVery good knowledge of DFT RTL insertion including MBIST and SRAM repair\nExperience of debugging test pattern issues\nProgramming or scripting experience\nVery good soft skills and experience in leading\n\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\n\nWe are on a journey to create the best Infineon for everyone.\nThis means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills.\nPlease let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.\nClick here for more information about Diversity & Inclusion at Infineon.", "jd_status": "stored"}, {"title": "Principal Software Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2025-04-10", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Software-Engineer_R49736", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Title: Principal Software Engineer\nLocation: Bangalore\n\nCadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.\n\nThe Cadence Advantage\nThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.\nCadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.\nThe unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success\nMultiple avenues of learning and development available for employees to explore as per their specific requirement and interests\nYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.\n\nExperience and Technical Skills required\n5+ to 12 years of hands-on experience in Software development experience with object-oriented languages (C++, Java, Python, etc.)  in an industrial setting\nStrong fundamental knowledge in designing data structures, algorithms, and software engineering principles\nStrong experience in C/C++ development\nStrong experience in Java development\nExcellent verbal and written communications skills\nStrong problem solving and analytical skills\nAdvantage:\nKnowledge/Experience with IP-XACT\nKnowledge/Experience with SystemVerilog and/or UVM\nKnowledge/Experience of communication protocols such as USB/AMBA/Ethernet\n\nQualifications\nBE/BTech or ME/M.Tech Graduate with Computer Science/Electronics & Communication/Electrical & Electronics/VLSI engineering or any other equivalent courses \n\nBehavioral skills required\nMust possess strong written, verbal and presentation skills\nAbility to establish a close working relationship with both customer peers and management\nExplore what’s possible to get the job done, including creative use of unconventional solutions\nWork effectively across functions and geographies\nPush to raise the bar while always operating with integrity\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Solutions Architect", "company": "Baya Systems", "location": "Bengaluru, Karnataka, India", "date_posted": "2025-04-08T23:19:16-04:00", "url": "https://job-boards.greenhouse.io/bayasystems/jobs/4624145008", "is_hardware": true, "platform": "greenhouse", "jd_text": "Baya Systems is inspired by the baya bird, also known as the weaver. Baya birds weave very unique and intricate hanging nests from different materials. The nests are robust and safe while being extremely lightweight and efficient.\n\nBaya is a fast-moving Series B startup built by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era.  We focus on software-driven, unified fabric solutions for single-die and multi-die systems. We design and license disruptive intellectual property for use in semiconductor chips, with software development platforms to simplify the design process and reduce the time to market for complex System-on-Chip (SoC) and multi-chiplet systems. This enables our partners to innovate and deliver compelling solutions for data center, infrastructure, AI, Automotive, and Edge IoT markets. We are looking for energetic and dedicated individuals share our passion for enabling innovation and excellence in the semiconductor industry that empowers game-changing products and services!\n\nSOLUTIONS ARCHITECT\n\nBENGALURU, INDIA\n\nAbout the role:\n\nIf you are skilled and have experience as a Technical Lead in system design and verification, and/or domain expertise in verticals like datacenter, automotive, infrastructure, or in application areas like functional safety, you will play a critical role in providing leadership in applying Baya’s technology to solve customer problems, and drive Baya product and technology forward. You will help understand key system design challenges and help design with and deploy Baya technologies. You will work closely with our sales and engineering teams to understand customer requirements, troubleshoot technical issues, and deliver customized solutions that exceed expectations.\n\nResponsibilities:\n\nServe as the primary technical point of contact for general or specialized solutions built on Baya technology, providing guidance and support throughout the product development lifecycle.\n\nAssist in the design and implementation of customized solutions to meet customer-specific requirements.\n\nDevelop and deliver technical presentations, demonstrations, and training sessions to customers, partners, and internal teams.\n\nStay current with industry trends, technologies, and standard methodologies to effectively advise customers on product development strategies.\n\nProvide timely resolution to customer inquiries, issues and concerns, ensuring high levels of customer satisfaction.\n\nSkills and Experience:\n\n10+ years of experience in designing or supporting complex SoC, from architecture definition to tape-out, addressing implementation challenges on advanced process nodes.\n\n5+ years of experience in a solution architecture or customer-facing technical role is preferred.\n\nMaster’s degree in electrical engineering, Computer Engineering, or related field is preferred.\n\nUnderstanding of RAS and reliability for enterprise and infrastructure markets is a plus.\n\nUnderstanding of functional safety standards and certification.\n\nExcellent communication and interpersonal skills, with the ability to effectively engage with customers, colleagues, and partners at all levels.\n\nThe role will involve travel to customer sites and events.\n\n \n\n \nCompensation:\n\nSalary commensurate with experience\n\nPerformance incentives\n\nComprehensive medical, dental, and vision benefits\n\n401(k) retirement plan\n\nEquity", "jd_status": "stored"}, {"title": "Lead Hardware Engineer - DFT IP R&D", "company": "Cadence", "location": "NOIDA", "date_posted": "2025-03-27", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/NOIDA/Lead-Software-Engineer---DFT-IP-R-D_R49107", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nPosition: Lead Hardware Engineer - DFT IP R&D\nLocation: Noida\nExperience: 4-6 Years\nJob Description\nCadence Design Systems is looking for a highly motivated software and hardware engineer to work as a member of the R&D staff on Cadence’s MODUS DFT software solution. MODUS is a complete product that encompasses Design for Test Solution for Achieving High Coverage, Reduced Test Time, and Superior PPA. The product breadth means we are looking for skilled and motivated candidates with backgrounds in RTL design, DFT architecture, computer architecture, verification, RTL compilation, placement, static timing analysis, power analysis, routing, extraction, and optimization.  You will be part of a team responsible for creating the innovative technologies required for technology leadership in the DFT space. This position will encourage building of a solid foundation in logic circuits and gentle entry into larger DFT IP tool development. Development responsibilities include designing, developing, troubleshooting, debugging and supporting the MODUS software product.\n\nJob Responsibilities:\nYou will play a key role in developing cutting-edge design-for-testability (DFT) tools, contributing to improved usability and quality through feature enhancement and rigorous verification. The role’s day to day responsibilities cover:\nDesigning and verifying Verilog/SystemVerilog/UVM RTL and test benches for DFT IP features, including new DFT IPs, full scan, compressed/uncompressed scan, memory BIST, JTAG, IEEE 1500, and boundary scan at block and SoC levels.\nProviding R&D support to application and product engineers, including problem analysis, debugging, and the development of new features to optimize synthesis results for timing, area, and power.\nThere is a significant research element to the work that Cadence does that is truly innovative; we don’t know what the answers are when we start out!\nMentoring and support will be provided to the successful candidate to both enable contribution to the large EDA problem domain and to develop their problem-solving skills into professional engineering skills.\n\nJob Qualifications:\nProficient in RTL design using Verilog and SystemVerilog.\nIn-depth knowledge of front-end EDA tools (Verilog/SV simulators, linters, CDC checkers).\nExperience with SystemVerilog assertions, checkers, and advanced verification techniques.\nKnowledge of scripting languages, particularly Perl or Python is highly desirable.\nKnowledge of DFT methodologies is a plus.\nStrong foundational knowledge of data structures and algorithms.\nFamiliarity with synthesis, static timing analysis (STA).\nExcellent written and verbal communication and presentation skills.\nExperience and understanding of EDA tool development concepts is a plus.\n\nPosition Qualifications:\nM.Tech, M.E, B.Tech, B.E. in EE/ECE/CS or Equivalent\nGood understanding of Digital Electronics.\nPrior knowledge of Verilog/System Verilog and EDA tools required.\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Principal Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2025-03-05", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Design-Engineer_R49184", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Title: Principal Design Engineer\nLocation: Bangalore\n\nCadence is a pivotal leader in electronic design, building upon more than 30+ years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.\n\nThe Cadence Advantage\nThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.\nCadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.\nThe unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success\nMultiple avenues of learning and development available for employees to explore as per their specific requirement and interests\nYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.\n\nJob Summary: \n\nEducation: (Diploma/BE/BTech/MTech/MS/ME in computer science/electronics or related field)\n\nExperience: 7-12 years\nResponsibilities:\n·     Complete DFT ownership of projects including:\nTest architecture definition.\nIdentifying and implementing RTL changes for DFT.\nPerforming scan insertion, LEC checks, low power CLP checks.\nDeveloping timing constraints for test mode timing closure.\nScan and ATPG for different fault models.\nBoundary scan, ACJTAG, IEEE 1500 implementation and verification.\nIEEE1687 (iJTAG) compliant ICL/PDL for functional manufacturing tests.\nRunning zero delay and timing simulations and debugging on all the above aspects.\nSupporting post silicon bring up.\nInteracting with customers on DFT aspects and support Marketing & Pre-Sales team.\nExperience working on very high speed and low power designs.\n\nRequirements/Qualifications:\n·     This role requires close interaction with multiple cross functional teams across geographies to align on project receivables/deliverables.\n·     Mentoring junior engineers and driving innovation/automation.\n·     BE/B.Tech/M.E/M.Tech with 9+ years of relevant work experience and strong understanding of DFT concepts and good communication skills.\n·     Strong hands-on experience using industry standard EDA Tools.\n·     Experience with logic simulators from one or more EDA vendors.\n·     Experience on industry standard ATPG tools like Cadence Modus.\n·     Experience with RTL lint tools like Jasper.\n·     Experience in scan insertion, coverage analysis and debugging skills on faults coverage enhancement is required.\n·     Programming in Perl/Tcl/Python or other scripting languages is a plus.\n·     Experience in post silicon validation, ATE debug and support is desired.\n·     Exposure to RTL2GDS flow and tasks such as synthesis and scan insertion, STA and IR drop.\n·     Good understanding of Logic design, RTL implementation & verification, logic synthesis, Logic Equivalent Checking & Static Timing Analysis are plus.\n·     Participate in driving new DFT methodology and solutions to improve quality, reliability and in-system test and debug capability.\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "DFT Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2025-02-26", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25000488", "is_hardware": true, "platform": "oracle", "jd_text": "We are seeking talented and motivated individuals to join our team in developing cutting-edge solutions with Application-Specific Microcontrollers (MCUs) for the rapidly evolving automotive industry. Our MCUs power a wide range of critical vehicle functions, including traction control, onboard charging (OBC) and DC-DC converters, advanced lighting systems, body control modules, engine management, and braking systems. Additionally, we are at the forefront of innovation with zonal microcontrollers designed to enable software-defined vehicles, paving the way for greater functionality, scalability, and efficiency. Our products shape the future of automotive technology and create impactful solutions for modern mobility challenges.\n\n \n\nPosition: Senior DFT Design Engineer\n\nWe are seeking an experienced Senior DFT Design Engineer to join our team in developing advanced automotive microcontroller solutions. The ideal candidate will have extensive expertise in Design for Testability (DFT) for SoCs, with a focus on Scan Insertion/ATPG and Memory Test methodologies.\n\nKey Responsibilities:\n\n• Define, influence DFT architecture for subsystems and SoCs, achieving automotive-grade Safety and Security standards for logic and memory tests.\n\n• Collaborate with IP teams, Systems, and Architecture teams to derive requirements, co-develop microarchitecture, and align DFT goals for IPs, subsystems, and SoCs.\n\n• Work closely with Product and Test Engineering teams to understand test needs, provide DFT solutions, debug issues, and optimize test costs.\n\n• Partner with cross-functional teams (RTL, DV, PD) to ensure high-quality and timely DFT implementation.", "jd_status": "source_unavailable"}, {"title": "Sr. Field Applications Engineer", "company": "Baya Systems", "location": "Bengaluru, Karnataka, India", "date_posted": "2025-02-14T00:26:28-05:00", "url": "https://job-boards.greenhouse.io/bayasystems/jobs/4543175008", "is_hardware": true, "platform": "greenhouse", "jd_text": "Baya Systems is inspired by the baya bird, also known as the weaver. Baya birds weave very unique and intricate hanging nests from different materials. The nests are robust and safe while being extremely lightweight and efficient.\n\nBaya is a fast-moving Series B startup built by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era.  We focus on software-driven, unified fabric solutions for single-die and multi-die systems. We design and license disruptive intellectual property for use in semiconductor chips, with software development platforms to simplify the design process and reduce the time to market for complex System-on-Chip (SoC) and multi-chiplet systems. This enables our partners to innovate and deliver compelling solutions for data center, infrastructure, AI, Automotive, and Edge IoT markets. We are looking for energetic and dedicated individuals share our passion for enabling innovation and excellence in the semiconductor industry that empowers game-changing products and services!\n\nSENIOR FIELD APPLICATIONS ENGINEER \n\nBENGALURU, INDIA\n\nAbout the role:\n\nIf you are skilled and have experience as a Senior Field Applications Engineer, you will play a critical role in providing technical expertise and support to our customers. You will empower and guide them on designing and deploying Baya technologies into their products. You will work closely with our sales and engineering teams to understand customer requirements, troubleshoot technical issues, and deliver customized solutions that exceed expectations.\n\nResponsibilities:\n\nServe as the primary technical point of contact for key customers, providing guidance and support throughout the product development lifecycle.\n\nAssist in the design and implementation of customized solutions to meet customer-specific requirements.\n\nDevelop and deliver technical presentations, demonstrations, and training sessions to customers, partners, and internal teams.\n\nProvide timely resolution to customer inquiries, issues, and concerns, ensuring high levels of customer satisfaction.\n\nStay current with industry trends, technologies, and standard methodologies to effectively advise customers on product development strategies.\n\nSkills and Experience:\n\n5+ years of experience in a field application engineering or customer-facing technical role, with a master’s degree in electrical engineering, Computer Engineering, or related field.\n\nExperience in designing or supporting complex SoC, from architecture definition to tape-out, addressing implementation challenges on advanced process nodes.\n\nUnderstanding of RAS and reliability for enterprise and infrastructure markets is a plus.\n\nUnderstanding of functional safety standards and certification.\n\nExcellent communication and interpersonal skills, with the ability to effectively engage with customers, colleagues, and partners at all levels.\n\nThe role will involve travel to customer sites and events.\n\n \nCompensation:\n\nSalary commensurate with experience\n\nPerformance incentives\n\nComprehensive medical, dental, and vision benefits\n\n401(k) retirement plan\n\nEquity", "jd_status": "stored"}, {"title": "Software Verification Engineer", "company": "Baya Systems", "location": "Bengaluru, Karnataka, India", "date_posted": "2025-02-14T00:26:24-05:00", "url": "https://job-boards.greenhouse.io/bayasystems/jobs/4513744008", "is_hardware": true, "platform": "greenhouse", "jd_text": "Baya Systems is inspired by the baya bird, also known as the weaver. Baya birds weave very unique and intricate hanging nests from different materials. The nests are robust and safe while being extremely lightweight and efficient.\n\nBaya is a fast-moving Series B startup built by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era.  We focus on software-driven, unified fabric solutions for single-die and multi-die systems. We design and license disruptive intellectual property for use in semiconductor chips, with software development platforms to simplify the design process and reduce the time to market for complex System-on-Chip (SoC) and multi-chiplet systems. This enables our partners to innovate and deliver compelling solutions for data center, infrastructure, AI, Automotive, and Edge IoT markets. We are looking for energetic and dedicated individuals share our passion for enabling innovation and excellence in the semiconductor industry that empowers game-changing products and services!\n\nSOFTWARE VERIFICATION ENGINEER \n\nBENGALURU, INDIA\n\nAbout the role: \n\n \n\nWe are seeking a seasoned Software Verification designer with a strong background in building infrastructure and writing test sequences for complex software platforms. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions\n\n \n\nResponsibilities​:\n\nOwn functional and performance verification of Baya’s software platforms\n\nDefine software verification infrastructure and processes to ensure high quality and performance\n\nDevelop and execute software test plans, verification convergence plans and monitor quality metrics\n\nCollaborate with architects to define and verify performance metrics of the IP\n\nGuide engineers on verification closure\n\nManage regressions, triaging and debugging\n\nSign-off on verification and quality for release milestones​\n\nQualifications:\n\nBS, MS in Computer Science, Computer Engineering or Electrical Engineering (or equivalent experience)\n\n4+ years of experience in SW or HW verification in the semiconductor, CAD or automotive industry\n\nProficiency in Python and C++\n\nProficiency with System C is a plus\n\nExcellent problem-solving skills and attention to detail\n\nFamiliarity with Arm CHI and AXI protocols is a plus\n\nUnderstanding of software systems design and modeling\n\nUnderstanding of computer architecture and networking concepts\n\nUnderstanding of System/SoC architecture\n\nExperience with modern code development practices: Git, CI, UI\n\nStrong communication and collaboration skills\n\n \n\n \n\n \nCompensation:\n\nSalary commensurate with experience\n\nPerformance incentives\n\nComprehensive medical, dental, and vision benefits\n\n401(k) retirement plan\n\nEquity", "jd_status": "stored"}, {"title": "Microarchitect and RTL Design Engineer", "company": "Baya Systems", "location": "Bengaluru, Karnataka, India", "date_posted": "2025-02-14T00:26:17-05:00", "url": "https://job-boards.greenhouse.io/bayasystems/jobs/4509311008", "is_hardware": true, "platform": "greenhouse", "jd_text": "Baya Systems is inspired by the baya bird, also known as the weaver. Baya birds weave very unique and intricate hanging nests from different materials. The nests are robust and safe while being extremely lightweight and efficient.\n\nBaya is a fast-moving Series B startup built by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era.  We focus on software-driven, unified fabric solutions for single-die and multi-die systems. We design and license disruptive intellectual property for use in semiconductor chips, with software development platforms to simplify the design process and reduce the time to market for complex System-on-Chip (SoC) and multi-chiplet systems. This enables our partners to innovate and deliver compelling solutions for data center, infrastructure, AI, Automotive, and Edge IoT markets. We are looking for energetic and dedicated individuals share our passion for enabling innovation and excellence in the semiconductor industry that empowers game-changing products and services!\n\nMICROARCHITECT AND RTL DESIGN  \n\nBENGALURU, INDIA\n\nAbout the role:\n\nWe are seeking a seasoned Microarchitect and RTL Design Engineer with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions\n\nResponsibilities:\n\nDesign and develop microarchitectures for a set of highly configurable IP's\n\nMicroarchitecture and RTL coding ensuring optimal performance, power, area\n\nCollaborate with software teams to define configuration requirements, verification collaterals etc.\n\nWork with verification teams on assertions, test plans, debug, coverage etc.\n\nQualifications and Preferred Skills:\n\nBS, MS in Electrical Engineering, Computer Engineering or Computer Science\n\n8+ years and current hands-on experience in microarchitecture and RTL development\n\nProficiency in Verilog, System Verilog\n\nFamiliarity with industry-standard EDA tools and methodologies\n\nExperience with large high-speed, pipelined, stateful designs, and low power designs\n\nIn-depth understanding of on-chip interconnects and NoC's\n\nExperience within Arm ACE/CHI or similar coherency protocols\n\nExperience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and NoC's\n\nFamiliarity with RAS designs, QoS in fabrics, PCIe/IO is a plus\n\nExperience with modern programming languages like Python is a plus\n\nExcellent problem-solving skills and attention to detail\n\nStrong communication and collaboration skills\n\n \nCompensation:\n\nSalary commensurate with experience\n\nPerformance incentives\n\nComprehensive medical, dental, and vision benefits\n\n401(k) retirement plan\n\nEquity", "jd_status": "stored"}, {"title": "Hardware Verification Engineer", "company": "Baya Systems", "location": "Bengaluru, Karnataka, India", "date_posted": "2025-02-14T00:26:14-05:00", "url": "https://job-boards.greenhouse.io/bayasystems/jobs/4511816008", "is_hardware": true, "platform": "greenhouse", "jd_text": "Baya Systems is inspired by the baya bird, also known as the weaver. Baya birds weave very unique and intricate hanging nests from different materials. The nests are robust and safe while being extremely lightweight and efficient.\n\nBaya is a fast-moving Series B startup built by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era.  We focus on software-driven, unified fabric solutions for single-die and multi-die systems. We design and license disruptive intellectual property for use in semiconductor chips, with software development platforms to simplify the design process and reduce the time to market for complex System-on-Chip (SoC) and multi-chiplet systems. This enables our partners to innovate and deliver compelling solutions for data center, infrastructure, AI, Automotive, and Edge IoT markets. We are looking for energetic and dedicated individuals share our passion for enabling innovation and excellence in the semiconductor industry that empowers game-changing products and services!\n\nDESIGN VERIFICATION ENGINEER\n\nBENGALURU, INDIA\n\nAbout the role:\n\nWe are seeking a seasoned Design Verification Engineer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions\n\nResponsibilities​:\n\nCreate test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems\n\nWrite UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards\n\nCollaborate with software teams to define and implement configurable test benches\n\nWork with design teams test plans, failure debug, coverage, etc.​\n\nQualifications and Preferred Skills​\n\nBS, MS in Electrical Engineering, Computer Engineering or Computer Science\n\n8+ years and current hands-on experience in block-level/IP-level/SoC-level verification\n\nProficiency in Verilog, SystemVerilog\n\nFamiliarity with industry-standard EDA tools for simulation and debug\n\nDeep experience with UVM-based test benches\n\nExperience with modern programming languages like Python\n\nKnowledge of Arm AMBA protocols such as AXI, APB, and AHB\n\nUnderstanding of Arm CHI protocol is a plus\n\nExperience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NoCs\n\nExperience with formal verification techniques, emulation platforms is a plus\n\nExcellent problem-solving skills and attention to detail\n\nStrong communication and collaboration skills\n\n \nCompensation:\n\nSalary commensurate with experience\n\nPerformance incentives\n\nComprehensive medical, dental, and vision benefits\n\n401(k) retirement plan\n\nEquity", "jd_status": "stored"}, {"title": "Lead Analog Design Engineer", "company": "Texas Instruments", "location": "Bengaluru, KA, IN", "date_posted": "2025-02-11", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/job/25000482", "is_hardware": true, "platform": "oracle", "jd_text": "Position Overview:\nWe are seeking a highly skilled and experienced Analog and Mixed Signal Designer to lead and drive the development of cutting-edge embedded Flash Memory IPs; which are comprised of analog and mixed signal circuits. The ideal candidate will have a strong analog/mixed-signal background, with hands on embedded Flash memory design experience and a deep understanding of underlying device physics.\n \n \nKey Responsibilities:\n \n1.       Technical Leadership:\n·       Oversee the design, development, and verification of analog and mixed-signal circuits for flash memory development, including charge pumps, voltage regulators, sense amplifiers, and memory interfaces.\n·       Define and review circuit architectures to optimize performance, power, and area (PPA).     \n·       Drive innovation in circuit design to address industry challenges in scaling, performance, and reliability for flash.\n·       Provide technical guidance and direction to team members, ensuring timely project execution.\n·       Collaborate with world-wide cross-functional teams, including layout, process, test engineering, and product teams.\n·       Ensure designs meet technical specifications, project timelines, and quality standards.\n·       Identify and mitigate design risks, ensuring robust circuit performance under process, voltage, and temperature (PVT) variations.\n2.       Collaboration and Communication:\n·       Work closely with flash bit-cell architecture and product teams to align circuit design with system-level requirements.\n·       Interface with Process teams (Process Integration Engineers) to optimize technology for flash/NVM applications.\n·       Present project updates, technical reviews, and status reports to stakeholders and senior management.\n3.       Innovation and Continuous Improvement:\n·       Stay updated on industry trends, emerging technologies, and best practices in embedded flash and analog design.\n·       Drive continuous improvement in design methodologies, tools, and workflows.", "jd_status": "source_unavailable"}, {"title": "Lead Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2024-12-03", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Design-Engineer_R45608", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nPosition Description:\nIP Integration and release Engineer for SSG IP Release engineering team.\nPosition is based in Bangalore.\nThe role would include IP integration, verification, and release of the IP solution of Cadence to different customers.\nThe work involved will be working with the existing RTL, integration of the PHY and controller to create the sub-system, addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring design is clean for LINT and CDC design guidelines.\nProficient in ASIC development flows like Lint/CDC/Synthesis (preferably with Genus)/STA.  Ability to debug and setup new flows.\n\nPosition Requirements:\nBE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design verification engineer, with a large portion of the recent work experience on RTL integration and verification.\n6-10 years of core RTL integration and verification experience using Verilog is a must.\nSystem Verilog experience and experience with UVM based environment usage / debugging is required.\nPCIe/CXL/IDE experience is highly desirable. Prior experience in implementation of complex protocols is a must.\nPrior experience in IP development teams would be an added advantage. \nScripting knowledge is an advantage.\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "DFT Engineer", "company": "MediaTek", "location": "Bangalore", "date_posted": "2024-11-27T16:00:00+00:00", "url": "https://careers.mediatek.com/en/jobs/MTB120190117001", "is_hardware": true, "platform": "mediatek", "jd_text": "6+ years working experience on DFT and usage of tools like Tetramax\nSoC / Modem DFT for Smartphone \nATPG Coverage analysis and improvements\nAPTG/TFT  pattern generation and optimization\nCo-work with Smartphone SOC team to plan SoC/Modem DFT requirements\nHandle pre-silicon DFT verification and post-silicon DFT debug\nDFT clocking and  DFT timing constraints\nDoing scan synthesis and scan-chain analysis/stitching etc\nDoing DCT/DCG synthesis.\nAnalyze DFT timings violations along with STA teams\nWork on the DFT methodologies for new technology nodes", "jd_status": "stored"}, {"title": "Sr Design Engineering Architect", "company": "Cadence", "location": "BANGALORE", "date_posted": "2024-10-15", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Sr-Design-Engineering-Architect_R47612-5", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nPosition Description:\nRTL Design Engineer for Interface Controller IP development team.\nPosition is based in Bangalore or Noida.\nThe role is for PCIe Architect with ARM CPU subsystem architecture, including memory subsystem design, IO and cache subsystems.\nThe role would also include design and support of the RTL of the PCIe/CXL/IDE/UALink IP solution of Cadence.\nThe work involved will be addition of new features into the RTL, working with existing RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring design is clean for LINT and CDC design guidelines.\nPosition Requirements:\nBE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.\n6-16 years of core RTL Design experience using Verilog is a must.\nSystem Verilog experience and experience with UVM based environment usage / debugging is required.\nArchitecture and design of CPU subsystem, including memory subsystem design, IO and cache subsystems is a must.\nPCIe/CXL/IDE experience is highly desirable. Prior experience in implementation of complex protocols is desirable.\nPrior experience in IP development teams would be an added advantage. \nScripting knowledge is an advantage.\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Lead Support Application Engineer - GCS", "company": "Cadence", "location": "BANGALORE", "date_posted": "2024-09-20", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Support-Application-Engineer---GCS_R47537", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nGCS AE Job Description Document\n\nJob Title: Lead Application Engineer - GCS\nLocation: Bangalore / Noida\nCadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.\nThe Cadence Advantage\nThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.\n\nCadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.\n\nThe unique “One Cadence – One Team” culture builds and fosters diversity, equity and inclusion to maximize our ability to innovate, drive growth, and win with our customers. Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. \n\nMultiple avenues of learning and development available for employees to explore as per their specific requirement and interests\n\nYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.\n\nJob Summary\nAs a member of the GCS Organization for the MSA (Multiphysics System Analysis), you will partner with world-wide Cadence customers to provide post sales technical consultation for IC level Power System analysis products for implementing cutting-edge designs. This involves working closely with the customers to understand and debug complex issues enabling them to proceed further with design cycle phases, help them leverage the latest tool capabilities, and guide them with implementation of software in their design methodologies. You will have an opportunity to acquire both breadth and depth of technical knowledge, get wide exposure to the latest design practices in industry and demonstrate expertise by authoring high impact knowledge content.\nThis role also provides opportunity to participate in the evolution of key technology solutions to the most pressing design problems. In this role, you will have the opportunity to work with product teams to identify and prioritize the product improvement initiatives with your timely feedback and observations.\nThis an excellent opportunity to work in a supportive, flexible and friendly work environment that GCS offers, where we are vested in each other’s success, and are passionate about technology and innovation.\n\nJob Responsibilities\nProvide technical support for Voltus product from the Multiphysics System Analysis (MSA) toolset of Cadence products with focus on productivity, and customer satisfaction\n\nSupport multiple tools/methods for customer requiring general domain knowledge and developing business experience\n\nAssist in creation of high quality and impactful knowledge content in MSA domain\n\nWork independently at Cadence or customer facilities to deliver quality results according to schedule requirements\n\nWork on problems of moderate scope that may require analysis of situations, data or tool problems\n\nQualifications\nBachelor’s Degree in; Electrical / Electronics / Electronics and Communication / VLSI Engineering with 5-7 years related experience\n\nOR Masters with 3-4 years of related experience\n\nOR PhD with 1 years of related experience\n\nExperience and Technical Skills required\n3-7 years relevant industry experience in EMIR analysis, PDN analysis with digital signoff tools and Digital Physical implementation as designer or methodology/flow expert\n\nStrong background in Digital logic Design, CMOS logic Design, Power IR drop analysis, Circuit Design and Analysis, Digital and Behavioral simulation fundamentals related to IC and Package Design\n\nDebugging of Low power and multiple power domain analysis for chip power integrity sign-off.\n\nUnderstanding of Digital design toolsets of Cadence (Genus/Innovus/Tempus/Conformal); knowledgeable of at least 50% of a given flow; detailed knowledge in one CDN tool, learning others; ability to analyze customer's environment and evaluate appropriate support solutions; learning competitive tools/technologies\n\nMust have excellent debugging skills and ability to separate out the critical issues from trivial ones.\n\nAbility to solve interface level problems emanating from IC Implementation side and System analysis side.\n\nAbility to debug Timing and thermal issues in relation to IR and EM is a plus\n\nGood understanding of Hardware description languages like VHDL, Verilog, System Verilog.\n\nKnowledge on TCL, Perl or Python scripting.\n\nBehavioral skills required\nMust possess strong written, verbal and presentation skills\n\nAbility to establish a close working relationship with both customer peers and management\n\nExplore what’s possible to get the job done, including creative use of unconventional solutions\n\nWork effectively across functions and geographies\n\nPush to raise the bar while always operating with integrity\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Lead Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2024-09-19", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Design-Engineer_R47293-5", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nBe part of the Cadence Memory IP Group adn responsible for - \nDeveloping firmware for DDR/LPDDR/GDDR/HBM PHY using microcontrollers\nResponsible for developing firmware in C and similar Embedded programming languages typically involving bare-metal programming and developing low level APIs on Microcontrollers.\nResponsible for collaborating with hardware designers and memory subsystem architects to derive algorithms and implement them.\nResponsible for collaborating with verification team to deduce firmware-hardware co-verification plan.\nSupport debug of firmware-based simulations in hardware behavioral simulations (RTL simulations with firmware for verification)\nSupport debugging issues on emulation and Silicon bring-up boards.\n\nRequired Skills:\n4-6 years of experience in developing bare-metal firmware for High-speed Serdes or Memory interface Physical Layer blocks.\nGood Knowledge C programming language for embedded software development and use of relevant IDE.\nComfortable debugging RTL simulations involving firmware and microcontroller subsystem. \nGood knowledge of Shell/Perl/Python/TCL scripting\nGood debugging skills\nGood experience on Verification EDA Tools like simulators and waveform viewers\nGood communication Skill\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Sr Principal Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2024-08-29", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Design-Engineering-Architect_R45339", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nPosition Description:\nRTL Design Engineer for DDR Memory Controller IP development team.\nThe role would include the design and support of the RTL of the DDR Memory Controller solution of Cadence. All leading DDR memory protocols will be supported – including DDR4/LPDDR4.\nThe work involved will be working with the existing RTL, the addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring the design is clean for LINT and CDC design guidelines.\n\nPosition Requirements:\nBE/B.Tech/ME/M.Tech - Electrical / Electronics / VLSI with experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.\nRTL Design using Verilog is a must.\nSystem Verilog experience and experience with UVM based environment usage / debugging is required.\nAXI3/4 experience is desired.\nDDR Memory controller and protocol experience is highly desirable. Prior experience in RTL design and implementation of complex protocols is a must.\nPrior experience in IP development teams would be an added advantage.\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Design Engineering Manager", "company": "Cadence", "location": "BANGALORE", "date_posted": "2024-08-07", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Design-Engineer_R43928", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Title: Design Engineering Manager\nLocation: Bangalore\n\nCadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.\n\nThe Cadence Advantage\nThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.\nCadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.\nThe unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success\nMultiple avenues of learning and development available for employees to explore as per their specific requirement and interests\nYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.\n\nJob Summary:\n               \n\nWe have an immediate opening in the Post Silicon Physical Layer Electrical Validation team at Cadence Design Systems Bangalore, for the post of \"Design Engineering Manager\".\n\nThe responsibility entails leading pre silicon Physical Layer Electrical Validation infrastructure development as well as post silicon validation efforts primarily on Cadence's High Speed SERDES Test chips, ie,  activities involving (but not limited to) designing the hardware and software architecture required to test the test chips (be it the test PCBs, controlling FPGA platforms, Labview/python automation for controlling the HW etc), defining test plans for rigorously testing the compliance of the Test chips to the Physical Layer Electrical specifications, implementing these tests as planned, generating high quality test reports based on the test results etc.\n\nWhat we are looking for in potential candidates is listed below. \n\nMinimum Qualifications:\n6-10 years (with Btech) or 4-8 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation\nDeep Physical Layer electrical validation experience on AT LEAST ONE High speed SERDES protocol like PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO etc\nStrong hands on Experience in using lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) etc\n\nPreferred Qualifications:\nExperience managing small teams (at least 2 members and above)\nExperience leading the complete post silicon validation efforts for at least one full project\n1-2 years of experience in FPGA Design, PCB schematic and layout design & Prototyping\nPre-Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring-up & Debug.\nFamiliarity with Verilog RTL coding, FPGA coding, Labview, python, C/C++, TCL\nExperience conducting hiring interviews and mentoring new hires\nCandidates are expected to be passionate about analog and digital electronic circuit design aspects as well as signal processing related aspects.\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Principal Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2024-07-24", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Design-Engineer_R46243", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nBE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.\n8+ years of Design Verification experience with SV/UVM\nStrong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.\nDesign Verification experience verifying complex designs and leading projects from concept to verification closure.\nStrong hands-on UVM and System Verilog coding experience and functional verification environment development is required.\n\nPrior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Design Engineer II", "company": "Cadence", "location": "BANGALORE", "date_posted": "2024-07-17", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Design-Engineer_R45986", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nMinimum Qualifications:\n2-4 years (with Btech) or 1-2 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation\nDeep Physical Layer electrical validation experience on AT LEAST ONE High speed SERDES protocol like PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO etc\nStrong hands on Experience in using lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) etc\nPreferred Qualifications:\nExperience managing small teams (at least 2 members and above)\nExperience leading the complete post silicon validation efforts for at least one full project\n1-2 years of experience in FPGA Design, PCB schematic and layout design & Prototyping\nPre-Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring-up & Debug.\nFamiliarity with Verilog RTL coding, FPGA coding, Labview, python, C/C++, TCL\n\nExperience conducting hiring interviews and mentoring new hires\nBE/BTech/ME/MTech or equivalent\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Electrical Engineer", "company": "Applied Materials", "location": "Bangalore,IND", "date_posted": "2024-05-30", "url": "https://amat.wd1.myworkdayjobs.com/External/job/BangaloreIND/Electrical-Engineer_R2414526", "is_hardware": true, "platform": "workday", "jd_text": "About Applied\nApplied Materials is the leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at atomic levels and on an industrial scale enables customers to transform possibilities into reality. At Applied Materials, our innovations make possible the technology shaping the future.\n\nYour Opportunity\nAs an EE you will be working in highly technical, flexible environment with top level exposure to all cutting-edge technologies and legacy system.  You will have the opportunity to engage in the Product Life Cycle from concept designs to volume manufacturing for the modules/systems enabling to solve the High value problems of our customers. You will be offered unique opportunities and challenges to get interfaced with our customers and suppliers. Applied continues to grow and is the #1 Semiconductor Manufacturing Company in the industry.\n\nKey Responsibilities\nExpert level technical support in the resolution of FPGA design and application issues\nDesign or modify electrical/electronic engineering assemblies, layouts/schematics and/or detailed drawings/specifications of moderate scope under general supervision.\nCreate design and specification documents, test plans and progress reports. \nConduct obsolescence risk assessment for prompt risk mitigation strategy and implementation to ensure product manufacturability and sustenance.\nCoordinate the procurement and assembly of electrical/electronic components/equipment and identify sources of critical parts and subsystems to resolve technical issues.\nParticipate in resolving customer complaints & escalations through root-cause analysis and corrective-preventive actions.\n\nFunctional Knowledge (Required Skills/Experience):\nExtensive knowledge of RTL design language. Hands on experience on design, simulation and testing of FPGA application.\nGood knowledge of electrical design engineering, Digital/Analog/Mixed signals, Power electronics, Controls and Instrumentation.\nGood knowledge of electrical engineering design concepts and applications - components, schematics, electrical system.\nGood understanding on communication interface such as I2C, SPI, USB, Wi-Fi, IoT and Bluetooth, memory device such as SRAM, DDR3+, and high speed communication protocols such as ETHERCAT, ETHERNET, PCIe\nExperience on microcontrollers and microprocessor design.\n\nInterpersonal Skills\nDemonstrate strong written, oral, and interpersonal communication skills.\nExcellent aptitude for multi-tasking and willing to learn.\n\nQualifications\nBachelor's Degree in Electrical Engineering / Electronics & Communication\n\nQualifications\n\nEducation:\nBachelor's Degree\nSkills:\n\nCertifications:\n\nLanguages:\n\nYears of Experience:\n4 - 7 Years\nWork Experience:\n\nAdditional Information\n\nTime Type:\nFull time\nEmployee Type:\nAssignee / Regular\nTravel:\nYes, 10% of the Time\nRelocation Eligible:\nYes\n\nApplied Materials is an Equal Opportunity Employer committed to diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.", "jd_status": "stored"}, {"title": "Senior DFT Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2024-05-20", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Senior-DFT-Engineer_R46228", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nWe are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches.\n\nMust be able to obtain and maintain a Department of Defense classified clearance\nPrior 5-15 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)\nShould possess intimate knowledge of DFT insertion flows\nBasic scan chain insertion using synthesis or other software tools\nExperience in compression scan insertion, LBIST and other scan technologies\nIntimate knowledge of memory build-in self-test (MBIST)\nExpertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals\nDebug and Analysis of failures to improve fault coverage\nVerification of ATPG testbenches and debugging root cause of simulation mis-compares\nWorking knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687\nKnowledge of timing analysis and equivalency checks would be added bonus\nAbility to work in collaborative team environment\nPrior experience with Cadence tools and flows is highly desirable\nShould be able to finish DFT tasks independently\nStrong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems\nAbility to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers\nSelf-driven and committed individual who can work in a fast-paced project environment\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Lead Solutions Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2024-05-01", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Solutions-Engineer_R46508", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nUnderstand/review Design specification and develop verification strategy/Test plan/coverage plan. Development of constrained random verification environments and verification components. Writing tests/sequences/functional coverage/assertions to meet verification goals. Developing c-based test cases for SOC verification.\n\nRequired experience\nStrong background on functional verification fundamentals, environment planning, test plan generation, environment development\nSystem Verilog experience and experience with UVM based functional verification environment development is required.\nGood knowledge of verilog/vhdl/C/C++/Perl/Python.\nExpertise in AMBA protocols. (AXI/AHB/APB).\nGood knowledge of at least one of the USB/PCIE/Ethernet/DDR/LPDDR or similar protocols\nGood handle on using one or more version control software\nGood handle on using one or more load sharing software\n\nDesirable skills and experience\nPrior experience with Cadence tools and flows is highly desirable.\nFamiliarity with ARM/CPU architectures is a plus.\nExperience in developing c-based test cases for SOC verification\nSome experience with assembly language programming\nGood knowledge of some of the protocols like UART, I2C, SPI, JTAG\nEmbedded C code development and debug\nFormal Verification experience\n\nStrong vocabulary, communication, organizational, planning, and presentation skills are essential. Ability to work independently and productively with high quality output and results in a fast paced and dynamic environment. Ability and desire to learn new methodologies, languages, protocols etc. Must be open to constant personal development and growth to meet the evolving demands of the semiconductor industry. Self-motivated and willing take up additional responsibilities to contribute to team’s success.\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Lead Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2024-04-25", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Design-Engineer_R45755", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nBE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.\n•    4+ years of Design Verification experience with SV/UVM\n•    Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.\n•    Design Verification experience verifying complex designs and leading projects from concept to verification closure.\n•    Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.\n•    Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.\n \nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Principal Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2024-03-21", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Design-Engineer_R45744-1", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nPosition RequirementsM.S. or BTech Electrical/Computer/Electronics Engineering (or similar degree)\nExperience - 7+ years\nsound knowledge of DDR4/5, LPDDR4/5 IP.\nHands on design/verification experience on DDR protocol\nExposure to DDR Integration and Verification at SOC Level\nExposure to Silicon Bring-up/Testing for DDR.\nHands on design/verification experience on AMBA based protocols like AXI, AHB, APB\nExperience on cadence tools\nExposure to Lint/CDC, Synthesis, Static Timing Analysis review\nExposure to all major IC implementation, design, and verification tools.\nWilling to travel to customer sites worldwide.\nWorking with global (US, west coast, and east coast) teams, which work in different time-zones.\n\nPrimary Responsibilities:Responsible for supporting integration / customization / post silicon bring up of CDNS DDR IP subsystems.\nAnalyze and resolve complex subsystem application or implementation issues and provide professional guidance to customers.\nSupport DDR Controller and PHY SOC integration reviews, and integration questions.\nPerform RTL and gate level simulations to verify functionality.\nAssist customers with gate level simulations and timing closure.\nParticipate in development of CDNS documentations and checklists for customers.\nSupport post silicon bring-up and deployment activities by our customers.\nEnhance customer experience by providing prompt updates to customers.\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Principal DFT Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2024-02-23", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-DFT-Design-Engineer_R44711-1", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\n·     This role requires close interaction with multiple cross functional teams across geographies to align on project receivables/deliverables.\n·     Mentoring junior engineers and driving innovation/automation.\n·     BE/B.Tech/M.E/M.Tech with 7+ years of relevant work experience and strong understanding of DFT concepts and good communication skills.\n·     Strong hands-on experience using industry standard EDA Tools.\n·     Experience with logic simulators from one or more EDA vendors.\n·     Experience on industry standard ATPG tools like Cadence Modus.\n·     Experience with RTL lint tools like Jasper.\n·     Experience in scan insertion, coverage analysis and debugging skills on faults coverage enhancement is required.\n·     Programming in Perl/Tcl/Python or other scripting languages is a plus.\n·     Experience in post silicon validation, ATE debug and support is desired.\n·     Exposure to RTL2GDS flow and tasks such as synthesis and scan insertion, STA and IR drop.\n·     Good understanding of Logic design, RTL implementation & verification, logic synthesis, Logic Equivalent Checking & Static Timing Analysis are plus.\n·     Participate in driving new DFT methodology and solutions to improve quality, reliability and in-system test and debug capability.\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Lead Product Engineer - Design Verification (MM/VIP)", "company": "Cadence", "location": "AHMEDABAD", "date_posted": "2024-01-12", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/AHMEDABAD/Lead-Product-Engineer---Design-Verification--MM-VIP-_R45116", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Title: Lead Product Engineer\nLocation: Ahmedabad\n\nCadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.\n\nThe Cadence Advantage\nThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.\nCadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.\nThe unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success\nMultiple avenues of learning and development available for employees to explore as per their specific requirement and interests\nYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.\n\nJob Summary\nDrives development of products and technologies and has material responsibility for the success of that product/technology. MM VIP PE is expected to become an expert in the Memory domain of Verification IP family – protocol and product-wise. The memory domain has many protocols such as SDRAM protocols (DDR5), SGRAM protocols (GDDR6), Memory Controller and PHY protocols (DFI), and others. The Cadence VIP Portfolio includes Memory Models that enable advanced verification of these protocols. The PE’s main role is to help accelerate VIP Portfolio adoption at Cadence’s top tier customers by supporting pre-sales technical activities. To ensure that, one must have strong verification expertise and understand customer design and verification flows. As a MM VIP and protocol expert, PE drives product knowledge transfer across our field engineers and customers, providing training and developing collaterals. The PE will also need to translate high-level requirements from customers into a technical spec and drive the product definition that fits the customer needs. The PE is expected to work independently and collaborate with other team members (R&D, Marketing, Customer Support, Field Teams) to ensure all dimensions of the product are aligned. This role requires approximately 20% travel and cross-site collaboration over multiple geographies (Asia Pacific, Europe, US-East, US-South and US-West).\n\nJob Responsibilities\nLeads projects with high resource, risk and/or complexity\nDevelops and leads large and multiple cross-functional and cross-organizational programs, initiatives, and activities with high resource requirements, risk and/or complexity\nContinually evaluates technology effectiveness/data interoperability of complex systems\nManages issue resolution with vendors on tech/product quality and functionality and influences vendor roadmap and direction of products\nCommunicates highly complex ideas, anticipates potential objections and persuades others, often at senior levels, to adopt a different point of view.\n\nExperience and Technical Skills required\nAt least 4 – 8 years of experience with Design and Verification\nExperience with Developing Verification environments using System Verilog\nWorking knowledge and experience with the UVM methodology\nGood experience on solving complex problems where analysis of situations or data requires an in-depth evaluation of various factors.\nExercises judgment within broadly defined practices and policies in selecting methods, techniques, and evaluation criteria for obtaining results.\nExcellent problem-solving and debugging skills\nFamiliarity with Memory protocols is a must.\nKnowledge of the DFI protocol is a plus.\n\nQualifications\nBTech/BE/MTech/ME or equivalent with Electrical, Electronics & Comm or Computer Science Engineering\n\nBehavioral skills required\nMust possess strong written, verbal and presentation skills\nAbility to establish a close working relationship with both customer peers and management\nExplore what’s possible to get the job done, including creative use of unconventional solutions\nWork effectively across functions and geographies\nPush to raise the bar while always operating with integrity\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Lead Application Engineer - GCS  ( Physical Design )", "company": "Cadence", "location": "BANGALORE", "date_posted": "2024-01-04", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Application-Engineer---GCS----Physical-Design--_R45058", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nGCS AE Job Description Document\n\nJob Title: Lead Application Engineer - GCS\nLocation: Bangalore / Noida\nCadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.\n\nThe Cadence Advantage\n\nThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.\nCadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.\nThe unique “One Cadence – One Team” culture builds and fosters diversity, equity and inclusion to maximize our ability to innovate, drive growth, and win with our customers. Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. \nMultiple avenues of learning and development available for employees to explore as per their specific requirement and interests\nYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.\n\nJob Summary\n\nAs a member of the GCS Organization for the DSG (Digital & Sign-off Group), you will partner with world-wide Cadence customers to provide post sales technical consultation for digital & sign-off domain products for implementing cutting-edge designs. This involves working closely with the customers to understand and debug complex issues enabling them to proceed further with design cycle phases, help them leverage the latest tool capabilities, and guide them with implementation of software in their design methodologies. You will have an opportunity to acquire both breadth and depth of technical knowledge, get wide exposure to the latest design practices in industry and demonstrate expertise by authoring high impact knowledge content.\nThis role also provides opportunity to participate in the evolution of key technology solutions to the most pressing design problems. In this role, you will have the opportunity to work with product teams to identify and prioritize the product improvement initiatives with your timely feedback and observations.\nThis an excellent opportunity to work in a supportive, flexible and friendly work environment that GCS offers, where we are vested in each other’s success, and are passionate about technology and innovation.\n\nJob Responsibilities\n\nProvide technical consultation on the usage of digital & sign-off toolset to Cadence customers with high level of satisfaction\nProvides a proactive and creative approach to resolving problems using specialized domain knowledge and advanced business experience; obtains feedback on issues/suggestions and brings back to R&D\nGuides creation and publishing of high quality and impactful knowledge content in DSG domain\nProvides effective technical leadership and mentoring for a small team working at Cadence or customer facilities to deliver quality results according to schedule requirements\nSolves highly complex problems and is able to identify viable and often innovative options, and uses analytical skills and judgment to recommend an appropriate solution\n\nQualifications\n\nBachelor’s Degree in; Electrical / Electronics / Electronics and Communication / VLSI Engineering with 7 years related experience\nOR Masters 4 years of related experience\nOR PhD 4 years of related experience\n\nExperience and Technical Skills required\n\n> 4 years of experience in Physical design and sign-off tools and/or design methodologies/flows\nSolid understanding of digital & sign-off tool set in the context of multiple flows; expert level skills on multiple tools; ability to analyze customer's environment and evaluate appropriate solutions; able to architect flows; anticipates technical issues and develops creative solutions before they become a problem\nMust have excellent debugging skills and ability to separate out the critical issues from trivial ones.\n\nBehavioral skills required\n\nMust possess strong written, verbal and presentation skills\nAbility to establish a close working relationship with both customer peers and management\nExplore what’s possible to get the job done, including creative use of unconventional solutions\nWork effectively across functions and geographies\nPush to raise the bar while always operating with integrity\n\nRegards\nMadhu\nkmadhup@cadence.com\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Principal Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2023-12-12", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Design-Engineer_R44714-1", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nResponsibilities:\nContribute to AMS design for High-speed Memory PHYs.\nResponsible for major sub-system of Memory PHY like Tx, Rx or Clocking\nUnderstand system specification, define design micro-architecture, and define the design hierarchy.\nParticipate in technical discussions with cross function teams\nFully accountable for AMS design quality and schedule\nOwn the design progress, identify potential risks, and mitigation plan for sub-system\nMentor and provide technical guidance to team working in the projects.\nContribute to AMS methodology improvements to boost efficiency and productivity.\n\nRequirements/Qualifications:\nBachelor's/Master's degree in Electronics/Electrical Engineering. Specialization in VLSI/Micro-electronics is preferred.\n7+ years of Analog Mixed Signal design experience\nSound knowledge on AMS design techniques and circuit architecture\nStrong experience on high-speed circuits like Tx, Rx, CTLE, Amplifiers, Samplers\nExposure to Serdes, DDR, HBM technologies\nShould have knowledge on all aspects of Mixed Signal IP design.\nExperience on working with AMS verification and logic designers to achieve AMS circuit requirements\nHands-on experience on block, IP and system level design.\nShould have involved in designing multiple IPs from Specification to Productization\nExperienced in lab debugs on AMS IPs\nExcellent communication and interpersonal skills, demonstrate teamwork and collaboration skills.   \nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Design Verification Engineer", "company": "MediaTek", "location": "Bangalore", "date_posted": "2023-11-02T16:00:00+00:00", "url": "https://careers.mediatek.com/en/jobs/MTB120231103000", "is_hardware": true, "platform": "mediatek", "jd_text": "Key Qualifications\n•\tPreferably BE/B.Tech/ME/M.Tech in EEE/ECE/CSE with 5-12 years of relevant industry experience.\n•\tShould have experience in verification methodology.\n•\tArchitecting and development of testbench, test-bench components for ISA features, clock/reset/power features of processor.\n•\tStrong assembly and CPU (x86/ARM/RISC-V) architecture knowledge.\n•\tStrong in C, C++, Verilog, and scripting (Perl, Python) languages.\n•\tAbility to work independently and across geographies", "jd_status": "stored"}, {"title": "Lead Design Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2023-09-05", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Design-Engineer_R43933-1", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nCadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.\n\nThe Cadence Advantage\nThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.\nCadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.\nThe unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success\nMultiple avenues of learning and development available for employees to explore as per their specific requirement and interests\nYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.\n\nJob responsibilities:\n\nThe role requires working with the existing functional verification environment, addition of new features into the verification environment or creating completely new verification environment from scratch and ensuring various customer configurations are clean meeting required DV metrics. Sometimes there may also be need to support customers in case of any issues with design.\nParticipate in Technical alignment with verification expert in Defining verification strategy, architecting verification environment. Also interface with other domains such as RTL , Physical design, Analog design and modelling teams. Technically small team/project depending on the project requriements.\nContribute towards Defining, developing and deploying new functional verification methodologies.\nThe engineers should have strong background in functional verification fundamentals, verification environment planning & development, test plan creation.\nPrior Digital verification experience in some of the serial bus multiprotocol PHY IP’s (such as SerDes, USB/DPHY,UCIe) is expected.\nOther verification domain skills:\n-Strong expertise in Verilog, HVL( SV, e) with UVM methodology\n-Experience in assertions development/closure, constraint randomization, functional coverage, code coverage.\n-Strong RTL and GLS debug skills.\nExpertise in more than two of following skills is desirable and added plus:\n-Power-aware RTL set-up, simulation and debug\n-Formal verification.\n-Gate-level simulations.\n-Good to have (not must have): Some experience or understanding and usage of Analog models. Basic awareness of mixed-mode simulations with Analog/digital,-Some exposure to Automotive IP verification (fault injection), emulation exposure though not mandatory but good to have.\nQualification :\n5+ years experience with B.E/B.Tech or M.E/M.Tech\n\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Lead FrontEnd Methodology Engineer", "company": "Cadence", "location": "BANGALORE", "date_posted": "2022-09-01", "url": "https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-DDR-Verification-Engineer_R39669", "is_hardware": true, "platform": "workday", "jd_text": "At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nThe candidate will have responsibilities to maintain/upgrade infrastructure/automation for RTL development and design-verification teams at multiple locations using multiple server farms, some in the Amazon and IBM clouds and some on-premise. The candidate will also have responsibilities in managing/monitoring regression trends, automating error/defect reporting, and supporting users in various server farms.\n\nThe candidate will have responsibilities to maintain/upgrade infrastructure/automation for RTL development and design-verification teams at multiple locations using multiple server farms, some in the Amazon and IBM clouds and some on-premise. The candidate will also have responsibilities in managing/monitoring regression trends, automating error/defect reporting, and supporting users in various server farms.\n\nWe’re looking for a candidate who has the following skillsets:\nExtensive knowledge of Perl and Python\nKnowledge of dependency-checking via make, SCons\nLSF or other batch-queuing system (e.g. Grid, PBS, Open Lava), and script integration\nUsing REST API (e.g. Jenkins, Jira) from Perl, Python\nMigrating scripts, script-libraries to different Linux OS releases\nKnowledge of SQL, relational database engines like MariaDB or PSQL, and integration with Perl/Python\nKnowledge of web technologies: Basic Apache setup, PHP, Javascript/Jquery, RSS automation\n\nThese skillsets and knowledge would also be desirable:\nBS/MS - Electrical / Computer Engineering.\nAt least 7 years of of relevant experience.\nUpdating/debugging TCL code embedded in a variety of tools, such as simulator, waveform-viewer, formal verification, in-house interpreter, etc.\nKnowledge of Verilog, SystemVerilog testbenches; some familiarity with methodologies like OVM or UVM; incorporate DPI or PLI models\nSome IT knowledge: NFS, memory/CPU profiling, NIS/DNS/LDAP, SMTP, syslog, cron, etc\nJenkins install/configuration/management\nModule-files and modulecmd to manage tools and tool-versions\nCloud deployment/maintenance: Amazon Web Services, MS Azure, IBM Cloud\nExperience with revision control like git or GitHub\nThe position is based in Austin/San Jose/Bangalore (India)\nWe’re doing work that matters. Help us solve what others can’t.", "jd_status": "stored"}, {"title": "Principal Engineer, Agentic AI (CAD/EDA)Bengaluru, IndiaCategory:EngineeringPosted:08/17/2026Job ID:18373", "company": "Synopsys", "location": "Bengaluru, India", "date_posted": null, "url": "https://careers.synopsys.com/job/bengaluru/principal-engineer-agentic-ai-cad-eda/44408/99402446848", "is_hardware": true, "platform": "talentbrew", "jd_text": null, "jd_status": "stored"}]}